From 6b4bf2100ec728e057c9b7f76412b37f7a53241b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 21 Oct 2025 10:39:54 +0530 Subject: [PATCH 0001/1330] UPSTREAM: dt-bindings: usb: qcom,snps-dwc3: Add the SM8750 compatible Add qcom,sm8750-dwc3 compatible to flattened implementation binding. Link: https://lore.kernel.org/all/20251021050954.3462613-1-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Konrad Dybcio Signed-off-by: Krishna Kurapati Reviewed-by: Krzysztof Kozlowski From 11d81cfa7be8c627ece136c138fa31c55787d1dc Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Tue, 21 Oct 2025 23:15:54 -0700 Subject: [PATCH 0002/1330] FROMLIST: dt-bindings: arm-smmu: Add compatible for Kaanapali and Glymur SoCs Qualcomm Kaanapali and Glymur SoCs include apps smmu that implements arm,mmu-500, which is used to translate device-visible virtual addresses to physical addresses. Add compatible for these items. Co-developed-by: Pankaj Patil Signed-off-by: Pankaj Patil Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yijie Yang Link: https://lore.kernel.org/all/20251021-b4-knp-smmu-v2-1-88774e6d2def@oss.qualcomm.com/ From 7654fdf03c1edac22626038b7f1d7df2da562c9c Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Wed, 22 Oct 2025 00:28:43 -0700 Subject: [PATCH 0003/1330] FROMLIST: dt-bindings: firmware: qcom,scm: Document SCM on Kaanapali SOC Document scm compatible for the Qualcomm Kaanapali SoC. Reviewed-by: Eugen Hristev Signed-off-by: Jingyi Wang Acked-by: Rob Herring (Arm) Signed-off-by: Yijie Yang Link: https://lore.kernel.org/all/20251022-knp-soc-binding-v2-3-3cd3f390f3e2@oss.qualcomm.com/ From 154937c5a5b194be0d57ae869e0a388c9bf7c22c Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Thu, 18 Sep 2025 14:57:01 +0530 Subject: [PATCH 0004/1330] FROMGIT: dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & PMCX0102 Add rpmh-regulator driver compatibles strings for below PMICs: - PMH0101 - PMH0104 - PMH0110 - PMCX0102 Also add the supply name properties for the regulators present on these PMICs. Co-developed-by: Jishnu Prakash Signed-off-by: Jishnu Prakash Signed-off-by: Kamal Wadhwa Link: https://patch.msgid.link/20250918-glymur-rpmh-regulator-driver-v3-1-184c09678be3@oss.qualcomm.com Signed-off-by: Mark Brown Signed-off-by: Yijie Yang From a38dc4b031790fff58713192a1ed1138c7c612e0 Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Thu, 18 Sep 2025 14:57:02 +0530 Subject: [PATCH 0005/1330] FROMGIT: dt-bindings: rpmh-regulator: Update pmic-id DT prop info for new CMD-DB Currently, CMD-DB names for RPMH regulators follow this format: `^(smps|ldo|bob|vs)[a-n][1-9][0-9]?$` Here, the `[a-n]` value is read from the `pmic-id` DT property, which is unique to each PMIC present on the board. Note that in this older CMD-DB name format the SPMI bus on which a particular PMIC regulator exists was not apparent from its CMD-DB name. New targets like Glymur, where we have multiple SPMI buses, overcome this limitation by following a new CMD-DB name format: `^(L|S|B)[1-9][0-9]?[A-N]_E[0-3]$` Here `[A-N]_E[0-3]` part will now be read from the `pmic-id` DT prop and it includes the SPMI bus id `[0-3]` as well. However, the PMIC ID part `[A-N]` of the CMD-DB name is now unique only to the SPMI bus that the PMIC regulator is present on. which means `L1B_E0` and `L1B_E1` are both possible CMD-DB names for two different regulator LDOs present on two different SPMI buses (bus id 0 and 1) on the same board. Note that since the new `pmic-id` DT property is a combo of PMIC ID and SPMI bus ID, so its still unique to each PMIC present on the board. Update the `pmic-id` property pattern information to reflect this change in the driver handling to support this new CMD-DB naming format while maintaining backward compatiblilty with old CMD-DB naming format which is still supported for older/existing targets. Signed-off-by: Kamal Wadhwa Link: https://patch.msgid.link/20250918-glymur-rpmh-regulator-driver-v3-2-184c09678be3@oss.qualcomm.com Signed-off-by: Mark Brown Signed-off-by: Yijie Yang From c2853d1a493633ed6d9482d6145594c26174ea49 Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Thu, 18 Sep 2025 14:57:04 +0530 Subject: [PATCH 0006/1330] FROMGIT: regulator: rpmh-regulator: Add RPMH regulator support for Glymur Add support for PMH0101/PMCX0102/PMH0110/PMH0104 PMIC voltage regulators which are present on Glymur boards. Introduce new LDOs & SMPSs under them (PMIC5 subtype 530 for both). For these new LDOs support a new optimum power mode(OPM). In this mode LDO will automatically switch between high power mode (HPM) and low power mode (LPM) based on the real-time LDO load current. Its operation is analogous to SMPS AUTO mode. Reviewed-by: Dmitry Baryshkov Co-developed-by: Jishnu Prakash Signed-off-by: Jishnu Prakash Signed-off-by: Kamal Wadhwa Link: https://patch.msgid.link/20250918-glymur-rpmh-regulator-driver-v3-4-184c09678be3@oss.qualcomm.com Signed-off-by: Mark Brown Signed-off-by: Yijie Yang From dff96835039e7ca30c38bb37900607e19b8c5479 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 24 Sep 2025 16:30:48 -0700 Subject: [PATCH 0007/1330] FROMGIT: regulator: rpmh-regulator: Add RPMH regulator support for PMR735D Add support for PMR735D PMIC voltage regulators which are present on Kaanapali boards. Signed-off-by: Jishnu Prakash Signed-off-by: Jingyi Wang Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yijie Yang Link: https://lore.kernel.org/all/20250924-knp-regulator-v1-2-d9cde9a98a44@oss.qualcomm.com/ From 6f962827cd186f5d6148c1f95745c4739a702445 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 24 Sep 2025 16:30:47 -0700 Subject: [PATCH 0008/1330] FROMGIT: regulator: dt-bindings: qcom,rpmh: Add support for PMR735D Add support for PMR735D PMIC used on Kaanapali boards. Signed-off-by: Jishnu Prakash Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yijie Yang Link: https://lore.kernel.org/all/20250924-knp-regulator-v1-1-d9cde9a98a44@oss.qualcomm.com/ From 6a3cbb92da9cfc366188aaa58efe7af2754ceb57 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 18 Sep 2025 19:47:38 +0530 Subject: [PATCH 0009/1330] FROMLIST: dt-bindings: firmware: qcom,scm: Document Glymur scm Document the SCM compatible for Qualcomm Glymur SoC. Secure Channel Manager(SCM) is used to communicate with secure firmware. Link: https://lore.kernel.org/all/20250918141738.2524269-1-pankaj.patil@oss.qualcomm.com/ Signed-off-by: Pankaj Patil Acked-by: Rob Herring (Arm) Signed-off-by: Sibi Sankar From 339a113463a746050cc9d2025412e54138ddc1cb Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Wed, 15 Oct 2025 16:22:07 +0530 Subject: [PATCH 0010/1330] FROMLIST: dt-bindings: usb: qcom,dwc3: Correct the SM8750 compatible SM8750 does not require an XO clock in the dt as it is the parent of the TCSR refclk_src, so move the compatible to a section where the XO clock is not required. Acked-by: Krzysztof Kozlowski Signed-off-by: Melody Olvera Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/all/20251015105207.2819689-1-krishna.kurapati@oss.qualcomm.com/#r Signed-off-by: Yash Gupta --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index a7f58114c02e8..2e2d4562fb03c 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -227,6 +227,7 @@ allOf: - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - qcom,sm6350-dwc3 + - qcom,sm8750-dwc3 then: properties: clocks: @@ -366,7 +367,6 @@ allOf: - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 - - qcom,sm8750-dwc3 then: properties: clocks: From 1c836ff864cf7b63077e90a82b2b7f0a7e0001c4 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:33:57 +0100 Subject: [PATCH 0011/1330] FROMLIST: dmaengine: Add DMA_PREP_LOCK/DMA_PREP_UNLOCK flags Some DMA engines may be accessed from linux and the TrustZone simultaneously. In order to allow synchronization, add lock and unlock flags for the command descriptor that allow the caller to request the controller to be locked for the duration of the transaction in an implementation-dependent way. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-1-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- Documentation/driver-api/dmaengine/provider.rst | 9 +++++++++ include/linux/dmaengine.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index f4ed98f701c91..56dadef74eb37 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -633,6 +633,15 @@ DMA_CTRL_REUSE - This flag is only supported if the channel reports the DMA_LOAD_EOT capability. +- DMA_PREP_LOCK + + - If set, the DMA controller will be locked for the duration of the current + transaction. + +- DMA_PREP_UNLOCK + + - If set, DMA will release he controller lock. + General Design Notes ==================== diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 99efe2b9b4ea9..c02be4bc8ac4c 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -200,6 +200,10 @@ struct dma_vec { * transaction is marked with DMA_PREP_REPEAT will cause the new transaction * to never be processed and stay in the issued queue forever. The flag is * ignored if the previous transaction is not a repeated transaction. + * @DMA_PREP_LOCK: tell the driver that there is a lock bit set on command + * descriptor. + * @DMA_PREP_UNLOCK: tell the driver that there is a un-lock bit set on command + * descriptor. */ enum dma_ctrl_flags { DMA_PREP_INTERRUPT = (1 << 0), @@ -212,6 +216,8 @@ enum dma_ctrl_flags { DMA_PREP_CMD = (1 << 7), DMA_PREP_REPEAT = (1 << 8), DMA_PREP_LOAD_EOT = (1 << 9), + DMA_PREP_LOCK = (1 << 10), + DMA_PREP_UNLOCK = (1 << 11), }; /** From 3145c91bc4225b5afb8e13d7cb40a8f1a5adb28f Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:33:58 +0100 Subject: [PATCH 0012/1330] FROMLIST: dmaengine: qcom: bam_dma: Extend the driver's device match data In preparation for supporting the pipe locking feature flag, extend the amount of information we can carry in device match data: create a separate structure and make the register information one of its fields. This way, in subsequent patches, it will be just a matter of adding a new field to the device data. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-2-ecddca23ca26@linaro.org/ Reviewed-by: Dmitry Baryshkov Signed-off-by: Bartosz Golaszewski --- drivers/dma/qcom/bam_dma.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 19116295f8325..e4e3fdea86429 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -112,6 +112,10 @@ struct reg_offset_data { unsigned int pipe_mult, evnt_mult, ee_mult; }; +struct bam_device_data { + const struct reg_offset_data *reg_info; +}; + static const struct reg_offset_data bam_v1_3_reg_info[] = { [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 }, @@ -141,6 +145,10 @@ static const struct reg_offset_data bam_v1_3_reg_info[] = { [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 }, }; +static const struct bam_device_data bam_v1_3_data = { + .reg_info = bam_v1_3_reg_info, +}; + static const struct reg_offset_data bam_v1_4_reg_info[] = { [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, @@ -170,6 +178,10 @@ static const struct reg_offset_data bam_v1_4_reg_info[] = { [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 }, }; +static const struct bam_device_data bam_v1_4_data = { + .reg_info = bam_v1_4_reg_info, +}; + static const struct reg_offset_data bam_v1_7_reg_info[] = { [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 }, @@ -199,6 +211,10 @@ static const struct reg_offset_data bam_v1_7_reg_info[] = { [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 }, }; +static const struct bam_device_data bam_v1_7_data = { + .reg_info = bam_v1_7_reg_info, +}; + /* BAM CTRL */ #define BAM_SW_RST BIT(0) #define BAM_EN BIT(1) @@ -392,7 +408,7 @@ struct bam_device { bool powered_remotely; u32 active_channels; - const struct reg_offset_data *layout; + const struct bam_device_data *dev_data; struct clk *bamclk; int irq; @@ -410,7 +426,7 @@ struct bam_device { static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe, enum bam_reg reg) { - const struct reg_offset_data r = bdev->layout[reg]; + const struct reg_offset_data r = bdev->dev_data->reg_info[reg]; return bdev->regs + r.base_offset + r.pipe_mult * pipe + @@ -1205,9 +1221,9 @@ static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan, } static const struct of_device_id bam_of_match[] = { - { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info }, - { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info }, - { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info }, + { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_data }, + { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_data }, + { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_data }, {} }; @@ -1231,7 +1247,7 @@ static int bam_dma_probe(struct platform_device *pdev) return -ENODEV; } - bdev->layout = match->data; + bdev->dev_data = match->data; bdev->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(bdev->regs)) From 0c42a4b89dc56e0781e1b0662e8ab01e63ec96d1 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:33:59 +0100 Subject: [PATCH 0013/1330] FROMLIST: dmaengine: qcom: bam_dma: Add bam_pipe_lock flag support Extend the device match data with a flag indicating whether the IP supports the BAM lock/unlock feature. Set it to true on BAM IP versions 1.4.0 and above. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-3-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/dma/qcom/bam_dma.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index e4e3fdea86429..04728880df3a8 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -59,6 +59,8 @@ struct bam_desc_hw { #define DESC_FLAG_EOB BIT(13) #define DESC_FLAG_NWD BIT(12) #define DESC_FLAG_CMD BIT(11) +#define DESC_FLAG_LOCK BIT(10) +#define DESC_FLAG_UNLOCK BIT(9) struct bam_async_desc { struct virt_dma_desc vd; @@ -114,6 +116,7 @@ struct reg_offset_data { struct bam_device_data { const struct reg_offset_data *reg_info; + bool bam_pipe_lock; }; static const struct reg_offset_data bam_v1_3_reg_info[] = { @@ -180,6 +183,7 @@ static const struct reg_offset_data bam_v1_4_reg_info[] = { static const struct bam_device_data bam_v1_4_data = { .reg_info = bam_v1_4_reg_info, + .bam_pipe_lock = true, }; static const struct reg_offset_data bam_v1_7_reg_info[] = { @@ -213,6 +217,7 @@ static const struct reg_offset_data bam_v1_7_reg_info[] = { static const struct bam_device_data bam_v1_7_data = { .reg_info = bam_v1_7_reg_info, + .bam_pipe_lock = true, }; /* BAM CTRL */ @@ -387,6 +392,9 @@ struct bam_chan { struct list_head desc_list; struct list_head node; + + /* Is the BAM currently locked? */ + bool locked; }; static inline struct bam_chan *to_bam_chan(struct dma_chan *common) @@ -665,6 +673,7 @@ static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, { struct bam_chan *bchan = to_bam_chan(chan); struct bam_device *bdev = bchan->bdev; + const struct bam_device_data *bdata = bdev->dev_data; struct bam_async_desc *async_desc; struct scatterlist *sg; u32 i; @@ -699,9 +708,34 @@ static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, unsigned int curr_offset = 0; do { - if (flags & DMA_PREP_CMD) + if (flags & DMA_PREP_CMD) { + if (!bdata->bam_pipe_lock && + (flags & (DMA_PREP_LOCK | DMA_PREP_UNLOCK))) { + dev_err(bdev->dev, "Device doesn't support BAM locking\n"); + return NULL; + } + desc->flags |= cpu_to_le16(DESC_FLAG_CMD); + if (bdata->bam_pipe_lock && (flags & DMA_PREP_LOCK)) { + if (bchan->locked) { + dev_err(bdev->dev, "BAM already locked\n"); + return NULL; + } + + desc->flags |= cpu_to_le16(DESC_FLAG_LOCK); + bchan->locked = true; + } else if (bdata->bam_pipe_lock && (flags & DMA_PREP_UNLOCK)) { + if (!bchan->locked) { + dev_err(bdev->dev, "BAM is not locked\n"); + return NULL; + } + + desc->flags |= cpu_to_le16(DESC_FLAG_UNLOCK); + bchan->locked = false; + } + } + desc->addr = cpu_to_le32(sg_dma_address(sg) + curr_offset); From d22adf652c603e51f49c8d0988490d7a53e3e4e9 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:34:00 +0100 Subject: [PATCH 0014/1330] FROMLIST: crypto: qce - Include algapi.h in the core.h header The header defines a struct embedding struct crypto_queue whose size needs to be known and which is defined in crypto/algapi.h. Move the inclusion from core.c to core.h. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-4-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/core.c | 1 - drivers/crypto/qce/core.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index b966f3365b7de..65205100c3df9 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include "core.h" diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index eb6fa7a8b64a8..f092ce2d3b04a 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -8,6 +8,7 @@ #include #include +#include #include "dma.h" From f2eea61ce36a8304cb71ee9789be05b1251ed5ab Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:34:01 +0100 Subject: [PATCH 0015/1330] FROMLIST: crypto: qce - Remove unused ignore_buf It's unclear what the purpose of this field is. It has been here since the initial commit but without any explanation. The driver works fine without it. We still keep allocating more space in the result buffer, we just don't need to store its address. While at it: move the QCE_IGNORE_BUF_SZ definition into dma.c as it's not used outside of this compilation unit. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-5-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/dma.c | 4 ++-- drivers/crypto/qce/dma.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 68cafd4741ad3..08bf3e8ec1243 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -9,6 +9,8 @@ #include "dma.h" +#define QCE_IGNORE_BUF_SZ (2 * QCE_BAM_BURST_SIZE) + static void qce_dma_release(void *data) { struct qce_dma_data *dma = data; @@ -41,8 +43,6 @@ int devm_qce_dma_request(struct device *dev, struct qce_dma_data *dma) goto error_nomem; } - dma->ignore_buf = dma->result_buf + QCE_RESULT_BUF_SZ; - return devm_add_action_or_reset(dev, qce_dma_release, dma); error_nomem: diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 31629185000e1..fc337c435cd14 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -23,7 +23,6 @@ struct qce_result_dump { u32 status2; }; -#define QCE_IGNORE_BUF_SZ (2 * QCE_BAM_BURST_SIZE) #define QCE_RESULT_BUF_SZ \ ALIGN(sizeof(struct qce_result_dump), QCE_BAM_BURST_SIZE) @@ -31,7 +30,6 @@ struct qce_dma_data { struct dma_chan *txchan; struct dma_chan *rxchan; struct qce_result_dump *result_buf; - void *ignore_buf; }; int devm_qce_dma_request(struct device *dev, struct qce_dma_data *dma); From a1cf928a921a0fbbeae793e8445cca584893cbaf Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:34:02 +0100 Subject: [PATCH 0016/1330] FROMLIST: crypto: qce - Simplify arguments of devm_qce_dma_request() This function can extract all the information it needs from struct qce_device alone so simplify its arguments. This is done in preparation for adding support for register I/O over DMA which will require accessing even more fields from struct qce_device. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-6-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/core.c | 2 +- drivers/crypto/qce/dma.c | 5 ++++- drivers/crypto/qce/dma.h | 4 +++- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 65205100c3df9..8b7bcd0c420c4 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -226,7 +226,7 @@ static int qce_crypto_probe(struct platform_device *pdev) if (ret) return ret; - ret = devm_qce_dma_request(qce->dev, &qce->dma); + ret = devm_qce_dma_request(qce); if (ret) return ret; diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 08bf3e8ec1243..c29b0abe94453 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -7,6 +7,7 @@ #include #include +#include "core.h" #include "dma.h" #define QCE_IGNORE_BUF_SZ (2 * QCE_BAM_BURST_SIZE) @@ -20,8 +21,10 @@ static void qce_dma_release(void *data) kfree(dma->result_buf); } -int devm_qce_dma_request(struct device *dev, struct qce_dma_data *dma) +int devm_qce_dma_request(struct qce_device *qce) { + struct qce_dma_data *dma = &qce->dma; + struct device *dev = qce->dev; int ret; dma->txchan = dma_request_chan(dev, "tx"); diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index fc337c435cd14..483789d9fa98e 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -8,6 +8,8 @@ #include +struct qce_device; + /* maximum data transfer block size between BAM and CE */ #define QCE_BAM_BURST_SIZE 64 @@ -32,7 +34,7 @@ struct qce_dma_data { struct qce_result_dump *result_buf; }; -int devm_qce_dma_request(struct device *dev, struct qce_dma_data *dma); +int devm_qce_dma_request(struct qce_device *qce); int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *sg_in, int in_ents, struct scatterlist *sg_out, int out_ents, dma_async_tx_callback cb, void *cb_param); From 78f37f3d78ba6910978a5b418615c3fc0f9bfd30 Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Mon, 22 Dec 2025 16:46:30 +0530 Subject: [PATCH 0017/1330] FROMLIST: crypto: qce - Use existing devres APIs in devm_qce_dma_request() Switch to devm_kmalloc() and devm_dma_alloc_chan() in devm_qce_dma_request(). This allows us to drop two labels and shrink the function. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-7-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/dma.c | 38 ++++++++------------------------------ 1 file changed, 8 insertions(+), 30 deletions(-) diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index c29b0abe94453..6518bff871949 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -12,47 +12,25 @@ #define QCE_IGNORE_BUF_SZ (2 * QCE_BAM_BURST_SIZE) -static void qce_dma_release(void *data) -{ - struct qce_dma_data *dma = data; - - dma_release_channel(dma->txchan); - dma_release_channel(dma->rxchan); - kfree(dma->result_buf); -} - int devm_qce_dma_request(struct qce_device *qce) { struct qce_dma_data *dma = &qce->dma; struct device *dev = qce->dev; - int ret; - dma->txchan = dma_request_chan(dev, "tx"); + dma->txchan = devm_dma_request_chan(dev, "tx"); if (IS_ERR(dma->txchan)) return dev_err_probe(dev, PTR_ERR(dma->txchan), "Failed to get TX DMA channel\n"); - dma->rxchan = dma_request_chan(dev, "rx"); - if (IS_ERR(dma->rxchan)) { - ret = dev_err_probe(dev, PTR_ERR(dma->rxchan), - "Failed to get RX DMA channel\n"); - goto error_rx; - } - - dma->result_buf = kmalloc(QCE_RESULT_BUF_SZ + QCE_IGNORE_BUF_SZ, - GFP_KERNEL); - if (!dma->result_buf) { - ret = -ENOMEM; - goto error_nomem; - } + dma->rxchan = devm_dma_request_chan(dev, "rx"); + if (IS_ERR(dma->rxchan)) + return PTR_ERR(dma->rxchan); - return devm_add_action_or_reset(dev, qce_dma_release, dma); + dma->result_buf = devm_kmalloc(dev, QCE_RESULT_BUF_SZ + QCE_IGNORE_BUF_SZ, GFP_KERNEL); + if (!dma->result_buf) + return -ENOMEM; -error_nomem: - dma_release_channel(dma->rxchan); -error_rx: - dma_release_channel(dma->txchan); - return ret; + return 0; } struct scatterlist * From ecf0c37e19847b9ce40f553f0494392fb66ed9af Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:34:04 +0100 Subject: [PATCH 0018/1330] FROMLIST: crypto: qce - Map crypto memory for DMA As the first step in converting the driver to using DMA for register I/O, let's map the crypto memory range. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-8-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/core.c | 25 +++++++++++++++++++++++-- drivers/crypto/qce/core.h | 6 ++++++ 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 8b7bcd0c420c4..2667fcd67fee8 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -185,10 +185,19 @@ static int qce_check_version(struct qce_device *qce) return 0; } +static void qce_crypto_unmap_dma(void *data) +{ + struct qce_device *qce = data; + + dma_unmap_resource(qce->dev, qce->base_dma, qce->dma_size, + DMA_BIDIRECTIONAL, 0); +} + static int qce_crypto_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qce_device *qce; + struct resource *res; int ret; qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); @@ -198,7 +207,7 @@ static int qce_crypto_probe(struct platform_device *pdev) qce->dev = dev; platform_set_drvdata(pdev, qce); - qce->base = devm_platform_ioremap_resource(pdev, 0); + qce->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(qce->base)) return PTR_ERR(qce->base); @@ -244,7 +253,19 @@ static int qce_crypto_probe(struct platform_device *pdev) qce->async_req_enqueue = qce_async_request_enqueue; qce->async_req_done = qce_async_request_done; - return devm_qce_register_algs(qce); + ret = devm_qce_register_algs(qce); + if (ret) + return ret; + + qce->dma_size = resource_size(res); + qce->base_dma = dma_map_resource(dev, res->start, qce->dma_size, + DMA_BIDIRECTIONAL, 0); + qce->base_phys = res->start; + ret = dma_mapping_error(dev, qce->base_dma); + if (ret) + return ret; + + return devm_add_action_or_reset(qce->dev, qce_crypto_unmap_dma, qce); } static const struct of_device_id qce_crypto_of_match[] = { diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index f092ce2d3b04a..a80e12eac6c87 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -27,6 +27,9 @@ * @dma: pointer to dma data * @burst_size: the crypto burst size * @pipe_pair_id: which pipe pair id the device using + * @base_dma: base DMA address + * @base_phys: base physical address + * @dma_size: size of memory mapped for DMA * @async_req_enqueue: invoked by every algorithm to enqueue a request * @async_req_done: invoked by every algorithm to finish its request */ @@ -43,6 +46,9 @@ struct qce_device { struct qce_dma_data dma; int burst_size; unsigned int pipe_pair_id; + dma_addr_t base_dma; + phys_addr_t base_phys; + size_t dma_size; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); From b97448018c6d51fc5d0b0711b9497d9b9eb9e3be Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:34:05 +0100 Subject: [PATCH 0019/1330] FROMLIST: crypto: qce - Add BAM DMA support for crypto register I/O Implement the infrastructure for performing register I/O over BAM DMA, not CPU. No functional change yet. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-9-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/core.h | 4 ++ drivers/crypto/qce/dma.c | 109 ++++++++++++++++++++++++++++++++++++++ drivers/crypto/qce/dma.h | 5 ++ 3 files changed, 118 insertions(+) diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index a80e12eac6c87..d238097f834e4 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -30,6 +30,8 @@ * @base_dma: base DMA address * @base_phys: base physical address * @dma_size: size of memory mapped for DMA + * @read_buf: Buffer for DMA to write back to + * @read_buf_dma: Mapped address of the read buffer * @async_req_enqueue: invoked by every algorithm to enqueue a request * @async_req_done: invoked by every algorithm to finish its request */ @@ -49,6 +51,8 @@ struct qce_device { dma_addr_t base_dma; phys_addr_t base_phys; size_t dma_size; + __le32 *read_buf; + dma_addr_t read_buf_dma; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 6518bff871949..c46074ee8bd4f 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include @@ -11,6 +13,98 @@ #include "dma.h" #define QCE_IGNORE_BUF_SZ (2 * QCE_BAM_BURST_SIZE) +#define QCE_BAM_CMD_SGL_SIZE 128 +#define QCE_BAM_CMD_ELEMENT_SIZE 128 +#define QCE_MAX_REG_READ 8 + +struct qce_desc_info { + struct dma_async_tx_descriptor *dma_desc; + enum dma_data_direction dir; +}; + +struct qce_bam_transaction { + struct bam_cmd_element bam_ce[QCE_BAM_CMD_ELEMENT_SIZE]; + struct scatterlist wr_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct qce_desc_info *desc; + u32 bam_ce_idx; + u32 pre_bam_ce_idx; + u32 wr_sgl_cnt; +}; + +void qce_clear_bam_transaction(struct qce_device *qce) +{ + struct qce_bam_transaction *bam_txn = qce->dma.bam_txn; + + bam_txn->bam_ce_idx = 0; + bam_txn->wr_sgl_cnt = 0; + bam_txn->bam_ce_idx = 0; + bam_txn->pre_bam_ce_idx = 0; +} + +int qce_submit_cmd_desc(struct qce_device *qce) +{ + struct qce_desc_info *qce_desc = qce->dma.bam_txn->desc; + struct qce_bam_transaction *bam_txn = qce->dma.bam_txn; + struct dma_async_tx_descriptor *dma_desc; + struct dma_chan *chan = qce->dma.rxchan; + unsigned long attrs = DMA_PREP_CMD; + dma_cookie_t cookie; + unsigned int mapped; + int ret; + + mapped = dma_map_sg_attrs(qce->dev, bam_txn->wr_sgl, bam_txn->wr_sgl_cnt, + DMA_TO_DEVICE, attrs); + if (!mapped) + return -ENOMEM; + + dma_desc = dmaengine_prep_slave_sg(chan, bam_txn->wr_sgl, bam_txn->wr_sgl_cnt, + DMA_MEM_TO_DEV, attrs); + if (!dma_desc) { + dma_unmap_sg(qce->dev, bam_txn->wr_sgl, bam_txn->wr_sgl_cnt, DMA_TO_DEVICE); + return -ENOMEM; + } + + qce_desc->dma_desc = dma_desc; + cookie = dmaengine_submit(qce_desc->dma_desc); + + ret = dma_submit_error(cookie); + if (ret) + return ret; + + qce_dma_issue_pending(&qce->dma); + + return 0; +} + +static void qce_prep_dma_cmd_desc(struct qce_device *qce, struct qce_dma_data *dma, + unsigned int addr, void *buf) +{ + struct qce_bam_transaction *bam_txn = dma->bam_txn; + struct bam_cmd_element *bam_ce_buf; + int bam_ce_size, cnt, idx; + + idx = bam_txn->bam_ce_idx; + bam_ce_buf = &bam_txn->bam_ce[idx]; + bam_prep_ce_le32(bam_ce_buf, addr, BAM_WRITE_COMMAND, *((__le32 *)buf)); + + bam_ce_buf = &bam_txn->bam_ce[bam_txn->pre_bam_ce_idx]; + bam_txn->bam_ce_idx++; + bam_ce_size = (bam_txn->bam_ce_idx - bam_txn->pre_bam_ce_idx) * sizeof(*bam_ce_buf); + + cnt = bam_txn->wr_sgl_cnt; + + sg_set_buf(&bam_txn->wr_sgl[cnt], bam_ce_buf, bam_ce_size); + + ++bam_txn->wr_sgl_cnt; + bam_txn->pre_bam_ce_idx = bam_txn->bam_ce_idx; +} + +void qce_write_dma(struct qce_device *qce, unsigned int offset, u32 val) +{ + unsigned int reg_addr = ((unsigned int)(qce->base_phys) + offset); + + qce_prep_dma_cmd_desc(qce, &qce->dma, reg_addr, &val); +} int devm_qce_dma_request(struct qce_device *qce) { @@ -30,6 +124,21 @@ int devm_qce_dma_request(struct qce_device *qce) if (!dma->result_buf) return -ENOMEM; + dma->bam_txn = devm_kzalloc(dev, sizeof(*dma->bam_txn), GFP_KERNEL); + if (!dma->bam_txn) + return -ENOMEM; + + dma->bam_txn->desc = devm_kzalloc(dev, sizeof(*dma->bam_txn->desc), GFP_KERNEL); + if (!dma->bam_txn->desc) + return -ENOMEM; + + sg_init_table(dma->bam_txn->wr_sgl, QCE_BAM_CMD_SGL_SIZE); + + qce->read_buf = dmam_alloc_coherent(qce->dev, QCE_MAX_REG_READ * sizeof(*qce->read_buf), + &qce->read_buf_dma, GFP_KERNEL); + if (!qce->read_buf) + return -ENOMEM; + return 0; } diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 483789d9fa98e..f05dfa9e6b25b 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -8,6 +8,7 @@ #include +struct qce_bam_transaction; struct qce_device; /* maximum data transfer block size between BAM and CE */ @@ -32,6 +33,7 @@ struct qce_dma_data { struct dma_chan *txchan; struct dma_chan *rxchan; struct qce_result_dump *result_buf; + struct qce_bam_transaction *bam_txn; }; int devm_qce_dma_request(struct qce_device *qce); @@ -43,5 +45,8 @@ int qce_dma_terminate_all(struct qce_dma_data *dma); struct scatterlist * qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, unsigned int max_len); +void qce_write_dma(struct qce_device *qce, unsigned int offset, u32 val); +int qce_submit_cmd_desc(struct qce_device *qce); +void qce_clear_bam_transaction(struct qce_device *qce); #endif /* _DMA_H_ */ From 8f4eac46754f8715af5a2c05a350fc40b965151e Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:34:06 +0100 Subject: [PATCH 0020/1330] FROMLIST: crypto: qce - Add support for BAM locking Implement the infrastructure for using the new DMA controller lock/unlock feature of the BAM driver. No functional change for now. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-10-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/common.c | 18 ++++++++++++++++++ drivers/crypto/qce/dma.c | 19 +++++++++++++++++-- drivers/crypto/qce/dma.h | 4 ++++ 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 04253a8d33409..74756c222fed6 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -593,3 +593,21 @@ void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step) *minor = (val & CORE_MINOR_REV_MASK) >> CORE_MINOR_REV_SHIFT; *step = (val & CORE_STEP_REV_MASK) >> CORE_STEP_REV_SHIFT; } + +int qce_bam_lock(struct qce_device *qce) +{ + qce_clear_bam_transaction(qce); + /* Dummy write to acquire the lock on the BAM pipe. */ + qce_write(qce, REG_AUTH_SEG_CFG, 0); + + return qce_submit_cmd_desc_lock(qce); +} + +int qce_bam_unlock(struct qce_device *qce) +{ + qce_clear_bam_transaction(qce); + /* Dummy write to release the lock on the BAM pipe. */ + qce_write(qce, REG_AUTH_SEG_CFG, 0); + + return qce_submit_cmd_desc_unlock(qce); +} diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index c46074ee8bd4f..de13a49cb2754 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -41,13 +41,13 @@ void qce_clear_bam_transaction(struct qce_device *qce) bam_txn->pre_bam_ce_idx = 0; } -int qce_submit_cmd_desc(struct qce_device *qce) +static int qce_do_submit_cmd_desc(struct qce_device *qce, unsigned long flags) { struct qce_desc_info *qce_desc = qce->dma.bam_txn->desc; struct qce_bam_transaction *bam_txn = qce->dma.bam_txn; struct dma_async_tx_descriptor *dma_desc; struct dma_chan *chan = qce->dma.rxchan; - unsigned long attrs = DMA_PREP_CMD; + unsigned long attrs = DMA_PREP_CMD | flags; dma_cookie_t cookie; unsigned int mapped; int ret; @@ -76,6 +76,21 @@ int qce_submit_cmd_desc(struct qce_device *qce) return 0; } +int qce_submit_cmd_desc(struct qce_device *qce) +{ + return qce_do_submit_cmd_desc(qce, 0); +} + +int qce_submit_cmd_desc_lock(struct qce_device *qce) +{ + return qce_do_submit_cmd_desc(qce, DMA_PREP_LOCK); +} + +int qce_submit_cmd_desc_unlock(struct qce_device *qce) +{ + return qce_do_submit_cmd_desc(qce, DMA_PREP_UNLOCK); +} + static void qce_prep_dma_cmd_desc(struct qce_device *qce, struct qce_dma_data *dma, unsigned int addr, void *buf) { diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index f05dfa9e6b25b..4b3ee17db72e2 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -47,6 +47,10 @@ qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, unsigned int max_len); void qce_write_dma(struct qce_device *qce, unsigned int offset, u32 val); int qce_submit_cmd_desc(struct qce_device *qce); +int qce_submit_cmd_desc_lock(struct qce_device *qce); +int qce_submit_cmd_desc_unlock(struct qce_device *qce); void qce_clear_bam_transaction(struct qce_device *qce); +int qce_bam_lock(struct qce_device *qce); +int qce_bam_unlock(struct qce_device *qce); #endif /* _DMA_H_ */ From 933fe1b12a92db51a491abc5f12cf4021a5584e4 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Nov 2025 12:34:07 +0100 Subject: [PATCH 0021/1330] FROMLIST: crypto: qce - Switch to using BAM DMA for crypto I/O With everything else in place, we can now switch to actually using the BAM DMA for register I/O with DMA engine locking. Link: https://lore.kernel.org/lkml/20251106-qcom-qce-cmd-descr-v8-11-ecddca23ca26@linaro.org/ Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/aead.c | 10 ++++++++++ drivers/crypto/qce/common.c | 21 ++++++++++----------- drivers/crypto/qce/sha.c | 8 ++++++++ drivers/crypto/qce/skcipher.c | 7 +++++++ 4 files changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index 846e1d42775d1..aeb9094de983f 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -63,6 +63,10 @@ static void qce_aead_done(void *data) sg_free_table(&rctx->dst_tbl); } + error = qce_bam_unlock(qce); + if (error) + dev_err(qce->dev, "aead: failed to unlock the BAM\n"); + error = qce_check_status(qce, &status); if (error < 0 && (error != -EBADMSG)) dev_err(qce->dev, "aead operation error (%x)\n", status); @@ -188,6 +192,8 @@ qce_aead_ccm_prepare_buf_assoclen(struct aead_request *req) struct crypto_aead *tfm = crypto_aead_reqtfm(req); struct qce_aead_reqctx *rctx = aead_request_ctx_dma(req); struct qce_aead_ctx *ctx = crypto_aead_ctx(tfm); + struct qce_alg_template *tmpl = to_aead_tmpl(crypto_aead_reqtfm(req)); + struct qce_device *qce = tmpl->qce; unsigned int assoclen = rctx->assoclen; unsigned int adata_header_len, cryptlen, totallen; gfp_t gfp; @@ -200,6 +206,10 @@ qce_aead_ccm_prepare_buf_assoclen(struct aead_request *req) cryptlen = rctx->cryptlen; totallen = cryptlen + req->assoclen; + ret = qce_bam_lock(qce); + if (ret) + return ret; + /* Get the msg */ msg_sg = scatterwalk_ffwd(__sg, req->src, req->assoclen); diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 74756c222fed6..930006aaba4ac 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -14,6 +14,7 @@ #include "cipher.h" #include "common.h" #include "core.h" +#include "dma.h" #include "regs-v5.h" #include "sha.h" #include "aead.h" @@ -25,7 +26,7 @@ static inline u32 qce_read(struct qce_device *qce, u32 offset) static inline void qce_write(struct qce_device *qce, u32 offset, u32 val) { - writel(val, qce->base + offset); + qce_write_dma(qce, offset, val); } static inline void qce_write_array(struct qce_device *qce, u32 offset, @@ -82,6 +83,8 @@ static void qce_setup_config(struct qce_device *qce) { u32 config; + qce_clear_bam_transaction(qce); + /* get big endianness */ config = qce_config_reg(qce, 0); @@ -90,12 +93,14 @@ static void qce_setup_config(struct qce_device *qce) qce_write(qce, REG_CONFIG, config); } -static inline void qce_crypto_go(struct qce_device *qce, bool result_dump) +static int qce_crypto_go(struct qce_device *qce, bool result_dump) { if (result_dump) qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); else qce_write(qce, REG_GOPROC, BIT(GO_SHIFT)); + + return qce_submit_cmd_desc(qce); } #if defined(CONFIG_CRYPTO_DEV_QCE_SHA) || defined(CONFIG_CRYPTO_DEV_QCE_AEAD) @@ -223,9 +228,7 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) config = qce_config_reg(qce, 1); qce_write(qce, REG_CONFIG, config); - qce_crypto_go(qce, true); - - return 0; + return qce_crypto_go(qce, true); } #endif @@ -386,9 +389,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) config = qce_config_reg(qce, 1); qce_write(qce, REG_CONFIG, config); - qce_crypto_go(qce, true); - - return 0; + return qce_crypto_go(qce, true); } #endif @@ -535,9 +536,7 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) qce_write(qce, REG_CONFIG, config); /* Start the process */ - qce_crypto_go(qce, !IS_CCM(flags)); - - return 0; + return qce_crypto_go(qce, !IS_CCM(flags)); } #endif diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index 402e4e64347dc..2e2806519811a 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -60,6 +60,10 @@ static void qce_ahash_done(void *data) rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]); rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]); + error = qce_bam_unlock(qce); + if (error) + dev_err(qce->dev, "ahash: failed to unlock the BAM\n"); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "ahash operation error (%x)\n", status); @@ -90,6 +94,10 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) rctx->authklen = AES_KEYSIZE_128; } + ret = qce_bam_lock(qce); + if (ret) + return ret; + rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); if (rctx->src_nents < 0) { dev_err(qce->dev, "Invalid numbers of src SG.\n"); diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index 4ad3a17020101..1bf0cc8d18b70 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -51,6 +51,9 @@ static void qce_skcipher_done(void *data) dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); sg_free_table(&rctx->dst_tbl); + error = qce_bam_unlock(qce); + if (error) + dev_err(qce->dev, "skcipher: failed to unlock the BAM\n"); error = qce_check_status(qce, &status); if (error < 0) @@ -78,6 +81,10 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req) rctx->ivsize = crypto_skcipher_ivsize(skcipher); rctx->cryptlen = req->cryptlen; + ret = qce_bam_lock(qce); + if (ret) + return ret; + diff_dst = (req->src != req->dst) ? true : false; dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; From 575d0eba9b95de86accb1f8c72b88589fc3270bc Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Sat, 10 Jan 2026 01:27:51 +0530 Subject: [PATCH 0022/1330] FROMLIST: iommu/arm-smmu-qcom: Restore ACTLR settings for MDSS on sa8775p The ACTLR configuration for the sa8775p MDSS client was inadvertently dropped while reworking the commit f91879fdf70b ("iommu/arm-smmu-qcom: Add actlr settings for mdss on Qualcomm platforms"). Without this entry, the sa8775p MDSS block does not receive the intended default ACTLR configuration. Restore the missing compatible entry so that the platform receives the expected behavior. Link: https://lore.kernel.org/all/20260120151105.614792-1-bibek.patro@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro From 2af676babc7a75380752aac3507f7cd5a591c9e4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 13 Jan 2026 18:41:59 +0200 Subject: [PATCH 0023/1330] arm64: dts: qcom: agatti: enable FastRPC on the ADSP On Agatti platform the ADSP provides FastRPC support. Add corresponding device node, in order to be able to utilize the DSP offload from the Linux side. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov From 50d27fc01c55bda598bf63a0ffb1525f567a3f9c Mon Sep 17 00:00:00 2001 From: Udit Tiwari Date: Thu, 20 Nov 2025 11:54:43 +0530 Subject: [PATCH 0024/1330] FROMLIST: crypto: qce - Add runtime PM and interconnect bandwidth scaling support The Qualcomm Crypto Engine (QCE) driver currently lacks support for runtime power management (PM) and interconnect bandwidth control. As a result, the hardware remains fully powered and clocks stay enabled even when the device is idle. Additionally, static interconnect bandwidth votes are held indefinitely, preventing the system from reclaiming unused bandwidth. Address this by enabling runtime PM and dynamic interconnect bandwidth scaling to allow the system to suspend the device when idle and scale interconnect usage based on actual demand. Improve overall system efficiency by reducing power usage and optimizing interconnect resource allocation. Make the following changes as part of this integration: - Add support for pm_runtime APIs to manage device power state transitions. - Implement runtime_suspend() and runtime_resume() callbacks to gate clocks and vote for interconnect bandwidth only when needed. - Replace devm_clk_get_optional_enabled() with devm_pm_clk_create() + pm_clk_add() and let the PM core manage device clocks during runtime PM and system sleep. - Register dev_pm_ops with the platform driver to hook into the PM framework. Tested: - Verify that ICC votes drop to zero after probe and upon request completion. - Confirm that runtime PM usage count increments during active requests and decrements afterward. - Observe that the device correctly enters the suspended state when idle. Signed-off-by: Udit Tiwari Link: https://lore.kernel.org/r/20251120062443.2016084-1-quic_utiwari@quicinc.com --- drivers/crypto/qce/core.c | 105 +++++++++++++++++++++++++++++++------- 1 file changed, 87 insertions(+), 18 deletions(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 2667fcd67fee8..391a6bc6e6cbd 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -12,6 +12,9 @@ #include #include #include +#include +#include +#include #include #include @@ -89,13 +92,17 @@ static int qce_handle_queue(struct qce_device *qce, struct crypto_async_request *async_req, *backlog; int ret = 0, err; + ret = pm_runtime_resume_and_get(qce->dev); + if (ret < 0) + return ret; + scoped_guard(mutex, &qce->lock) { if (req) ret = crypto_enqueue_request(&qce->queue, req); /* busy, do not dequeue request */ if (qce->req) - return ret; + goto qce_suspend; backlog = crypto_get_backlog(&qce->queue); async_req = crypto_dequeue_request(&qce->queue); @@ -104,7 +111,7 @@ static int qce_handle_queue(struct qce_device *qce, } if (!async_req) - return ret; + goto qce_suspend; if (backlog) { scoped_guard(mutex, &qce->lock) @@ -117,6 +124,8 @@ static int qce_handle_queue(struct qce_device *qce, schedule_work(&qce->done_work); } +qce_suspend: + pm_runtime_put_autosuspend(qce->dev); return ret; } @@ -215,37 +224,47 @@ static int qce_crypto_probe(struct platform_device *pdev) if (ret < 0) return ret; - qce->core = devm_clk_get_optional_enabled(qce->dev, "core"); - if (IS_ERR(qce->core)) - return PTR_ERR(qce->core); + /* PM clock helpers: register device clocks */ + ret = devm_pm_clk_create(dev); + if (ret) + return ret; - qce->iface = devm_clk_get_optional_enabled(qce->dev, "iface"); - if (IS_ERR(qce->iface)) - return PTR_ERR(qce->iface); + ret = pm_clk_add(dev, "core"); + if (ret) + return ret; - qce->bus = devm_clk_get_optional_enabled(qce->dev, "bus"); - if (IS_ERR(qce->bus)) - return PTR_ERR(qce->bus); + ret = pm_clk_add(dev, "iface"); + if (ret) + return ret; - qce->mem_path = devm_of_icc_get(qce->dev, "memory"); + ret = pm_clk_add(dev, "bus"); + if (ret) + return ret; + + qce->mem_path = devm_of_icc_get(dev, "memory"); if (IS_ERR(qce->mem_path)) return PTR_ERR(qce->mem_path); - ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); + /* Enable runtime PM after clocks and ICC are acquired */ + ret = devm_pm_runtime_enable(dev); if (ret) return ret; - ret = devm_qce_dma_request(qce); + ret = pm_runtime_resume_and_get(dev); if (ret) return ret; + ret = devm_qce_dma_request(qce); + if (ret) + goto err_pm; + ret = qce_check_version(qce); if (ret) - return ret; + goto err_pm; ret = devm_mutex_init(qce->dev, &qce->lock); if (ret) - return ret; + goto err_pm; INIT_WORK(&qce->done_work, qce_req_done_work); crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH); @@ -255,19 +274,68 @@ static int qce_crypto_probe(struct platform_device *pdev) ret = devm_qce_register_algs(qce); if (ret) - return ret; + goto err_pm; qce->dma_size = resource_size(res); qce->base_dma = dma_map_resource(dev, res->start, qce->dma_size, DMA_BIDIRECTIONAL, 0); qce->base_phys = res->start; ret = dma_mapping_error(dev, qce->base_dma); + if (ret) + goto err_pm; + + ret = devm_add_action_or_reset(qce->dev, qce_crypto_unmap_dma, qce); + if (ret) + goto err_pm; + + /* Configure autosuspend after successful init */ + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; + +err_pm: + pm_runtime_put(dev); + + return ret; +} + +static int __maybe_unused qce_runtime_suspend(struct device *dev) +{ + struct qce_device *qce = dev_get_drvdata(dev); + + icc_disable(qce->mem_path); + + return 0; +} + +static int __maybe_unused qce_runtime_resume(struct device *dev) +{ + struct qce_device *qce = dev_get_drvdata(dev); + int ret = 0; + + ret = icc_enable(qce->mem_path); if (ret) return ret; - return devm_add_action_or_reset(qce->dev, qce_crypto_unmap_dma, qce); + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); + if (ret) + goto err_icc; + + return 0; + +err_icc: + icc_disable(qce->mem_path); + return ret; } +static const struct dev_pm_ops qce_crypto_pm_ops = { + SET_RUNTIME_PM_OPS(qce_runtime_suspend, qce_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + static const struct of_device_id qce_crypto_of_match[] = { { .compatible = "qcom,crypto-v5.1", }, { .compatible = "qcom,crypto-v5.4", }, @@ -281,6 +349,7 @@ static struct platform_driver qce_crypto_driver = { .driver = { .name = KBUILD_MODNAME, .of_match_table = qce_crypto_of_match, + .pm = &qce_crypto_pm_ops, }, }; module_platform_driver(qce_crypto_driver); From 90242c1f087de9dbb6292c8c831d51aec1513ce1 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Fri, 23 Jan 2026 15:18:28 +0530 Subject: [PATCH 0025/1330] FROMLIST: ufs: ufs-qcom: Fix sequential read variance The current devfreq downdifferential threshold of 5% causes overly aggressive frequency downscaling, leading to performance degradation sometimes during sequential read workloads. Update the UFS devfreq downdifferential threshold to 65. This widens the hysteresis window and prevents overly aggressive downscaling, ensuring that frequency is maintained for loads above 5% and scaling down occurs only when utilization falls below this level, while scale-up still triggers above the 70% threshold. Signed-off-by: Nitin Rawat Reviewed-by: Konrad Dybcio Signed-off-by: Pradeep P V K Link: https://lore.kernel.org/all/20260122141331.239354-4-nitin.rawat@oss.qualcomm.com/ --- drivers/ufs/host/ufs-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 375fd24ba458a..243133f59a896 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -2085,7 +2085,7 @@ static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, p->polling_ms = 60; p->timer = DEVFREQ_TIMER_DELAYED; d->upthreshold = 70; - d->downdifferential = 5; + d->downdifferential = 65; hba->clk_scaling.suspend_on_no_request = true; } From 06afaadc96783669559b97bef69aa878023533e5 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Fri, 23 Jan 2026 17:16:17 +0530 Subject: [PATCH 0026/1330] FROMLIST: bus: mhi: host: pci_generic: Add Qualcomm SDX35 modem Add support for sdx35 modem. Similar to SDX75, SDX35 can take longer to transition to ready during power up, so use modem_qcom_v2_mhiv_config configurations. 01:00.0 Unassigned class [ff00]: Qualcomm Device 011a Subsystem: Qualcomm Device 011a Link: https://lore.kernel.org/r/20260123-mhi_sdx35-v1-1-79440abf0c92@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/host/pci_generic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index 51456cee70a21..0395a8ea52b0e 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -407,6 +407,16 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .sideband_wake = false, }; +static const struct mhi_pci_dev_info mhi_qcom_sdx35_info = { + .name = "qcom-sdx35m", + .config = &modem_qcom_v2_mhiv_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, + .mru_default = 32768, + .sideband_wake = false, + .edl_trigger = true, +}; + static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { .name = "qcom-sdx24", .edl = "qcom/prog_firehose_sdx24.mbn", @@ -909,6 +919,8 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* Telit FN920C04 (sdx35) */ {PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2020), .driver_data = (kernel_ulong_t) &mhi_telit_fn920c04_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x011a), + .driver_data = (kernel_ulong_t) &mhi_qcom_sdx35_info }, { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c), From 8a7da4cb4ac5d767c91b8fc16dec26f3c300ebf6 Mon Sep 17 00:00:00 2001 From: Anjelique Melendez Date: Mon, 9 Feb 2026 12:49:11 -0800 Subject: [PATCH 0027/1330] FROMLIST: dt-bindings: soc: qcom: qcom,pmic-glink: Add Glymur and Kaanapali compatibles Glymur (a recent compute platform) and Kaanapali (a recent mobile platform) have the charger FW running on a new subsystem SOCCP (SOC Control Processor) instead of on ADSP like in previous platforms. Because of this, pmic_glink interface on Glymur and Kaanapali platforms are not compatible with previous platforms. Hence, add new compatible strings for Glymur and Kaanapali. Signed-off-by: Anjelique Melendez Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20260209204915.1983997-2-anjelique.melendez@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 7085bf88afaba..ff01d2f3ee5be 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -23,6 +23,8 @@ properties: oneOf: - items: - enum: + - qcom,glymur-pmic-glink + - qcom,kaanapali-pmic-glink - qcom,qcm6490-pmic-glink - qcom,sc8180x-pmic-glink - qcom,sc8280xp-pmic-glink From 98207e313239e7f8d3b48dfbf79c623bf7bd0be9 Mon Sep 17 00:00:00 2001 From: Anjelique Melendez Date: Mon, 9 Feb 2026 12:49:12 -0800 Subject: [PATCH 0028/1330] FROMLIST: soc: qcom: pmic_glink: Add charger PDR service information to client data Currently, the charger PD service path and service name are hard coded however these paths are not guaranteed to be the same between SOCs. Define charger PDR service path and service name as client data so that each PMIC generation can properly define these paths. Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260209204915.1983997-3-anjelique.melendez@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- drivers/soc/qcom/pmic_glink.c | 58 ++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 24 deletions(-) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index 627f96ca322e1..df2fd03d3b334 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -23,13 +23,19 @@ enum { PMIC_GLINK_CLIENT_UCSI, }; +struct pmic_glink_data { + unsigned long client_mask; + const char *charger_pdr_service_name; + const char *charger_pdr_service_path; +}; + struct pmic_glink { struct device *dev; struct pdr_handle *pdr; struct rpmsg_endpoint *ept; - unsigned long client_mask; + const struct pmic_glink_data *data; struct auxiliary_device altmode_aux; struct auxiliary_device ps_aux; @@ -292,7 +298,6 @@ static struct rpmsg_driver pmic_glink_rpmsg_driver = { static int pmic_glink_probe(struct platform_device *pdev) { - const unsigned long *match_data; struct pdr_service *service; struct pmic_glink *pg; int ret; @@ -309,12 +314,10 @@ static int pmic_glink_probe(struct platform_device *pdev) spin_lock_init(&pg->client_lock); mutex_init(&pg->state_lock); - match_data = (unsigned long *)of_device_get_match_data(&pdev->dev); - if (!match_data) + pg->data = of_device_get_match_data(&pdev->dev); + if (!pg->data) return -EINVAL; - pg->client_mask = *match_data; - pg->pdr = pdr_handle_alloc(pmic_glink_pdr_callback, pg); if (IS_ERR(pg->pdr)) { ret = dev_err_probe(&pdev->dev, PTR_ERR(pg->pdr), @@ -322,27 +325,30 @@ static int pmic_glink_probe(struct platform_device *pdev) return ret; } - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) { + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) { ret = pmic_glink_add_aux_device(pg, &pg->ucsi_aux, "ucsi"); if (ret) goto out_release_pdr_handle; } - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) { + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) { ret = pmic_glink_add_aux_device(pg, &pg->altmode_aux, "altmode"); if (ret) goto out_release_ucsi_aux; } - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) { + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) { ret = pmic_glink_add_aux_device(pg, &pg->ps_aux, "power-supply"); if (ret) goto out_release_altmode_aux; } - service = pdr_add_lookup(pg->pdr, "tms/servreg", "msm/adsp/charger_pd"); - if (IS_ERR(service)) { - ret = dev_err_probe(&pdev->dev, PTR_ERR(service), - "failed adding pdr lookup for charger_pd\n"); - goto out_release_aux_devices; + if (pg->data->charger_pdr_service_name && pg->data->charger_pdr_service_path) { + service = pdr_add_lookup(pg->pdr, pg->data->charger_pdr_service_name, + pg->data->charger_pdr_service_path); + if (IS_ERR(service)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(service), + "failed adding pdr lookup for charger_pd\n"); + goto out_release_aux_devices; + } } mutex_lock(&__pmic_glink_lock); @@ -352,13 +358,13 @@ static int pmic_glink_probe(struct platform_device *pdev) return 0; out_release_aux_devices: - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) pmic_glink_del_aux_device(pg, &pg->ps_aux); out_release_altmode_aux: - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) pmic_glink_del_aux_device(pg, &pg->altmode_aux); out_release_ucsi_aux: - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) pmic_glink_del_aux_device(pg, &pg->ucsi_aux); out_release_pdr_handle: pdr_handle_release(pg->pdr); @@ -372,23 +378,27 @@ static void pmic_glink_remove(struct platform_device *pdev) pdr_handle_release(pg->pdr); - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) pmic_glink_del_aux_device(pg, &pg->ps_aux); - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) pmic_glink_del_aux_device(pg, &pg->altmode_aux); - if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) + if (pg->data->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) pmic_glink_del_aux_device(pg, &pg->ucsi_aux); guard(mutex)(&__pmic_glink_lock); __pmic_glink = NULL; } -static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | - BIT(PMIC_GLINK_CLIENT_ALTMODE) | - BIT(PMIC_GLINK_CLIENT_UCSI); +static const struct pmic_glink_data pmic_glink_adsp_data = { + .client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | + BIT(PMIC_GLINK_CLIENT_ALTMODE) | + BIT(PMIC_GLINK_CLIENT_UCSI), + .charger_pdr_service_name = "tms/servreg", + .charger_pdr_service_path = "msm/adsp/charger_pd", +}; static const struct of_device_id pmic_glink_of_match[] = { - { .compatible = "qcom,pmic-glink", .data = &pmic_glink_sm8450_client_mask }, + { .compatible = "qcom,pmic-glink", .data = &pmic_glink_adsp_data }, {} }; MODULE_DEVICE_TABLE(of, pmic_glink_of_match); From d06eecdd46b04aa37704df25d4f163efef1bf743 Mon Sep 17 00:00:00 2001 From: Anjelique Melendez Date: Mon, 9 Feb 2026 12:49:13 -0800 Subject: [PATCH 0029/1330] FROMLIST: soc: qcom: pmic_glink: Add support for Glymur and Kaanapali On Glymur, a compute platform, and Kaanapali, a mobile platform, charger FW runs on SOCCP (another subsystem). SOCCP does not have any specific charger PDs defined. So, add support for Glymur and Kaanapali compatible strings. Signed-off-by: Anjelique Melendez Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260209204915.1983997-4-anjelique.melendez@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- drivers/soc/qcom/pmic_glink.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index df2fd03d3b334..3042261578aad 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -397,7 +397,15 @@ static const struct pmic_glink_data pmic_glink_adsp_data = { .charger_pdr_service_path = "msm/adsp/charger_pd", }; +static const struct pmic_glink_data pmic_glink_soccp_data = { + .client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | + BIT(PMIC_GLINK_CLIENT_ALTMODE) | + BIT(PMIC_GLINK_CLIENT_UCSI), +}; + static const struct of_device_id pmic_glink_of_match[] = { + { .compatible = "qcom,glymur-pmic-glink", .data = &pmic_glink_soccp_data }, + { .compatible = "qcom,kaanapali-pmic-glink", .data = &pmic_glink_soccp_data }, { .compatible = "qcom,pmic-glink", .data = &pmic_glink_adsp_data }, {} }; From 1cc8713b0d837d0b7557f55110ac04713d25ed69 Mon Sep 17 00:00:00 2001 From: Anjelique Melendez Date: Mon, 9 Feb 2026 12:49:14 -0800 Subject: [PATCH 0030/1330] FROMLIST: usb: typec: ucsi: ucsi_glink: Add support for Glymur and Kaanapali Add Glymur and Kaanapali compatible strings which both need UCSI_DELAY_DEVICE_PDOS quirk. Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov Reviewed-by: Heikki Krogerus Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260209204915.1983997-5-anjelique.melendez@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- drivers/usb/typec/ucsi/ucsi_glink.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/typec/ucsi/ucsi_glink.c b/drivers/usb/typec/ucsi/ucsi_glink.c index 11b3e24e34e2b..c7878ea0d37ae 100644 --- a/drivers/usb/typec/ucsi/ucsi_glink.c +++ b/drivers/usb/typec/ucsi/ucsi_glink.c @@ -373,6 +373,8 @@ static unsigned long quirk_sc8280xp = UCSI_NO_PARTNER_PDOS | UCSI_DELAY_DEVICE_P static unsigned long quirk_sm8450 = UCSI_DELAY_DEVICE_PDOS; static const struct of_device_id pmic_glink_ucsi_of_quirks[] = { + { .compatible = "qcom,glymur-pmic-glink", .data = &quirk_sm8450, }, + { .compatible = "qcom,kaanapali-pmic-glink", .data = &quirk_sm8450, }, { .compatible = "qcom,qcm6490-pmic-glink", .data = &quirk_sc8280xp, }, { .compatible = "qcom,sc8180x-pmic-glink", .data = &quirk_sc8180x, }, { .compatible = "qcom,sc8280xp-pmic-glink", .data = &quirk_sc8280xp, }, From d43caaeb7a334d899f1912b318f106a9b94aae9b Mon Sep 17 00:00:00 2001 From: Anjelique Melendez Date: Mon, 9 Feb 2026 12:49:15 -0800 Subject: [PATCH 0031/1330] FROMLIST: power: supply: qcom_battmgr: Add support for Glymur and Kaanapali Glymur is a compute platform which has the same power supply properties as X1E80100 and Kaanapali is a mobile platform which has the same power supply properties as SM8550. Add support for the Glymur and Kaanapali compatible strings. Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260209204915.1983997-6-anjelique.melendez@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- drivers/power/supply/qcom_battmgr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qcom_battmgr.c index 80572ee945b4f..490137a23d00e 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -1611,6 +1611,8 @@ static void qcom_battmgr_pdr_notify(void *priv, int state) } static const struct of_device_id qcom_battmgr_of_variants[] = { + { .compatible = "qcom,glymur-pmic-glink", .data = (void *)QCOM_BATTMGR_X1E80100 }, + { .compatible = "qcom,kaanapali-pmic-glink", .data = (void *)QCOM_BATTMGR_SM8550 }, { .compatible = "qcom,sc8180x-pmic-glink", .data = (void *)QCOM_BATTMGR_SC8280XP }, { .compatible = "qcom,sc8280xp-pmic-glink", .data = (void *)QCOM_BATTMGR_SC8280XP }, { .compatible = "qcom,sm8550-pmic-glink", .data = (void *)QCOM_BATTMGR_SM8550 }, From e0d564b336598c1f12c5d62d00b682b75b84af81 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 9 Feb 2026 16:24:35 +0530 Subject: [PATCH 0032/1330] FROMLIST: dt-bindings: iio: adc: Split out QCOM VADC channel properties Split out the common channel properties for QCOM VADC devices into a separate file so that it can be included as a reference for devices using them. This will be needed for the upcoming ADC5 Gen3 binding support patch, as ADC5 Gen3 also uses all of these common properties. Reviewed-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron Link: https://lore.kernel.org/all/20260209105438.596339-2-jishnu.prakash@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- .../iio/adc/qcom,spmi-vadc-common.yaml | 84 +++++++++++++++++++ .../bindings/iio/adc/qcom,spmi-vadc.yaml | 76 +---------------- 2 files changed, 86 insertions(+), 74 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml new file mode 100644 index 0000000000000..3ae252c17b91a --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SPMI PMIC ADC channels + +maintainers: + - Jishnu Prakash + +description: + This defines the common properties used to define Qualcomm VADC channels. + +properties: + reg: + description: + ADC channel number (PMIC-specific for versions after PMIC5 ADC). + maxItems: 1 + + label: + description: + ADC input of the platform as seen in the schematics. + For thermistor inputs connected to generic AMUX or GPIO inputs + these can vary across platform for the same pins. Hence select + the platform schematics name for this channel. + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + + qcom,pre-scaling: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Used for scaling the channel input signal before the signal is + fed to VADC. The configuration for this node is to know the + pre-determined ratio and use it for post scaling. It is a pair of + integers, denoting the numerator and denominator of the fraction by which + input signal is multiplied. For example, <1 3> indicates the signal is scaled + down to 1/3 of its value before ADC measurement. + If property is not found default value depending on chip will be used. + oneOf: + - items: + - const: 1 + - enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ] + - items: + - const: 10 + - const: 81 + + qcom,ratiometric: + type: boolean + description: | + Channel calibration type. + - For compatible property "qcom,spmi-vadc", if this property is + specified VADC will use the VDD reference (1.8V) and GND for + channel calibration. If property is not found, channel will be + calibrated with 0.625V and 1.25V reference channels, also + known as absolute calibration. + - For other compatible properties, if this property is specified + VADC will use the VDD reference (1.875V) and GND for channel + calibration. If property is not found, channel will be calibrated + with 0V and 1.25V reference channels, also known as absolute calibration. + + qcom,hw-settle-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Time between AMUX getting configured and the ADC starting + conversion. The 'hw_settle_time' is an index used from valid values + and programmed in hardware to achieve the hardware settling delay. + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Number of samples to be used for measurement. + Averaging provides the option to obtain a single measurement + from the ADC that is an average of multiple samples. The value + selected is 2^(value). + +required: + - reg + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index b9dc04b0d307c..16c80709a3eed 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -56,7 +56,7 @@ required: patternProperties: "^channel@[0-9a-f]+$": type: object - additionalProperties: false + unevaluatedProperties: false description: | Represents the external channels which are connected to the ADC. For compatible property "qcom,spmi-vadc" following channels, also known as @@ -64,79 +64,7 @@ patternProperties: configuration nodes should be defined: VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, VADC_GND_REF and VADC_VDD_VADC. - - properties: - reg: - maxItems: 1 - description: | - ADC channel number. - See include/dt-bindings/iio/qcom,spmi-vadc.h - For PMIC7 ADC, the channel numbers are specified separately per PMIC - in the PMIC-specific files in include/dt-bindings/iio/. - - label: - description: | - ADC input of the platform as seen in the schematics. - For thermistor inputs connected to generic AMUX or GPIO inputs - these can vary across platform for the same pins. Hence select - the platform schematics name for this channel. - - qcom,decimation: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - This parameter is used to decrease ADC sampling rate. - Quicker measurements can be made by reducing decimation ratio. - - qcom,pre-scaling: - description: | - Used for scaling the channel input signal before the signal is - fed to VADC. The configuration for this node is to know the - pre-determined ratio and use it for post scaling. It is a pair of - integers, denoting the numerator and denominator of the fraction by which - input signal is multiplied. For example, <1 3> indicates the signal is scaled - down to 1/3 of its value before ADC measurement. - If property is not found default value depending on chip will be used. - $ref: /schemas/types.yaml#/definitions/uint32-array - oneOf: - - items: - - const: 1 - - enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ] - - items: - - const: 10 - - const: 81 - - qcom,ratiometric: - description: | - Channel calibration type. - - For compatible property "qcom,spmi-vadc", if this property is - specified VADC will use the VDD reference (1.8V) and GND for - channel calibration. If property is not found, channel will be - calibrated with 0.625V and 1.25V reference channels, also - known as absolute calibration. - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and - "qcom,spmi-adc-rev2", if this property is specified VADC will use - the VDD reference (1.875V) and GND for channel calibration. If - property is not found, channel will be calibrated with 0V and 1.25V - reference channels, also known as absolute calibration. - type: boolean - - qcom,hw-settle-time: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Time between AMUX getting configured and the ADC starting - conversion. The 'hw_settle_time' is an index used from valid values - and programmed in hardware to achieve the hardware settling delay. - - qcom,avg-samples: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Number of samples to be used for measurement. - Averaging provides the option to obtain a single measurement - from the ADC that is an average of multiple samples. The value - selected is 2^(value). - - required: - - reg + $ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml allOf: - if: From 9bcb1b9c19d44e21d7f8cd023c04b9fdcb022a8f Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 9 Feb 2026 16:24:36 +0530 Subject: [PATCH 0033/1330] FROMLIST: dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS(Programmable Boot Sequence) firmware through a single register interface. This interface is implemented on SDAM (Shared Direct Access Memory) peripherals on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Add documentation for PMIC5 Gen3 ADC and update SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode. Acked-by: Jonathan Cameron Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20260209105438.596339-3-jishnu.prakash@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 151 ++++++++++++++++++ .../bindings/iio/adc/qcom,spmi-vadc.yaml | 2 + .../bindings/mfd/qcom,spmi-pmic.yaml | 1 + 3 files changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml new file mode 100644 index 0000000000000..149f4af8f4b8b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC5 Gen3 + +maintainers: + - Jishnu Prakash + +description: | + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to clients to read + voltage. It is a 16-bit sigma-delta ADC. It also performs the same thermal + monitoring function as the existing ADC_TM devices. + + The interface is implemented on SDAM (Shared Direct Access Memory) peripherals + on the master PMIC rather than a dedicated ADC peripheral. The number of PMIC + SDAM peripherals allocated for ADC is not correlated with the PMIC used, it is + programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements. + All boards using a particular (SOC + master PMIC) combination will have the + same number of ADC SDAMs supported on that PMIC. + +properties: + compatible: + const: qcom,spmi-adc5-gen3 + + reg: + items: + - description: SDAM0 base address in the SPMI PMIC register map + - description: SDAM1 base address + minItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + + "#thermal-sensor-cells": + const: 1 + + interrupts: + items: + - description: SDAM0 end of conversion (EOC) interrupt + - description: SDAM1 EOC interrupt + minItems: 1 + +patternProperties: + "^channel@[0-9a-f]+$": + type: object + unevaluatedProperties: false + $ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml + description: + Represents the external channels which are connected to the ADC. + + properties: + qcom,decimation: + enum: [ 85, 340, 1360 ] + default: 1360 + + qcom,hw-settle-time: + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, + 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000 ] + default: 15 + + qcom,avg-samples: + enum: [ 1, 2, 4, 8, 16 ] + default: 1 + + qcom,adc-tm: + description: + ADC_TM is a threshold monitoring feature in HW which can be enabled + on any ADC channel, to trigger an IRQ for threshold violation. In + earlier ADC generations, it was implemented in a separate device + (documented in Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.) + In Gen3, this feature can be enabled in the same ADC device for any + channel and threshold monitoring and IRQ triggering are handled in FW + (PBS) instead of another dedicated HW block. + This property indicates ADC_TM monitoring is done on this channel. + type: boolean + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#io-channel-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + adc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; + + /* PMK8550 Channel nodes */ + channel@3 { + reg = <0x3>; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,adc-tm; + }; + + /* PM8550 Channel nodes */ + channel@103 { + reg = <0x103>; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@78f { + reg = <0x78f>; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = <0x203>; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index 16c80709a3eed..72188041e8b53 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -15,6 +15,8 @@ description: | voltage. The VADC is a 15-bit sigma-delta ADC. SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read voltage. The VADC is a 16-bit sigma-delta ADC. + Note that PMIC7 ADC is the generation between PMIC5 and PMIC5 Gen3 ADC, + it can be considered like PMIC5 Gen2. properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index e5931d18d9984..644c42b5e2e57 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -135,6 +135,7 @@ patternProperties: "^adc@[0-9a-f]+$": type: object oneOf: + - $ref: /schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# - $ref: /schemas/iio/adc/qcom,spmi-iadc.yaml# - $ref: /schemas/iio/adc/qcom,spmi-rradc.yaml# - $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml# From 216cb1d4872a4e5e49f87d13346d0a07ab0c8be5 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 9 Feb 2026 16:24:37 +0530 Subject: [PATCH 0034/1330] FROMLIST: iio: adc: Add support for QCOM PMIC5 Gen3 ADC The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2, with all SW communication to ADC going through PMK8550 which communicates with other PMICs through PBS. One major difference is that the register interface used here is that of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550. There may be more than one SDAM used for ADC5 Gen3 and each has eight channels, which may be used for either immediate reads (same functionality as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements (same as ADC_TM functionality). By convention, we reserve the first channel of the first SDAM for all immediate reads and use the remaining channels across all SDAMs for ADC_TM monitoring functionality. Add support for PMIC5 Gen3 ADC driver for immediate read functionality. ADC_TM is implemented as an auxiliary thermal driver under this ADC driver. Link: https://lore.kernel.org/all/20260209105438.596339-4-jishnu.prakash@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- drivers/iio/adc/Kconfig | 26 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/qcom-spmi-adc5-gen3.c | 860 ++++++++++++++++++ include/linux/iio/adc/qcom-adc5-gen3-common.h | 212 +++++ 4 files changed, 1099 insertions(+) create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c create mode 100644 include/linux/iio/adc/qcom-adc5-gen3-common.h diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 60038ae8dfc4d..1f5915dd192dd 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1366,6 +1366,32 @@ config QCOM_SPMI_ADC5 To compile this driver as a module, choose M here: the module will be called qcom-spmi-adc5. +config QCOM_SPMI_ADC5_GEN3 + tristate "Qualcomm Technologies Inc. SPMI PMIC5 GEN3 ADC" + depends on SPMI && THERMAL + select REGMAP_SPMI + select QCOM_VADC_COMMON + select AUXILIARY_BUS + help + IIO Voltage PMIC5 Gen3 ADC driver for Qualcomm Technologies Inc. + + The driver supports reading multiple channels. The ADC is a 16-bit + sigma-delta ADC. The hardware supports calibrated results for + conversion requests and clients include reading phone power supply + voltage, on board system thermistors connected to the PMIC ADC, + PMIC die temperature, charger temperature, battery current, USB + voltage input and voltage signals connected to supported PMIC GPIO + pins. The hardware supports internal pull-up for thermistors and can + choose between a 30k, 100k or 400k ohm pull up using the ADC channels. + + In addition, the same driver supports ADC thermal monitoring devices + too. They appear as thermal zones with multiple trip points. A thermal + client sets threshold temperature for both warm and cool trips and + gets updated when a threshold is reached. + + To compile this driver as a module, choose M here: the module will + be called qcom-spmi-adc5-gen3. + config RCAR_GYRO_ADC tristate "Renesas R-Car GyroADC driver" depends on ARCH_RCAR_GEN2 || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index c76550415ff17..097357d146baf 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -116,6 +116,7 @@ obj-$(CONFIG_PAC1934) += pac1934.o obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o +obj-$(CONFIG_QCOM_SPMI_ADC5_GEN3) += qcom-spmi-adc5-gen3.o obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c new file mode 100644 index 0000000000000..76ea9bde61685 --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADC5_GEN3_VADC_SDAM 0x0 + +struct adc5_chip; + +/** + * struct adc5_channel_prop - ADC channel structure + * @common_props: structure with ADC channel properties (common to TM usage). + * @adc_tm: indicates TM type if the channel is used for TM measurements. + * @chip: pointer to top-level ADC device structure. + */ +struct adc5_channel_prop { + struct adc5_channel_common_prop common_props; + int adc_tm; + struct adc5_chip *chip; +}; + +/** + * struct adc5_chip - ADC private structure. + * @dev: SPMI ADC5 Gen3 device. + * @dev_data: Top-level ADC device data. + * @nchannels: number of ADC channels. + * @chan_props: array of ADC channel properties. + * @iio_chans: array of IIO channels specification. + * @complete: ADC result notification after interrupt is received. + * @lock: ADC lock for access to the peripheral, to prevent concurrent + * requests from multiple clients. + * @data: software configuration data. + * @n_tm_channels: number of ADC channels used for TM measurements. + * @handler: TM callback to be called for threshold violation interrupt + * on first SDAM. + * @tm_aux: pointer to auxiliary TM device. + */ +struct adc5_chip { + struct device *dev; + struct adc5_device_data dev_data; + unsigned int nchannels; + struct adc5_channel_prop *chan_props; + struct iio_chan_spec *iio_chans; + struct completion complete; + struct mutex lock; + const struct adc5_data *data; + unsigned int n_tm_channels; + void (*handler)(struct auxiliary_device *tm_aux); + struct auxiliary_device *tm_aux; +}; + +int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len) +{ + return regmap_bulk_read(adc->regmap, + adc->base[sdam_index].base_addr + offset, + data, len); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_read, "QCOM_SPMI_ADC5_GEN3"); + +int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len) +{ + return regmap_bulk_write(adc->regmap, + adc->base[sdam_index].base_addr + offset, + data, len); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_write, "QCOM_SPMI_ADC5_GEN3"); + +static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data) +{ + u8 rslt[2]; + int ret; + + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_CH_DATA0(0), rslt, sizeof(rslt)); + if (ret) + return ret; + + *data = get_unaligned_le16(rslt); + + if (*data == ADC5_USR_DATA_CHECK) { + dev_err(adc->dev, "Invalid data:%#x\n", *data); + return -EINVAL; + } + + dev_dbg(adc->dev, "voltage raw code:%#x\n", *data); + + return 0; +} + +void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 *data) +{ + /* Update calibration select and decimation ratio select */ + *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK); + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method); + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_update_dig_param, "QCOM_SPMI_ADC5_GEN3"); + +#define ADC5_GEN3_READ_CONFIG_REGS 7 + +static int adc5_gen3_configure(struct adc5_chip *adc, + struct adc5_channel_common_prop *prop) +{ + u8 buf[ADC5_GEN3_READ_CONFIG_REGS]; + u8 conv_req = 0; + int ret; + + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID, + buf, sizeof(buf)); + if (ret) + return ret; + + /* Write SID */ + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid); + + /* + * Use channel 0 by default for immediate conversion and to indicate + * there is an actual conversion request + */ + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | 0; + + buf[2] = ADC5_GEN3_TIME_IMMEDIATE; + + /* Digital param selection */ + adc5_gen3_update_dig_param(prop, &buf[3]); + + /* Update fast average sample value */ + buf[4] = FIELD_PREP(ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK, + prop->avg_samples) | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] = prop->channel; + + /* Select HW settle delay for channel */ + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, + prop->hw_settle_time_us); + + reinit_completion(&adc->complete); + + ret = adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID, + buf, sizeof(buf)); + if (ret) + return ret; + + conv_req = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_CONV_REQ, &conv_req, sizeof(conv_req)); +} + +/* + * Worst case delay from PBS in readying handshake bit can be up to 15ms, when + * PBS is busy running other simultaneous transactions, while in the best case, + * it is already ready at this point. Assigning polling delay and retry count + * accordingly. + */ + +#define ADC5_GEN3_HS_DELAY_US 100 +#define ADC5_GEN3_HS_RETRY_COUNT 150 + +int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc, + unsigned int sdam_index) +{ + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ; + int ret; + u8 status = 0; + + for (int count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) { + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, sizeof(status)); + if (ret) + return ret; + + if (status == ADC5_GEN3_HS_READY) { + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ, + &conv_req, sizeof(conv_req)); + if (ret) + return ret; + + if (!conv_req) + return 0; + } + + fsleep(ADC5_GEN3_HS_DELAY_US); + } + + pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n", + sdam_index, status); + return -ETIMEDOUT; +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_poll_wait_hs, "QCOM_SPMI_ADC5_GEN3"); + +int adc5_gen3_status_clear(struct adc5_device_data *adc, + int sdam_index, u16 offset, u8 *val, int len) +{ + u8 value; + int ret; + + ret = adc5_gen3_write(adc, sdam_index, offset, val, len); + if (ret) + return ret; + + /* To indicate conversion request is only to clear a status */ + value = 0; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &value, + sizeof(value)); + if (ret) + return ret; + + value = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &value, + sizeof(value)); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_status_clear, "QCOM_SPMI_ADC5_GEN3"); + +/* + * Worst case delay from PBS for conversion time can be up to 500ms, when PBS + * has timed out twice, once for the initial attempt and once for a retry of + * the same transaction. + */ + +#define ADC5_GEN3_CONV_TIMEOUT_MS 501 + +static int adc5_gen3_do_conversion(struct adc5_chip *adc, + struct adc5_channel_common_prop *prop, + u16 *data_volt) +{ + unsigned long rc; + int ret; + u8 val; + + guard(mutex)(&adc->lock); + ret = adc5_gen3_poll_wait_hs(&adc->dev_data, ADC5_GEN3_VADC_SDAM); + if (ret) + return ret; + + ret = adc5_gen3_configure(adc, prop); + if (ret) { + dev_err(adc->dev, "ADC configure failed with %d\n", ret); + return ret; + } + + /* No support for polling mode at present */ + rc = wait_for_completion_timeout(&adc->complete, + msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS)); + if (!rc) { + dev_err(adc->dev, "Reading ADC channel %s timed out\n", + prop->label); + return -ETIMEDOUT; + } + + ret = adc5_gen3_read_voltage_data(adc, data_volt); + if (ret) + return ret; + + val = BIT(0); + return adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_EOC_CLR, &val, 1); +} + +static irqreturn_t adc5_gen3_isr(int irq, void *dev_id) +{ + struct adc5_chip *adc = dev_id; + struct device *dev = adc->dev; + struct auxiliary_device *adev; + u8 status, eoc_status, val; + u8 tm_status[2]; + int ret; + + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_STATUS1, &status, sizeof(status)); + if (ret) { + dev_err(dev, "adc read status1 failed with %d\n", ret); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_EOC_STS, &eoc_status, sizeof(eoc_status)); + if (ret) { + dev_err(dev, "adc read eoc status failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { + dev_err_ratelimited(dev, + "Unexpected conversion fault, status:%#x, eoc_status:%#x\n", + status, eoc_status); + val = ADC5_GEN3_CONV_ERR_CLR_REQ; + adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_CONV_ERR_CLR, &val, 1); + return IRQ_HANDLED; + } + + /* CHAN0 is the preconfigured channel for immediate conversion */ + if (eoc_status & ADC5_GEN3_EOC_CHAN_0) + complete(&adc->complete); + + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_TM_HIGH_STS, tm_status, sizeof(tm_status)); + if (ret) { + dev_err(dev, "adc read TM status failed with %d\n", ret); + return IRQ_HANDLED; + } + + dev_dbg(dev, "Interrupt status:%#x, EOC status:%#x, high:%#x, low:%#x\n", + status, eoc_status, tm_status[0], tm_status[1]); + + if (tm_status[0] || tm_status[1]) { + adev = adc->tm_aux; + if (!adev || !adev->dev.driver) { + dev_err(dev, "adc_tm auxiliary device not initialized\n"); + return IRQ_HANDLED; + } + + adc->handler(adev); + } + + return IRQ_HANDLED; +} + +static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev, + const struct fwnode_reference_args *iiospec) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + int v_channel; + + for (int i = 0; i < adc->nchannels; i++) { + v_channel = ADC5_GEN3_V_CHAN(adc->chan_props[i].common_props); + if (v_channel == iiospec->args[0]) + return i; + } + + return -ENOENT; +} + +static int adc5_gen3_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + struct adc5_channel_common_prop *prop; + u16 adc_code_volt; + int ret; + + prop = &adc->chan_props[chan->address].common_props; + + switch (mask) { + case IIO_CHAN_INFO_PROCESSED: + ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt); + if (ret) + return ret; + + ret = qcom_adc5_hw_scale(prop->scale_fn_type, prop->prescale, + adc->data, adc_code_volt, val); + if (ret) + return ret; + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int adc5_gen3_read_label(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, char *label) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + struct adc5_channel_prop *prop; + + prop = &adc->chan_props[chan->address]; + return sprintf(label, "%s\n", prop->common_props.label); +} + +static const struct iio_info adc5_gen3_info = { + .read_raw = adc5_gen3_read_raw, + .read_label = adc5_gen3_read_label, + .fwnode_xlate = adc5_gen3_fwnode_xlate, +}; + +struct adc5_channels { + unsigned int prescale_index; + enum iio_chan_type type; + long info_mask; + enum vadc_scale_fn_type scale_fn_type; +}; + +/* In these definitions, _pre refers to an index into adc5_prescale_ratios. */ +#define ADC5_CHAN(_type, _mask, _pre, _scale) \ + { \ + .prescale_index = _pre, \ + .type = _type, \ + .info_mask = _mask, \ + .scale_fn_type = _scale, \ + }, \ + +#define ADC5_CHAN_TEMP(_pre, _scale) \ + ADC5_CHAN(IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +#define ADC5_CHAN_VOLT(_pre, _scale) \ + ADC5_CHAN(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +#define ADC5_CHAN_CUR(_pre, _scale) \ + ADC5_CHAN(IIO_CURRENT, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = { + [ADC5_GEN3_REF_GND] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_PMIC_THERM_PM7) + [ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) +}; + +static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc, + struct adc5_channel_prop *prop, + struct fwnode_handle *fwnode) +{ + const char *name = fwnode_get_name(fwnode); + const struct adc5_data *data = adc->data; + struct device *dev = adc->dev; + const char *channel_name; + u32 chan, value, sid; + u32 varr[2]; + int ret; + + ret = fwnode_property_read_u32(fwnode, "reg", &chan); + if (ret < 0) + return dev_err_probe(dev, ret, "invalid channel number %s\n", + name); + + /* + * Value read from "reg" is virtual channel number + * virtual channel number = sid << 8 | channel number + */ + sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan); + chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan); + + if (chan > ADC5_MAX_CHANNEL) + return dev_err_probe(dev, -EINVAL, + "%s invalid channel number %d\n", + name, chan); + + prop->common_props.channel = chan; + prop->common_props.sid = sid; + + if (!adc->data->adc_chans[chan].info_mask) + return dev_err_probe(dev, -EINVAL, "Channel %#x not supported\n", chan); + + channel_name = name; + fwnode_property_read_string(fwnode, "label", &channel_name); + prop->common_props.label = channel_name; + + value = data->decimation[ADC5_DECIMATION_DEFAULT]; + fwnode_property_read_u32(fwnode, "qcom,decimation", &value); + ret = qcom_adc5_decimation_from_dt(value, data->decimation); + if (ret < 0) + return dev_err_probe(dev, ret, "%#x invalid decimation %d\n", + chan, value); + prop->common_props.decimation = ret; + + prop->common_props.prescale = adc->data->adc_chans[chan].prescale_index; + ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2); + if (!ret) { + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); + if (ret < 0) + return dev_err_probe(dev, ret, + "%#x invalid pre-scaling <%d %d>\n", + chan, varr[0], varr[1]); + prop->common_props.prescale = ret; + } + + value = data->hw_settle_1[VADC_DEF_HW_SETTLE_TIME]; + fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value); + ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1); + if (ret < 0) + return dev_err_probe(dev, ret, + "%#x invalid hw-settle-time %d us\n", + chan, value); + prop->common_props.hw_settle_time_us = ret; + + value = BIT(VADC_DEF_AVG_SAMPLES); + fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value); + ret = qcom_adc5_avg_samples_from_dt(value); + if (ret < 0) + return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n", + chan, value); + prop->common_props.avg_samples = ret; + + if (fwnode_property_read_bool(fwnode, "qcom,ratiometric")) + prop->common_props.cal_method = ADC5_RATIOMETRIC_CAL; + else + prop->common_props.cal_method = ADC5_ABSOLUTE_CAL; + + prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm"); + if (prop->adc_tm) { + adc->n_tm_channels++; + if (adc->n_tm_channels > (adc->dev_data.num_sdams * 8 - 1)) + return dev_err_probe(dev, -EINVAL, + "Number of TM nodes %u greater than channels supported:%u\n", + adc->n_tm_channels, + adc->dev_data.num_sdams * 8 - 1); + } + + return 0; +} + +static const struct adc5_data adc5_gen3_data_pmic = { + .full_scale_code_volt = 0x70e4, + .adc_chans = adc5_gen3_chans_pmic, + .info = &adc5_gen3_info, + .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) + { 85, 340, 1360 }, + .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) + { 15, 100, 200, 300, + 400, 500, 600, 700, + 1000, 2000, 4000, 8000, + 16000, 32000, 64000, 128000 }, +}; + +static const struct of_device_id adc5_match_table[] = { + { + .compatible = "qcom,spmi-adc5-gen3", + .data = &adc5_gen3_data_pmic, + }, + { } +}; +MODULE_DEVICE_TABLE(of, adc5_match_table); + +static int adc5_get_fw_data(struct adc5_chip *adc) +{ + const struct adc5_channels *adc_chan; + struct adc5_channel_prop *chan_props; + struct iio_chan_spec *iio_chan; + struct device *dev = adc->dev; + unsigned int index = 0; + int ret; + + adc->nchannels = device_get_child_node_count(dev); + if (!adc->nchannels) + return dev_err_probe(dev, -EINVAL, "No ADC channels found\n"); + + adc->iio_chans = devm_kcalloc(dev, adc->nchannels, + sizeof(*adc->iio_chans), GFP_KERNEL); + if (!adc->iio_chans) + return -ENOMEM; + + adc->chan_props = devm_kcalloc(dev, adc->nchannels, + sizeof(*adc->chan_props), GFP_KERNEL); + if (!adc->chan_props) + return -ENOMEM; + + chan_props = adc->chan_props; + adc->n_tm_channels = 0; + iio_chan = adc->iio_chans; + adc->data = device_get_match_data(dev); + + device_for_each_child_node_scoped(dev, child) { + ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child); + if (ret) + return ret; + + chan_props->chip = adc; + adc_chan = &adc->data->adc_chans[chan_props->common_props.channel]; + chan_props->common_props.scale_fn_type = adc_chan->scale_fn_type; + + iio_chan->channel = ADC5_GEN3_V_CHAN(chan_props->common_props); + iio_chan->info_mask_separate = adc_chan->info_mask; + iio_chan->type = adc_chan->type; + iio_chan->address = index; + iio_chan->indexed = 1; + iio_chan++; + chan_props++; + index++; + } + + return 0; +} + +static void adc5_gen3_uninit_aux(void *data) +{ + auxiliary_device_uninit(data); +} + +static void adc5_gen3_delete_aux(void *data) +{ + auxiliary_device_delete(data); +} + +static void adc5_gen3_aux_device_release(struct device *dev) {} + +static int adc5_gen3_add_aux_tm_device(struct adc5_chip *adc) +{ + struct tm5_aux_dev_wrapper *aux_device; + int ret, i_tm = 0; + + aux_device = devm_kzalloc(adc->dev, sizeof(*aux_device), GFP_KERNEL); + if (!aux_device) + return -ENOMEM; + + aux_device->aux_dev.name = "adc5_tm_gen3"; + aux_device->aux_dev.dev.parent = adc->dev; + aux_device->aux_dev.dev.release = adc5_gen3_aux_device_release; + + aux_device->tm_props = devm_kcalloc(adc->dev, adc->n_tm_channels, + sizeof(*aux_device->tm_props), + GFP_KERNEL); + if (!aux_device->tm_props) + return -ENOMEM; + + aux_device->dev_data = &adc->dev_data; + + for (int i = 0; i < adc->nchannels; i++) { + if (!adc->chan_props[i].adc_tm) + continue; + aux_device->tm_props[i_tm] = adc->chan_props[i].common_props; + i_tm++; + } + + device_set_of_node_from_dev(&aux_device->aux_dev.dev, adc->dev); + + aux_device->n_tm_channels = adc->n_tm_channels; + + ret = auxiliary_device_init(&aux_device->aux_dev); + if (ret) + return ret; + + ret = devm_add_action_or_reset(adc->dev, adc5_gen3_uninit_aux, + &aux_device->aux_dev); + if (ret) + return ret; + + ret = auxiliary_device_add(&aux_device->aux_dev); + if (ret) + return ret; + ret = devm_add_action_or_reset(adc->dev, adc5_gen3_delete_aux, + &aux_device->aux_dev); + if (ret) + return ret; + + adc->tm_aux = &aux_device->aux_dev; + + return 0; +} + +void adc5_gen3_mutex_lock(struct device *dev) + __acquires(&adc->lock) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); + struct adc5_chip *adc = iio_priv(indio_dev); + + mutex_lock(&adc->lock); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_mutex_lock, "QCOM_SPMI_ADC5_GEN3"); + +void adc5_gen3_mutex_unlock(struct device *dev) + __releases(&adc->lock) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); + struct adc5_chip *adc = iio_priv(indio_dev); + + mutex_unlock(&adc->lock); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_mutex_unlock, "QCOM_SPMI_ADC5_GEN3"); + +int adc5_gen3_get_scaled_reading(struct device *dev, + struct adc5_channel_common_prop *common_props, + int *val) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); + struct adc5_chip *adc = iio_priv(indio_dev); + u16 adc_code_volt; + int ret; + + ret = adc5_gen3_do_conversion(adc, common_props, &adc_code_volt); + if (ret) + return ret; + + return qcom_adc5_hw_scale(common_props->scale_fn_type, + common_props->prescale, + adc->data, adc_code_volt, val); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_get_scaled_reading, "QCOM_SPMI_ADC5_GEN3"); + +int adc5_gen3_therm_code_to_temp(struct device *dev, + struct adc5_channel_common_prop *common_props, + u16 code, int *val) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); + struct adc5_chip *adc = iio_priv(indio_dev); + + return qcom_adc5_hw_scale(common_props->scale_fn_type, + common_props->prescale, + adc->data, code, val); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_therm_code_to_temp, "QCOM_SPMI_ADC5_GEN3"); + +void adc5_gen3_register_tm_event_notifier(struct device *dev, + void (*handler)(struct auxiliary_device *)) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); + struct adc5_chip *adc = iio_priv(indio_dev); + + adc->handler = handler; +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_register_tm_event_notifier, "QCOM_SPMI_ADC5_GEN3"); + +static int adc5_gen3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct adc5_chip *adc; + struct regmap *regmap; + int ret; + u32 *reg; + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc = iio_priv(indio_dev); + adc->dev_data.regmap = regmap; + adc->dev = dev; + + platform_set_drvdata(pdev, indio_dev); + init_completion(&adc->complete); + ret = devm_mutex_init(dev, &adc->lock); + if (ret) + return ret; + + ret = device_property_count_u32(dev, "reg"); + if (ret < 0) + return ret; + + adc->dev_data.num_sdams = ret; + + reg = devm_kcalloc(dev, adc->dev_data.num_sdams, sizeof(u32), + GFP_KERNEL); + if (!reg) + return -ENOMEM; + + ret = device_property_read_u32_array(dev, "reg", reg, + adc->dev_data.num_sdams); + if (ret) + return dev_err_probe(dev, ret, + "Failed to read reg property\n"); + + adc->dev_data.base = devm_kcalloc(dev, adc->dev_data.num_sdams, + sizeof(*adc->dev_data.base), + GFP_KERNEL); + if (!adc->dev_data.base) + return -ENOMEM; + + for (int i = 0; i < adc->dev_data.num_sdams; i++) { + adc->dev_data.base[i].base_addr = reg[i]; + + ret = platform_get_irq(pdev, i); + if (ret < 0) + return dev_err_probe(dev, ret, + "Getting IRQ %d failed\n", i); + + adc->dev_data.base[i].irq = ret; + + adc->dev_data.base[i].irq_name = devm_kasprintf(dev, GFP_KERNEL, + "sdam%d", i); + if (!adc->dev_data.base[i].irq_name) + return -ENOMEM; + } + + ret = devm_request_irq(dev, adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq, + adc5_gen3_isr, 0, + adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq_name, + adc); + if (ret) + return dev_err_probe(dev, ret, + "Failed to request SDAM%d irq\n", + ADC5_GEN3_VADC_SDAM); + + ret = adc5_get_fw_data(adc); + if (ret) + return ret; + + if (adc->n_tm_channels > 0) { + ret = adc5_gen3_add_aux_tm_device(adc); + if (ret) + dev_err_probe(dev, ret, + "Failed to add auxiliary TM device\n"); + } + + indio_dev->name = "spmi-adc5-gen3"; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &adc5_gen3_info; + indio_dev->channels = adc->iio_chans; + indio_dev->num_channels = adc->nchannels; + + return devm_iio_device_register(dev, indio_dev); +} + +static struct platform_driver adc5_gen3_driver = { + .driver = { + .name = "qcom-spmi-adc5-gen3", + .of_match_table = adc5_match_table, + }, + .probe = adc5_gen3_probe, +}; +module_platform_driver(adc5_gen3_driver); + +MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("QCOM_SPMI_ADC5_GEN3"); diff --git a/include/linux/iio/adc/qcom-adc5-gen3-common.h b/include/linux/iio/adc/qcom-adc5-gen3-common.h new file mode 100644 index 0000000000000..e352733f4a706 --- /dev/null +++ b/include/linux/iio/adc/qcom-adc5-gen3-common.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Code used in the main and auxiliary Qualcomm PMIC voltage ADCs + * of type ADC5 Gen3. + */ + +#ifndef QCOM_ADC5_GEN3_COMMON_H +#define QCOM_ADC5_GEN3_COMMON_H + +#include +#include +#include +#include +#include +#include + +#define ADC5_GEN3_HS 0x45 +#define ADC5_GEN3_HS_BUSY BIT(7) +#define ADC5_GEN3_HS_READY BIT(0) + +#define ADC5_GEN3_STATUS1 0x46 +#define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7) +#define ADC5_GEN3_STATUS1_THR_CROSS BIT(6) +#define ADC5_GEN3_STATUS1_EOC BIT(0) + +#define ADC5_GEN3_TM_EN_STS 0x47 +#define ADC5_GEN3_TM_HIGH_STS 0x48 +#define ADC5_GEN3_TM_LOW_STS 0x49 + +#define ADC5_GEN3_EOC_STS 0x4a +#define ADC5_GEN3_EOC_CHAN_0 BIT(0) + +#define ADC5_GEN3_EOC_CLR 0x4b +#define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c +#define ADC5_GEN3_TM_LOW_STS_CLR 0x4d +#define ADC5_GEN3_CONV_ERR_CLR 0x4e +#define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0) + +#define ADC5_GEN3_SID 0x4f +#define ADC5_GEN3_SID_MASK GENMASK(3, 0) + +#define ADC5_GEN3_PERPH_CH 0x50 +#define ADC5_GEN3_CHAN_CONV_REQ BIT(7) + +#define ADC5_GEN3_TIMER_SEL 0x51 +#define ADC5_GEN3_TIME_IMMEDIATE 0x1 + +#define ADC5_GEN3_DIG_PARAM 0x52 +#define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4) +#define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2) + +#define ADC5_GEN3_FAST_AVG 0x53 +#define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7) +#define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0) + +#define ADC5_GEN3_ADC_CH_SEL_CTL 0x54 +#define ADC5_GEN3_DELAY_CTL 0x55 +#define ADC5_GEN3_HW_SETTLE_DELAY_MASK GENMASK(3, 0) + +#define ADC5_GEN3_CH_EN 0x56 +#define ADC5_GEN3_HIGH_THR_INT_EN BIT(1) +#define ADC5_GEN3_LOW_THR_INT_EN BIT(0) + +#define ADC5_GEN3_LOW_THR0 0x57 +#define ADC5_GEN3_LOW_THR1 0x58 +#define ADC5_GEN3_HIGH_THR0 0x59 +#define ADC5_GEN3_HIGH_THR1 0x5a + +#define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2) +#define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2) + +#define ADC5_GEN3_CONV_REQ 0xe5 +#define ADC5_GEN3_CONV_REQ_REQ BIT(0) + +#define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8) +#define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0) +#define ADC5_GEN3_V_CHAN(x) \ + (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) + +/* ADC channels for PMIC5 Gen3 */ +#define ADC5_GEN3_REF_GND 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_DIE_TEMP 0x03 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f +/* 100k pull-up channels */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +#define ADC5_MAX_CHANNEL 0xc0 + +struct device; + +enum adc5_cal_method { + ADC5_NO_CAL = 0, + ADC5_RATIOMETRIC_CAL, + ADC5_ABSOLUTE_CAL, +}; + +enum adc5_time_select { + MEAS_INT_DISABLE = 0, + MEAS_INT_IMMEDIATE, + MEAS_INT_50MS, + MEAS_INT_100MS, + MEAS_INT_1S, + MEAS_INT_NONE, +}; + +/** + * struct adc5_sdam_data - data per SDAM allocated for adc usage + * @base_addr: base address for the ADC SDAM peripheral. + * @irq_name: ADC IRQ name. + * @irq: ADC IRQ number. + */ +struct adc5_sdam_data { + u16 base_addr; + const char *irq_name; + int irq; +}; + +/** + * struct adc5_device_data - Top-level ADC device data + * @regmap: ADC peripheral register map field. + * @base: array of SDAM data. + * @num_sdams: number of ADC SDAM peripherals. + */ +struct adc5_device_data { + struct regmap *regmap; + struct adc5_sdam_data *base; + int num_sdams; +}; + +/** + * struct adc5_channel_common_prop - ADC channel properties (common to ADC and TM). + * @channel: channel number, refer to the channel list. + * @cal_method: calibration method. + * @decimation: sampling rate supported for the channel. + * @sid: ID of PMIC owning the channel. + * @label: Channel name used in device tree. + * @prescale: channel scaling performed on the input signal. + * @hw_settle_time_us: the time between AMUX being configured and the + * start of conversion in uS. + * @avg_samples: ability to provide single result from the ADC + * that is an average of multiple measurements. + * @scale_fn_type: Represents the scaling function to convert voltage + * physical units desired by the client for the channel. + */ +struct adc5_channel_common_prop { + unsigned int channel; + enum adc5_cal_method cal_method; + unsigned int decimation; + unsigned int sid; + const char *label; + unsigned int prescale; + unsigned int hw_settle_time_us; + unsigned int avg_samples; + enum vadc_scale_fn_type scale_fn_type; +}; + +/** + * struct tm5_aux_dev_wrapper - wrapper structure around TM auxiliary device + * @aux_dev: TM auxiliary device structure. + * @dev_data: Top-level ADC device data. + * @tm_props: Array of common ADC channel properties for TM channels. + * @n_tm_channels: number of TM channels. + */ +struct tm5_aux_dev_wrapper { + struct auxiliary_device aux_dev; + struct adc5_device_data *dev_data; + struct adc5_channel_common_prop *tm_props; + unsigned int n_tm_channels; +}; + +int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len); + +int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len); + +int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc, + unsigned int sdam_index); + +void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, + u8 *data); + +int adc5_gen3_status_clear(struct adc5_device_data *adc, + int sdam_index, u16 offset, u8 *val, int len); + +void adc5_gen3_mutex_lock(struct device *dev); +void adc5_gen3_mutex_unlock(struct device *dev); +int adc5_gen3_get_scaled_reading(struct device *dev, + struct adc5_channel_common_prop *common_props, + int *val); +int adc5_gen3_therm_code_to_temp(struct device *dev, + struct adc5_channel_common_prop *common_props, + u16 code, int *val); +void adc5_gen3_register_tm_event_notifier(struct device *dev, + void (*handler)(struct auxiliary_device *)); + +#endif /* QCOM_ADC5_GEN3_COMMON_H */ From 01f1ca36d419a5a8e3bae4eddd5afa99abdf2688 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 9 Feb 2026 16:24:38 +0530 Subject: [PATCH 0035/1330] FROMLIST: thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Add support for ADC_TM part of PMIC5 Gen3. This is an auxiliary driver under the Gen3 ADC driver, which implements the threshold setting and interrupt generating functionalities of QCOM ADC_TM drivers, used to support thermal trip points. Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/all/20260209105438.596339-5-jishnu.prakash@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash --- drivers/thermal/qcom/Kconfig | 9 + drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 507 ++++++++++++++++++ 3 files changed, 517 insertions(+) create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index a6bb01082ec69..1acb11e4ac800 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -21,6 +21,15 @@ config QCOM_SPMI_ADC_TM5 Thermal client sets threshold temperature for both warm and cool and gets updated when a threshold is reached. +config QCOM_SPMI_ADC_TM5_GEN3 + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3" + depends on QCOM_SPMI_ADC5_GEN3 + help + This enables the auxiliary thermal driver for the ADC5 Gen3 thermal + monitoring device. It shows up as a thermal zone with multiple trip points. + Thermal client sets threshold temperature for both warm and cool and + gets updated when a threshold is reached. + config QCOM_SPMI_TEMP_ALARM tristate "Qualcomm SPMI PMIC Temperature Alarm" depends on OF && SPMI && IIO diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 0fa2512042e78..828d9e7bc7970 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o +obj-$(CONFIG_QCOM_SPMI_ADC_TM5_GEN3) += qcom-spmi-adc-tm5-gen3.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o obj-$(CONFIG_QCOM_LMH) += lmh.o diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c new file mode 100644 index 0000000000000..fde9b073f4826 --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +struct device; +struct adc_tm5_gen3_chip; + +/** + * struct adc_tm5_gen3_channel_props - ADC_TM channel structure + * @timer: time period of recurring TM measurement. + * @tm_chan_index: TM channel number used (ranging from 1-7). + * @sdam_index: SDAM on which this TM channel lies. + * @common_props: structure with common ADC channel properties. + * @high_thr_en: TM high threshold crossing detection enabled. + * @low_thr_en: TM low threshold crossing detection enabled. + * @chip: ADC TM device. + * @tzd: pointer to thermal device corresponding to TM channel. + * @last_temp: last temperature that caused threshold violation, + * or a thermal TM channel. + * @last_temp_set: indicates if last_temp is stored. + */ +struct adc_tm5_gen3_channel_props { + unsigned int timer; + unsigned int tm_chan_index; + unsigned int sdam_index; + struct adc5_channel_common_prop common_props; + bool high_thr_en; + bool low_thr_en; + struct adc_tm5_gen3_chip *chip; + struct thermal_zone_device *tzd; + int last_temp; + bool last_temp_set; +}; + +/** + * struct adc_tm5_gen3_chip - ADC Thermal Monitoring device structure + * @dev_data: Top-level ADC device data. + * @chan_props: Array of ADC_TM channel structures. + * @nchannels: number of TM channels allocated + * @dev: SPMI ADC5 Gen3 device. + * @tm_handler_work: handler for TM interrupt for threshold violation. + */ +struct adc_tm5_gen3_chip { + struct adc5_device_data *dev_data; + struct adc_tm5_gen3_channel_props *chan_props; + unsigned int nchannels; + struct device *dev; + struct work_struct tm_handler_work; +}; + +DEFINE_GUARD(adc5_gen3, struct adc_tm5_gen3_chip *, adc5_gen3_mutex_lock(_T->dev), + adc5_gen3_mutex_unlock(_T->dev)) + +static int get_sdam_from_irq(struct adc_tm5_gen3_chip *adc_tm5, int irq) +{ + for (int i = 0; i < adc_tm5->dev_data->num_sdams; i++) { + if (adc_tm5->dev_data->base[i].irq == irq) + return i; + } + return -ENOENT; +} + +static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id) +{ + struct adc_tm5_gen3_chip *adc_tm5 = dev_id; + int ret, sdam_num; + u8 tm_status[2]; + u8 status, val; + + sdam_num = get_sdam_from_irq(adc_tm5, irq); + if (sdam_num < 0) { + dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", + irq); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, + &status, sizeof(status)); + if (ret) { + dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { + dev_err_ratelimited(adc_tm5->dev, + "Unexpected conversion fault, status:%#x\n", + status); + val = ADC5_GEN3_CONV_ERR_CLR_REQ; + adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, + ADC5_GEN3_CONV_ERR_CLR, &val, 1); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, + tm_status, sizeof(tm_status)); + if (ret) { + dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (tm_status[0] || tm_status[1]) + schedule_work(&adc_tm5->tm_handler_work); + + dev_dbg(adc_tm5->dev, "Interrupt status:%#x, high:%#x, low:%#x\n", + status, tm_status[0], tm_status[1]); + + return IRQ_HANDLED; +} + +static int adc5_gen3_tm_status_check(struct adc_tm5_gen3_chip *adc_tm5, + int sdam_index, u8 *tm_status, u8 *buf) +{ + int ret; + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS, + tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); + return ret; + } + + ret = adc5_gen3_status_clear(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR, + tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc status clear conv_req failed with %d\n", + ret); + return ret; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_CH_DATA0(0), + buf, 16); + if (ret) + dev_err(adc_tm5->dev, "adc read data failed with %d\n", ret); + + return ret; +} + +static void tm_handler_work(struct work_struct *work) +{ + struct adc_tm5_gen3_chip *adc_tm5 = container_of(work, struct adc_tm5_gen3_chip, + tm_handler_work); + int sdam_index = -1; + u8 tm_status[2] = { }; + u8 buf[16] = { }; + + for (int i = 0; i < adc_tm5->nchannels; i++) { + struct adc_tm5_gen3_channel_props *chan_prop = &adc_tm5->chan_props[i]; + int offset = chan_prop->tm_chan_index; + bool upper_set, lower_set; + int ret, temp; + u16 code; + + scoped_guard(adc5_gen3, adc_tm5) { + if (chan_prop->sdam_index != sdam_index) { + sdam_index = chan_prop->sdam_index; + ret = adc5_gen3_tm_status_check(adc_tm5, sdam_index, + tm_status, buf); + if (ret) + return; + } + + upper_set = ((tm_status[0] & BIT(offset)) && chan_prop->high_thr_en); + lower_set = ((tm_status[1] & BIT(offset)) && chan_prop->low_thr_en); + } + + if (!(upper_set || lower_set)) + continue; + + code = get_unaligned_le16(&buf[2 * offset]); + dev_dbg(adc_tm5->dev, "ADC_TM threshold code:%#x\n", code); + + ret = adc5_gen3_therm_code_to_temp(adc_tm5->dev, + &chan_prop->common_props, + code, &temp); + if (ret) { + dev_err(adc_tm5->dev, + "Invalid temperature reading, ret = %d, code=%#x\n", + ret, code); + continue; + } + + chan_prop->last_temp = temp; + chan_prop->last_temp_set = true; + thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED); + } +} + +static int adc_tm5_gen3_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz); + struct adc_tm5_gen3_chip *adc_tm5; + + if (!prop || !prop->chip) + return -EINVAL; + + adc_tm5 = prop->chip; + + if (prop->last_temp_set) { + pr_debug("last_temp: %d\n", prop->last_temp); + prop->last_temp_set = false; + *temp = prop->last_temp; + return 0; + } + + return adc5_gen3_get_scaled_reading(adc_tm5->dev, &prop->common_props, + temp); +} + +static int adc_tm5_gen3_disable_channel(struct adc_tm5_gen3_channel_props *prop) +{ + struct adc_tm5_gen3_chip *adc_tm5 = prop->chip; + int ret; + u8 val; + + prop->high_thr_en = false; + prop->low_thr_en = false; + + ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); + if (ret) + return ret; + + val = BIT(prop->tm_chan_index); + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_TM_HIGH_STS_CLR, &val, sizeof(val)); + if (ret) + return ret; + + val = MEAS_INT_DISABLE; + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_TIMER_SEL, &val, sizeof(val)); + if (ret) + return ret; + + /* To indicate there is an actual conversion request */ + val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_PERPH_CH, &val, sizeof(val)); + if (ret) + return ret; + + val = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_CONV_REQ, &val, sizeof(val)); +} + +#define ADC_TM5_GEN3_CONFIG_REGS 12 + +static int adc_tm5_gen3_configure(struct adc_tm5_gen3_channel_props *prop, + int low_temp, int high_temp) +{ + struct adc_tm5_gen3_chip *adc_tm5 = prop->chip; + u8 buf[ADC_TM5_GEN3_CONFIG_REGS]; + u8 conv_req; + u16 adc_code; + int ret; + + ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); + if (ret < 0) + return ret; + + ret = adc5_gen3_read(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + /* Write SID */ + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->common_props.sid); + + /* Select TM channel and indicate there is an actual conversion request */ + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + + buf[2] = prop->timer; + + /* Digital param selection */ + adc5_gen3_update_dig_param(&prop->common_props, &buf[3]); + + /* Update fast average sample value */ + buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK; + buf[4] |= prop->common_props.avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] = prop->common_props.channel; + + /* Select HW settle delay for channel */ + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, + prop->common_props.hw_settle_time_us); + + /* High temperature corresponds to low voltage threshold */ + prop->low_thr_en = (high_temp != INT_MAX); + if (prop->low_thr_en) { + adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp); + put_unaligned_le16(adc_code, &buf[8]); + } + + /* Low temperature corresponds to high voltage threshold */ + prop->high_thr_en = (low_temp != -INT_MAX); + if (prop->high_thr_en) { + adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp); + put_unaligned_le16(adc_code, &buf[10]); + } + + buf[7] = 0; + if (prop->high_thr_en) + buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN; + if (prop->low_thr_en) + buf[7] |= ADC5_GEN3_LOW_THR_INT_EN; + + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_SID, + buf, sizeof(buf)); + if (ret < 0) + return ret; + + conv_req = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_CONV_REQ, &conv_req, sizeof(conv_req)); +} + +static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz, + int low_temp, int high_temp) +{ + struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz); + struct adc_tm5_gen3_chip *adc_tm5; + + if (!prop || !prop->chip) + return -EINVAL; + + adc_tm5 = prop->chip; + + dev_dbg(adc_tm5->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n", + prop->common_props.label, low_temp, high_temp); + + guard(adc5_gen3)(adc_tm5); + if (high_temp == INT_MAX && low_temp == -INT_MAX) + return adc_tm5_gen3_disable_channel(prop); + + return adc_tm5_gen3_configure(prop, low_temp, high_temp); +} + +static const struct thermal_zone_device_ops adc_tm_ops = { + .get_temp = adc_tm5_gen3_get_temp, + .set_trips = adc_tm5_gen3_set_trip_temp, +}; + +static int adc_tm5_register_tzd(struct adc_tm5_gen3_chip *adc_tm5) +{ + struct thermal_zone_device *tzd; + unsigned int channel; + int ret; + + for (int i = 0; i < adc_tm5->nchannels; i++) { + channel = ADC5_GEN3_V_CHAN(adc_tm5->chan_props[i].common_props); + tzd = devm_thermal_of_zone_register(adc_tm5->dev, channel, + &adc_tm5->chan_props[i], + &adc_tm_ops); + if (IS_ERR(tzd)) { + if (PTR_ERR(tzd) == -ENODEV) { + dev_info(adc_tm5->dev, + "thermal sensor on channel %d is not used\n", + channel); + continue; + } + return dev_err_probe(adc_tm5->dev, PTR_ERR(tzd), + "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), channel); + } + adc_tm5->chan_props[i].tzd = tzd; + ret = devm_thermal_add_hwmon_sysfs(adc_tm5->dev, tzd); + if (ret) + return ret; + } + return 0; +} + +static void adc5_gen3_clear_work(void *data) +{ + struct adc_tm5_gen3_chip *adc_tm5 = data; + + cancel_work_sync(&adc_tm5->tm_handler_work); +} + +static void adc5_gen3_disable(void *data) +{ + struct adc_tm5_gen3_chip *adc_tm5 = data; + + guard(adc5_gen3)(adc_tm5); + /* Disable all available TM channels */ + for (int i = 0; i < adc_tm5->nchannels; i++) + adc_tm5_gen3_disable_channel(&adc_tm5->chan_props[i]); +} + +static void adctm_event_handler(struct auxiliary_device *adev) +{ + struct adc_tm5_gen3_chip *adc_tm5 = auxiliary_get_drvdata(adev); + + schedule_work(&adc_tm5->tm_handler_work); +} + +static int adc_tm5_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *id) +{ + struct adc_tm5_gen3_chip *adc_tm5; + struct tm5_aux_dev_wrapper *aux_dev_wrapper; + struct device *dev = &aux_dev->dev; + int ret; + + adc_tm5 = devm_kzalloc(dev, sizeof(*adc_tm5), GFP_KERNEL); + if (!adc_tm5) + return -ENOMEM; + + aux_dev_wrapper = container_of(aux_dev, struct tm5_aux_dev_wrapper, + aux_dev); + + adc_tm5->dev = dev; + adc_tm5->dev_data = aux_dev_wrapper->dev_data; + adc_tm5->nchannels = aux_dev_wrapper->n_tm_channels; + adc_tm5->chan_props = devm_kcalloc(dev, aux_dev_wrapper->n_tm_channels, + sizeof(*adc_tm5->chan_props), GFP_KERNEL); + if (!adc_tm5->chan_props) + return -ENOMEM; + + for (int i = 0; i < adc_tm5->nchannels; i++) { + adc_tm5->chan_props[i].common_props = aux_dev_wrapper->tm_props[i]; + adc_tm5->chan_props[i].timer = MEAS_INT_1S; + adc_tm5->chan_props[i].sdam_index = (i + 1) / 8; + adc_tm5->chan_props[i].tm_chan_index = (i + 1) % 8; + adc_tm5->chan_props[i].chip = adc_tm5; + } + + INIT_WORK(&adc_tm5->tm_handler_work, tm_handler_work); + + /* + * Skipping first SDAM IRQ as it is requested in parent driver. + * If there is a TM violation on that IRQ, the parent driver calls + * the notifier (adctm_event_handler) exposed from this driver to handle it. + */ + for (int i = 1; i < adc_tm5->dev_data->num_sdams; i++) { + ret = devm_request_threaded_irq(dev, + adc_tm5->dev_data->base[i].irq, + NULL, adctm5_gen3_isr, IRQF_ONESHOT, + adc_tm5->dev_data->base[i].irq_name, + adc_tm5); + if (ret < 0) + return ret; + } + + /* + * This drvdata is only used in the function (adctm_event_handler) + * called by parent ADC driver in case of TM violation on the first SDAM. + */ + auxiliary_set_drvdata(aux_dev, adc_tm5); + + adc5_gen3_register_tm_event_notifier(dev, adctm_event_handler); + + /* + * This is to cancel any instances of tm_handler_work scheduled by + * TM interrupt, at the time of module removal. + */ + ret = devm_add_action(dev, adc5_gen3_clear_work, adc_tm5); + if (ret) + return ret; + + ret = adc_tm5_register_tzd(adc_tm5); + if (ret) + return ret; + + /* This is to disable all ADC_TM channels in case of probe failure. */ + + return devm_add_action(dev, adc5_gen3_disable, adc_tm5); +} + +static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = { + { .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3", }, + { } +}; + +MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table); + +static struct auxiliary_driver adctm5gen3_auxiliary_driver = { + .id_table = adctm5_auxiliary_id_table, + .probe = adc_tm5_probe, +}; + +module_auxiliary_driver(adctm5gen3_auxiliary_driver); + +MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("QCOM_SPMI_ADC5_GEN3"); From dc3f93d9efb4e1b782f74e3eb8582c5114c75bc0 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Fri, 17 Oct 2025 19:46:22 +0530 Subject: [PATCH 0036/1330] FROMLIST: media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Kaanapali SOC brings in the new generation of video IP i.e iris4. When compared to previous generation, iris3x, it has, - separate power domains for stream and pixel processing hardware blocks (bse and vpp). - additional power domain for apv codec. - power domains for individual pipes (VPPx). - different clocks and reset lines. Iommus include all the different stream-ids which can be possibly generated by vpu4 video hardware in both secure and non secure execution mode. The vpu have reserved iova, i.e some portion of the addressable range is reserved for IO registers. Iris_resv would describe the acceptable address range. Link: https://lore.kernel.org/linux-media/20251017-knp_video-v2-1-f568ce1a4be3@oss.qualcomm.com/ Signed-off-by: Vikash Garodia --- .../bindings/media/qcom,kaanapali-iris.yaml | 231 ++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml new file mode 100644 index 0000000000000..39e9ac9dad221 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml @@ -0,0 +1,231 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Iris video encoder and decoder + +maintainers: + - Vikash Garodia + - Dikshita Agarwal + +description: + The iris video processing unit is a video encode and decode accelerator + present on Qualcomm Kaanapali SoC. + +properties: + compatible: + const: qcom,kaanapali-iris + + reg: + maxItems: 1 + + clocks: + maxItems: 10 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + - const: iface1 + - const: core_freerun + - const: vcodec0_core_freerun + - const: vcodec_bse + - const: vcodec_vpp0 + - const: vcodec_vpp1 + - const: vcodec_apv + + dma-coherent: true + + firmware-name: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + interrupts: + maxItems: 1 + + iommus: + minItems: 3 + maxItems: 8 + + memory-region: + minItems: 1 + maxItems: 2 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 7 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + - const: vpp0 + - const: vpp1 + - const: apv + + resets: + maxItems: 4 + + reset-names: + items: + - const: bus0 + - const: bus1 + - const: core_freerun_reset + - const: vcodec0_core_freerun_reset + +required: + - compatible + - reg + - clocks + - clock-names + - dma-coherent + - interconnects + - interconnect-names + - interrupts + - iommus + - power-domains + - power-domain-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + video-codec@2000000 { + compatible = "qcom,kaanapali-iris"; + reg = <0x02000000 0xf0000>; + + clocks = <&gcc_video_axi0_clk>, + <&video_cc_mvs0c_clk>, + <&video_cc_mvs0_clk>, + <&gcc_video_axi1_clk>, + <&video_cc_mvs0c_freerun_clk>, + <&video_cc_mvs0_freerun_clk>, + <&video_cc_mvs0b_clk>, + <&video_cc_mvs0_vpp0_clk>, + <&video_cc_mvs0_vpp1_clk>, + <&video_cc_mvs0a_clk>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun", + "vcodec_bse", + "vcodec_vpp0", + "vcodec_vpp1", + "vcodec_apv"; + + dma-coherent; + + interconnects = <&gem_noc_master_appss_proc &config_noc_slave_venus_cfg>, + <&mmss_noc_master_video_mvp &mc_virt_slave_ebi1>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = ; + + iommus = <&apps_smmu 0x1940 0x0>, + <&apps_smmu 0x1944 0x0>, + <&apps_smmu 0x1a20 0x0>, + <&apps_smmu 0x1943 0x0>; + + operating-points-v2 = <&iris_opp_table>; + + memory-region = <&video_mem>, <&iris_resv>; + + power-domains = <&video_cc_mvs0c_gdsc>, + <&video_cc_mvs0_gdsc>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&video_cc_mvs0_vpp0_gdsc>, + <&video_cc_mvs0_vpp1_gdsc>, + <&video_cc_mvs0a_gdsc>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx", + "vpp0", + "vpp1", + "apv"; + + resets = <&gcc_video_axi0_clk_ares>, + <&gcc_video_axi1_clk_ares>, + <&video_cc_mvs0c_freerun_clk_ares>, + <&video_cc_mvs0_freerun_clk_ares>; + reset-names = "bus0", + "bus1", + "core_freerun_reset", + "vcodec0_core_freerun_reset"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 240000000 240000000 360000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000 338000000 338000000 507000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000 420000000 420000000 630000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000 444000000 444000000 666000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-533000000 { + opp-hz = /bits/ 64 <533000000 533000000 533000000 800000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000 630000000 630000000 1104000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000 630000000 630000000 1260000000>; + required-opps = <&rpmhpd_opp_turbo_l0>, + <&rpmhpd_opp_turbo_l0>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000 630000000 850000000 1260000000>; + required-opps = <&rpmhpd_opp_turbo_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; From d374ed0c136ad88e8f67363fa4b7207f3b2035e9 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Fri, 17 Oct 2025 19:46:29 +0530 Subject: [PATCH 0037/1330] FROMLIST: media: iris: Add platform data for kaanapali Add support for the kaanapali platform by re-using the SM8550 definitions and using the vpu4 ops. Move the configurations that differs in a per-SoC platform header, that will contain SoC specific data. Link: https://lore.kernel.org/all/20251017-knp_video-v2-8-f568ce1a4be3@oss.qualcomm.com/ Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Reviewed-by: Bryan O'Donoghue --- .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_gen2.c | 88 +++++++++++++++++++ .../qcom/iris/iris_platform_kaanapali.h | 63 +++++++++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + 4 files changed, 156 insertions(+) create mode 100644 drivers/media/platform/qcom/iris/iris_platform_kaanapali.h diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 5a489917580eb..8c1ad8ae46025 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -41,6 +41,7 @@ enum pipe_type { PIPE_4 = 4, }; +extern const struct iris_platform_data kaanapali_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 5da90d47f9c6e..e0c99d28762cd 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -12,6 +12,7 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" +#include "iris_platform_kaanapali.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" @@ -921,6 +922,93 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { BUF_SCRATCH_2, }; +const struct iris_platform_data kaanapali_data = { + .get_instance = iris_hfi_gen2_get_instance, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .get_vpu_buffer_size = iris_vpu4x_buf_size, + .vpu_ops = &iris_vpu4x_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = kaanapali_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = kaanapali_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = kaanapali_clk_table, + .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), + .opp_clk_tbl = kaanapali_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu40_p2_s7.mbn", + .pas_id = IRIS_PAS_ID, + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), + .tz_cp_config_data = tz_cp_config_kaanapali, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), + .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 2, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4352) / 256) * 60, + .dec_input_config_params_default = + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc = + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 = + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_output_config_params = + sm8550_vdec_output_config_params, + .dec_output_config_params_size = + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params = + sm8550_venc_input_config_params, + .enc_input_config_params_size = + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params = + sm8550_venc_output_config_params, + .enc_output_config_params_size = + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop = sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), +}; + const struct iris_platform_data sm8550_data = { .get_instance = iris_hfi_gen2_get_instance, .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h new file mode 100644 index 0000000000000..247fb9d7cb632 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_KAANAPALI_H__ +#define __IRIS_PLATFORM_KAANAPALI_H__ + +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + +static const char *const kaanapali_clk_reset_table[] = { + "bus0", + "bus1", + "core_freerun_reset", + "vcodec0_core_freerun_reset", +}; + +static const char *const kaanapali_pmdomain_table[] = { + "venus", + "vcodec0", + "vpp0", + "vpp1", + "apv", +}; + +static const struct platform_clk_data kaanapali_clk_table[] = { + { IRIS_AXI_CLK, "iface" }, + { IRIS_CTRL_CLK, "core" }, + { IRIS_HW_CLK, "vcodec0_core" }, + { IRIS_AXI1_CLK, "iface1" }, + { IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, + { IRIS_BSE_HW_CLK, "vcodec_bse" }, + { IRIS_VPP0_HW_CLK, "vcodec_vpp0" }, + { IRIS_VPP1_HW_CLK, "vcodec_vpp1" }, + { IRIS_APV_HW_CLK, "vcodec_apv" }, +}; + +static const char *const kaanapali_opp_clk_table[] = { + "vcodec0_core", + "vcodec_apv", + "vcodec_bse", + "core", + NULL, +}; + +static struct tz_cp_config tz_cp_config_kaanapali[] = { + { + .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x01000000, + .cp_nonpixel_size = 0x24800000, + }, + { + .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x25800000, + .cp_nonpixel_size = 0xda400000, + }, +}; + +#endif /* __IRIS_PLATFORM_KAANAPALI_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index ddaacda523ecb..a27a23b960bdf 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -348,6 +348,10 @@ static const struct dev_pm_ops iris_pm_ops = { }; static const struct of_device_id iris_dt_match[] = { + { + .compatible = "qcom,kaanapali-iris", + .data = &kaanapali_data, + }, { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, From f4b663ff985fd81e9b9fa83601affaa95b1a2de5 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 11 Feb 2026 12:19:16 +0530 Subject: [PATCH 0038/1330] FROMLIST: media: iris: Enable Secure PAS support with IOMMU managed by Linux Most Qualcomm platforms feature a inhouse hypervisor (such as Gunyah or QHEE), which typically handles IOMMU configuration. This includes mapping memory regions and device memory resources for remote processors by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are later removed during teardown. Additionally, SHM bridge setup is required to enable memory protection for both remoteproc metadata and its memory regions. When the hypervisor is absent, the operating system must perform these configurations instead. Support for handling IOMMU and SHM setup in the absence of a hypervisor is now in place. Extend the Iris driver to enable this functionality on platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). Additionally, the Iris driver must map the firmware and its required resources to the firmware SID, which is now specified via the device tree. Link: https://lore.kernel.org/lkml/20250819165447.4149674-12-mukesh.ojha@oss.qualcomm.com/ Signed-off-by: Vikash Garodia Signed-off-by: Mukesh Ojha --- drivers/media/platform/qcom/iris/iris_core.c | 9 +- drivers/media/platform/qcom/iris/iris_core.h | 5 + .../media/platform/qcom/iris/iris_firmware.c | 127 ++++++++++++++++-- .../media/platform/qcom/iris/iris_firmware.h | 2 + 4 files changed, 133 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c index dbaac01eb15a0..7a901a310e757 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -18,6 +18,7 @@ void iris_core_deinit(struct iris_core *core) if (core->state != IRIS_CORE_DEINIT) { iris_fw_unload(core); iris_vpu_power_off(core); + iris_fw_deinit(core); iris_hfi_queues_deinit(core); core->state = IRIS_CORE_DEINIT; } @@ -67,10 +68,14 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_queue_deinit; - ret = iris_fw_load(core); + ret = iris_fw_init(core); if (ret) goto error_power_off; + ret = iris_fw_load(core); + if (ret) + goto error_firmware_deinit; + ret = iris_vpu_boot_firmware(core); if (ret) goto error_unload_fw; @@ -89,6 +94,8 @@ int iris_core_init(struct iris_core *core) error_unload_fw: iris_fw_unload(core); +error_firmware_deinit: + iris_fw_deinit(core); error_power_off: iris_vpu_power_off(core); error_queue_deinit: diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index fb194c967ad4f..ef081ccc3429d 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -82,6 +82,11 @@ struct iris_core { struct v4l2_device v4l2_dev; struct video_device *vdev_dec; struct video_device *vdev_enc; + struct video_firmware { + struct device *dev; + struct qcom_scm_pas_context *ctx; + struct iommu_domain *iommu_domain; + } fw; const struct v4l2_file_operations *iris_v4l2_file_ops; const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops_dec; const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops_enc; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index 5f408024e967f..d74a5aed291d7 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -3,10 +3,15 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include +#include +#include #include +#include #include +#include #include #include "iris_core.h" @@ -17,6 +22,7 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) { u32 pas_id = core->iris_platform_data->pas_id; + struct qcom_scm_pas_context *ctx; const struct firmware *firmware = NULL; struct device *dev = core->dev; struct resource res; @@ -36,6 +42,14 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) mem_phys = res.start; res_size = resource_size(&res); + dev = core->fw.dev ? : core->dev; + + ctx = devm_qcom_scm_pas_context_alloc(dev, pas_id, mem_phys, res_size); + if (!ctx) + return -ENOMEM; + + ctx->use_tzmem = core->fw.dev; + ret = request_firmware(&firmware, fw_name, dev); if (ret) return ret; @@ -52,9 +66,29 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) goto err_release_fw; } - ret = qcom_mdt_load(dev, firmware, fw_name, - pas_id, mem_virt, mem_phys, res_size, NULL); + ret = qcom_mdt_pas_load(ctx, firmware, fw_name, mem_virt, NULL); + qcom_scm_pas_metadata_release(ctx); + if (ret) + goto err_mem_unmap; + + if (core->fw.iommu_domain) { + ret = iommu_map(core->fw.iommu_domain, 0, mem_phys, res_size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + if (ret) + goto err_mem_unmap; + } + ret = qcom_scm_pas_prepare_and_auth_reset(ctx); + if (ret) + goto err_iommu_unmap; + + core->fw.ctx = ctx; + + return ret; + +err_iommu_unmap: + iommu_unmap(core->fw.iommu_domain, 0, res_size); +err_mem_unmap: memunmap(mem_virt); err_release_fw: release_firmware(firmware); @@ -79,12 +113,6 @@ int iris_fw_load(struct iris_core *core) return -ENOMEM; } - ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id); - if (ret) { - dev_err(core->dev, "auth and reset failed: %d\n", ret); - return ret; - } - for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { cp_config = &core->iris_platform_data->tz_cp_config_data[i]; ret = qcom_scm_mem_protect_video_var(cp_config->cp_start, @@ -103,10 +131,91 @@ int iris_fw_load(struct iris_core *core) int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + struct qcom_scm_pas_context *ctx = core->fw.ctx; + int ret; + + if (!ctx) + return -EINVAL; + + ret = qcom_scm_pas_shutdown(ctx->pas_id); + if (core->fw.iommu_domain) + iommu_unmap(core->fw.iommu_domain, 0, ctx->mem_size); + + core->fw.ctx = NULL; + return ret; } int iris_set_hw_state(struct iris_core *core, bool resume) { return qcom_scm_set_remote_state(resume, 0); } + +int iris_fw_init(struct iris_core *core) +{ + struct platform_device_info info; + struct iommu_domain *iommu_dom; + struct platform_device *pdev; + struct device_node *np; + int ret; + + np = of_get_child_by_name(core->dev->of_node, "video-firmware"); + if (!np) + return 0; + + memset(&info, 0, sizeof(info)); + info.fwnode = &np->fwnode; + info.parent = core->dev; + info.name = np->name; + info.dma_mask = DMA_BIT_MASK(32); + + pdev = platform_device_register_full(&info); + if (IS_ERR(pdev)) { + of_node_put(np); + return PTR_ERR(pdev); + } + + pdev->dev.of_node = np; + + ret = of_dma_configure(&pdev->dev, np, true); + if (ret) + goto err_unregister; + + core->fw.dev = &pdev->dev; + + iommu_dom = iommu_get_domain_for_dev(core->fw.dev); + if (!iommu_dom) { + ret = -EINVAL; + goto err_unset_fw_dev; + } + + ret = iommu_attach_device(iommu_dom, core->fw.dev); + if (ret) + goto err_unset_fw_dev; + + core->fw.iommu_domain = iommu_dom; + + of_node_put(np); + + return 0; + +err_unset_fw_dev: + core->fw.dev = NULL; +err_unregister: + platform_device_unregister(pdev); + of_node_put(np); + return ret; +} + +void iris_fw_deinit(struct iris_core *core) +{ + if (!core->fw.dev) + return; + + if (core->fw.iommu_domain) { + iommu_detach_device(core->fw.iommu_domain, core->fw.dev); + core->fw.iommu_domain = NULL; + } + + platform_device_unregister(to_platform_device(core->fw.dev)); + core->fw.dev = NULL; +} diff --git a/drivers/media/platform/qcom/iris/iris_firmware.h b/drivers/media/platform/qcom/iris/iris_firmware.h index e833ecd348871..adde461099667 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.h +++ b/drivers/media/platform/qcom/iris/iris_firmware.h @@ -11,5 +11,7 @@ struct iris_core; int iris_fw_load(struct iris_core *core); int iris_fw_unload(struct iris_core *core); int iris_set_hw_state(struct iris_core *core, bool resume); +int iris_fw_init(struct iris_core *core); +void iris_fw_deinit(struct iris_core *core); #endif From cdb37376c570593fad54bb86bc8a46f52a99ac7a Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Thu, 22 Jan 2026 18:48:53 +0800 Subject: [PATCH 0039/1330] FROMLIST: dt-bindings: i2c: qcom-cci: Document sm6150 compatible Add the sm6150 CCI device string compatible. Link: https://lore.kernel.org/all/20260122-sm6150_evk-v5-2-039b170450a3@oss.qualcomm.com/ Reviewed-by: Vladimir Zapolskiy Signed-off-by: Wenmeng Liu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Loic Poulain --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 399a09409e071..35d3a0685ac44 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -34,6 +34,7 @@ properties: - qcom,sc8280xp-cci - qcom,sdm670-cci - qcom,sdm845-cci + - qcom,sm6150-cci - qcom,sm6350-cci - qcom,sm8250-cci - qcom,sm8450-cci @@ -251,6 +252,7 @@ allOf: contains: enum: - qcom,sa8775p-cci + - qcom,sm6150-cci - qcom,sm8550-cci - qcom,sm8650-cci - qcom,x1e80100-cci From 7b4237eec9916e40ebd486f89022077ad511f1d3 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 23 Jan 2026 17:19:56 +0800 Subject: [PATCH 0040/1330] FROMLIST: media: i2c: imx412: Extend the power-on waiting time MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Arducam IMX577 module requires a longer reset time than the 1000µs configured in the current driver. Increase the wait time after power-on to ensure proper initialization. Link: https://lore.kernel.org/all/20260123-imx412-v7-2-e58303f2b76b@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu --- drivers/media/i2c/imx412.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/imx412.c b/drivers/media/i2c/imx412.c index aa63dfc349181..e25e0a9ff65c3 100644 --- a/drivers/media/i2c/imx412.c +++ b/drivers/media/i2c/imx412.c @@ -1037,7 +1037,11 @@ static int imx412_power_on(struct device *dev) goto error_reset; } - usleep_range(1000, 1200); + /* + * Certain Arducam IMX577 module variants require a longer reset settle + * time. Increasing the delay from 1ms to 10ms ensures reliable startup. + */ + usleep_range(10000, 12000); return 0; From a026ea16f8ed2251d4af7c8c4848fa148ae7d66e Mon Sep 17 00:00:00 2001 From: Song Xue Date: Mon, 22 Sep 2025 19:10:24 +0530 Subject: [PATCH 0041/1330] FROMLIST: arm64: dts: qcom: qcs615-ride: Add PSCI SYSTEM_RESET2 types Add support for SYSTEM_RESET2 vendor-specific resets in qcs615-ride as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/all/20251015-arm-psci-system_reset2-vendor-reboots-v16-14-b98aedaa23ee@oss.qualcomm.com/ Signed-off-by: Song Xue Signed-off-by: Shivendra Pratap --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 7 +++++++ arch/arm64/boot/dts/qcom/talos.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 5a24c19c415e3..c425dc9c2ef3d 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -516,6 +516,13 @@ status = "okay"; }; +&psci { + reboot-mode { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 6dab0d5dcbb8a..9a7b5dd24b2c9 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -559,7 +559,7 @@ interrupts = ; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; From 011fb17317519d96aaa645c1bf7a9d0eef1dea2d Mon Sep 17 00:00:00 2001 From: Qingqing Zhou Date: Wed, 21 Jan 2026 03:35:52 +0530 Subject: [PATCH 0042/1330] FROMLIST: arm64: dts: qcom: talos: add the GPU SMMU node Add the Adreno GPU SMMU node for Talos chipset. Signed-off-by: Qingqing Zhou Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260121-qcs615-spin-2-v7-1-52419b263e92@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/talos.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 9a7b5dd24b2c9..abcf1e2dd0c37 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1846,6 +1846,31 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@50a0000 { + compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x050a0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + power-domains = <&gpucc CX_GDSC>; + dma-coherent; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>, From 64dffe4f59a2acf759a6dbd9bae860930f324631 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Wed, 21 Jan 2026 03:35:53 +0530 Subject: [PATCH 0043/1330] FROMLIST: arm64: dts: qcom: talos: Add gpu and rgmu nodes Add gpu and rgmu nodes for Talos chipset. Signed-off-by: Jie Zhang Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/20260121-qcs615-spin-2-v7-2-52419b263e92@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/talos.dtsi | 110 ++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index abcf1e2dd0c37..3551ace70123f 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -651,6 +651,11 @@ reg = <0x0 0x95900000 0x0 0x1e00000>; no-map; }; + + pil_gpu_mem: pil-gpu@97715000 { + reg = <0x0 0x97715000 0x0 0x2000>; + no-map; + }; }; soc: soc@0 { @@ -1833,6 +1838,111 @@ }; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-612.0", "qcom,adreno"; + reg = <0x0 0x05000000 0x0 0x40000>, + <0x0 0x0509e000 0x0 0x1000>, + <0x0 0x05061000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>; + clock-names = "core"; + + interrupts = ; + + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0x0 0x401>; + + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + qcom,gmu = <&gmu>; + + #cooling-cells = <2>; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + required-opps = <&rpmhpd_opp_turbo>; + opp-peak-kBps = <7050000>; + }; + + opp-745000000 { + opp-hz = /bits/ 64 <745000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + opp-peak-kBps = <6075000>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5287500>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <3975000>; + }; + + opp-435000000 { + opp-hz = /bits/ 64 <435000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3000000>; + }; + }; + }; + + gmu: gmu@506a000 { + compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; + reg = <0x0 0x0506d000 0x0 0x2c000>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "smmu_vote"; + + power-domains = <&gpucc CX_GDSC>, + <&gpucc GX_GDSC>; + power-domain-names = "cx", + "gx"; + + interrupts = , + ; + interrupt-names = "oob", + "gmu"; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,qcs615-gpucc"; reg = <0 0x05090000 0 0x9000>; From 2d18a49f891448e7f6a033b7ca27904cbe7140a3 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Wed, 21 Jan 2026 03:35:54 +0530 Subject: [PATCH 0044/1330] FROMLIST: arm64: dts: qcom: talos: Add GPU cooling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when it reaches 105°C. Signed-off-by: Gaurav Kohli Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/20260121-qcs615-spin-2-v7-3-52419b263e92@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/talos.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 3551ace70123f..8cd5aa68c79c7 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -4971,12 +4972,25 @@ thermal-sensors = <&tsens0 9>; trips { + gpu_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; q6-hvx-thermal { From c4fd569fb1df9e2a8448bc295bcc1009c4c8bd2e Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Wed, 21 Jan 2026 03:35:55 +0530 Subject: [PATCH 0045/1330] FROMLIST: arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Enable GPU for qcs615-ride platform and provide path for zap shader. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260121-qcs615-spin-2-v7-4-52419b263e92@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index c425dc9c2ef3d..f061ae156e0c6 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -372,6 +372,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs615/a612_zap.mbn"; +}; + &i2c2 { clock-frequency = <400000>; status = "okay"; From c61da9a608b2d73debaf6f8aeb7c853d6f4c2ad0 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 23 Dec 2025 18:02:25 +0530 Subject: [PATCH 0046/1330] FROMLIST: arm64: dts: qcom: Enable cdsp qmi tmd devices for talos Enable cdsp cooling devices and thermal zone cooling map bindings for cdsp. Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20251223123227.1317244-7-gaurav.kohli@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/talos.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 8cd5aa68c79c7..bffd45ddab885 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -3693,6 +3693,14 @@ }; }; }; + + cooling { + compatible = "qcom,qmi-cooling-cdsp"; + cdsp_sw: cdsp_sw { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; }; pmu@90b6300 { @@ -4997,12 +5005,26 @@ thermal-sensors = <&tsens0 10>; trips { + q6_hvx_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + q6-hvx-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&q6_hvx_alert0>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; mdm-core-thermal { From 9518672e7434f1741f2154387996bbc750ed5219 Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 28 Dec 2025 22:50:28 +0530 Subject: [PATCH 0047/1330] FROMLIST: arm64: dts: qcom: talos: Add psci reboot-modes Add PSCI SYSTEM_RESET2 reboot-modes for talos based boards, for use by the psci_reboot_mode driver. The following modes are defined: - bootloader: reboot into fastboot mode for fastboot flashing. - edl: reboot into emergency download mode for image loading via the Firehose protocol. Support for these modes is firmware dependent. Signed-off-by: Song Xue Signed-off-by: Shivendra Pratap Signed-off-by: Xin Liu Link: https://lore.kernel.org/all/20251228-arm-psci-system_reset2-vendor-reboots-v19-10-ebb956053098@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/talos.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index bffd45ddab885..4ac3f60820006 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -618,6 +618,11 @@ &cluster_sleep_1 &cluster_sleep_2>; }; + + reboot-mode { + mode-bootloader = <0x80010001 0x2>; + mode-edl = <0x80000000 0x1>; + }; }; reserved-memory { From c47c38989d8fde8eab93c089c8f003c88124f324 Mon Sep 17 00:00:00 2001 From: Sudarshan Shetty Date: Wed, 14 Jan 2026 15:30:41 +0530 Subject: [PATCH 0048/1330] FROMLIST: dt-bindings: arm: qcom: talos-evk: Add QCS615 Talos EVK SMARC platform Add binding support for the Qualcomm Technologies, Inc. Talos EVK SMARC platform based on the QCS615 SoC. Link: https://lore.kernel.org/all/20260217103749.1249718-2-tessolveupstream@gmail.com/ Acked-by: Krzysztof Kozlowski Signed-off-by: Sudarshan Shetty Signed-off-by: Jie Gan --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index bdcf162d3f2d2..19e9469235e0e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -883,6 +883,7 @@ properties: - items: - enum: - qcom,qcs615-ride + - qcom,talos-evk - const: qcom,qcs615 - const: qcom,sm6150 From 3c180d313c1319c364efa31b0f0a6d05dc5bcffd Mon Sep 17 00:00:00 2001 From: Sudarshan Shetty Date: Tue, 17 Feb 2026 16:07:48 +0530 Subject: [PATCH 0049/1330] FROMLOST: arm64: dts: qcom: talos/qcs615-ride: Fix inconsistent USB PHY node naming The USB PHY nodes has inconsistent labels as 'usb_1_hsphy' and 'usb_hsphy_2' across talos.dtsi and qcs615-ride.dts. This patch renames them to follow a consistent naming scheme. No functional changes, only label renaming. Link: https://lore.kernel.org/all/20260217103749.1249718-3-tessolveupstream@gmail.com/ Reviewed-by: Dmitry Baryshkov Signed-off-by: Sudarshan Shetty --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index f061ae156e0c6..e5ce9a4faa9cb 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -677,7 +677,7 @@ dr_mode = "peripheral"; }; -&usb_hsphy_2 { +&usb_2_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; vdda-phy-dpdm-supply = <&vreg_l13a>; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 4ac3f60820006..b44e1a08e235d 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -4569,7 +4569,7 @@ status = "disabled"; }; - usb_hsphy_2: phy@88e3000 { + usb_2_hsphy: phy@88e3000 { compatible = "qcom,qcs615-qusb2-phy"; reg = <0x0 0x088e3000 0x0 0x180>; @@ -4752,7 +4752,7 @@ iommus = <&apps_smmu 0xe0 0x0>; interrupts = ; - phys = <&usb_hsphy_2>; + phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; snps,dis_u2_susphy_quirk; From d70d3b4bcdbe60361264e127549f2095dc8254d9 Mon Sep 17 00:00:00 2001 From: Sudarshan Shetty Date: Tue, 17 Feb 2026 16:07:49 +0530 Subject: [PATCH 0050/1330] FROMLIST: arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board Add the device tree for the QCS615-based Talos EVK platform. The platform is composed of a System-on-Module following the SMARC standard, and a Carrier Board. The Carrier Board supports several display configurations, HDMI and LVDS. Both configurations use the same base hardware, with the display selection controlled by a DIP switch. Use a DTBO file, talos-evk-lvds-auo,g133han01.dtso, which defines an overlay that disables HDMI and adds LVDS. The DTs file talos-evk can describe the HDMI display configurations. According to the hardware design and vendor guidance, the WiFi PA supplies VDD_PA_A and VDD_PA_B only need to be enabled at the same time as asserting WLAN_EN. On this platform, WiFi enablement is controlled via the WLAN_EN GPIO (GPIO84), which also drives the VDD_PA_A and VDD_PA_B power enables. Remove the VDD_PA_A and VDD_PA_B regulator nodes from the device tree and rely on WLAN_EN to enable WiFi functionality. Add talos-evk-usb1-peripheral.dtso overlay to enable USB0 peripheral (EDL) mode. The base DTS will keep USB0 host-only due to hardware routing through the EDL DIP switch, and the overlay switches the configuration for device-mode operation. The initial device tree includes support for: - CPU and memory - UART - GPIOs - Regulators - PMIC - Early console - AT24MAC602 EEPROM - MCP2515 SPI to CAN - ADV7535 DSI-to-HDMI bridge - DisplayPort interface - SN65DSI84ZXHR DSI-to-LVDS bridge - Wi-Fi/BT Link: https://lore.kernel.org/all/20260217103749.1249718-4-tessolveupstream@gmail.com/ Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Sudarshan Shetty --- arch/arm64/boot/dts/qcom/Makefile | 6 + .../qcom/talos-evk-lvds-auo,g133han01.dtso | 131 ++++ arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 614 ++++++++++++++++++ .../dts/qcom/talos-evk-usb1-peripheral.dtso | 10 + arch/arm64/boot/dts/qcom/talos-evk.dts | 139 ++++ 5 files changed, 900 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-som.dtsi create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso create mode 100644 arch/arm64/boot/dts/qcom/talos-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8c3b4eb02897f..201b3dda2e38c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -348,6 +348,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-evk.dtb +talos-evk-usb1-peripheral-dtbs := talos-evk.dtb talos-evk-usb1-peripheral.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-usb1-peripheral.dtb +talos-evk-lvds-auo,g133han01-dtbs := \ + talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtb x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso b/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso new file mode 100644 index 0000000000000..fc2296e346b83 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +#include + +&{/} { + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>, + <&tlmm 115 GPIO_ACTIVE_HIGH>; + default-on; + }; + + panel-lvds { + compatible = "auo,g133han01"; + power-supply = <&vreg_v3p3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* LVDS A (Odd pixels) */ + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + lvds_panel_out_a: endpoint { + remote-endpoint = <&sn65dsi84_out_a>; + }; + }; + + /* LVDS B (Even pixels) */ + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + lvds_panel_out_b: endpoint { + remote-endpoint = <&sn65dsi84_out_b>; + }; + }; + }; + }; + + vreg_v3p3: regulator-v3p3 { + compatible = "regulator-fixed"; + regulator-name = "vdd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&hdmi_connector { + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + hdmi_bridge: bridge@3d { + status = "disabled"; + }; + + lvds_bridge: bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi84_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + sn65dsi84_out_a: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&lvds_panel_out_a>; + }; + }; + + port@3 { + reg = <3>; + + sn65dsi84_out_b: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&lvds_panel_out_b>; + }; + }; + }; + }; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l11a>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi84_in>; + data-lanes = <0 1 2 3>; +}; + +&tlmm { + lcd_bklt_en: lcd-bklt-en-state { + pins = "gpio115"; + function = "gpio"; + bias-disable; + }; + + lcd_bklt_pwm: lcd-bklt-pwm-state { + pins = "gpio59"; + function = "gpio"; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi new file mode 100644 index 0000000000000..f877a3e5d0b00 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include +#include +#include "talos.dtsi" +#include "pm8150.dtsi" +/ { + aliases { + i2c1 = &i2c1; + i2c5 = &i2c5; + mmc0 = &sdhc_1; + serial0 = &uart0; + serial1 = &uart7; + spi6 = &spi6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + can_osc: can-oscillator { + compatible = "fixed-clock"; + clock-frequency = <20000000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + }; + + regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB2_VBUS"; + gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb2_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + + vreg_conn_1p8: regulator-conn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + }; + + vreg_conn_pa: regulator-conn-pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8150_gpios 6 GPIO_ACTIVE_HIGH>; + }; + + vreg_v3p3_can: regulator-v3p3-can { + compatible = "regulator-fixed"; + regulator-name = "vreg-v3p3-can"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v5p0_can: regulator-v5p0-can { + compatible = "regulator-fixed"; + regulator-name = "vreg-v5p0-can"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + pinctrl-0 = <&bt_en_state>, <&wlan_en_state>; + pinctrl-names = "default"; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_conn_pa>; + vddaon-supply = <&vreg_s5a>; + vddpmu-supply = <&vreg_conn_1p8>; + vddpmumx-supply = <&vreg_conn_1p8>; + vddpmucx-supply = <&vreg_conn_pa>; + vddrfa0p95-supply = <&vreg_s5a>; + vddrfa1p3-supply = <&vreg_s6a>; + vddrfa1p9-supply = <&vreg_l15a>; + vddpcie1p3-supply = <&vreg_s6a>; + vddpcie1p9-supply = <&vreg_l15a>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s3a: smps3 { + regulator-name = "vreg_s3a"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + regulator-initial-mode = ; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s6a: smps6 { + regulator-name = "vreg_s6a"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1404000>; + regulator-initial-mode = ; + }; + + vreg_l1a: ldo1 { + regulator-name = "vreg_l1a"; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <852000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2a: ldo2 { + regulator-name = "vreg_l2a"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10a: ldo10 { + regulator-name = "vreg_l10a"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11a: ldo11 { + regulator-name = "vreg_l11a"; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12a: ldo12 { + regulator-name = "vreg_l12a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = ; + }; + + vreg_l13a: ldo13 { + regulator-name = "vreg_l13a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15a: ldo15 { + regulator-name = "vreg_l15a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l16a: ldo16 { + regulator-name = "vreg_l16a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17a: ldo17 { + regulator-name = "vreg_l17a"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; + + eeprom@5f { + compatible = "atmel,24mac602"; + reg = <0x5f>; + pagesize = <16>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint = <&dp0_connector_in>; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l11a>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vcca-supply = <&vreg_l5a>; + status = "okay"; +}; + +&pcie { + perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&pcie_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + qcom,calibration-variant = "QC_QCS615_Ride"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pm8150_gpios { + usb2_en: usb2-en-state { + pins = "gpio10"; + function = "normal"; + output-enable; + power-source = <0>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs615/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs615/cdsp.mbn"; + + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + vmmc-supply = <&vreg_l17a>; + vqmmc-supply = <&vreg_s4a>; + + non-removable; + no-sd; + no-sdio; + + status = "okay"; +}; + +&spi6 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&can_osc>; + interrupts-extended = <&tlmm 87 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + vdd-supply = <&vreg_v3p3_can>; + xceiver-supply = <&vreg_v5p0_can>; + }; +}; + +&tlmm { + bt_en_state: bt-en-state { + pins = "gpio85"; + function = "gpio"; + bias-pull-down; + }; + + pcie_default_state: pcie-default-state { + clkreq-pins { + pins = "gpio90"; + function = "pcie_clk_req"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wifi_reg_en_pins_state: wifi-reg-en-pins-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <8>; + output-high; + bias-pull-up; + }; + + wlan_en_state: wlan-en-state { + pins = "gpio84"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + +/* + * USB0 routing and EDL mode: + * + * The USB0 controller’s HS differential pair is switched (manually) + * between the Micro-USB port for EDL/ADB and the on-board USB 3.0 hub. + * + * During EDL (Emergency Download) mode, the HS lines are explicitly + * routed to the Micro-USB port to allow the SoC to enter device mode + * for flashing. + * + * After EDL the switch is normally toggled so the HS lines stay + * connected to the hub’s Type-A downstream ports, leaving no electrical + * path to the Micro-USB connector — therefore USB0 runs host-only in + * normal runtime and device mode must not be advertised. + * + * USB0 is configured host-only in the base device tree; a separate + * device-tree overlay enables the Micro-USB peripheral configuration for + * ADB. For ADB to work during normal runtime the DIP switch SW1 must be + * manually toggled to the off position (reconnecting the HS pair to the + * Micro-USB port). + */ + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&usb_qmpphy_2 { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_s4a>; + vccq2-max-microamp = <600000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso b/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso new file mode 100644 index 0000000000000..2f4630a6ba66e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/qcom/talos-evk.dts new file mode 100644 index 0000000000000..af100e22beeec --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "talos-evk-som.dtsi" + +/ { + model = "Qualcomm QCS615 IQ 615 EVK"; + compatible = "qcom,talos-evk", "qcom,qcs615", "qcom,sm6150"; + chassis-type = "embedded"; + + aliases { + mmc1 = &sdhc_2; + }; + + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + + hpd-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + + hdmi_connector: hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + vreg_v1p8_out: regulator-v1p8-out { + compatible = "regulator-fixed"; + regulator-name = "vreg-v1p8-out"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vreg_v5p0_out>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v3p3_out: regulator-v3p3-out { + compatible = "regulator-fixed"; + regulator-name = "vreg-v3p3-out"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vreg_v5p0_out>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v5p0_out: regulator-v5p0-out { + compatible = "regulator-fixed"; + regulator-name = "vreg-v5p0-out"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + /* Powered by system 20V rail (USBC_VBUS_IN) */ + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + hdmi_bridge: bridge@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + avdd-supply = <&vreg_v1p8_out>; + dvdd-supply = <&vreg_v1p8_out>; + pvdd-supply = <&vreg_v1p8_out>; + a2vdd-supply = <&vreg_v1p8_out>; + v3p3-supply = <&vreg_v3p3_out>; + interrupts-extended = <&tlmm 26 IRQ_TYPE_LEVEL_LOW>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&adv7535_in>; + data-lanes = <0 1 2 3>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <4>; + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l10a>; + vqmmc-supply = <&vreg_s4a>; + + status = "okay"; +}; From b4b7f15ec4f7d7a4ec9d71d55a649bf48d494ad7 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 28 Jan 2026 09:25:34 +0800 Subject: [PATCH 0051/1330] FROMLIST: arm64: dts: qcom: talos: add ETR device Add the TMC ETR device to store collected trace data in DDR memory. Link: https://lore.kernel.org/all/20260128-enable-etr-on-talos-v2-1-ba77063d6b62@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/talos.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index b44e1a08e235d..d42afbc536c15 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -2397,6 +2397,14 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + replicator0_out0: endpoint { + remote-endpoint = <&tmc_etr_in>; + }; + }; + port@1 { reg = <1>; @@ -2431,6 +2439,25 @@ }; }; + tmc@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x06048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x01e0 0x0>; + arm,scatter-gather; + + in-ports { + port { + tmc_etr_in: endpoint { + remote-endpoint = <&replicator0_out0>; + }; + }; + }; + }; + replicator@604a000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0x0 0x0604a000 0x0 0x1000>; From 13ec4700340e58c5af16f59099173a2d85b51193 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Thu, 22 Jan 2026 18:48:52 +0800 Subject: [PATCH 0052/1330] FROMLIST: arm64: dts: qcom: talos: Add camss node Add node for the SM6150 camera subsystem. Link: https://lore.kernel.org/all/20260122-sm6150_evk-v5-1-039b170450a3@oss.qualcomm.com/ Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Signed-off-by: Wenmeng Liu --- arch/arm64/boot/dts/qcom/talos.dtsi | 200 ++++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index d42afbc536c15..fc842c6a303ab 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -3968,6 +3968,206 @@ #power-domain-cells = <1>; }; + camss: isp@acb3000 { + compatible = "qcom,sm6150-camss"; + + reg = <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0ac65000 0x0 0x1000>, + <0x0 0x0ac66000 0x0 0x1000>, + <0x0 0x0ac67000 0x0 0x1000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0ac6f000 0x0 0x3000>, + <0x0 0x0ac42000 0x0 0x5000>, + <0x0 0x0ac48000 0x0 0x1000>, + <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac18000 0x0 0x3000>, + <0x0 0x0ac00000 0x0 0x6000>, + <0x0 0x0ac10000 0x0 0x8000>, + <0x0 0x0ac87000 0x0 0x3000>, + <0x0 0x0ac52000 0x0 0x4000>, + <0x0 0x0ac4e000 0x0 0x4000>, + <0x0 0x0ac6b000 0x0 0x0a00>; + reg-names = "csid0", + "csid1", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite", + "bps", + "camnoc", + "cpas_cdm", + "cpas_top", + "icp_csr", + "icp_qgic", + "icp_sierra", + "ipe0", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_IPE_0_CLK>, + <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_JPEG_CLK>, + <&camcc CAM_CC_LRME_CLK>; + clock-names = "gcc_ahb", + "gcc_axi_hf", + "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "soc_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "bps", + "bps_ahb", + "bps_axi", + "bps_areg", + "icp", + "ipe0", + "ipe0_ahb", + "ipe0_areg", + "ipe0_axi", + "jpeg", + "lrme"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0", + "hf_1", + "sf_mnoc"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite", + "camnoc", + "cdm", + "icp", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + iommus = <&apps_smmu 0x0820 0x40>, + <&apps_smmu 0x0840 0x00>, + <&apps_smmu 0x0860 0x40>, + <&apps_smmu 0x0c00 0x00>, + <&apps_smmu 0x0cc0 0x00>, + <&apps_smmu 0x0c80 0x00>, + <&apps_smmu 0x0ca0 0x00>, + <&apps_smmu 0x0d00 0x00>, + <&apps_smmu 0x0d20 0x00>, + <&apps_smmu 0x0d40 0x00>, + <&apps_smmu 0x0d80 0x20>, + <&apps_smmu 0x0da0 0x20>, + <&apps_smmu 0x0de2 0x00>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>, + <&camcc BPS_GDSC>, + <&camcc IPE_0_GDSC>; + power-domain-names = "ife0", + "ife1", + "top", + "bps", + "ipe"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,qcs615-camcc"; reg = <0 0x0ad00000 0 0x10000>; From 93c191e16a6dcf4a5b211364df8fcf89e4ca2a29 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Thu, 22 Jan 2026 18:48:54 +0800 Subject: [PATCH 0053/1330] FROMLIST: arm64: dts: qcom: talos: Add CCI definitions Qualcomm Talos SoC contains single controller, containing 2 I2C hosts. Link: https://lore.kernel.org/all/20260122-sm6150_evk-v5-3-039b170450a3@oss.qualcomm.com/ Reviewed-by: Vladimir Zapolskiy Signed-off-by: Wenmeng Liu --- arch/arm64/boot/dts/qcom/talos.dtsi | 51 +++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index fc842c6a303ab..b435e6c0837c8 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1567,6 +1567,22 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + cci_i2c0_default: cci-i2c0-default-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci_i2c1_default: cci-i2c1-default-state { + /* SDA, SCL */ + pins = "gpio34", "gpio35"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -3968,6 +3984,41 @@ #power-domain-cells = <1>; }; + cci: cci@ac4a000 { + compatible = "qcom,sm6150-cci", "qcom,msm8996-cci"; + + reg = <0x0 0x0ac4a000 0x0 0x4000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: isp@acb3000 { compatible = "qcom,sm6150-camss"; From 432c3ea5fdb16d1a25a063fc165cd9b69b898eb4 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Thu, 22 Jan 2026 18:48:55 +0800 Subject: [PATCH 0054/1330] FROMLIST: arm64: dts: qcom: talos: Add camera MCLK pinctrl Define pinctrl definitions to enable camera master clocks on Talos. Link: https://lore.kernel.org/all/20260122-sm6150_evk-v5-4-039b170450a3@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Vladimir Zapolskiy Signed-off-by: Wenmeng Liu --- arch/arm64/boot/dts/qcom/talos.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index b435e6c0837c8..94c1e82fd8220 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1567,6 +1567,34 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + cam0_default: cam0-default-state { + pins = "gpio28"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam1_default: cam1-default-state { + pins = "gpio29"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam2_default: cam2-default-state { + pins = "gpio30"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam3_default: cam3-default-state { + pins = "gpio31"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + cci_i2c0_default: cci-i2c0-default-state { /* SDA, SCL */ pins = "gpio32", "gpio33"; From d9a6342746643bc4aa93ef38a0812b01b8e7c6f2 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Thu, 22 Jan 2026 18:48:53 +0800 Subject: [PATCH 0055/1330] FROMLIST: dt-bindings: i2c: qcom-cci: Document sm6150 compatible Add the sm6150 CCI device string compatible. Link: https://lore.kernel.org/all/20260122-sm6150_evk-v5-2-039b170450a3@oss.qualcomm.com/ Reviewed-by: Vladimir Zapolskiy Signed-off-by: Wenmeng Liu From aadcb2f59ee7faa518c2d8df3ad61e0978b166b0 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Thu, 22 Jan 2026 18:48:56 +0800 Subject: [PATCH 0056/1330] FROMLIST: arm64: dts: qcom: talos-evk-camera: Add DT overlay Enable IMX577 via CCI on Taloss EVK Core Kit. The Talos EVK board does not include a camera sensor by default, this DTSO has enabled the Arducam 12.3MP IMX577 Mini Camera Module on the CSI-1 interface. Link: https://lore.kernel.org/all/20260122-sm6150_evk-v5-5-039b170450a3@oss.qualcomm.com/ Reviewed-by: Vladimir Zapolskiy Signed-off-by: Wenmeng Liu --- arch/arm64/boot/dts/qcom/Makefile | 3 + .../dts/qcom/talos-evk-camera-imx577.dtso | 63 +++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-camera-imx577.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 201b3dda2e38c..529a5d56be714 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -350,9 +350,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-evk.dtb talos-evk-usb1-peripheral-dtbs := talos-evk.dtb talos-evk-usb1-peripheral.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtbo +talos-evk-camera-imx577-dtbs := talos-evk.dtb talos-evk-camera-imx577.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-usb1-peripheral.dtb talos-evk-lvds-auo,g133han01-dtbs := \ talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtb x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/talos-evk-camera-imx577.dtso b/arch/arm64/boot/dts/qcom/talos-evk-camera-imx577.dtso new file mode 100644 index 0000000000000..53006a861878f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-camera-imx577.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdd-csiphy-1p2-supply = <&vreg_l11a>; + vdd-csiphy-1p8-supply = <&vreg_l12a>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam2_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK2_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vreg_s4a>; + + port { + imx577_ep1: endpoint { + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; From 43ab5a30ffe14cdfa313723d6283cb9066623cfd Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 23 Feb 2026 14:55:41 +0800 Subject: [PATCH 0057/1330] FROMLIST: coresight: core: Refactoring ctcu_get_active_port and make it generic Remove ctcu_get_active_port from CTCU module and add it to the core framework. The port number is crucial for the CTCU device to identify which ETR it serves. With the port number we can correctly get required parameters of the CTCU device in TMC module. Link: https://lore.kernel.org/all/20260223-enable-byte-cntr-for-ctcu-v13-1-9cb44178b250@oss.qualcomm.com/ Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 24 +++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 19 +-------------- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 3 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 80e26396ad0a0..1cbaa63aa7215 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -585,6 +585,30 @@ struct coresight_device *coresight_get_sink(struct coresight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); +/** + * coresight_get_in_port: Find the input port number at @remote where the @csdev + * device is connected to. + * + * @csdev: csdev of the device. + * @remote: csdev of the remote device which is connected to @csdev. + * + * Return: port number upon success or -EINVAL for fail. + */ +int coresight_get_in_port(struct coresight_device *csdev, + struct coresight_device *remote) +{ + struct coresight_platform_data *pdata = remote->pdata; + int i; + + for (i = 0; i < pdata->nr_inconns; ++i) { + if (pdata->in_conns[i]->src_dev == csdev) + return pdata->in_conns[i]->dest_port; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(coresight_get_in_port); + u32 coresight_get_sink_id(struct coresight_device *csdev) { if (!csdev->ea) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c index abed15eb72b4a..78be783b3cb25 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -118,23 +118,6 @@ static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 traceid, in return 0; } -/* - * Searching the sink device from helper's view in case there are multiple helper devices - * connected to the sink device. - */ -static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper) -{ - struct coresight_platform_data *pdata = helper->pdata; - int i; - - for (i = 0; i < pdata->nr_inconns; ++i) { - if (pdata->in_conns[i]->src_dev == sink) - return pdata->in_conns[i]->dest_port; - } - - return -EINVAL; -} - static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight_path *path, bool enable) { @@ -147,7 +130,7 @@ static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight return -EINVAL; } - port_num = ctcu_get_active_port(sink, csdev); + port_num = coresight_get_in_port(sink, csdev); if (port_num < 0) return -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index fd896ac07942e..cbf80b83e5ce5 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -155,6 +155,8 @@ void coresight_remove_links(struct coresight_device *orig, u32 coresight_get_sink_id(struct coresight_device *csdev); void coresight_path_assign_trace_id(struct coresight_path *path, enum cs_mode mode); +int coresight_get_in_port(struct coresight_device *csdev, + struct coresight_device *remote); #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) int etm_readl_cp14(u32 off, unsigned int *val); From 5d1ce7bc4de21c514d9841f62f8c947719a159c7 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 23 Feb 2026 14:55:42 +0800 Subject: [PATCH 0058/1330] FROMLIST: coresight: tmc: add create/clean functions for etr_buf_list Introduce functions for creating and inserting or removing the etr_buf_node to/from the etr_buf_list. The byte-cntr functionality requires two etr_buf to receive trace data. The active etr_buf collects the trace data from source device, while the byte-cntr reading function accesses the deactivated etr_buf after is has been filled and synced, transferring data to the userspace. Link: https://lore.kernel.org/all/20260223-enable-byte-cntr-for-ctcu-v13-2-9cb44178b250@oss.qualcomm.com/ Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 1 + .../hwtracing/coresight/coresight-tmc-etr.c | 94 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 19 ++++ 3 files changed, 114 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 36599c431be62..1ea255ffa67cf 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -840,6 +840,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list = &etr_devs; + INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: desc.groups = coresight_etf_groups; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 4dc1defe27a5f..15c0874ff6418 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1918,6 +1918,100 @@ const struct coresight_ops tmc_etr_cs_ops = { .panic_ops = &tmc_etr_sync_ops, }; +/** + * tmc_clean_etr_buf_list - clean the etr_buf_list. + * @drvdata: driver data of the TMC device. + * + * Remove the allocated node from the list and free the extra buffer. + */ +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *next; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf == drvdata->sysfs_buf) { + if (coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED) { + drvdata->sysfs_buf = NULL; + tmc_free_etr_buf(nd->sysfs_buf); + nd->sysfs_buf = NULL; + } + list_del(&nd->node); + kfree(nd); + } else { + /* Free allocated buffers which are not utilized by ETR */ + list_del(&nd->node); + tmc_free_etr_buf(nd->sysfs_buf); + nd->sysfs_buf = NULL; + kfree(nd); + } + } +} +EXPORT_SYMBOL_GPL(tmc_clean_etr_buf_list); + +/** + * tmc_create_etr_buf_list - create a list to manage the etr_buf_node. + * @drvdata: driver data of the TMC device. + * @num_nodes: number of nodes want to create with the list. + * + * Return 0 upon success and return the error number if fail. + */ +int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes) +{ + struct etr_buf_node *new_node; + struct etr_buf *sysfs_buf; + int i = 0, ret = 0; + + /* We dont need a list if there is only one node */ + if (num_nodes < 2) + return -EINVAL; + + /* We expect that sysfs_buf in drvdata has already been allocated. */ + if (drvdata->sysfs_buf) { + /* Directly insert the allocated sysfs_buf into the list first */ + new_node = kzalloc_obj(*new_node, GFP_KERNEL); + if (IS_ERR(new_node)) + return PTR_ERR(new_node); + + new_node->sysfs_buf = drvdata->sysfs_buf; + new_node->is_free = false; + list_add(&new_node->node, &drvdata->etr_buf_list); + i++; + } + + while (i < num_nodes) { + new_node = kzalloc_obj(*new_node, GFP_KERNEL); + if (IS_ERR(new_node)) { + ret = PTR_ERR(new_node); + break; + } + + sysfs_buf = tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0), NULL); + if (IS_ERR(sysfs_buf)) { + kfree(new_node); + ret = PTR_ERR(sysfs_buf); + break; + } + + /* We dont have a available sysfs_buf in drvdata, setup one */ + if (!drvdata->sysfs_buf) { + drvdata->sysfs_buf = sysfs_buf; + new_node->is_free = false; + } else + new_node->is_free = true; + + new_node->sysfs_buf = sysfs_buf; + list_add(&new_node->node, &drvdata->etr_buf_list); + i++; + } + + /* Clean the list if there is an error */ + if (ret) + tmc_clean_etr_buf_list(drvdata); + + return ret; +} +EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list); + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret = 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 319a354ede9fc..57d8394d09b75 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -208,6 +208,19 @@ struct tmc_resrv_buf { s64 len; }; +/** + * @sysfs_buf: Allocated sysfs_buf. + * @is_free: Indicates whether the buffer is free to choose. + * @pos: Position of the buffer. + * @node: Node in etr_buf_list. + */ +struct etr_buf_node { + struct etr_buf *sysfs_buf; + bool is_free; + loff_t pos; + struct list_head node; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @atclk: optional clock for the core parts of the TMC. @@ -245,6 +258,8 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @etr_buf_list: List that is used to manage allocated etr_buf. + * @reading_node: Available buffer_node for byte-cntr reading. */ struct tmc_drvdata { struct clk *atclk; @@ -275,6 +290,8 @@ struct tmc_drvdata { struct etr_buf *perf_buf; struct tmc_resrv_buf resrv_buf; struct tmc_resrv_buf crash_mdata; + struct list_head etr_buf_list; + struct etr_buf_node *reading_node; }; struct etr_buf_operations { @@ -447,5 +464,7 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, enum cs_mode mode, struct coresight_path *path); extern const struct attribute_group coresight_etr_group; +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata); +int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes); #endif From 8d674b0fb4277b376203b1f52bef722f9e9ffe22 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 23 Feb 2026 14:55:43 +0800 Subject: [PATCH 0059/1330] FROMLIST: coresight: tmc: Introduce tmc_sysfs_ops to wrap sysfs read operations Introduce tmc_sysfs_ops as a wrapper, wrap sysfs read operations, for reading trace data from the TMC buffer. Link: https://lore.kernel.org/all/20260223-enable-byte-cntr-for-ctcu-v13-3-9cb44178b250@oss.qualcomm.com/ Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 51 ++++++++----------- drivers/hwtracing/coresight/coresight-tmc.h | 15 ++++++ 2 files changed, 37 insertions(+), 29 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 1ea255ffa67cf..32ca2ec994deb 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -232,17 +232,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) { int ret = 0; - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret = tmc_read_prepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret = tmc_read_prepare_etr(drvdata); - break; - default: + if (drvdata->sysfs_ops) + ret = drvdata->sysfs_ops->read_prepare(drvdata); + else ret = -EINVAL; - } if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); @@ -254,17 +247,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvdata) { int ret = 0; - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret = tmc_read_unprepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret = tmc_read_unprepare_etr(drvdata); - break; - default: + if (drvdata->sysfs_ops) + ret = drvdata->sysfs_ops->read_unprepare(drvdata); + else ret = -EINVAL; - } if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); @@ -291,15 +277,7 @@ static int tmc_open(struct inode *inode, struct file *file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp) { - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); - case TMC_CONFIG_TYPE_ETR: - return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); - } - - return -EINVAL; + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); } static ssize_t tmc_read(struct file *file, char __user *data, size_t len, @@ -769,6 +747,18 @@ static void register_crash_dev_interface(struct tmc_drvdata *drvdata, "Valid crash tracedata found\n"); } +static const struct tmc_sysfs_ops etb_sysfs_ops = { + .read_prepare = tmc_read_prepare_etb, + .read_unprepare = tmc_read_unprepare_etb, + .get_trace_data = tmc_etb_get_sysfs_trace, +}; + +static const struct tmc_sysfs_ops etr_sysfs_ops = { + .read_prepare = tmc_read_prepare_etr, + .read_unprepare = tmc_read_unprepare_etr, + .get_trace_data = tmc_etr_get_sysfs_trace, +}; + static int __tmc_probe(struct device *dev, struct resource *res) { int ret = 0; @@ -828,6 +818,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops = &tmc_etb_cs_ops; dev_list = &etb_devs; + drvdata->sysfs_ops = &etb_sysfs_ops; break; case TMC_CONFIG_TYPE_ETR: desc.groups = coresight_etr_groups; @@ -841,6 +832,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) mutex_init(&drvdata->idr_mutex); dev_list = &etr_devs; INIT_LIST_HEAD(&drvdata->etr_buf_list); + drvdata->sysfs_ops = &etr_sysfs_ops; break; case TMC_CONFIG_TYPE_ETF: desc.groups = coresight_etf_groups; @@ -849,6 +841,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; desc.ops = &tmc_etf_cs_ops; dev_list = &etf_devs; + drvdata->sysfs_ops = &etb_sysfs_ops; break; default: pr_err("%s: Unsupported TMC config\n", desc.name); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 57d8394d09b75..92ffaf771feab 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -260,6 +260,7 @@ struct etr_buf_node { * Used by ETR/ETF. * @etr_buf_list: List that is used to manage allocated etr_buf. * @reading_node: Available buffer_node for byte-cntr reading. + * @sysfs_ops: Read operations for sysfs mode. */ struct tmc_drvdata { struct clk *atclk; @@ -292,6 +293,20 @@ struct tmc_drvdata { struct tmc_resrv_buf crash_mdata; struct list_head etr_buf_list; struct etr_buf_node *reading_node; + const struct tmc_sysfs_ops *sysfs_ops; +}; + +/** + * struct tmc_sysfs_ops - read operations for TMC and its helper devices + * @read_prepare: prepare operation. + * @read_unprepare: unprepare operation. + * @get_trace_data: read operation. + */ +struct tmc_sysfs_ops { + int (*read_prepare)(struct tmc_drvdata *drvdata); + int (*read_unprepare)(struct tmc_drvdata *drvdata); + ssize_t (*get_trace_data)(struct tmc_drvdata *drvdata, loff_t pos, + size_t len, char **bufpp); }; struct etr_buf_operations { From f6406a07383d1f97f2d8f539e50846e867dd10ef Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 23 Feb 2026 14:55:44 +0800 Subject: [PATCH 0060/1330] FROMLIST: coresight: etr: add a new function to retrieve the CTCU device Add tmc_etr_get_ctcu_device function to find the ptr of the coresight_device of the CTCU device if the CTCU device is connected to the TMC ETR device. Link: https://lore.kernel.org/all/20260223-enable-byte-cntr-for-ctcu-v13-4-9cb44178b250@oss.qualcomm.com/ Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 24 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 15c0874ff6418..97d9e8384e0e0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -865,6 +865,30 @@ tmc_etr_get_catu_device(struct tmc_drvdata *drvdata) } EXPORT_SYMBOL_GPL(tmc_etr_get_catu_device); +/* + * TMC ETR could be connected to a CTCU device, which can provide ATID filter + * and byte-cntr service. This is represented by the output port of the TMC + * (ETR) connected to the input port of the CTCU. + * + * Retruns : coresight_device ptr for the CTCU device if a CTCU is found. + * : NULL otherwise. + */ +struct coresight_device * +tmc_etr_get_ctcu_device(struct tmc_drvdata *drvdata) +{ + struct coresight_device *etr = drvdata->csdev; + union coresight_dev_subtype ctcu_subtype = { + .helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU + }; + + if (!IS_ENABLED(CONFIG_CORESIGHT_CTCU)) + return NULL; + + return coresight_find_output_type(etr->pdata, CORESIGHT_DEV_TYPE_HELPER, + ctcu_subtype); +} +EXPORT_SYMBOL_GPL(tmc_etr_get_ctcu_device); + static const struct etr_buf_operations *etr_buf_ops[] = { [ETR_MODE_FLAT] = &etr_flat_buf_ops, [ETR_MODE_ETR_SG] = &etr_sg_buf_ops, diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 92ffaf771feab..27dd72065c606 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -472,6 +472,7 @@ static inline uint32_t find_crash_tracedata_crc(struct tmc_drvdata *drvdata, } struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); +struct coresight_device *tmc_etr_get_ctcu_device(struct tmc_drvdata *drvdata); void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); void tmc_etr_remove_catu_ops(void); From be4ede78e0574914416737a4f86da25e40024b92 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 23 Feb 2026 14:55:45 +0800 Subject: [PATCH 0061/1330] FROMLIST: dt-bindings: arm: add an interrupt property for Coresight CTCU Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Link: https://lore.kernel.org/all/20260223-enable-byte-cntr-for-ctcu-v13-5-9cb44178b250@oss.qualcomm.com/ Acked-by: Krzysztof Kozlowski Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index e002f87361ad3..2981001a7d7f7 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -44,6 +44,11 @@ properties: items: - const: apb + interrupts: + items: + - description: Interrupt for the ETR device connected to in-port0. + - description: Interrupt for the ETR device connected to in-port1. + label: description: Description of a coresight device. @@ -65,6 +70,8 @@ additionalProperties: false examples: - | + #include + ctcu@1001000 { compatible = "qcom,sa8775p-ctcu"; reg = <0x1001000 0x1000>; @@ -72,6 +79,9 @@ examples: clocks = <&aoss_qmp>; clock-names = "apb"; + interrupts = , + ; + in-ports { #address-cells = <1>; #size-cells = <0>; From 4cb3a02b84bace77e466075eea1cca50775a590a Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 23 Feb 2026 14:55:46 +0800 Subject: [PATCH 0062/1330] FROMLIST: coresight: ctcu: enable byte-cntr for TMC ETR devices The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the synced ETR buffer. Switching the sysfs_buf when current buffer is full or the timeout is triggered and resets rrp and rwp registers after switched the buffer. The synced buffer will become available for reading after the switch. Link: https://lore.kernel.org/all/20260223-enable-byte-cntr-for-ctcu-v13-6-9cb44178b250@oss.qualcomm.com/ Signed-off-by: Jie Gan --- .../testing/sysfs-bus-coresight-devices-ctcu | 8 + drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-ctcu-byte-cntr.c | 367 ++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 103 ++++- drivers/hwtracing/coresight/coresight-ctcu.h | 77 +++- .../hwtracing/coresight/coresight-tmc-etr.c | 18 + drivers/hwtracing/coresight/coresight-tmc.h | 1 + 7 files changed, 563 insertions(+), 13 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu new file mode 100644 index 0000000000000..a58a05491f7a6 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu @@ -0,0 +1,8 @@ +What: /sys/bus/coresight/devices//irq_threshold[0:1] +Date: February 2026 +KernelVersion: 7.1 +Contact: Tingwei Zhang ; Jinlong Mao ; Jie Gan +Description: + (RW) Configure the byte-cntr IRQ register for the specified ETR device + based on its port number. An interrupt is generated when the data size + exceeds the value set in the IRQ register. diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index ab16d06783a57..821a1b06b20c2 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -55,5 +55,5 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o -coresight-ctcu-y := coresight-ctcu-core.o +coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 0000000000000..bf59e654465b7 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data = (struct ctcu_byte_cntr *)data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + return IRQ_HANDLED; +} + +static void ctcu_reset_sysfs_buf(struct tmc_drvdata *drvdata) +{ + u32 sts; + + CS_UNLOCK(drvdata->base); + tmc_write_rrp(drvdata, drvdata->sysfs_buf->hwaddr); + tmc_write_rwp(drvdata, drvdata->sysfs_buf->hwaddr); + sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; + writel_relaxed(sts, drvdata->base + TMC_STS); + CS_LOCK(drvdata->base); +} + +static void ctcu_cfg_byte_cntr_reg(struct tmc_drvdata *drvdata, u32 val, u32 offset) +{ + struct ctcu_drvdata *ctcu_drvdata; + struct coresight_device *helper; + + helper = tmc_etr_get_ctcu_device(drvdata); + if (!helper) + return; + + ctcu_drvdata = dev_get_drvdata(helper->dev.parent); + /* A one value for IRQCTRL register represents 8 bytes */ + ctcu_program_register(ctcu_drvdata, val / 8, offset); +} + +static struct ctcu_byte_cntr *ctcu_get_byte_cntr_data(struct tmc_drvdata *drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct ctcu_drvdata *ctcu_drvdata; + struct coresight_device *helper; + int port; + + helper = tmc_etr_get_ctcu_device(drvdata); + if (!helper) + return NULL; + + port = coresight_get_in_port(drvdata->csdev, helper); + if (port < 0) + return NULL; + + ctcu_drvdata = dev_get_drvdata(helper->dev.parent); + byte_cntr_data = &ctcu_drvdata->byte_cntr_data[port]; + return byte_cntr_data; +} + +static bool ctcu_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct etr_buf_node *nd, *next, *curr_node, *picked_node; + struct etr_buf *curr_buf = drvdata->sysfs_buf; + bool found_free_buf = false; + + if (WARN_ON(!drvdata || !byte_cntr_data)) + return found_free_buf; + + /* Stop the ETR before we start the switch */ + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) + tmc_etr_enable_disable_hw(drvdata, false); + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + /* curr_buf is free for next round */ + if (nd->sysfs_buf == curr_buf) { + nd->is_free = true; + curr_node = nd; + } + + if (!found_free_buf && nd->is_free && nd->sysfs_buf != curr_buf) { + picked_node = nd; + found_free_buf = true; + } + } + + if (found_free_buf) { + curr_node->pos = 0; + drvdata->reading_node = curr_node; + drvdata->sysfs_buf = picked_node->sysfs_buf; + drvdata->etr_buf = picked_node->sysfs_buf; + picked_node->is_free = false; + /* Reset irq_cnt for next etr_buf */ + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* Reset rrp and rwp when the system has switched the buffer*/ + ctcu_reset_sysfs_buf(drvdata); + /* Restart the ETR when we find a free buffer */ + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) + tmc_etr_enable_disable_hw(drvdata, true); + } + + return found_free_buf; +} + +/* + * ctcu_byte_cntr_get_data() - reads data from the deactivated and filled buffer. + * The byte-cntr reading work reads data from the deactivated and filled buffer. + * The read operation waits for a buffer to become available, either filled or + * upon timeout, and then reads trace data from the synced buffer. + */ +static ssize_t ctcu_byte_cntr_get_data(struct tmc_drvdata *drvdata, loff_t pos, + size_t len, char **bufpp) +{ + struct etr_buf *sysfs_buf = drvdata->sysfs_buf; + struct device *dev = &drvdata->csdev->dev; + ssize_t actual, size = sysfs_buf->size; + struct ctcu_byte_cntr *byte_cntr_data; + size_t thresh_val; + atomic_t *irq_cnt; + int ret; + + byte_cntr_data = ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + thresh_val = byte_cntr_data->thresh_val; + irq_cnt = &byte_cntr_data->irq_cnt; + +wait_buffer: + if (!byte_cntr_data->reading_buf) { + ret = wait_event_interruptible_timeout(byte_cntr_data->wq, + ((atomic_read(irq_cnt) + 1) * thresh_val >= size) || + !byte_cntr_data->enable, + BYTE_CNTR_TIMEOUT); + if (ret < 0) + return ret; + /* + * The current etr_buf is almost full or timeout is triggered, + * so switch the buffer and mark the switched buffer as reading. + */ + if (byte_cntr_data->enable) { + if (!ctcu_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) { + dev_err(dev, "Switch buffer failed for byte-cntr\n"); + return -EINVAL; + } + + byte_cntr_data->reading_buf = true; + } else { + /* + * TMC-ETR has been disabled, so directly reads data from + * the drvdata->sysfs_buf. + */ + actual = drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); + if (actual > 0) { + byte_cntr_data->total_size += actual; + return actual; + } + + /* Exit byte-cntr reading */ + return 0; + } + } + + /* Check the status of current etr_buf*/ + if ((atomic_read(irq_cnt) + 1) * thresh_val >= size) + /* + * Unlikely to find a free buffer to switch, so just disable + * the ETR for a while. + */ + if (!ctcu_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) + dev_warn(dev, "No available buffer to store data, disable ETR\n"); + + pos = drvdata->reading_node->pos; + actual = drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); + if (actual <= 0) { + /* Reset flags upon reading is finished or failed */ + byte_cntr_data->reading_buf = false; + drvdata->reading_node = NULL; + + /* + * Nothing in the buffer, waiting for the next buffer + * to be filled. + */ + if (actual == 0) + goto wait_buffer; + } else + byte_cntr_data->total_size += actual; + + return actual; +} + +static int ctcu_read_prepare_byte_cntr(struct tmc_drvdata *drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + int ret = 0; + + /* config types are set a boot time and never change */ + if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR)) + return -EINVAL; + + /* + * Byte counter reading should start only after the TMC-ETR has been + * enabled, which implies that the sysfs_buf has already been setup + * in drvdata. + */ + if (!drvdata->sysfs_buf) + return -EINVAL; + + byte_cntr_data = ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + /* + * The threshold value must not exceed the buffer size. + * A margin should be maintained between the two values to account + * for the time gap between the interrupt and buffer switching. + */ + if (byte_cntr_data->thresh_val + SZ_16K >= drvdata->size) { + dev_err(&drvdata->csdev->dev, "The threshold value is too large\n"); + return -EINVAL; + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (byte_cntr_data->reading) { + ret = -EBUSY; + goto out_unlock; + } + + byte_cntr_data->reading = true; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + /* Setup an available etr_buf_list for byte-cntr */ + ret = tmc_create_etr_buf_list(drvdata, 2); + if (ret) + goto out; + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* Configure the byte-cntr register to enable IRQ */ + ctcu_cfg_byte_cntr_reg(drvdata, byte_cntr_data->thresh_val, + byte_cntr_data->irq_ctrl_offset); + enable_irq_wake(byte_cntr_data->irq); + byte_cntr_data->total_size = 0; + +out_unlock: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + +out: + return ret; +} + +static int ctcu_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata) +{ + struct device *dev = &drvdata->csdev->dev; + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + + byte_cntr_data = ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + /* Configure the byte-cntr register to disable IRQ */ + ctcu_cfg_byte_cntr_reg(drvdata, 0, byte_cntr_data->irq_ctrl_offset); + disable_irq_wake(byte_cntr_data->irq); + byte_cntr_data->reading = false; + byte_cntr_data->reading_buf = false; + drvdata->reading_node = NULL; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + dev_dbg(dev, "send data total size:%llu bytes\n", byte_cntr_data->total_size); + tmc_clean_etr_buf_list(drvdata); + + return 0; +} + +static const struct tmc_sysfs_ops byte_cntr_sysfs_ops = { + .read_prepare = ctcu_read_prepare_byte_cntr, + .read_unprepare = ctcu_read_unprepare_byte_cntr, + .get_trace_data = ctcu_byte_cntr_get_data, +}; + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path) +{ + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink = coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink) + return; + + port_num = coresight_get_in_port(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; + /* Don't start byte-cntr function when threshold is not set. */ + if (!byte_cntr_data->thresh_val || byte_cntr_data->enable) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable = true; + byte_cntr_data->reading_buf = false; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path) +{ + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink = coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink || coresight_get_mode(sink) == CS_MODE_SYSFS) + return; + + port_num = coresight_get_in_port(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable = false; +} + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd = dev->of_node; + int irq_num, ret, i; + + drvdata->byte_cntr_sysfs_ops = &byte_cntr_sysfs_ops; + for (i = 0; i < etr_num; i++) { + byte_cntr_data = &drvdata->byte_cntr_data[i]; + irq_num = of_irq_get(nd, i); + if (irq_num < 0) { + dev_err(dev, "Failed to get IRQ from DT for port%d\n", i); + continue; + } + + ret = devm_request_irq(dev, irq_num, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for port%d\n", i); + continue; + } + + byte_cntr_data->irq = irq_num; + init_waitqueue_head(&byte_cntr_data->wq); + raw_spin_lock_init(&drvdata->spin_lock); + } +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c index 78be783b3cb25..0e5cadaac3504 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "coresight-ctcu.h" #include "coresight-priv.h" @@ -45,17 +46,21 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 +#define CTCU_ETR0_IRQCTRL 0x6c +#define CTCU_ETR1_IRQCTRL 0x70 #define CTCU_ETR0_ATID0 0xf8 #define CTCU_ETR1_ATID0 0x108 static const struct ctcu_etr_config sa8775p_etr_cfgs[] = { { - .atid_offset = CTCU_ETR0_ATID0, - .port_num = 0, + .atid_offset = CTCU_ETR0_ATID0, + .irq_ctrl_offset = CTCU_ETR0_IRQCTRL, + .port_num = 0, }, { - .atid_offset = CTCU_ETR1_ATID0, - .port_num = 1, + .atid_offset = CTCU_ETR1_ATID0, + .irq_ctrl_offset = CTCU_ETR1_IRQCTRL, + .port_num = 1, }, }; @@ -64,6 +69,88 @@ static const struct ctcu_config sa8775p_cfgs = { .num_etr_config = ARRAY_SIZE(sa8775p_etr_cfgs), }; +void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offset) +{ + CS_UNLOCK(drvdata->base); + ctcu_writel(drvdata, val, offset); + CS_LOCK(drvdata->base); +} + +static ssize_t irq_threshold_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ctcu_byte_cntr_irq_attribute *irq_attr = + container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); + u8 port = irq_attr->port; + + if (!drvdata->byte_cntr_data[port].irq_ctrl_offset) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->byte_cntr_data[port].thresh_val); +} + +static ssize_t irq_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct ctcu_byte_cntr_irq_attribute *irq_attr = + container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); + u8 port = irq_attr->port; + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + /* Threshold 0 disables the interruption. */ + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); + /* A small threshold will result in a large number of interruptions */ + if (val && val < SZ_4K) + return -EINVAL; + + if (drvdata->byte_cntr_data[port].irq_ctrl_offset) + drvdata->byte_cntr_data[port].thresh_val = val; + + return size; +} + +static umode_t irq_threshold_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device_attribute *dev_attr = + container_of(attr, struct device_attribute, attr); + struct ctcu_byte_cntr_irq_attribute *irq_attr = + container_of(dev_attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct device *dev = kobj_to_dev(kobj); + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); + u8 port = irq_attr->port; + + if (drvdata && drvdata->byte_cntr_data[port].irq_ctrl_offset) + return attr->mode; + + return 0; +} + +static struct attribute *ctcu_attrs[] = { + ctcu_byte_cntr_irq_rw(0), + ctcu_byte_cntr_irq_rw(1), + NULL, +}; + +static struct attribute_group ctcu_attr_grp = { + .attrs = ctcu_attrs, + .is_visible = irq_threshold_is_visible, +}; + +static const struct attribute_group *ctcu_attr_grps[] = { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset, u8 bit, bool enable) { @@ -142,11 +229,15 @@ static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, struct coresight_path *path) { + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } static int ctcu_disable(struct coresight_device *csdev, struct coresight_path *path) { + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } @@ -197,7 +288,10 @@ static int ctcu_probe(struct platform_device *pdev) for (i = 0; i < cfgs->num_etr_config; i++) { etr_cfg = &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] = etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_ctrl_offset = + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } @@ -209,6 +303,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; desc.pdata = pdata; desc.dev = dev; + desc.groups = ctcu_attr_grps; desc.ops = &ctcu_ops; desc.access = CSDEV_ACCESS_IOMEM(base); diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h index e9594c38dd91c..bc833482c8bcb 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -5,19 +5,26 @@ #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + +#include #include "coresight-trace-id.h" /* Maximum number of supported ETR devices for a single CTCU. */ #define ETR_MAX_NUM 2 +#define BYTE_CNTR_TIMEOUT (5 * HZ) + /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @port_num: in-port number of the CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. + * @irq_name: IRQ name in dt node. */ struct ctcu_etr_config { const u32 atid_offset; const u32 port_num; + const u32 irq_ctrl_offset; }; struct ctcu_config { @@ -25,15 +32,69 @@ struct ctcu_config { int num_etr_config; }; -struct ctcu_drvdata { - void __iomem *base; - struct clk *apb_clk; - struct device *dev; - struct coresight_device *csdev; +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @reading: indicates that byte-cntr reading is started. + * @reading_buf: indicates that byte-cntr is reading data from the buffer. + * @thresh_val: threshold to trigger a interruption. + * @total_size: total size of transferred data. + * @irq: allocated number of the IRQ. + * @irq_cnt: IRQ count number for triggered interruptions. + * @wq: waitqueue for reading data from ETR buffer. + * @spin_lock: spinlock of byte_cntr_data. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + */ +struct ctcu_byte_cntr { + bool enable; + bool reading; + bool reading_buf; + u32 thresh_val; + u64 total_size; + int irq; + atomic_t irq_cnt; + wait_queue_head_t wq; raw_spinlock_t spin_lock; - u32 atid_offset[ETR_MAX_NUM]; + u32 irq_ctrl_offset; +}; + +struct ctcu_drvdata { + void __iomem *base; + struct clk *apb_clk; + struct device *dev; + struct coresight_device *csdev; + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; + raw_spinlock_t spin_lock; + u32 atid_offset[ETR_MAX_NUM]; /* refcnt for each traceid of each sink */ - u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; + u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; }; +/** + * struct ctcu_irq_thresh_attribute + * @attr: The device attribute. + * @idx: port number. + */ +struct ctcu_byte_cntr_irq_attribute { + struct device_attribute attr; + u8 port; +}; + +#define ctcu_byte_cntr_irq_rw(port) \ + (&((struct ctcu_byte_cntr_irq_attribute[]) { \ + { \ + __ATTR(irq_threshold##port, 0644, irq_threshold_show, \ + irq_threshold_store), \ + port, \ + } \ + })[0].attr.attr) + +void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offset); + +/* Byte-cntr functions */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path); +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path); +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int port_num); + #endif diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 97d9e8384e0e0..9cac8733d471c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1185,6 +1185,10 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, ssize_t actual = len; struct etr_buf *etr_buf = drvdata->sysfs_buf; + /* Reading the buffer from the buf_node if it exists*/ + if (drvdata->reading_node) + etr_buf = drvdata->reading_node->sysfs_buf; + if (pos + actual > etr_buf->len) actual = etr_buf->len - pos; if (actual <= 0) @@ -1248,6 +1252,20 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) } +/** + * tmc_etr_enable_disable_hw - enable/disable the ETR hw. + * @drvdata: drvdata of the TMC device. + * @enable: indicates enable/disable. + */ +void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable) +{ + if (enable) + __tmc_etr_enable_hw(drvdata); + else + __tmc_etr_disable_hw(drvdata); +} +EXPORT_SYMBOL_GPL(tmc_etr_enable_disable_hw); + void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etr_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 27dd72065c606..d60c70530c8a3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -482,5 +482,6 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, extern const struct attribute_group coresight_etr_group; void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata); int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes); +void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable); #endif From 36e0057720803c03143efa9f432ac64d82d80a4b Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 23 Feb 2026 14:55:47 +0800 Subject: [PATCH 0063/1330] FROMLIST: coresight: tmc: integrate byte-cntr's sysfs_ops with tmc sysfs file_ops Add code logic to invoke byte-cntr's tmc_sysfs_ops if the byte-cntr is enabled. Link: https://lore.kernel.org/all/20260223-enable-byte-cntr-for-ctcu-v13-7-9cb44178b250@oss.qualcomm.com/ Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 53 ++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 32ca2ec994deb..6486bdafdddc4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -31,6 +31,7 @@ #include "coresight-priv.h" #include "coresight-tmc.h" +#include "coresight-ctcu.h" DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); @@ -228,15 +229,47 @@ static int tmc_prepare_crashdata(struct tmc_drvdata *drvdata) return 0; } +/* Return the byte-cntr's tmc_sysfs_ops if in using */ +static const struct tmc_sysfs_ops *tmc_get_byte_cntr_sysfs_ops(struct tmc_drvdata *drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct ctcu_drvdata *ctcu_drvdata; + struct coresight_device *ctcu; + int port; + + ctcu = tmc_etr_get_ctcu_device(drvdata); + if (!ctcu) + return NULL; + + port = coresight_get_in_port(drvdata->csdev, ctcu); + if (port < 0) + return NULL; + + ctcu_drvdata = dev_get_drvdata(ctcu->dev.parent); + byte_cntr_data = &ctcu_drvdata->byte_cntr_data[port]; + if (byte_cntr_data && byte_cntr_data->thresh_val) + return ctcu_drvdata->byte_cntr_sysfs_ops; + + return NULL; +} + static int tmc_read_prepare(struct tmc_drvdata *drvdata) { + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; int ret = 0; + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) { + ret = byte_cntr_sysfs_ops->read_prepare(drvdata); + goto out; + } + if (drvdata->sysfs_ops) ret = drvdata->sysfs_ops->read_prepare(drvdata); else ret = -EINVAL; +out: if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); @@ -245,13 +278,21 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) static int tmc_read_unprepare(struct tmc_drvdata *drvdata) { + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; int ret = 0; + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) { + ret = byte_cntr_sysfs_ops->read_unprepare(drvdata); + goto out; + } + if (drvdata->sysfs_ops) ret = drvdata->sysfs_ops->read_unprepare(drvdata); else ret = -EINVAL; +out: if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); @@ -277,6 +318,12 @@ static int tmc_open(struct inode *inode, struct file *file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp) { + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; + + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) + return byte_cntr_sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); } @@ -297,7 +344,11 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len, return -EFAULT; } - *ppos += actual; + if (drvdata->reading_node) + drvdata->reading_node->pos += actual; + else + *ppos += actual; + dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); return actual; From f0e09f2e4be0eded24590ed4a764c2f4fcbb7cbb Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 19 Feb 2026 22:46:57 +0800 Subject: [PATCH 0064/1330] FROMLIST: coresight: ctcu: fix the spin_bug Acquiring an uninitialized raw_spin_lock is invalid and may trigger unexpected behavior or spin_bug. Link: https://lore.kernel.org/all/20260219-fix-spin-lock-issue-v1-1-557f7d513d7e@oss.qualcomm.com/ Fixes: f78d206f3d73 ("Coresight: Add Coresight TMC Control Unit driver") Reviewed-by: James Clark Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c index 0e5cadaac3504..444b460b82510 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -306,6 +306,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.groups = ctcu_attr_grps; desc.ops = &ctcu_ops; desc.access = CSDEV_ACCESS_IOMEM(base); + raw_spin_lock_init(&drvdata->spin_lock); drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) From 6b4e0b102871c01680ae5b36b66ce15ef5778303 Mon Sep 17 00:00:00 2001 From: Songwei Chai Date: Thu, 8 Jan 2026 18:11:35 -0800 Subject: [PATCH 0065/1330] FROMLIST: dt-bindings: arm: Add support for Qualcomm TGU trace The Trigger Generation Unit (TGU) is designed to detect patterns or sequences within a specific region of the System on Chip (SoC). Once configured and activated, it monitors sense inputs and can detect a pre-programmed state or sequence across clock cycles, subsequently producing a trigger. TGU configuration space offset table x-------------------------x | | | | | | Step configuration | | space layout | coresight management | x-------------x | registers | |---> | | | | | | reserve | | | | | | |-------------------------| | |-------------| | | | | priority[3] | | step[7] |<-- | |-------------| |-------------------------| | | | priority[2] | | | | | |-------------| | ... | |Steps region | | priority[1] | | | | | |-------------| |-------------------------| | | | priority[0] | | |<-- | |-------------| | step[0] |--------------------> | | |-------------------------| | condition | | | | | | control and status | x-------------x | space | | | x-------------------------x |Timer/Counter| | | x-------------x TGU Configuration in Hardware The TGU provides a step region for user configuration, similar to a flow chart. Each step region consists of three register clusters: 1.Priority Region: Sets the required signals with priority. 2.Condition Region: Defines specific requirements (e.g., signal A reaches three times) and the subsequent action once the requirement is met. 3.Timer/Counter (Optional): Provides timing or counting functionality. Add a new tgu.yaml file to describe the bindings required to define the TGU in the device trees. Link: https://lore.kernel.org/all/20260109021141.3778421-2-songwei.chai@oss.qualcomm.com/ Reviewed-by: Rob Herring (Arm) Signed-off-by: Songwei Chai --- .../devicetree/bindings/arm/qcom,tgu.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,tgu.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,tgu.yaml b/Documentation/devicetree/bindings/arm/qcom,tgu.yaml new file mode 100644 index 0000000000000..5b6a58ebe6911 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,tgu.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,tgu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trigger Generation Unit - TGU + +description: | + The Trigger Generation Unit (TGU) is a Data Engine which can be utilized + to sense a plurality of signals and create a trigger into the CTI or + generate interrupts to processors. The TGU is like the trigger circuit + of a Logic Analyzer. The corresponding trigger logic can be realized by + configuring the conditions for each step after sensing the signal. + Once setup and enabled, it will observe sense inputs and based upon + the activity of those inputs, even over clock cycles, may detect a + preprogrammed state/sequence and then produce a trigger or interrupt. + + The primary use case of the TGU is to detect patterns or sequences on a + given set of signals within some region to identify the issue in time + once there is abnormal behavior in the subsystem. + +maintainers: + - Mao Jinlong + - Songwei Chai + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,tgu + required: + - compatible + +properties: + compatible: + items: + - const: qcom,tgu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: + The port mechanism here ensures the relationship between TGU and + TPDM, as TPDM is one of the inputs for TGU. It will allow TGU to + function as TPDM's helper and enable TGU when the connected + TPDM is enabled. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + tgu@10b0e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x10b0e000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tgu_in_tpdm_swao: endpoint{ + remote-endpoint = <&tpdm_swao_out_tgu>; + }; + }; + }; + }; +... From 12589d5290788ac7fe7aab7455f37a7f3e47716f Mon Sep 17 00:00:00 2001 From: Songwei Chai Date: Thu, 8 Jan 2026 18:11:36 -0800 Subject: [PATCH 0066/1330] FROMLIST: qcom-tgu: Add TGU driver Add driver to support device TGU (Trigger Generation Unit). TGU is a Data Engine which can be utilized to sense a plurality of signals and create a trigger into the CTI or generate interrupts to processors. Add probe/enable/disable functions for tgu. Link: https://lore.kernel.org/all/20260109021141.3778421-3-songwei.chai@oss.qualcomm.com/ Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 9 + drivers/Makefile | 1 + drivers/hwtracing/Kconfig | 2 + drivers/hwtracing/qcom/Kconfig | 18 ++ drivers/hwtracing/qcom/Makefile | 3 + drivers/hwtracing/qcom/tgu.c | 176 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 51 +++++ 7 files changed, 260 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-amba-devices-tgu create mode 100644 drivers/hwtracing/qcom/Kconfig create mode 100644 drivers/hwtracing/qcom/Makefile create mode 100644 drivers/hwtracing/qcom/tgu.c create mode 100644 drivers/hwtracing/qcom/tgu.h diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu new file mode 100644 index 0000000000000..56ec3f5ab5d65 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -0,0 +1,9 @@ +What: /sys/bus/amba/devices//enable_tgu +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the enable/disable status of TGU + Accepts only one of the 2 values - 0 or 1. + 0 : disable TGU. + 1 : enable TGU. diff --git a/drivers/Makefile b/drivers/Makefile index 2c081c074c99e..89e85a173f849 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -177,6 +177,7 @@ obj-$(CONFIG_RAS) += ras/ obj-$(CONFIG_USB4) += thunderbolt/ obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/ obj-y += hwtracing/intel_th/ +obj-y += hwtracing/qcom/ obj-$(CONFIG_STM) += hwtracing/stm/ obj-$(CONFIG_HISI_PTT) += hwtracing/ptt/ obj-y += android/ diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig index 911ee977103c0..8a640218eed84 100644 --- a/drivers/hwtracing/Kconfig +++ b/drivers/hwtracing/Kconfig @@ -7,4 +7,6 @@ source "drivers/hwtracing/intel_th/Kconfig" source "drivers/hwtracing/ptt/Kconfig" +source "drivers/hwtracing/qcom/Kconfig" + endmenu diff --git a/drivers/hwtracing/qcom/Kconfig b/drivers/hwtracing/qcom/Kconfig new file mode 100644 index 0000000000000..d6f6d4b0f28ed --- /dev/null +++ b/drivers/hwtracing/qcom/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# QCOM specific hwtracing drivers +# +menu "Qualcomm specific hwtracing drivers" + +config QCOM_TGU + tristate "QCOM Trigger Generation Unit driver" + help + This driver provides support for Trigger Generation Unit that is + used to detect patterns or sequences on a given set of signals. + TGU is used to monitor a particular bus within a given region to + detect illegal transaction sequences or slave responses. It is also + used to monitor a data stream to detect protocol violations and to + provide a trigger point for centering data around a specific event + within the trace data buffer. + +endmenu diff --git a/drivers/hwtracing/qcom/Makefile b/drivers/hwtracing/qcom/Makefile new file mode 100644 index 0000000000000..5a0a868c1ea0d --- /dev/null +++ b/drivers/hwtracing/qcom/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_QCOM_TGU) += tgu.o diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c new file mode 100644 index 0000000000000..c5b2b384e6aeb --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tgu.h" + +static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +{ + TGU_UNLOCK(drvdata->base); + /* Enable TGU to program the triggers */ + writel(1, drvdata->base + TGU_CONTROL); + TGU_LOCK(drvdata->base); +} + +static int tgu_enable(struct device *dev) +{ + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + if (drvdata->enable) + return -EBUSY; + + tgu_write_all_hw_regs(drvdata); + drvdata->enable = true; + + return 0; +} + +static void tgu_disable(struct device *dev) +{ + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + if (drvdata->enable) { + TGU_UNLOCK(drvdata->base); + writel(0, drvdata->base + TGU_CONTROL); + TGU_LOCK(drvdata->base); + + drvdata->enable = false; + } +} + +static ssize_t enable_tgu_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + bool enabled; + + guard(spinlock)(&drvdata->lock); + enabled = drvdata->enable; + + return sysfs_emit(buf, "%d\n", enabled ? 1 : 0); +} + +/* enable_tgu_store - Configure Trace and Gating Unit (TGU) triggers. */ +static ssize_t enable_tgu_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + unsigned long val; + int ret = 0; + + ret = kstrtoul(buf, 0, &val); + if (ret) + return ret; + + if (val) { + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + ret = tgu_enable(dev); + if (ret) { + pm_runtime_put(dev); + return ret; + } + } else { + tgu_disable(dev); + pm_runtime_put(dev); + } + + return size; +} +static DEVICE_ATTR_RW(enable_tgu); + +static struct attribute *tgu_common_attrs[] = { + &dev_attr_enable_tgu.attr, + NULL, +}; + +static const struct attribute_group tgu_common_grp = { + .attrs = tgu_common_attrs, + NULL, +}; + +static const struct attribute_group *tgu_attr_groups[] = { + &tgu_common_grp, + NULL, +}; + +static int tgu_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct device *dev = &adev->dev; + struct tgu_drvdata *drvdata; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base = devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); + + spin_lock_init(&drvdata->lock); + + ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups); + if (ret) { + dev_err(dev, "failed to create sysfs groups: %d\n", ret); + return ret; + } + + drvdata->enable = false; + + pm_runtime_put(&adev->dev); + return 0; +} + +static void tgu_remove(struct amba_device *adev) +{ + struct device *dev = &adev->dev; + + sysfs_remove_groups(&dev->kobj, tgu_attr_groups); + + tgu_disable(dev); +} + +static const struct amba_id tgu_ids[] = { + { + .id = 0x000f0e00, + .mask = 0x000fffff, + }, + { 0, 0, NULL }, +}; + +MODULE_DEVICE_TABLE(amba, tgu_ids); + +static struct amba_driver tgu_driver = { + .drv = { + .name = "qcom-tgu", + .suppress_bind_attrs = true, + }, + .probe = tgu_probe, + .remove = tgu_remove, + .id_table = tgu_ids, +}; + +module_amba_driver(tgu_driver); + +MODULE_AUTHOR("Songwei Chai "); +MODULE_AUTHOR("Jinlong Mao "); +MODULE_DESCRIPTION("Qualcomm Trigger Generation Unit driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h new file mode 100644 index 0000000000000..b11cfb28261de --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _QCOM_TGU_H +#define _QCOM_TGU_H + +/* Register addresses */ +#define TGU_CONTROL 0x0000 +#define TGU_LAR 0xfb0 +#define TGU_UNLOCK_OFFSET 0xc5acce55 + +static inline void TGU_LOCK(void __iomem *addr) +{ + do { + /* Wait for things to settle */ + mb(); + writel_relaxed(0x0, addr + TGU_LAR); + } while (0); +} + +static inline void TGU_UNLOCK(void __iomem *addr) +{ + do { + writel_relaxed(TGU_UNLOCK_OFFSET, addr + TGU_LAR); + /* Make sure everyone has seen this */ + mb(); + } while (0); +} + +/** + * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) + * @base: Memory-mapped base address of the TGU device + * @dev: Pointer to the associated device structure + * @lock: Spinlock for handling concurrent access + * @enable: Flag indicating whether the TGU device is enabled + * + * This structure defines the data associated with a TGU device, + * including its base address, device pointers, clock, spinlock for + * synchronization, trigger data pointers, maximum limits for various + * trigger-related parameters, and enable status. + */ +struct tgu_drvdata { + void __iomem *base; + struct device *dev; + spinlock_t lock; + bool enable; +}; + +#endif From 541bc336e0eaebd29f6bed68ab0f9d7a8835aac2 Mon Sep 17 00:00:00 2001 From: Songwei Chai Date: Thu, 8 Jan 2026 18:11:37 -0800 Subject: [PATCH 0067/1330] FROMLIST: qcom-tgu: Add signal priority support Like circuit of a Logic analyzer, in TGU, the requirement could be configured in each step and the trigger will be created once the requirements are met. Add priority functionality here to sort the signals into different priorities. The signal which is wanted could be configured in each step's priority node, the larger number means the higher priority and the signal with higher priority will be sensed more preferentially. Link: https://lore.kernel.org/all/20260109021141.3778421-4-songwei.chai@oss.qualcomm.com/ Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 160 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 113 +++++++++++++ 3 files changed, 280 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu index 56ec3f5ab5d65..ec630e6ff2ee3 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -7,3 +7,10 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : disable TGU. 1 : enable TGU. + +What: /sys/bus/amba/devices//step[0:7]_priority[0:3]/reg[0:17] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the sensed signal with specific step and priority for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index c5b2b384e6aeb..f8870766d624d 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -14,14 +14,120 @@ #include "tgu.h" +static int calculate_array_location(struct tgu_drvdata *drvdata, + int step_index, int operation_index, + int reg_index) +{ + return operation_index * (drvdata->max_step) * (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; +} + +static ssize_t tgu_dataset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr = + container_of(attr, struct tgu_attribute, attr); + int index; + + index = calculate_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); +} + +static ssize_t tgu_dataset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tgu_drvdata *tgu_drvdata = dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr = + container_of(attr, struct tgu_attribute, attr); + unsigned long val; + int index; + + ret = kstrtoul(buf, 0, &val); + if (ret) + return ret; + + guard(spinlock)(&tgu_drvdata->lock); + index = calculate_array_location(tgu_drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + tgu_drvdata->value_table->priority[index] = val; + return size; +} + +static umode_t tgu_node_visible(struct kobject *kobject, + struct attribute *attr, + int n) +{ + struct device *dev = kobj_to_dev(kobject); + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + struct device_attribute *dev_attr = + container_of(attr, struct device_attribute, attr); + struct tgu_attribute *tgu_attr = + container_of(dev_attr, struct tgu_attribute, attr); + int ret = SYSFS_GROUP_INVISIBLE; + + if (tgu_attr->step_index < drvdata->max_step) { + ret = (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + } + return ret; +} + static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { + int i, j, k, index; + TGU_UNLOCK(drvdata->base); + for (i = 0; i < drvdata->max_step; i++) { + for (j = 0; j < MAX_PRIORITY; j++) { + for (k = 0; k < drvdata->max_reg; k++) { + index = calculate_array_location( + drvdata, i, j, k); + + writel(drvdata->value_table->priority[index], + drvdata->base + + PRIORITY_REG_STEP(i, j, k)); + } + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); TGU_LOCK(drvdata->base); } +static void tgu_set_reg_number(struct tgu_drvdata *drvdata) +{ + int num_sense_input; + int num_reg; + u32 devid; + + devid = readl(drvdata->base + TGU_DEVID); + + num_sense_input = TGU_DEVID_SENSE_INPUT(devid); + if (((num_sense_input * NUMBER_BITS_EACH_SIGNAL) % LENGTH_REGISTER) == 0) + num_reg = (num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTER; + else + num_reg = ((num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTER) + 1; + drvdata->max_reg = num_reg; + +} + +static void tgu_set_steps(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid = readl(drvdata->base + TGU_DEVID); + + drvdata->max_step = TGU_DEVID_STEPS(devid); +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata = dev_get_drvdata(dev); @@ -105,6 +211,38 @@ static const struct attribute_group tgu_common_grp = { static const struct attribute_group *tgu_attr_groups[] = { &tgu_common_grp, + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), NULL, }; @@ -112,6 +250,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; struct tgu_drvdata *drvdata; + size_t priority_size; + unsigned int *priority; int ret; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -127,12 +267,32 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->lock); + tgu_set_reg_number(drvdata); + tgu_set_steps(drvdata); + ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { dev_err(dev, "failed to create sysfs groups: %d\n", ret); return ret; } + drvdata->value_table = + devm_kzalloc(dev, sizeof(*drvdata->value_table), GFP_KERNEL); + if (!drvdata->value_table) + return -ENOMEM; + + priority_size = MAX_PRIORITY * drvdata->max_reg * + drvdata->max_step * + sizeof(*(drvdata->value_table->priority)); + + priority = devm_kzalloc(dev, priority_size, GFP_KERNEL); + + if (!priority) + return -ENOMEM; + + drvdata->value_table->priority = priority; + + drvdata->enable = false; pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index b11cfb28261de..f54cea01e4275 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -10,6 +10,113 @@ #define TGU_CONTROL 0x0000 #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 +#define TGU_DEVID 0xfc8 + +#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) +#define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) +#define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define NUMBER_BITS_EACH_SIGNAL 4 +#define LENGTH_REGISTER 32 + +/* + * TGU configuration space Step configuration + * offset table space layout + * x-------------------------x$ x-------------x$ + * | |$ | |$ + * | | | reserve |$ + * | | | |$ + * |coresight management | |-------------|base+n*0x1D8+0x1F4$ + * | registe | |---> |prioroty[3] |$ + * | | | |-------------|base+n*0x1D8+0x194$ + * | | | |prioroty[2] |$ + * |-------------------------| | |-------------|base+n*0x1D8+0x134$ + * | | | |prioroty[1] |$ + * | step[7] | | |-------------|base+n*0x1D8+0xD4$ + * |-------------------------|->base+0x40+7*0x1D8 | |prioroty[0] |$ + * | | | |-------------|base+n*0x1D8+0x74$ + * | ... | | | condition |$ + * | | | | select |$ + * |-------------------------|->base+0x40+1*0x1D8 | |-------------|base+n*0x1D8+0x60$ + * | | | | condition |$ + * | step[0] |--------------------> | decode |$ + * |-------------------------|-> base+0x40 |-------------|base+n*0x1D8+0x50$ + * | | | |$ + * | Control and status space| |Timer/Counter|$ + * | space | | |$ + * x-------------------------x->base x-------------x base+n*0x1D8+0x40$ + * + */ +#define STEP_OFFSET 0x1D8 +#define PRIORITY_START_OFFSET 0x0074 +#define PRIORITY_OFFSET 0x60 +#define REG_OFFSET 0x4 + +/* Calculate compare step addresses */ +#define PRIORITY_REG_STEP(step, priority, reg)\ + (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ + REG_OFFSET * reg + STEP_OFFSET * step) + +#define tgu_dataset_rw(name, step_index, type, reg_num) \ + (&((struct tgu_attribute[]){ { \ + __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ + step_index, \ + type, \ + reg_num, \ + } })[0].attr.attr) + +#define STEP_PRIORITY(step_index, reg_num, priority) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ + reg_num) + +#define STEP_PRIORITY_LIST(step_index, priority) \ + {STEP_PRIORITY(step_index, 0, priority), \ + STEP_PRIORITY(step_index, 1, priority), \ + STEP_PRIORITY(step_index, 2, priority), \ + STEP_PRIORITY(step_index, 3, priority), \ + STEP_PRIORITY(step_index, 4, priority), \ + STEP_PRIORITY(step_index, 5, priority), \ + STEP_PRIORITY(step_index, 6, priority), \ + STEP_PRIORITY(step_index, 7, priority), \ + STEP_PRIORITY(step_index, 8, priority), \ + STEP_PRIORITY(step_index, 9, priority), \ + STEP_PRIORITY(step_index, 10, priority), \ + STEP_PRIORITY(step_index, 11, priority), \ + STEP_PRIORITY(step_index, 12, priority), \ + STEP_PRIORITY(step_index, 13, priority), \ + STEP_PRIORITY(step_index, 14, priority), \ + STEP_PRIORITY(step_index, 15, priority), \ + STEP_PRIORITY(step_index, 16, priority), \ + STEP_PRIORITY(step_index, 17, priority), \ + NULL \ + } + +#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ + (&(const struct attribute_group){\ + .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ + .is_visible = tgu_node_visible,\ + .name = "step" #step "_priority" #priority \ + }) + +enum operation_index { + TGU_PRIORITY0, + TGU_PRIORITY1, + TGU_PRIORITY2, + TGU_PRIORITY3, +}; + +/* Maximum priority that TGU supports */ +#define MAX_PRIORITY 4 + +struct tgu_attribute { + struct device_attribute attr; + u32 step_index; + enum operation_index operation_index; + u32 reg_num; +}; + +struct value_table { + unsigned int *priority; +}; static inline void TGU_LOCK(void __iomem *addr) { @@ -35,6 +142,9 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @dev: Pointer to the associated device structure * @lock: Spinlock for handling concurrent access * @enable: Flag indicating whether the TGU device is enabled + * @value_table: Store given value based on relevant parameters. + * @max_reg: Maximum number of registers + * @max_step: Maximum step size * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -46,6 +156,9 @@ struct tgu_drvdata { struct device *dev; spinlock_t lock; bool enable; + struct value_table *value_table; + int max_reg; + int max_step; }; #endif From 5c6e64d57b13d86053e8efb8ab4833f9eb9e0606 Mon Sep 17 00:00:00 2001 From: Songwei Chai Date: Thu, 8 Jan 2026 18:11:38 -0800 Subject: [PATCH 0068/1330] FROMLIST: qcom-tgu: Add TGU decode support Decoding is when all the potential pieces for creating a trigger are brought together for a given step. Example - there may be a counter keeping track of some occurrences and a priority-group that is being used to detect a pattern on the sense inputs. These 2 inputs to condition_decode must be programmed, for a given step, to establish the condition for the trigger, or movement to another steps. Link: https://lore.kernel.org/all/20260109021141.3778421-5-songwei.chai@oss.qualcomm.com/ Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 162 ++++++++++++++++-- drivers/hwtracing/qcom/tgu.h | 27 +++ 3 files changed, 177 insertions(+), 19 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu index ec630e6ff2ee3..4efa36a11d8ee 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -14,3 +14,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the sensed signal with specific step and priority for TGU. + +What: /sys/bus/amba/devices//step[0:7]_condition_decode/reg[0:3] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the decode mode with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index f8870766d624d..39301d35ee9df 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -18,8 +18,36 @@ static int calculate_array_location(struct tgu_drvdata *drvdata, int step_index, int operation_index, int reg_index) { - return operation_index * (drvdata->max_step) * (drvdata->max_reg) + - step_index * (drvdata->max_reg) + reg_index; + int ret = -EINVAL; + + switch (operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + ret = operation_index * (drvdata->max_step) * + (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; + break; + case TGU_CONDITION_DECODE: + ret = step_index * (drvdata->max_condition_decode) + + reg_index; + break; + default: + break; + } + return ret; +} + +static int check_array_location(struct tgu_drvdata *drvdata, int step, + int ops, int reg) +{ + int result = calculate_array_location(drvdata, step, ops, reg); + + if (result == -EINVAL) + dev_err(drvdata->dev, "%s - Fail\n", __func__); + + return result; } static ssize_t tgu_dataset_show(struct device *dev, @@ -30,12 +58,26 @@ static ssize_t tgu_dataset_show(struct device *dev, container_of(attr, struct tgu_attribute, attr); int index; - index = calculate_array_location(drvdata, tgu_attr->step_index, - tgu_attr->operation_index, - tgu_attr->reg_num); - - return sysfs_emit(buf, "0x%x\n", - drvdata->value_table->priority[index]); + index = check_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, tgu_attr->reg_num); + + if (index == -EINVAL) + return index; + + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); + case TGU_CONDITION_DECODE: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->condition_decode[index]); + default: + break; + } + return -EINVAL; } static ssize_t tgu_dataset_store(struct device *dev, @@ -47,18 +89,37 @@ static ssize_t tgu_dataset_store(struct device *dev, container_of(attr, struct tgu_attribute, attr); unsigned long val; int index; + int ret; ret = kstrtoul(buf, 0, &val); if (ret) return ret; guard(spinlock)(&tgu_drvdata->lock); - index = calculate_array_location(tgu_drvdata, tgu_attr->step_index, + index = check_array_location(tgu_drvdata, tgu_attr->step_index, tgu_attr->operation_index, tgu_attr->reg_num); - tgu_drvdata->value_table->priority[index] = val; - return size; + if (index == -EINVAL) + return -EINVAL; + + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + tgu_drvdata->value_table->priority[index] = val; + ret = size; + break; + case TGU_CONDITION_DECODE: + tgu_drvdata->value_table->condition_decode[index] = val; + ret = size; + break; + default: + ret = -EINVAL; + break; + } + return ret; } static umode_t tgu_node_visible(struct kobject *kobject, @@ -74,13 +135,27 @@ static umode_t tgu_node_visible(struct kobject *kobject, int ret = SYSFS_GROUP_INVISIBLE; if (tgu_attr->step_index < drvdata->max_step) { - ret = (tgu_attr->reg_num < drvdata->max_reg) ? - attr->mode : 0; + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + ret = (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + break; + case TGU_CONDITION_DECODE: + ret = (tgu_attr->reg_num < + drvdata->max_condition_decode) ? + attr->mode : 0; + break; + default: + break; + } } return ret; } -static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { int i, j, k, index; @@ -88,8 +163,10 @@ static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) for (i = 0; i < drvdata->max_step; i++) { for (j = 0; j < MAX_PRIORITY; j++) { for (k = 0; k < drvdata->max_reg; k++) { - index = calculate_array_location( + index = check_array_location( drvdata, i, j, k); + if (index == -EINVAL) + goto exit; writel(drvdata->value_table->priority[index], drvdata->base + @@ -97,9 +174,23 @@ static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) } } } + + for (i = 0; i < drvdata->max_step; i++) { + for (j = 0; j < drvdata->max_condition_decode; j++) { + index = check_array_location(drvdata, i, + TGU_CONDITION_DECODE, j); + if (index == -EINVAL) + goto exit; + + writel(drvdata->value_table->condition_decode[index], + drvdata->base + CONDITION_DECODE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); +exit: TGU_LOCK(drvdata->base); + return index >= 0 ? 0 : -EINVAL; } static void tgu_set_reg_number(struct tgu_drvdata *drvdata) @@ -128,18 +219,32 @@ static void tgu_set_steps(struct tgu_drvdata *drvdata) drvdata->max_step = TGU_DEVID_STEPS(devid); } +static void tgu_set_conditions(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid = readl(drvdata->base + TGU_DEVID); + drvdata->max_condition_decode = TGU_DEVID_CONDITIONS(devid); +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + int ret = 0; guard(spinlock)(&drvdata->lock); if (drvdata->enable) return -EBUSY; - tgu_write_all_hw_regs(drvdata); + ret = tgu_write_all_hw_regs(drvdata); + + if (ret == -EINVAL) + goto exit; + drvdata->enable = true; - return 0; +exit: + return ret; } static void tgu_disable(struct device *dev) @@ -243,6 +348,14 @@ static const struct attribute_group *tgu_attr_groups[] = { PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(0), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(1), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(2), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(3), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(4), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7), NULL, }; @@ -250,8 +363,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; struct tgu_drvdata *drvdata; - size_t priority_size; - unsigned int *priority; + size_t priority_size, condition_size; + unsigned int *priority, *condition; int ret; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -269,6 +382,7 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); + tgu_set_conditions(drvdata); ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -292,6 +406,16 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) drvdata->value_table->priority = priority; + condition_size = drvdata->max_condition_decode * + drvdata->max_step * + sizeof(*(drvdata->value_table->condition_decode)); + + condition = devm_kzalloc(dev, condition_size, GFP_KERNEL); + + if (!condition) + return -ENOMEM; + + drvdata->value_table->condition_decode = condition; drvdata->enable = false; diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index f54cea01e4275..0d058663aca50 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -15,6 +15,7 @@ #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) #define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) #define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define TGU_DEVID_CONDITIONS(devid_val) ((int)BMVAL(devid_val, 0, 2)) #define NUMBER_BITS_EACH_SIGNAL 4 #define LENGTH_REGISTER 32 @@ -48,6 +49,7 @@ */ #define STEP_OFFSET 0x1D8 #define PRIORITY_START_OFFSET 0x0074 +#define CONDITION_DECODE_OFFSET 0x0050 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 @@ -56,6 +58,9 @@ (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ REG_OFFSET * reg + STEP_OFFSET * step) +#define CONDITION_DECODE_STEP(step, decode) \ + (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -68,6 +73,9 @@ tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ reg_num) +#define STEP_DECODE(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -90,6 +98,14 @@ NULL \ } +#define STEP_DECODE_LIST(n) \ + {STEP_DECODE(n, 0), \ + STEP_DECODE(n, 1), \ + STEP_DECODE(n, 2), \ + STEP_DECODE(n, 3), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -97,11 +113,19 @@ .name = "step" #step "_priority" #priority \ }) +#define CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs = (struct attribute*[])STEP_DECODE_LIST(step),\ + .is_visible = tgu_node_visible,\ + .name = "step" #step "_condition_decode" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, TGU_PRIORITY2, TGU_PRIORITY3, + TGU_CONDITION_DECODE, }; /* Maximum priority that TGU supports */ @@ -116,6 +140,7 @@ struct tgu_attribute { struct value_table { unsigned int *priority; + unsigned int *condition_decode; }; static inline void TGU_LOCK(void __iomem *addr) @@ -145,6 +170,7 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @value_table: Store given value based on relevant parameters. * @max_reg: Maximum number of registers * @max_step: Maximum step size + * @max_condition_decode: Maximum number of condition_decode * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -159,6 +185,7 @@ struct tgu_drvdata { struct value_table *value_table; int max_reg; int max_step; + int max_condition_decode; }; #endif From 4b3d5c85c176cb7e018ca06cc898edd96989099f Mon Sep 17 00:00:00 2001 From: Songwei Chai Date: Thu, 8 Jan 2026 18:11:39 -0800 Subject: [PATCH 0069/1330] FROMLIST: qcom-tgu: Add support to configure next action Add "select" node for each step to determine if another step is taken, trigger(s) are generated, counters/timers incremented/decremented, etc. Link: https://lore.kernel.org/all/20260109021141.3778421-6-songwei.chai@oss.qualcomm.com/ Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 +++ drivers/hwtracing/qcom/tgu.c | 57 ++++++++++++++++++- drivers/hwtracing/qcom/tgu.h | 27 +++++++++ 3 files changed, 89 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu index 4efa36a11d8ee..fffe65d3c0db5 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -21,3 +21,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the decode mode with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_condition_select/reg[0:3] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the next action with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 39301d35ee9df..e1a1f0f423bab 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -33,6 +33,10 @@ static int calculate_array_location(struct tgu_drvdata *drvdata, ret = step_index * (drvdata->max_condition_decode) + reg_index; break; + case TGU_CONDITION_SELECT: + ret = step_index * (drvdata->max_condition_select) + + reg_index; + break; default: break; } @@ -74,6 +78,9 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_DECODE: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_decode[index]); + case TGU_CONDITION_SELECT: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->condition_select[index]); default: break; } @@ -115,6 +122,10 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_decode[index] = val; ret = size; break; + case TGU_CONDITION_SELECT: + tgu_drvdata->value_table->condition_select[index] = val; + ret = size; + break; default: ret = -EINVAL; break; @@ -148,6 +159,15 @@ static umode_t tgu_node_visible(struct kobject *kobject, drvdata->max_condition_decode) ? attr->mode : 0; break; + case TGU_CONDITION_SELECT: + /* 'default' register is at the end of 'select' region */ + if (tgu_attr->reg_num == + drvdata->max_condition_select - 1) + attr->name = "default"; + ret = (tgu_attr->reg_num < + drvdata->max_condition_select) ? + attr->mode : 0; + break; default: break; } @@ -186,6 +206,19 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) drvdata->base + CONDITION_DECODE_STEP(i, j)); } } + + for (i = 0; i < drvdata->max_step; i++) { + for (j = 0; j < drvdata->max_condition_select; j++) { + index = check_array_location(drvdata, i, + TGU_CONDITION_SELECT, j); + + if (index == -EINVAL) + goto exit; + + writel(drvdata->value_table->condition_select[index], + drvdata->base + CONDITION_SELECT_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -225,6 +258,8 @@ static void tgu_set_conditions(struct tgu_drvdata *drvdata) devid = readl(drvdata->base + TGU_DEVID); drvdata->max_condition_decode = TGU_DEVID_CONDITIONS(devid); + /* select region has an additional 'default' register */ + drvdata->max_condition_select = TGU_DEVID_CONDITIONS(devid) + 1; } static int tgu_enable(struct device *dev) @@ -356,6 +391,14 @@ static const struct attribute_group *tgu_attr_groups[] = { CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5), CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6), CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(0), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(1), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(2), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(3), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(4), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), NULL, }; @@ -363,8 +406,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; struct tgu_drvdata *drvdata; - size_t priority_size, condition_size; - unsigned int *priority, *condition; + size_t priority_size, condition_size, select_size; + unsigned int *priority, *condition, *select; int ret; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -417,6 +460,16 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) drvdata->value_table->condition_decode = condition; + select_size = drvdata->max_condition_select * drvdata->max_step * + sizeof(*(drvdata->value_table->condition_select)); + + select = devm_kzalloc(dev, select_size, GFP_KERNEL); + + if (!select) + return -ENOMEM; + + drvdata->value_table->condition_select = select; + drvdata->enable = false; pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 0d058663aca50..8c92e88d7e2c9 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -50,6 +50,7 @@ #define STEP_OFFSET 0x1D8 #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 +#define CONDITION_SELECT_OFFSET 0x0060 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 @@ -61,6 +62,9 @@ #define CONDITION_DECODE_STEP(step, decode) \ (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) +#define CONDITION_SELECT_STEP(step, select) \ + (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -76,6 +80,9 @@ #define STEP_DECODE(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) +#define STEP_SELECT(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -106,6 +113,15 @@ NULL \ } +#define STEP_SELECT_LIST(n) \ + {STEP_SELECT(n, 0), \ + STEP_SELECT(n, 1), \ + STEP_SELECT(n, 2), \ + STEP_SELECT(n, 3), \ + STEP_SELECT(n, 4), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -120,12 +136,20 @@ .name = "step" #step "_condition_decode" \ }) +#define CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs = (struct attribute*[])STEP_SELECT_LIST(step),\ + .is_visible = tgu_node_visible,\ + .name = "step" #step "_condition_select" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, TGU_PRIORITY2, TGU_PRIORITY3, TGU_CONDITION_DECODE, + TGU_CONDITION_SELECT, }; /* Maximum priority that TGU supports */ @@ -141,6 +165,7 @@ struct tgu_attribute { struct value_table { unsigned int *priority; unsigned int *condition_decode; + unsigned int *condition_select; }; static inline void TGU_LOCK(void __iomem *addr) @@ -171,6 +196,7 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @max_reg: Maximum number of registers * @max_step: Maximum step size * @max_condition_decode: Maximum number of condition_decode + * @max_condition_select: Maximum number of condition_select * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -186,6 +212,7 @@ struct tgu_drvdata { int max_reg; int max_step; int max_condition_decode; + int max_condition_select; }; #endif From 8d1ae94e94b69989641786dada18d42c96a162b0 Mon Sep 17 00:00:00 2001 From: Songwei Chai Date: Thu, 8 Jan 2026 18:11:40 -0800 Subject: [PATCH 0070/1330] FROMLIST: qcom-tgu: Add timer/counter functionality for TGU Add counter and timer node for each step which could be programed if they are to be utilized in trigger event/sequence. Link: https://lore.kernel.org/all/20260109021141.3778421-7-songwei.chai@oss.qualcomm.com/ Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 14 ++ drivers/hwtracing/qcom/tgu.c | 126 +++++++++++++++++- drivers/hwtracing/qcom/tgu.h | 54 ++++++++ 3 files changed, 192 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu index fffe65d3c0db5..61b5a08bdee17 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -28,3 +28,17 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the next action with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_timer/reg[0:1] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the timer value with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_counter/reg[0:1] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the counter value with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index e1a1f0f423bab..a3d9c3c4e28a9 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -37,6 +37,12 @@ static int calculate_array_location(struct tgu_drvdata *drvdata, ret = step_index * (drvdata->max_condition_select) + reg_index; break; + case TGU_COUNTER: + ret = step_index * (drvdata->max_counter) + reg_index; + break; + case TGU_TIMER: + ret = step_index * (drvdata->max_timer) + reg_index; + break; default: break; } @@ -81,6 +87,12 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_SELECT: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_select[index]); + case TGU_TIMER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->timer[index]); + case TGU_COUNTER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->counter[index]); default: break; } @@ -126,6 +138,14 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_select[index] = val; ret = size; break; + case TGU_TIMER: + tgu_drvdata->value_table->timer[index] = val; + ret = size; + break; + case TGU_COUNTER: + tgu_drvdata->value_table->counter[index] = val; + ret = size; + break; default: ret = -EINVAL; break; @@ -168,6 +188,22 @@ static umode_t tgu_node_visible(struct kobject *kobject, drvdata->max_condition_select) ? attr->mode : 0; break; + case TGU_COUNTER: + if (drvdata->max_counter == 0) + ret = SYSFS_GROUP_INVISIBLE; + else + ret = (tgu_attr->reg_num < + drvdata->max_counter) ? + attr->mode : 0; + break; + case TGU_TIMER: + if (drvdata->max_timer == 0) + ret = SYSFS_GROUP_INVISIBLE; + else + ret = (tgu_attr->reg_num < + drvdata->max_timer) ? + attr->mode : 0; + break; default: break; } @@ -219,6 +255,30 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) drvdata->base + CONDITION_SELECT_STEP(i, j)); } } + + for (i = 0; i < drvdata->max_step; i++) { + for (j = 0; j < drvdata->max_timer; j++) { + index = check_array_location(drvdata, i, TGU_TIMER, j); + + if (index == -EINVAL) + goto exit; + + writel(drvdata->value_table->timer[index], + drvdata->base + TIMER_COMPARE_STEP(i, j)); + } + } + + for (i = 0; i < drvdata->max_step; i++) { + for (j = 0; j < drvdata->max_counter; j++) { + index = check_array_location(drvdata, i, TGU_COUNTER, j); + + if (index == -EINVAL) + goto exit; + + writel(drvdata->value_table->counter[index], + drvdata->base + COUNTER_COMPARE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -262,6 +322,31 @@ static void tgu_set_conditions(struct tgu_drvdata *drvdata) drvdata->max_condition_select = TGU_DEVID_CONDITIONS(devid) + 1; } +static void tgu_set_timer_counter(struct tgu_drvdata *drvdata) +{ + int num_timers, num_counters; + u32 devid2; + + devid2 = readl(drvdata->base + CORESIGHT_DEVID2); + + if (TGU_DEVID2_TIMER0(devid2) && TGU_DEVID2_TIMER1(devid2)) + num_timers = 2; + else if (TGU_DEVID2_TIMER0(devid2) || TGU_DEVID2_TIMER1(devid2)) + num_timers = 1; + else + num_timers = 0; + + if (TGU_DEVID2_COUNTER0(devid2) && TGU_DEVID2_COUNTER1(devid2)) + num_counters = 2; + else if (TGU_DEVID2_COUNTER0(devid2) || TGU_DEVID2_COUNTER1(devid2)) + num_counters = 1; + else + num_counters = 0; + + drvdata->max_timer = num_timers; + drvdata->max_counter = num_counters; +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata = dev_get_drvdata(dev); @@ -399,6 +484,22 @@ static const struct attribute_group *tgu_attr_groups[] = { CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), + TIMER_ATTRIBUTE_GROUP_INIT(0), + TIMER_ATTRIBUTE_GROUP_INIT(1), + TIMER_ATTRIBUTE_GROUP_INIT(2), + TIMER_ATTRIBUTE_GROUP_INIT(3), + TIMER_ATTRIBUTE_GROUP_INIT(4), + TIMER_ATTRIBUTE_GROUP_INIT(5), + TIMER_ATTRIBUTE_GROUP_INIT(6), + TIMER_ATTRIBUTE_GROUP_INIT(7), + COUNTER_ATTRIBUTE_GROUP_INIT(0), + COUNTER_ATTRIBUTE_GROUP_INIT(1), + COUNTER_ATTRIBUTE_GROUP_INIT(2), + COUNTER_ATTRIBUTE_GROUP_INIT(3), + COUNTER_ATTRIBUTE_GROUP_INIT(4), + COUNTER_ATTRIBUTE_GROUP_INIT(5), + COUNTER_ATTRIBUTE_GROUP_INIT(6), + COUNTER_ATTRIBUTE_GROUP_INIT(7), NULL, }; @@ -406,8 +507,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; struct tgu_drvdata *drvdata; - size_t priority_size, condition_size, select_size; - unsigned int *priority, *condition, *select; + size_t priority_size, condition_size, select_size, timer_size, counter_size; + unsigned int *priority, *condition, *select, *timer, *counter; int ret; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -426,6 +527,7 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); tgu_set_conditions(drvdata); + tgu_set_timer_counter(drvdata); ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -470,6 +572,26 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) drvdata->value_table->condition_select = select; + timer_size = drvdata->max_step * drvdata->max_timer * + sizeof(*(drvdata->value_table->timer)); + + timer = devm_kzalloc(dev, timer_size, GFP_KERNEL); + + if (!timer) + return -ENOMEM; + + drvdata->value_table->timer = timer; + + counter_size = drvdata->max_step * drvdata->max_counter * + sizeof(*(drvdata->value_table->counter)); + + counter = devm_kzalloc(dev, counter_size, GFP_KERNEL); + + if (!counter) + return -ENOMEM; + + drvdata->value_table->counter = counter; + drvdata->enable = false; pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 8c92e88d7e2c9..94708750b02dd 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -11,11 +11,17 @@ #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 #define TGU_DEVID 0xfc8 +#define CORESIGHT_DEVID2 0xfc0 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) #define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) #define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) #define TGU_DEVID_CONDITIONS(devid_val) ((int)BMVAL(devid_val, 0, 2)) +#define TGU_DEVID2_TIMER0(devid_val) ((int)BMVAL(devid_val, 18, 23)) +#define TGU_DEVID2_TIMER1(devid_val) ((int)BMVAL(devid_val, 13, 17)) +#define TGU_DEVID2_COUNTER0(devid_val) ((int)BMVAL(devid_val, 6, 11)) +#define TGU_DEVID2_COUNTER1(devid_val) ((int)BMVAL(devid_val, 0, 5)) + #define NUMBER_BITS_EACH_SIGNAL 4 #define LENGTH_REGISTER 32 @@ -51,6 +57,8 @@ #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 #define CONDITION_SELECT_OFFSET 0x0060 +#define TIMER_START_OFFSET 0x0040 +#define COUNTER_START_OFFSET 0x0048 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 @@ -62,6 +70,12 @@ #define CONDITION_DECODE_STEP(step, decode) \ (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) +#define TIMER_COMPARE_STEP(step, timer) \ + (TIMER_START_OFFSET + REG_OFFSET * timer + STEP_OFFSET * step) + +#define COUNTER_COMPARE_STEP(step, counter) \ + (COUNTER_START_OFFSET + REG_OFFSET * counter + STEP_OFFSET * step) + #define CONDITION_SELECT_STEP(step, select) \ (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) @@ -83,6 +97,12 @@ #define STEP_SELECT(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) +#define STEP_TIMER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_TIMER, reg_num) + +#define STEP_COUNTER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_COUNTER, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -122,6 +142,18 @@ NULL \ } +#define STEP_TIMER_LIST(n) \ + {STEP_TIMER(n, 0), \ + STEP_TIMER(n, 1), \ + NULL \ + } + +#define STEP_COUNTER_LIST(n) \ + {STEP_COUNTER(n, 0), \ + STEP_COUNTER(n, 1), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -143,6 +175,20 @@ .name = "step" #step "_condition_select" \ }) +#define TIMER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs = (struct attribute*[])STEP_TIMER_LIST(step),\ + .is_visible = tgu_node_visible,\ + .name = "step" #step "_timer" \ + }) + +#define COUNTER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs = (struct attribute*[])STEP_COUNTER_LIST(step),\ + .is_visible = tgu_node_visible,\ + .name = "step" #step "_counter" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, @@ -150,6 +196,8 @@ enum operation_index { TGU_PRIORITY3, TGU_CONDITION_DECODE, TGU_CONDITION_SELECT, + TGU_TIMER, + TGU_COUNTER }; /* Maximum priority that TGU supports */ @@ -166,6 +214,8 @@ struct value_table { unsigned int *priority; unsigned int *condition_decode; unsigned int *condition_select; + unsigned int *timer; + unsigned int *counter; }; static inline void TGU_LOCK(void __iomem *addr) @@ -197,6 +247,8 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @max_step: Maximum step size * @max_condition_decode: Maximum number of condition_decode * @max_condition_select: Maximum number of condition_select + * @max_timer: Maximum number of timers + * @max_counter: Maximum number of counters * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -213,6 +265,8 @@ struct tgu_drvdata { int max_step; int max_condition_decode; int max_condition_select; + int max_timer; + int max_counter; }; #endif From 92087f948dcb99733951e0f08c3190ff0da789f9 Mon Sep 17 00:00:00 2001 From: Songwei Chai Date: Thu, 8 Jan 2026 18:11:41 -0800 Subject: [PATCH 0071/1330] FROMLIST: qcom-tgu: Add reset node to initialize Add reset node to initialize the value of priority/condition_decode/condition_select/timer/counter nodes. Link: https://lore.kernel.org/all/20260109021141.3778421-8-songwei.chai@oss.qualcomm.com/ Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 ++ drivers/hwtracing/qcom/tgu.c | 74 +++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu index 61b5a08bdee17..fa2618b31ab97 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -42,3 +42,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the counter value with specific step for TGU. + +What: /sys/bus/amba/devices//reset_tgu +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (Write) Write 1 to reset the dataset for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index a3d9c3c4e28a9..0a45ff78858b8 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -424,8 +424,82 @@ static ssize_t enable_tgu_store(struct device *dev, } static DEVICE_ATTR_RW(enable_tgu); +/* reset_tgu_store - Reset Trace and Gating Unit (TGU) configuration. */ +static ssize_t reset_tgu_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + unsigned long value; + int i, j, ret; + + if (kstrtoul(buf, 0, &value) || value == 0) + return -EINVAL; + + if (!drvdata->enable) { + ret = pm_runtime_get_sync(drvdata->dev); + if (ret < 0) { + pm_runtime_put(drvdata->dev); + return ret; + } + } + + guard(spinlock)(&drvdata->lock); + TGU_UNLOCK(drvdata->base); + + writel(0, drvdata->base + TGU_CONTROL); + + TGU_LOCK(drvdata->base); + + if (drvdata->value_table->priority) + memset(drvdata->value_table->priority, 0, + MAX_PRIORITY * drvdata->max_step * + drvdata->max_reg * sizeof(unsigned int)); + + if (drvdata->value_table->condition_decode) + memset(drvdata->value_table->condition_decode, 0, + drvdata->max_condition_decode * drvdata->max_step * + sizeof(unsigned int)); + + /* Initialize all condition registers to NOT(value=0x1000000) */ + for (i = 0; i < drvdata->max_step; i++) { + for (j = 0; j < drvdata->max_condition_decode; j++) { + drvdata->value_table + ->condition_decode[calculate_array_location( + drvdata, i, TGU_CONDITION_DECODE, j)] = + 0x1000000; + } + } + + if (drvdata->value_table->condition_select) + memset(drvdata->value_table->condition_select, 0, + drvdata->max_condition_select * drvdata->max_step * + sizeof(unsigned int)); + + if (drvdata->value_table->timer) + memset(drvdata->value_table->timer, 0, + (drvdata->max_step) * + (drvdata->max_timer) * + sizeof(unsigned int)); + + if (drvdata->value_table->counter) + memset(drvdata->value_table->counter, 0, + (drvdata->max_step) * + (drvdata->max_counter) * + sizeof(unsigned int)); + + dev_dbg(dev, "Qualcomm-TGU reset complete\n"); + + drvdata->enable = false; + pm_runtime_put(drvdata->dev); + + return size; +} +static DEVICE_ATTR_WO(reset_tgu); + static struct attribute *tgu_common_attrs[] = { &dev_attr_enable_tgu.attr, + &dev_attr_reset_tgu.attr, NULL, }; From f6f9d38eee8f760dfce52094f30797902938fe95 Mon Sep 17 00:00:00 2001 From: Yingchao Deng Date: Tue, 2 Dec 2025 14:42:20 +0800 Subject: [PATCH 0072/1330] FROMLIST: coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays Replace the fixed-size u32 fields in the cti_config and cti_trig_grp structure with dynamically allocated bitmaps and arrays. This allows memory to be allocated based on the actual number of triggers during probe time, reducing memory footprint and improving scalability for platforms with varying trigger counts. Additionally, repack struct cti_config to reduce its size from 80 bytes to 72 bytes. Link: https://lore.kernel.org/all/20251202-extended_cti-v6-1-ab68bb15c4f5@oss.qualcomm.com/ Signed-off-by: Yingchao Deng --- .../hwtracing/coresight/coresight-cti-core.c | 58 ++++++++++++++----- .../coresight/coresight-cti-platform.c | 16 ++--- .../hwtracing/coresight/coresight-cti-sysfs.c | 10 +--- drivers/hwtracing/coresight/coresight-cti.h | 17 +++--- 4 files changed, 65 insertions(+), 36 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index bfbc365bb2ef2..f9970e40dd592 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -214,8 +214,8 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) -static void cti_set_default_config(struct device *dev, - struct cti_drvdata *drvdata) +static int cti_set_default_config(struct device *dev, + struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; u32 devid; @@ -234,12 +234,33 @@ static void cti_set_default_config(struct device *dev, config->nr_trig_max = CTIINOUTEN_MAX; } + config->trig_in_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); + if (!config->trig_in_use) + return -ENOMEM; + + config->trig_out_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); + if (!config->trig_out_use) + return -ENOMEM; + + config->trig_out_filter = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); + if (!config->trig_out_filter) + return -ENOMEM; + + config->ctiinen = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL); + if (!config->ctiinen) + return -ENOMEM; + + config->ctiouten = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL); + if (!config->ctiouten) + return -ENOMEM; + config->nr_ctm_channels = CTI_DEVID_CTMCHANNELS(devid); /* Most regs default to 0 as zalloc'ed except...*/ config->trig_filter_enable = true; config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0); config->enable_req_count = 0; + return 0; } /* @@ -270,8 +291,10 @@ int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata, cti_dev->nr_trig_con++; /* add connection usage bit info to overall info */ - drvdata->config.trig_in_use |= tc->con_in->used_mask; - drvdata->config.trig_out_use |= tc->con_out->used_mask; + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, + tc->con_in->used_mask, drvdata->config.nr_trig_max); + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, + tc->con_out->used_mask, drvdata->config.nr_trig_max); return 0; } @@ -293,12 +316,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, if (!in) return NULL; + in->used_mask = devm_bitmap_alloc(dev, in_sigs, GFP_KERNEL); + if (!in->used_mask) + return NULL; + out = devm_kzalloc(dev, offsetof(struct cti_trig_grp, sig_types[out_sigs]), GFP_KERNEL); if (!out) return NULL; + out->used_mask = devm_bitmap_alloc(dev, out_sigs, GFP_KERNEL); + if (!out->used_mask) + return NULL; + tc->con_in = in; tc->con_out = out; tc->con_in->nr_sigs = in_sigs; @@ -314,7 +345,6 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) { int ret = 0; int n_trigs = drvdata->config.nr_trig_max; - u32 n_trig_mask = GENMASK(n_trigs - 1, 0); struct cti_trig_con *tc = NULL; /* @@ -325,8 +355,9 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) if (!tc) return -ENOMEM; - tc->con_in->used_mask = n_trig_mask; - tc->con_out->used_mask = n_trig_mask; + bitmap_fill(tc->con_in->used_mask, n_trigs); + bitmap_fill(tc->con_out->used_mask, n_trigs); + ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); return ret; } @@ -339,7 +370,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, { struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cti_config *config = &drvdata->config; - u32 trig_bitmask; u32 chan_bitmask; u32 reg_value; int reg_offset; @@ -349,18 +379,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, (trigger_idx >= config->nr_trig_max)) return -EINVAL; - trig_bitmask = BIT(trigger_idx); - /* ensure registered triggers and not out filtered */ if (direction == CTI_TRIG_IN) { - if (!(trig_bitmask & config->trig_in_use)) + if (!(test_bit(trigger_idx, config->trig_in_use))) return -EINVAL; } else { - if (!(trig_bitmask & config->trig_out_use)) + if (!(test_bit(trigger_idx, config->trig_out_use))) return -EINVAL; if ((config->trig_filter_enable) && - (config->trig_out_filter & trig_bitmask)) + test_bit(trigger_idx, config->trig_out_filter)) return -EINVAL; } @@ -892,7 +920,9 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) raw_spin_lock_init(&drvdata->spinlock); /* initialise CTI driver config values */ - cti_set_default_config(dev, drvdata); + ret = cti_set_default_config(dev, drvdata); + if (ret) + return ret; pdata = coresight_cti_get_platform_data(dev); if (IS_ERR(pdata)) { diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c index 4eff96f48594e..af5f45c6fcf0f 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct device *dev, goto create_v8_etm_out; /* build connection data */ - tc->con_in->used_mask = 0xF0; /* sigs <4,5,6,7> */ - tc->con_out->used_mask = 0xF0; /* sigs <4,5,6,7> */ + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ /* * The EXTOUT type signals from the ETM are connected to a set of input @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct device *dev, goto of_create_v8_out; /* Set the v8 PE CTI connection data */ - tc->con_in->used_mask = 0x3; /* sigs <0 1> */ + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ tc->con_in->sig_types[0] = PE_DBGTRIGGER; tc->con_in->sig_types[1] = PE_PMUIRQ; - tc->con_out->used_mask = 0x7; /* sigs <0 1 2 > */ + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ tc->con_out->sig_types[0] = PE_EDBGREQ; tc->con_out->sig_types[1] = PE_DBGRESTART; tc->con_out->sig_types[2] = PE_CTIIRQ; @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device *dev, goto of_create_v8_out; /* filter pe_edbgreq - PE trigout sig <0> */ - drvdata->config.trig_out_filter |= 0x1; + set_bit(0, drvdata->config.trig_out_filter); of_create_v8_out: return ret; @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp *tgrp, if (!err) { /* set the signal usage mask */ for (idx = 0; idx < tgrp->nr_sigs; idx++) - tgrp->used_mask |= BIT(values[idx]); + set_bit(values[idx], tgrp->used_mask); } kfree(values); @@ -331,7 +331,9 @@ static int cti_plat_process_filter_sigs(struct cti_drvdata *drvdata, err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); if (!err) - drvdata->config.trig_out_filter |= tg->used_mask; + bitmap_or(drvdata->config.trig_out_filter, + drvdata->config.trig_out_filter, + tg->used_mask, drvdata->config.nr_trig_max); kfree(tg); return err; diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 572b80ee96fbf..a9df772151412 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -711,10 +711,8 @@ static ssize_t trigout_filtered_show(struct device *dev, struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cti_config *cfg = &drvdata->config; int size = 0, nr_trig_max = cfg->nr_trig_max; - unsigned long mask = cfg->trig_out_filter; - if (mask) - size = bitmap_print_to_pagebuf(true, buf, &mask, nr_trig_max); + size = bitmap_print_to_pagebuf(true, buf, cfg->trig_out_filter, nr_trig_max); return size; } static DEVICE_ATTR_RO(trigout_filtered); @@ -926,9 +924,8 @@ static ssize_t trigin_sig_show(struct device *dev, struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cti_config *cfg = &drvdata->config; - unsigned long mask = con->con_in->used_mask; - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); + return bitmap_print_to_pagebuf(true, buf, con->con_in->used_mask, cfg->nr_trig_max); } static ssize_t trigout_sig_show(struct device *dev, @@ -940,9 +937,8 @@ static ssize_t trigout_sig_show(struct device *dev, struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cti_config *cfg = &drvdata->config; - unsigned long mask = con->con_out->used_mask; - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); + return bitmap_print_to_pagebuf(true, buf, con->con_out->used_mask, cfg->nr_trig_max); } /* convert a sig type id to a name */ diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 4f89091ee93f5..e7b88b07cffec 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -68,7 +68,7 @@ struct fwnode_handle; */ struct cti_trig_grp { int nr_sigs; - u32 used_mask; + unsigned long *used_mask; int sig_types[]; }; @@ -146,20 +146,21 @@ struct cti_config { bool hw_enabled; bool hw_powered; - /* registered triggers and filtering */ - u32 trig_in_use; - u32 trig_out_use; - u32 trig_out_filter; bool trig_filter_enable; u8 xtrig_rchan_sel; /* cti cross trig programmable regs */ - u32 ctiappset; u8 ctiinout_sel; - u32 ctiinen[CTIINOUTEN_MAX]; - u32 ctiouten[CTIINOUTEN_MAX]; + u32 ctiappset; u32 ctigate; u32 asicctl; + u32 *ctiinen; + u32 *ctiouten; + + /* registered triggers and filtering */ + unsigned long *trig_in_use; + unsigned long *trig_out_use; + unsigned long *trig_out_filter; }; /** From f66c997e8f1e45c8d4a58e3d2b6ce9c155881b16 Mon Sep 17 00:00:00 2001 From: Yingchao Deng Date: Tue, 2 Dec 2025 14:42:21 +0800 Subject: [PATCH 0073/1330] FROMLIST: coresight: cti: Add Qualcomm extended CTI support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. Qualcomm CTI implementation differs from the standard CTI in the following aspects: 1. The number of supported triggers is extended to 128. 2. Several register offsets differ from the CoreSight specification. Link: https://lore.kernel.org/all/20251202-extended_cti-v6-2-ab68bb15c4f5@oss.qualcomm.com/ Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng --- .../testing/sysfs-bus-coresight-devices-cti | 11 ++ .../hwtracing/coresight/coresight-cti-core.c | 95 ++++++++-- .../hwtracing/coresight/coresight-cti-sysfs.c | 177 ++++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 43 ++++- drivers/hwtracing/coresight/qcom-cti.h | 29 +++ 5 files changed, 304 insertions(+), 51 deletions(-) create mode 100644 drivers/hwtracing/coresight/qcom-cti.h diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti index a2aef7f5a6d74..9478dfcee03b6 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti @@ -245,3 +245,14 @@ Date: Aug 2025 KernelVersion 6.18 Contact: Mao Jinlong Description: (Read) Show hardware context information of device. + +What: /sys/bus/coresight/devices//regs/ext_reg_sel +Date: Dec 2025 +KernelVersion: 6.19 +Contact: Mao Jinlong +Description: (RW) Select the index for extended registers. + QCOM CTI supports up to 128 triggers, there are 6 registers + need to be expanded to up to 4 instances: + CTITRIGINSTATUS, CTITRIGOUTSTATUS, + ITTRIGIN, ITTRIGOUT, + ITTRIGINACK, ITTRIGOUTACK. diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index f9970e40dd592..51b3644e97c4a 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -21,6 +21,55 @@ #include "coresight-priv.h" #include "coresight-cti.h" +#include "qcom-cti.h" + +static const u32 cti_normal_offset[] = { + [INDEX_CTIINTACK] = CTIINTACK, + [INDEX_CTIAPPSET] = CTIAPPSET, + [INDEX_CTIAPPCLEAR] = CTIAPPCLEAR, + [INDEX_CTIAPPPULSE] = CTIAPPPULSE, + [INDEX_CTIINEN] = CTIINEN(0), + [INDEX_CTIOUTEN] = CTIOUTEN(0), + [INDEX_CTITRIGINSTATUS] = CTITRIGINSTATUS, + [INDEX_CTITRIGOUTSTATUS] = CTITRIGOUTSTATUS, + [INDEX_CTICHINSTATUS] = CTICHINSTATUS, + [INDEX_CTICHOUTSTATUS] = CTICHOUTSTATUS, + [INDEX_CTIGATE] = CTIGATE, + [INDEX_ASICCTL] = ASICCTL, + [INDEX_ITCHINACK] = ITCHINACK, + [INDEX_ITTRIGINACK] = ITTRIGINACK, + [INDEX_ITCHOUT] = ITCHOUT, + [INDEX_ITTRIGOUT] = ITTRIGOUT, + [INDEX_ITCHOUTACK] = ITCHOUTACK, + [INDEX_ITTRIGOUTACK] = ITTRIGOUTACK, + [INDEX_ITCHIN] = ITCHIN, + [INDEX_ITTRIGIN] = ITTRIGIN, + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, +}; + +static const u32 cti_extended_offset[] = { + [INDEX_CTIINTACK] = QCOM_CTIINTACK, + [INDEX_CTIAPPSET] = QCOM_CTIAPPSET, + [INDEX_CTIAPPCLEAR] = QCOM_CTIAPPCLEAR, + [INDEX_CTIAPPPULSE] = QCOM_CTIAPPPULSE, + [INDEX_CTIINEN] = QCOM_CTIINEN, + [INDEX_CTIOUTEN] = QCOM_CTIOUTEN, + [INDEX_CTITRIGINSTATUS] = QCOM_CTITRIGINSTATUS, + [INDEX_CTITRIGOUTSTATUS] = QCOM_CTITRIGOUTSTATUS, + [INDEX_CTICHINSTATUS] = QCOM_CTICHINSTATUS, + [INDEX_CTICHOUTSTATUS] = QCOM_CTICHOUTSTATUS, + [INDEX_CTIGATE] = QCOM_CTIGATE, + [INDEX_ASICCTL] = QCOM_ASICCTL, + [INDEX_ITCHINACK] = QCOM_ITCHINACK, + [INDEX_ITTRIGINACK] = QCOM_ITTRIGINACK, + [INDEX_ITCHOUT] = QCOM_ITCHOUT, + [INDEX_ITTRIGOUT] = QCOM_ITTRIGOUT, + [INDEX_ITCHOUTACK] = QCOM_ITCHOUTACK, + [INDEX_ITTRIGOUTACK] = QCOM_ITTRIGOUTACK, + [INDEX_ITCHIN] = QCOM_ITCHIN, + [INDEX_ITTRIGIN] = QCOM_ITTRIGIN, + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, +}; /* * CTI devices can be associated with a PE, or be connected to CoreSight @@ -70,15 +119,16 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) /* write the CTI trigger registers */ for (i = 0; i < config->nr_trig_max; i++) { - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); + writel_relaxed(config->ctiinen[i], + drvdata->base + cti_offset(drvdata, INDEX_CTIINEN, i)); writel_relaxed(config->ctiouten[i], - drvdata->base + CTIOUTEN(i)); + drvdata->base + cti_offset(drvdata, INDEX_CTIOUTEN, i)); } /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); + writel_relaxed(config->ctigate, drvdata->base + cti_offset(drvdata, INDEX_CTIGATE, 0)); + writel_relaxed(config->asicctl, drvdata->base + cti_offset(drvdata, INDEX_ASICCTL, 0)); + writel_relaxed(config->ctiappset, drvdata->base + cti_offset(drvdata, INDEX_CTIAPPSET, 0)); /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -214,6 +264,9 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) +/* DEVARCH[31:21] - ARCHITECT */ +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31)) + static int cti_set_default_config(struct device *dev, struct cti_drvdata *drvdata) { @@ -394,8 +447,8 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, /* update the local register values */ chan_bitmask = BIT(channel_idx); - reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) : - CTIOUTEN(trigger_idx)); + reg_offset = (direction == CTI_TRIG_IN ? cti_offset(drvdata, INDEX_CTIINEN, trigger_idx) : + cti_offset(drvdata, INDEX_CTIOUTEN, trigger_idx)); raw_spin_lock(&drvdata->spinlock); @@ -479,19 +532,19 @@ int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, case CTI_CHAN_SET: config->ctiappset |= chan_bitmask; reg_value = config->ctiappset; - reg_offset = CTIAPPSET; + reg_offset = cti_offset(drvdata, INDEX_CTIAPPSET, 0); break; case CTI_CHAN_CLR: config->ctiappset &= ~chan_bitmask; reg_value = chan_bitmask; - reg_offset = CTIAPPCLEAR; + reg_offset = cti_offset(drvdata, INDEX_CTIAPPCLEAR, 0); break; case CTI_CHAN_PULSE: config->ctiappset &= ~chan_bitmask; reg_value = chan_bitmask; - reg_offset = CTIAPPPULSE; + reg_offset = cti_offset(drvdata, INDEX_CTIAPPPULSE, 0); break; default: @@ -895,6 +948,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) struct coresight_desc cti_desc; struct coresight_platform_data *pdata = NULL; struct resource *res = &adev->res; + u32 devarch; /* driver data*/ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -981,9 +1035,28 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) drvdata->csdev_release = drvdata->csdev->dev.release; drvdata->csdev->dev.release = cti_device_release; + /* check architect value*/ + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { + drvdata->subtype = QCOM_CTI; + drvdata->offsets = cti_extended_offset; + /* + * QCOM CTI does not implement Claimtag functionality as + * per CoreSight specification, but its CLAIMSET register + * is incorrectly initialized to 0xF. This can mislead + * tools or drivers into thinking the component is claimed. + * + * Reset CLAIMSET to 0 to reflect that no claims are active. + */ + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); + } else { + drvdata->subtype = ARM_STD_CTI; + drvdata->offsets = cti_normal_offset; + } + /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); + dev_info(&drvdata->csdev->dev, "CTI initialized; subtype=%d\n", drvdata->subtype); return 0; pm_release: diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index a9df772151412..12a4953829994 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -172,9 +172,8 @@ static struct attribute *coresight_cti_attrs[] = { /* register based attributes */ -/* Read registers with power check only (no enable check). */ -static ssize_t coresight_cti_reg_show(struct device *dev, - struct device_attribute *attr, char *buf) +static ssize_t coresight_cti_mgmt_reg_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); @@ -189,6 +188,40 @@ static ssize_t coresight_cti_reg_show(struct device *dev, return sysfs_emit(buf, "0x%x\n", val); } +/* Read registers with power check only (no enable check). */ +static ssize_t coresight_cti_reg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); + u32 idx, val = 0; + + pm_runtime_get_sync(dev->parent); + raw_spin_lock(&drvdata->spinlock); + idx = drvdata->config.ext_reg_sel; + if (drvdata->config.hw_powered) { + switch (cti_attr->off) { + case INDEX_CTITRIGINSTATUS: + case INDEX_CTITRIGOUTSTATUS: + case INDEX_ITTRIGINACK: + case INDEX_ITTRIGOUT: + case INDEX_ITTRIGOUTACK: + case INDEX_ITTRIGIN: + val = readl_relaxed(drvdata->base + + cti_offset(drvdata, cti_attr->off, idx)); + break; + + default: + val = readl_relaxed(drvdata->base + cti_offset(drvdata, cti_attr->off, 0)); + break; + } + } + + raw_spin_unlock(&drvdata->spinlock); + pm_runtime_put_sync(dev->parent); + return sysfs_emit(buf, "0x%x\n", val); +} + /* Write registers with power check only (no enable check). */ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, struct device_attribute *attr, @@ -197,19 +230,39 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); unsigned long val = 0; + u32 idx; if (kstrtoul(buf, 0, &val)) return -EINVAL; pm_runtime_get_sync(dev->parent); raw_spin_lock(&drvdata->spinlock); - if (drvdata->config.hw_powered) - cti_write_single_reg(drvdata, cti_attr->off, val); + idx = drvdata->config.ext_reg_sel; + if (drvdata->config.hw_powered) { + switch (cti_attr->off) { + case INDEX_ITTRIGINACK: + case INDEX_ITTRIGOUT: + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, idx), val); + break; + + default: + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, 0), val); + break; + } + } raw_spin_unlock(&drvdata->spinlock); pm_runtime_put_sync(dev->parent); return size; } +#define coresight_cti_mgmt_reg(name, offset) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_cti_mgmt_reg_show, NULL), \ + offset \ + } \ + })[0].attr.attr) + #define coresight_cti_reg(name, offset) \ (&((struct cs_off_attribute[]) { \ { \ @@ -237,17 +290,17 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, /* coresight management registers */ static struct attribute *coresight_cti_mgmt_attrs[] = { - coresight_cti_reg(devaff0, CTIDEVAFF0), - coresight_cti_reg(devaff1, CTIDEVAFF1), - coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS), - coresight_cti_reg(devarch, CORESIGHT_DEVARCH), - coresight_cti_reg(devid, CORESIGHT_DEVID), - coresight_cti_reg(devtype, CORESIGHT_DEVTYPE), - coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0), - coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1), - coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2), - coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3), - coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4), + coresight_cti_mgmt_reg(devaff0, CTIDEVAFF0), + coresight_cti_mgmt_reg(devaff1, CTIDEVAFF1), + coresight_cti_mgmt_reg(authstatus, CORESIGHT_AUTHSTATUS), + coresight_cti_mgmt_reg(devarch, CORESIGHT_DEVARCH), + coresight_cti_mgmt_reg(devid, CORESIGHT_DEVID), + coresight_cti_mgmt_reg(devtype, CORESIGHT_DEVTYPE), + coresight_cti_mgmt_reg(pidr0, CORESIGHT_PERIPHIDR0), + coresight_cti_mgmt_reg(pidr1, CORESIGHT_PERIPHIDR1), + coresight_cti_mgmt_reg(pidr2, CORESIGHT_PERIPHIDR2), + coresight_cti_mgmt_reg(pidr3, CORESIGHT_PERIPHIDR3), + coresight_cti_mgmt_reg(pidr4, CORESIGHT_PERIPHIDR4), NULL, }; @@ -258,13 +311,15 @@ static struct attribute *coresight_cti_mgmt_attrs[] = { * If inaccessible & pcached_val not NULL then show cached value. */ static ssize_t cti_reg32_show(struct device *dev, char *buf, - u32 *pcached_val, int reg_offset) + u32 *pcached_val, int index) { u32 val = 0; struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cti_config *config = &drvdata->config; + int reg_offset; raw_spin_lock(&drvdata->spinlock); + reg_offset = cti_offset(drvdata, index, 0); if ((reg_offset >= 0) && cti_active(config)) { CS_UNLOCK(drvdata->base); val = readl_relaxed(drvdata->base + reg_offset); @@ -284,11 +339,12 @@ static ssize_t cti_reg32_show(struct device *dev, char *buf, * if reg_offset >= 0 then write through if enabled. */ static ssize_t cti_reg32_store(struct device *dev, const char *buf, - size_t size, u32 *pcached_val, int reg_offset) + size_t size, u32 *pcached_val, int index) { unsigned long val; struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cti_config *config = &drvdata->config; + int reg_offset; if (kstrtoul(buf, 0, &val)) return -EINVAL; @@ -298,6 +354,7 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, if (pcached_val) *pcached_val = (u32)val; + reg_offset = cti_offset(drvdata, index, 0); /* write through if offset and enabled */ if ((reg_offset >= 0) && cti_active(config)) cti_write_single_reg(drvdata, reg_offset, val); @@ -306,14 +363,14 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, } /* Standard macro for simple rw cti config registers */ -#define cti_config_reg32_rw(name, cfgname, offset) \ +#define cti_config_reg32_rw(name, cfgname, index) \ static ssize_t name##_show(struct device *dev, \ struct device_attribute *attr, \ char *buf) \ { \ struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ return cti_reg32_show(dev, buf, \ - &drvdata->config.cfgname, offset); \ + &drvdata->config.cfgname, index); \ } \ \ static ssize_t name##_store(struct device *dev, \ @@ -322,7 +379,7 @@ static ssize_t name##_store(struct device *dev, \ { \ struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ return cti_reg32_store(dev, buf, size, \ - &drvdata->config.cfgname, offset); \ + &drvdata->config.cfgname, index); \ } \ static DEVICE_ATTR_RW(name) @@ -356,6 +413,46 @@ static ssize_t inout_sel_store(struct device *dev, } static DEVICE_ATTR_RW(inout_sel); +/* + * QCOM CTI supports up to 128 triggers, there are 6 registers need to be + * expanded to up to 4 instances, and ext_reg_sel can be used to indicate + * which one is in use. + * CTITRIGINSTATUS, CTITRIGOUTSTATUS, + * ITTRIGIN, ITTRIGOUT, + * ITTRIGINACK, ITTRIGOUTACK. + */ +static ssize_t ext_reg_sel_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u32 val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + raw_spin_lock(&drvdata->spinlock); + val = drvdata->config.ext_reg_sel; + raw_spin_unlock(&drvdata->spinlock); + return sprintf(buf, "%d\n", val); +} + +static ssize_t ext_reg_sel_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + if (val > ((drvdata->config.nr_trig_max + 31) / 32 - 1)) + return -EINVAL; + + raw_spin_lock(&drvdata->spinlock); + drvdata->config.ext_reg_sel = val; + raw_spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ext_reg_sel); + static ssize_t inen_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -389,7 +486,7 @@ static ssize_t inen_store(struct device *dev, /* write through if enabled */ if (cti_active(config)) - cti_write_single_reg(drvdata, CTIINEN(index), val); + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIINEN, index), val); raw_spin_unlock(&drvdata->spinlock); return size; } @@ -428,7 +525,7 @@ static ssize_t outen_store(struct device *dev, /* write through if enabled */ if (cti_active(config)) - cti_write_single_reg(drvdata, CTIOUTEN(index), val); + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIOUTEN, index), val); raw_spin_unlock(&drvdata->spinlock); return size; } @@ -448,9 +545,9 @@ static ssize_t intack_store(struct device *dev, } static DEVICE_ATTR_WO(intack); -cti_config_reg32_rw(gate, ctigate, CTIGATE); -cti_config_reg32_rw(asicctl, asicctl, ASICCTL); -cti_config_reg32_rw(appset, ctiappset, CTIAPPSET); +cti_config_reg32_rw(gate, ctigate, INDEX_CTIGATE); +cti_config_reg32_rw(asicctl, asicctl, INDEX_ASICCTL); +cti_config_reg32_rw(appset, ctiappset, INDEX_CTIAPPSET); static ssize_t appclear_store(struct device *dev, struct device_attribute *attr, @@ -504,6 +601,7 @@ static DEVICE_ATTR_WO(apppulse); */ static struct attribute *coresight_cti_regs_attrs[] = { &dev_attr_inout_sel.attr, + &dev_attr_ext_reg_sel.attr, &dev_attr_inen.attr, &dev_attr_outen.attr, &dev_attr_gate.attr, @@ -512,20 +610,20 @@ static struct attribute *coresight_cti_regs_attrs[] = { &dev_attr_appset.attr, &dev_attr_appclear.attr, &dev_attr_apppulse.attr, - coresight_cti_reg(triginstatus, CTITRIGINSTATUS), - coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), - coresight_cti_reg(chinstatus, CTICHINSTATUS), - coresight_cti_reg(choutstatus, CTICHOUTSTATUS), + coresight_cti_reg(triginstatus, INDEX_CTITRIGINSTATUS), + coresight_cti_reg(trigoutstatus, INDEX_CTITRIGOUTSTATUS), + coresight_cti_reg(chinstatus, INDEX_CTICHINSTATUS), + coresight_cti_reg(choutstatus, INDEX_CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS - coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), - coresight_cti_reg(ittrigin, ITTRIGIN), - coresight_cti_reg(itchin, ITCHIN), - coresight_cti_reg_rw(ittrigout, ITTRIGOUT), - coresight_cti_reg_rw(itchout, ITCHOUT), - coresight_cti_reg(itchoutack, ITCHOUTACK), - coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), - coresight_cti_reg_wo(ittriginack, ITTRIGINACK), - coresight_cti_reg_wo(itchinack, ITCHINACK), + coresight_cti_reg_rw(itctrl, INDEX_ITCTRL), + coresight_cti_reg(ittrigin, INDEX_ITTRIGIN), + coresight_cti_reg(itchin, INDEX_ITCHIN), + coresight_cti_reg_rw(ittrigout, INDEX_ITTRIGOUT), + coresight_cti_reg_rw(itchout, INDEX_ITCHOUT), + coresight_cti_reg(itchoutack, INDEX_ITCHOUTACK), + coresight_cti_reg(ittrigoutack, INDEX_ITTRIGOUTACK), + coresight_cti_reg_wo(ittriginack, INDEX_ITTRIGINACK), + coresight_cti_reg_wo(itchinack, INDEX_ITCHINACK), #endif NULL, }; @@ -740,6 +838,7 @@ static ssize_t chan_xtrigs_reset_store(struct device *dev, config->ctiappset = 0; config->ctiinout_sel = 0; config->xtrig_rchan_sel = 0; + config->ext_reg_sel = 0; /* if enabled then write through */ if (cti_active(config)) diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index e7b88b07cffec..fdd6d8892a95a 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -57,7 +57,38 @@ struct fwnode_handle; * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ -#define CTIINOUTEN_MAX 32 +#define CTIINOUTEN_MAX 128 + +/* Qcom CTI supports up to 128 triggers*/ +enum cti_subtype { + ARM_STD_CTI, + QCOM_CTI, +}; + +/* These registers are remapped in Qcom CTI*/ +enum cti_offset_index { + INDEX_CTIINTACK, + INDEX_CTIAPPSET, + INDEX_CTIAPPCLEAR, + INDEX_CTIAPPPULSE, + INDEX_CTIINEN, + INDEX_CTIOUTEN, + INDEX_CTITRIGINSTATUS, + INDEX_CTITRIGOUTSTATUS, + INDEX_CTICHINSTATUS, + INDEX_CTICHOUTSTATUS, + INDEX_CTIGATE, + INDEX_ASICCTL, + INDEX_ITCHINACK, + INDEX_ITTRIGINACK, + INDEX_ITCHOUT, + INDEX_ITTRIGOUT, + INDEX_ITCHOUTACK, + INDEX_ITTRIGOUTACK, + INDEX_ITCHIN, + INDEX_ITTRIGIN, + INDEX_ITCTRL, +}; /** * Group of related trigger signals @@ -149,6 +180,9 @@ struct cti_config { bool trig_filter_enable; u8 xtrig_rchan_sel; + /* qcom_cti regs' index */ + u8 ext_reg_sel; + /* cti cross trig programmable regs */ u8 ctiinout_sel; u32 ctiappset; @@ -181,6 +215,8 @@ struct cti_drvdata { struct cti_config config; struct list_head node; void (*csdev_release)(struct device *dev); + enum cti_subtype subtype; + const u32 *offsets; }; /* @@ -235,6 +271,11 @@ struct coresight_platform_data * coresight_cti_get_platform_data(struct device *dev); const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); +static inline u32 cti_offset(struct cti_drvdata *drvdata, int index, int num) +{ + return drvdata->offsets[index] + 4 * num; +} + /* cti powered and enabled */ static inline bool cti_active(struct cti_config *cfg) { diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h new file mode 100644 index 0000000000000..3c46317dd81f5 --- /dev/null +++ b/drivers/hwtracing/coresight/qcom-cti.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#define ARCHITECT_QCOM 0x477 + +/* CTI programming registers */ +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08c +/* Integration test registers */ +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 From b19b55f1b1b1d16e5f85ae4243e17497bc08ad3f Mon Sep 17 00:00:00 2001 From: Yingchao Deng Date: Thu, 29 Jan 2026 22:25:07 +0800 Subject: [PATCH 0074/1330] FROMLIST: stm: class: Add MIPI OST protocol support Add MIPI OST(Open System Trace) protocol support for stm to format the traces. The OST Protocol abstracts the underlying layers from the sending and receiving applications, thus removing dependencies on the connection media and platform implementation. OST over STP packet consists of Header/Payload/End. Header is designed to include the information required by all OST packets. Information that is not shared by all packets is left to the higher layer protocols. Thus, the OST Protocol Header can be regarded as the first part of a complete OST Packet Header, while a higher layer header can be regarded as an extension designed for a specific purpose. +--------+--------+--------+--------+ | start |version |entity |protocol| +--------+--------+--------+--------+ | stm version | magic | +-----------------------------------+ | cpu | +-----------------------------------+ | timestamp | | | +-----------------------------------+ | tgid | | | +-----------------------------------+ | payload | +-----------------------------------+ | ... | end | +-----------------------------------+ In header, there will be STARTSIMPLE/VERSION/ENTITY/PROTOCOL. STARTSIMPLE is used to signal the beginning of a simplified OST protocol. The Version field is a one byte, unsigned number identifying the version of the OST Protocol. The Entity ID field is a one byte unsigned number that identifies the source. The Protocol ID field is a one byte unsigned number identifying the higher layer protocol of the OST Packet, i.e. identifying the format of the data after the OST Protocol Header. OST Control Protocol ID value represents the common control protocol, the remaining Protocol ID values may be used by any higher layer protocols capable of being transported by the OST Protocol. Link: https://lore.kernel.org/all/20260129-p_ost-v5-1-2b14fff39428@oss.qualcomm.com/ Co-developed-by: Tingwei Zhang Signed-off-by: Tingwei Zhang Co-developed-by: Yuanfang Zhang Signed-off-by: Yuanfang Zhang Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng --- .../ABI/testing/configfs-stp-policy-p_ost | 6 + Documentation/trace/p_ost.rst | 36 +++ drivers/hwtracing/stm/Kconfig | 14 ++ drivers/hwtracing/stm/Makefile | 2 + drivers/hwtracing/stm/p_ost.c | 236 ++++++++++++++++++ 5 files changed, 294 insertions(+) create mode 100644 Documentation/ABI/testing/configfs-stp-policy-p_ost create mode 100644 Documentation/trace/p_ost.rst create mode 100644 drivers/hwtracing/stm/p_ost.c diff --git a/Documentation/ABI/testing/configfs-stp-policy-p_ost b/Documentation/ABI/testing/configfs-stp-policy-p_ost new file mode 100644 index 0000000000000..3cc4b38b456ef --- /dev/null +++ b/Documentation/ABI/testing/configfs-stp-policy-p_ost @@ -0,0 +1,6 @@ +What: /config/stp-policy/:p_ost.//entity +Date: Jan 2026 +KernelVersion: 6.20 +Description: + Set the entity which is to identify the source, RW. + diff --git a/Documentation/trace/p_ost.rst b/Documentation/trace/p_ost.rst new file mode 100644 index 0000000000000..df93b889eb4ce --- /dev/null +++ b/Documentation/trace/p_ost.rst @@ -0,0 +1,36 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=================== +MIPI OST over STP +=================== + +The OST(Open System Trace) driver is used with STM class devices to +generate standardized trace stream. Trace sources can be identified +by different entity ids. + +CONFIG_STM_PROTO_OST is for p_ost driver enablement. Once this config +is enabled, you can select the p_ost protocol by command below: + +# mkdir /sys/kernel/config/stp-policy/stm0:p_ost.policy + +The policy name format is extended like this: + :. + +With coresight-stm device, it will be look like "stm0:p_ost.policy". + +With MIPI OST protocol driver, the attributes for each protocol node is: +# mkdir /sys/kernel/config/stp-policy/stm0:p_ost.policy/default +# ls /sys/kernel/config/stp-policy/stm0:p_ost.policy/default +channels entity masters + +The entity here is the set the entity that p_ost supports. Currently +p_ost supports ftrace, console and diag entity. + +Set entity: +# echo 'ftrace' > /sys/kernel/config/stp-policy/stm0:p_ost.policy/default/entity + +Get available and currently selected (shown in square brackets) entity that p_ost supports: +# cat /sys/kernel/config/stp-policy/stm0:p_ost.policy/default/entity +[ftrace] console diag + +See Documentation/ABI/testing/configfs-stp-policy-p_ost for more details. diff --git a/drivers/hwtracing/stm/Kconfig b/drivers/hwtracing/stm/Kconfig index cd7f0b0f3fbeb..91700ef69add2 100644 --- a/drivers/hwtracing/stm/Kconfig +++ b/drivers/hwtracing/stm/Kconfig @@ -40,6 +40,20 @@ config STM_PROTO_SYS_T If you don't know what this is, say N. +config STM_PROTO_OST + tristate "MIPI OST STM framing protocol driver" + default CONFIG_STM + help + This is an implementation of MIPI OST protocol to be used + over the STP transport. In addition to the data payload, it + also carries additional metadata for entity, better + means of trace source identification, etc. + + The receiving side must be able to decode this protocol in + addition to the MIPI STP, in order to extract the data. + + If you don't know what this is, say N. + config STM_DUMMY tristate "Dummy STM driver" help diff --git a/drivers/hwtracing/stm/Makefile b/drivers/hwtracing/stm/Makefile index 1692fcd292779..d9c8615849b95 100644 --- a/drivers/hwtracing/stm/Makefile +++ b/drivers/hwtracing/stm/Makefile @@ -5,9 +5,11 @@ stm_core-y := core.o policy.o obj-$(CONFIG_STM_PROTO_BASIC) += stm_p_basic.o obj-$(CONFIG_STM_PROTO_SYS_T) += stm_p_sys-t.o +obj-$(CONFIG_STM_PROTO_OST) += stm_p_ost.o stm_p_basic-y := p_basic.o stm_p_sys-t-y := p_sys-t.o +stm_p_ost-y := p_ost.o obj-$(CONFIG_STM_DUMMY) += dummy_stm.o diff --git a/drivers/hwtracing/stm/p_ost.c b/drivers/hwtracing/stm/p_ost.c new file mode 100644 index 0000000000000..51fffa9429597 --- /dev/null +++ b/drivers/hwtracing/stm/p_ost.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * MIPI OST framing protocol for STM devices. + */ + +#include +#include +#include +#include +#include "stm.h" + +/* + * OST Base Protocol Header + * + * Position Bits Field Name + * 0 8 STARTSIMPLE + * 1 8 Version + * 2 8 Entity ID + * 3 8 protocol ID + */ +#define OST_FIELD_STARTSIMPLE 0 +#define OST_FIELD_VERSION 8 +#define OST_FIELD_ENTITY 16 +#define OST_FIELD_PROTOCOL 24 + +#define OST_TOKEN_STARTSIMPLE 0x10 +#define OST_VERSION_MIPI1 0x10 + +/* entity id to identify the source*/ +#define OST_ENTITY_FTRACE 0x01 +#define OST_ENTITY_CONSOLE 0x02 +#define OST_ENTITY_DIAG 0xEE + +#define OST_CONTROL_PROTOCOL 0x0 + +#define DATA_HEADER ((OST_TOKEN_STARTSIMPLE << OST_FIELD_STARTSIMPLE) | \ + (OST_VERSION_MIPI1 << OST_FIELD_PROTOCOL) | \ + (OST_CONTROL_PROTOCOL << OST_FIELD_PROTOCOL)) + +#define STM_MAKE_VERSION(ma, mi) (((ma) << 8) | (mi)) +#define STM_HEADER_MAGIC (0x5953) + +enum ost_entity_type { + OST_ENTITY_TYPE_NONE, + OST_ENTITY_TYPE_FTRACE, + OST_ENTITY_TYPE_CONSOLE, + OST_ENTITY_TYPE_DIAG, +}; + +static const char * const str_ost_entity_type[] = { + [OST_ENTITY_TYPE_NONE] = "none", + [OST_ENTITY_TYPE_FTRACE] = "ftrace", + [OST_ENTITY_TYPE_CONSOLE] = "console", + [OST_ENTITY_TYPE_DIAG] = "diag", +}; + +static const u32 ost_entity_value[] = { + [OST_ENTITY_TYPE_NONE] = 0, + [OST_ENTITY_TYPE_FTRACE] = OST_ENTITY_FTRACE, + [OST_ENTITY_TYPE_CONSOLE] = OST_ENTITY_CONSOLE, + [OST_ENTITY_TYPE_DIAG] = OST_ENTITY_DIAG, +}; + +struct ost_policy_node { + enum ost_entity_type entity_type; +}; + +struct ost_output { + struct ost_policy_node node; +}; + +/* Set default entity type as none */ +static void ost_policy_node_init(void *priv) +{ + struct ost_policy_node *pn = priv; + + pn->entity_type = OST_ENTITY_TYPE_NONE; +} + +static int ost_output_open(void *priv, struct stm_output *output) +{ + struct ost_policy_node *pn = priv; + struct ost_output *opriv; + + opriv = kzalloc(sizeof(*opriv), GFP_ATOMIC); + if (!opriv) + return -ENOMEM; + + memcpy(&opriv->node, pn, sizeof(opriv->node)); + output->pdrv_private = opriv; + return 0; +} + +static void ost_output_close(struct stm_output *output) +{ + kfree(output->pdrv_private); +} + +static ssize_t ost_t_policy_entity_show(struct config_item *item, + char *page) +{ + struct ost_policy_node *pn = to_pdrv_policy_node(item); + ssize_t sz = 0; + int i; + + for (i = 1; i < ARRAY_SIZE(str_ost_entity_type); i++) { + if (i == pn->entity_type) + sz += sysfs_emit_at(page, sz, "[%s] ", str_ost_entity_type[i]); + else + sz += sysfs_emit_at(page, sz, "%s ", str_ost_entity_type[i]); + } + + sz += sysfs_emit_at(page, sz, "\n"); + return sz; +} + +static int entity_index(const char *str) +{ + int i; + + for (i = 1; i < ARRAY_SIZE(str_ost_entity_type); i++) { + if (sysfs_streq(str, str_ost_entity_type[i])) + return i; + } + + return 0; +} + +static ssize_t +ost_t_policy_entity_store(struct config_item *item, const char *page, + size_t count) +{ + struct ost_policy_node *pn = to_pdrv_policy_node(item); + int i; + + i = entity_index(page); + if (i) + pn->entity_type = i; + else + return -EINVAL; + + return count; +} +CONFIGFS_ATTR(ost_t_policy_, entity); + +static struct configfs_attribute *ost_t_policy_attrs[] = { + &ost_t_policy_attr_entity, + NULL, +}; + +static ssize_t +notrace ost_write(struct stm_data *data, struct stm_output *output, + unsigned int chan, const char *buf, size_t count, + struct stm_source_data *source) +{ + struct ost_output *op = output->pdrv_private; + unsigned int c = output->channel + chan; + unsigned int m = output->master; + const unsigned char nil = 0; + u32 header = DATA_HEADER; + struct trc_hdr { + u16 version; + u16 magic; + u32 cpu; + u64 timestamp; + u64 tgid; + } hdr; + ssize_t sz; + + /* + * Identify the source by entity type. + * If entity type is not set, return error value. + */ + if (op->node.entity_type) + header |= ost_entity_value[op->node.entity_type]; + else + return -EINVAL; + + /* + * STP framing rules for OST frames: + * * the first packet of the OST frame is marked; + * * the last packet is a FLAG with timestamped tag. + */ + /* Message layout: HEADER / DATA / TAIL */ + /* HEADER */ + sz = data->packet(data, m, c, STP_PACKET_DATA, STP_PACKET_MARKED, + 4, (u8 *)&header); + if (sz <= 0) + return sz; + + /* DATA */ + hdr.version = STM_MAKE_VERSION(0, 3); + hdr.magic = STM_HEADER_MAGIC; + hdr.cpu = raw_smp_processor_id(); + hdr.timestamp = sched_clock(); + hdr.tgid = task_tgid_nr(current); + sz = stm_data_write(data, m, c, false, &hdr, sizeof(hdr)); + if (sz <= 0) + return sz; + + sz = stm_data_write(data, m, c, false, buf, count); + + /* TAIL */ + if (sz > 0) + data->packet(data, m, c, STP_PACKET_FLAG, + STP_PACKET_TIMESTAMPED, 0, &nil); + + return sz; +} + +static const struct stm_protocol_driver ost_pdrv = { + .owner = THIS_MODULE, + .name = "p_ost", + .write = ost_write, + .policy_attr = ost_t_policy_attrs, + .output_open = ost_output_open, + .output_close = ost_output_close, + .policy_node_init = ost_policy_node_init, +}; + +static int ost_stm_init(void) +{ + return stm_register_protocol(&ost_pdrv); +} +module_init(ost_stm_init); + +static void ost_stm_exit(void) +{ + stm_unregister_protocol(&ost_pdrv); +} +module_exit(ost_stm_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MIPI Open System Trace STM framing protocol driver"); From 1e7a81095008e66bdff3e09c753cd1202dca3e6b Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:41 -0800 Subject: [PATCH 0075/1330] FROMLIST: dt-bindings: arm: coresight: Add 'qcom,cpu-bound-components' property Introduce the `qcom,cpu-bound-components` boolean property for CoreSight components (TMC, Funnel, and Replicator). This property indicates that the component is physically located within a CPU cluster power domain. Such components share the power state of the cluster and may require special handling (e.g., cross-CPU register access) compared to system-wide components. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-1-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 5 +++++ .../bindings/arm/arm,coresight-dynamic-replicator.yaml | 5 +++++ Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml index b74db15e5f8af..a4c7333e8359d 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml @@ -57,6 +57,11 @@ properties: power-domains: maxItems: 1 + qcom,cpu-bound-components: + type: boolean + description: + Indicates whether the funnel is located physically within cpu cluster. + label: description: Description of a coresight device. diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml index 17ea936b796fd..2c6e78f02ed84 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml @@ -67,6 +67,11 @@ properties: Indicates that the replicator will lose register context when AMBA clock is removed which is observed in some replicator designs. + qcom,cpu-bound-components: + type: boolean + description: + Indicates whether the replicator is located physically within cpu cluster. + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml index 96dd5b5f771a3..8c4f2244a5c74 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -86,6 +86,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 15 + qcom,cpu-bound-components: + type: boolean + description: + indicates whether the TMC-ETF is located physically within cpu cluster. + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false From 59d184b0e6c779890108100bc92d452127e5391a Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:42 -0800 Subject: [PATCH 0076/1330] FROMLIST: coresight-funnel: Support CPU cluster funnel initialization Funnels associated with CPU clusters reside in the cluster's power domain. Unlike dynamic funnels (which are typically system-wide), these per-cluster funnels are only accessible when the cluster is powered on. Standard runtime PM may not suffice to wake up a cluster from low-power states, making direct register access unreliable. Enhance the funnel driver to support these per-cluster devices: 1. Safe Initialization: - Identify CPU cluster funnels via "qcom,cpu-bound-components". - Use smp_call_function_single() to perform hardware initialization (claim tag clearing) on a CPU within the cluster. - Refactor the probe flow to encapsulate device registration in funnel_add_coresight_dev(). 2. Cross-CPU Enablement: - Update funnel_enable() to use smp_call_function_single() when enabling the hardware on a cluster-bound funnel. 3. Debug Interface Support: - Update funnel_ctrl_show() to safely read the control register via cross-CPU calls when necessary. This ensures that funnel operations remain safe and functional even when the associated CPU cluster is in aggressive low-power states. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-2-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../hwtracing/coresight/coresight-funnel.c | 183 +++++++++++++++--- 1 file changed, 152 insertions(+), 31 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 3b248e54471a3..a1264df84ab4c 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,7 @@ DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); * @csdev: component vitals needed by the framework. * @priority: port selection order. * @spinlock: serialize enable/disable operations. + * @supported_cpus: Represent the CPUs related to this funnel. */ struct funnel_drvdata { void __iomem *base; @@ -48,6 +50,13 @@ struct funnel_drvdata { struct coresight_device *csdev; unsigned long priority; raw_spinlock_t spinlock; + struct cpumask *supported_cpus; +}; + +struct funnel_smp_arg { + struct funnel_drvdata *drvdata; + int port; + int rc; }; static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) @@ -76,6 +85,33 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) return rc; } +static void funnel_enable_hw_smp_call(void *info) +{ + struct funnel_smp_arg *arg = info; + + arg->rc = dynamic_funnel_enable_hw(arg->drvdata, arg->port); +} + +static int funnel_enable_hw(struct funnel_drvdata *drvdata, int port) +{ + int cpu, ret; + struct funnel_smp_arg arg = { 0 }; + + if (!drvdata->supported_cpus) + return dynamic_funnel_enable_hw(drvdata, port); + + arg.drvdata = drvdata; + arg.port = port; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + funnel_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static int funnel_enable(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out) @@ -86,19 +122,24 @@ static int funnel_enable(struct coresight_device *csdev, bool first_enable = false; raw_spin_lock_irqsave(&drvdata->spinlock, flags); - if (in->dest_refcnt == 0) { - if (drvdata->base) - rc = dynamic_funnel_enable_hw(drvdata, in->dest_port); - if (!rc) - first_enable = true; - } - if (!rc) + + if (in->dest_refcnt == 0) + first_enable = true; + else in->dest_refcnt++; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); - if (first_enable) - dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", - in->dest_port); + if (first_enable) { + if (drvdata->base) + rc = funnel_enable_hw(drvdata, in->dest_port); + if (!rc) { + in->dest_refcnt++; + dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", + in->dest_port); + } + } + return rc; } @@ -188,15 +229,39 @@ static u32 get_funnel_ctrl_hw(struct funnel_drvdata *drvdata) return functl; } +static void get_funnel_ctrl_smp_call(void *info) +{ + struct funnel_smp_arg *arg = info; + + arg->rc = get_funnel_ctrl_hw(arg->drvdata); +} + static ssize_t funnel_ctrl_show(struct device *dev, struct device_attribute *attr, char *buf) { u32 val; + int cpu, ret; struct funnel_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct funnel_smp_arg arg = { 0 }; pm_runtime_get_sync(dev->parent); - - val = get_funnel_ctrl_hw(drvdata); + if (!drvdata->supported_cpus) { + val = get_funnel_ctrl_hw(drvdata); + } else { + arg.drvdata = drvdata; + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + get_funnel_ctrl_smp_call, &arg, 1); + if (!ret) + break; + } + if (!ret) { + val = arg.rc; + } else { + pm_runtime_put(dev->parent); + return ret; + } + } pm_runtime_put(dev->parent); @@ -211,22 +276,68 @@ static struct attribute *coresight_funnel_attrs[] = { }; ATTRIBUTE_GROUPS(coresight_funnel); +static void funnel_clear_self_claim_tag(struct funnel_drvdata *drvdata) +{ + struct csdev_access access = CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static void funnel_init_on_cpu(void *info) +{ + struct funnel_drvdata *drvdata = info; + + funnel_clear_self_claim_tag(drvdata); +} + +static int funnel_add_coresight_dev(struct device *dev) +{ + struct coresight_desc desc = { 0 }; + struct funnel_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata->base) { + desc.groups = coresight_funnel_groups; + desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); + } + + desc.name = coresight_alloc_device_name(&funnel_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type = CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.ops = &funnel_cs_ops; + desc.pdata = dev->platform_data; + desc.dev = dev; + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + return 0; +} + +static struct cpumask *funnel_get_supported_cpus(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd = pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + static int funnel_probe(struct device *dev, struct resource *res) { void __iomem *base; struct coresight_platform_data *pdata = NULL; struct funnel_drvdata *drvdata; - struct coresight_desc desc = { 0 }; - int ret; + int cpu, ret; if (is_of_node(dev_fwnode(dev)) && of_device_is_compatible(dev->of_node, "arm,coresight-funnel")) dev_warn_once(dev, "Uses OBSOLETE CoreSight funnel binding\n"); - desc.name = coresight_alloc_device_name(&funnel_devs, dev); - if (!desc.name) - return -ENOMEM; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; @@ -244,9 +355,6 @@ static int funnel_probe(struct device *dev, struct resource *res) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base = base; - desc.groups = coresight_funnel_groups; - desc.access = CSDEV_ACCESS_IOMEM(base); - coresight_clear_self_claim_tag(&desc.access); } dev_set_drvdata(dev, drvdata); @@ -258,23 +366,36 @@ static int funnel_probe(struct device *dev, struct resource *res) dev->platform_data = pdata; raw_spin_lock_init(&drvdata->spinlock); - desc.type = CORESIGHT_DEV_TYPE_LINK; - desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; - desc.ops = &funnel_cs_ops; - desc.pdata = pdata; - desc.dev = dev; - drvdata->csdev = coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) - return PTR_ERR(drvdata->csdev); - return 0; + if (fwnode_property_present(dev_fwnode(dev), "qcom,cpu-bound-components")) { + drvdata->supported_cpus = funnel_get_supported_cpus(dev); + if (!drvdata->supported_cpus) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + funnel_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); + + if (ret) + return 0; + } else if (res) { + funnel_clear_self_claim_tag(drvdata); + } + + return funnel_add_coresight_dev(dev); } static int funnel_remove(struct device *dev) { struct funnel_drvdata *drvdata = dev_get_drvdata(dev); - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); return 0; } From b3e834766454b819a1efa61986e8123de29c54e9 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:43 -0800 Subject: [PATCH 0077/1330] FROMLIST: coresight-funnel: Defer probe when associated CPUs are offline Per-cluster funnels rely on the associated CPU cluster being online to securely access registers during initialization. If all CPUs in the cluster are offline during probe, these operations fail. Support deferred initialization for these devices: 1. Track funnels that fail to probe due to offline CPUs in a global list. 2. Register a CPU hotplug notifier (funnel_online_cpu) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration with the CoreSight framework. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-3-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../hwtracing/coresight/coresight-funnel.c | 62 +++++++++++++++++-- 1 file changed, 57 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index a1264df84ab4c..5d114ce1109f4 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -32,6 +32,9 @@ #define FUNNEL_ENSx_MASK 0xff DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); +static LIST_HEAD(funnel_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); /** * struct funnel_drvdata - specifics associated to a funnel component @@ -42,6 +45,8 @@ DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); * @priority: port selection order. * @spinlock: serialize enable/disable operations. * @supported_cpus: Represent the CPUs related to this funnel. + * @dev: pointer to the device associated with this funnel. + * @link: list node for adding this funnel to the delayed probe list. */ struct funnel_drvdata { void __iomem *base; @@ -51,6 +56,8 @@ struct funnel_drvdata { unsigned long priority; raw_spinlock_t spinlock; struct cpumask *supported_cpus; + struct device *dev; + struct list_head link; }; struct funnel_smp_arg { @@ -371,7 +378,7 @@ static int funnel_probe(struct device *dev, struct resource *res) drvdata->supported_cpus = funnel_get_supported_cpus(dev); if (!drvdata->supported_cpus) return -EINVAL; - + drvdata->dev = dev; cpus_read_lock(); for_each_cpu(cpu, drvdata->supported_cpus) { ret = smp_call_function_single(cpu, @@ -379,10 +386,15 @@ static int funnel_probe(struct device *dev, struct resource *res) if (!ret) break; } - cpus_read_unlock(); - if (ret) + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &funnel_delay_probe); + cpus_read_unlock(); return 0; + } + + cpus_read_unlock(); } else if (res) { funnel_clear_self_claim_tag(drvdata); } @@ -394,9 +406,12 @@ static int funnel_remove(struct device *dev) { struct funnel_drvdata *drvdata = dev_get_drvdata(dev); - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); - + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } return 0; } @@ -533,8 +548,41 @@ static struct amba_driver dynamic_funnel_driver = { .id_table = dynamic_funnel_ids, }; +static int funnel_online_cpu(unsigned int cpu) +{ + struct funnel_drvdata *drvdata, *tmp; + int ret; + + list_for_each_entry_safe(drvdata, tmp, &funnel_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->supported_cpus)) { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + + ret = pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + funnel_clear_self_claim_tag(drvdata); + funnel_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + } + } + return 0; +} + static int __init funnel_init(void) { + int ret; + + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight-funnel:online", + funnel_online_cpu, NULL); + + if (ret > 0) + hp_online = ret; + else + return ret; + return coresight_init_driver("funnel", &dynamic_funnel_driver, &funnel_driver, THIS_MODULE); } @@ -542,6 +590,10 @@ static int __init funnel_init(void) static void __exit funnel_exit(void) { coresight_remove_driver(&dynamic_funnel_driver, &funnel_driver); + if (hp_online) { + cpuhp_remove_state_nocalls(hp_online); + hp_online = 0; + } } module_init(funnel_init); From 023593b77f4379fa84f68780f739e78cec706a5f Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:44 -0800 Subject: [PATCH 0078/1330] FROMLIST: coresight-replicator: Support CPU cluster replicator initialization Replicators associated with CPU clusters reside in the cluster's power domain. Unlike system-wide replicators, their registers are only accessible when the cluster is powered on. Standard runtime PM may not suffice to wake up a cluster from low-power states, making direct register access unreliable during initialization or operation. Enhance the replicator driver to support these per-cluster devices: 1. Safe Initialization: - Identify per-cluster replicators via device properties. - Use smp_call_function_single() to perform hardware initialization (reset and claim tag clearing) on a CPU within the cluster. - Refactor the probe flow to encapsulate device registration in replicator_add_coresight_dev(). 2. Cross-CPU Enablement: - Update replicator_enable() to use smp_call_function_single() when enabling the hardware on a cluster-bound replicator. 3. Claim/Disclaim Handling: - Introduce replicator_claim/disclaim_device_unlocked() to manage device access safely before full framework registration. This ensures that replicator operations remain robust even when the associated CPU cluster is in low-power states, while maintaining compatibility with existing system-level replicators. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-4-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../coresight/coresight-replicator.c | 200 +++++++++++++++--- 1 file changed, 167 insertions(+), 33 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index e6472658235dc..c11da452559c7 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,7 @@ DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); * @csdev: component vitals needed by the framework * @spinlock: serialize enable/disable operations. * @check_idfilter_val: check if the context is lost upon clock removal. + * @supported_cpus: Represent the CPUs related to this funnel. */ struct replicator_drvdata { void __iomem *base; @@ -43,18 +45,61 @@ struct replicator_drvdata { struct coresight_device *csdev; raw_spinlock_t spinlock; bool check_idfilter_val; + struct cpumask *supported_cpus; }; -static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) +struct replicator_smp_arg { + struct replicator_drvdata *drvdata; + int outport; + int rc; +}; + +static void replicator_clear_self_claim_tag(struct replicator_drvdata *drvdata) +{ + struct csdev_access access = CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static int replicator_claim_device_unlocked(struct replicator_drvdata *drvdata) +{ + struct coresight_device *csdev = drvdata->csdev; + struct csdev_access access = CSDEV_ACCESS_IOMEM(drvdata->base); + u32 claim_tag; + + if (csdev) + return coresight_claim_device_unlocked(csdev); + + writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, drvdata->base + CORESIGHT_CLAIMSET); + + claim_tag = readl_relaxed(drvdata->base + CORESIGHT_CLAIMCLR); + if (claim_tag != CORESIGHT_CLAIM_SELF_HOSTED) { + coresight_clear_self_claim_tag_unlocked(&access); + return -EBUSY; + } + + return 0; +} + +static void replicator_disclaim_device_unlocked(struct replicator_drvdata *drvdata) { struct coresight_device *csdev = drvdata->csdev; + struct csdev_access access = CSDEV_ACCESS_IOMEM(drvdata->base); + + if (csdev) + return coresight_disclaim_device_unlocked(csdev); + coresight_clear_self_claim_tag_unlocked(&access); +} + +static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) +{ CS_UNLOCK(drvdata->base); - if (!coresight_claim_device_unlocked(csdev)) { + if (!replicator_claim_device_unlocked(drvdata)) { writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); - coresight_disclaim_device_unlocked(csdev); + replicator_disclaim_device_unlocked(drvdata); } CS_LOCK(drvdata->base); @@ -116,6 +161,34 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, return rc; } +static void replicator_enable_hw_smp_call(void *info) +{ + struct replicator_smp_arg *arg = info; + + arg->rc = dynamic_replicator_enable(arg->drvdata, 0, arg->outport); +} + +static int replicator_enable_hw(struct replicator_drvdata *drvdata, + int inport, int outport) +{ + int cpu, ret; + struct replicator_smp_arg arg = { 0 }; + + if (!drvdata->supported_cpus) + return dynamic_replicator_enable(drvdata, 0, outport); + + arg.drvdata = drvdata; + arg.outport = outport; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, replicator_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + + return ret; +} + static int replicator_enable(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out) @@ -126,19 +199,24 @@ static int replicator_enable(struct coresight_device *csdev, bool first_enable = false; raw_spin_lock_irqsave(&drvdata->spinlock, flags); - if (out->src_refcnt == 0) { - if (drvdata->base) - rc = dynamic_replicator_enable(drvdata, in->dest_port, - out->src_port); - if (!rc) - first_enable = true; - } - if (!rc) + + if (out->src_refcnt == 0) + first_enable = true; + else out->src_refcnt++; raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); - if (first_enable) - dev_dbg(&csdev->dev, "REPLICATOR enabled\n"); + if (first_enable) { + if (drvdata->base) + rc = replicator_enable_hw(drvdata, in->dest_port, + out->src_port); + if (!rc) { + out->src_refcnt++; + dev_dbg(&csdev->dev, "REPLICATOR enabled\n"); + return rc; + } + } + return rc; } @@ -217,23 +295,69 @@ static const struct attribute_group *replicator_groups[] = { NULL, }; +static int replicator_add_coresight_dev(struct device *dev) +{ + struct coresight_desc desc = { 0 }; + struct replicator_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata->base) { + desc.groups = replicator_groups; + desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); + } + + desc.name = coresight_alloc_device_name(&replicator_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type = CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; + desc.ops = &replicator_cs_ops; + desc.pdata = dev->platform_data; + desc.dev = dev; + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + return 0; +} + +static void replicator_init_hw(struct replicator_drvdata *drvdata) +{ + replicator_clear_self_claim_tag(drvdata); + replicator_reset(drvdata); +} + +static void replicator_init_on_cpu(void *info) +{ + struct replicator_drvdata *drvdata = info; + + replicator_init_hw(drvdata); +} + +static struct cpumask *replicator_get_supported_cpus(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd = pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + static int replicator_probe(struct device *dev, struct resource *res) { struct coresight_platform_data *pdata = NULL; struct replicator_drvdata *drvdata; - struct coresight_desc desc = { 0 }; void __iomem *base; - int ret; + int cpu, ret; if (is_of_node(dev_fwnode(dev)) && of_device_is_compatible(dev->of_node, "arm,coresight-replicator")) dev_warn_once(dev, "Uses OBSOLETE CoreSight replicator binding\n"); - desc.name = coresight_alloc_device_name(&replicator_devs, dev); - if (!desc.name) - return -ENOMEM; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; @@ -251,9 +375,6 @@ static int replicator_probe(struct device *dev, struct resource *res) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base = base; - desc.groups = replicator_groups; - desc.access = CSDEV_ACCESS_IOMEM(base); - coresight_clear_self_claim_tag(&desc.access); } if (fwnode_property_present(dev_fwnode(dev), @@ -268,25 +389,38 @@ static int replicator_probe(struct device *dev, struct resource *res) dev->platform_data = pdata; raw_spin_lock_init(&drvdata->spinlock); - desc.type = CORESIGHT_DEV_TYPE_LINK; - desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; - desc.ops = &replicator_cs_ops; - desc.pdata = dev->platform_data; - desc.dev = dev; - drvdata->csdev = coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) - return PTR_ERR(drvdata->csdev); + if (fwnode_property_present(dev_fwnode(dev), "qcom,cpu-bound-components")) { + drvdata->supported_cpus = replicator_get_supported_cpus(dev); + if (!drvdata->supported_cpus) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + replicator_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); - replicator_reset(drvdata); - return 0; + if (ret) + return 0; + } else if (res) { + replicator_init_hw(drvdata); + } + + ret = replicator_add_coresight_dev(dev); + + return ret; } static int replicator_remove(struct device *dev) { struct replicator_drvdata *drvdata = dev_get_drvdata(dev); - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); return 0; } From d6d63c925f97d4ae9b6fcede297752cbbf8e34b7 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:45 -0800 Subject: [PATCH 0079/1330] FROMLIST: coresight-replicator: Defer probe when associated CPUs are offline Per-cluster replicators rely on the associated CPU cluster being online to securely access registers during initialization. If all CPUs in the cluster are offline during probe, these operations fail. Support deferred initialization for these devices: 1. Track replicators that fail to probe due to offline CPUs in a global list. 2. Register a CPU hotplug notifier (`replicator_online_cpu`) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration with the CoreSight framework. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-5-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../coresight/coresight-replicator.c | 65 +++++++++++++++++-- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index c11da452559c7..f8d13894098f1 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -26,6 +26,9 @@ #define REPLICATOR_IDFILTER1 0x004 DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); +static LIST_HEAD(replicator_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); /** * struct replicator_drvdata - specifics associated to a replicator component @@ -37,6 +40,8 @@ DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); * @spinlock: serialize enable/disable operations. * @check_idfilter_val: check if the context is lost upon clock removal. * @supported_cpus: Represent the CPUs related to this funnel. + * @dev: pointer to the device associated with this replicator. + * @link: link to the delay_probed list. */ struct replicator_drvdata { void __iomem *base; @@ -46,6 +51,8 @@ struct replicator_drvdata { raw_spinlock_t spinlock; bool check_idfilter_val; struct cpumask *supported_cpus; + struct device *dev; + struct list_head link; }; struct replicator_smp_arg { @@ -394,7 +401,7 @@ static int replicator_probe(struct device *dev, struct resource *res) drvdata->supported_cpus = replicator_get_supported_cpus(dev); if (!drvdata->supported_cpus) return -EINVAL; - + drvdata->dev = dev; cpus_read_lock(); for_each_cpu(cpu, drvdata->supported_cpus) { ret = smp_call_function_single(cpu, @@ -402,10 +409,15 @@ static int replicator_probe(struct device *dev, struct resource *res) if (!ret) break; } - cpus_read_unlock(); - if (ret) + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &replicator_delay_probe); + cpus_read_unlock(); return 0; + } + + cpus_read_unlock(); } else if (res) { replicator_init_hw(drvdata); } @@ -419,8 +431,13 @@ static int replicator_remove(struct device *dev) { struct replicator_drvdata *drvdata = dev_get_drvdata(dev); - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } + return 0; } @@ -552,8 +569,44 @@ static struct amba_driver dynamic_replicator_driver = { .id_table = dynamic_replicator_ids, }; +static int replicator_online_cpu(unsigned int cpu) +{ + struct replicator_drvdata *drvdata, *tmp; + int ret; + + spin_lock(&delay_lock); + list_for_each_entry_safe(drvdata, tmp, &replicator_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->supported_cpus)) { + list_del(&drvdata->link); + spin_unlock(&delay_lock); + ret = pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + replicator_clear_self_claim_tag(drvdata); + replicator_reset(drvdata); + replicator_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + spin_lock(&delay_lock); + } + } + spin_unlock(&delay_lock); + return 0; +} + static int __init replicator_init(void) { + int ret; + + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight-replicator:online", + replicator_online_cpu, NULL); + + if (ret > 0) + hp_online = ret; + else + return ret; + return coresight_init_driver("replicator", &dynamic_replicator_driver, &replicator_driver, THIS_MODULE); } @@ -561,6 +614,10 @@ static int __init replicator_init(void) static void __exit replicator_exit(void) { coresight_remove_driver(&dynamic_replicator_driver, &replicator_driver); + if (hp_online) { + cpuhp_remove_state_nocalls(hp_online); + hp_online = 0; + } } module_init(replicator_init); From a81e109a5921e2d2fb9adf5c247eb9c5028a1fa2 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:46 -0800 Subject: [PATCH 0080/1330] FROMLIST: coresight-replicator: Update management interface for CPU-bound devices Standard system replicators allow direct register access from any CPU. However, replicators associated with specific CPU clusters share the cluster's power domain and require access via a CPU within that domain. Replace the standard `coresight_simple_reg*` accessors with custom handlers (`coresight_replicator_reg*`) to support these devices: - For cluster-bound replicators (indicated by `supported_cpus`), use `smp_call_function_single()` to read registers on an associated CPU. - For standard replicators, retain the direct access behavior. This ensures correct operation for per-cluster replicators while maintaining compatibility for existing system-level devices. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-6-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../coresight/coresight-replicator.c | 61 ++++++++++++++++++- 1 file changed, 59 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index f8d13894098f1..a9f22d0e15de2 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -58,6 +58,7 @@ struct replicator_drvdata { struct replicator_smp_arg { struct replicator_drvdata *drvdata; int outport; + u32 offset; int rc; }; @@ -286,9 +287,65 @@ static const struct coresight_ops replicator_cs_ops = { .link_ops = &replicator_link_ops, }; +static void replicator_read_register_smp_call(void *info) +{ + struct replicator_smp_arg *arg = info; + + arg->rc = readl_relaxed(arg->drvdata->base + arg->offset); +} + +static ssize_t coresight_replicator_reg32_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct replicator_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cs_off_attribute *cs_attr = container_of(attr, struct cs_off_attribute, attr); + unsigned long flags; + struct replicator_smp_arg arg = { 0 }; + u32 val; + int ret, cpu; + + pm_runtime_get_sync(dev->parent); + + if (!drvdata->supported_cpus) { + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + val = readl_relaxed(drvdata->base + cs_attr->off); + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + + } else { + arg.drvdata = drvdata; + arg.offset = cs_attr->off; + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + replicator_read_register_smp_call, + &arg, 1); + if (!ret) + break; + } + if (!ret) { + val = arg.rc; + } else { + pm_runtime_put_sync(dev->parent); + return ret; + } + } + + pm_runtime_put_sync(dev->parent); + + return sysfs_emit(buf, "0x%x\n", val); +} + +#define coresight_replicator_reg32(name, offset) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_replicator_reg32_show, NULL), \ + offset \ + } \ + })[0].attr.attr) + static struct attribute *replicator_mgmt_attrs[] = { - coresight_simple_reg32(idfilter0, REPLICATOR_IDFILTER0), - coresight_simple_reg32(idfilter1, REPLICATOR_IDFILTER1), + coresight_replicator_reg32(idfilter0, REPLICATOR_IDFILTER0), + coresight_replicator_reg32(idfilter1, REPLICATOR_IDFILTER1), NULL, }; From 3724a343631d1e621abe8ee6243e3d47cd7652ab Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:47 -0800 Subject: [PATCH 0081/1330] FROMLIST: coresight-tmc: Support probe and initialization for CPU cluster TMCs TMC instances associated with CPU clusters reside in the cluster's power domain. Unlike system-level TMCs, their registers are only accessible when the cluster is powered on. Standard runtime PM may not suffice to wake up a cluster from low-power states during probe, making direct register access unreliable. Refactor the probe sequence to handle these per-cluster devices safely: 1. Identify per-cluster TMCs using the "qcom,cpu-bound-components" property. 2. For such devices, use `smp_call_function_single()` to perform hardware initialization (`tmc_init_hw_config`) on a CPU within the cluster. This ensures the domain is powered during access. 3. Factor out the device registration logic into `tmc_add_coresight_dev()`. This allows common registration code to be shared between the standard probe path and the deferred probe path (used when the associated CPUs are initially offline). This change ensures reliable initialization for per-cluster TMCs while maintaining backward compatibility for standard system-level TMCs. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-7-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../hwtracing/coresight/coresight-tmc-core.c | 195 +++++++++++------- drivers/hwtracing/coresight/coresight-tmc.h | 6 + 2 files changed, 132 insertions(+), 69 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 6486bdafdddc4..d9d366f9d219d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -810,56 +811,14 @@ static const struct tmc_sysfs_ops etr_sysfs_ops = { .get_trace_data = tmc_etr_get_sysfs_trace, }; -static int __tmc_probe(struct device *dev, struct resource *res) +static int tmc_add_coresight_dev(struct device *dev) { - int ret = 0; - u32 devid; - void __iomem *base; - struct coresight_platform_data *pdata = NULL; - struct tmc_drvdata *drvdata; + struct tmc_drvdata *drvdata = dev_get_drvdata(dev); struct coresight_desc desc = { 0 }; struct coresight_dev_list *dev_list = NULL; + int ret = 0; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); - if (ret) - return ret; - - ret = -ENOMEM; - - /* Validity for the resource is already checked by the AMBA core */ - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) { - ret = PTR_ERR(base); - goto out; - } - - drvdata->base = base; - desc.access = CSDEV_ACCESS_IOMEM(base); - - raw_spin_lock_init(&drvdata->spinlock); - - devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); - drvdata->config_type = BMVAL(devid, 6, 7); - drvdata->memwidth = tmc_get_memwidth(devid); - /* This device is not associated with a session */ - drvdata->pid = -1; - drvdata->etr_mode = ETR_MODE_AUTO; - - if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { - drvdata->size = tmc_etr_get_default_buffer_size(dev); - drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev); - } else { - drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; - } - - tmc_get_reserved_region(dev); - + desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); desc.dev = dev; switch (drvdata->config_type) { @@ -876,9 +835,9 @@ static int __tmc_probe(struct device *dev, struct resource *res) desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; desc.ops = &tmc_etr_cs_ops; - ret = tmc_etr_setup_caps(dev, devid, &desc.access); + ret = tmc_etr_setup_caps(dev, drvdata->devid, &desc.access); if (ret) - goto out; + return ret; idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list = &etr_devs; @@ -896,44 +855,141 @@ static int __tmc_probe(struct device *dev, struct resource *res) break; default: pr_err("%s: Unsupported TMC config\n", desc.name); - ret = -EINVAL; - goto out; + return -EINVAL; } desc.name = coresight_alloc_device_name(dev_list, dev); - if (!desc.name) { - ret = -ENOMEM; + if (!desc.name) + return -ENOMEM; + + drvdata->desc_name = desc.name; + + desc.pdata = dev->platform_data; + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = desc.name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &tmc_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) + coresight_unregister(drvdata->csdev); + + return ret; +} + +static void tmc_clear_self_claim_tag(struct tmc_drvdata *drvdata) +{ + struct csdev_access access = CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static void tmc_init_hw_config(struct tmc_drvdata *drvdata) +{ + u32 devid; + + devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); + drvdata->config_type = BMVAL(devid, 6, 7); + drvdata->memwidth = tmc_get_memwidth(devid); + drvdata->devid = devid; + drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; + tmc_clear_self_claim_tag(drvdata); +} + +static void tmc_init_on_cpu(void *info) +{ + struct tmc_drvdata *drvdata = info; + + tmc_init_hw_config(drvdata); +} + +static struct cpumask *tmc_get_supported_cpus(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd = pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + +static int __tmc_probe(struct device *dev, struct resource *res) +{ + int cpu, ret = 0; + void __iomem *base; + struct coresight_platform_data *pdata = NULL; + struct tmc_drvdata *drvdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); + if (ret) + return ret; + + ret = -ENOMEM; + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); goto out; } + drvdata->base = base; + + raw_spin_lock_init(&drvdata->spinlock); + /* This device is not associated with a session */ + drvdata->pid = -1; + drvdata->etr_mode = ETR_MODE_AUTO; + tmc_get_reserved_region(dev); + pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) { ret = PTR_ERR(pdata); goto out; } dev->platform_data = pdata; - desc.pdata = pdata; - coresight_clear_self_claim_tag(&desc.access); - drvdata->csdev = coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) { - ret = PTR_ERR(drvdata->csdev); - goto out; + if (fwnode_property_present(dev_fwnode(dev), "qcom,cpu-bound-components")) { + drvdata->supported_cpus = tmc_get_supported_cpus(dev); + if (!drvdata->supported_cpus) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + tmc_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); + if (ret) { + ret = 0; + goto out; + } + } else { + tmc_init_hw_config(drvdata); } - drvdata->miscdev.name = desc.name; - drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; - drvdata->miscdev.fops = &tmc_fops; - ret = misc_register(&drvdata->miscdev); - if (ret) { - coresight_unregister(drvdata->csdev); - goto out; + if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { + drvdata->size = tmc_etr_get_default_buffer_size(dev); + drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev); } + ret = tmc_add_coresight_dev(dev); + out: if (is_tmc_crashdata_valid(drvdata) && !tmc_prepare_crashdata(drvdata)) - register_crash_dev_interface(drvdata, desc.name); + register_crash_dev_interface(drvdata, drvdata->desc_name); return ret; } @@ -979,10 +1035,12 @@ static void __tmc_remove(struct device *dev) * etb fops in this case, device is there until last file * handler to this device is closed. */ - misc_deregister(&drvdata->miscdev); + if (!drvdata->supported_cpus) + misc_deregister(&drvdata->miscdev); if (drvdata->crashdev.fops) misc_deregister(&drvdata->crashdev); - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); } static void tmc_remove(struct amba_device *adev) @@ -1037,7 +1095,6 @@ static void tmc_platform_remove(struct platform_device *pdev) if (WARN_ON(!drvdata)) return; - __tmc_remove(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index d60c70530c8a3..42fa61ee0ad2d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -261,6 +261,9 @@ struct etr_buf_node { * @etr_buf_list: List that is used to manage allocated etr_buf. * @reading_node: Available buffer_node for byte-cntr reading. * @sysfs_ops: Read operations for sysfs mode. + * @supported_cpus: Represent the CPUs related to this TMC. + * @devid: TMC variant ID inferred from the device configuration register. + * @desc_name: Name to be used while creating crash interface. */ struct tmc_drvdata { struct clk *atclk; @@ -294,6 +297,9 @@ struct tmc_drvdata { struct list_head etr_buf_list; struct etr_buf_node *reading_node; const struct tmc_sysfs_ops *sysfs_ops; + struct cpumask *supported_cpus; + u32 devid; + const char *desc_name; }; /** From f2d65d9fff57a748e8c7ac7ad02446be493fe21e Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:48 -0800 Subject: [PATCH 0082/1330] FROMLIST: coresight-tmc-etf: Refactor enable function for CPU cluster ETF support TMC-ETF devices associated with specific CPU clusters share the cluster's power domain. Accessing their registers requires the cluster to be powered on, which can only be guaranteed by running code on a CPU within that cluster. Refactor the enablement logic to support this requirement: 1. Split `tmc_etf_enable_hw` and `tmc_etb_enable_hw` into local and SMP-aware variants: - `*_local`: Performs the actual register access. - `*_smp_call`: Wrapper for `smp_call_function_single`. - The main entry point now detects if the device is CPU-bound and uses `smp_call_function_single` to execute the local variant on an appropriate CPU if necessary. 2. Adjust locking in `tmc_enable_etf_sink_sysfs` and `tmc_enable_etf_link`: - Drop the spinlock before calling `tmc_etf_enable_hw`. This is necessary because `smp_call_function_single` (used for cross-CPU calls) may require interrupts enabled or might sleep/wait, which is unsafe under a spinlock. - Re-acquire the lock afterwards to update driver state. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-8-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../hwtracing/coresight/coresight-tmc-etf.c | 87 ++++++++++++++++--- 1 file changed, 77 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 8882b1c4cdc05..11357788e9d93 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -47,7 +47,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) return rc; } -static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +static int tmc_etb_enable_hw_local(struct tmc_drvdata *drvdata) { int rc = coresight_claim_device(drvdata->csdev); @@ -60,6 +60,36 @@ static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) return rc; } +struct tmc_smp_arg { + struct tmc_drvdata *drvdata; + int rc; +}; + +static void tmc_etb_enable_hw_smp_call(void *info) +{ + struct tmc_smp_arg *arg = info; + + arg->rc = tmc_etb_enable_hw_local(arg->drvdata); +} + +static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +{ + int cpu, ret; + struct tmc_smp_arg arg = { 0 }; + + if (!drvdata->supported_cpus) + return tmc_etb_enable_hw_local(drvdata); + + arg.drvdata = drvdata; + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + tmc_etb_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) { char *bufp; @@ -130,7 +160,7 @@ static int __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) return rc; } -static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +static int tmc_etf_enable_hw_local(struct tmc_drvdata *drvdata) { int rc = coresight_claim_device(drvdata->csdev); @@ -143,6 +173,32 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) return rc; } +static void tmc_etf_enable_hw_smp_call(void *info) +{ + struct tmc_smp_arg *arg = info; + + arg->rc = tmc_etf_enable_hw_local(arg->drvdata); +} + +static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +{ + int cpu, ret; + struct tmc_smp_arg arg = { 0 }; + + if (!drvdata->supported_cpus) + return tmc_etf_enable_hw_local(drvdata); + + arg.drvdata = drvdata; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + tmc_etf_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) { struct coresight_device *csdev = drvdata->csdev; @@ -228,7 +284,11 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev) used = true; drvdata->buf = buf; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + ret = tmc_etb_enable_hw(drvdata); + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); if (!ret) { coresight_set_mode(csdev, CS_MODE_SYSFS); csdev->refcnt++; @@ -291,7 +351,11 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, break; } - ret = tmc_etb_enable_hw(drvdata); + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) + break; + + ret = tmc_etb_enable_hw_local(drvdata); if (!ret) { /* Associate with monitored process. */ drvdata->pid = pid; @@ -376,19 +440,22 @@ static int tmc_enable_etf_link(struct coresight_device *csdev, return -EBUSY; } - if (csdev->refcnt == 0) { + if (csdev->refcnt == 0) + first_enable = true; + + if (!first_enable) + csdev->refcnt++; + + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + if (first_enable) { ret = tmc_etf_enable_hw(drvdata); if (!ret) { coresight_set_mode(csdev, CS_MODE_SYSFS); - first_enable = true; + csdev->refcnt++; + dev_dbg(&csdev->dev, "TMC-ETF enabled\n"); } } - if (!ret) - csdev->refcnt++; - raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); - if (first_enable) - dev_dbg(&csdev->dev, "TMC-ETF enabled\n"); return ret; } From 33a4d3d5625b0977ccd4a31154a8f66458c2699c Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:49 -0800 Subject: [PATCH 0083/1330] FROMLIST: coresight-tmc: Update management interface for CPU-bound TMCs The current TMC management interface (sysfs attributes) assumes that device registers can be accessed directly from any CPU. However, for TMCs associated with specific CPU clusters, registers must be accessed from a CPU within that cluster. Replace the standard `coresight_simple_reg*` handlers with custom accessors (`coresight_tmc_reg*`). These new handlers check if the TMC is bound to a specific set of CPUs: - If bound, they use `smp_call_function_single()` to read the register on an appropriate CPU. - If not bound (global TMC), they fall back to direct access. This ensures correct register reads for per-cluster TMC devices while maintaining backward compatibility for global TMCs. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-9-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../hwtracing/coresight/coresight-tmc-core.c | 137 ++++++++++++++++-- 1 file changed, 123 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index d9d366f9d219d..232f8f6be2dc4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -487,21 +487,130 @@ static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) return memwidth; } +struct tmc_smp_arg { + struct tmc_drvdata *drvdata; + u32 offset; + int rc; +}; + +static void tmc_read_reg_smp_call(void *info) +{ + struct tmc_smp_arg *arg = info; + + arg->rc = readl_relaxed(arg->drvdata->base + arg->offset); +} + +static u32 cpu_tmc_read_reg(struct tmc_drvdata *drvdata, u32 offset) +{ + struct tmc_smp_arg arg = { + .drvdata = drvdata, + .offset = offset, + }; + int cpu, ret = 0; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret = smp_call_function_single(cpu, + tmc_read_reg_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + + return ret; +} + +static ssize_t coresight_tmc_reg32_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cs_off_attribute *cs_attr = container_of(attr, struct cs_off_attribute, attr); + int ret; + u32 val; + + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; + + if (!drvdata->supported_cpus) + val = readl_relaxed(drvdata->base + cs_attr->off); + else + val = cpu_tmc_read_reg(drvdata, cs_attr->off); + + pm_runtime_put(dev->parent); + + if (ret < 0) + return ret; + else + return sysfs_emit(buf, "0x%x\n", val); +} + +static ssize_t coresight_tmc_reg64_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cs_pair_attribute *cs_attr = container_of(attr, struct cs_pair_attribute, attr); + int ret; + u64 val; + + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; + if (!drvdata->supported_cpus) { + val = readl_relaxed(drvdata->base + cs_attr->lo_off) | + ((u64)readl_relaxed(drvdata->base + cs_attr->hi_off) << 32); + } else { + ret = cpu_tmc_read_reg(drvdata, cs_attr->lo_off); + + if (ret < 0) + goto out; + + val = ret; + + ret = cpu_tmc_read_reg(drvdata, cs_attr->hi_off); + if (ret < 0) + goto out; + + val |= ((u64)ret << 32); + } + +out: + pm_runtime_put_sync(dev->parent); + if (ret < 0) + return ret; + else + return sysfs_emit(buf, "0x%llx\n", val); +} + +#define coresight_tmc_reg32(name, offset) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_tmc_reg32_show, NULL), \ + offset \ + } \ + })[0].attr.attr) +#define coresight_tmc_reg64(name, lo_off, hi_off) \ + (&((struct cs_pair_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_tmc_reg64_show, NULL), \ + lo_off, hi_off \ + } \ + })[0].attr.attr) static struct attribute *coresight_tmc_mgmt_attrs[] = { - coresight_simple_reg32(rsz, TMC_RSZ), - coresight_simple_reg32(sts, TMC_STS), - coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI), - coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI), - coresight_simple_reg32(trg, TMC_TRG), - coresight_simple_reg32(ctl, TMC_CTL), - coresight_simple_reg32(ffsr, TMC_FFSR), - coresight_simple_reg32(ffcr, TMC_FFCR), - coresight_simple_reg32(mode, TMC_MODE), - coresight_simple_reg32(pscr, TMC_PSCR), - coresight_simple_reg32(devid, CORESIGHT_DEVID), - coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI), - coresight_simple_reg32(axictl, TMC_AXICTL), - coresight_simple_reg32(authstatus, TMC_AUTHSTATUS), + coresight_tmc_reg32(rsz, TMC_RSZ), + coresight_tmc_reg32(sts, TMC_STS), + coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI), + coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI), + coresight_tmc_reg32(trg, TMC_TRG), + coresight_tmc_reg32(ctl, TMC_CTL), + coresight_tmc_reg32(ffsr, TMC_FFSR), + coresight_tmc_reg32(ffcr, TMC_FFCR), + coresight_tmc_reg32(mode, TMC_MODE), + coresight_tmc_reg32(pscr, TMC_PSCR), + coresight_tmc_reg32(devid, CORESIGHT_DEVID), + coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI), + coresight_tmc_reg32(axictl, TMC_AXICTL), + coresight_tmc_reg32(authstatus, TMC_AUTHSTATUS), NULL, }; From 91311e786cabaa3fa0f426b7d70b3c2be6e510f2 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:50 -0800 Subject: [PATCH 0084/1330] FROMLIST: coresight-tmc: Defer probe when associated CPUs are offline On some platforms, the TMC driver may probe before the associated CPUs are online. This prevents the driver from securely accessing the hardware or configuring it via smp_call_function_single(), which requires the target CPU to be available. To address this, defer the hardware initialization if the associated CPUs are offline: 1. Track such deferred devices in a global list. 2. Register a CPU hotplug callback (`tmc_online_cpu`) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration for the waiting TMC devices. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-10-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- .../hwtracing/coresight/coresight-tmc-core.c | 59 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 4 ++ 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 232f8f6be2dc4..5e873bdcf7bb3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -37,6 +37,9 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); +static LIST_HEAD(tmc_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { @@ -1072,6 +1075,8 @@ static int __tmc_probe(struct device *dev, struct resource *res) if (!drvdata->supported_cpus) return -EINVAL; + drvdata->dev = dev; + cpus_read_lock(); for_each_cpu(cpu, drvdata->supported_cpus) { ret = smp_call_function_single(cpu, @@ -1079,11 +1084,16 @@ static int __tmc_probe(struct device *dev, struct resource *res) if (!ret) break; } - cpus_read_unlock(); + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &tmc_delay_probe); + cpus_read_unlock(); ret = 0; goto out; } + + cpus_read_unlock(); } else { tmc_init_hw_config(drvdata); } @@ -1148,8 +1158,12 @@ static void __tmc_remove(struct device *dev) misc_deregister(&drvdata->miscdev); if (drvdata->crashdev.fops) misc_deregister(&drvdata->crashdev); - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } } static void tmc_remove(struct amba_device *adev) @@ -1260,14 +1274,55 @@ static struct platform_driver tmc_platform_driver = { }, }; +static int tmc_online_cpu(unsigned int cpu) +{ + struct tmc_drvdata *drvdata, *tmp; + int ret; + + spin_lock(&delay_lock); + list_for_each_entry_safe(drvdata, tmp, &tmc_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->supported_cpus)) { + list_del(&drvdata->link); + + spin_unlock(&delay_lock); + ret = pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + tmc_init_hw_config(drvdata); + tmc_clear_self_claim_tag(drvdata); + tmc_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + spin_lock(&delay_lock); + } + } + spin_unlock(&delay_lock); + return 0; +} + static int __init tmc_init(void) { + int ret; + + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight-tmc:online", + tmc_online_cpu, NULL); + + if (ret > 0) + hp_online = ret; + else + return ret; + return coresight_init_driver("tmc", &tmc_driver, &tmc_platform_driver, THIS_MODULE); } static void __exit tmc_exit(void) { coresight_remove_driver(&tmc_driver, &tmc_platform_driver); + if (hp_online) { + cpuhp_remove_state_nocalls(hp_online); + hp_online = 0; + } } module_init(tmc_init); module_exit(tmc_exit); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 42fa61ee0ad2d..9d1a2b462285b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -264,6 +264,8 @@ struct etr_buf_node { * @supported_cpus: Represent the CPUs related to this TMC. * @devid: TMC variant ID inferred from the device configuration register. * @desc_name: Name to be used while creating crash interface. + * @dev: pointer to the device associated with this TMC. + * @link: link to the delay_probed list. */ struct tmc_drvdata { struct clk *atclk; @@ -300,6 +302,8 @@ struct tmc_drvdata { struct cpumask *supported_cpus; u32 devid; const char *desc_name; + struct device *dev; + struct list_head link; }; /** From 3736f979b82c80f14d07f58eef8dcd160f1ced39 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:51 -0800 Subject: [PATCH 0085/1330] FROMLIST: coresight: Pass trace mode to link enable callback Currently, the link enable callback does not receive the CoreSight mode (enum cs_mode). This prevents link drivers from knowing whether they are being enabled for SysFS or Perf. This distinction is crucial because Perf mode runs in atomic context, where certain operations (like smp_call_function_single()) are unsafe. Without knowing the mode, drivers cannot conditionally avoid these unsafe calls. Update the `enable` callback in `struct coresight_ops_link` to accept `enum cs_mode`. This allows drivers to implement mode-specific logic, such as using atomic-safe enablement sequences when running in Perf mode. Update all call sites and driver implementations accordingly. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-11-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-core.c | 7 +++--- .../hwtracing/coresight/coresight-funnel.c | 21 ++++++++++++++++- .../coresight/coresight-replicator.c | 23 ++++++++++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 19 ++++++++++++++- drivers/hwtracing/coresight/coresight-tnoc.c | 3 ++- drivers/hwtracing/coresight/coresight-tpda.c | 3 ++- include/linux/coresight.h | 3 ++- 7 files changed, 70 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 1cbaa63aa7215..8dc5291ca892e 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -314,7 +314,8 @@ static void coresight_disable_sink(struct coresight_device *csdev) static int coresight_enable_link(struct coresight_device *csdev, struct coresight_device *parent, struct coresight_device *child, - struct coresight_device *source) + struct coresight_device *source, + enum cs_mode mode) { int link_subtype; struct coresight_connection *inconn, *outconn; @@ -331,7 +332,7 @@ static int coresight_enable_link(struct coresight_device *csdev, if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT && IS_ERR(outconn)) return PTR_ERR(outconn); - return link_ops(csdev)->enable(csdev, inconn, outconn); + return link_ops(csdev)->enable(csdev, inconn, outconn, mode); } static void coresight_disable_link(struct coresight_device *csdev, @@ -550,7 +551,7 @@ int coresight_enable_path(struct coresight_path *path, enum cs_mode mode) case CORESIGHT_DEV_TYPE_LINK: parent = list_prev_entry(nd, link)->csdev; child = list_next_entry(nd, link)->csdev; - ret = coresight_enable_link(csdev, parent, child, source); + ret = coresight_enable_link(csdev, parent, child, source, mode); if (ret) goto err_disable_helpers; break; diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 5d114ce1109f4..c50522c2854c7 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -121,7 +121,8 @@ static int funnel_enable_hw(struct funnel_drvdata *drvdata, int port) static int funnel_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int rc = 0; struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -135,6 +136,23 @@ static int funnel_enable(struct coresight_device *csdev, else in->dest_refcnt++; + if (mode == CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + if (drvdata->base) + rc = dynamic_funnel_enable_hw(drvdata, in->dest_port); + if (!rc) + in->dest_refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) { @@ -183,6 +201,7 @@ static void funnel_disable(struct coresight_device *csdev, dynamic_funnel_disable_hw(drvdata, in->dest_port); last_disable = true; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); if (last_disable) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index a9f22d0e15de2..cc7d3916b8b9d 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -199,7 +199,8 @@ static int replicator_enable_hw(struct replicator_drvdata *drvdata, static int replicator_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int rc = 0; struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -212,6 +213,25 @@ static int replicator_enable(struct coresight_device *csdev, first_enable = true; else out->src_refcnt++; + + if (mode == CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + if (drvdata->base) + rc = dynamic_replicator_enable(drvdata, in->dest_port, + out->src_port); + if (!rc) + out->src_refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) { @@ -272,6 +292,7 @@ static void replicator_disable(struct coresight_device *csdev, out->src_port); last_disable = true; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); if (last_disable) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 11357788e9d93..f1b8264b4e5c8 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -427,7 +427,8 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) static int tmc_enable_etf_link(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int ret = 0; unsigned long flags; @@ -446,6 +447,22 @@ static int tmc_enable_etf_link(struct coresight_device *csdev, if (!first_enable) csdev->refcnt++; + if (mode == CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + ret = tmc_etf_enable_hw_local(drvdata); + if (!ret) + csdev->refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) { ret = tmc_etf_enable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c index 1128612e70a73..9873b017abbd9 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -81,7 +81,8 @@ static void trace_noc_enable_hw(struct trace_noc_drvdata *drvdata) } static int trace_noc_enable(struct coresight_device *csdev, struct coresight_connection *inport, - struct coresight_connection *outport) + struct coresight_connection *outport, + enum cs_mode mode) { struct trace_noc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 7055f8f134278..9d0a015e164ce 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -224,7 +224,8 @@ static int __tpda_enable(struct tpda_drvdata *drvdata, int port) static int tpda_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); int ret = 0; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 2b48be97fcd0d..218eb1d1dcef6 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -383,7 +383,8 @@ struct coresight_ops_sink { struct coresight_ops_link { int (*enable)(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out); + struct coresight_connection *out, + enum cs_mode mode); void (*disable)(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out); From 167c018c6f477307731f0dc93d65cfa0d8ee033e Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 3 Feb 2026 14:39:38 +0800 Subject: [PATCH 0086/1330] FROMLIST: dt-binding: document QCOM platforms for CTCU device Document the platforms that fallback to using the qcom,sa8775p-ctcu compatible for probing. Link: https://lore.kernel.org/all/20260204-enable-ctcu-and-etr-v3-1-0bb95c590ae1@oss.qualcomm.com/ Signed-off-by: Jie Gan --- .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 2981001a7d7f7..468da6439bbf9 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -29,7 +29,11 @@ properties: oneOf: - items: - enum: + - qcom,glymur-ctcu + - qcom,kaanapali-ctcu - qcom,qcs8300-ctcu + - qcom,sm8750-ctcu + - qcom,x1e80100-ctcu - const: qcom,sa8775p-ctcu - enum: - qcom,sa8775p-ctcu From 933d438d41847408839ce483d9cd38e94eb0ddb0 Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Mon, 24 Nov 2025 14:55:22 +0530 Subject: [PATCH 0087/1330] FROMLIST: phy: qcom: sgmii-eth: add second regulator support The Qualcomm SGMII SerDes PHY requires two regulators to function properly. If both of these are not enabled, the following error is observed: [ 77.105651] qcom-dwmac-sgmii-phy 8909000.phy: QSERDES_COM_C_READY_STATUS timed-out [ 77.113447] qcom-ethqos 23040000.ethernet eth0: __stmmac_open: Serdes powerup failed Therefore, add support for handling the additional regulator in the driver. Link: https://lore.kernel.org/linux-arm-msm/20251124-sgmiieth_serdes_regulator-v1-0-73ae8f9cbe2a@oss.qualcomm.com/T/#m44fe996d0f2a26c428b315959cd0623a0271ac3d Fixes: 601d06277007 ("phy: qcom: add the SGMII SerDes PHY driver") Signed-off-by: Mohd Ayaan Anwar --- drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 24 ++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c index 5b1c82459c126..5044f244762f4 100644 --- a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c +++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "phy-qcom-qmp-pcs-sgmii.h" #include "phy-qcom-qmp-qserdes-com-v5.h" @@ -26,6 +27,7 @@ #define QSERDES_COM_C_PLL_LOCKED BIT(1) struct qcom_dwmac_sgmii_phy_data { + struct regulator *vdda_0p9; struct regmap *regmap; struct clk *refclk; int speed; @@ -266,9 +268,23 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy) static int qcom_dwmac_sgmii_phy_power_on(struct phy *phy) { + int ret; struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy); - return clk_prepare_enable(data->refclk); + ret = regulator_enable(data->vdda_0p9); + if (ret) + goto out_ret; + + ret = clk_prepare_enable(data->refclk); + if (ret) + goto out_reg_disable; + + return 0; + +out_reg_disable: + regulator_disable(data->vdda_0p9); +out_ret: + return ret; } static int qcom_dwmac_sgmii_phy_power_off(struct phy *phy) @@ -283,6 +299,8 @@ static int qcom_dwmac_sgmii_phy_power_off(struct phy *phy) clk_disable_unprepare(data->refclk); + regulator_disable(data->vdda_0p9); + return 0; } @@ -343,6 +361,10 @@ static int qcom_dwmac_sgmii_phy_probe(struct platform_device *pdev) if (IS_ERR(data->refclk)) return PTR_ERR(data->refclk); + data->vdda_0p9 = devm_regulator_get(dev, "vdda-0p9"); + if (IS_ERR(data->vdda_0p9)) + return PTR_ERR(data->vdda_0p9); + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (IS_ERR(provider)) return PTR_ERR(provider); From 26225fc3c5f91fc60d447bd51cdad4068f212045 Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Sun, 14 Sep 2025 20:36:48 +0530 Subject: [PATCH 0088/1330] FROMLIST: net: phy: qcom: qca808x: Add .get_rate_matching support Add support for rate matching to the QCA8081 PHY driver to correctly report its capabilities. Some boards[0][1] with this PHY currently report support only for 2.5G. Implement the .get_rate_matching callback to allow phylink to determine the actual PHY capabilities and report them accurately. Before: # ethtool eth0 Settings for eth0: Supported ports: [ ] Supported link modes: 2500baseT/Full Supported pause frame use: Symmetric Receive-only ... After: # ethtool eth0 Settings for eth0: Supported ports: [ ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Full 2500baseT/Full Supported pause frame use: Symmetric Receive-only ... [0] https://lore.kernel.org/all/20250905192350.1223812-3-umang.chheda@oss.qualcomm.com/ [1] https://lore.kernel.org/all/20250908-lemans-evk-bu-v4-12-5c319c696a7d@oss.qualcomm.com/ Link: https://lore.kernel.org/netdev/20250914-qca808x_rate_match-v1-1-0f9e6a331c3b@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar --- drivers/net/phy/qcom/qca808x.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/phy/qcom/qca808x.c b/drivers/net/phy/qcom/qca808x.c index 8eb51b1a006c4..f22ebb1ac3328 100644 --- a/drivers/net/phy/qcom/qca808x.c +++ b/drivers/net/phy/qcom/qca808x.c @@ -643,6 +643,15 @@ static void qca808x_get_phy_stats(struct phy_device *phydev, qcom_phy_get_stats(stats, priv->hw_stats); } +static int qca808x_get_rate_matching(struct phy_device *phydev, + phy_interface_t iface) +{ + if (iface == PHY_INTERFACE_MODE_2500BASEX) + return RATE_MATCH_PAUSE; + + return RATE_MATCH_NONE; +} + static struct phy_driver qca808x_driver[] = { { /* Qualcomm QCA8081 */ @@ -674,6 +683,7 @@ static struct phy_driver qca808x_driver[] = { .led_polarity_set = qca808x_led_polarity_set, .update_stats = qca808x_update_stats, .get_phy_stats = qca808x_get_phy_stats, + .get_rate_matching = qca808x_get_rate_matching, }, }; module_phy_driver(qca808x_driver); From 88481b5fef259d60b9b32330b99de5a7096f3eb4 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Wed, 14 Jan 2026 22:42:55 -0800 Subject: [PATCH 0089/1330] FROMLIST: dt-bindings: remoteproc: qcom,sm8550-pas: Add Kaanapali ADSP Document compatible for Qualcomm Kaanapali SoC ADSP PAS which looks fully compatible with SM8750, which can fallback to SM8550 except for one more interrupt ("shutdown-ack"). Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/all/20260114-knp-remoteproc-v4-1-fcf0b04d01af@oss.qualcomm.com/ Signed-off-by: Yijie Yang --- .../devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 11b056d6a4808..cf3aaf5a46e47 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -28,7 +28,9 @@ properties: - qcom,x1e80100-adsp-pas - qcom,x1e80100-cdsp-pas - items: - - const: qcom,sm8750-adsp-pas + - enum: + - qcom,kaanapali-adsp-pas + - qcom,sm8750-adsp-pas - const: qcom,sm8550-adsp-pas - items: - const: qcom,sm8750-cdsp-pas @@ -95,6 +97,7 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-adsp-pas - qcom,sm8750-adsp-pas then: properties: From 91bded4ef55854a5a58deb74a60d8d5da5c23655 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Wed, 14 Jan 2026 22:42:56 -0800 Subject: [PATCH 0090/1330] FROMLIST: dt-bindings: remoteproc: qcom,sm8550-pas: Add Kaanapali CDSP Add remote processor PAS loader for Kaanapali CDSP processor, compatible with earlier SM8550 with minor difference: one more sixth "shutdown-ack" interrupt. It is not compatible with SM8650 because one memory region "global_sync_mem" is not managed by kernel on Kaanapali so it is removed in the remoteproc cdsp node. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/all/20260114-knp-remoteproc-v4-2-fcf0b04d01af@oss.qualcomm.com/ Signed-off-by: Yijie Yang --- .../devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index cf3aaf5a46e47..b117c82b057b3 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -32,6 +32,10 @@ properties: - qcom,kaanapali-adsp-pas - qcom,sm8750-adsp-pas - const: qcom,sm8550-adsp-pas + - items: + - enum: + - qcom,kaanapali-cdsp-pas + - const: qcom,sm8550-cdsp-pas - items: - const: qcom,sm8750-cdsp-pas - const: qcom,sm8650-cdsp-pas @@ -98,6 +102,7 @@ allOf: contains: enum: - qcom,kaanapali-adsp-pas + - qcom,kaanapali-cdsp-pas - qcom,sm8750-adsp-pas then: properties: From fc2ee115154b807346f75bca2662b7eefbcbcbde Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 2 Feb 2026 22:06:18 -0800 Subject: [PATCH 0091/1330] FROMLIST: arm64: dts: qcom: kaanapali: add coresight nodes Add CoreSight nodes to enable trace paths such as TPDM->ETF and STM->ETF. These devices are part of the AOSS, CDSP, QDSS, modem and some small subsystems, such as DCC, GCC, ipcc and so on. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-1-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1160 +++++++++++++++++++++++ 1 file changed, 1160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 9be86479ceef1..83f08c323cd0c 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -1080,6 +1080,1114 @@ }; }; + stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in7>; + }; + }; + }; + }; + + tpdm@10003000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10003000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_dcc_out: endpoint { + remote-endpoint = <&tpda_qdss_in0>; + }; + }; + }; + }; + + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_qdss_in0: endpoint { + remote-endpoint = <&tpdm_dcc_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint = <&tpdm_spdm_out>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint = <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint = <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_in0_in0: endpoint { + remote-endpoint = <&tn_ag_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_in0_in6: endpoint { + remote-endpoint = <&tpda_qdss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_in0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&funnel_aoss_in6>; + }; + }; + }; + }; + + tpdm@11000000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11000000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_modem0_out: endpoint { + remote-endpoint = <&tpda_modem_in0>; + }; + }; + }; + }; + + tpda@11004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_modem_in0: endpoint { + remote-endpoint = <&tpdm_modem0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_modem_in1: endpoint { + remote-endpoint = <&tpdm_modem1_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_modem_in2: endpoint { + remote-endpoint = <&tpdm_modem2_out>; + }; + }; + }; + + out-ports { + port { + tpda_modem_out: endpoint { + remote-endpoint = <&funnel_modem_dl_in0>; + }; + }; + }; + }; + + funnel@11005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11005000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_modem_dl_in0: endpoint { + remote-endpoint = <&tpda_modem_out>; + }; + }; + }; + + out-ports { + port { + funnel_modem_dl_out: endpoint { + remote-endpoint = <&tn_ag_in13>; + }; + }; + }; + }; + + tpdm@1102c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1102c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_gcc_out: endpoint { + remote-endpoint = <&tn_ag_in17>; + }; + }; + }; + }; + + tpdm@11180000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11180000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint = <&tpda_cdsp_in0>; + }; + }; + }; + }; + + tpdm@11183000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11183000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_cmsr1_out: endpoint { + remote-endpoint = <&tpda_cdsp_in3>; + }; + }; + }; + }; + + tpdm@11184000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11184000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_cmsr2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in4>; + }; + }; + }; + }; + + tpdm@11185000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11185000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_cdsp_dpm1_out: endpoint { + remote-endpoint = <&tpda_cdsp_in5>; + }; + }; + }; + }; + + tpdm@11186000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11186000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_cdsp_dpm2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in6>; + }; + }; + }; + }; + + tpda@11188000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11188000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_cdsp_in0: endpoint { + remote-endpoint = <&tpdm_cdsp_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_cdsp_in1: endpoint { + remote-endpoint = <&tpdm_cdsp_llm_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_cdsp_in2: endpoint { + remote-endpoint = <&tpdm_cdsp_llm2_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_cdsp_in3: endpoint { + remote-endpoint = <&tpdm_cdsp_cmsr1_out>; + }; + }; + + port@4 { + reg = <4>; + + tpda_cdsp_in4: endpoint { + remote-endpoint = <&tpdm_cdsp_cmsr2_out>; + }; + }; + + port@5 { + reg = <5>; + + tpda_cdsp_in5: endpoint { + remote-endpoint = <&tpdm_cdsp_dpm1_out>; + }; + }; + + port@6 { + reg = <6>; + + tpda_cdsp_in6: endpoint { + remote-endpoint = <&tpdm_cdsp_dpm2_out>; + }; + }; + }; + + out-ports { + port { + tpda_cdsp_out: endpoint { + remote-endpoint = <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11189000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint = <&tpda_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out: endpoint { + remote-endpoint = <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@111a3000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_pmu_out: endpoint { + remote-endpoint = <&tn_ag_in29>; + }; + }; + }; + }; + + tpdm@111a4000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qrng_out: endpoint { + remote-endpoint = <&tn_ag_in18>; + }; + }; + }; + }; + + tpdm@111a5000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a5000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_dlmm_out: endpoint { + remote-endpoint = <&tn_ag_in25>; + }; + }; + }; + }; + + tpdm@111a6000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a6000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_north_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in26>; + }; + }; + }; + }; + + tpdm@111a7000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a7000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_south_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in27>; + }; + }; + }; + }; + + tpdm@111a8000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a8000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb0_out: endpoint { + remote-endpoint = <&tn_ag_in30>; + }; + }; + }; + }; + + tpdm@111a9000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a9000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb1_out: endpoint { + remote-endpoint = <&tn_ag_in31>; + }; + }; + }; + }; + + tpdm@111aa000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111aa000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb2_out: endpoint { + remote-endpoint = <&tn_ag_in32>; + }; + }; + }; + }; + + tpdm@111ab000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111ab000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb0_out: endpoint { + remote-endpoint = <&tn_ag_in36>; + }; + }; + }; + }; + + tpdm@111ac000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111ac000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb1_out: endpoint { + remote-endpoint = <&tn_ag_in28>; + }; + }; + }; + }; + + tpdm@111ad000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111ad000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb2_out: endpoint { + remote-endpoint = <&tn_ag_in34>; + }; + }; + }; + }; + + tpdm@111ae000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111ae000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb3_out: endpoint { + remote-endpoint = <&tn_ag_in37>; + }; + }; + }; + }; + + tpdm@111af000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111af000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb4_out: endpoint { + remote-endpoint = <&tn_ag_in35>; + }; + }; + }; + }; + + tpdm@111b3000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111b3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_pcie_rscc_out: endpoint { + remote-endpoint = <&tn_ag_in8>; + }; + }; + }; + }; + + tn@111b8000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x0 0x111b8000 0x0 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + + tn_ag_in8: endpoint { + remote-endpoint = <&tpdm_pcie_rscc_out>; + }; + }; + + port@d { + reg = <0xd>; + + tn_ag_in13: endpoint { + remote-endpoint = <&funnel_modem_dl_out>; + }; + }; + + port@10 { + reg = <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint = <&funnel_cdsp_out>; + }; + }; + + port@11 { + reg = <0x11>; + + tn_ag_in17: endpoint { + remote-endpoint = <&tpdm_gcc_out>; + }; + }; + + port@12 { + reg = <0x12>; + + tn_ag_in18: endpoint { + remote-endpoint = <&tpdm_qrng_out>; + }; + }; + + port@13 { + reg = <0x13>; + + tn_ag_in19: endpoint { + remote-endpoint = <&tpdm_qm_out>; + }; + }; + + port@15 { + reg = <0x15>; + + tn_ag_in21: endpoint { + remote-endpoint = <&tpdm_ipa_out>; + }; + }; + + port@19 { + reg = <0x19>; + + tn_ag_in25: endpoint { + remote-endpoint = <&tpdm_dlmm_out>; + }; + }; + + port@1a { + reg = <0x1a>; + + tn_ag_in26: endpoint { + remote-endpoint = <&tpdm_north_dsb_out>; + }; + }; + + port@1b { + reg = <0x1b>; + + tn_ag_in27: endpoint { + remote-endpoint = <&tpdm_south_dsb_out>; + }; + }; + + port@1c { + reg = <0x1c>; + + tn_ag_in28: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb1_out>; + }; + }; + + port@1d { + reg = <0x1d>; + + tn_ag_in29: endpoint { + remote-endpoint = <&tpdm_pmu_out>; + }; + }; + + port@1e { + reg = <0x1e>; + + tn_ag_in30: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb0_out>; + }; + }; + + port@1f { + reg = <0x1f>; + + tn_ag_in31: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb1_out>; + }; + }; + + port@20 { + reg = <0x20>; + + tn_ag_in32: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb2_out>; + }; + }; + + port@22 { + reg = <0x22>; + + tn_ag_in34: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb2_out>; + }; + }; + + port@23 { + reg = <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb4_out>; + }; + }; + + port@24 { + reg = <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb0_out>; + }; + }; + + port@25 { + reg = <37>; + + tn_ag_in37: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb3_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint = <&funnel_in0_in0>; + }; + }; + }; + }; + + tpdm@111d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint = <&tn_ag_in19>; + }; + }; + }; + }; + + tpdm@11303000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11303000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio4_out: endpoint { + remote-endpoint = <&tpda_aoss_in4>; + }; + }; + }; + }; + + funnel@11304000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11304000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + + funnel_aoss_in5: endpoint { + remote-endpoint = <&tpda_aoss_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_aoss_in6: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out: endpoint { + remote-endpoint = <&tmc_etf_in>; + }; + }; + }; + }; + + tmc@11305000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x11305000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint = <&funnel_aoss_out>; + }; + }; + }; + }; + + tpda@11308000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11308000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_aoss_in0: endpoint { + remote-endpoint = <&tpdm_swao_prio0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_aoss_in1: endpoint { + remote-endpoint = <&tpdm_swao_prio1_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_aoss_in2: endpoint { + remote-endpoint = <&tpdm_swao_prio2_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_aoss_in3: endpoint { + remote-endpoint = <&tpdm_swao_prio3_out>; + }; + }; + + port@4 { + reg = <4>; + + tpda_aoss_in4: endpoint { + remote-endpoint = <&tpdm_swao_prio4_out>; + }; + }; + + port@5 { + reg = <5>; + + tpda_aoss_in5: endpoint { + remote-endpoint = <&tpdm_swao_out>; + }; + }; + }; + + out-ports { + port { + tpda_aoss_out: endpoint { + remote-endpoint = <&funnel_aoss_in5>; + }; + }; + }; + }; + + tpdm@11309000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11309000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio0_out: endpoint { + remote-endpoint = <&tpda_aoss_in0>; + }; + }; + }; + }; + + tpdm@1130a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1130a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio1_out: endpoint { + remote-endpoint = <&tpda_aoss_in1>; + }; + }; + }; + }; + + tpdm@1130b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1130b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio2_out: endpoint { + remote-endpoint = <&tpda_aoss_in2>; + }; + }; + }; + }; + + tpdm@1130c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1130c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio3_out: endpoint { + remote-endpoint = <&tpda_aoss_in3>; + }; + }; + }; + }; + + tpdm@1130d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1130d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_out: endpoint { + remote-endpoint = <&tpda_aoss_in5>; + }; + }; + }; + }; + + tpdm@11422000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11422000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_ipa_out: endpoint { + remote-endpoint = <&tn_ag_in21>; + }; + }; + }; + }; + sram@14680000 { compatible = "qcom,kaanapali-imem", "mmio-sram"; reg = <0x0 0x14680000 0x0 0x1000>; @@ -1603,4 +2711,56 @@ , ; }; + + tpdm-cdsp-llm { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm_out: endpoint { + remote-endpoint = <&tpda_cdsp_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in2>; + }; + }; + }; + }; + + tpdm-modem1 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_modem1_out: endpoint { + remote-endpoint = <&tpda_modem_in1>; + }; + }; + }; + }; + + tpdm-modem2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_modem2_out: endpoint { + remote-endpoint = <&tpda_modem_in2>; + }; + }; + }; + }; }; From 858498729580d058b08f61a41debcd392a89538b Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Mon, 2 Feb 2026 22:06:19 -0800 Subject: [PATCH 0092/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines Add device tree support for QUPv3 serial engine protocols on Kaanapali. Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with support of GPI DMA engines, and it also includes 5 I2C hubs. Signed-off-by: Jyothi Kumar Seerapu Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-2-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2226 ++++++++++++++++++++++- 1 file changed, 2159 insertions(+), 67 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 83f08c323cd0c..00e7f0da17d9f 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -468,102 +469,1692 @@ #power-domain-cells = <1>; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x1f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x436 0x0>; + dma-coherent; + }; + + qupv3_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x423 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c8: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c9: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi9: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c11: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c12: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + i2c_master_hub: geniqup@9c0000 { + compatible = "qcom,geni-se-i2c-master-hub"; + reg = <0x0 0x009c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + clock-names = "s-ahb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c_hub_0: i2c@980000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00980000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00984000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00988000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c2_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x0098c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00990000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x1f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xb6 0x0>; + dma-coherent; + }; + qupv3_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x2000>; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - clock-names = "m-ahb", - "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0xa3 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c4: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c5: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c6: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart7: serial@a9c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + ipcc: mailbox@1106000 { + compatible = "qcom,kaanapali-ipcc", "qcom,ipcc"; + reg = <0x0 0x01106000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,kaanapali-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x1a080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,kaanapali-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x6200>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,kaanapali-system-noc"; + reg = <0x0 0x01680000 0x0 0x1f080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,kaanapali-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x11400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + aggre_noc: interconnect@16e0000 { + compatible = "qcom,kaanapali-aggre-noc"; + reg = <0x0 0x016e0000 0x0 0x42400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,kaanapali-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + gpi_dma3: dma-controller@1900000 { + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x01900000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x1e>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x4d6 0x0>; + dma-coherent; + }; + + qupv3_3: geniqup@19c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x019c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x4c3 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c13: i2c@1980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01980000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, + <&gpi_dma3 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c14: i2c@1984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01984000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 1 QCOM_GPI_I2C>, + <&gpi_dma3 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@1984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01984000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma3 0 1 QCOM_GPI_SPI>, + <&gpi_dma3 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c15: i2c@1988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01988000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 2 QCOM_GPI_I2C>, + <&gpi_dma3 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@1988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01988000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma3 0 2 QCOM_GPI_SPI>, + <&gpi_dma3 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c16: i2c@198c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0198c000 0x0 0x4000>; + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 3 QCOM_GPI_I2C>, + <&gpi_dma3 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c16_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi16: spi@198c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x198c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma3 0 3 QCOM_GPI_SPI>, + <&gpi_dma3 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c17: i2c@1990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01990000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 4 QCOM_GPI_I2C>, + <&gpi_dma3 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c17_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi17: spi@1990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01990000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma3 0 4 QCOM_GPI_SPI>, + <&gpi_dma3 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart18: serial@1994000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x01994000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart18_default>, <&qup_uart18_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + gpi_dma4: dma-controller@1a00000 { + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x01a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x1e>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x536 0x0>; + dma-coherent; + }; + + qupv3_4: geniqup@1ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x01ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_4_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_4_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x523 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c19: i2c@1a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 0 QCOM_GPI_I2C>, + <&gpi_dma4 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c19_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi19: spi@1a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma4 0 0 QCOM_GPI_SPI>, + <&gpi_dma4 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c20: i2c@1a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 1 QCOM_GPI_I2C>, + <&gpi_dma4 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c20_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; - iommus = <&apps_smmu 0xa3 0x0>; + spi20: spi@1a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a84000 0x0 0x4000>; - dma-coherent; + interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; + clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names = "se"; - uart7: serial@a9c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a9c000 0x0 0x4000>; + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; - interrupts = ; + dmas = <&gpi_dma4 0 1 QCOM_GPI_SPI>, + <&gpi_dma4 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c21: i2c@1a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>; clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 2 QCOM_GPI_I2C>, + <&gpi_dma4 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c21_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi21: spi@1a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; - pinctrl-0 = <&qup_uart7_default>; + dmas = <&gpi_dma4 0 2 QCOM_GPI_SPI>, + <&gpi_dma4 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - }; - ipcc: mailbox@1106000 { - compatible = "qcom,kaanapali-ipcc", "qcom,ipcc"; - reg = <0x0 0x01106000 0x0 0x1000>; + i2c22: i2c@1a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a8c000 0x0 0x4000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; + interrupts = ; - #mbox-cells = <2>; - }; + clocks = <&gcc GCC_QUPV3_WRAP4_S3_CLK>; + clock-names = "se"; - cnoc_main: interconnect@1500000 { - compatible = "qcom,kaanapali-cnoc-main"; - reg = <0x0 0x01500000 0x0 0x1a080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; - config_noc: interconnect@1600000 { - compatible = "qcom,kaanapali-cnoc-cfg"; - reg = <0x0 0x01600000 0x0 0x6200>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; + dmas = <&gpi_dma4 0 3 QCOM_GPI_I2C>, + <&gpi_dma4 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; - system_noc: interconnect@1680000 { - compatible = "qcom,kaanapali-system-noc"; - reg = <0x0 0x01680000 0x0 0x1f080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; + pinctrl-0 = <&qup_i2c22_data_clk>; + pinctrl-names = "default"; - pcie_noc: interconnect@16c0000 { - compatible = "qcom,kaanapali-pcie-anoc"; - reg = <0x0 0x016c0000 0x0 0x11400>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, - <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; - }; + #address-cells = <1>; + #size-cells = <0>; - aggre_noc: interconnect@16e0000 { - compatible = "qcom,kaanapali-aggre-noc"; - reg = <0x0 0x016e0000 0x0 0x42400>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; - }; + status = "disabled"; + }; - mmss_noc: interconnect@1780000 { - compatible = "qcom,kaanapali-mmss-noc"; - reg = <0x0 0x01780000 0x0 0x5b800>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; + i2c23: i2c@1a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 4 QCOM_GPI_I2C>, + <&gpi_dma4 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c23_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; }; pcie0: pcie@1c00000 { @@ -1017,6 +2608,491 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio66", "gpio67"; + function = "i2chub0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio78", "gpio79"; + function = "i2chub0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio68", "gpio69"; + function = "i2chub0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio70", "gpio71"; + function = "i2chub0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio72", "gpio73"; + function = "i2chub0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio83"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio74", "gpio75"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio40", "gpio41"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio0", "gpio1"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins = "gpio117", "gpio118"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins = "gpio122", "gpio123"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins = "gpio208", "gpio209"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins = "gpio64", "gpio65"; + function = "qup3_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "qup3_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup3_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins = "gpio16", "gpio17"; + function = "qup3_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup3_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins = "gpio48", "gpio49"; + function = "qup4_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins = "gpio28", "gpio29"; + function = "qup4_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup4_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins = "gpio121", "gpio84"; + function = "qup4_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins = "gpio161", "gpio162"; + function = "qup4_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio81"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio83", "gpio82"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio77"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio74", "gpio75", "gpio76"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio43"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio40", "gpio41", "gpio42"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio47"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio39"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio36", "gpio37", "gpio38"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio56", "gpio57", "gpio58"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio3"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */pins = "gpio0", "gpio1", "gpio2"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio7"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio4", "gpio5", "gpio6"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio120"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio117", "gpio118", "gpio119"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio125"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio122", "gpio123", "gpio124"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio11"; + function = "qup3_se1"; + drive-strength = <6>; + bias-pull-up; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio8", "gpio9", "gpio10"; + function = "qup3_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio15"; + function = "qup3_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio12", "gpio13", "gpio14"; + function = "qup3_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins = "gpio19"; + function = "qup3_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio16", "gpio17", "gpio18"; + function = "qup3_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins = "gpio23"; + function = "qup3_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio20", "gpio21", "gpio22"; + function = "qup3_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins = "gpio51"; + function = "qup4_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio48", "gpio49", "gpio50"; + function = "qup4_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins = "gpio31"; + function = "qup4_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio28", "gpio29", "gpio30"; + function = "qup4_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins = "gpio35"; + function = "qup4_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup4_se2"; + drive-strength = <6>; + bias-disable; + }; + qup_uart7_default: qup-uart7-state { /* TX, RX */ pins = "gpio62", "gpio63"; @@ -1025,6 +3101,22 @@ bias-disable; }; + qup_uart18_default: qup-uart18-default-state { + /* TX, RX */ + pins = "gpio26", "gpio27"; + function = "qup3_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart18_cts_rts: qup-uart18-cts-rts-state { + /* CTS, RTS */ + pins = "gpio24", "gpio25"; + function = "qup3_se5"; + drive-strength = <2>; + bias-pull-down; + }; + sdc2_default: sdc2-default-state { clk-pins { pins = "sdc2_clk"; From a3af8bc44ba5d093d6fc9736f4b225e027665dd4 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 2 Feb 2026 22:06:20 -0800 Subject: [PATCH 0093/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add TSENS and thermal zones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Kaanapali includes seven TSENS instances, with a total of 55 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 130°C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 120°C and critical trip at 125°C. Signed-off-by: Manaf Meethalavalappu Pallikunhi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-3-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1075 +++++++++++++++++++++++ 1 file changed, 1075 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 00e7f0da17d9f..10cfcf13ae9f8 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2583,6 +2583,90 @@ interrupt-controller; }; + tsens0: thermal-sensor@c229000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c22a000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22a000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <12>; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22b000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22b000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <7>; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22c000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <4>; + #thermal-sensor-cells = <1>; + }; + + tsens4: thermal-sensor@c22d000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <8>; + #thermal-sensor-cells = <1>; + }; + + tsens5: thermal-sensor@c22e000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <12>; + #thermal-sensor-cells = <1>; + }; + + tsens6: thermal-sensor@c22f000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <7>; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-management@c300000 { compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; @@ -4795,6 +4879,997 @@ }; }; + thermal-zones { + cpullc-0-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + cpullc-0-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpullc-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpullc-0-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpullc-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + qmx-0-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + qmx-0-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + qmx-0-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-0-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + cpu-0-0-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpu-0-0-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpu-0-1-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + cpu-0-1-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + cpu-0-2-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-2-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + cpu-0-2-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-2-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + cpu-0-3-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-3-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + cpu-0-3-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-3-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + cpu-0-4-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-4-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + cpu-0-4-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-4-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors = <&tsens1 10>; + + trips { + cpu-0-5-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-5-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors = <&tsens1 11>; + + trips { + cpu-0-5-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-5-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + cpullc-1-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpullc-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + cpullc-1-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpullc-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + qmx-1-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + qmx-1-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + qmx-1-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + qmx-1-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + qmx-1-4-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-4-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + cpu-1-0-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + cpu-1-0-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + cpu-1-1-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + cpu-1-1-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors = <&tsens4 0>; + + trips { + nsphvx-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors = <&tsens4 1>; + + trips { + nsphvx-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors = <&tsens4 2>; + + trips { + nsphvx-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors = <&tsens4 3>; + + trips { + nsphvx-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors = <&tsens4 4>; + + trips { + nsphmx-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors = <&tsens4 5>; + + trips { + nsphmx-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors = <&tsens4 6>; + + trips { + nsphmx-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors = <&tsens4 7>; + + trips { + nsphmx-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors = <&tsens5 0>; + + trips { + gpuss-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors = <&tsens5 1>; + + trips { + gpuss-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-2-thermal { + thermal-sensors = <&tsens5 2>; + + trips { + gpuss-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors = <&tsens5 3>; + + trips { + gpuss-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors = <&tsens5 4>; + + trips { + gpuss-4-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-4-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-5-thermal { + thermal-sensors = <&tsens5 5>; + + trips { + gpuss-5-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-5-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-6-thermal { + thermal-sensors = <&tsens5 6>; + + trips { + gpuss-6-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-6-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-7-thermal { + thermal-sensors = <&tsens5 7>; + + trips { + gpuss-7-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-7-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-8-thermal { + thermal-sensors = <&tsens5 8>; + + trips { + gpuss-8-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-8-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-9-thermal { + thermal-sensors = <&tsens5 9>; + + trips { + gpuss-9-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-9-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-10-thermal { + thermal-sensors = <&tsens5 10>; + + trips { + gpuss-10-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-10-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + thermal-sensors = <&tsens5 11>; + + trips { + ddr-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + ddr-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss-0-thermal { + thermal-sensors = <&tsens6 0>; + + trips { + mdmss-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss-1-thermal { + thermal-sensors = <&tsens6 1>; + trips { + mdmss-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss-2-thermal { + thermal-sensors = <&tsens6 2>; + + trips { + mdmss-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss-3-thermal { + thermal-sensors = <&tsens6 3>; + + trips { + mdmss-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors = <&tsens6 4>; + + trips { + camera-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors = <&tsens6 5>; + + trips { + camera-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens6 6>; + + trips { + video-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + video-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; From c61e0bb58ea475ad1f368f8ebcaa7c42c5c6634b Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 2 Feb 2026 22:06:21 -0800 Subject: [PATCH 0094/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add ADSP and CDSP for Kaanapali SoC Add remoteproc PAS loader for ADSP and CDSP with its SMP2P and fastrpc nodes. Co-developed-by: Kumari Pallavi Signed-off-by: Kumari Pallavi Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-4-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 314 ++++++++++++++++++++++++ 1 file changed, 314 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 10cfcf13ae9f8..ccc744e0caa72 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -443,6 +443,58 @@ }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -2478,6 +2530,111 @@ #reset-cells = <1>; }; + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <2>; + + label = "lpass"; + + fastrpc { + compatible = "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + }; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,kaanapali-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -4760,6 +4917,163 @@ #interconnect-cells = <2>; }; + remoteproc_cdsp: remoteproc@26300000 { + compatible = "qcom,kaanapali-cdsp-pas", "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x26300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x19c1 0x0>, + <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x0c21 0x0>, + <&apps_smmu 0x0c01 0x40>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x0c42 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c23 0x0>, + <&apps_smmu 0x0c03 0x40>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c44 0x0>, + <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c45 0x0>, + <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x0c46 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c27 0x0>, + <&apps_smmu 0x0c07 0x40>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x0c48 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c2c 0x00>, + <&apps_smmu 0x0c0c 0x40>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x40>, + <&apps_smmu 0x0c2e 0x0>, + <&apps_smmu 0x0c2d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + }; + }; + }; + /* Cluster 0 */ pmu@310b3400 { compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; From 83f9ffd3df240bb57d1eefd4d648f7dd8dcb2f45 Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Mon, 2 Feb 2026 22:06:22 -0800 Subject: [PATCH 0095/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add support for audio Introduce audio support for Kaanapali SoC by adding LPASS macro codecs, TLMM pin controller and SoundWire controller with similar hardware implementation to SM8750 platform. Also add GPR (Generic Pack Router) node along with support for APM (Audio Process Manager) and PRM (Proxy Resource Manager) audio services. Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-5-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 367 ++++++++++++++++++++++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index ccc744e0caa72..46096db17d6c6 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -16,7 +16,9 @@ #include #include #include +#include #include +#include #include "kaanapali-ipcc.h" @@ -2632,9 +2634,212 @@ dma-coherent; }; }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1041 0x20>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; + lpass_wsa2macro: codec@6aa0000 { + compatible = "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06aa0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + }; + + swr3: soundwire@6ab0000 { + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg = <0 0x06ab0000 0 0x10000>; + interrupts = ; + clocks = <&lpass_wsa2macro>; + clock-names = "iface"; + label = "WSA2"; + + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible = "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; + reg = <0x0 0x06ac0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr1: soundwire@6ad0000 { + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg = <0 0x06ad0000 0 0x10000>; + interrupts = ; + clocks = <&lpass_rxmacro>; + clock-names = "iface"; + label = "RX"; + + pinctrl-0 = <&rx_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <1>; + qcom,dout-ports = <11>; + + qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_txmacro: codec@6ae0000 { + compatible = "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; + reg = <0x0 0x06ae0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06b00000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr0: soundwire@6b10000 { + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg = <0 0x06b10000 0 0x10000>; + interrupts = ; + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + label = "WSA"; + + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,kaanapali-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -2649,6 +2854,168 @@ #interconnect-cells = <2>; }; + swr2: soundwire@7630000 { + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg = <0 0x07630000 0 0x10000>; + interrupts-extended = <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core", "wakeup"; + clocks = <&lpass_txmacro>; + clock-names = "iface"; + label = "TX"; + + pinctrl-0 = <&tx_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_vamacro: codec@7660000 { + compatible = "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; + reg = <0 0x07660000 0 0x2000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible = "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg = <0 0x07760000 0 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + lpass_ag_noc: interconnect@7f40000 { compatible = "qcom,kaanapali-lpass-ag-noc"; reg = <0x0 0x07f40000 0x0 0xe080>; From a6885df225b1e9f93ba794544f05fb3672ee1729 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 2 Feb 2026 22:06:23 -0800 Subject: [PATCH 0096/1330] FROMLIST: arm64: dts: qcom: kaanapali-mtp: Enable ADSP and CDSP Enable ADSP and CDSP on Kaanapali MTP board. Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-6-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 32a0825984346..3544f744fd1d8 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -684,6 +684,20 @@ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; }; +&remoteproc_adsp { + firmware-name = "qcom/kaanapali/adsp.mbn", + "qcom/kaanapali/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/kaanapali/cdsp.mbn", + "qcom/kaanapali/cdsp_dtb.mbn"; + + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; From aadee2a8aa57731d330e20f3113435c483a65205 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 2 Feb 2026 22:06:24 -0800 Subject: [PATCH 0097/1330] FROMLIST: arm64: dts: qcom: kaanapali-qrd: Enable ADSP and CDSP Enable ADSP and CDSP on Kaanapali QRD board. Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-7-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 66b423a497b39..32034eed03eb0 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -682,6 +682,20 @@ status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/kaanapali/adsp.mbn", + "qcom/kaanapali/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/kaanapali/cdsp.mbn", + "qcom/kaanapali/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ From f397cac3b0a3dd183f57c1e41a8f6cca75c1e0e2 Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Mon, 2 Feb 2026 22:06:25 -0800 Subject: [PATCH 0098/1330] FROMLIST: arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC) Add support for audio on the Kaanapali MTP platform by introducing device tree nodes for WSA8845 smart speaker amplifier for playback, DMIC microphone for capture, and sound card routing. The WCD9395 codec is add to supply MIC-BIAS, for enabling onboard microphone capture. Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-8-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 3544f744fd1d8..bc57935c042c9 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -52,6 +52,115 @@ clock-div = <2>; }; }; + + sound { + compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard"; + model = "Kaanapali-MTP"; + + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, + <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcd939x: audio-codec { + compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + vdd-px-supply = <&vreg_l1g_1p2>; + + #sound-dai-cells = <1>; + }; }; &apps_rsc { @@ -665,6 +774,14 @@ }; }; +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l10b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + &pcie0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -715,12 +832,114 @@ status = "okay"; }; +&swr0 { + status = "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_0_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 76 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l2i_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l2i_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + &tlmm { gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ <119 2>, /* SoCCP */ <144 4>; /* CXM UART */ + spkr_0_sd_n_active: spkr-0-sd-n-active-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + pcie0_default_state: pcie0-default-state { perst-n-pins { pins = "gpio102"; @@ -743,6 +962,13 @@ bias-pull-up; }; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio161"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; &uart7 { From f7257c500bd6c3d218cbd0c6ad67ce8d3f7181c4 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 2 Feb 2026 22:06:26 -0800 Subject: [PATCH 0099/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add support for MM clock controllers for Kaanapali Add the device nodes for the multimedia clock controllers (cambistmclkcc, camcc, dispcc, videocc, gpucc and gxclkctl). Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-9-79d20dab8a60@oss.qualcomm.com/ Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 111 ++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 46096db17d6c6..18c029f491786 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3,7 +3,13 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include +#include #include +#include +#include +#include #include #include #include @@ -1557,6 +1563,24 @@ <&rpmhcc RPMH_IPA_CLK>; }; + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,kaanapali-cambistmclkcc"; + reg = <0x0 0x01760000 0x0 0x8000>; + + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + mmss_noc: interconnect@1780000 { compatible = "qcom,kaanapali-mmss-noc"; reg = <0x0 0x01780000 0x0 0x5b800>; @@ -2532,6 +2556,46 @@ #reset-cells = <1>; }; + videocc: clock-controller@20f0000 { + compatible = "qcom,kaanapali-videocc"; + reg = <0x0 0x020f0000 0x0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,kaanapali-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,kaanapali-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + remoteproc_adsp: remoteproc@6800000 { compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; reg = <0x0 0x06800000 0x0 0x10000>; @@ -3073,6 +3137,53 @@ }; }; + camcc: clock-controller@956d000 { + compatible = "qcom,kaanapali-camcc"; + reg = <0x0 0x0956d000 0x0 0x80000>; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@9ba2000 { + compatible = "qcom,kaanapali-dispcc"; + reg = <0x0 0x09ba2000 0x0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,kaanapali-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, From 329efd12c4ddf9ae28a006af47ff8f4f4f8f078b Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Wed, 24 Sep 2025 17:17:37 -0700 Subject: [PATCH 0100/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add iris video node Add DT node for the kaanapali iris video node. Written with help from Taniya Das(added videocc node). Link: https://lore.kernel.org/all/20250924-knp-dts-v1-20-3fdbc4b9e1b1@oss.qualcomm.com/ Signed-off-by: Vikash Garodia Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 138 ++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 18c029f491786..9ab6ce49cc256 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2556,6 +2556,144 @@ #reset-cells = <1>; }; + iris: video-codec@2000000 { + compatible = "qcom,kaanapali-iris"; + + reg = <0x0 0x02000000 0x0 0xf0000>; + + interrupts = ; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&videocc VIDEO_CC_MVS0_VPP0_GDSC>, + <&videocc VIDEO_CC_MVS0_VPP1_GDSC>, + <&videocc VIDEO_CC_MVS0A_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "vpp0", + "vpp1", + "apv", + "mxc", + "mmcx"; + + operating-points-v2 = <&iris_opp_table>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0B_CLK>, + <&videocc VIDEO_CC_MVS0_VPP0_CLK>, + <&videocc VIDEO_CC_MVS0_VPP1_CLK>, + <&videocc VIDEO_CC_MVS0A_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun", + "vcodec_bse", + "vcodec_vpp0", + "vcodec_vpp1", + "vcodec_apv"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + memory-region = <&video_mem>; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>; + reset-names = "bus0", + "bus1", + "core_freerun_reset", + "vcodec0_core_freerun_reset"; + + iommus = <&apps_smmu 0x1940 0x0>, + <&apps_smmu 0x1943 0x0>, + <&apps_smmu 0x1944 0x0>, + <&apps_smmu 0x1a20 0x0>; + + dma-coherent; + + /* + * IRIS firmware is signed by vendors, only + * enable on boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 240000000 + 240000000 360000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000 338000000 + 338000000 507000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000 420000000 + 420000000 630000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000 444000000 + 444000000 666000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-533000000 { + opp-hz = /bits/ 64 <533000000 533000000 + 533000000 800000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000 630000000 + 630000000 1104000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000 630000000 + 630000000 1260000000>; + required-opps = <&rpmhpd_opp_turbo_l0>, + <&rpmhpd_opp_turbo_l0>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000 630000000 + 850000000 1260000000>; + required-opps = <&rpmhpd_opp_turbo_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + videocc: clock-controller@20f0000 { compatible = "qcom,kaanapali-videocc"; reg = <0x0 0x020f0000 0x0 0x10000>; From 8fead7e881065dd75bb96edbbbf8b9e082b7bee0 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 14:15:03 +0530 Subject: [PATCH 0101/1330] FROMLIST: arm64: dts: qcom: kaanpali: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for kaanapali. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-2-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 9ab6ce49cc256..c6786ab7afe15 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2537,7 +2537,11 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From 869c81795e649965ca380d7802fa18cac1cebd2c Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Sun, 15 Feb 2026 23:51:32 +0530 Subject: [PATCH 0102/1330] FROMLIST: misc: fastrpc: Move fdlist to invoke context structure The fdlist is currently part of the meta buffer, computed during put_args. This leads to code duplication when preparing and reading critical meta buffer contents used by the FastRPC driver. Move fdlist to the invoke context structure to improve maintainability and reduce redundancy. This centralizes its handling and simplifies meta buffer preparation and reading logic. Link: https://lore.kernel.org/all/20260215182136.3995111-2-ekansh.gupta@oss.qualcomm.com/ Signed-off-by: Ekansh Gupta --- drivers/misc/fastrpc.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 1080f9acf70a3..e6e27fd25eba4 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -233,6 +233,7 @@ struct fastrpc_invoke_ctx { int pid; int client_id; u32 sc; + u64 *fdlist; u32 *crc; u64 ctxid; u64 msg_sz; @@ -1016,6 +1017,7 @@ static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) rpra = ctx->buf->virt; list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); pages = fastrpc_phy_page_start(list, ctx->nscalars); + ctx->fdlist = (u64 *)(pages + ctx->nscalars); args = (uintptr_t)ctx->buf->virt + metalen; rlen = pkt_size - metalen; ctx->rpra = rpra; @@ -1118,18 +1120,10 @@ static int fastrpc_put_args(struct fastrpc_invoke_ctx *ctx, union fastrpc_remote_arg *rpra = ctx->rpra; struct fastrpc_user *fl = ctx->fl; struct fastrpc_map *mmap = NULL; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - u64 *fdlist; - int i, inbufs, outbufs, handles; + int i, inbufs; int ret = 0; inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - outbufs = REMOTE_SCALARS_OUTBUFS(ctx->sc); - handles = REMOTE_SCALARS_INHANDLES(ctx->sc) + REMOTE_SCALARS_OUTHANDLES(ctx->sc); - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); - fdlist = (uint64_t *)(pages + inbufs + outbufs + handles); for (i = inbufs; i < ctx->nbufs; ++i) { if (!ctx->maps[i]) { @@ -1151,9 +1145,9 @@ static int fastrpc_put_args(struct fastrpc_invoke_ctx *ctx, cleanup_fdlist: /* Clean up fdlist which is updated by DSP */ for (i = 0; i < FASTRPC_MAX_FDLIST; i++) { - if (!fdlist[i]) + if (!ctx->fdlist[i]) break; - if (!fastrpc_map_lookup(fl, (int)fdlist[i], &mmap)) + if (!fastrpc_map_lookup(fl, (int)ctx->fdlist[i], &mmap)) fastrpc_map_put(mmap); } From 215eab37533dc9984650fc56f5526c1a143031d4 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Sun, 15 Feb 2026 23:51:33 +0530 Subject: [PATCH 0103/1330] FROMLIST: misc: fastrpc: Replace hardcoded ctxid mask with GENMASK Replace the hardcoded context ID mask (0xFF0) with GENMASK(11, 4) to improve readability and follow kernel bitfield conventions. Use FIELD_PREP and FIELD_GET instead of manual shifts for setting and extracting ctxid values. Link: https://lore.kernel.org/all/20260215182136.3995111-3-ekansh.gupta@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Ekansh Gupta --- drivers/misc/fastrpc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index e6e27fd25eba4..2b2e817296a8a 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -37,7 +37,7 @@ #define FASTRPC_CTX_MAX (256) #define FASTRPC_INIT_HANDLE 1 #define FASTRPC_DSP_UTILITIES_HANDLE 2 -#define FASTRPC_CTXID_MASK (0xFF0) +#define FASTRPC_CTXID_MASK GENMASK(11, 4) #define INIT_FILELEN_MAX (2 * 1024 * 1024) #define INIT_FILE_NAMELEN_MAX (128) #define FASTRPC_DEVICE_NAME "fastrpc" @@ -515,7 +515,7 @@ static void fastrpc_context_free(struct kref *ref) fastrpc_buf_free(ctx->buf); spin_lock_irqsave(&cctx->lock, flags); - idr_remove(&cctx->ctx_idr, ctx->ctxid >> 4); + idr_remove(&cctx->ctx_idr, FIELD_GET(FASTRPC_CTXID_MASK, ctx->ctxid)); spin_unlock_irqrestore(&cctx->lock, flags); kfree(ctx->maps); @@ -649,7 +649,7 @@ static struct fastrpc_invoke_ctx *fastrpc_context_alloc( spin_unlock_irqrestore(&cctx->lock, flags); goto err_idr; } - ctx->ctxid = ret << 4; + ctx->ctxid = FIELD_PREP(FASTRPC_CTXID_MASK, ret); spin_unlock_irqrestore(&cctx->lock, flags); kref_init(&ctx->refcount); @@ -2507,7 +2507,7 @@ static int fastrpc_rpmsg_callback(struct rpmsg_device *rpdev, void *data, if (len < sizeof(*rsp)) return -EINVAL; - ctxid = ((rsp->ctx & FASTRPC_CTXID_MASK) >> 4); + ctxid = FIELD_GET(FASTRPC_CTXID_MASK, rsp->ctx); spin_lock_irqsave(&cctx->lock, flags); ctx = idr_find(&cctx->ctx_idr, ctxid); From a8e87184bd09c876ef1969490b984c61098ea0c2 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Sun, 15 Feb 2026 23:51:34 +0530 Subject: [PATCH 0104/1330] FROMLIST: misc: fastrpc: Expand context ID mask for DSP polling mode support Current FastRPC context uses a 12-bit mask: [ID(8 bits)][PD type(4 bits)] = GENMASK(11, 4) This works for normal calls but fails for DSP polling mode. Polling mode expects a 16-bit layout: [15:8] = context ID (8 bits) [7:5] = reserved [4] = async mode bit [3:0] = PD type (4 bits) If async bit (bit 4) is set, DSP disables polling. With current mask, odd IDs can set this bit, causing DSP to skip poll updates. Update FASTRPC_CTXID_MASK to GENMASK(15, 8) so IDs occupy upper byte and lower byte is left for DSP flags and PD type. Reserved bits remain unused. This change is compatible with polling mode and does not break non-polling behavior. Bit layout: [15:8] = CCCCCCCC (context ID) [7:5] = xxx (reserved) [4] = A (async mode) [3:0] = PPPP (PD type) Link: https://lore.kernel.org/all/20260215182136.3995111-4-ekansh.gupta@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Signed-off-by: Ekansh Gupta --- drivers/misc/fastrpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 2b2e817296a8a..4eb37839343db 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -37,7 +37,7 @@ #define FASTRPC_CTX_MAX (256) #define FASTRPC_INIT_HANDLE 1 #define FASTRPC_DSP_UTILITIES_HANDLE 2 -#define FASTRPC_CTXID_MASK GENMASK(11, 4) +#define FASTRPC_CTXID_MASK GENMASK(15, 8) #define INIT_FILELEN_MAX (2 * 1024 * 1024) #define INIT_FILE_NAMELEN_MAX (128) #define FASTRPC_DEVICE_NAME "fastrpc" From 7dd7efa9378963db1c0325fb8f9fcd7d7fddb8fa Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Sun, 15 Feb 2026 23:51:35 +0530 Subject: [PATCH 0105/1330] FROMLIST: misc: fastrpc: Add polling mode support for fastRPC driver For any remote call to DSP, after sending an invocation message, fastRPC driver waits for glink response and during this time the CPU can go into low power modes. This adds latency to overall fastrpc call as CPU wakeup and scheduling latencies are included. Add polling mode support with which fastRPC driver will poll continuously on a memory after sending a message to remote subsystem which will eliminate CPU wakeup and scheduling latencies and reduce fastRPC overhead. Poll mode can be enabled by user by using FASTRPC_IOCTL_SET_OPTION ioctl request with FASTRPC_POLL_MODE request id. Link: https://lore.kernel.org/all/20260215182136.3995111-5-ekansh.gupta@oss.qualcomm.com/ Signed-off-by: Ekansh Gupta --- drivers/misc/fastrpc.c | 142 ++++++++++++++++++++++++++++++++++-- include/uapi/misc/fastrpc.h | 10 +++ 2 files changed, 145 insertions(+), 7 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 4eb37839343db..ffd2af2e5aacd 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include #define ADSP_DOMAIN_ID (0) #define MDSP_DOMAIN_ID (1) @@ -37,6 +39,7 @@ #define FASTRPC_CTX_MAX (256) #define FASTRPC_INIT_HANDLE 1 #define FASTRPC_DSP_UTILITIES_HANDLE 2 +#define FASTRPC_MAX_STATIC_HANDLE (20) #define FASTRPC_CTXID_MASK GENMASK(15, 8) #define INIT_FILELEN_MAX (2 * 1024 * 1024) #define INIT_FILE_NAMELEN_MAX (128) @@ -105,6 +108,12 @@ #define miscdev_to_fdevice(d) container_of(d, struct fastrpc_device, miscdev) +/* Poll response number from remote processor for call completion */ +#define FASTRPC_POLL_RESPONSE (0xdecaf) + +/* Polling mode timeout limit */ +#define FASTRPC_POLL_MAX_TIMEOUT_US (10000) + struct fastrpc_phy_page { dma_addr_t addr; /* dma address */ u64 size; /* size of contiguous region */ @@ -235,8 +244,14 @@ struct fastrpc_invoke_ctx { u32 sc; u64 *fdlist; u32 *crc; + /* Poll memory that DSP updates */ + u32 *poll; u64 ctxid; u64 msg_sz; + /* work done status flag */ + bool is_work_done; + /* process updates poll memory instead of glink response */ + bool is_polled; struct kref refcount; struct list_head node; /* list of ctxs */ struct completion work; @@ -307,6 +322,8 @@ struct fastrpc_user { int client_id; int pd; bool is_secure_dev; + /* Flags poll mode state */ + bool poll_mode; /* Lock for lists */ spinlock_t lock; /* lock for allocations */ @@ -922,7 +939,8 @@ static int fastrpc_get_meta_size(struct fastrpc_invoke_ctx *ctx) sizeof(struct fastrpc_invoke_buf) + sizeof(struct fastrpc_phy_page)) * ctx->nscalars + sizeof(u64) * FASTRPC_MAX_FDLIST + - sizeof(u32) * FASTRPC_MAX_CRCLIST; + sizeof(u32) * FASTRPC_MAX_CRCLIST + + sizeof(u32); return size; } @@ -1018,6 +1036,9 @@ static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); pages = fastrpc_phy_page_start(list, ctx->nscalars); ctx->fdlist = (u64 *)(pages + ctx->nscalars); + ctx->poll = (u32 *)((uintptr_t)ctx->fdlist + sizeof(u64) * FASTRPC_MAX_FDLIST + + sizeof(u32) * FASTRPC_MAX_CRCLIST); + args = (uintptr_t)ctx->buf->virt + metalen; rlen = pkt_size - metalen; ctx->rpra = rpra; @@ -1186,6 +1207,75 @@ static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, } +static inline u32 fastrpc_poll_op(void *p) +{ + struct fastrpc_invoke_ctx *ctx = p; + + dma_rmb(); + return READ_ONCE(*ctx->poll); +} + +static int poll_for_remote_response(struct fastrpc_invoke_ctx *ctx) +{ + u32 val; + int ret; + + /* + * Poll until DSP writes FASTRPC_POLL_RESPONSE into *ctx->poll + * or until another path marks the work done. + */ + ret = read_poll_timeout_atomic(fastrpc_poll_op, val, + (val == FASTRPC_POLL_RESPONSE) || + ctx->is_work_done, 1, + FASTRPC_POLL_MAX_TIMEOUT_US, false, ctx); + + if (!ret && val == FASTRPC_POLL_RESPONSE) { + ctx->is_work_done = true; + ctx->retval = 0; + } + + if (ret == -ETIMEDOUT) + ret = -EIO; + + return ret; +} + +static inline int fastrpc_wait_for_response(struct fastrpc_invoke_ctx *ctx, + u32 kernel) +{ + int err = 0; + + if (kernel) { + if (!wait_for_completion_timeout(&ctx->work, 10 * HZ)) + err = -ETIMEDOUT; + } else { + err = wait_for_completion_interruptible(&ctx->work); + } + + return err; +} + +static int fastrpc_wait_for_completion(struct fastrpc_invoke_ctx *ctx, + u32 kernel) +{ + int err; + + do { + if (ctx->is_polled) { + err = poll_for_remote_response(ctx); + /* If polling timed out, move to normal response mode */ + if (err) + ctx->is_polled = false; + } else { + err = fastrpc_wait_for_response(ctx, kernel); + if (err) + return err; + } + } while (!ctx->is_work_done); + + return err; +} + static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, u32 handle, u32 sc, struct fastrpc_invoke_args *args) @@ -1221,16 +1311,26 @@ static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, if (err) goto bail; - if (kernel) { - if (!wait_for_completion_timeout(&ctx->work, 10 * HZ)) - err = -ETIMEDOUT; - } else { - err = wait_for_completion_interruptible(&ctx->work); - } + /* + * Set message context as polled if the call is for a user PD + * dynamic module and user has enabled poll mode. + */ + if (handle > FASTRPC_MAX_STATIC_HANDLE && fl->pd == USER_PD && + fl->poll_mode) + ctx->is_polled = true; + + err = fastrpc_wait_for_completion(ctx, kernel); if (err) goto bail; + if (!ctx->is_work_done) { + err = -ETIMEDOUT; + dev_dbg(fl->sctx->dev, "Invalid workdone state for handle 0x%x, sc 0x%x\n", + handle, sc); + goto bail; + } + /* make sure that all memory writes by DSP are seen by CPU */ dma_rmb(); /* populate all the output buffers with results */ @@ -1811,6 +1911,30 @@ static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap, return 0; } +static int fastrpc_set_option(struct fastrpc_user *fl, char __user *argp) +{ + struct fastrpc_ioctl_set_option opt = {0}; + int i; + + if (copy_from_user(&opt, argp, sizeof(opt))) + return -EFAULT; + + for (i = 0; i < ARRAY_SIZE(opt.reserved); i++) { + if (opt.reserved[i] != 0) + return -EINVAL; + } + + if (opt.req != FASTRPC_POLL_MODE) + return -EINVAL; + + if (opt.value) + fl->poll_mode = true; + else + fl->poll_mode = false; + + return 0; +} + static int fastrpc_get_dsp_info(struct fastrpc_user *fl, char __user *argp) { struct fastrpc_ioctl_capability cap = {0}; @@ -2166,6 +2290,9 @@ static long fastrpc_device_ioctl(struct file *file, unsigned int cmd, case FASTRPC_IOCTL_MEM_UNMAP: err = fastrpc_req_mem_unmap(fl, argp); break; + case FASTRPC_IOCTL_SET_OPTION: + err = fastrpc_set_option(fl, argp); + break; case FASTRPC_IOCTL_GET_DSP_INFO: err = fastrpc_get_dsp_info(fl, argp); break; @@ -2519,6 +2646,7 @@ static int fastrpc_rpmsg_callback(struct rpmsg_device *rpdev, void *data, } ctx->retval = rsp->retval; + ctx->is_work_done = true; complete(&ctx->work); /* diff --git a/include/uapi/misc/fastrpc.h b/include/uapi/misc/fastrpc.h index c6e2925f47e69..c37e24a764ae6 100644 --- a/include/uapi/misc/fastrpc.h +++ b/include/uapi/misc/fastrpc.h @@ -16,6 +16,7 @@ #define FASTRPC_IOCTL_INIT_CREATE_STATIC _IOWR('R', 9, struct fastrpc_init_create_static) #define FASTRPC_IOCTL_MEM_MAP _IOWR('R', 10, struct fastrpc_mem_map) #define FASTRPC_IOCTL_MEM_UNMAP _IOWR('R', 11, struct fastrpc_mem_unmap) +#define FASTRPC_IOCTL_SET_OPTION _IOWR('R', 12, struct fastrpc_ioctl_set_option) #define FASTRPC_IOCTL_GET_DSP_INFO _IOWR('R', 13, struct fastrpc_ioctl_capability) /** @@ -67,6 +68,9 @@ enum fastrpc_proc_attr { /* Fastrpc attribute for memory protection of buffers */ #define FASTRPC_ATTR_SECUREMAP (1) +/* Set option request ID to enable poll mode */ +#define FASTRPC_POLL_MODE (1) + struct fastrpc_invoke_args { __u64 ptr; __u64 length; @@ -133,6 +137,12 @@ struct fastrpc_mem_unmap { __s32 reserved[5]; }; +struct fastrpc_ioctl_set_option { + __u32 req; /* request id */ + __u32 value; /* value */ + __s32 reserved[6]; +}; + struct fastrpc_ioctl_capability { __u32 unused; /* deprecated, ignored by the kernel */ __u32 attribute_id; From cf793a93f2b433a266b469f787fc26273ecf0998 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 24 Nov 2025 02:24:34 -0800 Subject: [PATCH 0106/1330] FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Kaanapali compatible Document compatible for the QMP PCIe PHY on Kaanapali platform. Link: https://lore.kernel.org/all/20251124-kaanapali-pcie-phy-v4-1-d04ee9cca83b@oss.qualcomm.com/ Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Qiang Yu --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 3a35120a77ec0..83df98c352702 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -183,6 +183,7 @@ allOf: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy From 735929c63d174e66114d2c021e5a6997198c4984 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 28 Jan 2026 17:10:42 +0530 Subject: [PATCH 0107/1330] FROMLIST: PCI: dwc: Use common D3cold eligibility helper in suspend path Previously, the driver skipped putting the link into L2/device state in D3cold whenever L1 ASPM was enabled, since some devices (e.g. NVMe) expect low resume latency and may not tolerate deeper power states. However, such devices typically remain in D0 and are already covered by the new helper's requirement that all endpoints be in D3hot before the host bridge may enter D3cold. So, replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with the shared pci_host_common_can_enter_d3cold() helper to decide whether the DesignWare host bridge can safely transition to D3cold. Link: https://lore.kernel.org/r/20260128-d3cold-v1-2-dd8f3f0ce824@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 7 +------ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 6adde3fc32be9..d615249b1f989 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1218,18 +1218,13 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) int dw_pcie_suspend_noirq(struct dw_pcie *pci) { - u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int ret = 0; u32 val; if (!dw_pcie_link_up(pci)) goto stop_link; - /* - * If L1SS is supported, then do not put the link into L2 as some - * devices such as NVMe expect low resume latency. - */ - if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1) + if (!pci_host_common_can_enter_d3cold(pci->pp.bridge)) return 0; if (pci->pp.ops->pme_turn_off) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 3e69ef60165b0..3957babd1c3d8 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -26,6 +26,7 @@ #include #include +#include "../pci-host-common.h" #include "../../pci.h" /* DWC PCIe IP-core versions (native support since v4.70a) */ From c93e9564e959835bfec687b8224e7e571adbde71 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 28 Jan 2026 17:10:41 +0530 Subject: [PATCH 0108/1330] FROMLIST: PCI: host-common: Add shared D3cold eligibility helper for host bridges Add a common helper, pci_host_common_can_enter_d3cold(), to determine whether a PCI host bridge can safely transition to D3cold. The helper walks all devices on the bridge's bus and only allows the host bridge to enter D3cold if all PCIe endpoints are already in PCI_D3hot. For devices that may wake the system, it additionally requires that the device supports PME wakeup from D3cold(with WAKE#). Devices without wakeup enabled are not restricted by this check and can be allowed to keep device in D3cold. Link: https://lore.kernel.org/r/20260128-d3cold-v1-1-dd8f3f0ce824@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/pci-host-common.c | 29 ++++++++++++++++++++++++ drivers/pci/controller/pci-host-common.h | 2 ++ 2 files changed, 31 insertions(+) diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c index d6258c1cffe5e..1e53819f5e720 100644 --- a/drivers/pci/controller/pci-host-common.c +++ b/drivers/pci/controller/pci-host-common.c @@ -106,5 +106,34 @@ void pci_host_common_remove(struct platform_device *pdev) } EXPORT_SYMBOL_GPL(pci_host_common_remove); +static int pci_host_common_check_d3cold(struct pci_dev *pdev, void *userdata) +{ + bool *d3cold_allow = userdata; + + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ENDPOINT) + return 0; + + if (pdev->current_state != PCI_D3hot) + goto exit; + + if (device_may_wakeup(&pdev->dev) && !pci_pme_capable(pdev, PCI_D3cold)) + goto exit; + + return 0; +exit: + *d3cold_allow = false; + return -EBUSY; +} + +bool pci_host_common_can_enter_d3cold(struct pci_host_bridge *bridge) +{ + bool d3cold_allow = true; + + pci_walk_bus(bridge->bus, pci_host_common_check_d3cold, &d3cold_allow); + + return d3cold_allow; +} +EXPORT_SYMBOL_GPL(pci_host_common_can_enter_d3cold); + MODULE_DESCRIPTION("Common library for PCI host controller drivers"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/controller/pci-host-common.h index b5075d4bd7eb3..18a731bca0588 100644 --- a/drivers/pci/controller/pci-host-common.h +++ b/drivers/pci/controller/pci-host-common.h @@ -20,4 +20,6 @@ void pci_host_common_remove(struct platform_device *pdev); struct pci_config_window *pci_host_common_ecam_create(struct device *dev, struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops); + +bool pci_host_common_can_enter_d3cold(struct pci_host_bridge *bridge); #endif From e2e457a87faf6334a546545e3a5bceea315c3ac7 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 28 Jan 2026 17:10:43 +0530 Subject: [PATCH 0109/1330] FROMLIST: PCI: qcom: Add D3cold support Add pme_turn_off() support and use DWC common suspend resume methods for device D3cold entry & exit. If the device is not kept in D3cold use existing methods like keeping icc votes, opp votes etc.. intact. In qcom_pcie_deinit_2_7_0(), explicitly disable PCIe clocks and resets in the controller. Remove suspended flag from qcom_pcie structure as it is no longer needed. Link: https://lore.kernel.org/r/20260128-d3cold-v1-3-dd8f3f0ce824@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 116 +++++++++++++++---------- 1 file changed, 69 insertions(+), 47 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9fdfc88ac1512..d01c7c5b28f84 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -144,6 +144,7 @@ /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) +#define ELBI_SYS_CTRL_PME_TURNOFF_MSG BIT(4) /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 @@ -282,7 +283,6 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; struct list_head ports; - bool suspended; bool use_pm_opp; }; @@ -1069,6 +1069,12 @@ static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + u32 val; + + /* Disable PCIe clocks and resets */ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); @@ -1372,10 +1378,18 @@ static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) pcie->cfg->ops->host_post_init(pcie); } +static void qcom_pcie_host_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + writel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pci->elbi_base + ELBI_SYS_CTRL); +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { .init = qcom_pcie_host_init, .deinit = qcom_pcie_host_deinit, .post_init = qcom_pcie_host_post_init, + .pme_turn_off = qcom_pcie_host_pme_turn_off, }; /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ @@ -2039,53 +2053,51 @@ static int qcom_pcie_suspend_noirq(struct device *dev) if (!pcie) return 0; - /* - * Set minimum bandwidth required to keep data path functional during - * suspend. - */ - if (pcie->icc_mem) { - ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); - if (ret) { - dev_err(dev, - "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", - ret); - return ret; - } - } + ret = dw_pcie_suspend_noirq(pcie->pci); + if (ret) + return ret; - /* - * Turn OFF the resources only for controllers without active PCIe - * devices. For controllers with active devices, the resources are kept - * ON and the link is expected to be in L0/L1 (sub)states. - * - * Turning OFF the resources for controllers with active PCIe devices - * will trigger access violation during the end of the suspend cycle, - * as kernel tries to access the PCIe devices config space for masking - * MSIs. - * - * Also, it is not desirable to put the link into L2/L3 state as that - * implies VDD supply will be removed and the devices may go into - * powerdown state. This will affect the lifetime of the storage devices - * like NVMe. - */ - if (!dw_pcie_link_up(pcie->pci)) { - qcom_pcie_host_deinit(&pcie->pci->pp); - pcie->suspended = true; - } + if (pcie->pci->suspended) { + ret = icc_disable(pcie->icc_mem); + if (ret) + dev_err(dev, "Failed to disable PCIe-MEM interconnect path: %d\n", ret); - /* - * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. - * Because on some platforms, DBI access can happen very late during the - * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC - * error. - */ - if (pm_suspend_target_state != PM_SUSPEND_MEM) { ret = icc_disable(pcie->icc_cpu); if (ret) dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); if (pcie->use_pm_opp) dev_pm_opp_set_opp(pcie->pci->dev, NULL); + } else { + /* + * Set minimum bandwidth required to keep data path functional during + * suspend. + */ + if (pcie->icc_mem) { + ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); + if (ret) { + dev_err(dev, + "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + return ret; + } + } + + /* + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. + * Because on some platforms, DBI access can happen very late during the + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC + * error. + */ + if (pm_suspend_target_state != PM_SUSPEND_MEM) { + ret = icc_disable(pcie->icc_cpu); + if (ret) + dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", + ret); + + if (pcie->use_pm_opp) + dev_pm_opp_set_opp(pcie->pci->dev, NULL); + } } return ret; } @@ -2099,20 +2111,30 @@ static int qcom_pcie_resume_noirq(struct device *dev) if (!pcie) return 0; - if (pm_suspend_target_state != PM_SUSPEND_MEM) { + if (pcie->pci->suspended) { ret = icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); return ret; } - } - if (pcie->suspended) { - ret = qcom_pcie_host_init(&pcie->pci->pp); - if (ret) + ret = icc_enable(pcie->icc_mem); + if (ret) { + dev_err(dev, "Failed to enable PCIe-MEM interconnect path: %d\n", ret); return ret; - - pcie->suspended = false; + } + ret = dw_pcie_resume_noirq(pcie->pci); + if (ret && (ret != -ETIMEDOUT)) + return ret; + } else { + if (pm_suspend_target_state != PM_SUSPEND_MEM) { + ret = icc_enable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", + ret); + return ret; + } + } } qcom_pcie_icc_opp_update(pcie); From 3f33a71ccbd2ff9d33c7c4cdf33cc177c6efbea5 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 28 Jan 2026 17:52:42 +0530 Subject: [PATCH 0110/1330] FROMLIST: PCI: qcom: Prevent GDSC power down on suspend Currently, the driver expects the devices to remain in D0 across system suspend, but the genpd framework may still power down the associated GDSC during suspend. When that happens, the PCIe link goes down and cannot be recovered on resume. Prevent genpd from turning off the PCIe GDSC by using dev_pm_genpd_rpm_always_on() so that the power domain stays on while the controller is suspended. This preserves the link state across suspend/resume and avoids unrecoverable link failures. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20260128-genpd_fix-v1-1-cd45a249d12f@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index d01c7c5b28f84..4a824998bef8f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -2057,6 +2058,11 @@ static int qcom_pcie_suspend_noirq(struct device *dev) if (ret) return ret; + if (pcie->pci->suspended) + dev_pm_genpd_rpm_always_on(dev, false); + else + dev_pm_genpd_rpm_always_on(dev, true); + if (pcie->pci->suspended) { ret = icc_disable(pcie->icc_mem); if (ret) From 41920d5d7623512fcfb1026603f7057ea095966d Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 29 May 2025 17:06:00 +0530 Subject: [PATCH 0111/1330] QCLINUX: defconfig: Introduce prune.config fragment Add prune.config fragment to disable support for non-Qualcomm architectures. This helps reduce boot image size and improves kernel build KPIs by trimming unnecessary configuration options. Signed-off-by: Komal Bajaj --- arch/arm64/configs/prune.config | 326 ++++++++++++++++++++++++++++++++ 1 file changed, 326 insertions(+) create mode 100644 arch/arm64/configs/prune.config diff --git a/arch/arm64/configs/prune.config b/arch/arm64/configs/prune.config new file mode 100644 index 0000000000000..54cf8fa1cd0e0 --- /dev/null +++ b/arch/arm64/configs/prune.config @@ -0,0 +1,326 @@ +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AIROHA is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BCMBCA is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BLAIZE is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_NXP is not set +# CONFIG_ARCH_MA35 is not set +# CONFIG_ARCH_NPCM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set +# CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_TESLA_FSD is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VISCONTI is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZYNQMP is not set +# CONFIG_MOUSE_PS2 is not set +# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set +# CONFIG_NET_DSA_TAG_OCELOT is not set +# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set +# CONFIG_BT_HCIBTUSB_MTK is not set +# CONFIG_BT_HCIUART_BCM is not set +# CONFIG_BT_HCIUART_MRVL is not set +# CONFIG_BT_MRVL is not set +# CONFIG_BT_MRVL_SDIO is not set +# CONFIG_PCIE_ALTERA is not set +# CONFIG_PCIE_ALTERA_MSI is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCI_MESON is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_GNSS_MTK_SERIAL is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_NAND_DENALI_DT is not set +# CONFIG_MTD_NAND_BRCMNAND is not set +# CONFIG_MTD_NAND_BRCMNAND_BCMBCA is not set +# CONFIG_MTD_NAND_BRCMNAND_BRCMSTB is not set +# CONFIG_MTD_NAND_BRCMNAND_IPROC is not set +# CONFIG_B53_SRAB_DRIVER is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_AMD_XGBE is not set +# CONFIG_BCMGENET is not set +# CONFIG_BNX2X is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_MACB is not set +# CONFIG_THUNDER_NIC_PF is not set +# CONFIG_HIX5HD2_GMAC is not set +# CONFIG_HNS_DSAF is not set +# CONFIG_HNS_ENET is not set +# CONFIG_HNS3 is not set +# CONFIG_HNS3_HCLGE is not set +# CONFIG_HNS3_ENET is not set +# CONFIG_MVMDIO is not set +# CONFIG_SKY2 is not set +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLX5_CORE_EN is not set +# CONFIG_R8169 is not set +# CONFIG_SMC91X is not set +# CONFIG_SMSC911X is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83TD510_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_MCP251XFD is not set +# CONFIG_BRCMFMAC is not set +# CONFIG_MWIFIEX is not set +# CONFIG_MWIFIEX_SDIO is not set +# CONFIG_MWIFIEX_PCIE is not set +# CONFIG_MT7921E is not set +# CONFIG_WL18XX is not set +# CONFIG_WLCORE_SDIO is not set +# CONFIG_KEYBOARD_CROS_EC is not set +# CONFIG_KEYBOARD_MTK_PMIC is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_INPUT_TPS65219_PWRBUTTON is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART_CONSOLE is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LPUART_CONSOLE is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE is not set +# CONFIG_TCG_TIS_SPI_CR50 is not set +# CONFIG_TCG_TIS_I2C_CR50 is not set +# CONFIG_TCG_TIS_I2C_INFINEON is not set +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_CROS_EC_TUNNEL is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_DW_DMA is not set +# CONFIG_SPI_DW_MMIO is not set +# CONFIG_PINCTRL_MAX77620 is not set +# CONFIG_CHARGER_MT6360 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_PM8916_WATCHDOG is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_REGULATOR_AXP20X is not set +# CONFIG_REGULATOR_BD718XX is not set +# CONFIG_REGULATOR_BD9571MWV is not set +# CONFIG_REGULATOR_CROS_EC is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_HI6421V530 is not set +# CONFIG_REGULATOR_MAX77620 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MT6315 is not set +# CONFIG_REGULATOR_MT6357 is not set +# CONFIG_REGULATOR_MT6358 is not set +# CONFIG_REGULATOR_MT6359 is not set +# CONFIG_REGULATOR_MT6360 is not set +# CONFIG_REGULATOR_MT6397 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_RK808 is not set +# CONFIG_REGULATOR_S2MPS11 is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS65219 is not set +# CONFIG_REGULATOR_RK808 is not set +# CONFIG_REGULATOR_S2MPS11 is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS65219 is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_SAMSUNG_DSIM is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_I2C_ADV7511_AUDIO is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_PL111 is not set +# CONFIG_DRM_LIMA is not set +# CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_TIDSS is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_EASRC is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set +# CONFIG_MMC_SDHCI_CADENCE is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX77686 is not set +# CONFIG_RTC_DRV_RK808 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_S5M is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_CROS_EC is not set +# CONFIG_RTC_DRV_MT6397 is not set +# CONFIG_BCM_SBA_RAID is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_MV_XOR_V2 is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CROS_EC is not set +# CONFIG_CROS_EC_I2C is not set +# CONFIG_CROS_EC_RPMSG is not set +# CONFIG_CROS_EC_SPI is not set +# CONFIG_CROS_EC_CHARDEV is not set +# CONFIG_CLK_VEXPRESS_OSC is not set +# CONFIG_COMMON_CLK_RK808 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_S2MPS11 is not set +# CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_BD718XX is not set +# CONFIG_SOC_TI is not set +# CONFIG_TI_ADS1015 is not set +# CONFIG_TI_AM335X_ADC is not set +# CONFIG_IIO_CROS_EC_SENSORS_CORE is not set +# CONFIG_IIO_CROS_EC_SENSORS is not set +# CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_CROS_EC_LIGHT_PROX is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_VCNL4000 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_IIO_CROS_EC_BARO is not set +# CONFIG_MPL3115 is not set +# CONFIG_PWM_CROS_EC is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set +# CONFIG_CRYPTO_DEV_HISI_ZIP is not set +# CONFIG_CRYPTO_DEV_HISI_HPRE is not set +# CONFIG_CRYPTO_DEV_HISI_TRNG is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_DEVMEM is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set From c326e427bb104f67cc0dfafd58002dc86bc3e7b0 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 23 Sep 2025 14:20:27 +0530 Subject: [PATCH 0112/1330] QCLINUX: defconfig: Define qcom.config and enable DMABUF heaps Introduce `qcom.config`, a Qualcomm-specific kernel configuration fragment that enables features required by Qualcomm SoCs. It includes CONFIGs not acceptable under the community's common defconfig and ensures essential features and subsystems required by Qualcomm platforms are enbaled. This initial version of `qcom.config` enables DMABUF heap support, including the system heap and default CMA heap. These configurations are essential for buffer sharing across subsystems such as camera, display, and DSP on Qualcomm platforms like qcs6490. Signed-off-by: Komal Bajaj --- arch/arm64/configs/qcom.config | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/arm64/configs/qcom.config diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config new file mode 100644 index 0000000000000..7458e86bdc06c --- /dev/null +++ b/arch/arm64/configs/qcom.config @@ -0,0 +1,8 @@ +# qcom.config for Qualcomm-specific kernel configuration +# +# $ make ARCH=arm64 defconfig qcom.config +# +# Keep alphabetically sorted +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_SYSTEM=y From 02c0ab9a1e7f3f6f6eaff9809f66ce1b0ac45079 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 26 Sep 2025 10:08:11 +0800 Subject: [PATCH 0113/1330] QCLINUX: arch: arm64: configs: Enable coresight components in qcom.config Add Coresight configs to enable Coresight device drivers on mainline. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom.config | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 7458e86bdc06c..52b94c17169d0 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -3,6 +3,12 @@ # $ make ARCH=arm64 defconfig qcom.config # # Keep alphabetically sorted +CONFIG_CORESIGHT_CORESIGHT_TNOC=m +CONFIG_CORESIGHT_CTCU=m +CONFIG_CORESIGHT_DUMMY=m +CONFIG_CORESIGHT_SOURCE_ETM4X=m +CONFIG_CORESIGHT_TGU=m +CONFIG_CORESIGHT_TPDM=m CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_CMA=y CONFIG_DMABUF_HEAPS_SYSTEM=y From 2f75bee6b253423a4e2cbcde1d7258c5327174c0 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 30 Sep 2025 18:27:55 +0530 Subject: [PATCH 0114/1330] QCLINUX: defconfig: enable zram defconfig on qcom.config Enable ZRAM defconfig on qcom.config. This empowers users to use the compressed block devices for usecases, eg: swap device on zram. Tested: make ARCH=arm64 menuconfig defconfig qcom.config, booted with this configuration on QEMU and verified if /dev/zram0 is exist. Signed-off-by: Charan Teja Kalla --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 52b94c17169d0..93e642c519059 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -12,3 +12,4 @@ CONFIG_CORESIGHT_TPDM=m CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_CMA=y CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_ZRAM=y From 20b58fd093c88d53c06f75141c3d3d7416fbe8ef Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 6 Oct 2025 16:56:58 +0530 Subject: [PATCH 0115/1330] QCLINUX: defconfig: Enable scheduler and thermal related configs Enabled key configs for thermal management (CPU_IDLE_THERMAL, IDLE_INJECT), scheduler (SCHED_DEBUG, SCHEDSTATS, TRACE_MMIO_ACCESS), and power control (POWERCAP, UCLAMP_TASK). Also enabled KPROBES, PAN emulation and watchdog pretimeout panic governor for improved instrumentation and security. Signed-off-by: Komal Bajaj --- arch/arm64/configs/qcom.config | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 93e642c519059..9cd2b50f8b367 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -3,13 +3,30 @@ # $ make ARCH=arm64 defconfig qcom.config # # Keep alphabetically sorted +CONFIG_ARM64_SW_TTBR0_PAN=y CONFIG_CORESIGHT_CORESIGHT_TNOC=m CONFIG_CORESIGHT_CTCU=m CONFIG_CORESIGHT_DUMMY=m CONFIG_CORESIGHT_SOURCE_ETM4X=m CONFIG_CORESIGHT_TGU=m CONFIG_CORESIGHT_TPDM=m +CONFIG_CPU_IDLE_THERMAL=y +# CONFIG_DEBUG_INFO_REDUCED is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_CMA=y CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_IDLE_INJECT=y +CONFIG_KPROBES=y +CONFIG_POWERCAP=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TRACE_MMIO_ACCESS=y +CONFIG_UCLAMP_TASK_GROUP=y +CONFIG_UCLAMP_TASK=y +# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_ZRAM=y From 7e865e8c1d25e7f7b2e4b2a6280aa692008d35c2 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 6 Oct 2025 17:11:01 +0530 Subject: [PATCH 0116/1330] QCLINUX: debug: Enable additional Qualcomm-specific debug configs Enabled various debug-related kernel config options to improve system diagnostics and aid in development and issue analysis. Signed-off-by: Komal Bajaj --- kernel/configs/debug.config | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/kernel/configs/debug.config b/kernel/configs/debug.config index 307c97ac5fa9c..2df1c1bd8106f 100644 --- a/kernel/configs/debug.config +++ b/kernel/configs/debug.config @@ -116,3 +116,12 @@ CONFIG_FUNCTION_TRACER=y # CONFIG_DEBUG_PREEMPT=y CONFIG_PREEMPT=y + +# +# Qualcomm Debug Configs +# +CONFIG_CMA_DEBUG=y +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_PAGEALLOC=y +# CONFIG_FW_LOADER_DEBUG is not set +CONFIG_HARDLOCKUP_DETECTOR=y From 65c3f2637761fe5cb489b222d010ea5464518435 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 31 Oct 2025 15:58:40 +0800 Subject: [PATCH 0117/1330] QCLINUX: arch: arm64: configs: Enable stm components in qcom.config Add STM configs to enable STM functions, like stm ftrace and stm heartbeat. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom.config | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 9cd2b50f8b367..00e740e4e29de 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -20,6 +20,11 @@ CONFIG_KPROBES=y CONFIG_POWERCAP=y CONFIG_SCHED_DEBUG=y CONFIG_SCHEDSTATS=y +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +CONFIG_STM_SOURCE_CONSOLE=m +CONFIG_STM_SOURCE_FTRACE=m +CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y From 1ce58d1579900a7b53852417e318f71da33a25c6 Mon Sep 17 00:00:00 2001 From: Wenjia Zhang Date: Tue, 4 Nov 2025 17:35:07 +0800 Subject: [PATCH 0118/1330] QCLINUX: defconfig: enable Crypto and ICE related configs Enabled key config of Crypto (CONFIG_CRYPTO_USER_API, CONFIG_CRYPTO_USER_API_HASH, CONFIG_CRYPTO_USER_API_SKCIPHER, CONFIG_CRYPTO_USER_API_AEAD). And else for support ICE config. Signed-off-by: Wenjia Zhang --- arch/arm64/configs/qcom.config | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 00e740e4e29de..68f9420987e84 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -35,3 +35,20 @@ CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_ZRAM=y + +# Add config to support Crypto and ICE +CONFIG_SCSI_UFS_QCOM=y +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT_FALLBACK=y +CONFIG_FS_ENCRYPTION_HW_WRAPPED_KEYS=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_QCOM_INLINE_CRYPTO_ENGINE=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y +CONFIG_BLK_INLINE_ENCRYPTION_HW_WRAPPED_KEYS=y + From 87ec7661b174038f2f61c82ebceec217fb24f16f Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Wed, 5 Nov 2025 14:26:27 +0530 Subject: [PATCH 0119/1330] QCLINUX: defconfig: enable amc6821 defconfig on qcom.config Enable SENSOR_AMC6821 defconfig to enable fan controller support. Signed-off-by: Gaurav Kohli --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 68f9420987e84..ad4bb73a69202 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -25,6 +25,7 @@ CONFIG_STM_PROTO_SYS_T=m CONFIG_STM_SOURCE_CONSOLE=m CONFIG_STM_SOURCE_FTRACE=m CONFIG_STM_SOURCE_HEARTBEAT=m +CONFIG_SENSORS_AMC6821=y CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y From 7805e6da039e05492aa9bb02e44123e60abc8f5b Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Thu, 13 Nov 2025 14:59:19 +0530 Subject: [PATCH 0120/1330] QCLINUX: defconfig: Enable QCA808X ethernet phy config Enable the config for the QCA808X ethernet PHY driver. Ethernet is non functional without this driver on Lemans and Monaco EVK. Signed-off-by: Mohd Ayaan Anwar --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index ad4bb73a69202..24fba94365ed2 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -18,6 +18,7 @@ CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_IDLE_INJECT=y CONFIG_KPROBES=y CONFIG_POWERCAP=y +CONFIG_QCA808X_PHY=m CONFIG_SCHED_DEBUG=y CONFIG_SCHEDSTATS=y CONFIG_STM_PROTO_BASIC=m From 4f2050d390b1cc5a436a95920718d8ad3c833d08 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 14 Nov 2025 19:08:45 +0530 Subject: [PATCH 0121/1330] QCLINUX: defconfig: Enable EDAC_QCOM on qcom.config Enable QCOM EDAC driver support for QCOM SoCs. Signed-off-by: Komal Bajaj --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 24fba94365ed2..5358c519a2102 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -15,6 +15,7 @@ CONFIG_CPU_IDLE_THERMAL=y CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_CMA=y CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_EDAC_QCOM=m CONFIG_IDLE_INJECT=y CONFIG_KPROBES=y CONFIG_POWERCAP=y From b9ef52a3b9c06ce9d7afbc3adcdf99fe0588ca61 Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Wed, 12 Nov 2025 11:29:07 +0800 Subject: [PATCH 0122/1330] QCLINUX: debug: Enable WLAN related debug configs Enable WLAN related debug configs. Signed-off-by: Yingying Tang --- kernel/configs/debug.config | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/kernel/configs/debug.config b/kernel/configs/debug.config index 2df1c1bd8106f..2b19e5e651cb9 100644 --- a/kernel/configs/debug.config +++ b/kernel/configs/debug.config @@ -120,8 +120,31 @@ CONFIG_PREEMPT=y # # Qualcomm Debug Configs # +CONFIG_ATH11K_COREDUMP=y +CONFIG_ATH11K_DEBUG=y +CONFIG_ATH11K_DEBUGFS=y +CONFIG_ATH11K_TRACING=y +CONFIG_ATH12K_DEBUG=y +CONFIG_ATH12K_DEBUGFS=y +CONFIG_ATH12K_TRACING=y +CONFIG_ATH12K_COREDUMP=y +CONFIG_CFG80211_DEBUGFS=y CONFIG_CMA_DEBUG=y CONFIG_DEBUG_LIST=y CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_FUNCTION_GRAPH_TRACER=y # CONFIG_FW_LOADER_DEBUG is not set CONFIG_HARDLOCKUP_DETECTOR=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_KPROBE_EVENTS=y +CONFIG_MAC80211_DEBUGFS=y +CONFIG_NL80211_TESTMODE=y +CONFIG_PREEMPT_TRACER=y +CONFIG_PREEMPTIRQ_TRACEPOINTS=y +CONFIG_SCHED_TRACER=y +CONFIG_STACK_TRACER=y +CONFIG_TRACEPOINTS=y +CONFIG_TRACING=y +CONFIG_UPROBE_EVENTS=y From b9334230dbd14e3ef5f0bca59ab3f2c7377aae72 Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Wed, 12 Nov 2025 12:01:17 +0800 Subject: [PATCH 0123/1330] QCLINUX: defconfig: Enable ATH reg setting Enable ATH reg setting, then user can change country code by netlink command. Signed-off-by: Yingying Tang --- arch/arm64/configs/qcom.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 5358c519a2102..f024f6b9a39dd 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -4,6 +4,8 @@ # # Keep alphabetically sorted CONFIG_ARM64_SW_TTBR0_PAN=y +CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y +CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CORESIGHT_CORESIGHT_TNOC=m CONFIG_CORESIGHT_CTCU=m CONFIG_CORESIGHT_DUMMY=m @@ -16,6 +18,7 @@ CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_CMA=y CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_EDAC_QCOM=m +CONFIG_EXPERT=y CONFIG_IDLE_INJECT=y CONFIG_KPROBES=y CONFIG_POWERCAP=y From 06c9d012b3946cf8c5fc261214b454df21d9890d Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Wed, 19 Nov 2025 19:55:44 +0530 Subject: [PATCH 0124/1330] QCLINUX: defconfig: Enable BT_RFCOMM, BT_BNEP and UHID Enable as modules the BT_BNEP and BT_RFCOMM drivers which are required for Bluetooth profiles such as PAN and SPP. Without these modules, PAN and SPP functionality will not be available. Enable UHID support to allow HID over GATT operations. Without this, user-space cannot create virtual HID devices, which impacts HID profile usage over Bluetooth. Signed-off-by: Wei Deng --- arch/arm64/configs/qcom.config | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index f024f6b9a39dd..3fb7c7776c892 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -5,6 +5,11 @@ # Keep alphabetically sorted CONFIG_ARM64_SW_TTBR0_PAN=y CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CORESIGHT_CORESIGHT_TNOC=m CONFIG_CORESIGHT_CTCU=m @@ -34,6 +39,7 @@ CONFIG_SENSORS_AMC6821=y CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y +CONFIG_UHID=m # CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y From 4a9f87f1e6cbd9827ee9e42667cbb2f0013959e9 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 21 Nov 2025 10:01:00 +0530 Subject: [PATCH 0125/1330] QCLINUX: defconfig: Enable various power management configs Enable various PM configs to enable suspend-resume. Signed-off-by: Maulik Shah --- arch/arm64/configs/qcom.config | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 3fb7c7776c892..8311dc4f933e9 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -26,6 +26,13 @@ CONFIG_EDAC_QCOM=m CONFIG_EXPERT=y CONFIG_IDLE_INJECT=y CONFIG_KPROBES=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM=y CONFIG_POWERCAP=y CONFIG_QCA808X_PHY=m CONFIG_SCHED_DEBUG=y From 3fb9db8bb95da522d03e1efa6104d6fc89126087 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 21 Nov 2025 13:32:46 +0530 Subject: [PATCH 0126/1330] QCLINUX: debug: Enable power management debug configs Enabled various power management debug related kernel config options to improve system diagnostics and aid in development and issue analysis. Signed-off-by: Maulik Shah --- kernel/configs/debug.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/configs/debug.config b/kernel/configs/debug.config index 2b19e5e651cb9..8579fc7f0d69a 100644 --- a/kernel/configs/debug.config +++ b/kernel/configs/debug.config @@ -143,6 +143,9 @@ CONFIG_MAC80211_DEBUGFS=y CONFIG_NL80211_TESTMODE=y CONFIG_PREEMPT_TRACER=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_PM_DEBUG=y +CONFIG_PM_SLEEP_DEBUG=y CONFIG_SCHED_TRACER=y CONFIG_STACK_TRACER=y CONFIG_TRACEPOINTS=y From 0ee094d953e83a6b137ed67b1148aa86aa97185e Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Thu, 20 Nov 2025 16:28:06 +0530 Subject: [PATCH 0127/1330] FROMLIST: defconfig: qcom: Enable lt8713sx bridge driver Lontium LT8713sx DP bridge hub can be found in monaco-evk for converting 1 DP to 3 DP output. Co-developed-by: Prahlad Valluru Signed-off-by: Prahlad Valluru Signed-off-by: Vishnu Saini Link: https://lore.kernel.org/all/20251120-lt8713sx-bridge-linux-for-next-v1-2-2246fc5fb490@qti.qualcomm.com/ --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b67d5b1fc45b0..0a11c9aa45007 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1001,6 +1001,7 @@ CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_FSL_LDB=m CONFIG_DRM_ITE_IT6263=m +CONFIG_DRM_LONTIUM_LT8713SX=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m From f154cf2ee514b6bcad733ed65c85cd4f2cf90049 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 27 Nov 2025 15:03:55 +0530 Subject: [PATCH 0128/1330] QCLINUX: Revert "QCLINUX: defconfig: enable Crypto and ICE related configs" Revert commit 68f6c9a13767b281d3859caf834fbdd3c027ee22. Enabling ICE-related configurations causes crashes on the lemans-evk device, so this change is being reverted until the issue is resolved. Signed-off-by: Komal Bajaj --- arch/arm64/configs/qcom.config | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 8311dc4f933e9..4133da26d73aa 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -54,20 +54,3 @@ CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_ZRAM=y - -# Add config to support Crypto and ICE -CONFIG_SCSI_UFS_QCOM=y -CONFIG_CRYPTO_USER_API=y -CONFIG_CRYPTO_USER_API_HASH=y -CONFIG_CRYPTO_USER_API_SKCIPHER=y -CONFIG_CRYPTO_USER_API_AEAD=y -CONFIG_BLK_INLINE_ENCRYPTION=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y -CONFIG_FS_ENCRYPTION_INLINE_CRYPT_FALLBACK=y -CONFIG_FS_ENCRYPTION_HW_WRAPPED_KEYS=y -CONFIG_SCSI_UFS_CRYPTO=y -CONFIG_QCOM_INLINE_CRYPTO_ENGINE=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y -CONFIG_BLK_INLINE_ENCRYPTION_HW_WRAPPED_KEYS=y - From c6ddb3131e8a7bb54b1b4f5263be2137f9b9f0dc Mon Sep 17 00:00:00 2001 From: Nikhil V Date: Thu, 27 Nov 2025 15:15:16 +0530 Subject: [PATCH 0129/1330] QCLINUX: defconfig: Enable watchdog drivers for VM usecases CrosVM supports vCPU Stall watchdog. QEMU supports I6300 ESB watchdog. Enable corresponding drivers for Guest VM usecases. Signed-off-by: Nikhil V --- arch/arm64/configs/qcom.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 4133da26d73aa..5fa9e6af25edb 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -24,6 +24,7 @@ CONFIG_DMABUF_HEAPS_CMA=y CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_EDAC_QCOM=m CONFIG_EXPERT=y +CONFIG_I6300ESB_WDT=y CONFIG_IDLE_INJECT=y CONFIG_KPROBES=y CONFIG_PM_SLEEP=y @@ -47,6 +48,7 @@ CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y CONFIG_UHID=m +CONFIG_VCPU_STALL_DETECTOR=y # CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y From a79d37fec1f700fc6c3c681d74c3edc6f58aaabe Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 28 Nov 2025 12:38:09 +0530 Subject: [PATCH 0130/1330] QCLINUX: debug.config: Drop heavy debug configs Removed UBSAN, KASAN, kmemleak, lock proving, and function tracing from debug.config to reduce bootup time and prevent probe deferring issues. Signed-off-by: Komal Bajaj --- kernel/configs/debug.config | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/kernel/configs/debug.config b/kernel/configs/debug.config index 8579fc7f0d69a..6a9237a66deb7 100644 --- a/kernel/configs/debug.config +++ b/kernel/configs/debug.config @@ -32,12 +32,12 @@ CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y CONFIG_DEBUG_IRQFLAGS=y -CONFIG_UBSAN=y -CONFIG_UBSAN_BOOL=y -CONFIG_UBSAN_BOUNDS=y -CONFIG_UBSAN_ENUM=y -CONFIG_UBSAN_SHIFT=y -CONFIG_UBSAN_UNREACHABLE=y +# CONFIG_UBSAN is not set +# CONFIG_UBSAN_BOOL is not set +# CONFIG_UBSAN_BOUNDS is not set +# CONFIG_UBSAN_ENUM is not set +# CONFIG_UBSAN_SHIFT is not set +# CONFIG_UBSAN_UNREACHABLE is not set # # Networking Debugging # @@ -56,8 +56,8 @@ CONFIG_DEBUG_NET=y # CONFIG_SLUB_STATS is not set CONFIG_PAGE_EXTENSION=y CONFIG_PAGE_OWNER=y -CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN is not set CONFIG_DEBUG_OBJECTS=y CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 CONFIG_DEBUG_OBJECTS_FREE=y @@ -72,10 +72,10 @@ CONFIG_DEBUG_VM=y CONFIG_DEBUG_VM_PGFLAGS=y CONFIG_DEBUG_VM_RB=y CONFIG_DEBUG_VM_VMACACHE=y -CONFIG_KASAN=y -CONFIG_KASAN_GENERIC=y -CONFIG_KASAN_INLINE=y -CONFIG_KASAN_VMALLOC=y +# CONFIG_KASAN is not set +# CONFIG_KASAN_GENERIC is not set +# CONFIG_KASAN_INLINE is not set +# CONFIG_KASAN_VMALLOC is not set CONFIG_PTDUMP_DEBUGFS=y CONFIG_SCHED_STACK_END_CHECK=y CONFIG_SLUB_DEBUG_ON=y @@ -93,7 +93,7 @@ CONFIG_SOFTLOCKUP_DETECTOR=y # Lock Debugging (spinlocks, mutexes, etc...) # # CONFIG_PROVE_RAW_LOCK_NESTING is not set -CONFIG_PROVE_LOCKING=y +# CONFIG_PROVE_LOCKING is not set # # Debug kernel data structures # @@ -101,16 +101,16 @@ CONFIG_BUG_ON_DATA_CORRUPTION=y # # RCU Debugging # -CONFIG_RCU_EXPERT=y -CONFIG_PROVE_RCU=y -CONFIG_PROVE_RCU_LIST=y +# CONFIG_RCU_EXPERT is not set +# CONFIG_PROVE_RCU is not set +# CONFIG_PROVE_RCU_LIST is not set # # Tracers # CONFIG_BRANCH_PROFILE_NONE=y CONFIG_DYNAMIC_FTRACE=y CONFIG_FTRACE=y -CONFIG_FUNCTION_TRACER=y +# CONFIG_FUNCTION_TRACER is not set # # Preemption # From 97f05b775be911e059c52892110331195f538ec4 Mon Sep 17 00:00:00 2001 From: Jiaxing Li Date: Tue, 18 Nov 2025 00:16:10 +0800 Subject: [PATCH 0131/1330] QCLINUX: defconfig: Enable Trusted Execution Environment (TEE) driver for Qualcomm TEE (QTEE) We are planning to replace QPTEE with QCOMTEE on all QCOM-released kernel versions. QTEE allows Trusted Applications (TAs) and services to run securely and offers the same functionality as OPTEE. Signed-off-by: Jiaxing Li Link: https://github.com/qualcomm-linux/kernel-topics/pull/121 --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0a11c9aa45007..308e37cc178fb 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1835,6 +1835,7 @@ CONFIG_FPGA_MGR_ZYNQMP_FPGA=m CONFIG_FPGA_MGR_VERSAL_FPGA=m CONFIG_TEE=y CONFIG_OPTEE=y +CONFIG_QCOMTEE=y CONFIG_MUX_GPIO=m CONFIG_MUX_MMIO=y CONFIG_SLIMBUS=m From 7feec7b8b3790f56dd335fed8aed23c2c086ed65 Mon Sep 17 00:00:00 2001 From: Nikhil V Date: Thu, 20 Nov 2025 15:11:23 +0530 Subject: [PATCH 0132/1330] QCLINUX: defconfig: Enable support for vhost-net, vsock Added the required configs to enable host kernel accelerator for virtio net(vhost-net) and virtual socket protocol(vsock). Signed-off-by: Nikhil V --- arch/arm64/configs/qcom.config | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 5fa9e6af25edb..ecfe6f69a3880 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -27,6 +27,8 @@ CONFIG_EXPERT=y CONFIG_I6300ESB_WDT=y CONFIG_IDLE_INJECT=y CONFIG_KPROBES=y +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y CONFIG_PM_AUTOSLEEP=y @@ -49,6 +51,11 @@ CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y CONFIG_UHID=m CONFIG_VCPU_STALL_DETECTOR=y +CONFIG_VHOST_NET=y +CONFIG_VHOST_VSOCK=y +CONFIG_VSOCKETS=y +# CONFIG_VSOCKETS_DIAG is not set +# CONFIG_VSOCKETS_LOOPBACK is not set # CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y From 2092700eb4eb650807aea44cc38e9df3edfe6ef1 Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Wed, 3 Dec 2025 10:12:17 +0530 Subject: [PATCH 0133/1330] FROMLIST: arm64: defconfig: Enable Sound DMIC driver Enable CONFIG_SND_SOC_DMIC as a module in the arm64 defconfig to support digital microphone functionality on Qualcomm's Monaco and Lemans platforms. Link: https://lore.kernel.org/all/20251218084604.2054971-1-ravi.hothi@oss.qualcomm.com/ Signed-off-by: Ravi Hothi --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 308e37cc178fb..16eeabf360bc1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1140,6 +1140,7 @@ CONFIG_SND_SOC_XILINX_SPDIF=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_AK4619=m CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_ES8316=m From 7c92a6b2d411b667c5d9f8613271412d327ea281 Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Thu, 4 Dec 2025 18:20:29 +0530 Subject: [PATCH 0134/1330] QCLINUX: arm64: configs: qcom.config: Enable GUNYAH_WATCHDOG Enable Gunyah watchdog driver for rb3gen2. Signed-off-by: Shivendra Pratap --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index ecfe6f69a3880..d2fe51d328e50 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -24,6 +24,7 @@ CONFIG_DMABUF_HEAPS_CMA=y CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_EDAC_QCOM=m CONFIG_EXPERT=y +CONFIG_GUNYAH_WATCHDOG=y CONFIG_I6300ESB_WDT=y CONFIG_IDLE_INJECT=y CONFIG_KPROBES=y From 86a42b45df85b8df736892528d70374e70653274 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 5 Feb 2026 17:50:42 +0530 Subject: [PATCH 0135/1330] FROMLIST: arm64: defconfig: Enable Glymur configs for boot to shell The serial engine must be properly setup before kernel reaches "init", so UART driver and its dependencies needs to be built in. Enable its dependency clocks,interconnect and pinctrl as built-in to boot Qualcomm's dev platform - Glymur CRD board to UART console with rootfs on nvme storage. DISPCC enabled as module, used for display. Link: https://lore.kernel.org/r/20260205-upstream_v3_glymur_introduction-v7-2-849e7a9e6888@oss.qualcomm.com Reviewed-by: Krzysztof Kozlowski Signed-off-by: Pankaj Patil Reviewed-by: Dmitry Baryshkov --- arch/arm64/configs/defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 16eeabf360bc1..73a98df9748cf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -647,6 +647,7 @@ CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_IMX_SCMI=y CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_GLYMUR=y CONFIG_PINCTRL_IPQ5018=y CONFIG_PINCTRL_IPQ5332=y CONFIG_PINCTRL_IPQ5424=y @@ -1456,6 +1457,9 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y CONFIG_COMMON_CLK_MT8192_VDECSYS=y CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_CLK_GLYMUR_DISPCC=m +CONFIG_CLK_GLYMUR_GCC=y +CONFIG_CLK_GLYMUR_TCSRCC=m CONFIG_CLK_KAANAPALI_GCC=y CONFIG_CLK_KAANAPALI_TCSRCC=m CONFIG_CLK_X1E80100_CAMCC=m @@ -1849,6 +1853,7 @@ CONFIG_INTERCONNECT_IMX8MN=m CONFIG_INTERCONNECT_IMX8MQ=m CONFIG_INTERCONNECT_IMX8MP=y CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_GLYMUR=y CONFIG_INTERCONNECT_QCOM_KAANAPALI=y CONFIG_INTERCONNECT_QCOM_MSM8916=m CONFIG_INTERCONNECT_QCOM_MSM8953=y From 0d27bdf4bca59b0c1ef6538411565e25d6332fe8 Mon Sep 17 00:00:00 2001 From: Raghavender Reddy Bujala Date: Wed, 10 Dec 2025 16:16:53 +0530 Subject: [PATCH 0136/1330] QCLINUX: arm64: configs: qcom.config: Enable UINPUT Enable UINPUT, which is required for BT AVRC profile to register the events and All passthrough commands of AVRCP will be listed in this event under /dev/input/ Signed-off-by: Raghavender Reddy Bujala --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index d2fe51d328e50..7dc21568d5cf5 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -27,6 +27,7 @@ CONFIG_EXPERT=y CONFIG_GUNYAH_WATCHDOG=y CONFIG_I6300ESB_WDT=y CONFIG_IDLE_INJECT=y +CONFIG_INPUT_UINPUT=y CONFIG_KPROBES=y CONFIG_MACVLAN=y CONFIG_MACVTAP=y From 5fdc292ad6da014f80d218b3c7ecaed122d2f352 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Mon, 15 Dec 2025 12:37:54 +0530 Subject: [PATCH 0137/1330] QCLINUX: defconfig: enable EMC2305 defconfig on qcom.config Enable SENSOR_EMC2305 defconfig to enable fan controller support. Signed-off-by: Gaurav Kohli --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 7dc21568d5cf5..4fff1e0a0aabb 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -48,6 +48,7 @@ CONFIG_STM_SOURCE_CONSOLE=m CONFIG_STM_SOURCE_FTRACE=m CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_SENSORS_AMC6821=y +CONFIG_SENSORS_EMC2305=y CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y From 3248e3c07305057b9db5a0ec65c18e27b4e50aeb Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Wed, 17 Dec 2025 18:42:40 +0530 Subject: [PATCH 0138/1330] QCLINUX: arm64: configs: Added new rt.config for RT kernel Enabled PREEMPT_RT in new rt.config to enable RT kernel features. Signed-off-by: Anurag Pateriya --- arch/arm64/configs/rt.config | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 arch/arm64/configs/rt.config diff --git a/arch/arm64/configs/rt.config b/arch/arm64/configs/rt.config new file mode 100644 index 0000000000000..ca92615d38a17 --- /dev/null +++ b/arch/arm64/configs/rt.config @@ -0,0 +1,3 @@ +# rt.config for Real time kernel features +CONFIG_EXPERT=y +CONFIG_PREEMPT_RT=y From dcc00e7e0dfcb4d6df5b80c746137b263f8d7ba5 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Thu, 11 Dec 2025 16:41:21 +0530 Subject: [PATCH 0139/1330] QCLINUX: arm64: configs: qcom.config: Enable I2C_QCOM_GENI as built-in On Lemans and Monaco EVK platforms the boot-from-SD-card feature requires an IO expander to be enabled at an early stage to detect the SD card. This IO expander is connected over I2C. Currently the I2C driver is built as a loadable module which resides on the SD card along with other modules. This creates a circular dependency where to detect the SD card the IO expander must be initialized the IO expander depends on the I2C driver and the I2C driver is on the SD card which cannot be accessed until detection succeeds. To break this dependency enable I2C_QCOM_GENI as built-in so that the driver is available during early boot. Signed-off-by: Viken Dadhaniya --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 4fff1e0a0aabb..0707e99b09ace 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -25,6 +25,7 @@ CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_EDAC_QCOM=m CONFIG_EXPERT=y CONFIG_GUNYAH_WATCHDOG=y +CONFIG_I2C_QCOM_GENI=y CONFIG_I6300ESB_WDT=y CONFIG_IDLE_INJECT=y CONFIG_INPUT_UINPUT=y From 75742b8007b1f616a649b9e798e7abab2fbf2f92 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Thu, 18 Dec 2025 15:10:56 +0530 Subject: [PATCH 0140/1330] QCLINUX: arm64: configs: Added Kubernetes support in qcom.config Adding config options for Kubernetes support in qcom.config Signed-off-by: Anurag Pateriya --- arch/arm64/configs/qcom.config | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 0707e99b09ace..4cb8bc80ee0df 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -67,3 +67,13 @@ CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_ZRAM=y + +# Kubernetes support +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_FAVOR_DYNMODS=y +CONFIG_IPC_NS=y +CONFIG_NAMESPACES=y +CONFIG_NET_NS=y +CONFIG_PID_NS=y +CONFIG_UTS_NS=y + From d1bc253f5b11105b2d786ffa361f2edb5d872d2e Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 23 Dec 2025 17:07:14 +0530 Subject: [PATCH 0141/1330] QCLINUX: qcom.comfig: disable ICE/UFS crypto RB3GEN2 on v6.19-rc2 crashes in qcom_ice_probe() and fails to boot. Disable inline crypto (ICE) and UFS crypto as a temporary workaround. Disabled: - CONFIG_QCOM_INLINE_CRYPTO_ENGINE - CONFIG_SCSI_UFS_CRYPTO Will be reverted once ICE probe is fixed. Signed-off-by: Komal Bajaj --- arch/arm64/configs/qcom.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 4cb8bc80ee0df..e3c45f29461f2 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -77,3 +77,6 @@ CONFIG_NET_NS=y CONFIG_PID_NS=y CONFIG_UTS_NS=y +# Disable ICE/UFS crypto +# CONFIG_QCOM_INLINE_CRYPTO_ENGINE is not set +# CONFIG_SCSI_UFS_CRYPTO is not set From 0dfdd207708ce6415679d1b2257bd3a45811317b Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Wed, 24 Dec 2025 18:34:18 +0530 Subject: [PATCH 0142/1330] QCLINUX: defconfig: enable Remoteproc cooling feature Enable Remoteproc cooling feature config. Signed-off-by: Gaurav Kohli --- arch/arm64/configs/qcom.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index e3c45f29461f2..4be5a6115b4ef 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -41,6 +41,8 @@ CONFIG_PM_WAKELOCKS_LIMIT=0 CONFIG_PM=y CONFIG_POWERCAP=y CONFIG_QCA808X_PHY=m +CONFIG_QCOM_QMI_COOLING=y +CONFIG_REMOTEPROC_THERMAL=y CONFIG_SCHED_DEBUG=y CONFIG_SCHEDSTATS=y CONFIG_STM_PROTO_BASIC=m From 21889051eeefcc412a30658946095244cc6aa9d9 Mon Sep 17 00:00:00 2001 From: Jagadeesh Pagadala Date: Thu, 8 Jan 2026 14:14:29 +0530 Subject: [PATCH 0143/1330] QCLINUX: arm64: configs: qcom.config: Enable CONNECTOR, PROC_EVENTS Enable CONFIG_CONNECTOR and CONFIG_PROC_EVENTS to allow userspace to receive process lifecycle events (fork/exec/exit) via the proc connector over netlink. Signed-off-by: Jagadeesh Pagadala --- arch/arm64/configs/qcom.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 4be5a6115b4ef..b87760e3d1d86 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -11,6 +11,7 @@ CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_CFG80211_CERTIFICATION_ONUS=y +CONFIG_CONNECTOR=y CONFIG_CORESIGHT_CORESIGHT_TNOC=m CONFIG_CORESIGHT_CTCU=m CONFIG_CORESIGHT_DUMMY=m @@ -40,6 +41,7 @@ CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set CONFIG_PM=y CONFIG_POWERCAP=y +CONFIG_PROC_EVENTS=y CONFIG_QCA808X_PHY=m CONFIG_QCOM_QMI_COOLING=y CONFIG_REMOTEPROC_THERMAL=y From 52043fda40220f82722e17cf8187cb0ca500371c Mon Sep 17 00:00:00 2001 From: Wenjia Zhang Date: Mon, 5 Jan 2026 15:59:47 +0800 Subject: [PATCH 0144/1330] QCLINUX: qcom.config: add crypto corresponding config Enable crypto api for user test. The configs are for testapp that's why the kernel upstream team would suggest having this enabled for clients who needs it and not by default since in qcom we need this, we should be enabling ideally in qcom-next. Signed-off-by: Wenjia Zhang --- arch/arm64/configs/qcom.config | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index b87760e3d1d86..896ceb9454054 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -84,3 +84,9 @@ CONFIG_UTS_NS=y # Disable ICE/UFS crypto # CONFIG_QCOM_INLINE_CRYPTO_ENGINE is not set # CONFIG_SCSI_UFS_CRYPTO is not set + +# Support Crypto api +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER_API_AEAD=y From cc630eb6ec3bf1c755ecddcd3338f299cdc4990a Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 13 Jan 2026 22:54:34 +0530 Subject: [PATCH 0145/1330] FROMLIST: arm64: defconfig: Enable camcc, videocc clock controllers on SM8750 Enable the SM8750 video, camera clock controller for their respective functionalities on the Qualcomm SM8750 MTP platform. Link: https://lore.kernel.org/all/20260113-enable_mmcc_defconfig-v1-1-4b709daadd1f@oss.qualcomm.com/ Signed-off-by: Taniya Das --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 73a98df9748cf..25953dbd11cf1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1531,6 +1531,7 @@ CONFIG_SM_CAMCC_MILOS=m CONFIG_SM_CAMCC_8250=m CONFIG_SM_CAMCC_8550=m CONFIG_SM_CAMCC_8650=m +CONFIG_SM_CAMCC_8750=m CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_8250=y CONFIG_SM_DISPCC_6350=m @@ -1564,6 +1565,7 @@ CONFIG_SM_VIDEOCC_6350=m CONFIG_SM_VIDEOCC_MILOS=m CONFIG_SM_VIDEOCC_8250=y CONFIG_SM_VIDEOCC_8550=m +CONFIG_SM_VIDEOCC_8750=m CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_SM_VIDEOCC_8450=m From 81d2f9abdb40970bb93882954b8b6390a3df6215 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 19 Jan 2026 15:47:00 +0800 Subject: [PATCH 0146/1330] QCLINUX: prune.config: Enable backlight config for Hamoa/Purwa Hamoa/Purwa currently requires the backlight node from the eDP device, but this macro was overridden by CONFIG_DRM_NOUVEAU. Remove it from prune.config to properly enable the BACKLIGHT_* related config. Signed-off-by: Yongxing Mou --- arch/arm64/configs/prune.config | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/prune.config b/arch/arm64/configs/prune.config index 54cf8fa1cd0e0..fba07d6ebe12d 100644 --- a/arch/arm64/configs/prune.config +++ b/arch/arm64/configs/prune.config @@ -188,7 +188,6 @@ # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_MALI_DISPLAY is not set # CONFIG_DRM_KOMEDA is not set -# CONFIG_DRM_NOUVEAU is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set From 0ce48d2da9a4103b6fb1c67269709c16b7909edf Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Fri, 23 Jan 2026 13:32:49 +0530 Subject: [PATCH 0147/1330] QCLINUX: qcom.config: Enable 39-bit VA space for 4K-page builds For Qualcomm 4K-page based builds, explicitly enable VA_BITS_39 in the qcom.config fragment. Lower-end arm64 systems typically do not benefit from a 48/52-bit VA space, while they do benefit from smaller page tables and reduced TLB pressure. Selecting 39-bit VA sizing aligns better with constraints and performance characteristics of lower-end Qualcomm platforms. This change does not affect 64K-page builds (which retain 48/52-bit VA). Background: - With 4K pages, arm64 supports 39-bit (3-level) or 48-bit (4-level) VAs. - 52-bit VAs are only available with 64K pages and ARMv8.2-LVA, and kernels must be able to fall back to 48-bit at boot. Signed-off-by: Anurag Pateriya --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 896ceb9454054..8190237481eee 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -4,6 +4,7 @@ # # Keep alphabetically sorted CONFIG_ARM64_SW_TTBR0_PAN=y +CONFIG_ARM64_VA_BITS_39=y CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y From 9427ac434f5845eb0298c5265cc6fadf6b6470d6 Mon Sep 17 00:00:00 2001 From: Wenjia Zhang Date: Tue, 27 Jan 2026 15:59:30 +0800 Subject: [PATCH 0148/1330] QCLINUX: qcom.config: enable the ICE related config Below is the reason why config aren't enable in upstream: Not all filesystem support encryption, the default config must be safe for all situation. Upstream kernel keeps optional features off by default. Filesystem encryption must be enabled in per-filesystem. Kernel developmenters added options to dosable fscrypt per-filesystem means it's not intended as default. CRs-Fixed: 4418940 Signed-off-by: Wenjia Zhang --- arch/arm64/configs/qcom.config | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 8190237481eee..1663137c14770 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -82,12 +82,15 @@ CONFIG_NET_NS=y CONFIG_PID_NS=y CONFIG_UTS_NS=y -# Disable ICE/UFS crypto -# CONFIG_QCOM_INLINE_CRYPTO_ENGINE is not set -# CONFIG_SCSI_UFS_CRYPTO is not set - # Support Crypto api CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_AEAD=y + +# Support ICE/UFS crypto driver +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_QCOM_INLINE_CRYPTO_ENGINE=m +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_FS_ENCRYPTION=y From aa03351a86639cdcdbafc72ddc1bb81faa3e10aa Mon Sep 17 00:00:00 2001 From: Gopi Botlagunta Date: Wed, 12 Nov 2025 20:18:12 +0530 Subject: [PATCH 0149/1330] FROMLIST: arm64: configs: Update defconfig for DSI-LVDS bridge support Enable the LT9211 bridge driver to support DSI-to-LVDS conversion on the Qualcomm RB3GEN2 Industrial Kit. Signed-off-by: Gopi Botlagunta Co-developed-by: Yi Zhang Signed-off-by: Yi Zhang Link: https://lore.kernel.org/lkml/20260130-add-lt9211c-bridge-for-rb3gen2-industrial-mezzanine-v2-2-a98714fa1531@oss.qualcomm.com/ --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 25953dbd11cf1..bfc48ce1aaeea 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1004,6 +1004,7 @@ CONFIG_DRM_FSL_LDB=m CONFIG_DRM_ITE_IT6263=m CONFIG_DRM_LONTIUM_LT8713SX=m CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9211=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=m From 01ea5de87b79d050f9b0ea14ffbb2ac66ad03ab6 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 24 Feb 2026 23:19:25 -0800 Subject: [PATCH 0150/1330] FROMLIST: arm64: defconfig: Enable Kaanapali clock controllers Enable the Kaanapali display, video, camera and gpu clock controller for their respective functionalities on the Qualcomm Kaanapali QRD and MTP boards. Link: https://lore.kernel.org/r/20260224-knp-dts-misc-v6-10-79d20dab8a60@oss.qualcomm.com Signed-off-by: Taniya Das Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bfc48ce1aaeea..3cb1a49e8312f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1461,8 +1461,12 @@ CONFIG_COMMON_CLK_QCOM=y CONFIG_CLK_GLYMUR_DISPCC=m CONFIG_CLK_GLYMUR_GCC=y CONFIG_CLK_GLYMUR_TCSRCC=m +CONFIG_CLK_KAANAPALI_CAMCC=m +CONFIG_CLK_KAANAPALI_DISPCC=m CONFIG_CLK_KAANAPALI_GCC=y +CONFIG_CLK_KAANAPALI_GPUCC=m CONFIG_CLK_KAANAPALI_TCSRCC=m +CONFIG_CLK_KAANAPALI_VIDEOCC=m CONFIG_CLK_X1E80100_CAMCC=m CONFIG_CLK_X1E80100_DISPCC=m CONFIG_CLK_X1E80100_GCC=y From 8b166134e8b59ab80e7c288fe8246baa1cbdb1d4 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 29 Jan 2026 15:52:47 +0530 Subject: [PATCH 0151/1330] QCLINUX: qcom.config: Enable FTRACE option for performance profiling Enable kernel tracing option in qcom.config to support performance profiling on Qualcomm arm64 builds. Signed-off-by: Komal Bajaj --- arch/arm64/configs/qcom.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 1663137c14770..bd33d12832ab7 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -94,3 +94,6 @@ CONFIG_QCOM_INLINE_CRYPTO_ENGINE=m CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y CONFIG_SCSI_UFS_CRYPTO=y CONFIG_FS_ENCRYPTION=y + +# Support performance profiling +CONFIG_FTRACE=y From 5d3e3425604a3404a6575e643124069078705246 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 28 Jan 2026 00:56:39 +0530 Subject: [PATCH 0152/1330] FROMLIST: arm64: defconfig: Enable VIDEOCC and CAMCC drivers on Qualcomm X1P42100 Enable video and camera clock controller drivers for their respective functionalities on Qualcomm X1P42100-CRD and similar other platforms with Snapdragon X1P42100 SoC. Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-8-b23de57df5ba@oss.qualcomm.com Signed-off-by: Taniya Das --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3cb1a49e8312f..4d352b1a5a4c5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1472,7 +1472,9 @@ CONFIG_CLK_X1E80100_DISPCC=m CONFIG_CLK_X1E80100_GCC=y CONFIG_CLK_X1E80100_GPUCC=m CONFIG_CLK_X1E80100_TCSRCC=y +CONFIG_CLK_X1P42100_CAMCC=m CONFIG_CLK_X1P42100_GPUCC=m +CONFIG_CLK_X1P42100_VIDEOCC=m CONFIG_CLK_QCM2290_GPUCC=m CONFIG_QCOM_A53PLL=y CONFIG_QCOM_CLK_APCS_MSM8916=y From 828dfc3b8ad2ff21b26de20eeb91e533ef14b2d0 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Wed, 18 Feb 2026 12:00:01 +0530 Subject: [PATCH 0153/1330] Revert "QCLINUX: qcom.config: Enable 39-bit VA space for 4K-page builds" This reverts commit 02fdded1047f4a65082e9ee523dec4af032d99bc. Since bootup issues are observed after enabling 39-bit VA, reverting it untill issues are root caused and fixed. Signed-off-by: Anurag Pateriya --- arch/arm64/configs/qcom.config | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index bd33d12832ab7..c0033a973b164 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -4,7 +4,6 @@ # # Keep alphabetically sorted CONFIG_ARM64_SW_TTBR0_PAN=y -CONFIG_ARM64_VA_BITS_39=y CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y From 7af014f707b060d81a3c5e390bf4e0bae9021bce Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 20 Feb 2026 08:33:37 +0530 Subject: [PATCH 0154/1330] QCLINUX: qcom.config: Enable CPUidle Teo and Menu governors Menu governor gets default enabled if Teo governor is not compiled in. Menu still stays as default governor when both are compiled in due to menu having higher rating than teo. Keeping Teo available helps in evaluating power and performance without spinning builds. Enable both menu and teo governors for CPUidle. Signed-off-by: Maulik Shah --- arch/arm64/configs/qcom.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index c0033a973b164..54195f5b6277a 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -18,6 +18,8 @@ CONFIG_CORESIGHT_DUMMY=m CONFIG_CORESIGHT_SOURCE_ETM4X=m CONFIG_CORESIGHT_TGU=m CONFIG_CORESIGHT_TPDM=m +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y CONFIG_CPU_IDLE_THERMAL=y # CONFIG_DEBUG_INFO_REDUCED is not set CONFIG_DMABUF_HEAPS=y From 2972056e38677d88239a2d765104914b5c8594cf Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sun, 22 Feb 2026 22:17:52 +0530 Subject: [PATCH 0155/1330] FROMLIST: arm64: defconfig: Enable SM8750 clock controllers Enable the SM8750 video, camera and gpu clock controller for their respective functionalities on the Qualcomm SM8750 MTP boards. Link: https://lore.kernel.org/lkml/20260220-sm8750_defconfig_cc-v1-1-666aa922b392@oss.qualcomm.com/ Signed-off-by: Taniya Das --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4d352b1a5a4c5..849572b1a55ac 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1564,6 +1564,7 @@ CONFIG_SM_GPUCC_8350=m CONFIG_SM_GPUCC_8450=m CONFIG_SM_GPUCC_8550=m CONFIG_SM_GPUCC_8650=m +CONFIG_SM_GPUCC_8750=m CONFIG_SM_TCSRCC_8550=y CONFIG_SM_TCSRCC_8650=y CONFIG_SM_TCSRCC_8750=m From 41746b6f6892b97c2604a4266488692f63abd853 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 20 Feb 2026 15:46:58 +0530 Subject: [PATCH 0156/1330] FROMLIST: arm64: defconfig: Enable Glymur clock controllers Enable the Glymur video and gpu clock controller for their respective functionalities on the Qualcomm Glymur CRD boards. Link: https://lore.kernel.org/r/20260220-glymur_mmcc_dt_config-v1-2-e0e2f43a32af@oss.qualcomm.com Signed-off-by: Taniya Das --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 849572b1a55ac..e1e67dd61fb3c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1460,7 +1460,9 @@ CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_QCOM=y CONFIG_CLK_GLYMUR_DISPCC=m CONFIG_CLK_GLYMUR_GCC=y +CONFIG_CLK_GLYMUR_GPUCC=m CONFIG_CLK_GLYMUR_TCSRCC=m +CONFIG_CLK_GLYMUR_VIDEOCC=m CONFIG_CLK_KAANAPALI_CAMCC=m CONFIG_CLK_KAANAPALI_DISPCC=m CONFIG_CLK_KAANAPALI_GCC=y From a28058fda5e5308f160b978800a2cde2e29c5003 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 27 Jan 2026 17:32:06 +0530 Subject: [PATCH 0157/1330] FROMLIST: drm/msm/adreno: Add GPU to MODULE_DEVICE_TABLE Since it is possible to independently probe Adreno GPU, add GPU match table to MODULE_DEVICE_TABLE to allow auto-loading of msm module. Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/lkml/20260124-adreno-module-table-v1-1-9c2dbb2638b4@oss.qualcomm.com/ From 4a89cf573195714eedaf7a5cb0328bd434124b33 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Fri, 17 Oct 2025 11:25:35 +0530 Subject: [PATCH 0158/1330] QCLINUX: arm64: dts: qcom: Add camera DT binding Add the camera DT binding header, which will be utilized by the camera downstream drivers and DTSI files. Signed-off-by: Chandan Kumar Jha --- include/dt-bindings/camera/msm-camera.h | 155 ++++++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 include/dt-bindings/camera/msm-camera.h diff --git a/include/dt-bindings/camera/msm-camera.h b/include/dt-bindings/camera/msm-camera.h new file mode 100644 index 0000000000000..97228c26e7040 --- /dev/null +++ b/include/dt-bindings/camera/msm-camera.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __MSM_CAMERA_H +#define __MSM_CAMERA_H + +/* CPAS path data types */ +#define CAM_CPAS_PATH_DATA_IFE_START_OFFSET 0 +#define CAM_CPAS_PATH_DATA_IFE_LINEAR (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 0) +#define CAM_CPAS_PATH_DATA_IFE_VID (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_IFE_DISP (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 2) +#define CAM_CPAS_PATH_DATA_IFE_STATS (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 3) +#define CAM_CPAS_PATH_DATA_IFE_RDI0 (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 4) +#define CAM_CPAS_PATH_DATA_IFE_RDI1 (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 5) +#define CAM_CPAS_PATH_DATA_IFE_RDI2 (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 6) +#define CAM_CPAS_PATH_DATA_IFE_RDI3 (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 7) +#define CAM_CPAS_PATH_DATA_IFE_PDAF (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 8) +#define CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 9) +#define CAM_CPAS_PATH_DATA_IFE_MAX_OFFSET (CAM_CPAS_PATH_DATA_IFE_START_OFFSET + 31) + +#define CAM_CPAS_PATH_DATA_IPE_START_OFFSET 32 +#define CAM_CPAS_PATH_DATA_IPE_RD_IN (CAM_CPAS_PATH_DATA_IPE_START_OFFSET + 0) +#define CAM_CPAS_PATH_DATA_IPE_RD_REF (CAM_CPAS_PATH_DATA_IPE_START_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_IPE_WR_VID (CAM_CPAS_PATH_DATA_IPE_START_OFFSET + 2) +#define CAM_CPAS_PATH_DATA_IPE_WR_DISP (CAM_CPAS_PATH_DATA_IPE_START_OFFSET + 3) +#define CAM_CPAS_PATH_DATA_IPE_WR_REF (CAM_CPAS_PATH_DATA_IPE_START_OFFSET + 4) +#define CAM_CPAS_PATH_DATA_IPE_WR_APP (CAM_CPAS_PATH_DATA_IPE_START_OFFSET + 5) +#define CAM_CPAS_PATH_DATA_IPE_MAX_OFFSET (CAM_CPAS_PATH_DATA_IPE_START_OFFSET + 31) + +#define CAM_CPAS_PATH_DATA_OPE_START_OFFSET 64 +#define CAM_CPAS_PATH_DATA_OPE_RD_IN (CAM_CPAS_PATH_DATA_OPE_START_OFFSET + 0) +#define CAM_CPAS_PATH_DATA_OPE_RD_REF (CAM_CPAS_PATH_DATA_OPE_START_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_OPE_WR_VID (CAM_CPAS_PATH_DATA_OPE_START_OFFSET + 2) +#define CAM_CPAS_PATH_DATA_OPE_WR_DISP (CAM_CPAS_PATH_DATA_OPE_START_OFFSET + 3) +#define CAM_CPAS_PATH_DATA_OPE_WR_REF (CAM_CPAS_PATH_DATA_OPE_START_OFFSET + 4) +#define CAM_CPAS_PATH_DATA_OPE_MAX_OFFSET (CAM_CPAS_PATH_DATA_OPE_START_OFFSET + 31) + +#define CAM_CPAS_PATH_DATA_SFE_START_OFFSET 96 +#define CAM_CPAS_PATH_DATA_SFE_NRDI (CAM_CPAS_PATH_DATA_SFE_START_OFFSET + 0) +#define CAM_CPAS_PATH_DATA_SFE_RDI0 (CAM_CPAS_PATH_DATA_SFE_START_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_SFE_RDI1 (CAM_CPAS_PATH_DATA_SFE_START_OFFSET + 2) +#define CAM_CPAS_PATH_DATA_SFE_RDI2 (CAM_CPAS_PATH_DATA_SFE_START_OFFSET + 3) +#define CAM_CPAS_PATH_DATA_SFE_RDI3 (CAM_CPAS_PATH_DATA_SFE_START_OFFSET + 4) +#define CAM_CPAS_PATH_DATA_SFE_RDI4 (CAM_CPAS_PATH_DATA_SFE_START_OFFSET + 5) +#define CAM_CPAS_PATH_DATA_SFE_STATS (CAM_CPAS_PATH_DATA_SFE_START_OFFSET + 6) +#define CAM_CPAS_PATH_DATA_SFE_MAX_OFFSET (CAM_CPAS_PATH_DATA_SFE_START_OFFSET + 31) + +#define CAM_CPAS_PATH_DATA_CRE_START_OFFSET (CAM_CPAS_PATH_DATA_SFE_MAX_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_CRE_RD_IN (CAM_CPAS_PATH_DATA_CRE_START_OFFSET + 0) +#define CAM_CPAS_PATH_DATA_CRE_WR_OUT (CAM_CPAS_PATH_DATA_CRE_START_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_CRE_MAX_OFFSET (CAM_CPAS_PATH_DATA_CRE_START_OFFSET + 31) + +#define CAM_CPAS_PATH_DATA_OFE_START_OFFSET (CAM_CPAS_PATH_DATA_CRE_MAX_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_OFE_RD_EXT (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 0) +#define CAM_CPAS_PATH_DATA_OFE_RD_INT_PDI (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_OFE_RD_INT_HDR (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 2) +#define CAM_CPAS_PATH_DATA_OFE_WR_VID (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 3) +#define CAM_CPAS_PATH_DATA_OFE_WR_DISP (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 4) +#define CAM_CPAS_PATH_DATA_OFE_WR_IR (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 5) +#define CAM_CPAS_PATH_DATA_OFE_WR_HDR_LTM (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 6) +#define CAM_CPAS_PATH_DATA_OFE_WR_DC4 (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 7) +#define CAM_CPAS_PATH_DATA_OFE_WR_AI (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 8) +#define CAM_CPAS_PATH_DATA_OFE_WR_PDI (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 9) +#define CAM_CPAS_PATH_DATA_OFE_WR_IDEALRAW (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 10) +#define CAM_CPAS_PATH_DATA_OFE_WR_STATS (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 11) +#define CAM_CPAS_PATH_DATA_OFE_MAX_OFFSET (CAM_CPAS_PATH_DATA_OFE_START_OFFSET + 31) + +#define CAM_CPAS_PATH_DATA_CONSO_OFFSET 256 +#define CAM_CPAS_PATH_DATA_ALL (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 0) + +/* IFE consolidated paths */ +#define CAM_CPAS_PATH_DATA_IFE_LINEAR_PDAF (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 1) +#define CAM_CPAS_PATH_DATA_IFE_UBWC_STATS (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 2) +#define CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 3) +#define CAM_CPAS_PATH_DATA_IFE_RDI_PIXEL_RAW (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 4) +#define CAM_CPAS_PATH_DATA_IFE_RDI_ALL (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 5) +#define CAM_CPAS_PATH_DATA_IFE_UBWC (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 6) +#define CAM_CPAS_PATH_DATA_IFE_LINEAR_STATS (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 7) +#define CAM_CPAS_PATH_DATA_IFE_UBWC_LINEAR (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 8) +#define CAM_CPAS_PATH_DATA_IFE_PDAF_LINEAR (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 9) + +/* IPE Consolidated paths */ +#define CAM_CPAS_PATH_DATA_IPE_WR_VID_DISP (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 1) + +/* CPAS transaction types */ +#define CAM_CPAS_TRANSACTION_READ 0 +#define CAM_CPAS_TRANSACTION_WRITE 1 + +/* CPAS traffic merge types */ +#define CAM_CPAS_TRAFFIC_MERGE_SUM 0 +#define CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE 1 + +/* Feature bit type */ +#define CAM_CPAS_FEATURE_TYPE_DISABLE 0 +#define CAM_CPAS_FEATURE_TYPE_ENABLE 1 +#define CAM_CPAS_FEATURE_TYPE_VALUE 2 + +/* Feature support bit positions in feature fuse register*/ +#define CAM_CPAS_QCFA_BINNING_ENABLE 0 +#define CAM_CPAS_SECURE_CAMERA_ENABLE 1 +#define CAM_CPAS_MF_HDR_ENABLE 2 +#define CAM_CPAS_MP_LIMIT_FUSE 3 +#define CAM_CPAS_ISP_FUSE 4 +#define CAM_CPAS_ISP_PIX_FUSE 5 +#define CAM_CPAS_ISP_LITE_FUSE 6 +#define CAM_CPAS_CSIPHY_FUSE 7 +#define CAM_CPAS_IPE_VID_OUT_8BPP_LIMIT_ENABLE 8 +#define CAM_CPAS_SFE_FUSE 9 +#define CAM_CPAS_CUSTOM_FUSE 10 +#define CAM_CPAS_CAM_FUSE 11 +#define CAM_CPAS_SHDR_FUSE 12 +#define CAM_CPAS_RT_OT_FUSE 13 +#define CAM_CPAS_FUSE_FEATURE_MAX 14 + +/* Flash type*/ +#define CAM_FLASH_TYPE_PMIC 0 +#define CAM_FLASH_TYPE_I2C 1 +#define CAM_FLASH_TYPE_GPIO 2 + +/* CCI master */ +#define CCI_MASTER_0 0 +#define CCI_MASTER_1 1 +#define CCI_MASTER_MAX 2 + +/* AON Camera IDs*/ +#define AON_CAM1 0 +#define AON_CAM2 1 +#define MAX_AON_CAM 2 +#define NOT_AON_CAM 255 + +/* Camera DRV enable masks */ +#define CAM_DDR_DRV 0x1 +#define CAM_CLK_DRV 0x2 + +/* Port index for BW voting */ +#define CAM_CPAS_PORT_HLOS_DRV 0 +#define CAM_CPAS_PORT_DRV_0 1 +#define CAM_CPAS_PORT_DRV_1 2 +#define CAM_CPAS_PORT_DRV_2 3 +#define CAM_CPAS_PORT_DRV_DYN 32 + +/* Domain ID types */ +#define CAM_CPAS_NON_SECURE_DOMAIN 0 +#define CAM_CPAS_SECURE_DOMAIN 1 + +/* Debug bypass driver */ +#define CAM_BYPASS_RGLTR 0x1 +#define CAM_BYPASS_RGLTR_MODE 0x2 +#define CAM_BYPASS_CLKS 0x4 +#define CAM_BYPASS_CESTA 0x8 +#define CAM_BYPASS_ICC 0x10 + +#endif From 4dfed6cfef30d5d7576e4721c1f838d9a40cc18e Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Fri, 10 Oct 2025 16:51:48 +0530 Subject: [PATCH 0159/1330] QCLINUX: arm64: dts: qcom: Add lemans camx overlay dts Add CAMX overlay dts file for lemans boards. This change also enables the compilation of the CAMX overlay on Lemans boards. Co-developed-by: Vikram Sharma Signed-off-by: Vikram Sharma Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/Makefile | 20 + .../boot/dts/qcom/lemans-camera-sensor.dtsi | 502 ++++ arch/arm64/boot/dts/qcom/lemans-camera.dtsi | 2559 +++++++++++++++++ .../dts/qcom/lemans-evk-camera-sensor.dtsi | 736 +++++ arch/arm64/boot/dts/qcom/lemans-evk-camx.dtso | 138 + .../boot/dts/qcom/sa8775p-ride-camx.dtso | 16 + 6 files changed, 3971 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/lemans-camera.dtsi create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-camx.dtso create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride-camx.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 529a5d56be714..b953af8076cca 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -411,3 +411,23 @@ x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb x1p64100-acer-swift-sf14-11-el2-dtbs := x1p64100-acer-swift-sf14-11.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-acer-swift-sf14-11.dtb x1p64100-acer-swift-sf14-11-el2.dtb + +lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camx.dtb + +qcs9100-ride-camx-dtbs:= qcs9100-ride.dtb sa8775p-ride-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-camx.dtb + +qcs9100-ride-r3-camx-dtbs:= qcs9100-ride-r3.dtb sa8775p-ride-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3-camx.dtb + +sa8775p-ride-camx-dtbs:= sa8775p-ride.dtb sa8775p-ride-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-camx.dtb + +sa8775p-ride-r3-camx-dtbs:= sa8775p-ride-r3.dtb sa8775p-ride-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/lemans-camera-sensor.dtsi new file mode 100644 index 0000000000000..d531f89dda08e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-camera-sensor.dtsi @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci0 { + /* GMSL deserializer 0 */ + qcom,cam-gmsl-deserializer0 { + cell-index = <0>; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&pmm8654au_0_gpios 7 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser0_port0: endpoint { + remote-endpoint = <&gmsl_sensor0_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser0_port1: endpoint { + remote-endpoint = <&gmsl_sensor1_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser0_port2: endpoint { + remote-endpoint = <&gmsl_sensor2_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser0_port3: endpoint { + remote-endpoint = <&gmsl_sensor3_ep>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 0 */ + qcom,cam-gmsl-sensor0 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <0>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor0_ep: endpoint { + remote-endpoint = <&deser0_port0>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 1 */ + qcom,cam-gmsl-sensor1 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <1>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor1_ep: endpoint { + remote-endpoint = <&deser0_port1>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 2 */ + qcom,cam-gmsl-sensor2 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <2>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor2_ep: endpoint { + remote-endpoint = <&deser0_port2>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 3 */ + qcom,cam-gmsl-sensor3 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <3>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor3_ep: endpoint { + remote-endpoint = <&deser0_port3>; + }; + }; + }; +}; + +&cam_cci1 { + /* GMSL deserializer 1 */ + qcom,cam-gmsl-deserializer1 { + cell-index = <1>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&pmm8654au_0_gpios 8 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser1_port0: endpoint { + remote-endpoint = <&gmsl_sensor4_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser1_port1: endpoint { + remote-endpoint = <&gmsl_sensor5_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser1_port2: endpoint { + remote-endpoint = <&gmsl_sensor6_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser1_port3: endpoint { + remote-endpoint = <&gmsl_sensor7_ep>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 0 */ + qcom,cam-gmsl-sensor4 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <4>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor4_ep: endpoint { + remote-endpoint = <&deser1_port0>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 1 */ + qcom,cam-gmsl-sensor5 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <5>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor5_ep: endpoint { + remote-endpoint = <&deser1_port1>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 2 */ + qcom,cam-gmsl-sensor6 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <6>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor6_ep: endpoint { + remote-endpoint = <&deser1_port2>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 3 */ + qcom,cam-gmsl-sensor7 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <7>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor7_ep: endpoint { + remote-endpoint = <&deser1_port3>; + }; + }; + }; +}; + +&cam_cci2 { + /* GMSL deserializer 2 */ + qcom,cam-gmsl-deserializer2 { + cell-index = <2>; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&pmm8654au_0_gpios 9 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET2"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser2_port0: endpoint { + remote-endpoint = <&gmsl_sensor8_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser2_port1: endpoint { + remote-endpoint = <&gmsl_sensor9_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser2_port2: endpoint { + remote-endpoint = <&gmsl_sensor10_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser2_port3: endpoint { + remote-endpoint = <&gmsl_sensor11_ep>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 0 */ + qcom,cam-gmsl-sensor8 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <8>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor8_ep: endpoint { + remote-endpoint = <&deser2_port0>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 1 */ + qcom,cam-gmsl-sensor9 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <9>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor9_ep: endpoint { + remote-endpoint = <&deser2_port1>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 2 */ + qcom,cam-gmsl-sensor10 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <10>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor10_ep: endpoint { + remote-endpoint = <&deser2_port2>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 3 */ + qcom,cam-gmsl-sensor11 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <11>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor11_ep: endpoint { + remote-endpoint = <&deser2_port3>; + }; + }; + }; +}; + +&cam_cci3 { + /* GMSL deserializer 3 */ + qcom,cam-gmsl-deserializer3 { + cell-index = <3>; + csiphy-sd-index = <3>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&pmm8654au_0_gpios 10 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET3"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser3_port0: endpoint { + remote-endpoint = <&gmsl_sensor12_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser3_port1: endpoint { + remote-endpoint = <&gmsl_sensor13_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser3_port2: endpoint { + remote-endpoint = <&gmsl_sensor14_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser3_port3: endpoint { + remote-endpoint = <&gmsl_sensor15_ep>; + }; + }; + }; + + /* GMSL deserializer 3 sensor 0 */ + qcom,cam-gmsl-sensor12 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <12>; + csiphy-sd-index = <3>; + status = "ok"; + + port { + gmsl_sensor12_ep: endpoint { + remote-endpoint = <&deser3_port0>; + }; + }; + }; + + /* GMSL deserializer 3 sensor 1 */ + qcom,cam-gmsl-sensor13 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <13>; + csiphy-sd-index = <3>; + status = "ok"; + + port { + gmsl_sensor13_ep: endpoint { + remote-endpoint = <&deser3_port1>; + }; + }; + }; + + /* GMSL deserializer 3 sensor 2 */ + qcom,cam-gmsl-sensor14 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <14>; + csiphy-sd-index = <3>; + status = "ok"; + + port { + gmsl_sensor14_ep: endpoint { + remote-endpoint = <&deser3_port2>; + }; + }; + }; + + /* GMSL deserializer 3 sensor 3 */ + qcom,cam-gmsl-sensor15 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <15>; + csiphy-sd-index = <3>; + status = "ok"; + + port { + gmsl_sensor15_ep: endpoint { + remote-endpoint = <&deser3_port3>; + }; + }; + }; +}; + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + gpios-shared = <518 519 520 521>; + status = "ok"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-camera.dtsi b/arch/arm64/boot/dts/qcom/lemans-camera.dtsi new file mode 100644 index 0000000000000..18d78926b1f17 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-camera.dtsi @@ -0,0 +1,2559 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&soc { + cam_cci0: qcom,cci0@ac13000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac13000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x13000>; + interrupts = ; + interrupt-names = "CCI0"; + operating-points-v2 = <&cci0_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-0 = <&cci0_active>; + pinctrl-1 = <&cci0_suspend>; + pinctrl-2 = <&cci1_active>; + pinctrl-3 = <&cci1_suspend>; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + cell-index = <0>; + status = "ok"; + + cci0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci0: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci0: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac14000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac14000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x14000>; + interrupts = ; + interrupt-names = "CCI1"; + operating-points-v2 = <&cci1_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + pinctrl-2 = <&cci3_active>; + pinctrl-3 = <&cci3_suspend>; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + cell-index = <1>; + status = "ok"; + + cci1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci1: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci1: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci2: qcom,cci2@ac15000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac15000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupts = ; + interrupt-names = "CCI2"; + operating-points-v2 = <&cci2_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names = "cci_2_clk_src", + "cci_2_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_2_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-0 = <&cci4_active>; + pinctrl-1 = <&cci4_suspend>; + pinctrl-2 = <&cci5_active>; + pinctrl-3 = <&cci5_suspend>; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + cell-index = <2>; + status = "ok"; + + cci2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci2: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci2: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci2: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci2: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci3: qcom,cci3@ac16000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac16000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupts = ; + interrupt-names = "CCI3"; + operating-points-v2 = <&cci3_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_3_CLK_SRC>, + <&camcc CAM_CC_CCI_3_CLK>; + clock-names = "cci_3_clk_src", + "cci_3_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_3_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-0 = <&cci6_active>; + pinctrl-1 = <&cci6_suspend>; + pinctrl-2 = <&cci7_active>; + pinctrl-3 = <&cci7_suspend>; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + cell-index = <3>; + status = "ok"; + + cci3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci3: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci3: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci3: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci3: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_csiphy0: qcom,csiphy0@ac9c000 { + compatible = "qcom,csiphy-v1.3.0", "qcom,csiphy"; + reg = <0x0 0x0ac9c000 0x0 0x2000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy0_opp_table>; + reg-cam-base = <0x9c000>; + interrupts = ; + interrupt-names = "CSIPHY0"; + csi-vdd-1p2-supply = <&vreg_l1c>; + csi-vdd-0p9-supply = <&vreg_l4a>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1140000 831000>; + rgltr-max-voltage = <1260000 920000>; + rgltr-load-current = <8900 15900>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <400000000 0 400000000 0>; + aggregator-rx; + cell-index = <0>; + status = "ok"; + + csiphy0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy1: qcom,csiphy1@ac9e000 { + compatible = "qcom,csiphy-v1.3.0", "qcom,csiphy"; + reg = <0x0 0xac9e000 0x0 0x2000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy1_opp_table>; + reg-cam-base = <0x9e000>; + interrupts = ; + interrupt-names = "CSIPHY1"; + csi-vdd-1p2-supply = <&vreg_l1c>; + csi-vdd-0p9-supply = <&vreg_l4a>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1140000 831000>; + rgltr-max-voltage = <1260000 920000>; + rgltr-load-current = <8900 15900>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <400000000 0 400000000 0>; + cell-index = <1>; + aggregator-rx; + status = "ok"; + + csiphy1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy2: qcom,csiphy2@aca0000 { + compatible = "qcom,csiphy-v1.3.0", "qcom,csiphy"; + reg = <0x0 0xaca0000 0x0 0x2000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy2_opp_table>; + reg-cam-base = <0xa0000>; + interrupts = ; + interrupt-names = "CSIPHY2"; + csi-vdd-1p2-supply = <&vreg_l1c>; + csi-vdd-0p9-supply = <&vreg_l4a>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1140000 831000>; + rgltr-max-voltage = <1260000 920000>; + rgltr-load-current = <8900 15900>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <400000000 0 400000000 0>; + cell-index = <2>; + aggregator-rx; + status = "ok"; + + csiphy2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy3: qcom,csiphy3@aca2000 { + compatible = "qcom,csiphy-v1.3.0", "qcom,csiphy"; + reg = <0x0 0xaca2000 0x0 0x2000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy3_opp_table>; + reg-cam-base = <0xa2000>; + interrupts = ; + interrupt-names = "CSIPHY3"; + csi-vdd-1p2-supply = <&vreg_l1c>; + csi-vdd-0p9-supply = <&vreg_l4a>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1140000 831000>; + rgltr-max-voltage = <1260000 920000>; + rgltr-load-current = <8900 15900>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <400000000 0 400000000 0>; + cell-index = <3>; + aggregator-rx; + status = "ok"; + + csiphy3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy_tpg17: qcom,tpg17@acac000 { + compatible = "qcom,cam-tpg1031"; + reg = <0x0 0xacac000 0x0 0x400>, + <0x0 0xac11000 0x0 0x1000>; + reg-names = "tpg0", "cam_cpas_top"; + reg-cam-base = <0xac000 0x11000>; + operating-points-v2 = <&csiphy_tpg0_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg0"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cphy_rx_clk_src"; + cell-index = <17>; + phy-id = <0>; + status = "ok"; + + csiphy_tpg0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy_tpg18: qcom,tpg18@acad000 { + compatible = "qcom,cam-tpg1031"; + reg = <0x0 0xacad000 0x0 0x400>, + <0x0 0xac11000 0x0 0x1000>; + reg-names = "tpg1", "cam_cpas_top"; + reg-cam-base = <0xad000 0x11000>; + operating-points-v2 = <&csiphy_tpg1_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg1"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cphy_rx_clk_src"; + cell-index = <18>; + phy-id = <1>; + status = "ok"; + + csiphy_tpg1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy_tpg19: qcom,tpg19@acae000 { + compatible = "qcom,cam-tpg1031"; + reg = <0x0 0xacae000 0x0 0x400>, + <0x0 0xac11000 0x0 0x1000>; + reg-names = "tpg2", "cam_cpas_top"; + reg-cam-base = <0xae000 0x11000>; + operating-points-v2 = <&csiphy_tpg2_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg2"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cphy_rx_clk_src"; + cell-index = <19>; + phy-id = <2>; + status = "ok"; + + csiphy_tpg2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + qcom,cam-cpas { + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg = <0x0 0xac11000 0x0 0x1000>, + <0x0 0xac1A000 0x0 0x9400>, + <0x0 0xbbf0000 0x0 0x1f00>; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg-cam-base = <0x11000 0x1A000 0x0bbf0000>; + interrupts = ; + interrupt-names = "cpas_camnoc"; + camnoc-axi-min-ib-bw = <3000000000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "gcc_camera_sf_axi_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk", + "cam_cc_core_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "cam_cc_camnoc_axi_clk_src", + "cam_cc_camnoc_axi_clk", + "cam_cc_qdss_debug_xo_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0 0>; + clock-cntl-level = "suspend", "svs_l1", "nominal"; + clock-names-option = "cam_icp_clk"; + clocks-option = <&camcc CAM_CC_ICP_CLK>; + clock-rates-option = <480000000>; + operating-points-v2 = <&cpas_opp_table>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + cam-icc-path-names = "cam_ahb"; + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", "cam_hf_0", "cam_sf_0", "cam_sf_icp"; + cam-ahb-num-cases = <7>; + cam-ahb-bw-KBps = <0 0>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", "turbo", "turbo"; + client-id-based; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "cci0", "cci1", "cci2", "cci3","csid0", "csid1", + "csid2", "csid3", "csid4", "csid5", "csid6", + "ife0", "ife1", "ife2", "ife3", "ife4", + "ife5", "ife6", "ipe0", "sfe0", "sfe1", + "cam-cdm-intf0", "rt-cdm0", "rt-cdm1", "rt-cdm2", + "rt-cdm3", "icp0", "tpg17", "tpg18", "tpg19"; + + enable-secure-qos-update; + cell-index = <0>; + status = "ok"; + + cpas_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + camera-bus-nodes { + level0-nodes { + level-index = <0>; + + icp_all_rd: icp-all-rd { + cell-index = <0>; + node-name = "icp-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_icp_rd>; + }; + + ife_0_wr_0: ife-0-wr-0 { + cell-index = <1>; + node-name = "ife-0-wr-0"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_0_wr_1: ife-0-wr-1 { + cell-index = <2>; + node-name = "ife-0-wr-1"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr1>; + }; + + ife_1_wr_0: ife-1-wr-0 { + cell-index = <3>; + node-name = "ife-1-wr-0"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + + ife_1_wr_1: ife-1-wr-1 { + cell-index = <4>; + node-name = "ife-1-wr-1"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr1>; + }; + + ife_lite_0_wr_0: ife-lite-0-wr-0 { + cell-index = <5>; + node-name = "ife-lite-0-wr-0"; + client-name = "ife2"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_lite_1_wr_0: ife-lite-1-wr-0 { + cell-index = <6>; + node-name = "ife-lite-1-wr-0"; + client-name = "ife3"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_lite_2_wr_0: ife-lite-2-wr-0 { + cell-index = <7>; + node-name = "ife-lite-2-wr-0"; + client-name = "ife4"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_lite_3_wr_0: ife-lite-3-wr-0 { + cell-index = <8>; + node-name = "ife-lite-3-wr-0"; + client-name = "ife5"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_lite_4_wr_0: ife-lite-4-wr-0 { + cell-index = <9>; + node-name = "ife-lite-4-wr-0"; + client-name = "ife6"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ipe_0_rd_all: ipe-0-rd-all { + cell-index = <10>; + node-name = "ipe-0-rd-all"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level2_nrt_rd1>; + }; + + ipe_0_wr_2: ipe-0-wr-2 { + cell-index = <11>; + node-name = "ipe-0-wr-2"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level2_nrt_wr2>; + }; + + ipe_cdm0_all_rd: ipe-cdm0-all-rd { + cell-index = <12>; + node-name = "ipe-cdm0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + rt_cdm0_all_rd_2: rt-cdm0-all-rd-2 { + cell-index = <13>; + node-name = "rt-cdm0-all-rd-2"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + rt_cdm1_all_rd_2: rt-cdm1-all-rd-2 { + cell-index = <14>; + node-name = "rt-cdm1-all-rd-2"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + rt_cdm2_all_rd_2: rt-cdm2-all-rd-2 { + cell-index = <15>; + node-name = "rt-cdm2-all-rd-2"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt_rd2>; + }; + + rt_cdm3_all_rd_2: rt-cdm3-all-rd-2 { + cell-index = <16>; + node-name = "rt-cdm3-all-rd-2"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + sfe_0_rd_0: sfe-0-rd-0 { + cell-index = <17>; + node-name = "sfe-0-rd-0"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_rd0>; + }; + + sfe_1_rd_0: sfe-1-rd-0 { + cell-index = <18>; + node-name = "sfe-1-rd-0"; + client-name = "sfe1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_rd0>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + + level1_nrt_rd2: level1-nrt-rd2 { + cell-index = <19>; + node-name = "level1-nrt-rd2"; + parent-node = <&level2_nrt_rd2>; + traffic-merge-type = ; + }; + + level1_rt_rd0: level1-rt-read0 { + cell-index = <20>; + node-name = "level1-rt-rd0"; + parent-node = <&level2_rt_rd0>; + traffic-merge-type = ; + }; + + level1_rt_wr0: level1-rt-wr0 { + cell-index = <21>; + node-name = "level1-rt-wr0"; + parent-node = <&level2_rt_wr0>; + traffic-merge-type = ; + }; + + level1_rt_wr1: level1-rt-wr1 { + cell-index = <22>; + node-name = "level1-rt-wr1"; + parent-node = <&level2_rt_wr1>; + traffic-merge-type = ; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + + level2_icp_rd: level2-icp-rd { + cell-index = <23>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_nrt_rd1: level2-nrt-rd1 { + cell-index = <24>; + node-name = "level2-nrt-rd1"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_nrt_rd2: level2-nrt-rd2 { + cell-index = <25>; + node-name = "level2-nrt-rd2"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_nrt_wr2: level2-nrt-wr2 { + cell-index = <26>; + node-name = "level2-nrt-wr2"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_rt_rd0: level2-rt-read0 { + cell-index = <27>; + node-name = "level2-rt-rd0"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_rt_wr0: level2-rt-wr0 { + cell-index = <28>; + node-name = "level2-rt-wr0"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_rt_wr1: level2-rt-wr1 { + cell-index = <29>; + node-name = "level2-rt-wr1"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = ; + }; + }; + + level3-nodes { + level-index = <3>; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <30>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <31>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_icp"; + }; + }; + + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <32>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0"; + }; + }; + }; + }; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", "qcom,ipe0"; + num-icp = <1>; + num-ipe = <1>; + icp_use_pil; + status = "ok"; + }; + + qcom,cam-i3c-id-table { + i3c-sensor-id-table = <0x1B0 0x0766>; + i3c-eeprom-id-table = <>; + i3c-actuator-id-table = <>; + i3c-ois-id-table = <>; + status = "disabled"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam-smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + force_cache_allocs; + status = "ok"; + + msm-cam-smmu-cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0860 0x400>, + <&apps_smmu 0x0C60 0x400>; + cam-smmu-label = "rt-cdm"; + dma-coherent; + multiple-client-devices; + + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0800 0x400>, + <&apps_smmu 0x0840 0x480>, + <&apps_smmu 0x08C0 0x480>, + <&apps_smmu 0x0C00 0x400>, + <&apps_smmu 0x0C40 0x480>, + <&apps_smmu 0x0CC0 0x480>; + cam-smmu-label = "icp"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + iova-region-discard = <0xe0000000 0x800000>; + dma-coherent; + + icp_iova_mem_map: iova-mem-map { + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + iova-region-start = <0x10400000>; + iova-region-len = <0x700000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x10400000>; + iova-region-len = <0x200000>; + iova-region-id = <0x0>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 3.8 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xe0000000 0x800000>; + status = "ok"; + }; + + iova-mem-region-qdss { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is ~250MB long */ + iova-region-name = "shared"; + iova-region-start = <0x800000>; + iova-region-len = <0xfc00000>; + iova-region-id = <0x1>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x3400 0x0020>, + <&apps_smmu 0x3420 0x0020>; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + dma-coherent; + + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,camera-main { + compatible = "qcom,camera"; + status = "ok"; + }; + + cam_csid0: qcom,csid0 { + compatible = "qcom,csid690"; + reg = <0x0 0xac7a000 0x0 0xf01>, + <0x0 0xac78000 0x0 0x1000>; + reg-names = "csid0", "csid_top"; + reg-cam-base = <0x7a000 0x78000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "csid0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cam_cc_csid_clk_src", + "cam_cc_csid_clk", + "cam_cc_csid_csiphy_rx_clk"; + clock-rates = <400000000 0 0>; + clock-cntl-level = "svs_l1"; + src-clock-name = "cam_cc_csid_clk_src"; + operating-points-v2 = <&csid0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "ok"; + + csid0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + cam_csid1: qcom,csid1 { + compatible = "qcom,csid690"; + reg = <0x0 0xac7c000 0x0 0xf01>, + <0x0 0xac78000 0x0 0x1000>; + reg-names = "csid1", "csid_top"; + reg-cam-base = <0x7c000 0x78000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "csid0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cam_cc_csid_clk_src", + "cam_cc_csid_clk", + "cam_cc_csid_csiphy_rx_clk"; + clock-rates = <400000000 0 0>; + clock-cntl-level = "svs_l1"; + src-clock-name = "cam_cc_csid_clk_src"; + operating-points-v2 = <&csid1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "ok"; + + csid1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + cam_csid_lite0: qcom,csid-lite0 { + compatible = "qcom,csid-lite690"; + reg = <0x0 0xac84000 0x0 0xf01>; + reg-names = "csid-lite0"; + reg-cam-base = <0x84000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "csid-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <2>; + status = "ok"; + + csid_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite1: qcom,csid-lite1 { + compatible = "qcom,csid-lite690"; + reg = <0x0 0xac88000 0x0 0xf01>; + reg-names = "csid-lite1"; + reg-cam-base = <0x88000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "csid-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <3>; + status = "ok"; + + csid_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite2: qcom,csid-lite2 { + compatible = "qcom,csid-lite690"; + reg = <0x0 0xac8c000 0x0 0xf01>; + reg-names = "csid-lite2"; + reg-cam-base = <0x8c000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "csid-lite2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite2_opp_table>; + clock-control-debugfs = "true"; + cell-index = <4>; + status = "ok"; + + csid_lite2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite3: qcom,csid-lite3 { + compatible = "qcom,csid-lite690"; + reg = <0x0 0xac90000 0x0 0xf01>; + reg-names = "csid-lite3"; + reg-cam-base = <0x90000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "csid-lite3"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite3_opp_table>; + clock-control-debugfs = "true"; + cell-index = <5>; + status = "ok"; + + csid_lite3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite4: qcom,csid-lite4 { + compatible = "qcom,csid-lite690"; + reg = <0x0 0xac94000 0x0 0xf01>; + reg-names = "csid-lite4"; + reg-cam-base = <0x94000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "csid-lite4"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite4_opp_table>; + clock-control-debugfs = "true"; + cell-index = <6>; + status = "ok"; + + csid_lite4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_icp: qcom,icp { + compatible = "qcom,cam-icp_v3_0"; + reg = <0x0 0xac01000 0x0 0x400>, + <0x0 0xac01800 0x0 0x400>, + <0x0 0xac04000 0x0 0x1000>; + reg-names ="icp_csr", "icp_cirq", "icp_wd0"; + reg-cam-base = <0x1000 0x1800 0x4000>; + interrupts = ; + interrupt-names = "icp"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + memory-region = <&pil_camera_mem>; + src-clock-name = "cam_cc_icp_clk_src"; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + clock-names = "cam_cc_soc_fast_ahb_clk_src", + "cam_cc_icp_ahb_clk", + "cam_cc_icp_clk_src", + "cam_cc_icp_clk"; + clock-rates = <300000000 0 480000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + nrt-device; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + qos-val = <0xa0a>; + operating-points-v2 = <&icp_opp_table>; + icp-version = <0x0300>; + cam_hw_pid = <12>; + cell-index = <0>; + status = "ok"; + + icp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe0: qcom,ife0 { + compatible = "qcom,vfe690"; + reg = <0x0 0xac4d000 0x0 0xd000>, + <0x0 0xac1a000 0x0 0x9400>; + reg-names = "ife0", "cam_camnoc"; + reg-cam-base = <0x4d000 0x1a000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "ife0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>; + clock-names = "cam_cc_cpas_ife_0_clk", + "cam_cc_ife_0_clk", + "cam_cc_ife_0_clk_src", + "cam_cc_ife_0_fast_ahb_clk"; + clock-rates = <0 0 480000000 0>, + <0 0 600000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_0_clk_src"; + operating-points-v2 = <&vfe0_opp_table>; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <8 16>; + cell-index = <0>; + status = "ok"; + + vfe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe1: qcom,ife1 { + compatible = "qcom,vfe690"; + reg = <0x0 0xac5a000 0x0 0xd000>, + <0x0 0xac1a000 0x0 0x9400>; + reg-names = "ife1", "cam_camnoc"; + reg-cam-base = <0x5a000 0x1a000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "ife1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>; + clock-names = "cam_cc_cpas_ife_1_clk", + "cam_cc_ife_1_clk", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_1_fast_ahb_clk"; + clock-rates = <0 0 480000000 0>, + <0 0 600000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_1_clk_src"; + operating-points-v2 = <&vfe1_opp_table>; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <9 17>; + cell-index = <1>; + status = "ok"; + + vfe1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite0: qcom,ife-lite0 { + compatible = "qcom,vfe-lite690"; + reg = <0x0 0xac84000 0x0 0x1d00>; + reg-names = "ife-lite0"; + reg-cam-base = <0x84000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <2>; + status = "ok"; + + vfe_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite1: qcom,ife-lite1 { + compatible = "qcom,vfe-lite690"; + reg = <0x0 0xac88000 0x0 0x1d00>; + reg-names = "ife-lite1"; + reg-cam-base = <0x88000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite1_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <3>; + status = "ok"; + + vfe_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite2: qcom,ife-lite2 { + compatible = "qcom,vfe-lite690"; + reg = <0x0 0xac8c000 0x0 0x1d00>; + reg-names = "ife-lite2"; + reg-cam-base = <0x8c000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite2_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <4>; + status = "ok"; + + vfe_lite2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite3: qcom,ife-lite3 { + compatible = "qcom,vfe-lite690"; + reg = <0x0 0xac90000 0x0 0x1d00>; + reg-names = "ife-lite3"; + reg-cam-base = <0x90000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite3"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite3_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <5>; + status = "ok"; + + vfe_lite3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite4: qcom,ife-lite4 { + compatible = "qcom,vfe-lite690"; + reg = <0x0 0xac94000 0x0 0x1d00>; + reg-names = "ife-lite4"; + reg-cam-base = <0x94000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite4"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite4_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <6>; + status = "ok"; + + vfe_lite4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_ipe0: qcom,ipe0 { + compatible = "qcom,cam-ipe"; + reg = <0x0 0xac2d000 0x0 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x2d000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + src-clock-name = "cam_cc_ipe_clk_src"; + clocks = <&camcc CAM_CC_CPAS_IPE_CLK>, + <&camcc CAM_CC_IPE_AHB_CLK>, + <&camcc CAM_CC_IPE_CLK>, + <&camcc CAM_CC_IPE_CLK_SRC>, + <&camcc CAM_CC_IPE_FAST_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>; + clock-names = "cam_cc_cpas_ipe_clk", + "cam_cc_ipe_ahb_clk", + "cam_cc_ipe_clk", + "cam_cc_ipe_clk_src", + "cam_cc_ipe_fast_ahb_clk", + "cam_cc_fast_ahb_clk_src"; + clock-rates = <0 0 0 480000000 0 300000000>, + <0 0 0 600000000 0 400000000>; + clock-cntl-level = "svs_l1", "nominal"; + operating-points-v2 = <&ipe0_opp_table>; + nrt-device; + cam_hw_pid = <14 15>; + cell-index = <0>; + status = "ok"; + + ipe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + }; + + qcom,rt-cdm0 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac26000 0x0 0x1000>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x26000>; + interrupts = ; + interrupt-names = "rt-cdm0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <300000000 0>; + operating-points-v2 = <&cdm_cpas_opp_table0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife0", "dualife0"; + single-context-cdm; + cell-index = <0>; + status = "ok"; + + cdm_cpas_opp_table0: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + qcom,rt-cdm1 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac27000 0x0 0x1000>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x27000>; + interrupts = ; + interrupt-names = "rt-cdm1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <300000000 0>; + operating-points-v2 = <&cdm_cpas_opp_table1>; + clock-cntl-level = "svs_l1"; + cdm-client-names = "ife1", "dualife1"; + single-context-cdm; + cell-index = <1>; + status = "ok"; + + cdm_cpas_opp_table1: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + qcom,rt-cdm2 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac28000 0x0 0x1000>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x28000>; + interrupts = ; + interrupt-names = "rt-cdm2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-rates = <80000000 0>; + operating-points-v2 = <&cdm_cpas_opp_table2>; + clock-cntl-level = "svs_l1"; + cdm-client-names = "ife2", "ife3", "ife4", "ife5", "ife6"; + single-context-cdm; + cell-index = <2>; + status = "ok"; + + cdm_cpas_opp_table2: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + qcom,rt-cdm3 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac29000 0x0 0x1000>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x29000>; + interrupts = ; + interrupt-names = "rt-cdm3"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-rates = <80000000 0>; + operating-points-v2 = <&cdm_cpas_opp_table3>; + clock-cntl-level = "svs"; + cdm-client-names = "ife2", "ife3", "ife4", "ife5", "ife6"; + single-context-cdm; + cell-index = <3>; + status = "ok"; + + cdm_cpas_opp_table3: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_sfe_lite0: qcom,sfe-lite0 { + compatible = "qcom,sfe-lite690"; + reg = <0x0 0xac74000 0x0 0x1000>; + reg-names = "sfe-lite0"; + reg-cam-base = <0x74000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "sfe-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clock-names = "cam_cc_sfe_lite_0_fast_ahb_clk", + "cam_cc_sfe_lite_0_clk", + "cam_cc_cpas_sfe_lite_0_clk"; + clocks = <&camcc CAM_CC_SFE_LITE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_LITE_0_CLK>, + <&camcc CAM_CC_CPAS_SFE_LITE_0_CLK>; + clock-rates = <0 480000000 300000000>, + <0 600000000 400000000>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_sfe_lite_0_clk"; + operating-points-v2 = <&cam_sfe_lite_opp_table0>; + cam_hw_pid = <4>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "ok"; + + cam_sfe_lite_opp_table0: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_sfe_lite1: qcom,sfe-lite1 { + compatible = "qcom,sfe-lite690"; + reg = <0x0 0xac75000 0x0 0x1000>; + reg-names = "sfe-lite1"; + reg-cam-base = <0x75000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "sfe-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SFE_LITE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_LITE_1_CLK>, + <&camcc CAM_CC_CPAS_SFE_LITE_1_CLK>; + clock-names = "cam_cc_sfe_lite_1_fast_ahb_clk", + "cam_cc_sfe_lite_1_clk", + "cam_cc_cpas_sfe_1_clk"; + clock-rates = <0 480000000 300000000>, + <0 600000000 400000000>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_sfe_lite_1_clk"; + operating-points-v2 = <&cam_sfe_lite_opp_table1>; + cam_hw_pid = <5>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "ok"; + + cam_sfe_lite_opp_table1: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +}; + +&tlmm { + cam_sensor_mclk0_active: cam-sensor-mclk0-active { + /* MCLK0 */ + mux { + pins = "gpio72"; + function = "cam_mclk"; + }; + + config { + pins = "gpio72"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam-sensor-mclk0-suspend { + /* MCLK0 */ + mux { + pins = "gpio72"; + function = "cam_mclk"; + }; + + config { + pins = "gpio72"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam-sensor-mclk1-active { + /* MCLK1 */ + mux { + pins = "gpio73"; + function = "cam_mclk"; + }; + + config { + pins = "gpio73"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam-sensor-mclk1-suspend { + /* MCLK1 */ + mux { + pins = "gpio73"; + function = "cam_mclk"; + }; + + config { + pins = "gpio73"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam-sensor-mclk2-active { + /* MCLK2 */ + mux { + pins = "gpio74"; + function = "cam_mclk"; + }; + + config { + pins = "gpio74"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam-sensor-mclk2-suspend { + /* MCLK2 */ + mux { + pins = "gpio74"; + function = "cam_mclk"; + }; + + config { + pins = "gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam-sensor-mclk3-active { + /* MCLK3 */ + mux { + pins = "gpio75"; + function = "cam_mclk"; + }; + + config { + pins = "gpio75"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam-sensor-mclk3-suspend { + /* MCLK3 */ + mux { + pins = "gpio75"; + function = "cam_mclk"; + }; + + config { + pins = "gpio75"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_active: cci0-active { + mux { + /* CLK, DATA */ + pins = "gpio61","gpio60"; + function = "cci_i2c"; + }; + + config { + pins = "gpio61","gpio60"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; /* I2C PULL */ + }; + }; + + cci0_suspend: cci0-suspend { + mux { + /* CLK, DATA */ + pins = "gpio61","gpio60"; + function = "cci_i2c"; + }; + + config { + pins = "gpio61","gpio60"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1-active { + mux { + /* CLK, DATA */ + pins = "gpio53","gpio52"; + function = "cci_i2c"; + }; + + config { + pins = "gpio53","gpio52"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; /* I2C PULL */ + }; + }; + + cci1_suspend: cci1-suspend { + mux { + /* CLK, DATA */ + pins = "gpio53","gpio52"; + function = "cci_i2c"; + }; + + config { + pins = "gpio53","gpio52"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2-active { + mux { + /* CLK, DATA */ + pins = "gpio63","gpio62"; + function = "cci_i2c"; + }; + + config { + pins = "gpio63","gpio62"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; /* I2C PULL */ + }; + }; + + cci2_suspend: cci2-suspend { + mux { + /* CLK, DATA */ + pins = "gpio63","gpio62"; + function = "cci_i2c"; + }; + + config { + pins = "gpio63","gpio62"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3-active { + mux { + /* CLK, DATA */ + pins = "gpio55","gpio54"; + function = "cci_i2c"; + }; + + config { + pins = "gpio55","gpio54"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; /* I2C PULL */ + }; + }; + + cci3_suspend: cci3-suspend { + mux { + /* CLK, DATA */ + pins = "gpio55","gpio54"; + function = "cci_i2c"; + }; + + config { + pins = "gpio55","gpio54"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci4_active: cci4-active { + mux { + /* CLK, DATA */ + pins = "gpio65","gpio64"; + function = "cci_i2c"; + }; + + config { + pins = "gpio65","gpio64"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; /* I2C PULL */ + }; + }; + + cci4_suspend: cci4-suspend { + mux { + /* CLK, DATA */ + pins = "gpio65","gpio64"; + function = "cci_i2c"; + }; + + config { + pins = "gpio65","gpio64"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci5_active: cci5-active { + mux { + /* CLK, DATA */ + pins = "gpio57","gpio56"; + function = "cci_i2c"; + }; + + config { + pins = "gpio57","gpio56"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; /* I2C PULL */ + }; + }; + + cci5_suspend: cci5-suspend { + mux { + /* CLK, DATA */ + pins = "gpio57","gpio56"; + function = "cci_i2c"; + }; + + config { + pins = "gpio57","gpio56"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci6_active: cci6-active { + mux { + /* CLK, DATA */ + pins = "gpio67","gpio66"; + function = "cci_i2c"; + }; + + config { + pins = "gpio67","gpio66"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; /* I2C PULL */ + }; + }; + + cci6_suspend: cci6-suspend { + mux { + /* CLK, DATA */ + pins = "gpio67","gpio66"; + function = "cci_i2c"; + }; + + config { + pins = "gpio67","gpio66"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci7_active: cci7-active { + mux { + /* CLK, DATA */ + pins = "gpio59","gpio58"; + function = "cci_i2c"; + }; + + config { + pins = "gpio59","gpio58"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; /* I2C PULL */ + }; + }; + + cci7_suspend: cci7-suspend { + mux { + /* CLK, DATA */ + pins = "gpio59","gpio58"; + function = "cci_i2c"; + }; + + config { + pins = "gpio59","gpio58"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi new file mode 100644 index 0000000000000..8eb1026e7da1b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci0 { + /* GMSL deserializer 0 */ + qcom,cam-gmsl-deserializer0 { + cell-index = <0>; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&pmm8654au_0_gpios 7 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser0_port0: endpoint { + remote-endpoint = <&gmsl_sensor0_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser0_port1: endpoint { + remote-endpoint = <&gmsl_sensor1_ep>; + }; + }; + + port@2 { + reg = <0>; + deser0_port2: endpoint { + remote-endpoint = <&gmsl_sensor2_ep>; + }; + }; + + port@3 { + reg = <1>; + deser0_port3: endpoint { + remote-endpoint = <&gmsl_sensor3_ep>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 0 */ + qcom,cam-gmsl-sensor0 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <0>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor0_ep: endpoint { + remote-endpoint = <&deser0_port0>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 1 */ + qcom,cam-gmsl-sensor1 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <1>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor1_ep: endpoint { + remote-endpoint = <&deser0_port1>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 2 */ + qcom,cam-gmsl-sensor2 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <2>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor2_ep: endpoint { + remote-endpoint = <&deser0_port2>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 3 */ + qcom,cam-gmsl-sensor3 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <3>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor3_ep: endpoint { + remote-endpoint = <&deser0_port3>; + }; + }; + }; + + /*cam0a-ov9282*/ + qcom,cam-sensor1 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 72 0>, + <&tlmm 132 0>, + <&pmm8654au_0_gpios 7 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK0", + "CAMIF_RESET0", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <20>; + status = "ok"; + }; + + /*cam24-ov13858*/ + qcom,cam-sensor24 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam24>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 72 0>, + <&tlmm 132 0>, + <&pmm8654au_0_gpios 7 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK0", + "CAMIF_RESET0", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <24>; + status = "ok"; + }; + + eeprom_cam24: qcom,eeprom24 { + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 72 0>, + <&tlmm 132 0>, + <&pmm8654au_0_gpios 7 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK0", + "CAMIF_RESET0", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <24>; + status = "ok"; + }; +}; + +&cam_cci1 { + /* GMSL deserializer 1 */ + qcom,cam-gmsl-deserializer1 { + cell-index = <1>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&pmm8654au_0_gpios 8 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser1_port0: endpoint { + remote-endpoint = <&gmsl_sensor4_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser1_port1: endpoint { + remote-endpoint = <&gmsl_sensor5_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser1_port2: endpoint { + remote-endpoint = <&gmsl_sensor6_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser1_port3: endpoint { + remote-endpoint = <&gmsl_sensor7_ep>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 0 */ + qcom,cam-gmsl-sensor4 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <4>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor4_ep: endpoint { + remote-endpoint = <&deser1_port0>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 1 */ + qcom,cam-gmsl-sensor5 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <5>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor5_ep: endpoint { + remote-endpoint = <&deser1_port1>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 2 */ + qcom,cam-gmsl-sensor6 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <6>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor6_ep: endpoint { + remote-endpoint = <&deser1_port2>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 3 */ + qcom,cam-gmsl-sensor7 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <7>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor7_ep: endpoint { + remote-endpoint = <&deser1_port3>; + }; + }; + }; + + /*cam1-ov9282*/ + qcom,cam-sensor21 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 73 0>, + <&tlmm 133 0>, + <&pmm8654au_0_gpios 8 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <21>; + status = "ok"; + }; +}; + +&cam_cci2 { + /* GMSL deserializer 2 */ + qcom,cam-gmsl-deserializer2 { + cell-index = <2>; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&pmm8654au_0_gpios 9 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET2"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser2_port0: endpoint { + remote-endpoint = <&gmsl_sensor8_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser2_port1: endpoint { + remote-endpoint = <&gmsl_sensor9_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser2_port2: endpoint { + remote-endpoint = <&gmsl_sensor10_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser2_port3: endpoint { + remote-endpoint = <&gmsl_sensor11_ep>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 0 */ + qcom,cam-gmsl-sensor8 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <8>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor8_ep: endpoint { + remote-endpoint = <&deser2_port0>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 1 */ + qcom,cam-gmsl-sensor9 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <9>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor9_ep: endpoint { + remote-endpoint = <&deser2_port1>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 2 */ + qcom,cam-gmsl-sensor10 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <10>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor10_ep: endpoint { + remote-endpoint = <&deser2_port2>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 3 */ + qcom,cam-gmsl-sensor11 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <11>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor11_ep: endpoint { + remote-endpoint = <&deser2_port3>; + }; + }; + }; + + /*cam2-ov9282*/ + qcom,cam-sensor22 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 74 0>, + <&tlmm 134 0>, + <&pmm8654au_0_gpios 9 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK2", + "CAMIF_RESET2", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <22>; + status = "ok"; + }; +}; + +&cam_cci3 { + /* GMSL deserializer 3 */ + qcom,cam-gmsl-deserializer3 { + cell-index = <3>; + csiphy-sd-index = <3>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&pmm8654au_0_gpios 10 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET3"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser3_port0: endpoint { + remote-endpoint = <&gmsl_sensor12_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser3_port1: endpoint { + remote-endpoint = <&gmsl_sensor13_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser3_port2: endpoint { + remote-endpoint = <&gmsl_sensor14_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser3_port3: endpoint { + remote-endpoint = <&gmsl_sensor15_ep>; + }; + }; + }; + + /* GMSL deserializer 3 sensor 0 */ + qcom,cam-gmsl-sensor12 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <12>; + csiphy-sd-index = <3>; + status = "ok"; + + port { + gmsl_sensor12_ep: endpoint { + remote-endpoint = <&deser3_port0>; + }; + }; + }; + + /* GMSL deserializer 3 sensor 1 */ + qcom,cam-gmsl-sensor13 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <13>; + csiphy-sd-index = <3>; + status = "ok"; + + port { + gmsl_sensor13_ep: endpoint { + remote-endpoint = <&deser3_port1>; + }; + }; + }; + + /* GMSL deserializer 3 sensor 2 */ + qcom,cam-gmsl-sensor14 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <14>; + csiphy-sd-index = <3>; + status = "ok"; + + port { + gmsl_sensor14_ep: endpoint { + remote-endpoint = <&deser3_port2>; + }; + }; + }; + + /* GMSL deserializer 3 sensor 3 */ + qcom,cam-gmsl-sensor15 { + cell-index = <15>; + compatible = "qcom,cam-gmsl-sensor"; + csiphy-sd-index = <3>; + status = "ok"; + + port { + gmsl_sensor15_ep: endpoint { + remote-endpoint = <&deser3_port3>; + }; + }; + }; + + /*cam3-ov9282*/ + qcom,cam-sensor23 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 75 0>, + <&tlmm 135 0>, + <&pmm8654au_0_gpios 10 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK3", + "CAMIF_RESET3", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <23>; + status = "ok"; + }; +}; + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + gpios-shared = <518 519 520 521>; + status = "ok"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camx.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-camx.dtso new file mode 100644 index 0000000000000..520fb14660142 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camx.dtso @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "lemans-camera.dtsi" +#include "lemans-evk-camera-sensor.dtsi" + +&camss { + status = "disabled"; +}; + +&tlmm { + cam_sensor_active_rst0: cam-sensor-active-rst0 { + /* RESET */ + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst1: cam-sensor-active-rst1 { + /* RESET */ + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst2: cam-sensor-active-rst2 { + /* RESET */ + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst3: cam-sensor-active-rst3 { + /* RESET */ + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam-sensor-suspend-rst0 { + /* RESET */ + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst1: cam-sensor-suspend-rst1 { + /* RESET */ + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst2: cam-sensor-suspend-rst2 { + /* RESET */ + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst3: cam-sensor-suspend-rst3 { + /* RESET */ + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-camx.dtso b/arch/arm64/boot/dts/qcom/sa8775p-ride-camx.dtso new file mode 100644 index 0000000000000..f81fa6565f281 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-camx.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "lemans-camera.dtsi" +#include "lemans-camera-sensor.dtsi" From 8a5d1cfe27fe3e6fb5072fb07bf7a60868583043 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Fri, 17 Oct 2025 11:25:35 +0530 Subject: [PATCH 0160/1330] QCLINUX: arm64: dts: qcom: Add rb3gen2 camx overlay dts Add CAMX overlay dts file for rb3gen2 vision mezzanine board. This change also enables the compilation of the CAMX overlay for Kodiak rb3gen2 vision mezzanine board. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/Makefile | 5 + arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi | 2471 +++++++++++++++++ .../qcom/qcs6490-rb3gen2-camera-sensor.dtsi | 551 ++++ ...qcs6490-rb3gen2-vision-mezzanine-camx.dtso | 24 + 4 files changed, 3051 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine-camx.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b953af8076cca..48432400e1332 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -416,6 +416,11 @@ lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camx.dtb +qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.dtb \ + qcs6490-rb3gen2-vision-mezzanine-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtb + qcs9100-ride-camx-dtbs:= qcs9100-ride.dtb sa8775p-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi new file mode 100644 index 0000000000000..f6af6827784bd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi @@ -0,0 +1,2471 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&soc { + cam_a5: qcom,a5 { + compatible = "qcom,cam-a5"; + cell-index = <0>; + reg = <0x0 0xac00000 0x0 0x6000>, + <0x0 0xac10000 0x0 0x8000>, + <0x0 0xac18000 0x0 0x3000>; + reg-names = "a5_qgic", "a5_sierra", "a5_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "a5"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + clock-names = "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + clock-rates = <100000000 0 400000000 0>, + <200000000 0 400000000 0>, + <300000000 0 600000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "soc_fast_ahb"; + operating-points-v2 = <&a5_opp_table>; + fw_name = "CAMERA_ICP_170.elf"; + ubwc-ipe-fetch-cfg = <0x7073 0x707b>; + ubwc-ipe-write-cfg = <0x161cf 0x161ef>; + ubwc-bps-fetch-cfg = <0x7073 0x707b>; + ubwc-bps-write-cfg = <0x161cf 0x161ef>; + qos-val = <0x00000A0A>; + status = "ok"; + + a5_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_bps: qcom,bps { + compatible = "qcom,cam-bps"; + cell-index = <0>; + reg = <0x0 0xac6f000 0x0 0x8000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + power-domains = <&camcc CAM_CC_BPS_GDSC>; + clocks = <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>; + clock-names = "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + clock-rates = <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + src-clock-name = "bps_clk_src"; + operating-points-v2 = <&bps_opp_table>; + clock-control-debugfs = "true"; + status = "ok"; + + bps_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "lrmecdm"; + status = "ok"; + }; + + qcom,cam-cpas { + compatible = "qcom,cam-cpas"; + cell-index = <0>; + label = "cpas"; + arch-compat = "cpas_top"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac9f000 0x0 0x10000>; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg-cam-base = <0x40000 0x9f000>; + cam_hw_fuse = , + , + , + , + , + ; + interrupts = ; + interrupt-names = "cpas_camnoc"; + camnoc-axi-min-ib-bw = <3000000000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK>; + clock-names = "gcc_camera_hf_axi_clk", + "gcc_camera_sf_axi_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk_src", + "cam_cc_camnoc_axi_clk", + "cam_cc_icp_ahb_clk", + "cam_cc_icp_clk"; + src-clock-name = "cam_cc_camnoc_axi_clk_src"; + clock-rates = <0 0 0 0 0 0 0 0>, + <0 0 80000000 0 150000000 0 0 0>, + <0 0 80000000 0 240000000 0 0 0>, + <0 0 80000000 0 320000000 0 0 0>, + <0 0 80000000 0 400000000 0 0 0>, + <0 0 80000000 0 480000000 0 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + operating-points-v2 = <&cpas_opp_table>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", "cam_hf_0", "cam_sf_0", "cam_sf_icp"; + cam-ahb-num-cases = <7>; + cam-ahb-bw-KBps = <0 0>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", "turbo", "turbo"; + client-id-based; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "cci0", "cci1", "csid0", "csid1", + "csid2", "csid3", "csid4", "ife0", "ife1", + "ife2", "ife3", "ife4", "ipe0", "cam-cdm-intf0", + "cpas-cdm0", "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", + "lrmecpas0"; + status = "ok"; + + cpas_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + + camera-bus-nodes { + level0-nodes { + level-index = <0>; + + bps0_all_rd: bps0-all-rd { + cell-index = <0>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_read0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <1>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_write0>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <2>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_read0>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <3>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt1_read0>; + }; + + ife0_pixelall_wr: ife0-pixelall-wr { + cell-index = <4>; + node-name = "ife0-pixelall-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt1_write0>; + }; + + ife0_rdi_wr: ife0-rdi-wr { + cell-index = <5>; + node-name = "ife0-rdi-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ife1_pixelall_wr: ife1-pixelall-wr { + cell-index = <6>; + node-name = "ife1-pixelall-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt1_write0>; + }; + + ife1_rdi_wr: ife1-rdi-wr { + cell-index = <7>; + node-name = "ife1-rdi-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ife2_pixelall_wr: ife2-pixelall-wr { + cell-index = <8>; + node-name = "ife2-pixelall-wr"; + client-name = "ife2"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt1_write1>; + }; + + ife2_rdi_wr: ife2-rdi-wr { + cell-index = <9>; + node-name = "ife2-rdi-wr"; + client-name = "ife2"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ife3_rdi_wr: ife3-rdi-wr { + cell-index = <10>; + node-name = "ife3-rdi-wr"; + client-name = "ife3"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ife4_rdi_wr: ife4-rdi-wr { + cell-index = <11>; + node-name = "ife4-rdi-wr"; + client-name = "ife4"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ipe0_all_rd: ipe0-all-rd { + cell-index = <12>; + node-name = "ipe0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_nrt0_read0>; + }; + + ipe0_ref_wr: ipe0-ref-wr { + cell-index = <13>; + node-name = "ipe0-ref-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_write0>; + }; + + ipe0_viddisp_wr: ipe0-viddisp-wr { + cell-index = <14>; + node-name = "ipe0-viddisp-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_nrt0_write0>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <15>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt1_read0>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <16>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt1_write0>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <17>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt1_read0>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <18>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt1_write0>; + }; + + lrme0_all_rd: lrme0-all-rd { + cell-index = <19>; + node-name = "lrme0-all-rd"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_read0>; + }; + + lrme0_all_wr: lrme0-all-wr { + cell-index = <20>; + node-name = "lrme0-all-wr"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_write0>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + + level1_nrt0_write0: level1-nrt0-write0 { + cell-index = <21>; + node-name = "level1-nrt0-write0"; + parent-node = <&level2_nrt0_write0>; + traffic-merge-type = ; + }; + + level1_nrt0_read0: level1-nrt0-read0 { + cell-index = <22>; + node-name = "level1-nrt0-read0"; + parent-node = <&level2_nrt0_read0>; + traffic-merge-type = ; + }; + + level1_nrt1_write0: level1-nrt1-write0 { + cell-index = <23>; + node-name = "level1-nrt1-write0"; + parent-node = <&level2_nrt0_write0>; + traffic-merge-type = ; + }; + + level1_nrt1_read0: level1-nrt1-read0 { + cell-index = <24>; + node-name = "level1-nrt1-read0"; + parent-node = <&level2_nrt0_read0>; + traffic-merge-type = ; + }; + + level1_rt0_write0: level1-rt0-write0 { + cell-index = <25>; + node-name = "level1-rt0-write0"; + parent-node = <&level2_rt0_write0>; + traffic-merge-type = ; + }; + + level1_rt1_write0: level1-rt1-write0 { + cell-index = <26>; + node-name = "level1-rt1-write0"; + parent-node = <&level2_rt1_write0>; + traffic-merge-type = ; + }; + + level1_rt1_write1: level1-rt1-write1 { + cell-index = <27>; + node-name = "level1-rt1-write1"; + parent-node = <&level2_rt1_write0>; + traffic-merge-type = ; + }; + }; + + level2-nodes { + level-index = <3>; + camnoc-max-needed; + + level2_nrt0_write0: level2-nrt0-write0 { + cell-index = <28>; + node-name = "level2-nrt0-write0"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_nrt0_read0: level2-nrt0-read0 { + cell-index = <29>; + node-name = "level2-nrt0-read0"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_nrt1_read0: level2-nrt1-read0 { + cell-index = <30>; + node-name = "level2-nrt1-read0"; + parent-node = <&level3_nrt1_rd_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + + level2_rt0_write0: level2-rt0-write0 { + cell-index = <31>; + node-name = "level2-rt0-write0"; + parent-node = <&level3_rt0_wr_sum>; + traffic-merge-type = ; + }; + + level2_rt1_write0: level2-rt1-write0 { + cell-index = <32>; + node-name = "level2-rt1-write0"; + parent-node = <&level3_rt0_wr_sum>; + traffic-merge-type = ; + }; + }; + + level3-nodes { + level-index = <3>; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <33>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = ; + + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF 0 + &mc_virt SLAVE_EBI1 0>; + }; + }; + + level3_nrt1_rd_sum: level3-nrt1-rd-sum { + cell-index = <34>; + node-name = "level3-nrt1-rd-sum"; + traffic-merge-type = ; + + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP 0 + &mc_virt SLAVE_EBI1 0>; + }; + }; + + level3_rt0_wr_sum: level3-rt0-wr-sum { + cell-index = <35>; + node-name = "level3-rt0-wr-sum"; + traffic-merge-type = ; + ib-bw-voting-needed; + + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF 0 + &mc_virt SLAVE_EBI1 0>; + }; + }; + }; + }; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,a5", + "qcom,ipe0", + "qcom,bps"; + num-a5 = <1>; + num-ipe = <1>; + num-bps = <1>; + icp_pc_en; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + qcom,camera-main { + compatible = "qcom,camera_kt"; + status = "ok"; + }; + + qcom,cam-smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + force_cache_allocs; + status = "ok"; + + msm-cam-icp-fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&camera_mem>; + }; + + msm-cam-smmu-cpas-cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2040 0x0>; + cam-smmu-label = "cpas-cdm"; + dma-coherent; + + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x100000>; + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2000 0x20>, + <&apps_smmu 0x2020 0x20>, + <&apps_smmu 0x2062 0x0>, + <&apps_smmu 0x2080 0x20>, + <&apps_smmu 0x20A0 0x20>, + <&apps_smmu 0x2140 0x0>; + cam-smmu-label = "icp"; + dma-coherent; + + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.7 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xcf300000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-region-qdss { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x4E0>, + <&apps_smmu 0x820 0x4E0>, + <&apps_smmu 0x840 0x4E0>, + <&apps_smmu 0x860 0x4E0>, + <&apps_smmu 0x880 0x4E0>, + <&apps_smmu 0x8A0 0x4E0>, + <&apps_smmu 0x8C0 0x4E0>, + <&apps_smmu 0x8E0 0x4E0>, + <&apps_smmu 0xC00 0x4E0>, + <&apps_smmu 0xC20 0x4E0>, + <&apps_smmu 0xC40 0x4E0>, + <&apps_smmu 0xC60 0x4E0>, + <&apps_smmu 0xC80 0x4E0>, + <&apps_smmu 0xCA0 0x4E0>, + <&apps_smmu 0xCC0 0x4E0>, + <&apps_smmu 0xCE0 0x4E0>; + cam-smmu-label = "ife"; + multiple-client-devices; + dma-coherent; + + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x100000>; + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20C0 0x20>, + <&apps_smmu 0x20E0 0x20>; + cam-smmu-label = "jpeg"; + dma-coherent; + + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x100000>; + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2100 0x20>, + <&apps_smmu 0x2120 0x20>; + cam-smmu-label = "lrme"; + dma-coherent; + + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x100000>; + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac4a000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupts = ; + interrupt-names = "cci"; + operating-points-v2 = <&cci0_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 69 0>, + <&tlmm 70 0>, + <&tlmm 71 0>, + <&tlmm 72 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + cell-index = <0>; + status = "ok"; + + cci0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci0: qcom,i2c-custom-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci0: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac4b000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupts = ; + interrupt-names = "cci"; + operating-points-v2 = <&cci1_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pinctrl-0 = <&cci2_active &cci3_active>; + pinctrl-1 = <&cci2_suspend &cci3_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 73 0>, + <&tlmm 74 0>, + <&tlmm 75 0>, + <&tlmm 76 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2", + "CCI_I2C_DATA3", + "CCI_I2C_CLK3"; + cell-index = <1>; + status = "ok"; + + cci1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci1: qcom,i2c-custom-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci1: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cpas-cdm0 { + compatible = "qcom,cam170-cpas-cdm0"; + cell-index = <0>; + label = "cpas-cdm"; + reg = <0x0 0xac48000 0x0 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + clock-rates = <80000000 0>; + clock-cntl-level = "svs"; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + operating-points-v2 = <&cdm_cpas_opp_table>; + cdm-client-names = "ife0", "ife1", "ife2", + "ife3", "ife4", "dualife"; + status = "ok"; + + cdm_cpas_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csid0: qcom,csid0 { + compatible = "qcom,csid165_204"; + cell-index = <0>; + reg = <0x0 0xacb3000 0x0 0x1000>; + reg-names = "csid"; + reg-cam-base = <0xb3000>; + interrupts = ; + interrupt-names = "csid0"; + power-domains = <&camcc CAM_CC_IFE_0_GDSC>; + clocks = <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-names = "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clock-rates = <300000000 0 0 380000000 0 0>, + <400000000 0 0 510000000 0 0>, + <400000000 0 0 637000000 0 0>, + <400000000 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + operating-points-v2 = <&csid0_opp_table>; + clock-control-debugfs = "true"; + status = "ok"; + + csid0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-637000000 { + opp-hz = /bits/ 64 <637000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid1: qcom,csid1 { + compatible = "qcom,csid165_204"; + cell-index = <1>; + reg = <0x0 0xacba000 0x0 0x1000>; + reg-names = "csid"; + reg-cam-base = <0xba000>; + interrupts = ; + interrupt-names = "csid1"; + power-domains = <&camcc CAM_CC_IFE_1_GDSC>; + clocks = <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-names = "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clock-rates = <300000000 0 0 380000000 0 0>, + <400000000 0 0 510000000 0 0>, + <400000000 0 0 637000000 0 0>, + <400000000 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + operating-points-v2 = <&csid1_opp_table>; + clock-control-debugfs = "true"; + status = "ok"; + + csid1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-637000000 { + opp-hz = /bits/ 64 <637000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid2: qcom,csid2 { + compatible = "qcom,csid165_204"; + cell-index = <2>; + reg = <0x0 0x0acc1000 0x0 0x1000>; + reg-names = "csid"; + reg-cam-base = <0xc1000>; + interrupts = ; + interrupt-names = "csid2"; + power-domains = <&camcc CAM_CC_IFE_2_GDSC>; + clocks = <&camcc CAM_CC_IFE_2_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-names = "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clock-rates = <300000000 0 0 380000000 0 0>, + <400000000 0 0 510000000 0 0>, + <400000000 0 0 637000000 0 0>, + <400000000 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + operating-points-v2 = <&csid2_opp_table>; + clock-control-debugfs = "true"; + status = "ok"; + + csid2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-637000000 { + opp-hz = /bits/ 64 <637000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite0: qcom,csid-lite0 { + compatible = "qcom,csid-lite165"; + cell-index = <3>; + reg = <0x0 0xacc8000 0x0 0x1000>; + reg-names = "csid-lite"; + reg-cam-base = <0xc8000>; + interrupts = ; + interrupt-names = "csid-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_IFE_LITE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_0_CLK>; + clock-names = "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clock-rates = <300000000 0 0 320000000 0>, + <400000000 0 0 400000000 0>, + <400000000 0 0 480000000 0>, + <400000000 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + operating-points-v2 = <&csid_lite0_opp_table>; + clock-control-debugfs = "true"; + status = "ok"; + + csid_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite1: qcom,csid-lite1 { + compatible = "qcom,csid-lite165"; + cell-index = <4>; + reg = <0x0 0x0accf000 0x0 0x1000>; + reg-names = "csid-lite"; + reg-cam-base = <0xcf000>; + interrupts = ; + interrupt-names = "csid-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_IFE_LITE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_1_CLK>; + clock-names = "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clock-rates = <300000000 0 0 320000000 0>, + <400000000 0 0 400000000 0>, + <400000000 0 0 480000000 0>, + <400000000 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + operating-points-v2 = <&csid_lite1_opp_table>; + clock-control-debugfs = "true"; + status = "ok"; + + csid_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy0: qcom,csiphy0 { + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + cell-index = <0>; + reg = <0x0 0x0ace0000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe0000>; + interrupts = ; + interrupt-names = "csiphy0"; + operating-points-v2 = <&csiphy0_opp_table>; + csi-vdd-1p2-supply = <&vreg_l6b_1p2>; + csi-vdd-0p9-supply = <&vreg_l10c_0p88>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1260000 1050000>; + rgltr-load-current = <54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clock-rates = <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + clock-cntl-level = "lowsvs", "svs"; + src-clock-name = "csi0phytimer_clk_src"; + status = "ok"; + + csiphy0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x0 0xace2000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe2000>; + interrupts = ; + interrupt-names = "csiphy1"; + operating-points-v2 = <&csiphy1_opp_table>; + csi-vdd-1p2-supply = <&vreg_l6b_1p2>; + csi-vdd-0p9-supply = <&vreg_l10c_0p88>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1260000 1050000>; + rgltr-load-current = <54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + + csiphy1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x0 0xace4000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupts = ; + interrupt-names = "csiphy2"; + operating-points-v2 = <&csiphy2_opp_table>; + csi-vdd-1p2-supply = <&vreg_l6b_1p2>; + csi-vdd-0p9-supply = <&vreg_l10c_0p88>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1260000 1050000>; + rgltr-load-current = <54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + + csiphy2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x0 0xace6000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupts = ; + interrupt-names = "csiphy3"; + operating-points-v2 = <&csiphy3_opp_table>; + csi-vdd-1p2-supply = <&vreg_l6b_1p2>; + csi-vdd-0p9-supply = <&vreg_l10c_0p88>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1260000 1050000>; + rgltr-load-current = <54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + + csiphy3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + }; + + cam_csiphy4: qcom,csiphy4 { + cell-index = <4>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x0 0xace8000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupts = ; + interrupt-names = "csiphy4"; + operating-points-v2 = <&csiphy4_opp_table>; + csi-vdd-1p2-supply = <&vreg_l6b_1p2>; + csi-vdd-0p9-supply = <&vreg_l10c_0p88>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1260000 1050000>; + rgltr-load-current = <54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + + csiphy4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + }; + + cam_ipe0: qcom,ipe0 { + compatible = "qcom,cam-ipe"; + cell-index = <0>; + reg = <0x0 0xac87000 0x0 0xa000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + power-domains = <&camcc CAM_CC_IPE_0_GDSC>; + clocks = <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&camcc CAM_CC_IPE_0_CLK>; + clock-names = "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + clock-rates = <0 0 0 300000000 0>, + <0 0 0 430000000 0>, + <0 0 0 520000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + src-clock-name = "ipe_0_clk_src"; + operating-points-v2 = <&ipe0_opp_table>; + clock-control-debugfs = "true"; + status = "ok"; + + ipe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_jpeg_dma: qcom,jpegdma { + compatible = "qcom,cam_jpeg_dma_165"; + cell-index = <0>; + reg = <0x0 0xac52000 0x0 0x4000>, + <0x0 0x0ac9f000 0x0 0x10000>; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg-cam-base = <0x52000 0x9f000>; + interrupts = ; + interrupt-names = "jpegdma"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "jpegdma_clk_src", + "jpegdma_clk"; + clock-rates = <600000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "jpegdma_clk_src"; + operating-points-v2 = <&jpeg_dma_opp_table>; + cam_hw_pid = <20 21>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <2>; + status = "ok"; + + jpeg_dma_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_jpeg_enc: qcom,jpegenc { + compatible = "qcom,cam_jpeg_enc_165"; + cell-index = <0>; + reg = <0x0 0xac4e000 0x0 0x4000>, + <0x0 0x0ac9f000 0x0 0x10000>; + reg-names = "jpege_hw", "cam_camnoc"; + reg-cam-base = <0x4e000 0x9f000>; + interrupts = ; + interrupt-names = "jpeg"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "jpegenc_clk_src", + "jpegenc_clk"; + clock-rates = <600000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "jpegenc_clk_src"; + operating-points-v2 = <&jpeg_enc_opp_table>; + cam_hw_pid = <22 23>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <2>; + status = "ok"; + + jpeg_enc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_lrme: qcom,lrme { + compatible = "qcom,lrme"; + cell-index = <0>; + reg = <0x0 0xac6b000 0x0 0x1000>; + reg-names = "lrme"; + reg-cam-base = <0x6b000>; + interrupts = ; + interrupt-names = "lrme"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_LRME_CLK_SRC>, + <&camcc CAM_CC_LRME_CLK>; + clock-names = "lrme_clk_src", + "lrme_clk"; + clock-rates = <240000000 0>, + <300000000 0>, + <320000000 0>, + <400000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "lrme_clk_src"; + operating-points-v2 = <&lrme_opp_table>; + status = "ok"; + + lrme_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe0: qcom,vfe0 { + compatible = "qcom,vfe165_160"; + reg = <0x0 0xacaf000 0x0 0x5200>; + reg-names = "ife"; + reg-cam-base = <0xaf000>; + interrupts = ; + interrupt-names = "ife0"; + power-domains = <&camcc CAM_CC_IFE_0_GDSC>; + clocks = <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-names = "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clock-rates = <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + operating-points-v2 = <&vfe0_opp_table>; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <760000000>; + cam_hw_pid = <24 8>; + cell-index = <0>; + status = "ok"; + + vfe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-637000000 { + opp-hz = /bits/ 64 <637000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe1: qcom,vfe1 { + compatible = "qcom,vfe165_160"; + reg = <0x0 0xacb6000 0x0 0x5200>; + reg-names = "ife"; + reg-cam-base = <0xb6000>; + interrupts = ; + interrupt-names = "ife1"; + power-domains = <&camcc CAM_CC_IFE_1_GDSC>; + clocks = <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-names = "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clock-rates = <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + operating-points-v2 = <&vfe1_opp_table>; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <760000000>; + cam_hw_pid = <25 9>; + cell-index = <1>; + status = "ok"; + + vfe1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-637000000 { + opp-hz = /bits/ 64 <637000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + + cam_vfe2: qcom,vfe2 { + compatible = "qcom,vfe165_160"; + reg = <0x0 0x0acbd000 0x0 0x5200>; + reg-names = "ife"; + reg-cam-base = <0xbd000>; + interrupts = ; + interrupt-names = "ife2"; + power-domains = <&camcc CAM_CC_IFE_2_GDSC>; + clocks = <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-names = "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clock-rates = <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + operating-points-v2 = <&vfe2_opp_table>; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_2_DSP_CLK>; + clock-rates-option = <760000000>; + cam_hw_pid = <3 10>; + cell-index = <2>; + status = "ok"; + + vfe2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-637000000 { + opp-hz = /bits/ 64 <637000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite0: qcom,vfe-lite0 { + compatible = "qcom,vfe-lite165"; + cell-index = <3>; + reg = <0x0 0xacc4000 0x0 0x5000>; + reg-names = "ife-lite"; + reg-cam-base = <0xc4000>; + interrupts = ; + interrupt-names = "ife-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_IFE_LITE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_0_CLK>; + clock-names = "ife_clk_src", + "ife_clk"; + clock-rates = <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + operating-points-v2 = <&vfe_lite0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <11>; + status = "ok"; + + vfe_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite1: qcom,vfe-lite1 { + compatible = "qcom,vfe-lite165"; + reg = <0x0 0x0accb000 0x0 0x5000>; + reg-names = "ife-lite"; + reg-cam-base = <0xcb000>; + interrupts = ; + interrupt-names = "ife-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_IFE_LITE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_1_CLK>; + clock-names = "ife_clk_src", + "ife_clk"; + clock-rates = <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + operating-points-v2 = <&vfe_lite1_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <12>; + cell-index = <4>; + status = "ok"; + + vfe_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +}; + +&tlmm { + cam_sensor_active_mux: cam-sensor-active-mux { + /* GC630 bypass mux */ + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam-sensor-active-rst0 { + /* RESET REAR */ + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst1: cam-sensor-active-rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst2: cam-sensor-active-rst2 { + /* RESET 2 */ + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst3: cam-sensor-active-rst3 { + /* RESET 3 */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst4: cam-sensor-active-rst4 { + /* RESET 4 */ + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor-mclk0-active { + /* MCLK0 */ + mux { + pins = "gpio64"; + function = "cam_mclk"; + }; + + config { + pins = "gpio64"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam-sensor-mclk0-suspend { + /* MCLK0 */ + mux { + pins = "gpio64"; + function = "cam_mclk"; + }; + + config { + pins = "gpio64"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam-sensor-mclk1-active { + /* MCLK1 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam-sensor-mclk1-suspend { + /* MCLK1 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam-sensor-mclk2-active { + /* MCLK2 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam-sensor-mclk2-suspend { + /* MCLK2 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam-sensor-mclk3-active { + /* MCLK3 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam-sensor-mclk3-suspend { + /* MCLK3 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam-sensor-mclk4-active { + /* MCLK4 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam-sensor-mclk4-suspend { + /* MCLK4 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_active: cam-sensor-mclk5-active { + /* MCLK5 */ + mux { + pins = "gpio98"; + function = "cam_mclk"; + }; + + config { + pins = "gpio98"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam-sensor-mclk5-suspend { + /* MCLK5 */ + mux { + pins = "gpio98"; + function = "cam_mclk"; + }; + + config { + pins = "gpio98"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_mux: cam-sensor-suspend-mux { + /* GC630 bypass mux */ + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst0: cam_sensor-suspend-rst0 { + /* RESET REAR */ + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst1: cam-sensor-suspend-rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst2: cam-sensor-suspend-rst2 { + /* RESET 2 */ + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst3: cam-sensor-suspend-rst3 { + /* RESET 3 */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst4: cam-sensor-suspend-rst4 { + /* RESET 4 */ + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cci0_active: cci0-active { + mux { + /* DATA, CLK */ + pins = "gpio69","gpio70"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio69","gpio70"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0-suspend { + mux { + /* DATA, CLK */ + pins = "gpio69","gpio70"; + function = "cci_i2c"; + }; + + config { + pins = "gpio69","gpio70"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1-active { + mux { + /* DATA, CLK */ + pins = "gpio71","gpio72"; + function = "cci_i2c"; + }; + + config { + pins = "gpio71","gpio72"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1-suspend { + mux { + /* DATA, CLK */ + pins = "gpio71","gpio72"; + function = "cci_i2c"; + }; + + config { + pins = "gpio71","gpio72"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2-active { + mux { + /* DATA, CLK */ + pins = "gpio73","gpio74"; + function = "cci_i2c"; + }; + + config { + pins = "gpio73","gpio74"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2-suspend { + mux { + /* DATA, CLK */ + pins = "gpio73","gpio74"; + function = "cci_i2c"; + }; + + config { + pins = "gpio73","gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3-active { + mux { + /* DATA, CLK */ + pins = "gpio75","gpio76"; + function = "cci_i2c"; + }; + + config { + pins = "gpio75","gpio76"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3-suspend { + mux { + /* DATA, CLK */ + pins = "gpio75","gpio76"; + function = "cci_i2c"; + }; + + config { + pins = "gpio75","gpio76"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi new file mode 100644 index 0000000000000..8b75b1a441db4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi @@ -0,0 +1,551 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci0 { + //cam1 interpose on dk csi0 + actuator_rear_cam11: qcom,actuator11 { + compatible = "qcom,actuator"; + cell-index = <11>; + cci-master = <1>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear_cam11: qcom,eeprom11 { + compatible = "qcom,eeprom"; + cell-index = <11>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio", "cam_clk"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <120000 0>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 65 0>, + <&tlmm 21 0>, + <&pm7250b_gpios 3 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam0a-ov9282*/ + qcom,cam-sensor1 { + compatible = "qcom,cam-sensor"; + cell-index = <1>; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 64 0>, + <&tlmm 20 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam1-ov9282*/ + qcom,cam-sensor6 { + compatible = "qcom,cam-sensor"; + cell-index = <6>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 65 0>, + <&tlmm 21 0>, + <&pm7250b_gpios 3 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam1-imx586/imx686*/ + qcom,cam-sensor11 { + compatible = "qcom,cam-sensor"; + cell-index = <11>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_cam11>; + eeprom-src = <&eeprom_rear_cam11>; + cam_vio-supply = <&vreg_l18b_1p8>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <120000 0>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 65 0>, + <&tlmm 21 0>, + <&pm7250b_gpios 3 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + eeprom_cam2: qcom,eeprom0 { + compatible = "qcom,eeprom"; + cell-index = <8>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 66 0>, + <&tlmm 77 0>, + <&pm7250b_gpios 7 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_cam3: qcom,eeprom3 { + compatible = "qcom,eeprom"; + cell-index = <0>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 67 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + qcom,cam-power-seq-type ="cam_reset","cam_vio", + "cam_clk","cam_reset"; + qcom,cam-power-seq-val = "cam_reset","cam_vio", + "cam_mclk","cam_reset"; + qcom,cam-power-seq-cfg-val = <0 1 24000000 1>; + qcom,cam-power-seq-delay = <1 0 1 18>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam3-imx577*/ + qcom,cam-sensor0 { + compatible = "qcom,cam-sensor"; + cell-index = <0>; + csiphy-sd-index = <3>; + eeprom-src = <&eeprom_cam3>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 67 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* GMSL 1 */ + qcom,cam-sensor4 { + compatible = "qcom,cam-sensor"; + cell-index = <4>; + csiphy-sd-index = <4>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + gpios = <&tlmm 93 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + }; + + /* GMSL 2 */ + qcom,cam-sensor5 { + compatible = "qcom,cam-sensor"; + cell-index = <5>; + csiphy-sd-index = <3>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + gpios = <&tlmm 93 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_5"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + }; + + /*cam0b-ov9282*/ + qcom,cam-sensor7 { + compatible = "qcom,cam-sensor"; + cell-index = <7>; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst5>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 68 0>, + <&tlmm 149 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET5"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam2-imx577*/ + qcom,cam-sensor8 { + compatible = "qcom,cam-sensor"; + cell-index = <8>; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam2>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 66 0>, + <&tlmm 77 0>, + <&pm7250b_gpios 7 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* GMSL 3 */ + qcom,cam-sensor9 { + compatible = "qcom,cam-sensor"; + cell-index = <9>; + csiphy-sd-index = <4>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + gpios = <&tlmm 93 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_9"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + }; + + /* GMSL 4 */ + qcom,cam-sensor10 { + compatible = "qcom,cam-sensor"; + cell-index = <10>; + csiphy-sd-index = <4>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l18b_1p8>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + gpios = <&tlmm 93 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_10"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + }; +}; + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + gpios-shared-pinctrl = <640>; + shared-pctrl-gpio-names = "gmsl"; + pinctrl-0 = <&cam_sensor_active_gmsl>; + pinctrl-1 = <&cam_sensor_suspend_gmsl>; + pinctrl-names = "gmsl_active", "gmsl_suspend"; + status = "ok"; + }; +}; + +&tlmm { + cam_sensor_active_gmsl: cam-sensor-active-gmsl { + /* GMSL_ENABLE */ + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + bias-pull-up; + drive-strength = <2>; /* 2 MA */ + output-high; + }; + }; + + cam_sensor_active_rst5: cam-sensor-active-rst5 { + /* RESET 5 */ + mux { + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_gmsl: cam-sensor-suspend-gmsl { + /* GMSL_ENABLE */ + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst5: cam-sensor-suspend-rst5 { + /* RESET 5 */ + mux { + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine-camx.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine-camx.dtso new file mode 100644 index 0000000000000..eb183d7dbd3d5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine-camx.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "qcs6490-camera.dtsi" +#include "qcs6490-rb3gen2-camera-sensor.dtsi" + +&camss { + status = "disabled"; +}; + +&cci1 { + status = "disabled"; +}; From 589f14659a5302f4dbd9d1420d0fe91636fe6291 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Sun, 19 Oct 2025 11:20:50 +0530 Subject: [PATCH 0161/1330] QCLINUX: arm64: dts: qcom: Add monaco camx overlay dts Add CAMX overlay dts file for Monaco boards. This change also enables the compilation of the CAMX overlay for Monaco boards. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/Makefile | 8 + .../boot/dts/qcom/monaco-camera-sensor.dtsi | 380 +++ arch/arm64/boot/dts/qcom/monaco-camera.dtsi | 2505 +++++++++++++++++ .../dts/qcom/monaco-evk-camera-sensor.dtsi | 794 ++++++ arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso | 107 + .../boot/dts/qcom/qcs8300-ride-camx.dtso | 16 + 6 files changed, 3810 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/monaco-camera.dtsi create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso create mode 100644 arch/arm64/boot/dts/qcom/qcs8300-ride-camx.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 48432400e1332..9a4e34a2b1517 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -416,11 +416,19 @@ lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camx.dtb +monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb + qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.dtb \ qcs6490-rb3gen2-vision-mezzanine-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtb +qcs8300-ride-camx-dtbs:= qcs8300-ride.dtb qcs8300-ride-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-camx.dtb + qcs9100-ride-camx-dtbs:= qcs9100-ride.dtb sa8775p-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/monaco-camera-sensor.dtsi new file mode 100644 index 0000000000000..0023c97edce91 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-camera-sensor.dtsi @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci0 { + /* GMSL deserializer 0 */ + qcom,cam-gmsl-deserializer0 { + cell-index = <0>; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 73 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser0_port0: endpoint { + remote-endpoint = <&gmsl_sensor0_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser0_port1: endpoint { + remote-endpoint = <&gmsl_sensor1_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser0_port2: endpoint { + remote-endpoint = <&gmsl_sensor2_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser0_port3: endpoint { + remote-endpoint = <&gmsl_sensor3_ep>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 0 */ + qcom,cam-gmsl-sensor0 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <0>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor0_ep: endpoint { + remote-endpoint = <&deser0_port0>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 1 */ + qcom,cam-gmsl-sensor1 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <1>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor1_ep: endpoint { + remote-endpoint = <&deser0_port1>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 2 */ + qcom,cam-gmsl-sensor2 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <2>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor2_ep: endpoint { + remote-endpoint = <&deser0_port2>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 3 */ + qcom,cam-gmsl-sensor3 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <3>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor3_ep: endpoint { + remote-endpoint = <&deser0_port3>; + }; + }; + }; +}; + +&cam_cci1 { + /* GMSL deserializer 1 */ + qcom,cam-gmsl-deserializer1 { + cell-index = <1>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 74 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser1_port0: endpoint { + remote-endpoint = <&gmsl_sensor4_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser1_port1: endpoint { + remote-endpoint = <&gmsl_sensor5_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser1_port2: endpoint { + remote-endpoint = <&gmsl_sensor6_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser1_port3: endpoint { + remote-endpoint = <&gmsl_sensor7_ep>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 0 */ + qcom,cam-gmsl-sensor4 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <4>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor4_ep: endpoint { + remote-endpoint = <&deser1_port0>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 1 */ + qcom,cam-gmsl-sensor5 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <5>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor5_ep: endpoint { + remote-endpoint = <&deser1_port1>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 2 */ + qcom,cam-gmsl-sensor6 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <6>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor6_ep: endpoint { + remote-endpoint = <&deser1_port2>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 3 */ + qcom,cam-gmsl-sensor7 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <7>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor7_ep: endpoint { + remote-endpoint = <&deser1_port3>; + }; + }; + }; +}; + +&cam_cci2 { + /* GMSL deserializer 2 */ + qcom,cam-gmsl-deserializer2 { + cell-index = <2>; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 75 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET2"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser2_port0: endpoint { + remote-endpoint = <&gmsl_sensor8_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser2_port1: endpoint { + remote-endpoint = <&gmsl_sensor9_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser2_port2: endpoint { + remote-endpoint = <&gmsl_sensor10_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser2_port3: endpoint { + remote-endpoint = <&gmsl_sensor11_ep>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 0 */ + qcom,cam-gmsl-sensor8 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <8>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor8_ep: endpoint { + remote-endpoint = <&deser2_port0>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 1 */ + qcom,cam-gmsl-sensor9 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <9>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor9_ep: endpoint { + remote-endpoint = <&deser2_port1>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 2 */ + qcom,cam-gmsl-sensor10 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <10>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor10_ep: endpoint { + remote-endpoint = <&deser2_port2>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 3 */ + qcom,cam-gmsl-sensor11 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <11>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor11_ep: endpoint { + remote-endpoint = <&deser2_port3>; + }; + }; + }; +}; + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + gpios-shared = <518 519 520 521>; + status = "ok"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-camera.dtsi b/arch/arm64/boot/dts/qcom/monaco-camera.dtsi new file mode 100644 index 0000000000000..bd619b507831f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-camera.dtsi @@ -0,0 +1,2505 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&soc { + cam_cci0: qcom,cci0@ac13000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac13000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x13000>; + interrupts = ; + interrupt-names = "CCI0"; + operating-points-v2 = <&cci0_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + cell-index = <0>; + status = "ok"; + + cci0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci0: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci0: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac14000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac14000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x14000>; + interrupts = ; + interrupt-names = "CCI1"; + operating-points-v2 = <&cci1_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; + pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + cell-index = <1>; + status = "ok"; + + cci1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci1: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci1: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci2: qcom,cci2@ac15000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac15000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupts = ; + interrupt-names = "CCI2"; + operating-points-v2 = <&cci2_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names = "cci_2_clk_src", + "cci_2_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_2_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-0 = <&cci_i2c_scl4_active &cci_i2c_sda4_active>; + pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; + pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; + pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + cell-index = <2>; + status = "ok"; + + cci2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci2: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci2: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci2: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_100Khz_cci2: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_csiphy0: qcom,csiphy0@ac9c000 { + compatible = "qcom,csiphy-v1.3.0", "qcom,csiphy"; + reg = <0x0 0x0ac9c000 0x0 0x2000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy0_opp_table>; + reg-cam-base = <0x9c000>; + interrupts = ; + interrupt-names = "CSIPHY0"; + csi-vdd-1p2-supply = <&vreg_l5a>; + csi-vdd-0p9-supply = <&vreg_l4a>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 912000>; + rgltr-load-current = <8900 15900>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <400000000 0 400000000 0>; + cell-index = <0>; + aggregator-rx; + status = "ok"; + + csiphy0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy1: qcom,csiphy1@ac9e000 { + compatible = "qcom,csiphy-v1.3.0", "qcom,csiphy"; + reg = <0x0 0xac9e000 0x0 0x2000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy1_opp_table>; + reg-cam-base = <0x9e000>; + interrupts = ; + interrupt-names = "CSIPHY1"; + csi-vdd-1p2-supply = <&vreg_l5a>; + csi-vdd-0p9-supply = <&vreg_l4a>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 912000>; + rgltr-load-current = <8900 15900>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <400000000 0 400000000 0>; + cell-index = <1>; + aggregator-rx; + status = "ok"; + + csiphy1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy2: qcom,csiphy2@aca0000 { + compatible = "qcom,csiphy-v1.3.0", "qcom,csiphy"; + reg = <0x0 0xaca0000 0x0 0x2000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy2_opp_table>; + reg-cam-base = <0xa0000>; + interrupts = ; + interrupt-names = "CSIPHY2"; + csi-vdd-1p2-supply = <&vreg_l5a>; + csi-vdd-0p9-supply = <&vreg_l4a>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 912000>; + rgltr-load-current = <8900 15900>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <400000000 0 400000000 0>; + cell-index = <2>; + aggregator-rx; + status = "ok"; + + csiphy2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy_tpg13: qcom,tpg13@acac000 { + compatible = "qcom,cam-tpg1031"; + reg = <0x0 0xacac000 0x0 0x400>, + <0x0 0xac11000 0x0 0x1000>; + reg-names = "tpg0", "cam_cpas_top"; + reg-cam-base = <0xac000 0x11000>; + operating-points-v2 = <&csiphy_tpg0_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg0"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cphy_rx_clk_src"; + cell-index = <13>; + phy-id = <0>; + status = "ok"; + + csiphy_tpg0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy_tpg14: qcom,tpg14@acad000 { + compatible = "qcom,cam-tpg1031"; + reg = <0x0 0xacad000 0x0 0x400>, + <0x0 0xac11000 0x0 0x1000>; + reg-names = "tpg1", "cam_cpas_top"; + reg-cam-base = <0xad000 0x11000>; + operating-points-v2 = <&csiphy_tpg1_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg1"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cphy_rx_clk_src"; + cell-index = <14>; + phy-id = <1>; + status = "ok"; + + csiphy_tpg1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_csiphy_tpg15: qcom,tpg15@acae000 { + compatible = "qcom,cam-tpg1031"; + reg = <0x0 0xacae000 0x0 0x400>, + <0x0 0xac11000 0x0 0x1000>; + reg-names = "tpg2", "cam_cpas_top"; + reg-cam-base = <0xae000 0x11000>; + operating-points-v2 = <&csiphy_tpg2_opp_table>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg2"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cphy_rx_clk_src"; + cell-index = <15>; + phy-id = <2>; + status = "ok"; + + csiphy_tpg2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + qcom,cam-cpas { + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg = <0x0 0xac11000 0x0 0x1000>, + <0x0 0xac1A000 0x0 0x9400>, + <0x0 0xbbf0000 0x0 0x1f00>; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg-cam-base = <0x11000 0x1A000 0x0bbf0000>; + interrupts = ; + interrupt-names = "cpas_camnoc"; + camnoc-axi-min-ib-bw = <3000000000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "gcc_camera_sf_axi_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk", + "cam_cc_core_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "cam_cc_camnoc_axi_clk_src", + "cam_cc_camnoc_axi_clk", + "cam_cc_qdss_debug_xo_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0 0>; + clock-cntl-level = "suspend", "svs_l1", "nominal"; + clock-names-option = "cam_icp_clk"; + clocks-option = <&camcc CAM_CC_ICP_CLK>; + clock-rates-option = <480000000>; + operating-points-v2 = <&cpas_opp_table>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + cam-icc-path-names = "cam_ahb"; + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", "cam_hf_0", "cam_sf_0", "cam_sf_icp"; + cam-ahb-num-cases = <7>; + cam-ahb-bw-KBps = <0 0>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", "turbo", "turbo"; + client-id-based; + client-names = "csiphy0", "csiphy1", "csiphy2", + "cci0", "cci1", "cci2", + "csid0", "csid1", "csid2", "csid3", + "csid4", "csid5", "csid6", "ife0", + "ife1", "ife2", "ife3", "ife4", + "ife5", "ife6", "ipe0", "sfe0", "sfe1", + "cam-cdm-intf0", "rt-cdm0", "rt-cdm1", "rt-cdm2", + "rt-cdm3", "icp0", "tpg13", "tpg14", "tpg15"; + enable-secure-qos-update; + cell-index = <0>; + status = "ok"; + + cpas_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + camera-bus-nodes { + level0-nodes { + level-index = <0>; + + icp_all_rd: icp-all-rd { + cell-index = <0>; + node-name = "icp-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_icp_rd>; + }; + + ife_0_wr_0: ife-0-wr-0 { + cell-index = <1>; + node-name = "ife-0-wr-0"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_0_wr_1: ife-0-wr-1 { + cell-index = <2>; + node-name = "ife-0-wr-1"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr1>; + }; + + ife_1_wr_0: ife-1-wr-0 { + cell-index = <3>; + node-name = "ife-1-wr-0"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_1_wr_1: ife-1-wr-1 { + cell-index = <3>; + node-name = "ife-1-wr-1"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr1>; + }; + + ife_lite_0_wr_0: ife-lite-0-wr-0 { + cell-index = <4>; + node-name = "ife-lite-0-wr-0"; + client-name = "ife2"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_lite_1_wr_0: ife-lite-1-wr-0 { + cell-index = <5>; + node-name = "ife-lite-1-wr-0"; + client-name = "ife3"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_lite_2_wr_0: ife-lite-2-wr-0 { + cell-index = <6>; + node-name = "ife-lite-2-wr-0"; + client-name = "ife4"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_lite_3_wr_0: ife-lite-3-wr-0 { + cell-index = <7>; + node-name = "ife-lite-3-wr-0"; + client-name = "ife5"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ife_lite_4_wr_0: ife-lite-4-wr-0 { + cell-index = <8>; + node-name = "ife-lite-4-wr-0"; + client-name = "ife6"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_wr0>; + }; + + ipe_0_rd_all: ipe-0-rd-all { + cell-index = <9>; + node-name = "ipe-0-rd-all"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level2_nrt_rd1>; + }; + + ipe_0_wr_2: ipe-0-wr-2 { + cell-index = <10>; + node-name = "ipe-0-wr-2"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level2_nrt_wr2>; + }; + + ipe_cdm0_all_rd: ipe-cdm0-all-rd { + cell-index = <11>; + node-name = "ipe-cdm0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + rt_cdm0_all_rd_2: rt-cdm0-all-rd-2 { + cell-index = <12>; + node-name = "rt-cdm0-all-rd-2"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + rt_cdm1_all_rd_2: rt-cdm1-all-rd-2 { + cell-index = <13>; + node-name = "rt-cdm1-all-rd-2"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + rt_cdm2_all_rd_2: rt-cdm2-all-rd-2 { + cell-index = <14>; + node-name = "rt-cdm2-all-rd-2"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + rt_cdm3_all_rd_2: rt-cdm3-all-rd-2 { + cell-index = <15>; + node-name = "rt-cdm3-all-rd-2"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt_rd2>; + }; + + sfe_0_rd_0: sfe-0-rd-0 { + cell-index = <16>; + node-name = "sfe-0-rd-0"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_rd0>; + }; + + sfe_1_rd_0: sfe-1-rd-0 { + cell-index = <17>; + node-name = "sfe-1-rd-0"; + client-name = "sfe1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt_rd0>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + + level1_nrt_rd2: level1-nrt-rd2 { + cell-index = <22>; + node-name = "level1-nrt-rd2"; + parent-node = <&level2_nrt_rd2>; + traffic-merge-type = ; + }; + + level1_rt_rd0: level1-rt-read0 { + cell-index = <21>; + node-name = "level1-rt-rd0"; + parent-node = <&level2_rt_rd0>; + traffic-merge-type = ; + }; + + level1_rt_wr0: level1-rt-wr0 { + cell-index = <19>; + node-name = "level1-rt-wr0"; + parent-node = <&level2_rt_wr0>; + traffic-merge-type = ; + }; + + level1_rt_wr1: level1-rt-wr1 { + cell-index = <20>; + node-name = "level1-rt-wr1"; + parent-node = <&level2_rt_wr1>; + traffic-merge-type = ; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + + level2_icp_rd: level2-icp-rd { + cell-index = <23>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_nrt_rd1: level2-nrt-rd1 { + cell-index = <24>; + node-name = "level2-nrt-rd1"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_nrt_rd2: level2-nrt-rd2 { + cell-index = <25>; + node-name = "level2-nrt-rd2"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_nrt_wr2: level2-nrt-wr2 { + cell-index = <26>; + node-name = "level2-nrt-wr2"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_rt_rd0: level2-rt-read0 { + cell-index = <27>; + node-name = "level2-rt-rd0"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_rt_wr0: level2-rt-wr0 { + cell-index = <28>; + node-name = "level2-rt-wr0"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = ; + }; + + level2_rt_wr1: level2-rt-wr1 { + cell-index = <29>; + node-name = "level2-rt-wr1"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = ; + }; + }; + + level3-nodes { + level-index = <3>; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <30>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = ; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <31>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = ; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_icp"; + }; + }; + + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <32>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = ; + ib-bw-voting-needed; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0"; + }; + }; + }; + }; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0"; + num-icp = <1>; + num-ipe = <1>; + icp_use_pil; + status = "ok"; + }; + + qcom,cam-i3c-id-table { + compatible = "qcom,cam-i3c-id-table"; + i3c-sensor-id-table = <0x1B0 0x0766>; + i3c-eeprom-id-table = <>; + i3c-actuator-id-table = <>; + i3c-ois-id-table = <>; + status = "disabled"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,camera-main { + compatible = "qcom,camera"; + status = "ok"; + }; + + qcom,cam-smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + force_cache_allocs; + status = "ok"; + + msm-cam-smmu-cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0860 0x400>, + <&apps_smmu 0x0C60 0x400>; + cam-smmu-label = "rt-cdm"; + dma-coherent; + multiple-client-devices; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0800 0x400>, + <&apps_smmu 0x0840 0x480>, + <&apps_smmu 0x08C0 0x480>, + <&apps_smmu 0x0C00 0x400>, + <&apps_smmu 0x0C40 0x480>, + <&apps_smmu 0x0CC0 0x480>; + cam-smmu-label = "icp"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + iova-region-discard = <0xe0000000 0x800000>; + dma-coherent; + + icp_iova_mem_map: iova-mem-map { + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + iova-region-start = <0x10400000>; + iova-region-len = <0x700000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x10400000>; + iova-region-len = <0x200000>; + iova-region-id = <0x0>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 3.8 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xe0000000 0x800000>; + status = "ok"; + }; + + iova-mem-region-qdss { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is ~250MB long */ + iova-region-name = "shared"; + iova-region-start = <0x800000>; + iova-region-len = <0xfc00000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + }; + }; + + msm-cam-smmu-ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2400 0x0020>, + <&apps_smmu 0x2420 0x0020>; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + dma-coherent; + + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm-cam-smmu-secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csid0: qcom,csid0 { + compatible = "qcom,csid692"; + reg = <0x0 0xac7a000 0x0 0xf01>, + <0x0 0xac78000 0x0 0x1000>; + reg-names = "csid0", "csid_top"; + reg-cam-base = <0x7a000 0x78000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "csid0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cam_cc_csid_clk_src", + "cam_cc_csid_clk", + "cam_cc_csid_csiphy_rx_clk"; + clock-rates = <400000000 0 0>; + clock-cntl-level = "svs_l1"; + src-clock-name = "cam_cc_csid_clk_src"; + operating-points-v2 = <&csid0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "ok"; + + csid0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + cam_csid1: qcom,csid1 { + compatible = "qcom,csid692"; + reg = <0x0 0xac7c000 0x0 0xf01>, + <0x0 0xac78000 0x0 0x1000>; + reg-names = "csid1", "csid_top"; + reg-cam-base = <0x7c000 0x78000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "csid1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cam_cc_csid_clk_src", + "cam_cc_csid_clk", + "cam_cc_csid_csiphy_rx_clk"; + clock-rates = <400000000 0 0>; + clock-cntl-level = "svs_l1"; + src-clock-name = "cam_cc_csid_clk_src"; + operating-points-v2 = <&csid1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "ok"; + + csid1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + cam_csid_lite0: qcom,csid-lite0 { + compatible = "qcom,csid-lite692"; + reg = <0x0 0xac84000 0x0 0xf01>; + reg-names = "csid-lite0"; + reg-cam-base = <0x84000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "csid-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <2>; + status = "ok"; + + csid_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite1: qcom,csid-lite1 { + compatible = "qcom,csid-lite692"; + reg = <0x0 0xac88000 0x0 0xf01>; + reg-names = "csid-lite1"; + reg-cam-base = <0x88000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "csid-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <3>; + status = "ok"; + + csid_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite3: qcom,csid-lite3 { + cell-index = <5>; + compatible = "qcom,csid-lite692"; + reg-names = "csid-lite3"; + reg = <0x0 0xac90000 0x0 0xf01>; + reg-cam-base = <0x90000>; + rt-wrapper-base = <0x83000>; + interrupt-names = "csid-lite3"; + interrupts = ; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clock-names = + "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clocks = + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite3_opp_table>; + + clock-control-debugfs = "true"; + status = "ok"; + + csid_lite3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite2: qcom,csid-lite2 { + cell-index = <4>; + compatible = "qcom,csid-lite692"; + reg-names = "csid-lite2"; + reg = <0x0 0xac8c000 0x0 0xf01>; + reg-cam-base = <0x8c000>; + rt-wrapper-base = <0x83000>; + interrupt-names = "csid-lite2"; + interrupts = ; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clock-names = + "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clocks = + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite2_opp_table>; + + clock-control-debugfs = "true"; + status = "ok"; + + csid_lite2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite4: qcom,csid-lite4 { + cell-index = <6>; + compatible = "qcom,csid-lite692"; + reg-names = "csid-lite4"; + reg = <0x0 0xac94000 0x0 0xf01>; + reg-cam-base = <0x94000>; + rt-wrapper-base = <0x83000>; + interrupt-names = "csid-lite4"; + interrupts = ; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clock-names = + "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clocks = + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite4_opp_table>; + + clock-control-debugfs = "true"; + status = "ok"; + + csid_lite4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_icp: qcom,icp { + compatible = "qcom,cam-icp_v3_0"; + reg = <0x0 0xac01000 0x0 0x400>, + <0x0 0xac01800 0x0 0x400>, + <0x0 0xac04000 0x0 0x1000>; + reg-names ="icp_csr", "icp_cirq", "icp_wd0"; + reg-cam-base = <0x1000 0x1800 0x4000>; + interrupts = ; + interrupt-names = "icp"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + memory-region = <&camera_mem>; + src-clock-name = "cam_cc_icp_clk_src"; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + clock-names = "cam_cc_soc_fast_ahb_clk_src", + "cam_cc_icp_ahb_clk", + "cam_cc_icp_clk_src", + "cam_cc_icp_clk"; + clock-rates = <300000000 0 480000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + nrt-device; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + qos-val = <0xa0a>; + operating-points-v2 = <&icp_opp_table>; + icp-version = <0x0300>; + cam_hw_pid = <12>; + cell-index = <0>; + status = "ok"; + + icp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe0: qcom,ife0 { + compatible = "qcom,vfe692"; + reg = <0x0 0xac4d000 0x0 0xf000>, + <0x0 0xac1a000 0x0 0x9400>; + reg-names = "ife0", "cam_camnoc"; + reg-cam-base = <0x4d000 0x1a000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "ife0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>; + clock-names = "cam_cc_cpas_ife_0_clk", + "cam_cc_ife_0_clk", + "cam_cc_ife_0_clk_src", + "cam_cc_ife_0_fast_ahb_clk"; + clock-rates = <0 0 480000000 0>, + <0 0 600000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_0_clk_src"; + operating-points-v2 = <&vfe0_opp_table>; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <8 16>; + cell-index = <0>; + status = "ok"; + + vfe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe1: qcom,ife1 { + compatible = "qcom,vfe692"; + reg = <0x0 0xac60000 0x0 0xf000>, + <0x0 0xac1a000 0x0 0x9400>; + reg-names = "ife1", "cam_camnoc"; + reg-cam-base = <0x60000 0x1a000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "ife1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>; + clock-names = "cam_cc_cpas_ife_1_clk", + "cam_cc_ife_1_clk", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_1_fast_ahb_clk"; + clock-rates = <0 0 480000000 0>, + <0 0 600000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_1_clk_src"; + operating-points-v2 = <&vfe1_opp_table>; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <9 17>; + cell-index = <1>; + status = "ok"; + + vfe1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite0: qcom,ife-lite0 { + compatible = "qcom,vfe-lite692"; + reg = <0x0 0xac84000 0x0 0x1d00>; + reg-names = "ife-lite0"; + reg-cam-base = <0x84000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <2>; + status = "ok"; + + vfe_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite1: qcom,ife-lite1 { + compatible = "qcom,vfe-lite692"; + reg = <0x0 0xac88000 0x0 0x1d00>; + reg-names = "ife-lite1"; + reg-cam-base = <0x88000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite1_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <3>; + status = "ok"; + + vfe_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite2: qcom,ife-lite2 { + compatible = "qcom,vfe-lite692"; + reg = <0x0 0xac8c000 0x0 0x1d00>; + reg-names = "ife-lite2"; + reg-cam-base = <0x8c000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite2_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <4>; + status = "ok"; + + vfe_lite2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite3: qcom,ife-lite3 { + compatible = "qcom,vfe-lite692"; + reg = <0x0 0xac90000 0x0 0x1d00>; + reg-names = "ife-lite3"; + reg-cam-base = <0x90000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite3"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite3_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <5>; + status = "ok"; + + vfe_lite3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite4: qcom,ife-lite4 { + compatible = "qcom,vfe-lite692"; + reg = <0x0 0xac94000 0x0 0x1d00>; + reg-names = "ife-lite4"; + reg-cam-base = <0x94000>; + rt-wrapper-base = <0x83000>; + interrupts = ; + interrupt-names = "ife-lite4"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite4_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + cell-index = <6>; + status = "ok"; + + vfe_lite4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_ipe0: qcom,ipe0 { + compatible = "qcom,cam-ipe"; + reg = <0x0 0xac2d000 0x0 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x2d000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + src-clock-name = "cam_cc_ipe_clk_src"; + clocks = <&camcc CAM_CC_CPAS_IPE_CLK>, + <&camcc CAM_CC_IPE_AHB_CLK>, + <&camcc CAM_CC_IPE_CLK>, + <&camcc CAM_CC_IPE_CLK_SRC>, + <&camcc CAM_CC_IPE_FAST_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>; + clock-names = "cam_cc_cpas_ipe_clk", + "cam_cc_ipe_ahb_clk", + "cam_cc_ipe_clk", + "cam_cc_ipe_clk_src", + "cam_cc_ipe_fast_ahb_clk", + "cam_cc_fast_ahb_clk_src"; + clock-rates = <0 0 0 480000000 0 300000000>, + <0 0 0 600000000 0 400000000>; + clock-cntl-level = "svs_l1", "nominal"; + operating-points-v2 = <&ipe0_opp_table>; + nrt-device; + cam_hw_pid = <14 15>; + cell-index = <0>; + status = "ok"; + + ipe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm0 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac26000 0x0 0x1000>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x26000>; + interrupts = ; + interrupt-names = "rt-cdm0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <300000000 0>; + operating-points-v2 = <&cdm_cpas_opp_table0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife0", "dualife0"; + single-context-cdm; + cell-index = <0>; + status = "ok"; + + cdm_cpas_opp_table0: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + qcom,rt-cdm1 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac27000 0x0 0x1000>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x27000>; + interrupts = ; + interrupt-names = "rt-cdm1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <300000000 0>; + operating-points-v2 = <&cdm_cpas_opp_table1>; + clock-cntl-level = "svs_l1"; + cdm-client-names = "ife1", "dualife1"; + single-context-cdm; + cell-index = <1>; + status = "ok"; + + cdm_cpas_opp_table1: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + qcom,rt-cdm2 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac28000 0x0 0x1000>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x28000>; + interrupts = ; + interrupt-names = "rt-cdm2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-rates = <80000000 0>; + operating-points-v2 = <&cdm_cpas_opp_table2>; + clock-cntl-level = "svs_l1"; + cdm-client-names = "ife2", "ife3", "ife4", "ife5", "ife6"; + single-context-cdm; + cell-index = <2>; + status = "ok"; + + cdm_cpas_opp_table2: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + qcom,rt-cdm3 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac29000 0x0 0x1000>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x29000>; + interrupts = ; + interrupt-names = "rt-cdm3"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-rates = <80000000 0>; + operating-points-v2 = <&cdm_cpas_opp_table3>; + clock-cntl-level = "svs"; + cdm-client-names = "ife2", "ife3", "ife4", "ife5", "ife6"; + single-context-cdm; + cell-index = <3>; + status = "ok"; + + cdm_cpas_opp_table3: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_sfe_lite0: qcom,sfe-lite0 { + compatible = "qcom,sfe-lite692"; + reg = <0x0 0xac74000 0x0 0x1000>; + reg-names = "sfe-lite0"; + reg-cam-base = <0x74000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "sfe-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SFE_LITE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_LITE_0_CLK>, + <&camcc CAM_CC_CPAS_SFE_LITE_0_CLK>; + clock-names = "cam_cc_sfe_lite_0_fast_ahb_clk", + "cam_cc_sfe_lite_0_clk", + "cam_cc_cpas_sfe_lite_0_clk"; + clock-rates = <0 480000000 300000000>, + <0 600000000 400000000>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_sfe_lite_0_clk"; + operating-points-v2 = <&cam_sfe_lite_opp_table0>; + cam_hw_pid = <4>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "ok"; + + cam_sfe_lite_opp_table0: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_sfe_lite1: qcom,sfe-lite1 { + compatible = "qcom,sfe-lite692"; + reg = <0x0 0xac75000 0x0 0x1000>; + reg-names = "sfe-lite1"; + reg-cam-base = <0x75000>; + rt-wrapper-base = <0x4d000>; + interrupts = ; + interrupt-names = "sfe-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SFE_LITE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_LITE_1_CLK>, + <&camcc CAM_CC_CPAS_SFE_LITE_1_CLK>; + clock-names = "cam_cc_sfe_lite_1_fast_ahb_clk", + "cam_cc_sfe_lite_1_clk", + "cam_cc_cpas_sfe_1_clk"; + clock-rates = <0 480000000 300000000>, + <0 600000000 400000000>; + clock-cntl-level = "svs_l1", "nominal"; + src-clock-name = "cam_cc_sfe_lite_1_clk"; + operating-points-v2 = <&cam_sfe_lite_opp_table1>; + cam_hw_pid = <5>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "ok"; + + cam_sfe_lite_opp_table1: opp-table { + compatible = "operating-points-v2"; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +}; + +&tlmm { + cam_sensor_mclk0_active: cam-sensor-mclk0-active { + /* MCLK0 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam-sensor-mclk0-suspend { + /* MCLK0 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam-sensor-mclk1-active { + /* MCLK1 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam-sensor-mclk1-suspend { + /* MCLK1 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam-sensor-mclk2-active { + /* MCLK2 */ + mux { + pins = "gpio69"; + function = "cam_mclk"; + }; + + config { + pins = "gpio69"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam-sensor-mclk2-suspend { + /* MCLK2 */ + mux { + pins = "gpio69"; + function = "cam_mclk"; + }; + + config { + pins = "gpio69"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci-i2c-scl0-active { + mux { + /* CLK, DATA */ + pins = "gpio58"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio58"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl0_suspend: cci-i2c-scl0-suspend { + mux { + /* CLK, DATA */ + pins = "gpio58"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio58"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci-i2c-scl1-active { + mux { + /* CLK, DATA */ + pins = "gpio30"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio30"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl1_suspend: cci-i2c-scl1-suspend { + mux { + /* CLK, DATA */ + pins = "gpio30"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci-i2c-scl2-active { + mux { + /* CLK, DATA */ + pins = "gpio60"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio60"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl2_suspend: cci-i2c-scl2-suspend { + mux { + /* CLK, DATA */ + pins = "gpio60"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio60"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl3_active: cci-i2c-scl3-active { + mux { + pins = "gpio32"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio32"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl3_suspend: cci-i2c-scl3-suspend { + mux { + pins = "gpio32"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl4_active: cci-i2c-scl4-active { + mux { + /* CLK, DATA */ + pins = "gpio62"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio62"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl4_suspend: cci-i2c-scl4-suspend { + mux { + /* CLK, DATA */ + pins = "gpio62"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio62"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl5_active: cci-i2c-scl5-active { + mux { + /* CLK, DATA */ + pins = "gpio55"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio55"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl5_suspend: cci-i2c-scl5-suspend { + mux { + /* CLK, DATA */ + pins = "gpio55"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio55"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda0_active: cci-i2c-sda0-active { + mux { + /* CLK, DATA */ + pins = "gpio57"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio57"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda0_suspend: cci-i2c-sda0-suspend { + mux { + /* CLK, DATA */ + pins = "gpio57"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio57"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci-i2c-sda1-active { + mux { + /* CLK, DATA */ + pins = "gpio29"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio29"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda1_suspend: cci-i2c-sda1-suspend { + mux { + /* CLK, DATA */ + pins = "gpio29"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci-i2c-sda2-active { + mux { + /* CLK, DATA */ + pins = "gpio59"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio59"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda2_suspend: cci-i2c-sda2-suspend { + mux { + /* CLK, DATA */ + pins = "gpio59"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio59"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda3_active: cci-i2c-sda3-active { + mux { + pins = "gpio31"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio31"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda3_suspend: cci-i2c-sda3-suspend { + mux { + pins = "gpio31"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio31"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda4_active: cci-i2c-sda4-active { + mux { + /* CLK, DATA */ + pins = "gpio61"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio61"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda4_suspend: cci-i2c-sda4-suspend { + mux { + /* CLK, DATA */ + pins = "gpio61"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio61"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda5_active: cci-i2c-sda5-active { + mux { + /* CLK, DATA */ + pins = "gpio54"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio54"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda5_suspend: cci-i2c-sda5-suspend { + mux { + /* CLK, DATA */ + pins = "gpio54"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio54"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/monaco-evk-camera-sensor.dtsi new file mode 100644 index 0000000000000..167b85c0e8844 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camera-sensor.dtsi @@ -0,0 +1,794 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci0 { + /* GMSL deserializer 0 */ + qcom,cam-gmsl-deserializer0 { + cell-index = <0>; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 73 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser0_port0: endpoint { + remote-endpoint = <&gmsl_sensor0_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser0_port1: endpoint { + remote-endpoint = <&gmsl_sensor1_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser0_port2: endpoint { + remote-endpoint = <&gmsl_sensor2_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser0_port3: endpoint { + remote-endpoint = <&gmsl_sensor3_ep>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 0 */ + qcom,cam-gmsl-sensor0 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <0>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor0_ep: endpoint { + remote-endpoint = <&deser0_port0>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 1 */ + qcom,cam-gmsl-sensor1 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <1>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor1_ep: endpoint { + remote-endpoint = <&deser0_port1>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 2 */ + qcom,cam-gmsl-sensor2 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <2>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor2_ep: endpoint { + remote-endpoint = <&deser0_port2>; + }; + }; + }; + + /* GMSL deserializer 0 sensor 3 */ + qcom,cam-gmsl-sensor3 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <3>; + csiphy-sd-index = <0>; + status = "ok"; + + port { + gmsl_sensor3_ep: endpoint { + remote-endpoint = <&deser0_port3>; + }; + }; + }; + + /*cam0-ov9282*/ + rb4_slot0: qcom,cam-sensor16 { + compatible = "qcom,cam-sensor"; + cell-index = <16>; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 67 0>, + <&tlmm 73 0>, + <&expander2 0 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK0", + "CAMIF_RESET0", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam0-imx577*/ + qcom,cam-sensor20 { + compatible = "qcom,cam-sensor"; + cell-index = <20>; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam20>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 67 0>, + <&tlmm 73 0>, + <&expander2 0 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK0", + "CAMIF_RESET0", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_cam20: qcom,eeprom20 { + cell-index = <20>; + compatible = "qcom,eeprom"; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 67 0>, + <&tlmm 73 0>, + <&expander2 0 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK0", + "CAMIF_RESET0", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + /* GMSL deserializer 1 */ + qcom,cam-gmsl-deserializer1 { + cell-index = <1>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 74 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser1_port0: endpoint { + remote-endpoint = <&gmsl_sensor4_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser1_port1: endpoint { + remote-endpoint = <&gmsl_sensor5_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser1_port2: endpoint { + remote-endpoint = <&gmsl_sensor6_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser1_port3: endpoint { + remote-endpoint = <&gmsl_sensor7_ep>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 0 */ + qcom,cam-gmsl-sensor4 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <4>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor4_ep: endpoint { + remote-endpoint = <&deser1_port0>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 1 */ + qcom,cam-gmsl-sensor5 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <5>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor5_ep: endpoint { + remote-endpoint = <&deser1_port1>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 2 */ + qcom,cam-gmsl-sensor6 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <6>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor6_ep: endpoint { + remote-endpoint = <&deser1_port2>; + }; + }; + }; + + /* GMSL deserializer 1 sensor 3 */ + qcom,cam-gmsl-sensor7 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <7>; + csiphy-sd-index = <1>; + status = "ok"; + + port { + gmsl_sensor7_ep: endpoint { + remote-endpoint = <&deser1_port3>; + }; + }; + }; + + /*cam1-ov9282*/ + rb4_slot1: qcom,cam-sensor17 { + compatible = "qcom,cam-sensor"; + cell-index = <17>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 68 0>, + <&tlmm 74 0>, + <&expander2 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam0-imx577*/ + qcom,cam-sensor19 { + compatible = "qcom,cam-sensor"; + cell-index = <19>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam19>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 68 0>, + <&tlmm 74 0>, + <&expander2 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam0-imx577*/ + qcom,cam-sensor21 { + compatible = "qcom,cam-sensor"; + cell-index = <21>; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam21>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 68 0>, + <&tlmm 74 0>, + <&expander2 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_cam19: qcom,eeprom19 { + compatible = "qcom,eeprom"; + cell-index = <19>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 68 0>, + <&tlmm 74 0>, + <&expander2 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_cam21: qcom,eeprom21 { + compatible = "qcom,eeprom"; + cell-index = <21>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 68 0>, + <&tlmm 74 0>, + <&expander2 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci2 { + /* GMSL deserializer 2 */ + qcom,cam-gmsl-deserializer2 { + cell-index = <2>; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 75 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET2"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + + port@0 { + reg = <0>; + + deser2_port0: endpoint { + remote-endpoint = <&gmsl_sensor8_ep>; + }; + }; + + port@1 { + reg = <1>; + + deser2_port1: endpoint { + remote-endpoint = <&gmsl_sensor9_ep>; + }; + }; + + port@2 { + reg = <0>; + + deser2_port2: endpoint { + remote-endpoint = <&gmsl_sensor10_ep>; + }; + }; + + port@3 { + reg = <1>; + + deser2_port3: endpoint { + remote-endpoint = <&gmsl_sensor11_ep>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 0 */ + qcom,cam-gmsl-sensor8 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <8>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor8_ep: endpoint { + remote-endpoint = <&deser2_port0>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 1 */ + qcom,cam-gmsl-sensor9 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <9>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor9_ep: endpoint { + remote-endpoint = <&deser2_port1>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 2 */ + qcom,cam-gmsl-sensor10 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <10>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor10_ep: endpoint { + remote-endpoint = <&deser2_port2>; + }; + }; + }; + + /* GMSL deserializer 2 sensor 3 */ + qcom,cam-gmsl-sensor11 { + compatible = "qcom,cam-gmsl-sensor"; + cell-index = <11>; + csiphy-sd-index = <2>; + status = "ok"; + + port { + gmsl_sensor11_ep: endpoint { + remote-endpoint = <&deser2_port3>; + }; + }; + }; + + /*cam2-ov9282*/ + rb4_slot2: qcom,cam-sensor18 { + compatible = "qcom,cam-sensor"; + cell-index = <18>; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 69 0>, + <&tlmm 75 0>, + <&expander2 2 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK2", + "CAMIF_RESET2", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /*cam2-imx577*/ + qcom,cam-sensor22 { + compatible = "qcom,cam-sensor"; + cell-index = <22>; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam22>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 69 0>, + <&tlmm 75 0>, + <&expander2 2 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK2", + "CAMIF_RESET2", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_cam22: qcom,eeprom22 { + compatible = "qcom,eeprom"; + cell-index = <22>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 69 0>, + <&tlmm 75 0>, + <&expander2 2 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK2", + "CAMIF_RESET2", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + gpios-shared = <609 610 611>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso new file mode 100644 index 0000000000000..3945c77528ccb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "monaco-camera.dtsi" +#include "monaco-evk-camera-sensor.dtsi" + +&camss { + status = "disabled"; +}; + +&tlmm { + cam_sensor_active_rst0: cam-sensor-active-rst0 { + /* RESET */ + mux { + pins = "gpio73"; + function = "gpio"; + }; + + config { + pins = "gpio73"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst1: cam-sensor-active-rst1 { + /* RESET */ + mux { + pins = "gpio74"; + function = "gpio"; + }; + + config { + pins = "gpio74"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst2: cam-sensor-active-rst2 { + /* RESET */ + mux { + pins = "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio75"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam-sensor-suspend-rst0 { + /* RESET */ + mux { + pins = "gpio73"; + function = "gpio"; + }; + + config { + pins = "gpio73"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst1: cam-sensor-suspend-rst1 { + /* RESET */ + mux { + pins = "gpio74"; + function = "gpio"; + }; + config { + pins = "gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst2: cam-sensor-suspend-rst2 { + /* RESET */ + mux { + pins = "gpio75"; + function = "gpio"; + }; + config { + pins = "gpio75"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride-camx.dtso b/arch/arm64/boot/dts/qcom/qcs8300-ride-camx.dtso new file mode 100644 index 0000000000000..8f26e6dc070b0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride-camx.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "monaco-camera.dtsi" +#include "monaco-camera-sensor.dtsi" From e342df5b472bff99ffb7c07b1c7bc82a1d29b965 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Thu, 30 Oct 2025 00:58:58 +0530 Subject: [PATCH 0162/1330] PENDING: arm64: dts: qcom: qcs8300: Update camera PIL region to 7MB The camera firmware size for IoT variant qcs8300 SoC is more than 5MB. Update the PIL memory region size of camera to 7MB to accomodate the same. Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 37d0515e88936..1d7fbc34c3135 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -781,7 +781,7 @@ }; camera_mem: camera-region@95200000 { - reg = <0x0 0x95200000 0x0 0x500000>; + reg = <0x0 0x95200000 0x0 0x700000>; no-map; }; From 6cf6e1e49fe3be1016b7ba09c45fb9b1643642e1 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 27 Oct 2025 23:48:22 +0530 Subject: [PATCH 0163/1330] QCLINUX: arm64: dts: qcom: Update rbgen2 camx overlay dts - Fix the indentation issue. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi index f6af6827784bd..37ea48e35d09c 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi @@ -620,8 +620,8 @@ qcom,cam-icp { compatible = "qcom,cam-icp"; compat-hw-name = "qcom,a5", - "qcom,ipe0", - "qcom,bps"; + "qcom,ipe0", + "qcom,bps"; num-a5 = <1>; num-ipe = <1>; num-bps = <1>; @@ -643,7 +643,7 @@ qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; compat-hw-name = "qcom,jpegenc", - "qcom,jpegdma"; + "qcom,jpegdma"; num-jpeg-enc = <1>; num-jpeg-dma = <1>; status = "ok"; From 1b6f93abe4fb95c297b72547c26f391909983200 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 27 Oct 2025 23:42:23 +0530 Subject: [PATCH 0164/1330] QCLINUX: arm64: dts: qcom: Update Monaco camx overlay dts - Fix the indentation issue. - Update DT clock property name after clock. - Short DT nodes. - Fix indexing issue. - Update gpios shared pin. Signed-off-by: Chandan Kumar Jha --- .../boot/dts/qcom/monaco-camera-sensor.dtsi | 2 +- arch/arm64/boot/dts/qcom/monaco-camera.dtsi | 204 +++++++++--------- 2 files changed, 100 insertions(+), 106 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/monaco-camera-sensor.dtsi index 0023c97edce91..a2a2cd0a27a3a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-camera-sensor.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-camera-sensor.dtsi @@ -374,7 +374,7 @@ &soc { qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; - gpios-shared = <518 519 520 521>; + gpios-shared = <609 610 611>; status = "ok"; }; }; diff --git a/arch/arm64/boot/dts/qcom/monaco-camera.dtsi b/arch/arm64/boot/dts/qcom/monaco-camera.dtsi index bd619b507831f..f72161e75f7e7 100644 --- a/arch/arm64/boot/dts/qcom/monaco-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-camera.dtsi @@ -565,8 +565,8 @@ "cam_cc_qdss_debug_xo_clk"; src-clock-name = "cam_cc_fast_ahb_clk_src"; clock-rates = <0 0 0 0 0 0 0 0 0 0 0>, - <0 0 0 80000000 0 0 300000000 0 400000000 0 0>, - <0 0 0 80000000 0 0 400000000 0 400000000 0 0>; + <0 0 0 80000000 0 0 300000000 0 400000000 0 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0 0>; clock-cntl-level = "suspend", "svs_l1", "nominal"; clock-names-option = "cam_icp_clk"; clocks-option = <&camcc CAM_CC_ICP_CLK>; @@ -679,7 +679,7 @@ }; ife_1_wr_1: ife-1-wr-1 { - cell-index = <3>; + cell-index = <4>; node-name = "ife-1-wr-1"; client-name = "ife1"; traffic-data = ; @@ -693,7 +693,7 @@ }; ife_lite_0_wr_0: ife-lite-0-wr-0 { - cell-index = <4>; + cell-index = <5>; node-name = "ife-lite-0-wr-0"; client-name = "ife2"; traffic-data = ; @@ -707,7 +707,7 @@ }; ife_lite_1_wr_0: ife-lite-1-wr-0 { - cell-index = <5>; + cell-index = <6>; node-name = "ife-lite-1-wr-0"; client-name = "ife3"; traffic-data = ; @@ -721,7 +721,7 @@ }; ife_lite_2_wr_0: ife-lite-2-wr-0 { - cell-index = <6>; + cell-index = <7>; node-name = "ife-lite-2-wr-0"; client-name = "ife4"; traffic-data = ; @@ -735,7 +735,7 @@ }; ife_lite_3_wr_0: ife-lite-3-wr-0 { - cell-index = <7>; + cell-index = <8>; node-name = "ife-lite-3-wr-0"; client-name = "ife5"; traffic-data = ; @@ -749,7 +749,7 @@ }; ife_lite_4_wr_0: ife-lite-4-wr-0 { - cell-index = <8>; + cell-index = <9>; node-name = "ife-lite-4-wr-0"; client-name = "ife6"; traffic-data = ; @@ -763,7 +763,7 @@ }; ipe_0_rd_all: ipe-0-rd-all { - cell-index = <9>; + cell-index = <10>; node-name = "ipe-0-rd-all"; client-name = "ipe0"; traffic-data = ; @@ -774,7 +774,7 @@ }; ipe_0_wr_2: ipe-0-wr-2 { - cell-index = <10>; + cell-index = <11>; node-name = "ipe-0-wr-2"; client-name = "ipe0"; traffic-data = ; @@ -787,7 +787,7 @@ }; ipe_cdm0_all_rd: ipe-cdm0-all-rd { - cell-index = <11>; + cell-index = <12>; node-name = "ipe-cdm0-all-rd"; client-name = "ipe0"; traffic-data = ; @@ -796,7 +796,7 @@ }; rt_cdm0_all_rd_2: rt-cdm0-all-rd-2 { - cell-index = <12>; + cell-index = <13>; node-name = "rt-cdm0-all-rd-2"; client-name = "rt-cdm0"; traffic-data = ; @@ -805,7 +805,7 @@ }; rt_cdm1_all_rd_2: rt-cdm1-all-rd-2 { - cell-index = <13>; + cell-index = <14>; node-name = "rt-cdm1-all-rd-2"; client-name = "rt-cdm1"; traffic-data = ; @@ -814,7 +814,7 @@ }; rt_cdm2_all_rd_2: rt-cdm2-all-rd-2 { - cell-index = <14>; + cell-index = <15>; node-name = "rt-cdm2-all-rd-2"; client-name = "rt-cdm2"; traffic-data = ; @@ -823,7 +823,7 @@ }; rt_cdm3_all_rd_2: rt-cdm3-all-rd-2 { - cell-index = <15>; + cell-index = <16>; node-name = "rt-cdm3-all-rd-2"; client-name = "rt-cdm3"; traffic-data = ; @@ -832,7 +832,7 @@ }; sfe_0_rd_0: sfe-0-rd-0 { - cell-index = <16>; + cell-index = <17>; node-name = "sfe-0-rd-0"; client-name = "sfe0"; traffic-data = ; @@ -842,7 +842,7 @@ }; sfe_1_rd_0: sfe-1-rd-0 { - cell-index = <17>; + cell-index = <18>; node-name = "sfe-1-rd-0"; client-name = "sfe1"; traffic-data = ; @@ -857,28 +857,28 @@ camnoc-max-needed; level1_nrt_rd2: level1-nrt-rd2 { - cell-index = <22>; + cell-index = <19>; node-name = "level1-nrt-rd2"; parent-node = <&level2_nrt_rd2>; traffic-merge-type = ; }; level1_rt_rd0: level1-rt-read0 { - cell-index = <21>; + cell-index = <20>; node-name = "level1-rt-rd0"; parent-node = <&level2_rt_rd0>; traffic-merge-type = ; }; level1_rt_wr0: level1-rt-wr0 { - cell-index = <19>; + cell-index = <21>; node-name = "level1-rt-wr0"; parent-node = <&level2_rt_wr0>; traffic-merge-type = ; }; level1_rt_wr1: level1-rt-wr1 { - cell-index = <20>; + cell-index = <22>; node-name = "level1-rt-wr1"; parent-node = <&level2_rt_wr1>; traffic-merge-type = ; @@ -978,8 +978,7 @@ qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp", - "qcom,ipe0"; + compat-hw-name = "qcom,icp", "qcom,ipe0"; num-icp = <1>; num-ipe = <1>; icp_use_pil; @@ -1023,6 +1022,7 @@ cam-smmu-label = "rt-cdm"; dma-coherent; multiple-client-devices; + rt_cdm_iova_mem_map: iova-mem-map { iova-mem-region-io { /* IO region is approximately 4.0 GB */ @@ -1059,6 +1059,7 @@ iova-region-id = <0x6>; subregion_support; status = "ok"; + /* Used for HFI queues/sec heap */ iova-mem-region-generic-region { iova-region-name = "icp_hfi"; @@ -1096,7 +1097,6 @@ iova-region-id = <0x1>; status = "ok"; }; - }; }; @@ -1298,49 +1298,46 @@ }; }; - cam_csid_lite3: qcom,csid-lite3 { - cell-index = <5>; + cam_csid_lite2: qcom,csid-lite2 { compatible = "qcom,csid-lite692"; - reg-names = "csid-lite3"; - reg = <0x0 0xac90000 0x0 0xf01>; - reg-cam-base = <0x90000>; + reg = <0x0 0xac8c000 0x0 0xf01>; + reg-names = "csid-lite2"; + reg-cam-base = <0x8c000>; rt-wrapper-base = <0x83000>; - interrupt-names = "csid-lite3"; - interrupts = ; + interrupts = ; + interrupt-names = "csid-lite2"; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - clock-names = - "cam_cc_cpas_ife_lite_clk", - "cam_cc_ife_lite_ahb_clk", - "cam_cc_ife_lite_csid_clk_src", - "cam_cc_ife_lite_csid_clk", - "cam_cc_ife_lite_cphy_rx_clk", - "cam_cc_ife_lite_clk_src", - "cam_cc_ife_lite_clk"; - clocks = - <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, - <&camcc CAM_CC_IFE_LITE_AHB_CLK>, - <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, - <&camcc CAM_CC_IFE_LITE_CSID_CLK>, - <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, - <&camcc CAM_CC_IFE_LITE_CLK_SRC>, - <&camcc CAM_CC_IFE_LITE_CLK>; - clock-rates = - <0 0 400000000 0 0 400000000 0>, - <0 0 400000000 0 0 480000000 0>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; clock-cntl-level = "svs_l1", "nominal"; src-clock-name = "cam_cc_ife_lite_csid_clk_src"; - operating-points-v2 = <&csid_lite3_opp_table>; - + operating-points-v2 = <&csid_lite2_opp_table>; clock-control-debugfs = "true"; + cell-index = <4>; status = "ok"; - csid_lite3_opp_table: opp-table { + csid_lite2_opp_table: opp-table { compatible = "operating-points-v2"; opp-400000000 { opp-hz = /bits/ 64 <400000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; + opp-480000000 { opp-hz = /bits/ 64 <480000000>; required-opps = <&rpmhpd_opp_nom>; @@ -1348,49 +1345,46 @@ }; }; - cam_csid_lite2: qcom,csid-lite2 { - cell-index = <4>; + cam_csid_lite3: qcom,csid-lite3 { compatible = "qcom,csid-lite692"; - reg-names = "csid-lite2"; - reg = <0x0 0xac8c000 0x0 0xf01>; - reg-cam-base = <0x8c000>; + reg = <0x0 0xac90000 0x0 0xf01>; + reg-names = "csid-lite3"; + reg-cam-base = <0x90000>; rt-wrapper-base = <0x83000>; - interrupt-names = "csid-lite2"; - interrupts = ; + interrupts = ; + interrupt-names = "csid-lite3"; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - clock-names = - "cam_cc_cpas_ife_lite_clk", - "cam_cc_ife_lite_ahb_clk", - "cam_cc_ife_lite_csid_clk_src", - "cam_cc_ife_lite_csid_clk", - "cam_cc_ife_lite_cphy_rx_clk", - "cam_cc_ife_lite_clk_src", - "cam_cc_ife_lite_clk"; - clocks = - <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, - <&camcc CAM_CC_IFE_LITE_AHB_CLK>, - <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, - <&camcc CAM_CC_IFE_LITE_CSID_CLK>, - <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, - <&camcc CAM_CC_IFE_LITE_CLK_SRC>, - <&camcc CAM_CC_IFE_LITE_CLK>; - clock-rates = - <0 0 400000000 0 0 400000000 0>, - <0 0 400000000 0 0 480000000 0>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; clock-cntl-level = "svs_l1", "nominal"; src-clock-name = "cam_cc_ife_lite_csid_clk_src"; - operating-points-v2 = <&csid_lite2_opp_table>; - + operating-points-v2 = <&csid_lite3_opp_table>; clock-control-debugfs = "true"; + cell-index = <5>; status = "ok"; - csid_lite2_opp_table: opp-table { + csid_lite3_opp_table: opp-table { compatible = "operating-points-v2"; opp-400000000 { opp-hz = /bits/ 64 <400000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; + opp-480000000 { opp-hz = /bits/ 64 <480000000>; required-opps = <&rpmhpd_opp_nom>; @@ -1399,39 +1393,35 @@ }; cam_csid_lite4: qcom,csid-lite4 { - cell-index = <6>; compatible = "qcom,csid-lite692"; - reg-names = "csid-lite4"; reg = <0x0 0xac94000 0x0 0xf01>; + reg-names = "csid-lite4"; reg-cam-base = <0x94000>; rt-wrapper-base = <0x83000>; - interrupt-names = "csid-lite4"; interrupts = ; + interrupt-names = "csid-lite4"; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - clock-names = - "cam_cc_cpas_ife_lite_clk", - "cam_cc_ife_lite_ahb_clk", - "cam_cc_ife_lite_csid_clk_src", - "cam_cc_ife_lite_csid_clk", - "cam_cc_ife_lite_cphy_rx_clk", - "cam_cc_ife_lite_clk_src", - "cam_cc_ife_lite_clk"; - clocks = - <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, - <&camcc CAM_CC_IFE_LITE_AHB_CLK>, - <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, - <&camcc CAM_CC_IFE_LITE_CSID_CLK>, - <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, - <&camcc CAM_CC_IFE_LITE_CLK_SRC>, - <&camcc CAM_CC_IFE_LITE_CLK>; - clock-rates = - <0 0 400000000 0 0 400000000 0>, - <0 0 400000000 0 0 480000000 0>; + clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; + clock-rates = <0 0 400000000 0 0 400000000 0>, + <0 0 400000000 0 0 480000000 0>; clock-cntl-level = "svs_l1", "nominal"; src-clock-name = "cam_cc_ife_lite_csid_clk_src"; operating-points-v2 = <&csid_lite4_opp_table>; - clock-control-debugfs = "true"; + cell-index = <6>; status = "ok"; csid_lite4_opp_table: opp-table { @@ -1441,6 +1431,7 @@ opp-hz = /bits/ 64 <400000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; + opp-480000000 { opp-hz = /bits/ 64 <480000000>; required-opps = <&rpmhpd_opp_nom>; @@ -1489,6 +1480,7 @@ opp-hz = /bits/ 64 <480000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; + opp-600000000 { opp-hz = /bits/ 64 <600000000>; required-opps = <&rpmhpd_opp_nom>; @@ -1532,6 +1524,7 @@ opp-hz = /bits/ 64 <480000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; + opp-600000000 { opp-hz = /bits/ 64 <600000000>; required-opps = <&rpmhpd_opp_nom>; @@ -1575,6 +1568,7 @@ opp-hz = /bits/ 64 <480000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; + opp-600000000 { opp-hz = /bits/ 64 <600000000>; required-opps = <&rpmhpd_opp_nom>; From 092f39434231ae63143d163c6296ca24679ff09b Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 27 Oct 2025 23:36:51 +0530 Subject: [PATCH 0165/1330] QCLINUX: arm64: dts: qcom: Update Lemans camx overlay dts - Fix the indentation issue. - Update DT clock property name after clock. - Shorted DT nodes. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/lemans-camera.dtsi | 43 +++++++++------------ 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-camera.dtsi b/arch/arm64/boot/dts/qcom/lemans-camera.dtsi index 18d78926b1f17..855d29dff618f 100644 --- a/arch/arm64/boot/dts/qcom/lemans-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-camera.dtsi @@ -743,7 +743,6 @@ "ife5", "ife6", "ipe0", "sfe0", "sfe1", "cam-cdm-intf0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "icp0", "tpg17", "tpg18", "tpg19"; - enable-secure-qos-update; cell-index = <0>; status = "ok"; @@ -817,7 +816,6 @@ parent-node = <&level1_rt_wr0>; }; - ife_1_wr_1: ife-1-wr-1 { cell-index = <4>; node-name = "ife-1-wr-1"; @@ -958,8 +956,7 @@ node-name = "rt-cdm2-all-rd-2"; client-name = "rt-cdm2"; traffic-data = ; - traffic-transaction-type = - ; + traffic-transaction-type = ; parent-node = <&level1_nrt_rd2>; }; @@ -1086,8 +1083,7 @@ level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { cell-index = <30>; node-name = "level3-nrt0-rd-wr-sum"; - traffic-merge-type = - ; + traffic-merge-type = ; qcom,axi-port-mnoc { cam-icc-path-names = "cam_sf_0"; @@ -1097,8 +1093,7 @@ level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { cell-index = <31>; node-name = "level3-nrt1-rd-wr-sum"; - traffic-merge-type = - ; + traffic-merge-type = ; qcom,axi-port-mnoc { cam-icc-path-names = "cam_sf_icp"; @@ -1108,8 +1103,7 @@ level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { cell-index = <32>; node-name = "level3-rt-rd-wr-sum"; - traffic-merge-type = - ; + traffic-merge-type = ; ib-bw-voting-needed; qcom,axi-port-mnoc { @@ -1148,8 +1142,8 @@ status = "ok"; }; - qcom,cam-sync { - compatible = "qcom,cam-sync"; + qcom,camera-main { + compatible = "qcom,camera"; status = "ok"; }; @@ -1274,8 +1268,8 @@ }; }; - qcom,camera-main { - compatible = "qcom,camera"; + qcom,cam-sync { + compatible = "qcom,cam-sync"; status = "ok"; }; @@ -1544,13 +1538,6 @@ interrupts = ; interrupt-names = "csid-lite4"; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - clock-names = "cam_cc_cpas_ife_lite_clk", - "cam_cc_ife_lite_ahb_clk", - "cam_cc_ife_lite_csid_clk_src", - "cam_cc_ife_lite_csid_clk", - "cam_cc_ife_lite_cphy_rx_clk", - "cam_cc_ife_lite_clk_src", - "cam_cc_ife_lite_clk"; clocks = <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, <&camcc CAM_CC_IFE_LITE_AHB_CLK>, <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, @@ -1558,6 +1545,13 @@ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, <&camcc CAM_CC_IFE_LITE_CLK_SRC>, <&camcc CAM_CC_IFE_LITE_CLK>; + clock-names = "cam_cc_cpas_ife_lite_clk", + "cam_cc_ife_lite_ahb_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_ife_lite_clk"; clock-rates = <0 0 400000000 0 0 400000000 0>, <0 0 400000000 0 0 480000000 0>; clock-cntl-level = "svs_l1", "nominal"; @@ -2000,7 +1994,6 @@ required-opps = <&rpmhpd_opp_nom>; }; }; - }; qcom,rt-cdm0 { @@ -2140,12 +2133,12 @@ interrupts = ; interrupt-names = "sfe-lite0"; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - clock-names = "cam_cc_sfe_lite_0_fast_ahb_clk", - "cam_cc_sfe_lite_0_clk", - "cam_cc_cpas_sfe_lite_0_clk"; clocks = <&camcc CAM_CC_SFE_LITE_0_FAST_AHB_CLK>, <&camcc CAM_CC_SFE_LITE_0_CLK>, <&camcc CAM_CC_CPAS_SFE_LITE_0_CLK>; + clock-names = "cam_cc_sfe_lite_0_fast_ahb_clk", + "cam_cc_sfe_lite_0_clk", + "cam_cc_cpas_sfe_lite_0_clk"; clock-rates = <0 480000000 300000000>, <0 600000000 400000000>; clock-cntl-level = "svs_l1", "nominal"; From e7cb65aaaacfc50756b38bc907a0e1a97168a1bf Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Wed, 24 Dec 2025 14:00:56 +0800 Subject: [PATCH 0166/1330] PENDING: arm64: dts: qcom: change pil camera memory map Add the pil camera carveout region based on v2 memory map. Signed-off-by: Qingqing Zhou Signed-off-by: Xin Liu --- arch/arm64/boot/dts/qcom/talos.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 94c1e82fd8220..faa472b216b53 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -662,6 +662,11 @@ reg = <0x0 0x97715000 0x0 0x2000>; no-map; }; + + pil_camera_mem: pil-camera-region@97717000 { + reg = <0x0 0x97717000 0x0 0x800000>; + no-map; + }; }; soc: soc@0 { From ae87fce9540af299822678f2945a5c03d329eb74 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 24 Dec 2025 16:16:57 +0530 Subject: [PATCH 0167/1330] QCLINUX: arm64: dts: qcom: Add Talos camx overlay dts Add CAMX overlay dts file for Talos boards. This change also enables the compilation of the CAMX overlay on Talos boards. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../arm64/boot/dts/qcom/qcs615-ride-camx.dtso | 16 + .../boot/dts/qcom/talos-camera-sensor.dtsi | 152 ++ arch/arm64/boot/dts/qcom/talos-camera.dtsi | 1984 +++++++++++++++++ 4 files changed, 2156 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs615-ride-camx.dtso create mode 100644 arch/arm64/boot/dts/qcom/talos-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/talos-camera.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 9a4e34a2b1517..9d7cec028cae7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -420,6 +420,10 @@ monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb +qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb + qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.dtb \ qcs6490-rb3gen2-vision-mezzanine-camx.dtbo diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride-camx.dtso b/arch/arm64/boot/dts/qcom/qcs615-ride-camx.dtso new file mode 100644 index 0000000000000..a40d8817a7a20 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs615-ride-camx.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "talos-camera.dtsi" +#include "talos-camera-sensor.dtsi" diff --git a/arch/arm64/boot/dts/qcom/talos-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/talos-camera-sensor.dtsi new file mode 100644 index 0000000000000..7e76197614781 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-camera-sensor.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci { + /*cam0-imx577*/ + tl_slot0: qcom,cam-sensor0 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam0>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 28 0>, + <&tlmm 75 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK0", "CAMIF_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <0>; + status = "okay"; + }; + + /*cam1-imx577*/ + t1_slot1: qcom,cam-sensor1 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam1>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 30 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK1", "CAMIF_RESET1"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <1>; + status = "okay"; + }; + + /*cam0-imx577-eeprom*/ + eeprom_cam0: qcom,eeprom0 { + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 28 0>, + <&tlmm 75 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK0", "CAMIF_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <0>; + status = "okay"; + }; + + /*cam1-imx577-eeprom*/ + eeprom_cam1: qcom,eeprom1 { + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 30 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK1", "CAMIF_RESET1"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <1>; + status = "okay"; + }; +}; + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-camera.dtsi b/arch/arm64/boot/dts/qcom/talos-camera.dtsi new file mode 100644 index 0000000000000..e2daa14db1e80 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-camera.dtsi @@ -0,0 +1,1984 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +&soc { + cam_icp: qcom,icp@ac00000 { + compatible = "qcom,cam-icp_v1"; + icp-version = <0x0100>; + reg = <0x0 0xac00000 0x0 0x6000>, + <0x0 0xac10000 0x0 0x8000>, + <0x0 0xac18000 0x0 0x3000>; + reg-names = "icp_qgic", "icp_sierra", "icp_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "a5"; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk", + "cam_cc_icp_clk", + "cam_cc_icp_clk_src"; + clock-rates = <0 0 100000000 0 0 0 0 240000000>, + <0 0 200000000 0 0 0 0 360000000>, + <0 0 300000000 0 0 0 0 432000000>, + <0 0 404000000 0 0 0 0 480000000>, + <0 0 404000000 0 0 0 0 540000000>, + <0 0 404000000 0 0 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; + src-clock-name = "cam_cc_icp_clk_src"; + operating-points-v2 = <&a5_opp_table>; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x73 0x1CF>; + cam_hw_pid = <15>; + cell-index = <0>; + status = "okay"; + + a5_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + qcom,cam-cpas@ac40000 { + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg = <0x0 0xac40000 0x0 0x1000>, + <0x0 0xac42000 0x0 0x5000>; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg-cam-base = <0x40000 0x42000>; + interrupts = ; + interrupt-names = "cpas_camnoc"; + camnoc-axi-min-ib-bw = <3000000000>; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk"; + clock-rates = <0 0 0 0 0 0>, + <0 0 0 80000000 0 150000000>, + <0 0 0 80000000 0 240000000>, + <0 0 0 80000000 0 265000000>, + <0 0 0 80000000 0 355000000>, + <0 0 0 80000000 0 426000000>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "cam_cc_camnoc_axi_clk"; + operating-points-v2 = <&cpas_opp_table>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + cam-icc-path-names = "cam_ahb"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cam_ahb", + "cam_hf_0_mnoc", + "cam_hf_1_mnoc", + "cam_sf_0_mnoc"; + cam-ahb-num-cases = <7>; + cam-ahb-bw-KBps = <0 0>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", + "svs_l1", "nominal", "nominal", + "nominal", "turbo", "turbo"; + client-id-based; + client-names = "csiphy0", "csiphy1", "csiphy2", "cci0", + "csid0", "csid1", "csid2","ife0", + "ife1", "ife2", "ipe0", "cam-cdm-intf0", + "cpas-cdm0", "bps0", "icp0", "jpeg-dma0", + "jpeg-enc0", "lrmecpas0"; + cell-index = <0>; + status = "okay"; + + cpas_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-265000000 { + opp-hz = /bits/ 64 <265000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-426000000 { + opp-hz = /bits/ 64 <426000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + + camera-bus-nodes { + level0-nodes { + level-index = <0>; + + bps0_all_rd: bps0-all-rd { + cell-index = <0>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_read0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <1>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_write0>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <2>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_read2>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <3>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_read3>; + }; + + ife0_linear_pdaf_wr: ife0-linear-pdaf-wr { + cell-index = <4>; + node-name = "ife0-linear-pdaf-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <5>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ife0_ubwc_stats_wr: ife0-ubwc-stats-wr { + cell-index = <6>; + node-name = "ife0-ubwc-stats-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ife1_linear_pdaf_wr: ife1-linear-pdaf-wr { + cell-index = <7>; + node-name = "ife1-linear-pdaf-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt1_write0>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <8>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt1_write0>; + }; + + ife1_ubwc_stats_wr: ife1-ubwc-stats-wr { + cell-index = <9>; + node-name = "ife1-ubwc-stats-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt1_write0>; + }; + + ife2_rdi_wr: ife2-rdi-wr { + cell-index = <10>; + node-name = "ife2-rdi-wr"; + client-name = "ife2"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_write0>; + }; + + ipe0_all_rd: ipe0-all-rd { + cell-index = <11>; + node-name = "ipe0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_nrt0_read0>; + }; + + ipe0_ref_wr: ipe0-ref-wr { + cell-index = <12>; + node-name = "ipe0-ref-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_write0>; + }; + + ipe0_viddisp_wr: ipe0-viddisp-wr { + cell-index = <13>; + node-name = "ipe0-viddisp-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_nrt0_write0>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <14>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_read1>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <15>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_write1>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <16>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_read1>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <17>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_write1>; + }; + + lrme0_all_rd: lrme0-all-rd { + cell-index = <18>; + node-name = "lrme0-all-rd"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_read0>; + }; + + lrme0_all_wr: lrme0-all-wr { + cell-index = <19>; + node-name = "lrme0-all-wr"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_write0>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + + level1_nrt0_read0: level1-nrt0-read0 { + cell-index = <20>; + node-name = "level1-nrt0-read0"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level1_nrt0_read1: level1-nrt0-read1 { + cell-index = <21>; + node-name = "level1-nrt0-read1"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level1_nrt0_read2: level1-nrt0-read2 { + cell-index = <22>; + node-name = "level1-nrt0-read2"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level1_nrt0_read3: level1-nrt0-read3 { + cell-index = <23>; + node-name = "level1-nrt0-read3"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level1_nrt0_write0: level1-nrt0-write0 { + cell-index = <24>; + node-name = "level1-nrt0-write0"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level1_nrt0_write1: level1-nrt0-write1 { + cell-index = <25>; + node-name = "level1-nrt0-write1"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level1_rt0_write0: level1-rt0-write0 { + cell-index = <26>; + node-name = "level1-rt0-write0"; + parent-node = <&level2_rt0_rd_wr_sum>; + traffic-merge-type = ; + }; + + level1_rt1_write0: level1-rt1-write0 { + cell-index = <27>; + node-name = "level1-rt1-write0"; + parent-node = <&level2_rt1_rd_wr_sum>; + traffic-merge-type = ; + }; + }; + + level2-nodes { + level-index = <2>; + + level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { + cell-index = <28>; + node-name = "level2-nrt0-rd-wr-sum"; + traffic-merge-type = ; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0_mnoc"; + }; + }; + + level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { + cell-index = <29>; + node-name = "level2-rt0-rd-wr-sum"; + traffic-merge-type = ; + ib-bw-voting-needed; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0_mnoc"; + }; + }; + + level2_rt1_rd_wr_sum: level2-rt1-rd-wr-sum { + cell-index = <30>; + node-name = "level3-rt1-rd-wr-sum"; + traffic-merge-type = ; + + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_1_mnoc"; + }; + }; + }; + }; + }; + + qcom,cpas-cdm0@ac48000 { + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0x0 0xac48000 0x0 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk", + "cam_cc_slow_ahb_clk_src"; + clock-rates = <0 0 0 0 0 80000000>; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + operating-points-v2 = <&cpas_cdm_opp_table>; + clock-cntl-level = "svs"; + cdm-client-names = "ife0", "ife1", "ife2", + "ife3", "dualife"; + single-context-cdm; + cell-index = <0>; + status = "okay"; + + cpas_cdm_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + + cam_cci: qcom,cci@ac4a000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac4a000 0x0 0x4000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupts = ; + interrupt-names = "CCI"; + operating-points-v2 = <&cci_opp_table>; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_CLK_SRC>, + <&camcc CAM_CC_CCI_CLK>; + clock-names = "cci_clk_src", + "cci_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + cell-index = <0>; + status = "okay"; + + cci_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci: qcom,i2c-custom-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_400Khz_cci: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_1Mhz_cci: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_100Khz_cci: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + }; + + cam_jpeg_enc: qcom,jpegenc@ac4e000 { + compatible = "qcom,cam_jpeg_enc_170"; + reg = <0x0 0xac4e000 0x0 0x4000>; + reg-names = "jpege_hw"; + reg-cam-base = <0x4e000>; + interrupts = ; + interrupt-names = "jpeg"; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk", + "cam_cc_jpeg_clk_src", + "cam_cc_jpeg_clk"; + clock-rates = <0 0 0 0 0 600000000 0>; + src-clock-name = "cam_cc_jpeg_clk_src"; + operating-points-v2 = <&jpeg_enc_opp_table>; + clock-cntl-level = "turbo"; + cell-index = <0>; + status = "okay"; + + jpeg_enc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_jpeg_dma: qcom,jpegdma@ac52000{ + compatible = "qcom,cam_jpeg_dma_170"; + reg = <0x0 0xac52000 0x0 0x4000>; + reg-names = "jpegdma_hw"; + reg-cam-base = <0x52000>; + interrupts = ; + interrupt-names = "jpegdma"; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk", + "cam_cc_jpeg_clk_src", + "cam_cc_jpeg_clk"; + clock-rates = <0 0 0 0 0 600000000 0>; + src-clock-name = "cam_cc_jpeg_clk_src"; + operating-points-v2 = <&jpeg_dma_opp_table>; + clock-cntl-level = "turbo"; + cell-index = <0>; + status = "okay"; + + jpeg_dma_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_csiphy0: qcom,csiphy@ac65000 { + compatible = "qcom,csiphy-v2.0.0", "qcom,csiphy"; + reg = <0x0 0x0ac65000 0x0 0x1000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy0_opp_table>; + reg-cam-base = <0x65000>; + interrupts = ; + interrupt-names = "CSIPHY0"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&vreg_l11a>; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "svs_l1", "turbo"; + clock-rates = <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; + cell-index = <0>; + status = "okay"; + + csiphy0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-269333333 { + opp-hz = /bits/ 64 <269333333>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_csiphy1: qcom,csiphy@ac66000 { + compatible = "qcom,csiphy-v2.0.0", "qcom,csiphy"; + reg = <0x0 0xac66000 0x0 0x1000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy1_opp_table>; + reg-cam-base = <0x66000>; + interrupts = ; + interrupt-names = "CSIPHY1"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&vreg_l11a>; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "svs_l1", "turbo"; + clock-rates = <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; + cell-index = <1>; + status = "okay"; + + csiphy1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-269333333 { + opp-hz = /bits/ 64 <269333333>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_csiphy2: qcom,csiphy@ac67000 { + compatible = "qcom,csiphy-v2.0.0", "qcom,csiphy"; + reg = <0x0 0xac67000 0x0 0x1000>; + reg-names = "csiphy"; + operating-points-v2 = <&csiphy2_opp_table>; + reg-cam-base = <0x67000>; + interrupts = ; + interrupt-names = "CSIPHY2"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&vreg_l11a>; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "svs_l1", "turbo"; + clock-rates = <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; + cell-index = <2>; + status = "okay"; + + csiphy2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-269333333 { + opp-hz = /bits/ 64 <269333333>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_lrme: qcom,lrme@ac6b000 { + compatible = "qcom,lrme"; + reg = <0x0 0xac6b000 0x0 0xa00>; + reg-names = "lrme"; + reg-cam-base = <0x6b000>; + interrupts = ; + interrupt-names = "lrme"; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_LRME_CLK_SRC>, + <&camcc CAM_CC_LRME_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk", + "cam_cc_lrme_clk_src", + "cam_cc_lrme_clk"; + clock-rates = <0 0 0 0 0 200000000 0>, + <0 0 0 0 0 216000000 0>, + <0 0 0 0 0 300000000 0>, + <0 0 0 0 0 404000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "cam_cc_lrme_clk_src"; + operating-points-v2 = <&lrme_opp_table>; + cam_hw_pid = <6 10>; + cell-index = <0>; + status = "okay"; + + lrme_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-404000000 { + opp-hz = /bits/ 64 <404000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_bps: qcom,bps@0x0ac6f000 { + compatible = "qcom,cam-bps"; + reg = <0x0 0xac6f000 0x0 0x3000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + power-domains = <&camcc BPS_GDSC>; + clocks = <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>; + clock-names = "cam_cc_bps_ahb_clk", + "cam_cc_bps_areg_clk", + "cam_cc_bps_axi_clk", + "cam_cc_bps_clk", + "cam_cc_bps_clk_src"; + clock-rates = <0 0 0 0 200000000>, + <0 0 0 0 360000000>, + <0 0 0 0 432000000>, + <0 0 0 0 480000000>, + <0 0 0 0 540000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "cam_cc_bps_clk_src"; + operating-points-v2 = <&bps_opp_table>; + cam_hw_pid = <5 9>; + cell-index = <0>; + status = "okay"; + + bps_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_ipe0: qcom,ipe0@0x0ac87000 { + compatible = "qcom,cam-ipe"; + reg = <0x0 0xac87000 0x0 0x3000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + power-domains = <&camcc IPE_0_GDSC>; + clock-names = "cam_cc_ipe_0_ahb_clk", + "cam_cc_ipe_0_areg_clk", + "cam_cc_ipe_0_axi_clk", + "cam_cc_ipe_0_clk", + "cam_cc_ipe_0_clk_src"; + clocks = <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>; + clock-rates = <0 0 0 0 240000000>, + <0 0 0 0 360000000>, + <0 0 0 0 432000000>, + <0 0 0 0 480000000>, + <0 0 0 0 540000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "lowsvs","svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "cam_cc_ipe_0_clk_src"; + operating-points-v2 = <&ipe0_opp_table>; + cam_hw_pid = <4 8>; + cell-index = <0>; + status = "okay"; + + ipe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_vfe0: qcom,vfe0@acaf000 { + compatible = "qcom,vfe170"; + reg = <0x0 0xacaf000 0x0 0x4000>, + <0x0 0xac42000 0x0 0x5000>; + reg-names = "ife0", "cam_camnoc"; + reg-cam-base = <0xaf000 0x42000>; + interrupts = ; + interrupt-names = "ife0"; + power-domains = <&camcc IFE_0_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_0_clk", + "cam_cc_ife_0_clk_src", + "cam_cc_camnoc_axi_clk", + "cam_cc_ife_0_axi_clk"; + clock-rates = <0 0 0 0 0 0 240000000 0 0>, + <0 0 0 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0>, + <0 0 0 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "cam_cc_ife_0_clk_src"; + operating-points-v2 = <&vfe0_opp_table>; + clock-names-option = "cam_cc_ife_0_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <600000000>; + cam_hw_pid = <1>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "okay"; + + vfe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_csid0: qcom,csid0@acb3000 { + compatible = "qcom,csid170"; + reg = <0x0 0xacb3000 0x0 0x1000>; + reg-names = "csid0"; + reg-cam-base = <0xb3000>; + interrupts = ; + interrupt-names = "csid0"; + power-domains = <&camcc IFE_0_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_0_csid_clk", + "cam_cc_ife_0_csid_clk_src", + "cam_cc_ife_0_cphy_rx_clk", + "cam_cc_cphy_rx_clk_src", + "cam_cc_ife_0_clk", + "cam_cc_ife_0_clk_src", + "cam_cc_camnoc_axi_clk", + "cam_cc_ife_0_axi_clk"; + clock-rates = <0 0 0 0 0 0 100000000 0 0 0 240000000 0 0>, + <0 0 0 0 0 0 200000000 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 320000000 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 404000000 0 0 0 540000000 0 0>, + <0 0 0 0 0 0 480000000 0 0 0 540000000 0 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; + operating-points-v2 = <&csid0_opp_table>; + src-clock-name = "cam_cc_ife_0_csid_clk_src"; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "okay"; + + csid0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-404000000 { + opp-hz = /bits/ 64 <404000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_vfe1: qcom,vfe1@acb6000 { + compatible = "qcom,vfe170"; + reg = <0x0 0xacb6000 0x0 0x4000>, + <0x0 0xac42000 0x0 0x5000>; + reg-names = "ife1", "cam_camnoc"; + reg-cam-base = <0xb6000 0x42000>; + interrupts = ; + interrupt-names = "ife1"; + power-domains = <&camcc IFE_1_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_1_clk", + "cam_cc_ife_1_clk_src", + "cam_cc_camnoc_axi_clk", + "cam_cc_ife_1_axi_clk"; + clock-rates = <0 0 0 0 0 0 240000000 0 0>, + <0 0 0 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0>, + <0 0 0 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "cam_cc_ife_1_clk_src"; + operating-points-v2 = <&vfe1_opp_table>; + clock-names-option = "cam_cc_ife_1_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <600000000>; + cam_hw_pid = <2>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "okay"; + + vfe1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_csid1: qcom,csid1@acba000 { + compatible = "qcom,csid170"; + reg = <0x0 0xacba000 0x0 0x1000>; + reg-names = "csid1"; + reg-cam-base = <0xba000>; + interrupts = ; + interrupt-names = "csid1"; + power-domains = <&camcc IFE_1_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_1_csid_clk", + "cam_cc_ife_1_csid_clk_src", + "cam_cc_ife_1_cphy_rx_clk", + "cam_cc_cphy_rx_clk_src", + "cam_cc_ife_1_clk", + "cam_cc_ife_1_clk_src", + "cam_cc_camnoc_axi_clk", + "cam_cc_ife_1_axi_clk"; + clock-rates = <0 0 0 0 0 0 100000000 0 0 0 240000000 0 0>, + <0 0 0 0 0 0 200000000 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 320000000 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 404000000 0 0 0 540000000 0 0>, + <0 0 0 0 0 0 480000000 0 0 0 540000000 0 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; + src-clock-name = "cam_cc_ife_1_csid_clk_src"; + operating-points-v2 = <&csid1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "okay"; + + csid1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-404000000 { + opp-hz = /bits/ 64 <404000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_vfe_lite: qcom,vfe-lite@acc4000 { + compatible = "qcom,vfe-lite170"; + reg = <0x0 0xacc4000 0x0 0x4000>; + reg-names = "ife-lite0"; + reg-cam-base = <0xc4000>; + interrupts = ; + interrupt-names = "ife-lite0"; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_lite_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_camnoc_axi_clk"; + clock-rates = <0 0 0 0 0 0 240000000 0>, + <0 0 0 0 0 0 360000000 0>, + <0 0 0 0 0 0 432000000 0>, + <0 0 0 0 0 0 540000000 0>, + <0 0 0 0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "cam_cc_ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite0_opp_table>; + cam_hw_pid = <3>; + clock-control-debugfs = "true"; + cell-index = <2>; + status = "okay"; + + vfe_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + cam_csid_lite: qcom,csid-lite@acc8000 { + compatible = "qcom,csid-lite170"; + reg = <0x0 0xacc8000 0x0 0x1000>; + reg-names = "csid-lite0"; + reg-cam-base = <0xc8000>; + interrupts = ; + interrupt-names = "csid-lite0"; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-names = "gcc_camera_ahb_clk", + "gcc_camera_hf_axi_clk", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_lite_csid_clk", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_ife_lite_cphy_rx_clk", + "cam_cc_cphy_rx_clk_src", + "cam_cc_ife_lite_clk", + "cam_cc_ife_lite_clk_src", + "cam_cc_camnoc_axi_clk"; + clock-rates = <0 0 0 0 0 0 100000000 0 0 0 240000000 0>, + <0 0 0 0 0 0 200000000 0 0 0 360000000 0>, + <0 0 0 0 0 0 320000000 0 0 0 432000000 0>, + <0 0 0 0 0 0 404000000 0 0 0 540000000 0>, + <0 0 0 0 0 0 480000000 0 0 0 540000000 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; + src-clock-name = "cam_cc_ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <2>; + status = "okay"; + + csid_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-404000000 { + opp-hz = /bits/ 64 <404000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", "jpegdma", + "jpegenc", "lrmecdm"; + status = "okay"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + ipe0-mask = <0x1000>; + icp_pc_en; + status = "okay"; + }; + + cam_isp_mgr: qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "okay"; + }; + + cam_jpeg_mgr: qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "okay"; + }; + + cam_lrme_mgr: qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "okay"; + }; + + qcom,camera-main { + compatible = "qcom,camera_qcs615"; + status = "okay"; + }; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "okay"; + }; + + cam_smmu: qcom,cam-smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "okay"; + + msm-cam-icp-fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm-cam-smmu-cpas-cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0c00 0x0>; + cam-smmu-label = "cpas-cdm"; + + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0de2 0x0>, + <&apps_smmu 0x0c80 0x0>, + <&apps_smmu 0x0ca0 0x0>, + <&apps_smmu 0x0d00 0x0>, + <&apps_smmu 0x0d20 0x0>; + cam-smmu-label = "icp"; + + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 8MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x800000>; + iova-region-id = <0x0>; + status = "okay"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.3 GB */ + iova-region-name = "io"; + iova-region-start = <0x10C00000>; + iova-region-len = <0xCF300000>; + iova-region-id = <0x3>; + status = "okay"; + }; + + iova-mem-qdss-region { + /* qdss region is approximately 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10B00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "okay"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10A00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "okay"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + iova-granularity = <0x15>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0820 0x40>, + <&apps_smmu 0x0840 0x00>, + <&apps_smmu 0x0860 0x40>; + cam-smmu-label = "ife"; + multiple-client-devices; + com,iommu-faults = "stall-disable", "non-fatal"; + + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xd80 0x20>, + <&apps_smmu 0xda0 0x20>; + cam-smmu-label = "jpeg"; + + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0cc0 0x0>, + <&apps_smmu 0x0d40 0x0>; + cam-smmu-label = "lrme"; + + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "okay"; + }; + + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "okay"; + }; +}; + +&tlmm { + cam_sensor_active_rst0: cam-sensor-active-rst0 { + /* RESET */ + mux { + pins = "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio75"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst1: cam-sensor-active-rst1 { + /* RESET */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst2: cam-sensor-active-rst2 { + /* RESET */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam-sensor-mclk2-active { + /* MCLK2 */ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam-sensor-mclk2-suspend { + /* MCLK2 */ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam-sensor-mclk3-active { + /* MCLK3 */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam-sensor-mclk3-suspend { + /* MCLK3 */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam-sensor-suspend-rst0 { + /* RESET */ + mux { + pins = "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio75"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst1: cam-sensor-suspend-rst1 { + /* RESET */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst2: cam-sensor-suspend-rst2 { + /* RESET */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cci_i2c_scl0_active: cci-i2c-scl0-active { + mux { + /* CLK, DATA */ + pins = "gpio33"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_suspend: cci-i2c-scl0-suspend { + mux { + /* CLK, DATA */ + pins = "gpio33"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci-i2c-scl1-active { + mux { + /* CLK, DATA */ + pins = "gpio35"; + function = "cci_i2c"; + }; + + config { + pins = "gpio35"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_suspend: cci-i2c-scl1-suspend { + mux { + /* CLK, DATA */ + pins = "gpio35"; + function = "cci_i2c"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + + cci_i2c_sda0_active: cci-i2c-sda0-active { + mux { + /* CLK, DATA */ + pins = "gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio32"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda0_suspend: cci-i2c-sda0-suspend { + mux { + /* CLK, DATA */ + pins = "gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci-i2c-sda1-active { + mux { + /* CLK, DATA */ + pins = "gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio34"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_suspend: cci-i2c-sda1-suspend { + mux { + /* CLK, DATA */ + pins = "gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; From d6ed90d19d1a5ba27dda9b7e0cdbad41fa53baa4 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 7 Jan 2026 19:23:37 +0530 Subject: [PATCH 0168/1330] QCLINUX: arm64: dts: qcom: Change rb3gen2 camera firmware path update the path for the camera icp firmware. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi index 37ea48e35d09c..2fadfb9de1fee 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs6490-camera.dtsi @@ -32,7 +32,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; src-clock-name = "soc_fast_ahb"; operating-points-v2 = <&a5_opp_table>; - fw_name = "CAMERA_ICP_170.elf"; + fw_name = "qcom/qcm6490/CAMERA_ICP_170.elf"; ubwc-ipe-fetch-cfg = <0x7073 0x707b>; ubwc-ipe-write-cfg = <0x161cf 0x161ef>; ubwc-bps-fetch-cfg = <0x7073 0x707b>; From 3ebd0c20a9cb161d56254275dd0bfe7a6e520b1e Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 7 Jan 2026 19:33:18 +0530 Subject: [PATCH 0169/1330] QCLINUX: arm64: dts: qcom: Change monaco camera firmware path update the path for the camera icp firmware. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/monaco-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-camera.dtsi b/arch/arm64/boot/dts/qcom/monaco-camera.dtsi index f72161e75f7e7..258ad08ffee2f 100644 --- a/arch/arm64/boot/dts/qcom/monaco-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-camera.dtsi @@ -1463,7 +1463,7 @@ <400000000 0 600000000 0>; clock-cntl-level = "svs_l1", "nominal"; nrt-device; - fw_name = "CAMERA_ICP"; + fw_name = "qcom/qcs8300/CAMERA_ICP"; ubwc-ipe-fetch-cfg = <0x707b 0x7083>; ubwc-ipe-write-cfg = <0x161ef 0x1620f>; qos-val = <0xa0a>; From fe4a3698eb85c8c741e427d62611599c2330cc69 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 7 Jan 2026 19:32:20 +0530 Subject: [PATCH 0170/1330] QCLINUX: arm64: dts: qcom: Change lemans camera firmware path update the path for the camera icp firmware. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/lemans-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-camera.dtsi b/arch/arm64/boot/dts/qcom/lemans-camera.dtsi index 855d29dff618f..a207377cce6c1 100644 --- a/arch/arm64/boot/dts/qcom/lemans-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-camera.dtsi @@ -1600,7 +1600,7 @@ <400000000 0 600000000 0>; clock-cntl-level = "svs_l1", "nominal"; nrt-device; - fw_name = "CAMERA_ICP"; + fw_name = "qcom/sa8775p/CAMERA_ICP"; ubwc-ipe-fetch-cfg = <0x707b 0x7083>; ubwc-ipe-write-cfg = <0x161ef 0x1620f>; qos-val = <0xa0a>; From a17030e99ee35c591280f5afdabe7ef98cdd5831 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 7 Jan 2026 19:30:22 +0530 Subject: [PATCH 0171/1330] QCLINUX: arm64: dts: qcom: Change talos camera firmware path update the path for the camera icp firmware. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/talos-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos-camera.dtsi b/arch/arm64/boot/dts/qcom/talos-camera.dtsi index e2daa14db1e80..5a79115547f9a 100644 --- a/arch/arm64/boot/dts/qcom/talos-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-camera.dtsi @@ -43,7 +43,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "cam_cc_icp_clk_src"; operating-points-v2 = <&a5_opp_table>; - fw_name = "CAMERA_ICP.elf"; + fw_name = "qcom/qcs615/CAMERA_ICP.elf"; ubwc-cfg = <0x73 0x1CF>; cam_hw_pid = <15>; cell-index = <0>; From dc420d870e046e6adb2784cbd0843deb9084fae8 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Fri, 9 Jan 2026 00:54:23 +0530 Subject: [PATCH 0172/1330] QCLINUX: arm64: dts: qcom: talos: add camnoc bandwidth levels Add two new AHB bandwidth levels for the camnoc path and update cam-ahb-num-cases accordingly. This ensures that the DT reflects the full set of supported interconnect bandwidth cases. Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/talos-camera.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos-camera.dtsi b/arch/arm64/boot/dts/qcom/talos-camera.dtsi index 5a79115547f9a..e0f59fb00a5fc 100644 --- a/arch/arm64/boot/dts/qcom/talos-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-camera.dtsi @@ -134,9 +134,10 @@ "cam_hf_0_mnoc", "cam_hf_1_mnoc", "cam_sf_0_mnoc"; - cam-ahb-num-cases = <7>; + cam-ahb-num-cases = <9>; cam-ahb-bw-KBps = <0 0>, <0 76800>, <0 150000>, <0 150000>, - <0 300000>, <0 300000>, <0 300000>; + <0 300000>, <0 300000>, <0 300000>, + <0 300000>, <0 300000>; vdd-corners = Date: Fri, 23 Jan 2026 12:57:03 +0530 Subject: [PATCH 0173/1330] QCLINUX: arm64: dts: qcom: disabled vreg_cam1_2p8 regulator Disabled vreg_cam1_2p8 regulator to free GPIOs. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso index 3945c77528ccb..c0fea4bb3dc23 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camx.dtso @@ -105,3 +105,7 @@ }; }; }; + +&vreg_cam1_2p8 { + status = "disabled"; +}; From 9829ecc133ddc699ee4c6db7ff26847d5217adee Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Thu, 29 Jan 2026 18:26:31 +0530 Subject: [PATCH 0174/1330] QCLINUX: arm64: dts: qcom: Enable IMX577 sensor on lemans Enable imx577 sensor on lemans boards from slot0 to slot3. Signed-off-by: Nihal Kumar Gupta --- .../dts/qcom/lemans-evk-camera-sensor.dtsi | 384 ++++++++++++++++++ 1 file changed, 384 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi index 8eb1026e7da1b..2a650bc52d1fc 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi @@ -205,6 +205,47 @@ status = "ok"; }; + /*cam0-cmk_imx577*/ + qcom,cam-sensor27 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam27>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 72 0>, + <&tlmm 132 0>, + <&pmm8654au_0_gpios 7 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK0", + "CAMIF_RESET0", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <27>; + status = "ok"; + }; + eeprom_cam24: qcom,eeprom24 { compatible = "qcom,eeprom"; cam_vio-supply = <&vreg_s4a>; @@ -239,6 +280,41 @@ cell-index = <24>; status = "ok"; }; + + eeprom_cam27: qcom,eeprom27 { + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 72 0>, + <&tlmm 132 0>, + <&pmm8654au_0_gpios 7 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK0", + "CAMIF_RESET0", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <27>; + status = "ok"; + }; }; &cam_cci1 { @@ -401,6 +477,160 @@ cell-index = <21>; status = "ok"; }; + + /*cam1-imx577*/ + qcom,cam-sensor26 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam26>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 73 0>, + <&tlmm 133 0>, + <&pmm8654au_0_gpios 8 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <26>; + status = "ok"; + }; + + /*cam1-cmk_imx577*/ + qcom,cam-sensor28 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam28>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 73 0>, + <&tlmm 133 0>, + <&pmm8654au_0_gpios 8 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <28>; + status = "ok"; + }; + + eeprom_cam26: qcom,eeprom26 { + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 73 0>, + <&tlmm 133 0>, + <&pmm8654au_0_gpios 8 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <26>; + status = "ok"; + }; + + eeprom_cam28: qcom,eeprom28 { + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 73 0>, + <&tlmm 133 0>, + <&pmm8654au_0_gpios 8 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <28>; + status = "ok"; + }; }; &cam_cci2 { @@ -563,6 +793,83 @@ cell-index = <22>; status = "ok"; }; + + /*cam2-cmk_imx577*/ + qcom,cam-sensor29 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam29>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 74 0>, + <&tlmm 134 0>, + <&pmm8654au_0_gpios 9 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK2", + "CAMIF_RESET2", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <29>; + status = "ok"; + }; + + eeprom_cam29: qcom,eeprom29 { + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios = <&tlmm 74 0>, + <&tlmm 134 0>, + <&pmm8654au_0_gpios 9 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <29>; + status = "ok"; + }; }; &cam_cci3 { @@ -725,6 +1032,83 @@ cell-index = <23>; status = "ok"; }; + + /*cam3-cmk_imx577*/ + qcom,cam-sensor30 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam30>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 75 0>, + <&tlmm 135 0>, + <&pmm8654au_0_gpios 10 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK3", + "CAMIF_RESET3", + "CAM_CUSTOM1"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <30>; + status = "ok"; + }; + + eeprom_cam30: qcom,eeprom30 { + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 75 0>, + <&tlmm 135 0>, + <&pmm8654au_0_gpios 10 0>; + pinctrl-names = "cam_default", "cam_suspend"; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_CUSTOM1"; + sensor-mode = <0>; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <30>; + status = "ok"; + }; }; &soc { From e3a95cfd3515ac0f77066cbf601999a07bac4bd2 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Mon, 2 Feb 2026 15:46:31 +0530 Subject: [PATCH 0175/1330] QCLINUX: arm64: dts: qcom: Add camx overlay for talos evk Add camx overlay for talos EVK baord. Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ arch/arm64/boot/dts/qcom/talos-evk-camx.dtso | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-camx.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 9d7cec028cae7..43abe20f0dc2a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -448,3 +448,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-camx.dtb sa8775p-ride-r3-camx-dtbs:= sa8775p-ride-r3.dtb sa8775p-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3-camx.dtb + +talos-evk-camx-dtbs := talos-evk.dtb talos-evk-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/talos-evk-camx.dtso b/arch/arm64/boot/dts/qcom/talos-evk-camx.dtso new file mode 100644 index 0000000000000..a40d8817a7a20 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-camx.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "talos-camera.dtsi" +#include "talos-camera-sensor.dtsi" From 37f4252dc13d8e20af4ae9ed8527dc5a41fcb93d Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 2 Feb 2026 22:21:36 +0530 Subject: [PATCH 0176/1330] QCLINUX: arm64: dts: qcom: add node labels and explicit QoS flag in lemans Adds labels to cam-cpas and cam-icp nodes and changes enable-secure-qos-update from boolean to explicit. This change is required for KVM support. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/lemans-camera.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-camera.dtsi b/arch/arm64/boot/dts/qcom/lemans-camera.dtsi index a207377cce6c1..d6cce86922c26 100644 --- a/arch/arm64/boot/dts/qcom/lemans-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-camera.dtsi @@ -667,7 +667,7 @@ status = "ok"; }; - qcom,cam-cpas { + cam_cpas: qcom,cam-cpas { compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; @@ -743,7 +743,7 @@ "ife5", "ife6", "ipe0", "sfe0", "sfe1", "cam-cdm-intf0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "icp0", "tpg17", "tpg18", "tpg19"; - enable-secure-qos-update; + enable-secure-qos-update = <1>; cell-index = <0>; status = "ok"; @@ -1114,7 +1114,7 @@ }; }; - qcom,cam-icp { + cam_icp_firmware: qcom,cam-icp { compatible = "qcom,cam-icp"; compat-hw-name = "qcom,icp", "qcom,ipe0"; num-icp = <1>; From bf7880a760d0738c98065508ba6b10a4fcf3334d Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 2 Feb 2026 22:38:12 +0530 Subject: [PATCH 0177/1330] QCLINUX: arm64: dts: qcom: add node labels and explicit QoS flag in monaco Adds labels to cam-cpas and cam-icp nodes and changes enable-secure-qos-update from boolean to explicit. This change is required for KVM support. Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/monaco-camera.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-camera.dtsi b/arch/arm64/boot/dts/qcom/monaco-camera.dtsi index 258ad08ffee2f..8250f66c34526 100644 --- a/arch/arm64/boot/dts/qcom/monaco-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-camera.dtsi @@ -528,7 +528,7 @@ status = "ok"; }; - qcom,cam-cpas { + cam_cpas: qcom,cam-cpas { compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; @@ -605,7 +605,7 @@ "ife5", "ife6", "ipe0", "sfe0", "sfe1", "cam-cdm-intf0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "icp0", "tpg13", "tpg14", "tpg15"; - enable-secure-qos-update; + enable-secure-qos-update = <1>; cell-index = <0>; status = "ok"; @@ -976,7 +976,7 @@ }; }; - qcom,cam-icp { + cam_icp_firmware: qcom,cam-icp { compatible = "qcom,cam-icp"; compat-hw-name = "qcom,icp", "qcom,ipe0"; num-icp = <1>; From 0a4daafb067991488c736949ed9c051ef9acaa53 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Sat, 7 Feb 2026 15:37:33 +0530 Subject: [PATCH 0178/1330] QCLINUX: arm64: dts: qcom: lemans: Add CamX EL2 overlay Add camx el2 DT overlay for lemans platforms. The overlay updates the ICP firmware node with Secure SMMU SID and disables secure QoS updates for CPAS in EL2/KVM configurations. Wire up the new overlay-built DTBs in the qcom DT Makefile so the corresponding *-camx-el2.dtb targets are generated. Co-developed-by: Ignatius Michael Jihan Signed-off-by: Ignatius Michael Jihan Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/Makefile | 4 +++ arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso | 27 +++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 43abe20f0dc2a..1303bd82723d1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -416,6 +416,10 @@ lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camx.dtb +lemans-camx-el2-dtbs := lemans-evk-el2.dtb lemans-evk-camx.dtbo lemans-camx-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb + monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso b/arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso new file mode 100644 index 0000000000000..83b5605f026a8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +/ { + /* cam_cpas label -> /soc@0/qcom,cam-cpas * + fragment@0 { + target-path = "/soc@0/qcom,cam-cpas"; + __overlay__ { + enable-secure-qos-update = <0>; + }; + }; + + /* cam_icp_firmware label -> /soc@0/qcom,cam-icp */ + fragment@1 { + target-path = "/soc@0/qcom,cam-icp"; + __overlay__ { + camera-firmware { + iommus = <&apps_smmu 0x08c1 0x0400>; + }; + }; + }; +}; From 4ee679562d2b1f2b447c3b70a705fd6168172e0c Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Thu, 23 Oct 2025 12:28:39 +0530 Subject: [PATCH 0179/1330] QCLINUX: firmware: qcom_scm: Add new scm to update Camera QoS Add new SCM call to program secure camera qos settings. For each NIU camera driver can call this scm API which need each NIU's register offsets, value and number of registers offset that need to be programmed. Signed-off-by: Vikram Sharma --- drivers/firmware/qcom/qcom_scm.c | 45 ++++++++++++++++++++++++++ drivers/firmware/qcom/qcom_scm.h | 3 ++ include/linux/firmware/qcom/qcom_scm.h | 10 ++++++ 3 files changed, 58 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index c1f13cdc2dfeb..0b48cad45f39f 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2510,6 +2510,51 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); +int qcom_scm_camera_update_camnoc_qos(uint32_t use_case_id, + uint32_t cam_qos_cnt, struct qcom_scm_camera_qos *cam_qos) +{ + int ret; + dma_addr_t payload_phys; + u32 *payload_buf = NULL; + u32 payload_size = 0; + + if ((cam_qos_cnt > QCOM_SCM_CAMERA_MAX_QOS_CNT) || (cam_qos_cnt && !cam_qos)) { + pr_err("Invalid input SmartQoS count: %d\n", cam_qos_cnt); + return -EINVAL; + } + + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_CAMERA, + .cmd = QCOM_SCM_CAMERA_UPDATE_CAMNOC_QOS, + .owner = ARM_SMCCC_OWNER_SIP, + .args[0] = use_case_id, + .args[2] = payload_size, + .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_VAL, QCOM_SCM_RW, QCOM_SCM_VAL), + }; + + payload_size = cam_qos_cnt * sizeof(struct qcom_scm_camera_qos); + + /* fill all required qos settings */ + if (use_case_id && payload_size && cam_qos) { + payload_buf = dma_alloc_coherent(__scm->dev, + payload_size, &payload_phys, GFP_KERNEL); + if (!payload_buf) + return -ENOMEM; + + memcpy(payload_buf, cam_qos, payload_size); + desc.args[1] = payload_phys; + desc.args[2] = payload_size; + + } + ret = qcom_scm_call(__scm->dev, &desc, NULL); + + if (payload_buf) + dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_scm_camera_update_camnoc_qos); + static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 hwirq) { if (hwirq >= GIC_SPI_BASE && hwirq <= GIC_MAX_SPI) { diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index caab80a73e17f..d8c39bfec47f7 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -175,6 +175,9 @@ int qcom_scm_shm_bridge_enable(struct device *scm_dev); #define QCOM_SCM_INTERRUPTED 1 #define QCOM_SCM_WAITQ_SLEEP 2 +#define QCOM_SCM_SVC_CAMERA 0x18 +#define QCOM_SCM_CAMERA_UPDATE_CAMNOC_QOS 0xA + static inline int qcom_scm_remap_error(int err) { switch (err) { diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 5747bd191bf15..d84b5eb6870c6 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -10,10 +10,12 @@ #include #include +#include #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1 +#define QCOM_SCM_CAMERA_MAX_QOS_CNT 2 #define QCOM_SCM_HDCP_MAX_REQ_CNT 5 struct qcom_scm_hdcp_req { @@ -77,6 +79,14 @@ struct qcom_scm_pas_context { bool use_tzmem; }; +struct qcom_scm_camera_qos { + u32 offset; + u32 val; +}; + +int qcom_scm_camera_update_camnoc_qos(uint32_t use_case_id, + uint32_t qos_cnt, struct qcom_scm_camera_qos *scm_buf); + struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev, u32 pas_id, phys_addr_t mem_phys, From f1fcba21b10b18dc04b90cc52e4292fac0114a9f Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Sun, 9 Nov 2025 20:07:19 +0530 Subject: [PATCH 0180/1330] FROMLIST: dt-bindings: arm: Document reboot mode magic Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-6-46e085bca4cc@oss.qualcomm.com Reviewed-by: Rob Herring (Arm) Signed-off-by: Elliot Berman Signed-off-by: Shivendra Pratap --- .../devicetree/bindings/arm/psci.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 6e2e0c5518411..5d4368d77d07e 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -98,6 +98,27 @@ properties: [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/cpu/idle-states.yaml + reboot-mode: + type: object + $ref: /schemas/power/reset/reboot-mode.yaml# + unevaluatedProperties: false + properties: + # "mode-normal" is just SYSTEM_RESET + mode-normal: false + patternProperties: + "^mode-.*$": + minItems: 1 + maxItems: 2 + description: | + Describes a vendor-specific reset type. The string after "mode-" + maps a reboot mode to the parameters in the PSCI SYSTEM_RESET2 call. + + Parameters are named mode-xxx = , where xxx + is the name of the magic reboot mode, type is the lower 31 bits + of the reset_type, and, optionally, the cookie value. If the cookie + is not provided, it is defaulted to zero. + The 31st bit (vendor-resets) will be implicitly set by the driver. + patternProperties: "^power-domain-": $ref: /schemas/power/power-domain.yaml# @@ -137,6 +158,15 @@ allOf: required: - cpu_off - cpu_on + - if: + not: + properties: + compatible: + contains: + const: arm,psci-1.0 + then: + properties: + reboot-mode: false additionalProperties: false @@ -260,4 +290,17 @@ examples: domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>; }; }; + + - |+ + + // Case 5: SYSTEM_RESET2 vendor resets + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + reboot-mode { + mode-edl = <0>; + mode-bootloader = <1 2>; + }; + }; ... From f291132dd39982c61f4e1113f3a4ad69572f96b6 Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Sun, 9 Nov 2025 20:07:21 +0530 Subject: [PATCH 0181/1330] FROMLIST: arm64: dts: qcom: qcm6490-idp: Add PSCI SYSTEM_RESET2 types Add support for SYSTEM_RESET2 vendor-specific resets in qcm6490-idp as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-8-46e085bca4cc@oss.qualcomm.com Reviewed-by: Konrad Dybcio Signed-off-by: Elliot Berman Signed-off-by: Shivendra Pratap --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index ba0f7e5c89a0d..1c5bc51bc1791 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -863,7 +863,7 @@ interrupts = ; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index b2f00e107643d..0d91113389f30 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -695,6 +695,13 @@ status = "okay"; }; +&psci { + reboot-mode { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From 8ea94cbc3b0aec358f9ccb05f3c7c4c7e0b1e6a8 Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Sun, 9 Nov 2025 20:07:22 +0530 Subject: [PATCH 0182/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Add PSCI SYSTEM_RESET2 types Add support for SYSTEM_RESET2 vendor-specific resets in qcs6490-rb3gen2 as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-9-46e085bca4cc@oss.qualcomm.com Reviewed-by: Konrad Dybcio Signed-off-by: Elliot Berman Signed-off-by: Shivendra Pratap --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e3d2f01881ae0..1862529815486 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1031,6 +1031,13 @@ status = "okay"; }; +&psci { + reboot-mode { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; +}; + &qup_uart7_cts { /* * Configure a bias-bus-hold on CTS to lower power From 61bbdc67fd97b2de143f56c299dfa764320374d8 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 15 Dec 2025 16:29:34 +0530 Subject: [PATCH 0183/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Adjust tsens thermal zone configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform but has a different thermal junction temperature specification due to package-level differences. Update passive/hot trip thresholds to 105°C and critical trip thresholds to 115°C for various subsystem TSENS sensors. Disable CPU cooling maps for CPU TSENS since CPU thermal mitigation is handled automatically in hardware on this board. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20251215105934.2428987-1-manaf.pallikunhi@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 334 +++++++++++++++++++ 1 file changed, 334 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 1862529815486..af4925ffa40c9 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1216,6 +1216,340 @@ }; }; +&thermal_zones { + cpu0-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu1-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu2-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu3-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu4-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu5-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu6-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu7-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu8-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu9-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu10-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + cpu11-thermal { + trips { + /delete-node/ trip-point0; + /delete-node/ trip-point1; + + cpu-crit { + temperature = <115000>; + }; + }; + + /delete-node/ cooling-maps; + }; + + aoss0-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + aoss0-crit { + temperature = <115000>; + }; + }; + }; + + aoss1-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + aoss1-crit { + temperature = <115000>; + }; + }; + }; + + cpuss0-thermal { + trips { + /delete-node/ trip-point0; + + cluster0-crit { + temperature = <115000>; + }; + }; + }; + + cpuss1-thermal { + trips { + /delete-node/ trip-point0; + + cluster0-crit { + temperature = <115000>; + }; + }; + }; + + gpuss0-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + gpuss0-crit { + temperature = <115000>; + }; + }; + }; + + gpuss1-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + gpuss1-crit { + temperature = <115000>; + }; + }; + }; + + nspss0-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + nspss0-crit { + temperature = <115000>; + }; + }; + }; + + nspss1-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + nspss1-crit { + temperature = <115000>; + }; + }; + }; + + video-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + video-crit { + temperature = <115000>; + }; + }; + }; + + ddr-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + ddr-crit { + temperature = <115000>; + }; + }; + }; + + mdmss0-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + mdmss0-crit { + temperature = <115000>; + }; + }; + }; + + mdmss1-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + mdmss1-crit { + temperature = <115000>; + }; + }; + }; + + mdmss2-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + mdmss2-crit { + temperature = <115000>; + }; + }; + }; + + mdmss3-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + mdmss3-crit { + temperature = <115000>; + }; + }; + }; + + camera0-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + + camera0-crit { + temperature = <115000>; + }; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ From 856c8d739415546306756ad18321e4612c0daae8 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 23 Dec 2025 18:02:26 +0530 Subject: [PATCH 0184/1330] FROMLIST: arm64: dts: qcom: Enable cdsp qmi tmd devices for kodiak Enable cdsp cooling devices and cooling map bindings for cdsp. Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20251223123227.1317244-8-gaurav.kohli@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 1c5bc51bc1791..80e9481471f24 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -4793,6 +4793,14 @@ }; }; }; + + cooling { + compatible = "qcom,qmi-cooling-cdsp"; + cdsp_sw: cdsp_sw { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; }; usb_1: usb@a600000 { @@ -7600,12 +7608,26 @@ type = "hot"; }; + nspss0_alert1: trip-point1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + nspss0_crit: nspss0-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&nspss0_alert1>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nspss1-thermal { @@ -7618,12 +7640,26 @@ type = "hot"; }; + nspss1_alert1: trip-point1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + nspss1_crit: nspss1-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&nspss1_alert1>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; video-thermal { From 730e59167826a517102e7d266c2c1f4e3f9f141b Mon Sep 17 00:00:00 2001 From: Gopi Botlagunta Date: Fri, 30 Jan 2026 15:57:25 +0530 Subject: [PATCH 0185/1330] FROMLIST: arm64: dts: qcom: Enable lvds panel-DV215FHM-R01 for rb3gen2 industrial mezzanine Below is the routing diagram of dsi lanes from qcs6490 soc to mezzanine. DSI0 --> SW1403.4 --> LT9611uxc --> hdmi port | --> SW2700.1 --> dsi connector | --> LT9211c --> LVDS connector Disable hdmi connector for industrial mezzanine and enable LT9211c bridge and lvds panel node. LT9211c is powered by default with reset gpio connected to 117. Link: https://lore.kernel.org/r/20260130-add-lt9211c-bridge-for-rb3gen2-industrial-mezzanine-v2-1-a98714fa1531@oss.qualcomm.com Signed-off-by: Gopi Botlagunta Co-developed-by: Yi Zhang Signed-off-by: Yi Zhang --- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 619a42b5ef48d..cc8ee16431679 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -8,6 +8,112 @@ #include #include +/ { + + hdmi-connector { + status = "disabled"; + }; + + panel_lvds: panel-lvds@0 { + compatible = "panel-lvds"; + data-mapping = "vesa-24"; + width-mm = <476>; + height-mm = <268>; + + status = "okay"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hback-porch = <148>; + hsync-len = <44>; + vfront-porch = <4>; + vback-porch = <36>; + vsync-len = <5>; + de-active = <1>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dual-lvds-odd-pixels; + panel_in_lvds_odd: endpoint { + remote-endpoint = <<9211c_out_odd>; + }; + }; + + port@1 { + reg = <1>; + + dual-lvds-even-pixels; + panel_in_lvds_even: endpoint { + remote-endpoint = <<9211c_out_even>; + }; + + }; + }; + }; + +}; + +&i2c1 { + status = "okay"; + + lvds_bridge: lvds-bridge@29 { + compatible = "lontium,lt9211c"; + reg = <0x29>; + reset-gpios = <&tlmm 117 1>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9211c_in: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9211c_out_odd: endpoint { + remote-endpoint = <&panel_in_lvds_odd>; + }; + }; + + port@3 { + reg = <3>; + + lt9211c_out_even: endpoint { + remote-endpoint = <&panel_in_lvds_even>; + }; + }; + }; + }; + + +}; + +<9611_codec { + status = "disabled"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9211c_in>; +}; + &spi11 { #address-cells = <1>; #size-cells = <0>; From 8540930294e0c4d592998bc8718472c062c54f51 Mon Sep 17 00:00:00 2001 From: Janaki Ramaiah Thota Date: Tue, 3 Feb 2026 12:48:07 +0530 Subject: [PATCH 0186/1330] FROMLIST: arm64: dts: qcom: qcm6490-idp: add and enable BT node Add the PMU node for WCN6750 present on the qcm6490-idp board and assign its power outputs to the Bluetooth module. In WCN6750 module sw_ctrl and wifi-enable pins are handled in the wifi controller firmware. Therefore, it is not required to have those pins' entries in the PMU node. Link: https://lore.kernel.org/r/20260203071807.764036-1-janaki.thota@oss.qualcomm.com Reviewed-by: Konrad Dybcio Signed-off-by: Janaki Ramaiah Thota --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 169 +++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 0d91113389f30..e6b9adfa184a1 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -36,6 +36,7 @@ aliases { serial0 = &uart5; + serial1 = &uart7; }; pm8350c_pwm_backlight: backlight { @@ -194,6 +195,63 @@ #sound-dai-cells = <1>; }; + + wcn6750-pmu { + compatible = "qcom,wcn6750-pmu"; + pinctrl-0 = <&bt_en>; + pinctrl-names = "default"; + vddaon-supply = <&vreg_s7b_0p972>; + vddasd-supply = <&vreg_l11c_2p8>; + vddpmu-supply = <&vreg_s7b_0p972>; + vddrfa0p8-supply = <&vreg_s7b_0p972>; + vddrfa1p2-supply = <&vreg_s8b_1p272>; + vddrfa1p7-supply = <&vreg_s1b_1p872>; + vddrfa2p2-supply = <&vreg_s1c_2p19>; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -702,6 +760,39 @@ }; }; +&qup_uart7_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + &qupv3_id_0 { status = "okay"; }; @@ -927,6 +1018,59 @@ gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ + bt_en: bt-en-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + sd_cd: sd-cd-state { pins = "gpio91"; function = "gpio"; @@ -945,6 +1089,31 @@ status = "okay"; }; +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + max-speed = <3200000>; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l7b_2p952>; From b419ba5ac00a9558daa9aa8e26fc2357d0bb3477 Mon Sep 17 00:00:00 2001 From: Sushrut Shree Trivedi Date: Thu, 12 Feb 2026 17:36:29 +0530 Subject: [PATCH 0187/1330] FROMLIST: arm64: dts: qcom: qcm6490-idp: Enable PCIe1 Remove PCIe1 clocks from protected-list and enable PCIe1 controller and its corresponding PHY nodes on qcm6490-idp platform. PCIe1 is used to connect NVMe based SSD's on this platform. Signed-off-by: Sushrut Shree Trivedi Link: https://lore.kernel.org/r/20260212-qcm6490-idp-v1-1-80a45bd46ac5@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 39 ++++++++++++++++++++---- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index e6b9adfa184a1..50ff128b99eb0 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -591,12 +591,7 @@ }; &gcc { - protected-clocks = ,, - , , - , , - , , - , , - , , + protected-clocks = , , ,, , , , @@ -673,6 +668,22 @@ status = "okay"; }; +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + &pm7250b_gpios { lcd_disp_bias_en: lcd-disp-bias-en-state { pins = "gpio2"; @@ -1071,6 +1082,22 @@ bias-pull-up; }; + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sd_cd: sd-cd-state { pins = "gpio91"; function = "gpio"; From 124f441adb0c817ede1300d13e9711369d9f60a1 Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 9 Nov 2025 20:07:23 +0530 Subject: [PATCH 0188/1330] FROMLIST: arm64: dts: qcom: lemans: Add PSCI SYSTEM_RESET2 types Add support for SYSTEM_RESET2 vendor-specific resets as reboot-modes in the psci node. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-10-46e085bca4cc@oss.qualcomm.com Signed-off-by: Elliot Berman Signed-off-by: Shivendra Pratap --- arch/arm64/boot/dts/qcom/lemans.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index be8c8c59ef5ab..38e014a7a5b09 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -635,6 +635,11 @@ #power-domain-cells = <0>; domain-idle-states = <&cluster_sleep_apss_rsc_pc>; }; + + reboot-mode { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; }; reserved-memory { From 8b0ec24ab1f0e99b665c4d65933e11e0271f90e8 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 28 Jan 2026 17:18:50 +0530 Subject: [PATCH 0189/1330] FROMLIST: arm64: dts: qcom: lemans: Add eDP ref clock for eDP PHYs The eDP PHY nodes on lemans were missing the reference clock voting. This initially went unnoticed because the clock was implicitly enabled by the UFS PHY driver, and the eDP PHY happened to rely on that. After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off calls"), the UFS driver no longer keeps the reference clock enabled. As a result, the eDP PHY fails to power on. To fix this, add eDP reference clock for eDP PHYs on lemans chipset ensuring reference clock is enabled. Link: https://lore.kernel.org/r/20260128114853.2543416-3-quic_riteshk@quicinc.com Fixes: e1e3e5673f8d7 ("arm64: dts: qcom: sa8775p: add DisplayPort device nodes") Signed-off-by: Ritesh Kumar --- arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 38e014a7a5b09..0abaeccffe966 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5306,9 +5306,11 @@ <0x0 0x0aec2000 0x0 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; @@ -5325,9 +5327,11 @@ <0x0 0x0aec5000 0x0 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; From 86285fd337489afd877305f3040833ce043a5e5f Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Wed, 12 Nov 2025 12:08:26 +0530 Subject: [PATCH 0190/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Enable Bluetooth support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's a WCN6855 WiFi/Bluetooth module on an M.2 card. To make Bluetooth work, we need to define the necessary device tree nodes, including UART configuration and power supplies. Since there is no standard M.2 binding in the device tree at present, the PMU is described using dedicated PMU nodes to represent the internal regulators required by the module. The module provides a 3.3V supply, which originates from the main board’s 12V rail. To represent this power hierarchy in the device tree, add a fixed 12V regulator node as the DC-IN source and link it to the 3.3V regulator node. Link: https://lore.kernel.org/all/20251112071147.1450258-2-wei.deng@oss.qualcomm.com/ Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 99 +++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 90fce947ca7e5..a227b6037b37c 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -21,6 +21,7 @@ ethernet0 = ðernet0; mmc1 = &sdhc; serial0 = &uart10; + serial1 = &uart17; }; dmic: audio-codec-0 { @@ -149,6 +150,17 @@ regulator-max-microvolt = <2950000>; }; + vreg_dcin_12v: regulator-dcin-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_DCIN_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + regulator-boot-on; + regulator-always-on; + }; + vreg_sdc: regulator-vreg-sdc { compatible = "regulator-gpio"; @@ -162,6 +174,75 @@ startup-delay-us = <100>; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_dcin_12v>; + + regulator-boot-on; + }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + vddio-supply = <&vreg_wcn_3p3>; + vddaon-supply = <&vreg_wcn_3p3>; + vddpmu-supply = <&vreg_wcn_3p3>; + vddpmumx-supply = <&vreg_wcn_3p3>; + vddpmucx-supply = <&vreg_wcn_3p3>; + vddrfa0p95-supply = <&vreg_wcn_3p3>; + vddrfa1p3-supply = <&vreg_wcn_3p3>; + vddrfa1p9-supply = <&vreg_wcn_3p3>; + vddpcielp3-supply = <&vreg_wcn_3p3>; + vddpcielp9-supply = <&vreg_wcn_3p3>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -878,6 +959,24 @@ status = "okay"; }; +&uart17 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6855-bt"; + max-speed = <3200000>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l8a>; From 6f4d3c423bf075cdace00bcb5ed6e2faab6c9f7d Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Mon, 24 Nov 2025 14:55:17 +0530 Subject: [PATCH 0191/1330] FROMLIST: dt-bindings: phy: describe additional regulator for Qualcomm SGMII PHY Describe the additional vdda-0p9-supply for the Qualcomm SGMII PHY. Link: https://lore.kernel.org/r/20251124-sgmiieth_serdes_regulator-v1-1-73ae8f9cbe2a@oss.qualcomm.com Signed-off-by: Mohd Ayaan Anwar --- .../devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml index 90fc8c039219c..0a1330b9118d6 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml @@ -36,6 +36,10 @@ properties: description: Phandle to a regulator that provides power to the PHY. + vdda-0p9-supply: + description: + Phandle to a 0.9V regulator supply to the PHY. + "#phy-cells": const: 0 From a060b67f2ca6b2e5864d8072f14ca673c14961dd Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Mon, 24 Nov 2025 14:55:18 +0530 Subject: [PATCH 0192/1330] FROMLIST: arm64: dts: qcom: lemans-evk: add additional SerDes PHY regulator Add the additional 0.9V regulator for the Qualcomm SerDes PHY. Fixes: 71ee90ed1756 ("arm64: dts: qcom: lemans-evk: Enable 2.5G Ethernet interface") Link: https://lore.kernel.org/r/20251124-sgmiieth_serdes_regulator-v1-2-73ae8f9cbe2a@oss.qualcomm.com Signed-off-by: Mohd Ayaan Anwar --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index a227b6037b37c..b6403d9e5ef74 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -850,6 +850,7 @@ &serdes0 { phy-supply = <&vreg_l5a>; + vdda-0p9-supply = <&vreg_l4a>; status = "okay"; }; From 5cbe46181090c0795048a1a4fb0d1c7e2acae0aa Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Mon, 24 Nov 2025 14:55:19 +0530 Subject: [PATCH 0193/1330] FROMLIST: arm64: dts: qcom: lemans-ride-common: add additional SerDes PHY regulators Add the additional 0.9V regulators for both of the Qualcomm SerDes PHYs. Link: https://lore.kernel.org/r/20251124-sgmiieth_serdes_regulator-v1-3-73ae8f9cbe2a@oss.qualcomm.com Fixes: 5ef26fb8b3ed ("arm64: dts: qcom: sa8775p-ride: enable the SerDes PHY") Signed-off-by: Mohd Ayaan Anwar --- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 8fb7d1fc6d563..e020cc85089d3 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -787,11 +787,15 @@ &serdes0 { phy-supply = <&vreg_l5a>; + vdda-0p9-supply = <&vreg_l4a>; + status = "okay"; }; &serdes1 { phy-supply = <&vreg_l5a>; + vdda-0p9-supply = <&vreg_l4a>; + status = "okay"; }; From 016628630985b89d9a42631d06c9f62ab59b00c0 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 23 Dec 2025 18:02:24 +0530 Subject: [PATCH 0194/1330] FROMLIST: arm64: dts: qcom: Enable cdsp qmi tmd devices for lemans Enable cdsp cooling devices and thermal zone cooling map bindings for both cdsp and cdsp1. Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20251223123227.1317244-6-gaurav.kohli@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/lemans.dtsi | 137 ++++++++++++++++++++++++--- 1 file changed, 125 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 0abaeccffe966..b455b9d9348e5 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -7290,6 +7290,14 @@ }; }; }; + + cooling { + compatible = "qcom,qmi-cooling-cdsp"; + cdsp_sw0: cdsp_sw { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; }; nspb_noc: interconnect@2a0c0000 { @@ -7453,6 +7461,15 @@ }; }; }; + + + cooling { + compatible = "qcom,qmi-cooling-cdsp"; + cdsp_sw1: cdsp_sw { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; }; remoteproc_adsp: remoteproc@30000000 { @@ -8177,7 +8194,7 @@ thermal-sensors = <&tsens2 5>; trips { - trip-point0 { + nsp_0_0_0_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8189,6 +8206,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_0_0_alert0>; + cooling-device = <&cdsp_sw0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-0-1-0-thermal { @@ -8197,7 +8222,7 @@ thermal-sensors = <&tsens2 6>; trips { - trip-point0 { + nsp_0_1_0_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8209,6 +8234,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_1_0_alert0>; + cooling-device = <&cdsp_sw0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-0-2-0-thermal { @@ -8217,7 +8250,7 @@ thermal-sensors = <&tsens2 7>; trips { - trip-point0 { + nsp_0_2_0_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8229,6 +8262,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_2_0_alert0>; + cooling-device = <&cdsp_sw0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-1-0-0-thermal { @@ -8237,7 +8278,7 @@ thermal-sensors = <&tsens2 8>; trips { - trip-point0 { + nsp_1_0_0_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8249,6 +8290,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_1_0_0_alert0>; + cooling-device = <&cdsp_sw1 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-1-1-0-thermal { @@ -8257,7 +8306,7 @@ thermal-sensors = <&tsens2 9>; trips { - trip-point0 { + nsp_1_1_0_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8269,6 +8318,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_1_1_0_alert0>; + cooling-device = <&cdsp_sw1 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-1-2-0-thermal { @@ -8277,7 +8334,7 @@ thermal-sensors = <&tsens2 10>; trips { - trip-point0 { + nsp_1_2_0_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8289,6 +8346,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_1_2_0_alert0>; + cooling-device = <&cdsp_sw1 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; ddrss-0-thermal { @@ -8431,7 +8496,7 @@ thermal-sensors = <&tsens3 5>; trips { - trip-point0 { + nsp_0_0_1_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8443,6 +8508,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_0_1_alert0>; + cooling-device = <&cdsp_sw0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-0-1-1-thermal { @@ -8451,7 +8524,7 @@ thermal-sensors = <&tsens3 6>; trips { - trip-point0 { + nsp_0_1_1_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8463,6 +8536,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_1_1_alert0>; + cooling-device = <&cdsp_sw0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-0-2-1-thermal { @@ -8471,7 +8552,7 @@ thermal-sensors = <&tsens3 7>; trips { - trip-point0 { + nsp_0_2_1_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8483,6 +8564,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_2_1_alert0>; + cooling-device = <&cdsp_sw0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-1-0-1-thermal { @@ -8491,7 +8580,7 @@ thermal-sensors = <&tsens3 8>; trips { - trip-point0 { + nsp_1_0_1_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8503,6 +8592,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_1_0_1_alert0>; + cooling-device = <&cdsp_sw1 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-1-1-1-thermal { @@ -8511,7 +8608,7 @@ thermal-sensors = <&tsens3 9>; trips { - trip-point0 { + nsp_1_1_1_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8523,6 +8620,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_1_1_1_alert0>; + cooling-device = <&cdsp_sw1 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-1-2-1-thermal { @@ -8531,7 +8636,7 @@ thermal-sensors = <&tsens3 10>; trips { - trip-point0 { + nsp_1_2_1_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8543,6 +8648,14 @@ type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_1_2_1_alert0>; + cooling-device = <&cdsp_sw1 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; ddrss-1-thermal { From cbc98443ab713c6abc152a08c63b5383ba3d6bd8 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Thu, 22 Jan 2026 14:58:51 +0530 Subject: [PATCH 0195/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Rename hd3ss3220_ instance for primary port controller Rename the hd3ss3220_ instance to improve clarity and simplify usage when adding a secondary port controller. Link: https://lore.kernel.org/r/20260122092852.887624-4-swati.agarwal@oss.qualcomm.com Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index b6403d9e5ef74..cc7fed3e3a158 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -63,7 +63,7 @@ reg = <1>; usb0_con_ss_ep: endpoint { - remote-endpoint = <&hd3ss3220_in_ep>; + remote-endpoint = <&hd3ss3220_0_in_ep>; }; }; }; @@ -603,7 +603,7 @@ port@0 { reg = <0>; - hd3ss3220_in_ep: endpoint { + hd3ss3220_0_in_ep: endpoint { remote-endpoint = <&usb0_con_ss_ep>; }; }; @@ -611,7 +611,7 @@ port@1 { reg = <1>; - hd3ss3220_out_ep: endpoint { + hd3ss3220_0_out_ep: endpoint { remote-endpoint = <&usb_0_dwc3_ss>; }; }; @@ -1004,7 +1004,7 @@ }; &usb_0_dwc3_ss { - remote-endpoint = <&hd3ss3220_out_ep>; + remote-endpoint = <&hd3ss3220_0_out_ep>; }; &usb_0_hsphy { From 98dd9e0ba36a3d956909aac9981f2092818b21a8 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Thu, 22 Jan 2026 14:58:52 +0530 Subject: [PATCH 0196/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Enable secondary USB controller in host mode Enable secondary USB controller in host mode on lemans EVK Platform. Secondary USB controller is connected to a Genesys Logic USB HUB GL3590 having 4 ports. The ports of hub that are present on lemans EVK standalone board are used as follows:- 1) port-1 is connected to HD3SS3220 Type-C port controller. 2) port-4 is used for the M.2 E key on corekit. Standard core kit uses UART for Bluetooth. This port is to be used only if user optionally replaces the WiFi card with the NFA765 chip which uses USB for Bluetooth. Remaining 2 ports will become functional when the interface plus mezzanine board is stacked on top of corekit: 3) port-2 is connected to another hub which is present on the mezz through which 4 type-A ports are connected. 4) port-3 is used for the M.2 B key for a 5G card when the mezz is connected. Mark the second USB controller as host only capable and add the HD3SS3220 Type-C port controller along with Type-c connector for controlling vbus supply. Link: https://lore.kernel.org/r/20260122092852.887624-5-swati.agarwal@oss.qualcomm.com Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 208 ++++++++++++++++++++++++ 1 file changed, 208 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index cc7fed3e3a158..3a9f40a3e2a62 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -69,6 +69,45 @@ }; }; + connector-1 { + compatible = "usb-c-connector"; + label = "USB1-Type-C"; + data-role = "host"; + power-role = "source"; + + vbus-supply = <&vbus_supply_regulator_1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_con_ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_1_in_ep>; + }; + }; + + port@1 { + reg = <1>; + + usb1_hs_in: endpoint { + remote-endpoint = <&usb_hub_2_1>; + }; + + }; + + port@2 { + reg = <2>; + + usb1_ss_in: endpoint { + remote-endpoint = <&usb_hub_3_1>; + }; + }; + }; + }; + edp0-connector { compatible = "dp-connector"; label = "EDP0"; @@ -142,6 +181,16 @@ enable-active-high; }; + vbus_supply_regulator_1: regulator-vbus-supply-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus_supply_1"; + gpio = <&expander1 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + }; + vmmc_sdc: regulator-vmmc-sdc { compatible = "regulator-fixed"; @@ -617,6 +666,39 @@ }; }; }; + + usb-typec@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + + interrupts-extended = <&pmm8654au_2_gpios 6 IRQ_TYPE_EDGE_FALLING>; + + id-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb1_id>, <&usb1_intr>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_1_in_ep: endpoint { + remote-endpoint = <&usb1_con_ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_1_out_ep: endpoint { + }; + }; + }; + }; + }; &i2c18 { @@ -780,6 +862,14 @@ bias-pull-up; power-source = <0>; }; + + usb1_intr: usb1-intr-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; }; &qup_i2c19_default { @@ -950,6 +1040,12 @@ function = "gpio"; bias-pull-up; }; + + usb1_id: usb1-id-state { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + }; }; &uart10 { @@ -1022,6 +1118,118 @@ status = "okay"; }; +&usb_1 { + dr_mode = "host"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + usb_hub_2_x: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + + peer-hub = <&usb_hub_3_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_2_1: endpoint { + remote-endpoint = <&usb1_hs_in>; + }; + }; + + /* + * Port-2 and port-3 are not connected to anything on corekit. + */ + port@2 { + reg = <2>; + + usb_hub_2_2: endpoint { + }; + }; + + port@3 { + reg = <3>; + + usb_hub_2_3: endpoint { + }; + }; + + /* + * Port-4 is connected to M.2 E key connector on corekit. + */ + port@4 { + reg = <4>; + + usb_hub_2_4: endpoint { + }; + }; + }; + }; + + usb_hub_3_x: hub@2 { + compatible = "usb5e3,625"; + reg = <2>; + + peer-hub = <&usb_hub_2_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_3_1: endpoint { + remote-endpoint = <&usb1_ss_in>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_3_2: endpoint { + }; + }; + + port@3 { + reg = <3>; + + usb_hub_3_3: endpoint { + }; + }; + + port@4 { + reg = <4>; + + usb_hub_3_4: endpoint { + }; + }; + }; + }; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; From f2db5cd46027c385a0cf4d2ea1e2c18ba19f253b Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Mon, 12 Jan 2026 13:05:20 +0530 Subject: [PATCH 0197/1330] WORKAROUND: arm64: dts: qcom: lemans-evk: Remove WCN6855 PMU node to bypass pwrseq flow There is a conflict between the current DTS configuration and the driver behavior for the WCN6855 Bluetooth path. With the PMU node in place, the driver takes the pwrseq code path unintentionally, which leads to Bluetooth failing to power up during an on -> off -> on transition. To unblock function, temporarily remove the WCN6855 PMU node so that the driver follows the non-pwrseq path and avoids the unexpected sequence. This is a TEMPORARY WORKAROUND. Once a proper M.2 binding/solution is upstreamed, will re-submit both DTS and driver changes aligned with the M.2 model. Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 73 +++---------------------- 1 file changed, 8 insertions(+), 65 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 3a9f40a3e2a62..ab4f50ac7e5e7 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -235,63 +235,6 @@ regulator-boot-on; }; - - wcn6855-pmu { - compatible = "qcom,wcn6855-pmu"; - - vddio-supply = <&vreg_wcn_3p3>; - vddaon-supply = <&vreg_wcn_3p3>; - vddpmu-supply = <&vreg_wcn_3p3>; - vddpmumx-supply = <&vreg_wcn_3p3>; - vddpmucx-supply = <&vreg_wcn_3p3>; - vddrfa0p95-supply = <&vreg_wcn_3p3>; - vddrfa1p3-supply = <&vreg_wcn_3p3>; - vddrfa1p9-supply = <&vreg_wcn_3p3>; - vddpcielp3-supply = <&vreg_wcn_3p3>; - vddpcielp9-supply = <&vreg_wcn_3p3>; - - regulators { - vreg_pmu_rfa_cmn: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn"; - }; - - vreg_pmu_aon_0p59: ldo1 { - regulator-name = "vreg_pmu_aon_0p59"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p85: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p85"; - }; - - vreg_pmu_btcmx_0p85: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p85"; - }; - - vreg_pmu_rfa_0p8: ldo5 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; - - vreg_pmu_rfa_1p2: ldo6 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; - - vreg_pmu_rfa_1p8: ldo7 { - regulator-name = "vreg_pmu_rfa_1p8"; - }; - - vreg_pmu_pcie_0p9: ldo8 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; - - vreg_pmu_pcie_1p8: ldo9 { - regulator-name = "vreg_pmu_pcie_1p8"; - }; - }; - }; }; &apps_rsc { @@ -1063,14 +1006,14 @@ compatible = "qcom,wcn6855-bt"; max-speed = <3200000>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddrfacmn-supply = <&vreg_wcn_3p3>; + vddaon-supply = <&vreg_wcn_3p3>; + vddwlcx-supply = <&vreg_wcn_3p3>; + vddwlmx-supply = <&vreg_wcn_3p3>; + vddbtcmx-supply = <&vreg_wcn_3p3>; + vddrfa0p8-supply = <&vreg_wcn_3p3>; + vddrfa1p2-supply = <&vreg_wcn_3p3>; + vddrfa1p8-supply = <&vreg_wcn_3p3>; }; }; From 03c7283bf6069e2f5dab07ce215df69f0b92c81d Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Tue, 27 Jan 2026 14:01:00 +0530 Subject: [PATCH 0198/1330] FROMLIST: arm64: dts: qcom: lemans: disable zap-shader for EL2 configuration We don't need to use zap shader in EL2 as Linux can zap the gpu on it's own. Lets disable zap-shader for Lemans EL2 configuration. Link: https://lore.kernel.org/lkml/20260127-talos-el2-overlay-v2-1-b6a2266532c4@oss.qualcomm.com/ Signed-off-by: Mukesh Ojha --- arch/arm64/boot/dts/qcom/lemans-el2.dtso | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-el2.dtso b/arch/arm64/boot/dts/qcom/lemans-el2.dtso index ed615dce6c789..621ad930cf547 100644 --- a/arch/arm64/boot/dts/qcom/lemans-el2.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-el2.dtso @@ -10,6 +10,10 @@ /dts-v1/; /plugin/; +&gpu_zap_shader { + status = "disabled"; +}; + &iris { status = "disabled"; }; From b1392ca0e45b54bb4f07e2632258804ff273603f Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 9 Nov 2025 20:07:24 +0530 Subject: [PATCH 0199/1330] FROMLIST: arm64: dts: qcom: monaco: Add PSCI SYSTEM_RESET2 types Add support for SYSTEM_RESET2 vendor-specific resets as reboot-modes in the psci node. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-11-46e085bca4cc@oss.qualcomm.com Signed-off-by: Shivendra Pratap --- arch/arm64/boot/dts/qcom/monaco.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 1d7fbc34c3135..a0a6f0ea56cde 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -740,6 +740,11 @@ #power-domain-cells = <0>; domain-idle-states = <&system_sleep>; }; + + reboot-mode { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; }; reserved-memory { From 564cb3509acf6086ed826c47227189cd915525c3 Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Wed, 26 Nov 2025 13:40:56 +0530 Subject: [PATCH 0200/1330] FROMLIST: arm64: dts: qcom: qcs8300: Add CCI definitions Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI). Compared to Lemans, the key difference is in SDA/SCL GPIO assignments and number of CCIs. Link: https://lore.kernel.org/r/20251126081057.4191122-3-quic_vikramsa@quicinc.com Signed-off-by: Nihal Kumar Gupta Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Co-developed-by: Suresh Vankadara Signed-off-by: Suresh Vankadara Signed-off-by: Vikram Sharma Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/monaco.dtsi | 345 +++++++++++++++++++++++++++ 1 file changed, 345 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index a0a6f0ea56cde..cecfd0bd76d87 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5329,6 +5329,117 @@ #power-domain-cells = <1>; }; + cci0: cci@ac13000 { + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac13000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_0_default &cci0_1_default>; + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac14000 { + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac14000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_0_default &cci1_1_default>; + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci2: cci@ac15000 { + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac15000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names = "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci2_0_default &cci2_1_default>; + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: isp@ac78000 { compatible = "qcom,qcs8300-camss"; @@ -5886,6 +5997,240 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam0_default: cam0-default-state { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam1_default: cam1-default-state { + pins = "gpio68"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state { + pins = "gpio75"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam2_default: cam2-default-state { + pins = "gpio69"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cci0_0_default: cci0-0-default-state { + sda-pins { + pins = "gpio57"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio58"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins = "gpio57"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio58"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins = "gpio29"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio30"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins = "gpio29"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio30"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins = "gpio59"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio60"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins = "gpio59"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio60"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins = "gpio31"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio32"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins = "gpio31"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio32"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_0_default: cci2-0-default-state { + sda-pins { + pins = "gpio61"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio62"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci2_0_sleep: cci2-0-sleep-state { + sda-pins { + pins = "gpio61"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio62"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_1_default: cci2-1-default-state { + sda-pins { + pins = "gpio54"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio55"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci2_1_sleep: cci2-1-sleep-state { + sda-pins { + pins = "gpio54"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio55"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins = "gpio106", "gpio107", "gpio108", "gpio109"; function = "hs0_mi2s"; From db1cde89fc325cde61917d502d762881408d4f07 Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Wed, 26 Nov 2025 13:40:57 +0530 Subject: [PATCH 0201/1330] FROMLIST: arm64: dts: qcom: monaco-evk-camera: Add DT overlay Monaco EVK board does not include a camera sensor in its default hardware configuration. Introducing a device tree overlay to support optional integration of the IMX577 sensor via CSIPHY1. Camera reset is handled through an I2C expander, and power is enabled via TLMM GPIO74. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -V '"imx577 3-001a":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy1":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy1":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video1 Link: https://lore.kernel.org/r/20251126081057.4191122-4-quic_vikramsa@quicinc.com Signed-off-by: Nihal Kumar Gupta Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Signed-off-by: Vikram Sharma Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/Makefile | 4 ++ .../dts/qcom/monaco-evk-camera-imx577.dtso | 67 +++++++++++++++++++ arch/arm64/boot/dts/qcom/monaco-evk.dts | 10 +++ 3 files changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1303bd82723d1..759d7ad1c9ae6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -45,6 +45,10 @@ lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb + +monaco-evk-camera-imx577-dtbs := monaco-evk.dtb monaco-evk-camera-imx577.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso new file mode 100644 index 0000000000000..351eb5ee70ba8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 = <&cci1_0_default>; + pinctrl-1 = <&cci1_0_sleep>; + + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&expander2 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam1_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vreg_cam1_2p8>; + + port { + imx577_ep1: endpoint { + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 565418b86b2ad..e2aba68e5fac4 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -77,6 +77,16 @@ }; }; }; + + vreg_cam1_2p8: vreg-cam1-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1_2p8"; + startup-delay-us = <10000>; + enable-active-high; + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&cam1_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; }; &apps_rsc { From 77bc95913d53d9d00e2224223cbf69b7cfc32c60 Mon Sep 17 00:00:00 2001 From: Wei Zhang Date: Tue, 24 Feb 2026 23:14:59 -0800 Subject: [PATCH 0202/1330] FROMLIST: arm64: dts: qcom: qcs8300-ride: enable WLAN on qcs8300-ride Enable WLAN on qcs8300-ride by adding a node for the PMU module of the WCN6855 and assigning its LDO power outputs to the existing WiFi module. On the qcs8300-ride platform, the corresponding firmware and BDF are QCA6698AQ instead of WCN6855, which have been added in the 20250211 release. Link: https://lore.kernel.org/r/20260225071459.1600394-1-wei.zhang@oss.qualcomm.com Signed-off-by: Wei Zhang Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 130 ++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index c04e0ad53eecf..2ed1015b3465a 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -36,6 +36,50 @@ }; }; + vreg_conn_1p05: regulator-conn-1p05 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + vin-supply = <&vreg_conn_1p8>; + }; + + vreg_conn_1p35: regulator-conn-1p35 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + vin-supply = <&vreg_conn_1p8>; + }; + + vreg_conn_1p8: regulator-conn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pmm8650au_1_gpios 4 GPIO_ACTIVE_HIGH>; + }; + + vreg_conn_1p95: regulator-conn-1p95 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p95"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + vin-supply = <&vreg_conn_1p8>; + }; + + vreg_conn_pa: regulator-conn-pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pmm8650au_1_gpios 6 GPIO_ACTIVE_HIGH>; + }; + regulator-usb2-vbus { compatible = "regulator-fixed"; regulator-name = "USB2_VBUS"; @@ -45,6 +89,69 @@ enable-active-high; regulator-always-on; }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + pinctrl-0 = <&wlan_en_state>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_conn_pa>; + vddaon-supply = <&vreg_conn_1p8>; + vddpmu-supply = <&vreg_conn_pa>; + vddpmumx-supply = <&vreg_conn_1p8>; + vddpmucx-supply = <&vreg_conn_pa>; + /* WLAN rails: 1.05/1.35/1.95V (nominal 0.95/1.30/1.90V) */ + vddrfa0p95-supply = <&vreg_conn_1p05>; + vddrfa1p3-supply = <&vreg_conn_1p35>; + vddrfa1p9-supply = <&vreg_conn_1p95>; + vddpcie1p3-supply = <&vreg_conn_1p35>; + vddpcie1p9-supply = <&vreg_conn_1p95>; + + wlan-enable-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -363,6 +470,23 @@ &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + + qcom,calibration-variant = "QC_QCS8300_Ride"; + }; }; &pcie0_phy { @@ -503,6 +627,12 @@ function = "edp0_hot"; bias-disable; }; + + wlan_en_state: wlan-en-state { + pins = "gpio54"; + function = "gpio"; + bias-pull-down; + }; }; &uart7 { From 3183112467b4b8176cc3f0ac17ad706f1c4ed83a Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Thu, 13 Nov 2025 18:35:19 +0530 Subject: [PATCH 0203/1330] FROMLIST: arm64: dts: qcom: monaco-evk: Enable Bluetooth support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's a WCN6855 WiFi/Bluetooth module on an M.2 card. To make Bluetooth work, we need to define the necessary device tree nodes, including UART configuration and power supplies. Since there is no standard M.2 binding in the device tree at present, the PMU is described using dedicated PMU nodes to represent the internal regulators required by the module. The module provides a 3.3V supply, which originates from the main board’s 12V rail. To represent this power hierarchy in the device tree, add a fixed 12V regulator node as the DC-IN source and link it to the 3.3V regulator node. Link: https://lore.kernel.org/all/20251113130519.2647081-1-wei.deng@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 99 +++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index e2aba68e5fac4..833089e5f511a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -21,6 +21,7 @@ ethernet0 = ðernet0; i2c1 = &i2c1; serial0 = &uart7; + serial1 = &uart2; }; chosen { @@ -87,6 +88,86 @@ pinctrl-0 = <&cam1_avdd_2v8_en_default>; pinctrl-names = "default"; }; + + vreg_dcin_12v: regulator-dcin-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_DCIN_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_dcin_12v>; + + regulator-boot-on; + }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + vddio-supply = <&vreg_wcn_3p3>; + vddaon-supply = <&vreg_wcn_3p3>; + vddpmu-supply = <&vreg_wcn_3p3>; + vddpmumx-supply = <&vreg_wcn_3p3>; + vddpmucx-supply = <&vreg_wcn_3p3>; + vddrfa0p95-supply = <&vreg_wcn_3p3>; + vddrfa1p3-supply = <&vreg_wcn_3p3>; + vddrfa1p9-supply = <&vreg_wcn_3p3>; + vddpcielp3-supply = <&vreg_wcn_3p3>; + vddpcielp9-supply = <&vreg_wcn_3p3>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -582,6 +663,24 @@ }; }; +&uart2 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6855-bt"; + max-speed = <3200000>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &uart7 { status = "okay"; }; From e9812201f6bbc594ffeb1b6a3ed6f4f258c13a26 Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Thu, 13 Nov 2025 12:10:10 +0530 Subject: [PATCH 0204/1330] FROMLIST: arm64: dts: qcom: qcs8300-ride: Enable Bluetooth support Enable BT on qcs8300-ride by adding a BT device tree node. Since the platform uses the QCA6698 Bluetooth chip. While the QCA6698 shares the same IP core as the WCN6855, it has different RF components and RAM sizes, requiring new firmware files. Use the firmware-name property to specify the NVM and rampatch firmware to load. Link: https://lore.kernel.org/all/20251118140406.1551669-2-wei.deng@oss.qualcomm.com/ Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 2ed1015b3465a..a0ac926d2006f 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -18,6 +18,7 @@ aliases { serial0 = &uart7; mmc0 = &sdhc_1; + serial1 = &uart2; }; chosen { @@ -108,6 +109,8 @@ vddpcie1p3-supply = <&vreg_conn_1p35>; vddpcie1p9-supply = <&vreg_conn_1p95>; + + bt-enable-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; wlan-enable-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; regulators { @@ -583,6 +586,13 @@ }; }; + bt_en_state: bt-en-state { + pins = "gpio55"; + function = "gpio"; + bias-pull-down; + output-low; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; @@ -635,6 +645,25 @@ }; }; +&uart2 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6855-bt"; + firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv"; + max-speed = <3200000>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + &uart7 { status = "okay"; }; From 452157ae4e994f3688cd4e6e8cd9faa58ff1b64a Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Tue, 17 Feb 2026 14:39:54 +0530 Subject: [PATCH 0205/1330] FROMLIST: arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes Add device tree nodes for the DSI0 controller with their corresponding PHY found on Qualcomm QCS8300 SoC. Link: https://lore.kernel.org/r/20260217090955.2446470-2-quic_amakhija@quicinc.com Signed-off-by: Ayushi Makhija Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/monaco.dtsi | 107 ++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index cecfd0bd76d87..8fc995645a871 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -5694,9 +5695,19 @@ reg = <0>; dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; }; }; + + port@1 { + reg = <1>; + + dpu_intf1_out: endpoint { + + remote-endpoint = <&mdss_dsi0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -5724,6 +5735,98 @@ }; }; + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,qcs8300-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + refgen-supply = <&refgen>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,qcs8300-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg = <0x0 0x0ae94400 0x0 0x200>, + <0x0 0x0ae94600 0x0 0x280>, + <0x0 0x0ae94900 0x0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + status = "disabled"; + }; + mdss_dp0_phy: phy@aec2a00 { compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; @@ -5851,7 +5954,9 @@ <&mdss_dp0_phy 0>, <&mdss_dp0_phy 1>, <0>, <0>, - <0>, <0>, <0>, <0>; + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; #clock-cells = <1>; #reset-cells = <1>; From 6346b5bd1371e6354fdd8488c08c4a36a98ea18b Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Tue, 17 Feb 2026 14:39:55 +0530 Subject: [PATCH 0206/1330] FROMLIST: arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node Add anx7625 DSI to DP bridge device node. Link: https://lore.kernel.org/r/20260217090955.2446470-3-quic_amakhija@quicinc.com Signed-off-by: Ayushi Makhija Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 179 ++++++++++++++++++++++ 1 file changed, 179 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index a0ac926d2006f..ec8991923f2ab 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -25,6 +25,69 @@ stdout-path = "serial0:115200n8"; }; + vreg_1p0: regulator-vreg-1p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P0"; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + vin-supply = <&vreg_1p8>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_5p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_3p0: regulator-vreg-3p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_3P0"; + + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&vreg_12p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_5p0: regulator-vreg-5p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_5P0"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vreg_12p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_12p0: regulator-vreg-12p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_12P0"; + + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + regulator-always-on; + regulator-boot-on; + }; + dp0-connector { compatible = "dp-connector"; label = "DP0"; @@ -37,6 +100,18 @@ }; }; + dp-dsi0-connector { + compatible = "dp-connector"; + label = "DSI0"; + type = "full-size"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint = <&dsi2dp_bridge_out>; + }; + }; + }; + vreg_conn_1p05: regulator-conn-1p05 { compatible = "regulator-fixed"; regulator-name = "vreg_conn_1p05"; @@ -426,6 +501,75 @@ firmware-name = "qcom/qcs8300/a623_zap.mbn"; }; +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + io_expander: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + interrupts-extended = <&tlmm 93 IRQ_TYPE_EDGE_BOTH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&io_expander_intr_active>, + <&io_expander_reset_active>; + pinctrl-names = "default"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + bridge@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupts-extended = <&io_expander 2 IRQ_TYPE_EDGE_FALLING>; + enable-gpios = <&io_expander 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&vreg_1p0>; + vdd18-supply = <&vreg_1p8>; + vdd33-supply = <&vreg_3p0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_bridge_in: endpoint { + + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_bridge_out: endpoint { + + remote-endpoint = <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + &pmm8650au_1_gpios { usb2_en: usb2-en-state { pins = "gpio7"; @@ -518,10 +662,31 @@ status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&dsi2dp_bridge_in>; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/qcs8300/adsp.mbn"; status = "okay"; @@ -632,6 +797,20 @@ }; }; + io_expander_reset_active: io-expander-reset-active-state { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + io_expander_intr_active: io-expander-intr-active-state { + pins = "gpio93"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + dp_hot_plug_det: dp-hot-plug-det-state { pins = "gpio94"; function = "edp0_hot"; From 3aecfa9aac16a5bc8a473ffcc5ef5e78465de3e6 Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Sun, 28 Dec 2025 19:10:38 +0530 Subject: [PATCH 0207/1330] FROMLIST: arm64: dts: qcom: monaco: add lt8713sx bridge with displayport Monaco-evk has LT8713sx which act as DP to 3 DP output converter. Edp PHY from monaco soc is connected to lt8713sx as input and output of lt8713sx is connected to 3 mini DP ports. Two ports are available in mainboard and one port is available on Mezz board. lt8713sx is connected to soc over i2c0 and with reset gpio connected to pin6 of ioexpander5. Enable the edp nodes from monaco and enable lontium lt8713sx bridge node. Link: https://lore.kernel.org/r/20251228-lt8713sx-bridge-linux-for-next-v3-1-3f77ad84d7d1@oss.qualcomm.com Co-developed-by: Prahlad Valluru Signed-off-by: Prahlad Valluru Signed-off-by: Vishnu Saini --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 89 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/monaco.dtsi | 6 ++ 2 files changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 833089e5f511a..435291f9efb86 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -34,6 +34,30 @@ num-channels = <1>; }; + dp-connector0 { + compatible = "dp-connector"; + label = "DP"; + type = "mini"; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <<8713sx_dp0_out>; + }; + }; + }; + + dp-connector1 { + compatible = "dp-connector"; + label = "DP"; + type = "mini"; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <<8713sx_dp1_out>; + }; + }; + }; + max98357a: audio-codec-1 { compatible = "maxim,max98357a"; #sound-dai-cells = <0>; @@ -409,6 +433,42 @@ firmware-name = "qcom/qcs8300/a623_zap.mbn"; }; +&i2c0 { + status = "okay"; + + bridge@4f { + compatible = "lontium,lt8713sx"; + reg = <0x4f>; + reset-gpios = <&expander5 6 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt8713sx_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + + port@1 { + reg = <1>; + lt8713sx_dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + + port@2 { + reg = <2>; + lt8713sx_dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; + }; + }; +}; + &i2c1 { pinctrl-0 = <&qup_i2c1_default>; pinctrl-names = "default"; @@ -498,6 +558,30 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <<8713sx_dp_in>; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + &iris { status = "okay"; }; @@ -540,6 +624,11 @@ wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; }; +&qup_i2c0_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + &qupv3_id_0 { firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 8fc995645a871..09a81556c8b53 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -6336,6 +6336,12 @@ }; }; + dp_hot_plug_det: dp-hot-plug-det-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins = "gpio106", "gpio107", "gpio108", "gpio109"; function = "hs0_mi2s"; From 1a77fbe11adee646e4a1ddf7593f2a967617a4a2 Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Mon, 24 Nov 2025 14:55:20 +0530 Subject: [PATCH 0208/1330] FROMLIST: arm64: dts: qcom: monaco-evk: fix the SerDes PHY regulators The Qualcomm SerDes PHY, present on multiple boards, has two regulators providing supplies of 1.2V (L5A) and 0.9V (L4A). Update the node to reflect the same instead of incorrectly voting for only L4A. Link: https://lore.kernel.org/r/20251124-sgmiieth_serdes_regulator-v1-4-73ae8f9cbe2a@oss.qualcomm.com Fixes: 117d6bc9326b ("arm64: dts: qcom: qcs8300: Add Monaco EVK board") Signed-off-by: Mohd Ayaan Anwar --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 435291f9efb86..ace3b3e42d9ef 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -658,7 +658,8 @@ }; &serdes0 { - phy-supply = <&vreg_l4a>; + phy-supply = <&vreg_l5a>; + vdda-0p9-supply = <&vreg_l4a>; status = "okay"; }; From 25d8fe691765a73f8c47a2ee7cc6f3bbb3065146 Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Mon, 24 Nov 2025 14:55:21 +0530 Subject: [PATCH 0209/1330] FROMLIST: arm64: dts: qcom: qcs8300-ride: add additional SerDes PHY regulator Add the additional 0.9V regulator for the Qualcomm SerDes PHY. Link: https://lore.kernel.org/r/20251124-sgmiieth_serdes_regulator-v1-5-73ae8f9cbe2a@oss.qualcomm.com Fixes: 787cb3b4c434 ("arm64: dts: qcom: qcs8300-ride: enable ethernet0") Signed-off-by: Mohd Ayaan Anwar --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index ec8991923f2ab..5866a5144457f 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -704,6 +704,8 @@ &serdes0 { phy-supply = <&vreg_l5a>; + vdda-0p9-supply = <&vreg_l4a>; + status = "okay"; }; From a9a4574c2cf894b5352c4087f76d45af14742024 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 27 Nov 2025 17:28:29 +0530 Subject: [PATCH 0210/1330] QCLINUX: arch: arm64: qcom: qcs8300-ride: Enable PCIe Qref regulator PCIe phy needs to be voted for QREF regulator, As the base dtsi changes are still pending we haven't posted the actual fix. Till we post actual fix to upstream, use this change as a workaround. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 5866a5144457f..2b9bfba793b34 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -638,7 +638,7 @@ &pcie0_phy { vdda-phy-supply = <&vreg_l6a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; status = "okay"; }; From fdfbc3b40ecd7f7faa75f5a9e3ca2b313f2ccfa3 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Wed, 3 Dec 2025 14:13:57 +0530 Subject: [PATCH 0211/1330] FROMLIST: arm64: dts: qcom: Enable cdsp qmi tmd devices for monaco Enable cdsp cooling devices and thermal zone cooling map bindings for cdsp. Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/all/20251223123227.1317244-9-gaurav.kohli@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/monaco.dtsi | 92 ++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 09a81556c8b53..01f5d73b31316 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -7660,6 +7660,14 @@ }; }; }; + + cooling { + compatible = "qcom,qmi-cooling-cdsp"; + cdsp_sw: cdsp_sw { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; }; }; @@ -7994,36 +8002,78 @@ thermal-sensors = <&tsens2 5>; trips { + nsp_0_0_0_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_0_0_alert0>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-0-1-0-thermal { thermal-sensors = <&tsens2 6>; trips { + nsp_0_1_0_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_1_0_alert0>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-0-2-0-thermal { thermal-sensors = <&tsens2 7>; trips { + nsp_0_2_0_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_2_0_alert0>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; ddrss-0-thermal { @@ -8114,36 +8164,78 @@ thermal-sensors = <&tsens3 5>; trips { + nsp_0_0_1_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_0_1_alert0>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-0-1-1-thermal { thermal-sensors = <&tsens3 6>; trips { + nsp_0_1_1_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_1_1_alert0>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-0-2-1-thermal { thermal-sensors = <&tsens3 7>; trips { + nsp_0_2_1_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&nsp_0_2_1_alert0>; + cooling-device = <&cdsp_sw + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; ddrss-1-thermal { From 6b9d6d23c66f528a9a4d7ad0e0505a386c1acc68 Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Wed, 21 Jan 2026 11:37:55 +0530 Subject: [PATCH 0212/1330] WORKAROUND: arm64: dts: qcom: monaco-evk: Remove WCN6855 PMU node to bypass pwrseq flow There is a conflict between the current DTS configuration and the driver behavior for the WCN6855 Bluetooth path. With the PMU node in place, the driver takes the pwrseq code path unintentionally, which leads to Bluetooth failing to power up during an on -> off -> on transition. To unblock function, temporarily remove the WCN6855 PMU node so that the driver follows the non-pwrseq path and avoids the unexpected sequence. This is a TEMPORARY WORKAROUND. Once a proper M.2 binding/solution is upstreamed, will re-submit both DTS and driver changes aligned with the M.2 model. Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 73 +++---------------------- 1 file changed, 8 insertions(+), 65 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index ace3b3e42d9ef..acf2e7c36f143 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -135,63 +135,6 @@ regulator-boot-on; }; - - wcn6855-pmu { - compatible = "qcom,wcn6855-pmu"; - - vddio-supply = <&vreg_wcn_3p3>; - vddaon-supply = <&vreg_wcn_3p3>; - vddpmu-supply = <&vreg_wcn_3p3>; - vddpmumx-supply = <&vreg_wcn_3p3>; - vddpmucx-supply = <&vreg_wcn_3p3>; - vddrfa0p95-supply = <&vreg_wcn_3p3>; - vddrfa1p3-supply = <&vreg_wcn_3p3>; - vddrfa1p9-supply = <&vreg_wcn_3p3>; - vddpcielp3-supply = <&vreg_wcn_3p3>; - vddpcielp9-supply = <&vreg_wcn_3p3>; - - regulators { - vreg_pmu_rfa_cmn: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn"; - }; - - vreg_pmu_aon_0p59: ldo1 { - regulator-name = "vreg_pmu_aon_0p59"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p85: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p85"; - }; - - vreg_pmu_btcmx_0p85: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p85"; - }; - - vreg_pmu_rfa_0p8: ldo5 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; - - vreg_pmu_rfa_1p2: ldo6 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; - - vreg_pmu_rfa_1p8: ldo7 { - regulator-name = "vreg_pmu_rfa_1p8"; - }; - - vreg_pmu_pcie_0p9: ldo8 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; - - vreg_pmu_pcie_1p8: ldo9 { - regulator-name = "vreg_pmu_pcie_1p8"; - }; - }; - }; }; &apps_rsc { @@ -760,14 +703,14 @@ compatible = "qcom,wcn6855-bt"; max-speed = <3200000>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddrfacmn-supply = <&vreg_wcn_3p3>; + vddaon-supply = <&vreg_wcn_3p3>; + vddwlcx-supply = <&vreg_wcn_3p3>; + vddwlmx-supply = <&vreg_wcn_3p3>; + vddbtcmx-supply = <&vreg_wcn_3p3>; + vddrfa0p8-supply = <&vreg_wcn_3p3>; + vddrfa1p2-supply = <&vreg_wcn_3p3>; + vddrfa1p8-supply = <&vreg_wcn_3p3>; }; }; From 7f542de8d546509c4af1072808df3161ad21915a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 19 Jan 2026 13:51:00 +0530 Subject: [PATCH 0213/1330] FROMLIST: arm64: dts: qcom: monaco: Add EL2 overlay All the Monaco IOT variants boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Monaco IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Link: https://lore.kernel.org/lkml/20260127-talos-el2-overlay-v2-2-b6a2266532c4@oss.qualcomm.com/ Signed-off-by: Mukesh Ojha --- arch/arm64/boot/dts/qcom/Makefile | 8 +++++++ arch/arm64/boot/dts/qcom/monaco-el2.dtso | 29 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 759d7ad1c9ae6..530db9f71be06 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -46,6 +46,10 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb +monaco-evk-el2-dtbs := monaco-evk.dtb monaco-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-el2.dtb + monaco-evk-camera-imx577-dtbs := monaco-evk.dtb monaco-evk-camera-imx577.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb @@ -151,6 +155,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb + +qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-el2.dtso b/arch/arm64/boot/dts/qcom/monaco-el2.dtso new file mode 100644 index 0000000000000..a7e3270f86090 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-el2.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Monaco specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +&gpu_zap_shader { + status = "disabled"; +}; + +&iris { + status = "disabled"; +}; + +&remoteproc_adsp { + iommus = <&apps_smmu 0x2000 0x0>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x19c0 0x0400>; +}; + +&remoteproc_gpdsp { + iommus = <&apps_smmu 0x28a0 0x0>; +}; From 94ac917e9a79c9d9cede0638c6ffe73573f7285d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 5 Feb 2026 15:35:49 +0530 Subject: [PATCH 0214/1330] WORKAROUND: arm64: dts: qcom: monaco: Disable global IRQ for pcie1 Currently pcie1 global IRQ is blocking a CPU core, due to which ufs is getting blocked and failing. As workaround disable PCIe1 global IRQ for now. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 01f5d73b31316..934a97001f6ce 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2487,8 +2487,7 @@ , , , - , - ; + ; interrupt-names = "msi0", "msi1", "msi2", @@ -2496,8 +2495,7 @@ "msi4", "msi5", "msi6", - "msi7", - "global"; + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, From a6faa9b7a066d90c7457056b12eb5b6db837cd1c Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 13 Jan 2026 19:00:16 +0530 Subject: [PATCH 0215/1330] QCLINUX: drivers: increase deferred probe timeout Certain drivers were failing to probe during boot because their dependencies were not ready within the default deferred probe timeout. To address this, increase the deferred probe timeout to allow dependent drivers sufficient time to register and avoid probe failures during system startup. Signed-off-by: Komal Bajaj --- drivers/base/dd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/dd.c b/drivers/base/dd.c index ec7ef9c5d62e1..1841218ee03f3 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -258,7 +258,7 @@ static int deferred_devs_show(struct seq_file *s, void *data) DEFINE_SHOW_ATTRIBUTE(deferred_devs); #ifdef CONFIG_MODULES -static int driver_deferred_probe_timeout = 10; +static int driver_deferred_probe_timeout = 15; #else static int driver_deferred_probe_timeout; #endif From d157d7b2d456812358f7863cbf400c7f196f7e07 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 8 Jan 2026 09:42:56 +0530 Subject: [PATCH 0216/1330] QCLINUX: PCI: Disable L1ss through quirk for Qualcomm SA8775P When PCIe L1ss is enabled, WLAN functionality is completly broken. There are some connectivity issues in this platform mostly with CLKREQ# pin. Disable L1ss as workaround untill actual issue get resolved. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/quirks.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index cdb6271397f6a..bcdf8b51d183b 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2553,6 +2553,12 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1); +static void quirk_disable_aspm_l1ss(struct pci_dev *dev) +{ + pci_disable_link_state(dev, PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_2); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QCOM, 0x1103, quirk_disable_aspm_l1ss); + /* * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain * Link bit cleared after starting the link retrain process to allow this From f03c946fc7d076c4e8f4691b1f3a567adebecb67 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 4 Feb 2026 21:40:53 +0530 Subject: [PATCH 0217/1330] WORKAROUND: arm64: dts: qcom: lemans: Disable global IRQ for pcie1 Currently pcie1 global IRQ is blocking a CPU core, due to which ufs is getting blocked and failing. As workaround disable PCIe1 global IRQ for now. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index b455b9d9348e5..e202558085783 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -8919,8 +8919,7 @@ , , , - , - ; + ; interrupt-names = "msi0", "msi1", "msi2", @@ -8928,8 +8927,7 @@ "msi4", "msi5", "msi6", - "msi7", - "global"; + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, From 3ab4c43613996c158732a57ddd8c64ca80d59522 Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Sat, 7 Feb 2026 17:55:39 +0530 Subject: [PATCH 0218/1330] WORKAROUND: scsi: ufs: core: Set uic_cmd_timeout to max It is obsrved that qcs9100-ride fails to boot intermittently due to ufs cmd timeouts. The timeout happens as the ufs threaded-irq fails to schedule within the default UIC_CMD_TIMEOUT_DEFAULT (500 msec) due to console logs spewing at the same moment. Increase timeout to max for now to UIC_CMD_TIMEOUT_MAX (5000 msecs) to allow ufs cmd sequences to complete. Signed-off-by: Shiraz Hashim --- drivers/ufs/core/ufshcd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 9ceb6d6d479d0..b57bef3f3e4b6 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -120,7 +120,7 @@ static bool is_mcq_supported(struct ufs_hba *hba) module_param(use_mcq_mode, bool, 0644); MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); -static unsigned int uic_cmd_timeout = UIC_CMD_TIMEOUT_DEFAULT; +static unsigned int uic_cmd_timeout = UIC_CMD_TIMEOUT_MAX; static int uic_cmd_timeout_set(const char *val, const struct kernel_param *kp) { From 59c6a9ab3aca3d6f9dc58394378b42a2fe0e6440 Mon Sep 17 00:00:00 2001 From: Anandu Krishnan E Date: Thu, 26 Feb 2026 21:26:47 +0530 Subject: [PATCH 0219/1330] FROMLIST: misc: fastrpc: Add reference counting for fastrpc_user structure Add reference counting using kref to the fastrpc_user structure to prevent use-after-free issues when contexts are freed from workqueue after device release. The issue occurs when fastrpc_device_release() frees the user structure while invoke contexts are still pending in the workqueue. When the workqueue later calls fastrpc_context_free(), it attempts to access buf->fl->cctx in fastrpc_buf_free(), leading to a use-after-free: pc : fastrpc_buf_free+0x38/0x80 [fastrpc] lr : fastrpc_context_free+0xa8/0x1b0 [fastrpc] ... fastrpc_context_free+0xa8/0x1b0 [fastrpc] fastrpc_context_put_wq+0x78/0xa0 [fastrpc] process_one_work+0x180/0x450 worker_thread+0x26c/0x388 Implement proper reference counting to fix this: - Initialize kref in fastrpc_device_open() - Take a reference in fastrpc_context_alloc() for each context - Release the reference in fastrpc_context_free() when context is freed - Release the initial reference in fastrpc_device_release() This ensures the user structure remains valid as long as there are contexts holding references to it, preventing the race condition. Link: https://lore.kernel.org/all/20260226151121.818852-1-anandu.e@oss.qualcomm.com/ Signed-off-by: Anandu Krishnan E --- drivers/misc/fastrpc.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index ffd2af2e5aacd..21b9bb63691ff 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -328,6 +328,8 @@ struct fastrpc_user { spinlock_t lock; /* lock for allocations */ struct mutex mutex; + /* Reference count */ + struct kref refcount; }; /* Extract SMMU PA from consolidated IOVA */ @@ -515,15 +517,36 @@ static void fastrpc_channel_ctx_put(struct fastrpc_channel_ctx *cctx) kref_put(&cctx->refcount, fastrpc_channel_ctx_free); } +static void fastrpc_user_free(struct kref *ref) +{ + struct fastrpc_user *fl = container_of(ref, struct fastrpc_user, refcount); + + fastrpc_channel_ctx_put(fl->cctx); + mutex_destroy(&fl->mutex); + kfree(fl); +} + +static void fastrpc_user_get(struct fastrpc_user *fl) +{ + kref_get(&fl->refcount); +} + +static void fastrpc_user_put(struct fastrpc_user *fl) +{ + kref_put(&fl->refcount, fastrpc_user_free); +} + static void fastrpc_context_free(struct kref *ref) { struct fastrpc_invoke_ctx *ctx; struct fastrpc_channel_ctx *cctx; + struct fastrpc_user *fl; unsigned long flags; int i; ctx = container_of(ref, struct fastrpc_invoke_ctx, refcount); cctx = ctx->cctx; + fl = ctx->fl; for (i = 0; i < ctx->nbufs; i++) fastrpc_map_put(ctx->maps[i]); @@ -539,6 +562,8 @@ static void fastrpc_context_free(struct kref *ref) kfree(ctx->olaps); kfree(ctx); + /* Release the reference taken in fastrpc_context_alloc() */ + fastrpc_user_put(fl); fastrpc_channel_ctx_put(cctx); } @@ -646,6 +671,8 @@ static struct fastrpc_invoke_ctx *fastrpc_context_alloc( /* Released in fastrpc_context_put() */ fastrpc_channel_ctx_get(cctx); + /* Take a reference to user, released in fastrpc_context_free() */ + fastrpc_user_get(user); ctx->sc = sc; ctx->retval = -1; @@ -676,6 +703,7 @@ static struct fastrpc_invoke_ctx *fastrpc_context_alloc( spin_lock(&user->lock); list_del(&ctx->node); spin_unlock(&user->lock); + fastrpc_user_put(user); fastrpc_channel_ctx_put(cctx); kfree(ctx->maps); kfree(ctx->olaps); @@ -1701,11 +1729,9 @@ static int fastrpc_device_release(struct inode *inode, struct file *file) } fastrpc_session_free(cctx, fl->sctx); - fastrpc_channel_ctx_put(cctx); - - mutex_destroy(&fl->mutex); - kfree(fl); file->private_data = NULL; + /* Release the reference taken in fastrpc_device_open */ + fastrpc_user_put(fl); return 0; } @@ -1749,6 +1775,7 @@ static int fastrpc_device_open(struct inode *inode, struct file *filp) spin_lock_irqsave(&cctx->lock, flags); list_add_tail(&fl->user, &cctx->users); spin_unlock_irqrestore(&cctx->lock, flags); + kref_init(&fl->refcount); return 0; } From f61ecd0ba2ce94f6c9cb87e6fee7253000bc8b44 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 27 Jan 2026 16:08:45 +0530 Subject: [PATCH 0220/1330] soc: qcom: smp2p: Add irqchip state support A remoteproc booted during earlier boot stages such as UEFI or the bootloader, may need to be attached to without restarting the remoteproc hardware. To do this the remoteproc will need to check the ready and handover states in smp2p without an interrupt notification. Create qcom_smp2p_start_in() to initialize the shadow state without notifying clients because these early events happened in the past. Add support for the .irq_get_irqchip_state callback so remoteproc can read the current state of the fatal, ready and handover bits. Signed-off-by: Chris Lew Link: https://lore.kernel.org/r/20260127-smp2pv2-v3-1-4060b859b1e2@oss.qualcomm.com Signed-off-by: Deepak Kumar Singh --- drivers/soc/qcom/smp2p.c | 55 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index cb515c2340c10..c27ffb44b8253 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -222,6 +222,39 @@ static void qcom_smp2p_negotiate(struct qcom_smp2p *smp2p) } } +static void qcom_smp2p_start_in(struct qcom_smp2p *smp2p) +{ + unsigned int smem_id = smp2p->smem_items[SMP2P_INBOUND]; + unsigned int pid = smp2p->remote_pid; + char buf[SMP2P_MAX_ENTRY_NAME]; + struct smp2p_smem_item *in; + struct smp2p_entry *entry; + size_t size; + int i; + + in = qcom_smem_get(pid, smem_id, &size); + if (IS_ERR(in)) + return; + + smp2p->in = in; + + /* Check if version is initialized by the remote. */ + if (in->version == 0) + return; + + for (i = smp2p->valid_entries; i < in->valid_entries; i++) { + list_for_each_entry(entry, &smp2p->inbound, node) { + memcpy(buf, in->entries[i].name, sizeof(buf)); + if (!strcmp(buf, entry->name)) { + entry->value = &in->entries[i].value; + entry->last_value = readl(entry->value); + break; + } + } + } + smp2p->valid_entries = i; +} + static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) { struct smp2p_smem_item *in; @@ -368,12 +401,31 @@ static void smp2p_irq_print_chip(struct irq_data *irqd, struct seq_file *p) seq_printf(p, "%8s", dev_name(entry->smp2p->dev)); } +static int smp2p_irq_get_irqchip_state(struct irq_data *irqd, enum irqchip_irq_state which, + bool *state) +{ + struct smp2p_entry *entry = irq_data_get_irq_chip_data(irqd); + u32 val; + + if (which != IRQCHIP_STATE_LINE_LEVEL) + return -EINVAL; + + if (!entry->value) + return -ENODEV; + + val = readl(entry->value); + *state = !!(val & BIT(irqd_to_hwirq(irqd))); + + return 0; +} + static struct irq_chip smp2p_irq_chip = { .name = "smp2p", .irq_mask = smp2p_mask_irq, .irq_unmask = smp2p_unmask_irq, .irq_set_type = smp2p_set_irq_type, .irq_print_chip = smp2p_irq_print_chip, + .irq_get_irqchip_state = smp2p_irq_get_irqchip_state, }; static int smp2p_irq_map(struct irq_domain *d, @@ -618,6 +670,9 @@ static int qcom_smp2p_probe(struct platform_device *pdev) } } + /* Check inbound entries in the case of early boot processor */ + qcom_smp2p_start_in(smp2p); + /* Kick the outgoing edge after allocating entries */ qcom_smp2p_kick(smp2p); From 98dd80de76444ced31e1020599f2d39d378a8475 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 27 Jan 2026 16:08:46 +0530 Subject: [PATCH 0221/1330] soc: qcom: smp2p: Add support for smp2p v2 smp2p v2 adds support for allowing remote processors to write outbound smp2p items without completing the feature negotiation. This is required for processors that start before linux to write out signals like error and clock ready and unblock their bootup. If a remote processor only supports v1, smp2p can version down by mirroring the peer version during the negotiation stage. When using smp2p version 2, the remote does not wait for the ssr ack before setting the items. To accommodate this, set the last_value of all the entries to 0 when SSR is detected. This forces smp2p to detect the new values written by the remote. Because the SSR ack is skipped, the down transition of bits is missed in smp2p version 2. Signed-off-by: Chris Lew Link: https://lore.kernel.org/r/20260127-smp2pv2-v3-2-4060b859b1e2@oss.qualcomm.com Signed-off-by: Deepak Kumar Singh --- drivers/soc/qcom/smp2p.c | 48 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index c27ffb44b8253..af0ceeaf6e073 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -36,6 +36,10 @@ * The driver uses the Linux GPIO and interrupt framework to expose a virtual * GPIO for each outbound entry and a virtual interrupt controller for each * inbound entry. + * + * V2 of SMP2P allows remote processors to write to outbound smp2p items before + * the full smp2p connection is negotiated. This is important for processors + * started before linux runs. */ #define SMP2P_MAX_ENTRY 16 @@ -47,11 +51,12 @@ #define SMP2P_MAGIC 0x504d5324 #define SMP2P_ALL_FEATURES SMP2P_FEATURE_SSR_ACK +#define MAX_VERSION 2 /** * struct smp2p_smem_item - in memory communication structure * @magic: magic number - * @version: version - must be 1 + * @version: version * @features: features flag - currently unused * @local_pid: processor id of sending end * @remote_pid: processor id of receiving end @@ -180,14 +185,22 @@ static void qcom_smp2p_kick(struct qcom_smp2p *smp2p) static bool qcom_smp2p_check_ssr(struct qcom_smp2p *smp2p) { struct smp2p_smem_item *in = smp2p->in; + struct smp2p_entry *entry; + bool restart_done; bool restart; if (!smp2p->ssr_ack_enabled) return false; - restart = in->flags & BIT(SMP2P_FLAGS_RESTART_DONE_BIT); + restart_done = in->flags & BIT(SMP2P_FLAGS_RESTART_DONE_BIT); + restart = restart_done != smp2p->ssr_ack; + list_for_each_entry(entry, &smp2p->inbound, node) { + if (!entry->value) + continue; + entry->last_value = 0; + } - return restart != smp2p->ssr_ack; + return restart; } static void qcom_smp2p_do_ssr_ack(struct qcom_smp2p *smp2p) @@ -219,9 +232,26 @@ static void qcom_smp2p_negotiate(struct qcom_smp2p *smp2p) smp2p->negotiation_done = true; trace_smp2p_negotiate(smp2p->dev, out->features); + } else if (in->version && in->version < out->version) { + out->version = in->version; + qcom_smp2p_kick(smp2p); } } +static int qcom_smp2p_in_version(struct qcom_smp2p *smp2p) +{ + unsigned int smem_id = smp2p->smem_items[SMP2P_INBOUND]; + unsigned int pid = smp2p->remote_pid; + struct smp2p_smem_item *in; + size_t size; + + in = qcom_smem_get(pid, smem_id, &size); + if (IS_ERR(in)) + return 0; + + return in->version; +} + static void qcom_smp2p_start_in(struct qcom_smp2p *smp2p) { unsigned int smem_id = smp2p->smem_items[SMP2P_INBOUND]; @@ -516,6 +546,7 @@ static int qcom_smp2p_alloc_outbound_item(struct qcom_smp2p *smp2p) struct smp2p_smem_item *out; unsigned smem_id = smp2p->smem_items[SMP2P_OUTBOUND]; unsigned pid = smp2p->remote_pid; + u8 in_version; int ret; ret = qcom_smem_alloc(pid, smem_id, sizeof(*out)); @@ -537,12 +568,21 @@ static int qcom_smp2p_alloc_outbound_item(struct qcom_smp2p *smp2p) out->valid_entries = 0; out->features = SMP2P_ALL_FEATURES; + in_version = qcom_smp2p_in_version(smp2p); + if (in_version > MAX_VERSION) { + dev_err(smp2p->dev, "Unsupported smp2p version %d\n", in_version); + return -EINVAL; + } + /* * Make sure the rest of the header is written before we validate the * item by writing a valid version number. */ wmb(); - out->version = 1; + if (in_version && in_version <= 2) + out->version = in_version; + else + out->version = 2; qcom_smp2p_kick(smp2p); From 2bff13fc5137b93d36e59bce486d45498df41a6b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 8 Jan 2026 15:21:50 +0100 Subject: [PATCH 0222/1330] soc: qcom: smem: Expose DDR data from SMEM Most modern Qualcomm platforms (>= SM8150) expose information about the DDR memory present on the system via SMEM. Details from this information is used in various scenarios, such as multimedia drivers configuring the hardware based on the "Highest Bank address Bit" (hbb), or the list of valid frequencies in validation scenarios... Add support for parsing v3-v7 version of the structs. Unforunately, they are not versioned, so some elbow grease is necessary to determine which one is present. See for reference: ver 3: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/1d11897d2cfcc7b85f28ff74c445018dbbecac7a ver 4: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/f6e9aa549260bbc0bdcb156c2b05f48dc5963203 ver 5: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/617d3297abe8b1b8dd3de3d1dd69c3961e6f343f ver 5 with 6regions: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/d770e009f9bae58d56d926f7490bbfb45af8341f ver 6: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/62659b557fdb1551b20fae8073d1d701dfa8a62e ver 7: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/734d95599c5ebb1ca0d4e1639142e65c590532b7 Reviewed-by: Bjorn Andersson Signed-off-by: Konrad Dybcio Tested-by: Neil Armstrong # on SM8650-HDK Link: https://lore.kernel.org/r/20260108-topic-smem_dramc-v3-1-6b64df58a017@oss.qualcomm.com --- drivers/soc/qcom/Makefile | 3 +- drivers/soc/qcom/smem.c | 14 +- drivers/soc/qcom/smem.h | 9 + drivers/soc/qcom/smem_dramc.c | 408 ++++++++++++++++++++++++++++++++++ include/linux/soc/qcom/smem.h | 4 + 5 files changed, 436 insertions(+), 2 deletions(-) create mode 100644 drivers/soc/qcom/smem.h create mode 100644 drivers/soc/qcom/smem_dramc.c diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index b7f1d2a573674..798643be3590c 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -23,7 +23,8 @@ obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o qcom_rpmh-y += rpmh-rsc.o qcom_rpmh-y += rpmh.o obj-$(CONFIG_QCOM_SMD_RPM) += rpm-proc.o smd-rpm.o -obj-$(CONFIG_QCOM_SMEM) += smem.o +qcom_smem-y += smem.o smem_dramc.o +obj-$(CONFIG_QCOM_SMEM) += qcom_smem.o obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o CFLAGS_smp2p.o := -I$(src) obj-$(CONFIG_QCOM_SMP2P) += smp2p.o diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index d5c94b47f431f..7e05e0555dcb4 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -4,6 +4,7 @@ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -16,6 +17,8 @@ #include #include +#include "smem.h" + /* * The Qualcomm shared memory system is a allocate only heap structure that * consists of one of more memory areas that can be accessed by the processors @@ -284,6 +287,8 @@ struct qcom_smem { struct smem_partition global_partition; struct smem_partition partitions[SMEM_HOST_COUNT]; + struct dentry *debugfs_dir; + unsigned num_regions; struct smem_region regions[] __counted_by(num_regions); }; @@ -1236,17 +1241,24 @@ static int qcom_smem_probe(struct platform_device *pdev) __smem = smem; + smem->debugfs_dir = smem_dram_parse(smem->dev); + smem->socinfo = platform_device_register_data(&pdev->dev, "qcom-socinfo", PLATFORM_DEVID_NONE, NULL, 0); - if (IS_ERR(smem->socinfo)) + if (IS_ERR(smem->socinfo)) { + debugfs_remove_recursive(smem->debugfs_dir); + dev_dbg(&pdev->dev, "failed to register socinfo device\n"); + } return 0; } static void qcom_smem_remove(struct platform_device *pdev) { + debugfs_remove_recursive(__smem->debugfs_dir); + platform_device_unregister(__smem->socinfo); /* Set to -EPROBE_DEFER to signal unprobed state */ diff --git a/drivers/soc/qcom/smem.h b/drivers/soc/qcom/smem.h new file mode 100644 index 0000000000000..8bf3f606e1ae8 --- /dev/null +++ b/drivers/soc/qcom/smem.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __QCOM_SMEM_INTERNAL__ +#define __QCOM_SMEM_INTERNAL__ + +#include + +struct dentry *smem_dram_parse(struct device *dev); + +#endif diff --git a/drivers/soc/qcom/smem_dramc.c b/drivers/soc/qcom/smem_dramc.c new file mode 100644 index 0000000000000..017bb894a91b6 --- /dev/null +++ b/drivers/soc/qcom/smem_dramc.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "smem.h" + +#define SMEM_DDR_INFO_ID 603 + +#define MAX_DDR_FREQ_NUM_V3 13 +#define MAX_DDR_FREQ_NUM_V5 14 + +#define MAX_CHAN_NUM 8 +#define MAX_RANK_NUM 2 + +#define DDR_HBB_MIN 13 +#define DDR_HBB_MAX 19 + +#define MAX_SHUB_ENTRIES 8 + +static struct smem_dram *__dram; + +enum ddr_info_version { + INFO_UNKNOWN, + INFO_V3, + INFO_V3_WITH_14_FREQS, + INFO_V4, + INFO_V5, + INFO_V5_WITH_6_REGIONS, + INFO_V6, /* INFO_V6 seems to only have shipped with 6 DDR regions, unlike V7 */ + INFO_V7, + INFO_V7_WITH_6_REGIONS, +}; + +struct smem_dram { + unsigned long frequencies[MAX_DDR_FREQ_NUM_V5]; + u32 num_frequencies; + u8 hbb; +}; + +enum ddr_type { + DDR_TYPE_NODDR = 0, + DDR_TYPE_LPDDR1 = 1, + DDR_TYPE_LPDDR2 = 2, + DDR_TYPE_PCDDR2 = 3, + DDR_TYPE_PCDDR3 = 4, + DDR_TYPE_LPDDR3 = 5, + DDR_TYPE_LPDDR4 = 6, + DDR_TYPE_LPDDR4X = 7, + DDR_TYPE_LPDDR5 = 8, + DDR_TYPE_LPDDR5X = 9, +}; + +/* The data structures below are NOT __packed on purpose! */ + +/* Structs used across multiple versions */ +struct ddr_part_details { + __le16 revision_id1; + __le16 revision_id2; + __le16 width; + __le16 density; +}; + +struct ddr_freq_table { + u32 freq_khz; + u8 enabled; +}; + +/* V3 */ +struct ddr_freq_plan_v3 { + struct ddr_freq_table ddr_freq[MAX_DDR_FREQ_NUM_V3]; /* NOTE: some have 14 like v5 */ + u8 num_ddr_freqs; + phys_addr_t clk_period_address; +}; + +struct ddr_details_v3 { + u8 manufacturer_id; + u8 device_type; + struct ddr_part_details ddr_params[MAX_CHAN_NUM]; + struct ddr_freq_plan_v3 ddr_freq_tbl; + u8 num_channels; +}; + +/* V4 */ +struct ddr_details_v4 { + u8 manufacturer_id; + u8 device_type; + struct ddr_part_details ddr_params[MAX_CHAN_NUM]; + struct ddr_freq_plan_v3 ddr_freq_tbl; + u8 num_channels; + u8 num_ranks[MAX_CHAN_NUM]; + u8 highest_bank_addr_bit[MAX_CHAN_NUM][MAX_RANK_NUM]; +}; + +/* V5 */ +struct shub_freq_table { + u8 enable; + u32 freq_khz; +}; + +struct shub_freq_plan_entry { + u8 num_shub_freqs; + struct shub_freq_table shub_freq[MAX_SHUB_ENTRIES]; +}; + +struct ddr_xbl2quantum_smem_data { + phys_addr_t ssr_cookie_addr; + u32 reserved[10]; +}; + +struct ddr_freq_plan_v5 { + struct ddr_freq_table ddr_freq[MAX_DDR_FREQ_NUM_V5]; + u8 num_ddr_freqs; + phys_addr_t clk_period_address; + u32 max_nom_ddr_freq; +}; + +struct ddr_region_v5 { + u64 start_address; + u64 size; + u64 mem_controller_address; + u32 granule_size; /* MiB */ + u8 ddr_rank; +#define DDR_RANK_0 BIT(0) +#define DDR_RANK_1 BIT(1) + u8 segments_start_index; + u64 segments_start_offset; +}; + +struct ddr_regions_v5 { + u32 ddr_region_num; /* We expect this to always be 4 or 6 */ + u64 ddr_rank0_size; + u64 ddr_rank1_size; + u64 ddr_cs0_start_addr; + u64 ddr_cs1_start_addr; + u32 highest_bank_addr_bit; + struct ddr_region_v5 ddr_region[] __counted_by(ddr_region_num); +}; + +struct ddr_details_v5 { + u8 manufacturer_id; + u8 device_type; + struct ddr_part_details ddr_params[MAX_CHAN_NUM]; + struct ddr_freq_plan_v5 ddr_freq_tbl; + u8 num_channels; + u8 _padding; + struct ddr_regions_v5 ddr_regions; +}; + +/* V6 */ +struct ddr_misc_info_v6 { + u32 dsf_version; + u32 reserved[10]; +}; + +/* V7 */ +struct ddr_details_v7 { + u8 manufacturer_id; + u8 device_type; + struct ddr_part_details ddr_params[MAX_CHAN_NUM]; + struct ddr_freq_plan_v5 ddr_freq_tbl; + u8 num_channels; + u8 sct_config; + struct ddr_regions_v5 ddr_regions; +}; + +/** + * qcom_smem_dram_get_hbb(): Get the Highest bank address bit + * + * Context: Check qcom_smem_is_available() before calling this function. + * Because __dram * is initialized by smem_dram_parse(), which is in turn + * called from * qcom_smem_probe(), __dram will only be NULL if the data + * couldn't have been found/interpreted correctly. + * + * Return: 0 on success, -ENODATA on failure. + */ +int qcom_smem_dram_get_hbb(void) +{ + int hbb; + + if (!__dram) + return -ENODATA; + + hbb = __dram->hbb; + if (hbb == 0) + return -ENODATA; + else if (hbb < DDR_HBB_MIN || hbb > DDR_HBB_MAX) + return -EINVAL; + + return hbb; +} +EXPORT_SYMBOL_GPL(qcom_smem_dram_get_hbb); + +static void smem_dram_parse_v3_data(struct smem_dram *dram, void *data, bool additional_freq_entry) +{ + /* This may be 13 or 14 */ + int num_freq_entries = MAX_DDR_FREQ_NUM_V3; + struct ddr_details_v3 *details = data; + + if (additional_freq_entry) + num_freq_entries++; + + for (int i = 0; i < num_freq_entries; i++) { + struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i]; + + if (freq_entry->freq_khz && freq_entry->enabled) + dram->frequencies[dram->num_frequencies++] = 1000 * freq_entry->freq_khz; + } +} + +static void smem_dram_parse_v4_data(struct smem_dram *dram, void *data) +{ + struct ddr_details_v4 *details = data; + + /* Rank 0 channel 0 entry holds the correct value */ + dram->hbb = details->highest_bank_addr_bit[0][0]; + + for (int i = 0; i < MAX_DDR_FREQ_NUM_V3; i++) { + struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i]; + + if (freq_entry->freq_khz && freq_entry->enabled) + dram->frequencies[dram->num_frequencies++] = 1000 * freq_entry->freq_khz; + } +} + +static void smem_dram_parse_v5_data(struct smem_dram *dram, void *data) +{ + struct ddr_details_v5 *details = data; + struct ddr_regions_v5 *region = &details->ddr_regions; + + dram->hbb = region[0].highest_bank_addr_bit; + + for (int i = 0; i < MAX_DDR_FREQ_NUM_V5; i++) { + struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i]; + + if (freq_entry->freq_khz && freq_entry->enabled) + dram->frequencies[dram->num_frequencies++] = 1000 * freq_entry->freq_khz; + } +} + +static void smem_dram_parse_v7_data(struct smem_dram *dram, void *data) +{ + struct ddr_details_v7 *details = data; + struct ddr_regions_v5 *region = &details->ddr_regions; + + dram->hbb = region[0].highest_bank_addr_bit; + + for (int i = 0; i < MAX_DDR_FREQ_NUM_V5; i++) { + struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i]; + + if (freq_entry->freq_khz && freq_entry->enabled) + dram->frequencies[dram->num_frequencies++] = 1000 * freq_entry->freq_khz; + } +} + +/* The structure contains no version field, so we have to perform some guesswork.. */ +static int smem_dram_infer_struct_version(size_t size) +{ + /* Some early versions provided less bytes of less useful data */ + if (size < sizeof(struct ddr_details_v3)) + return -EINVAL; + + if (size == sizeof(struct ddr_details_v3)) + return INFO_V3; + + if (size == sizeof(struct ddr_details_v3) + + sizeof(struct ddr_freq_table)) + return INFO_V3_WITH_14_FREQS; + + if (size == sizeof(struct ddr_details_v4)) + return INFO_V4; + + if (size == sizeof(struct ddr_details_v5) + + 4 * sizeof(struct ddr_region_v5)) + return INFO_V5; + + if (size == sizeof(struct ddr_details_v5) + + 4 * sizeof(struct ddr_region_v5) + + sizeof(struct ddr_xbl2quantum_smem_data) + + sizeof(struct shub_freq_plan_entry)) + return INFO_V5; + + if (size == sizeof(struct ddr_details_v5) + + 6 * sizeof(struct ddr_region_v5)) + return INFO_V5_WITH_6_REGIONS; + + if (size == sizeof(struct ddr_details_v5) + + 6 * sizeof(struct ddr_region_v5) + + sizeof(struct ddr_xbl2quantum_smem_data) + + sizeof(struct shub_freq_plan_entry)) + return INFO_V5_WITH_6_REGIONS; + + if (size == sizeof(struct ddr_details_v5) + + 6 * sizeof(struct ddr_region_v5) + + sizeof(struct ddr_misc_info_v6) + + sizeof(struct shub_freq_plan_entry)) + return INFO_V6; + + if (size == sizeof(struct ddr_details_v7) + + 4 * sizeof(struct ddr_region_v5) + + sizeof(struct ddr_misc_info_v6) + + sizeof(struct shub_freq_plan_entry)) + return INFO_V7; + + if (size == sizeof(struct ddr_details_v7) + + 6 * sizeof(struct ddr_region_v5) + + sizeof(struct ddr_misc_info_v6) + + sizeof(struct shub_freq_plan_entry)) + return INFO_V7_WITH_6_REGIONS; + + return INFO_UNKNOWN; +} + +static int smem_dram_frequencies_show(struct seq_file *s, void *unused) +{ + struct smem_dram *dram = s->private; + + for (int i = 0; i < dram->num_frequencies; i++) + seq_printf(s, "%lu\n", dram->frequencies[i]); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(smem_dram_frequencies); + +static int smem_hbb_show(struct seq_file *s, void *unused) +{ + struct smem_dram *dram = s->private; + + if (!dram->hbb) + return -EINVAL; + + seq_printf(s, "%d\n", dram->hbb); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(smem_hbb); + +struct dentry *smem_dram_parse(struct device *dev) +{ + struct dentry *debugfs_dir; + enum ddr_info_version ver; + struct smem_dram *dram; + size_t actual_size; + void *data = NULL; + + /* No need to check qcom_smem_is_available(), this func is called by the SMEM driver */ + data = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_DDR_INFO_ID, &actual_size); + if (IS_ERR_OR_NULL(data)) + return ERR_PTR(-ENODATA); + + ver = smem_dram_infer_struct_version(actual_size); + if (ver < 0) { + /* Some SoCs don't provide data that's useful for us */ + return ERR_PTR(-ENODATA); + } else if (ver == INFO_UNKNOWN) { + /* In other cases, we may not have added support for a newer struct revision */ + pr_err("Found an unknown type of DRAM info struct (size = %zu)\n", actual_size); + return ERR_PTR(-EINVAL); + } + + dram = devm_kzalloc(dev, sizeof(*dram), GFP_KERNEL); + if (!dram) + return ERR_PTR(-ENOMEM); + + switch (ver) { + case INFO_V3: + smem_dram_parse_v3_data(dram, data, false); + break; + case INFO_V3_WITH_14_FREQS: + smem_dram_parse_v3_data(dram, data, true); + break; + case INFO_V4: + smem_dram_parse_v4_data(dram, data); + break; + case INFO_V5: + case INFO_V5_WITH_6_REGIONS: + case INFO_V6: + smem_dram_parse_v5_data(dram, data); + break; + case INFO_V7: + case INFO_V7_WITH_6_REGIONS: + smem_dram_parse_v7_data(dram, data); + break; + default: + return ERR_PTR(-EINVAL); + } + + /* Both the entry and its parent dir will be cleaned up by debugfs_remove_recursive */ + debugfs_dir = debugfs_create_dir("qcom_smem", NULL); + debugfs_create_file("dram_frequencies", 0444, debugfs_dir, dram, + &smem_dram_frequencies_fops); + debugfs_create_file("hbb", 0444, debugfs_dir, dram, &smem_hbb_fops); + + /* If there was no failure so far, assign the global variable */ + __dram = dram; + + return debugfs_dir; +} diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h index f946e3beca215..223cd5090a2a8 100644 --- a/include/linux/soc/qcom/smem.h +++ b/include/linux/soc/qcom/smem.h @@ -2,6 +2,8 @@ #ifndef __QCOM_SMEM_H__ #define __QCOM_SMEM_H__ +#include + #define QCOM_SMEM_HOST_ANY -1 bool qcom_smem_is_available(void); @@ -17,4 +19,6 @@ int qcom_smem_get_feature_code(u32 *code); int qcom_smem_bust_hwspin_lock_by_host(unsigned int host); +int qcom_smem_dram_get_hbb(void); + #endif From 1f41c93d1db9f76f302e28c084123797539cbfed Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Thu, 5 Feb 2026 13:51:31 +0530 Subject: [PATCH 0223/1330] FROMLIST: net: qrtr: Expand control port access to root When qrtr is loaded as module, qrtr-ns runs from SELinux kmod_t domain. On targets using upstream SELinux policies, this domain does not receive CAP_NET_ADMIN, which prevents it from binding control port even though qrtr-ns is a trusted system component. Granting kmod_t the CAP_NET_ADMIN capability in policy is possible, but not desirable, as kmod_t is not expected to perform networking operations and widening its capability set is discouraged. To address this in a contained way within qrtr, extend the control port permission check to allow binding when either: - the process has CAP_NET_ADMIN, or - the process belongs to GLOBAL_ROOT_GID (root-equivalent tasks) This permits qrtr-ns to successfully bind its control port in kmod_t restricted environments without broadening SELinux capability assignments. Link: https://lore.kernel.org/r/20260205-qrtr-control-port-access-permission-v1-1-e900039e92d5@oss.qualcomm.com Co-developed-by: Deepak Kumar Singh Signed-off-by: Deepak Kumar Singh Signed-off-by: Vishnu Santhosh --- net/qrtr/af_qrtr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/qrtr/af_qrtr.c b/net/qrtr/af_qrtr.c index d77e9c8212da5..aed2fe7368525 100644 --- a/net/qrtr/af_qrtr.c +++ b/net/qrtr/af_qrtr.c @@ -8,6 +8,7 @@ #include #include /* For TIOCINQ/OUTQ */ #include +#include #include #include @@ -733,7 +734,8 @@ static int qrtr_port_assign(struct qrtr_sock *ipc, int *port) if (!*port) { rc = xa_alloc(&qrtr_ports, port, ipc, QRTR_EPH_PORT_RANGE, GFP_KERNEL); - } else if (*port < QRTR_MIN_EPH_SOCKET && !capable(CAP_NET_ADMIN)) { + } else if (*port < QRTR_MIN_EPH_SOCKET && !(capable(CAP_NET_ADMIN) || + in_egroup_p(GLOBAL_ROOT_GID))) { rc = -EACCES; } else if (*port == QRTR_PORT_CTRL) { rc = xa_insert(&qrtr_ports, 0, ipc, GFP_KERNEL); From 3c26be56ea8dfc723c79180e54cecf5779e223a3 Mon Sep 17 00:00:00 2001 From: Shivnandan Kumar Date: Fri, 27 Feb 2026 16:40:51 +0530 Subject: [PATCH 0224/1330] FROMLIST: soc: qcom: icc-bwmon: Update zone1_thres_count to 3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reduce zone1_thres_count from 16 to 3 so the driver can lower the bus vote after 3 sample windows instead of waiting for 16. The previous 16‑window delay (~64 ms) is too long at higher FPS workloads, causing delayed decision making and measurable power regression. Empirical tuning showed that lower values (e.g., 2) made bwmon behavior jittery, while higher values (4–6) were stable but less responsive and reduced power savings. A value of 3 provided the best balance: responsive enough for timely power reduction while maintaining stable bwmon operation. Significant power savings were observed across multiple use cases when reducing the threshold from 16 to 3: USECASE zone1_thres_count=16 zone1_thres_count=3 4K video playback 236.15 mA 203.15 mA Sleep 7mA 6.9mA Display (idle display) 71.95mA 67.11mA Link: https://lore.kernel.org/r/20260227111051.1789439-1-pussin@qti.qualcomm.com Signed-off-by: Shivnandan Kumar Signed-off-by: Pushpendra Singh --- drivers/soc/qcom/icc-bwmon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index 597f9025e4228..e46975da7dba6 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -830,7 +830,7 @@ static const struct icc_bwmon_data msm8998_bwmon_data = { static const struct icc_bwmon_data sdm845_cpu_bwmon_data = { .sample_ms = 4, .count_unit_kb = 64, - .zone1_thres_count = 16, + .zone1_thres_count = 3, .zone3_thres_count = 1, .quirks = BWMON_HAS_GLOBAL_IRQ, .regmap_fields = sdm845_cpu_bwmon_reg_fields, @@ -849,7 +849,7 @@ static const struct icc_bwmon_data sdm845_llcc_bwmon_data = { static const struct icc_bwmon_data sc7280_llcc_bwmon_data = { .sample_ms = 4, .count_unit_kb = 64, - .zone1_thres_count = 16, + .zone1_thres_count = 3, .zone3_thres_count = 1, .quirks = BWMON_NEEDS_FORCE_CLEAR, .regmap_fields = sdm845_llcc_bwmon_reg_fields, From 7fc5c6d16cf0575abb6364e8e54a288ea6541eac Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Tue, 18 Nov 2025 10:40:56 +0000 Subject: [PATCH 0225/1330] FROMLIST: firmware: qcom: scm: Register gunyah watchdog device To restrict Gunyah watchdog initialization to Qualcomm platforms running under the Gunyah Hypervisor, register the watchdog device in the QCOM SCM driver. When Gunyah is not present or Gunyah emulates MMIO-based watchdog, we expect Qualcomm watchdog or ARM SBSA watchdog device to be present in the devicetree. First, we make sure we're running under the Gunyah Hypervisor. Then we move to check if any of the above mentioned watchdog device nodes are present, if not then we proceed to register the SMC-based Gunyah watchdog device. Link: https://lore.kernel.org/all/20251118-gunyah_watchdog-v8-1-e5de12e2eef5@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Tested-by: Shivendra Pratap Tested-by: Neil Armstrong Signed-off-by: Hrishabh Rajput --- drivers/firmware/qcom/qcom_scm.c | 53 ++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 0b48cad45f39f..bebebe8cd9812 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2469,6 +2469,56 @@ int qcom_scm_qtee_callback_response(phys_addr_t buf, size_t buf_size, } EXPORT_SYMBOL(qcom_scm_qtee_callback_response); +static void qcom_scm_gunyah_wdt_free(void *data) +{ + struct platform_device *gunyah_wdt_dev = data; + + platform_device_unregister(gunyah_wdt_dev); +} + +static void qcom_scm_gunyah_wdt_init(struct qcom_scm *scm) +{ + struct platform_device *gunyah_wdt_dev; + struct device_node *np; + bool of_wdt_available; + int i; + static const uuid_t gunyah_uuid = UUID_INIT(0xc1d58fcd, 0xa453, 0x5fdb, + 0x92, 0x65, 0xce, 0x36, + 0x67, 0x3d, 0x5f, 0x14); + static const char * const of_wdt_compatible[] = { + "qcom,kpss-wdt", + "arm,sbsa-gwdt", + }; + + /* Bail out if we are not running under Gunyah */ + if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY) || + !arm_smccc_hypervisor_has_uuid(&gunyah_uuid)) + return; + + /* + * Gunyah emulates either of Qualcomm watchdog or ARM SBSA watchdog on + * newer platforms. Bail out if we find them in the devicetree. + */ + for (i = 0; i < ARRAY_SIZE(of_wdt_compatible); i++) { + np = of_find_compatible_node(NULL, NULL, of_wdt_compatible[i]); + of_wdt_available = of_device_is_available(np); + of_node_put(np); + if (of_wdt_available) + return; + } + + gunyah_wdt_dev = platform_device_register_simple("gunyah-wdt", -1, + NULL, 0); + if (IS_ERR(gunyah_wdt_dev)) { + dev_err(scm->dev, "Failed to register Gunyah watchdog device: %ld\n", + PTR_ERR(gunyah_wdt_dev)); + return; + } + + devm_add_action_or_reset(scm->dev, qcom_scm_gunyah_wdt_free, + gunyah_wdt_dev); +} + static void qcom_scm_qtee_free(void *data) { struct platform_device *qtee_dev = data; @@ -2858,6 +2908,9 @@ static int qcom_scm_probe(struct platform_device *pdev) /* Initialize the QTEE object interface. */ qcom_scm_qtee_init(scm); + /* Initialize the Gunyah watchdog platform device. */ + qcom_scm_gunyah_wdt_init(scm); + return 0; } From 8f75259f09972ee78afb4cb81b4636177c843930 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Tue, 18 Nov 2025 10:40:57 +0000 Subject: [PATCH 0226/1330] FROMLIST: watchdog: Add driver for Gunyah Watchdog On Qualcomm SoCs running under the Gunyah hypervisor, access to watchdog through MMIO is not available on all platforms. Depending on the hypervisor configuration, the watchdog is either fully emulated or exposed via ARM's SMC Calling Conventions (SMCCC) through the Vendor Specific Hypervisor Service Calls space. Add driver to support the SMC-based watchdog provided by the Gunyah Hypervisor. Device registration is done in the QCOM SCM driver after checks to restrict the watchdog initialization to Qualcomm devices running under Gunyah. Gunyah watchdog is not a hardware but an SMC-based vendor-specific hypervisor interface provided by the Gunyah hypervisor. The design involving QCOM SCM driver for registering the platform device has been devised to avoid adding non-hardware nodes to devicetree. Link: https://lore.kernel.org/all/20251118-gunyah_watchdog-v8-2-e5de12e2eef5@oss.qualcomm.com/ Tested-by: Shivendra Pratap Tested-by: Neil Armstrong Signed-off-by: Hrishabh Rajput --- MAINTAINERS | 1 + drivers/watchdog/Kconfig | 13 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/gunyah_wdt.c | 261 ++++++++++++++++++++++++++++++++++ 4 files changed, 276 insertions(+) create mode 100644 drivers/watchdog/gunyah_wdt.c diff --git a/MAINTAINERS b/MAINTAINERS index 85bbf2d242458..05b1f90fa79a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3364,6 +3364,7 @@ F: arch/arm64/boot/dts/qcom/ F: drivers/bus/qcom* F: drivers/firmware/qcom/ F: drivers/soc/qcom/ +F: drivers/watchdog/gunyah_wdt.c F: include/dt-bindings/arm/qcom,ids.h F: include/dt-bindings/firmware/qcom,scm.h F: include/dt-bindings/soc/qcom* diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index dc78729ba2a5d..5f1dfb6ac41bf 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -2354,4 +2354,17 @@ config KEEMBAY_WATCHDOG To compile this driver as a module, choose M here: the module will be called keembay_wdt. +config GUNYAH_WATCHDOG + tristate "Qualcomm Gunyah Watchdog" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_ARM_SMCCC + select WATCHDOG_CORE + help + Say Y here to include support for watchdog timer provided by the + Gunyah hypervisor. The driver uses ARM SMC Calling Convention (SMCCC) + to interact with Gunyah Watchdog. + + To compile this driver as a module, choose M here: the + module will be called gunyah_wdt. + endif # WATCHDOG diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index d2fb16b9f9ce7..4d1547702ef03 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_MSC313E_WATCHDOG) += msc313e_wdt.o obj-$(CONFIG_APPLE_WATCHDOG) += apple_wdt.o obj-$(CONFIG_SUNPLUS_WATCHDOG) += sunplus_wdt.o obj-$(CONFIG_MARVELL_GTI_WDT) += marvell_gti_wdt.o +obj-$(CONFIG_GUNYAH_WATCHDOG) += gunyah_wdt.o # X86 (i386 + ia64 + x86_64) Architecture obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o diff --git a/drivers/watchdog/gunyah_wdt.c b/drivers/watchdog/gunyah_wdt.c new file mode 100644 index 0000000000000..49dfef459e847 --- /dev/null +++ b/drivers/watchdog/gunyah_wdt.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GUNYAH_WDT_SMCCC_CALL_VAL(func_id) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_VENDOR_HYP, func_id) + +/* SMCCC function IDs for watchdog operations */ +#define GUNYAH_WDT_CONTROL GUNYAH_WDT_SMCCC_CALL_VAL(0x0005) +#define GUNYAH_WDT_STATUS GUNYAH_WDT_SMCCC_CALL_VAL(0x0006) +#define GUNYAH_WDT_PING GUNYAH_WDT_SMCCC_CALL_VAL(0x0007) +#define GUNYAH_WDT_SET_TIME GUNYAH_WDT_SMCCC_CALL_VAL(0x0008) + +/* + * Control values for GUNYAH_WDT_CONTROL. + * Bit 0 is used to enable or disable the watchdog. If this bit is set, + * then the watchdog is enabled and vice versa. + * Bit 1 should always be set to 1 as this bit is reserved in Gunyah and + * it's expected to be 1. + */ +#define WDT_CTRL_ENABLE (BIT(1) | BIT(0)) +#define WDT_CTRL_DISABLE BIT(1) + +enum gunyah_error { + GUNYAH_ERROR_OK = 0, + GUNYAH_ERROR_UNIMPLEMENTED = -1, + GUNYAH_ERROR_ARG_INVAL = 1, +}; + +/** + * gunyah_error_remap() - Remap Gunyah hypervisor errors into a Linux error code + * @gunyah_error: Gunyah hypercall return value + */ +static inline int gunyah_error_remap(enum gunyah_error gunyah_error) +{ + switch (gunyah_error) { + case GUNYAH_ERROR_OK: + return 0; + case GUNYAH_ERROR_UNIMPLEMENTED: + return -EOPNOTSUPP; + default: + return -EINVAL; + } +} + +static int gunyah_wdt_call(unsigned long func_id, unsigned long arg1, + unsigned long arg2) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_smc(func_id, arg1, arg2, &res); + return gunyah_error_remap(res.a0); +} + +static int gunyah_wdt_start(struct watchdog_device *wdd) +{ + unsigned int timeout_ms; + struct device *dev = wdd->parent; + int ret; + + ret = gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_DISABLE, 0); + if (ret && watchdog_active(wdd)) { + dev_err(dev, "%s: Failed to stop gunyah wdt %d\n", __func__, ret); + return ret; + } + + timeout_ms = wdd->timeout * 1000; + ret = gunyah_wdt_call(GUNYAH_WDT_SET_TIME, timeout_ms, timeout_ms); + if (ret) { + dev_err(dev, "%s: Failed to set timeout for gunyah wdt %d\n", + __func__, ret); + return ret; + } + + ret = gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_ENABLE, 0); + if (ret) + dev_err(dev, "%s: Failed to start gunyah wdt %d\n", __func__, ret); + + return ret; +} + +static int gunyah_wdt_stop(struct watchdog_device *wdd) +{ + return gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_DISABLE, 0); +} + +static int gunyah_wdt_ping(struct watchdog_device *wdd) +{ + return gunyah_wdt_call(GUNYAH_WDT_PING, 0, 0); +} + +static int gunyah_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout_sec) +{ + wdd->timeout = timeout_sec; + + if (watchdog_active(wdd)) + return gunyah_wdt_start(wdd); + + return 0; +} + +static int gunyah_wdt_get_time_since_last_ping(void) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_smc(GUNYAH_WDT_STATUS, 0, 0, &res); + if (res.a0) + return gunyah_error_remap(res.a0); + + return res.a2 / 1000; +} + +static unsigned int gunyah_wdt_get_timeleft(struct watchdog_device *wdd) +{ + int seconds_since_last_ping; + + seconds_since_last_ping = gunyah_wdt_get_time_since_last_ping(); + if (seconds_since_last_ping < 0 || + seconds_since_last_ping > wdd->timeout) + return 0; + + return wdd->timeout - seconds_since_last_ping; +} + +static int gunyah_wdt_restart(struct watchdog_device *wdd, + unsigned long action, void *data) +{ + /* Set timeout to 1ms and send a ping */ + gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_DISABLE, 0); + gunyah_wdt_call(GUNYAH_WDT_SET_TIME, 1, 1); + gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_ENABLE, 0); + gunyah_wdt_call(GUNYAH_WDT_PING, 0, 0); + + /* Wait to make sure reset occurs */ + mdelay(100); + + return 0; +} + +static const struct watchdog_info gunyah_wdt_info = { + .identity = "Gunyah Watchdog", + .options = WDIOF_SETTIMEOUT + | WDIOF_KEEPALIVEPING + | WDIOF_MAGICCLOSE, +}; + +static const struct watchdog_ops gunyah_wdt_ops = { + .owner = THIS_MODULE, + .start = gunyah_wdt_start, + .stop = gunyah_wdt_stop, + .ping = gunyah_wdt_ping, + .set_timeout = gunyah_wdt_set_timeout, + .get_timeleft = gunyah_wdt_get_timeleft, + .restart = gunyah_wdt_restart +}; + +static int gunyah_wdt_probe(struct platform_device *pdev) +{ + struct watchdog_device *wdd; + struct device *dev = &pdev->dev; + int ret; + + ret = gunyah_wdt_call(GUNYAH_WDT_STATUS, 0, 0); + if (ret == -EOPNOTSUPP) + return -ENODEV; + + if (ret) + return dev_err_probe(dev, ret, "status check failed\n"); + + wdd = devm_kzalloc(dev, sizeof(*wdd), GFP_KERNEL); + if (!wdd) + return -ENOMEM; + + wdd->info = &gunyah_wdt_info; + wdd->ops = &gunyah_wdt_ops; + wdd->parent = dev; + + /* + * Although Gunyah expects 16-bit unsigned int values as timeout values + * in milliseconds, values above 0x8000 are reserved. This limits the + * max timeout value to 32 seconds. + */ + wdd->max_timeout = 32; /* seconds */ + wdd->min_timeout = 1; /* seconds */ + wdd->timeout = wdd->max_timeout; + + gunyah_wdt_stop(wdd); + platform_set_drvdata(pdev, wdd); + watchdog_set_restart_priority(wdd, 0); + + return devm_watchdog_register_device(dev, wdd); +} + +static void gunyah_wdt_remove(struct platform_device *pdev) +{ + struct watchdog_device *wdd = platform_get_drvdata(pdev); + + gunyah_wdt_stop(wdd); +} + +static int gunyah_wdt_suspend(struct device *dev) +{ + struct watchdog_device *wdd = dev_get_drvdata(dev); + + if (watchdog_active(wdd)) + gunyah_wdt_stop(wdd); + + return 0; +} + +static int gunyah_wdt_resume(struct device *dev) +{ + struct watchdog_device *wdd = dev_get_drvdata(dev); + + if (watchdog_active(wdd)) + gunyah_wdt_start(wdd); + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(gunyah_wdt_pm_ops, gunyah_wdt_suspend, gunyah_wdt_resume); + +/* + * Gunyah watchdog is a vendor-specific hypervisor interface provided by the + * Gunyah hypervisor. Using QCOM SCM driver to detect Gunyah watchdog SMCCC + * hypervisor service and register platform device when the service is available + * allows this driver to operate independently of the devicetree and avoids + * adding the non-hardware nodes to the devicetree. + */ +static const struct platform_device_id gunyah_wdt_id[] = { + { .name = "gunyah-wdt" }, + {} +}; +MODULE_DEVICE_TABLE(platform, gunyah_wdt_id); + +static struct platform_driver gunyah_wdt_driver = { + .driver = { + .name = "gunyah-wdt", + .pm = pm_sleep_ptr(&gunyah_wdt_pm_ops), + }, + .id_table = gunyah_wdt_id, + .probe = gunyah_wdt_probe, + .remove = gunyah_wdt_remove, +}; + +module_platform_driver(gunyah_wdt_driver); + +MODULE_DESCRIPTION("Gunyah Watchdog Driver"); +MODULE_LICENSE("GPL"); From 1320b456febb76a73c0370e782a50f9d3026810e Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 2 Feb 2026 16:06:40 +0530 Subject: [PATCH 0227/1330] FROMLIST: soc: qcom: pd-mapper: Fix element length in servreg_loc_pfr_req_ei It looks element length declared in servreg_loc_pfr_req_ei for reason not matching servreg_loc_pfr_req's reason field due which we could observe decoding error on PD crash. qmi_decode_string_elem: String len 81 >= Max Len 65 Fix this by matching with servreg_loc_pfr_req's reason field. Cc: stable@vger.kernel.org Fixes: 1ebcde047c54 ("soc: qcom: add pd-mapper implementation") Reviewed-by: Dmitry Baryshkov Co-developed-by: Gokul Krishnakumar Signed-off-by: Gokul Krishnakumar Signed-off-by: Mukesh Ojha Signed-off-by: Xin Liu Link: https://lore.kernel.org/all/20260202103641.3003867-1-mukesh.ojha@oss.qualcomm.com/ From 15222b0cadbe6adf6fe7daa05993cb879a5190dc Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 2 Feb 2026 16:06:41 +0530 Subject: [PATCH 0228/1330] FROMLIST: soc: qcom: qmi: Print error codes in failure paths Few error paths in the qmi_interface module log a failure message but do not include the actual error code. Include the error value in the log so debugging failures becomes easier. Reviewed-by: Dmitry Baryshkov Signed-off-by: Mukesh Ojha Signed-off-by: Xin Liu Link: https://lore.kernel.org/all/20260202103641.3003867-2-mukesh.ojha@oss.qualcomm.com/ --- drivers/soc/qcom/qmi_interface.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c index 16e2e24b60968..974ed2b3d611d 100644 --- a/drivers/soc/qcom/qmi_interface.c +++ b/drivers/soc/qcom/qmi_interface.c @@ -321,7 +321,7 @@ int qmi_txn_init(struct qmi_handle *qmi, struct qmi_txn *txn, mutex_lock(&qmi->txn_lock); ret = idr_alloc_cyclic(&qmi->txns, txn, 0, U16_MAX, GFP_KERNEL); if (ret < 0) - pr_err("failed to allocate transaction id\n"); + pr_err("failed to allocate transaction id: %d\n", ret); txn->id = ret; mutex_unlock(&qmi->txn_lock); @@ -413,7 +413,7 @@ static void qmi_invoke_handler(struct qmi_handle *qmi, struct sockaddr_qrtr *sq, ret = qmi_decode_message(buf, len, handler->ei, dest); if (ret < 0) - pr_err("failed to decode incoming message\n"); + pr_err("failed to decode incoming message: %d\n", ret); else handler->fn(qmi, sq, txn, dest); @@ -502,7 +502,7 @@ static void qmi_handle_message(struct qmi_handle *qmi, if (txn->dest && txn->ei) { ret = qmi_decode_message(buf, len, txn->ei, txn->dest); if (ret < 0) - pr_err("failed to decode incoming message\n"); + pr_err("failed to decode incoming message: %d\n", ret); txn->result = ret; complete(&txn->completion); @@ -661,8 +661,8 @@ int qmi_handle_init(struct qmi_handle *qmi, size_t recv_buf_size, if (PTR_ERR(qmi->sock) == -EAFNOSUPPORT) { ret = -EPROBE_DEFER; } else { - pr_err("failed to create QMI socket\n"); ret = PTR_ERR(qmi->sock); + pr_err("failed to create QMI socket: %d\n", ret); } goto err_destroy_wq; } @@ -766,7 +766,7 @@ static ssize_t qmi_send_message(struct qmi_handle *qmi, if (qmi->sock) { ret = kernel_sendmsg(qmi->sock, &msghdr, &iv, 1, len); if (ret < 0) - pr_err("failed to send QMI message\n"); + pr_err("failed to send QMI message: %d\n", ret); } else { ret = -EPIPE; } From 2ef890f15676238d121a33d602c13855c0a9a5e4 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 12:34:25 +0000 Subject: [PATCH 0229/1330] FROMLIST: dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema Add a base schema initially compatible with x1e80100 to describe MIPI CSI2 PHY devices. The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices have their own pinouts on the SoC as well as their own individual voltage rails. The need to model voltage rails on a per-PHY basis leads us to define CSIPHY devices as individual nodes. Two nice outcomes in terms of schema and DT arise from this change. 1. The ability to define on a per-PHY basis voltage rails. 2. The ability to require those voltage. We have had a complete bodge upstream for this where a single set of voltage rail for all CSIPHYs has been buried inside of CAMSS. Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in CAMSS parlance, the CSIPHY devices should be individually modelled. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-x1e-csi2-phy-v3-1-11e608759410@linaro.org/ --- .../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 31 ++++--------------- 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml index b83c2d65ebc6e..c937d26ccbda9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml @@ -41,16 +41,7 @@ properties: maxItems: 1 power-domains: - items: - - description: TITAN TOP GDSC - - description: MXC or MXA voltage rail - - description: MMCX voltage rail - - power-domain-names: - items: - - const: top - - const: mx - - const: mmcx + maxItems: 1 vdda-0p8-supply: description: Phandle to a 0.8V regulator supply to a PHY. @@ -67,7 +58,6 @@ required: - interrupts - operating-points-v2 - power-domains - - power-domain-names - vdda-0p8-supply - vdda-1p2-supply @@ -79,7 +69,6 @@ examples: #include #include #include - #include csiphy@ace4000 { compatible = "qcom,x1e80100-csi2-phy"; @@ -99,35 +88,27 @@ examples: interrupts = ; - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, - <&rpmhpd RPMHPD_MX>, - <&rpmhpd RPMHPD_MMCX>; - power-domain-names = "top", - "mx", - "mmcx"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; vdda-0p8-supply = <&vreg_l2c_0p8>; vdda-1p2-supply = <&vreg_l1c_1p2>; }; - csiphy_opp_table: opp-table { + csiphy_opp_table: opp-table-csiphy { compatible = "operating-points-v2"; opp-300000000 { opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_low_svs_d1>, - <&rpmhpd_opp_low_svs_d1>; + required-opps = <&rpmhpd_opp_low_svs_d1>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - required-opps = <&rpmhpd_opp_low_svs>, - <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_low_svs>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - required-opps = <&rpmhpd_opp_low_svs>, - <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_low_svs>; }; }; From 830665d6571943697725f598ddd169cfc448d308 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 12:34:26 +0000 Subject: [PATCH 0230/1330] FROMLIST: phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver Add a new MIPI CSI2 driver in DPHY mode initially. The entire set of existing CAMSS CSI PHY init sequences are imported in order to save time and effort in later patches. The following devices are supported in this drop: "qcom,x1e80100-csi2-phy" In-line with other PHY drivers the process node is included in the name. At the moment we follow the assignment of lane positions - the bitmap of physical input lanes to logical lane numbers as a linear list per the existing DPHY @lanes data-member. This is fine for us in upstream at the moment since we also map the lanes contiguously but, our hardware can support different lane mappings so we should in the future extend out the DPHY structure to capture the mapping. The Qualcomm 3PH class of PHYs can do both DPHY and CPHY mode. For now only DPHY is supported. In porting some of the logic over from camss-csiphy*.c to here its also possible to rationalise some of the code. In particular use of regulator_bulk and clk_bulk as well as dropping the seemingly useless and unused interrupt handler. The PHY sequences and a lot of the logic that goes with them are well proven in CAMSS and mature so the main thing to watch out for here is how to get the right sequencing of regulators, clocks and register-writes. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-x1e-csi2-phy-v3-2-11e608759410@linaro.org/ --- .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 208 ++++++++++-------- .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 136 +++++++----- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 15 +- 3 files changed, 199 insertions(+), 160 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 874c5c2cb01c8..f9f3451e9a5e1 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* + * camss-phy_qcom_mipi_csi2-3ph-1-0.c + * * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0 * * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. @@ -40,124 +42,129 @@ #define CSI_CTRL_MAX 33 #define CSIPHY_DEFAULT_PARAMS 0 +#define CSIPHY_LANE_ENABLE 1 #define CSIPHY_SETTLE_CNT_LOWER_BYTE 2 +#define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3 +#define CSIPHY_DNP_PARAMS 4 +#define CSIPHY_2PH_REGS 5 +#define CSIPHY_3PH_REGS 6 #define CSIPHY_SKEW_CAL 7 /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ static const struct mipi_csi2phy_lane_regs lane_regs_x1e80100[] = { /* Power up lanes 2ph mode */ - {.reg_addr = 0x1014, .reg_data = 0xd5, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x101c, .reg_data = 0x7a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x1014, .reg_data = 0xD5, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x101C, .reg_data = 0x7A, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x1018, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0094, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x00a0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x00A0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0090, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0098, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0094, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0030, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0000, .reg_data = 0x8e, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0038, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x002c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0034, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x001c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0000, .reg_data = 0x8E, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0038, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x002C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0034, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x001C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0014, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x003c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0004, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x003C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0004, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0020, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0008, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, {.reg_addr = 0x0010, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0094, .reg_data = 0xd7, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x005c, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0060, .reg_data = 0xbd, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0064, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL}, - - {.reg_addr = 0x0e94, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0ea0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e90, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e98, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e94, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e30, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e28, .reg_data = 0x04, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e00, .reg_data = 0x80, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e0c, .reg_data = 0xff, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e38, .reg_data = 0x1f, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e2c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e34, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e1c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e14, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e3c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e04, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e20, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0e08, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {.reg_addr = 0x0e10, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0094, .reg_data = 0xD7, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x005C, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0060, .reg_data = 0xBD, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0064, .reg_data = 0x7F, .param_type = CSIPHY_SKEW_CAL}, + + {.reg_addr = 0x0E94, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0EA0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E90, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E98, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E94, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E30, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E28, .reg_data = 0x04, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E00, .reg_data = 0x80, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E0C, .reg_data = 0xFF, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E38, .reg_data = 0x1F, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E2C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E34, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E1C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E14, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E3C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E04, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E20, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0E08, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0E10, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0494, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x04a0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x04A0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0490, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0498, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0494, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0430, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0400, .reg_data = 0x8e, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0438, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x042c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0434, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x041c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0400, .reg_data = 0x8E, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0438, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x042C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0434, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x041C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0414, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x043c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0404, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x043C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0404, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0420, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0408, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, {.reg_addr = 0x0410, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0494, .reg_data = 0xd7, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x045c, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0460, .reg_data = 0xbd, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0464, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0494, .reg_data = 0xD7, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x045C, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0460, .reg_data = 0xBD, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0464, .reg_data = 0x7F, .param_type = CSIPHY_SKEW_CAL}, {.reg_addr = 0x0894, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x08a0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x08A0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0890, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0898, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0894, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0830, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0800, .reg_data = 0x8e, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0838, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x082c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0834, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x081c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x8E, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0838, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x082C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0834, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x081C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0814, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x083c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0804, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x083C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0804, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0820, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, {.reg_addr = 0x0808, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, {.reg_addr = 0x0810, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0894, .reg_data = 0xd7, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x085c, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0860, .reg_data = 0xbd, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0864, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL}, - - {.reg_addr = 0x0c94, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0ca0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c90, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c98, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c94, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c30, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c00, .reg_data = 0x8e, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c38, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c2c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c34, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c1c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c14, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c3c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c04, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c20, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c08, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {.reg_addr = 0x0c10, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, - {.reg_addr = 0x0c94, .reg_data = 0xd7, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0c5c, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0c60, .reg_data = 0xbd, .param_type = CSIPHY_SKEW_CAL}, - {.reg_addr = 0x0c64, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0894, .reg_data = 0xD7, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x085C, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0860, .reg_data = 0xBD, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0864, .reg_data = 0x7F, .param_type = CSIPHY_SKEW_CAL}, + + {.reg_addr = 0x0C94, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0CA0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C90, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C98, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C94, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C30, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C00, .reg_data = 0x8E, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C38, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C2C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C34, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C1C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C14, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C3C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C04, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C20, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C08, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0C10, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C94, .reg_data = 0xD7, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0C5C, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0C60, .reg_data = 0xBD, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0C64, .reg_data = 0x7F, .param_type = CSIPHY_SKEW_CAL}, }; static inline const struct mipi_csi2phy_device_regs * @@ -328,6 +335,22 @@ static const struct mipi_csi2phy_hw_ops phy_qcom_mipi_csi2_ops_3ph_1_0 = { .lanes_disable = phy_qcom_mipi_csi2_lanes_disable, }; +static const struct mipi_csi2phy_clk_freq zero = { 0 }; + +static const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy = { + .freq = { + 300000000, 400000000, 480000000 + }, + .num_freq = 3, +}; + +static const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy_timer = { + .freq = { + 266666667, 400000000 + }, + .num_freq = 2, +}; + static const char * const x1e_clks[] = { "camnoc_axi", "cpas_ahb", @@ -335,16 +358,6 @@ static const char * const x1e_clks[] = { "csiphy_timer" }; -static const char * const x1e_supplies[] = { - "vdda-0p8", - "vdda-1p2" -}; - -static const char * const x1e_genpd_names[] = { - "mx", - "mmcx", -}; - const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0, .reg_info = { @@ -353,12 +366,19 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { .common_regs_offset = 0x1000, .generation = GEN2, }, - .supply_names = (const char **)x1e_supplies, - .num_supplies = ARRAY_SIZE(x1e_supplies), + .supply_names = (const char *[]){ + "vdda-0p8", + "vdda-1p2" + }, + .num_supplies = 2, .clk_names = (const char **)x1e_clks, .num_clk = ARRAY_SIZE(x1e_clks), .opp_clk = x1e_clks[2], .timer_clk = x1e_clks[3], - .genpd_names = (const char **)x1e_genpd_names, - .num_genpd_names = ARRAY_SIZE(x1e_genpd_names), + .clk_freq = { + zero, + zero, + dphy_4nm_x1e_csiphy, + dphy_4nm_x1e_csiphy_timer, + }, }; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c index b5969ce66cd6d..454144f81b719 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -22,51 +21,99 @@ #include "phy-qcom-mipi-csi2.h" +#define CAMSS_CLOCK_MARGIN_NUMERATOR 105 +#define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 + +static inline void phy_qcom_mipi_csi2_add_clock_margin(u64 *rate) +{ + *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR; + *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR); +} + static int phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy, s64 link_freq) { + const struct mipi_csi2phy_soc_cfg *soc_cfg = csi2phy->soc_cfg; + unsigned long rates[MAX_CSI2PHY_CLKS] = {0}; struct device *dev = csi2phy->dev; - unsigned long opp_rate = link_freq / 4; - struct dev_pm_opp *opp; - long timer_rate; + unsigned long vote_freq = 0; + int i, j; int ret; - opp = dev_pm_opp_find_freq_ceil(dev, &opp_rate); - if (IS_ERR(opp)) { - dev_err(csi2phy->dev, "Couldn't find ceiling for %lld Hz\n", - link_freq); - return PTR_ERR(opp); - } + for (i = 0; i < soc_cfg->num_clk; i++) { + const struct mipi_csi2phy_clk_freq *clk_freq = &soc_cfg->clk_freq[i]; + const char *clk_name = soc_cfg->clk_names[i]; + struct clk *clk = csi2phy->clks[i].clk; + u64 min_rate = link_freq / 4; + long round_rate; - for (int i = 0; i < csi2phy->num_pds; i++) { - unsigned int perf = dev_pm_opp_get_required_pstate(opp, i); + phy_qcom_mipi_csi2_add_clock_margin(&min_rate); - ret = dev_pm_genpd_set_performance_state(csi2phy->pds[i], perf); - if (ret) { - dev_err(csi2phy->dev, "Couldn't set perf state %u\n", - perf); - dev_pm_opp_put(opp); - return ret; + /* This clock should be enabled only not set */ + if (!clk_freq->num_freq) + continue; + + for (j = 0; j < clk_freq->num_freq; j++) + if (min_rate < clk_freq->freq[j]) + break; + + if (j == clk_freq->num_freq) { + dev_err(dev, + "Pixel clock %llu is too high for %s\n", + min_rate, clk_name); + return -EINVAL; } + + /* if sensor pixel clock is not available + * set highest possible CSIPHY clock rate + */ + if (min_rate == 0) + j = clk_freq->num_freq - 1; + + round_rate = clk_round_rate(clk, clk_freq->freq[j]); + if (round_rate < 0) { + dev_err(dev, "clk round rate failed: %ld\n", + round_rate); + return -EINVAL; + } + + rates[i] = round_rate; + + if (!strcmp(clk_name, soc_cfg->timer_clk)) + csi2phy->timer_clk_rate = round_rate; + + if (!strcmp(clk_name, soc_cfg->opp_clk)) + vote_freq = round_rate; } - dev_pm_opp_put(opp); - ret = dev_pm_opp_set_rate(dev, opp_rate); - if (ret) { - dev_err(csi2phy->dev, "dev_pm_opp_set_rate() fail\n"); + if (!vote_freq) { + dev_err(dev, "Unable to find operating point frequency\n"); + return -ENODEV; + }; + + dev_dbg(dev, "OPP freq: %lu Hz\n", vote_freq); + + ret = dev_pm_opp_set_rate(dev, vote_freq); + if (ret < 0) { + dev_err(dev, "Failed to set OPP rate: %d\n", ret); return ret; } - timer_rate = clk_round_rate(csi2phy->timer_clk, link_freq / 4); - if (timer_rate < 0) - return timer_rate; + for (i = 0; i < soc_cfg->num_clk; i++) { + if (rates[i] == 0) + continue; - ret = clk_set_rate(csi2phy->timer_clk, timer_rate); - if (ret) - return ret; + dev_dbg(dev, "Setting clk %s to %lu Hz\n", + soc_cfg->clk_names[i], rates[i]); - csi2phy->timer_clk_rate = timer_rate; + ret = clk_set_rate(csi2phy->clks[i].clk, rates[i]); + if (ret < 0) { + dev_err(dev, "clk_set_rate failed for %s: %d\n", + soc_cfg->clk_names[i], ret); + return ret; + } + } return 0; } @@ -150,10 +197,6 @@ static int phy_qcom_mipi_csi2_power_on(struct phy *phy) static int phy_qcom_mipi_csi2_power_off(struct phy *phy) { struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy); - int i; - - for (int i = 0; i < csi2phy->num_pds; i++) - dev_pm_genpd_set_performance_state(csi2phy->pds[i], 0); clk_bulk_disable_unprepare(csi2phy->soc_cfg->num_clk, csi2phy->clks); @@ -172,7 +215,7 @@ static const struct phy_ops phy_qcom_mipi_csi2_ops = { static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) { - unsigned int i, num_clk, num_supplies, num_pds; + unsigned int i, num_clk, num_supplies; struct mipi_csi2phy_device *csi2phy; struct phy_provider *phy_provider; struct device *dev = &pdev->dev; @@ -194,25 +237,6 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) if (!csi2phy->clks) return -ENOMEM; - num_pds = csi2phy->soc_cfg->num_genpd_names; - if (!num_pds) - return -EINVAL; - - csi2phy->pds = devm_kzalloc(dev, sizeof(*csi2phy->pds) * num_pds, GFP_KERNEL); - if (!csi2phy->pds) - return -ENOMEM; - - for (i = 0; i < num_pds; i++) { - csi2phy->pds[i] = dev_pm_domain_attach_by_name(dev, - csi2phy->soc_cfg->genpd_names[i]); - if (IS_ERR(csi2phy->pds[i])) { - return dev_err_probe(dev, PTR_ERR(csi2phy->pds[i]), - "Failed to attach %s\n", - csi2phy->soc_cfg->genpd_names[i]); - } - } - csi2phy->num_pds = num_pds; - for (i = 0; i < num_clk; i++) csi2phy->clks[i].id = csi2phy->soc_cfg->clk_names[i]; @@ -220,12 +244,6 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "Failed to get clocks\n"); - csi2phy->timer_clk = devm_clk_get(dev, csi2phy->soc_cfg->timer_clk); - if (IS_ERR(csi2phy->timer_clk)) { - return dev_err_probe(dev, PTR_ERR(csi2phy->timer_clk), - "Failed to get timer clock\n"); - } - ret = devm_pm_opp_set_clkname(dev, csi2phy->soc_cfg->opp_clk); if (ret) return dev_err_probe(dev, ret, "Failed to set opp clkname\n"); diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h index 179f535121aad..4f3a245ba6a53 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -59,6 +59,12 @@ struct mipi_csi2phy_device_regs { } generation; }; +#define MAX_CSI2PHY_CLKS 8 +struct mipi_csi2phy_clk_freq { + u32 num_freq; + u32 freq[MAX_CSI2PHY_CLKS]; +}; + struct mipi_csi2phy_soc_cfg { const struct mipi_csi2phy_hw_ops *ops; const struct mipi_csi2phy_device_regs reg_info; @@ -72,8 +78,7 @@ struct mipi_csi2phy_soc_cfg { const char * const opp_clk; const char * const timer_clk; - const char ** const genpd_names; - const unsigned int num_genpd_names; + const struct mipi_csi2phy_clk_freq clk_freq[]; }; struct mipi_csi2phy_device { @@ -83,12 +88,8 @@ struct mipi_csi2phy_device { void __iomem *base; struct clk_bulk_data *clks; - struct clk *timer_clk; - u32 timer_clk_rate; - struct regulator_bulk_data *supplies; - struct device **pds; - unsigned int num_pds; + u32 timer_clk_rate; const struct mipi_csi2phy_soc_cfg *soc_cfg; struct mipi_csi2phy_stream_cfg stream_cfg; From 14d91df7483ceca0cc0067502eb060a99ebd62b6 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:28:42 +0000 Subject: [PATCH 0231/1330] FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Add optional PHY handle definitions Add optional PHY handle definitions. This will allow for supporting both legacy PHY definitions as well as supporting the optional new handle based approach. Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/all/20260226-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v9-1-a59c3f037d0b@linaro.org/ --- .../devicetree/bindings/media/qcom,x1e80100-camss.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml index 3e91bbfb808b3..56a45bdafc91b 100644 --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -457,6 +457,11 @@ examples: vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; + phys = <&csiphy0>, <&csiphy1>, + <&csiphy2>, <&csiphy4>; + phy-names = "csiphy0", "csiphy1", + "csiphy2", "csiphy4"; + ports { #address-cells = <1>; #size-cells = <0>; From 2bd6215db00fbcf51cc9d8865d12f65a44017c28 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:28:43 +0000 Subject: [PATCH 0232/1330] FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Add support for combo-mode endpoints Qualcomm CSI2 PHYs support a mode where two sensors may be attached to the one CSIPHY. When we have one endpoint we may have - DPHY 1, 2 or 4 data lanes + 1 clock lane - CPHY 3 wire data lane When we have two endpoints this indicates the special fixed combo-mode. - DPHY endpoint0 => 2+1 and endpoint1 => 1+1 data-lane/clock-lane combination. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v9-2-a59c3f037d0b@linaro.org/ --- .../devicetree/bindings/media/qcom,x1e80100-camss.yaml | 8 -------- 1 file changed, 8 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml index 56a45bdafc91b..f1686e1998c2c 100644 --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -256,14 +256,6 @@ properties: minItems: 1 maxItems: 4 -patternProperties: - "^phy@[0-9a-f]+$": - $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml - unevaluatedProperties: false - - "^opp-table(-.*)?$": - type: object - required: - compatible - reg From e487bcf01b30d1b951147b88a3fed4d3a69d1d34 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:28:44 +0000 Subject: [PATCH 0233/1330] FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Add iommus minItems: 5 Specify a minimum number of iommus entries. Currently the schema requires exactly eight. Add minItems to allow fewer entries while retaining the existing maximum. Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/all/20260226-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v9-3-a59c3f037d0b@linaro.org/ --- .../bindings/media/qcom,x1e80100-camss.yaml | 22 +++++-------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml index f1686e1998c2c..9f52068d628b5 100644 --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -116,22 +116,8 @@ properties: - const: sf_icp_mnoc iommus: - oneOf: - - items: - - description: S1 HLOS IFE and IFE_LITE non-protected read - - description: S1 HLOS IFE and IFE_LITE non-protected write - - description: S1 HLOS SFE non-protected read - - description: S1 HLOS SFE non-protected write - - description: S1 HLOS CDM IFE non-protected - - description: Legacy slot 0 - do not use - - description: Legacy slot 1 - do not use - - description: Legacy slot 2 - do not use - - items: - - description: S1 HLOS IFE and IFE_LITE non-protected read - - description: S1 HLOS IFE and IFE_LITE non-protected write - - description: S1 HLOS SFE non-protected read - - description: S1 HLOS SFE non-protected write - - description: S1 HLOS CDM IFE non-protected + minItems: 5 + maxItems: 8 power-domains: items: @@ -436,7 +422,9 @@ examples: <&apps_smmu 0x820 0x60>, <&apps_smmu 0x840 0x60>, <&apps_smmu 0x860 0x60>, - <&apps_smmu 0x18a0 0x0>; + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x19a0 0x20>; power-domains = <&camcc CAM_CC_IFE_0_GDSC>, <&camcc CAM_CC_IFE_1_GDSC>, From 35ba45ac4786fbadb028913de8d54e4e10164151 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:28:45 +0000 Subject: [PATCH 0234/1330] FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Allow CSIPHY supplies to be optional When CSIPHY devices are modelled as standalone PHY nodes the voltage rails are defined per-PHY. Allow the CAMSS-level supply properties to be omitted in this case. Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/all/20260226-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v9-4-a59c3f037d0b@linaro.org/ From b24e26bd23beb532a0e9232643a4529b137369ce Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:28:46 +0000 Subject: [PATCH 0235/1330] FROMLIST: media: qcom: camss: Add legacy_phy flag to SoC definition structures Flag which SoCs have legacy - builtin PHY code. This will be useful in subsequent patches to inform PHY bringup logic if legacy bindings are available. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v9-5-a59c3f037d0b@linaro.org/ --- drivers/media/platform/qcom/camss/camss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 4bc5e298b81c4..622d88e826db4 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -5326,6 +5326,7 @@ static const struct camss_resources sm8650_resources = { static const struct camss_resources x1e80100_resources = { .version = CAMSS_X1E80100, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_x1e80100, .csid_res = csid_res_x1e80100, .vfe_res = vfe_res_x1e80100, From 88a86e6552aded76054696745cb7a6d7db099b60 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:28:47 +0000 Subject: [PATCH 0236/1330] FROMLIST: media: qcom: camss: Add support for PHY API devices Add the ability to use a PHY pointer which interacts with the standard PHY API. In the first instance the code will try to use the new PHY interface. If no PHYs are present in the DT then the legacy method will be attempted. Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/all/20260226-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v9-6-a59c3f037d0b@linaro.org/ From a5d6a3d39533831cc637d9cebdfa4c46c105a7cc Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:28:48 +0000 Subject: [PATCH 0237/1330] FROMLIST: media: qcom: camss: Drop legacy PHY descriptions from x1e x1e is the first CAMSS SoC to use the new PHY interface. Drop the redundant legacy CSIPHY descriptions. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v9-7-a59c3f037d0b@linaro.org/ --- drivers/media/platform/qcom/camss/camss.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 622d88e826db4..4bc5e298b81c4 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -5326,7 +5326,6 @@ static const struct camss_resources sm8650_resources = { static const struct camss_resources x1e80100_resources = { .version = CAMSS_X1E80100, .pd_name = "top", - .legacy_phy = true, .csiphy_res = csiphy_res_x1e80100, .csid_res = csid_res_x1e80100, .vfe_res = vfe_res_x1e80100, From 7895d229aa2c9b81f28353a7b904b0b071e7052a Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Fri, 2 Jan 2026 18:10:18 +0530 Subject: [PATCH 0238/1330] mmc: host: sdhci-msm: Add support for wrapped keys Add the wrapped key support for sdhci-msm by implementing the needed methods in struct blk_crypto_ll_ops and setting the appropriate flag in blk_crypto_profile::key_types_supported. Tested on SC7280 eMMC variant. How to test: Use the "v1.3.0" tag from https://github.com/google/fscryptctl and build fscryptctl that supports generating wrapped keys. Enable the following config options: CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_QCOM_INLINE_CRYPTO_ENGINE=y CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y CONFIG_MMC_CRYPTO=y Enable "qcom_ice.use_wrapped_keys" via kernel command line. $ mkfs.ext4 -F -O encrypt,stable_inodes /dev/disk/by-partlabel/vm-data $ mount /dev/disk/by-partlabel/vm-data -o inlinecrypt /mnt $ fscryptctl generate_hw_wrapped_key /dev/disk/by-partlabel/vm-data > /mnt/key.longterm $ fscryptctl prepare_hw_wrapped_key /dev/disk/by-partlabel/vm-data < /mnt/key.longterm > /tmp/key.ephemeral $ KEYID=$(fscryptctl add_key --hw-wrapped-key < /tmp/key.ephemeral /mnt) $ rm -rf /mnt/dir $ mkdir /mnt/dir $ fscryptctl set_policy --iv-ino-lblk-32 "$KEYID" /mnt/dir $ dmesg > /mnt/dir/test.txt $ sync Reboot the board $ mount /dev/disk/by-partlabel/vm-data -o inlinecrypt /mnt $ ls /mnt/dir # File should be encrypted $ fscryptctl prepare_hw_wrapped_key /dev/disk/by-partlabel/vm-data < /mnt/key.longterm > /tmp/key.ephemeral $ KEYID=$(fscryptctl add_key --hw-wrapped-key < /tmp/key.ephemeral /mnt) $ fscryptctl set_policy --iv-ino-lblk-32 "$KEYID" /mnt/dir $ cat /mnt/dir/test.txt # File should now be decrypted Tested-by: Wenjia Zhang Signed-off-by: Neeraj Soni Acked-by: Adrian Hunter Reviewed-by: Eric Biggers --- drivers/mmc/host/sdhci-msm.c | 47 +++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 3b85233131b38..98356c17e5386 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1914,11 +1914,6 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, if (IS_ERR_OR_NULL(ice)) return PTR_ERR_OR_ZERO(ice); - if (qcom_ice_get_supported_key_type(ice) != BLK_CRYPTO_KEY_TYPE_RAW) { - dev_warn(dev, "Wrapped keys not supported. Disabling inline encryption support.\n"); - return 0; - } - msm_host->ice = ice; /* Initialize the blk_crypto_profile */ @@ -1932,7 +1927,7 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, profile->ll_ops = sdhci_msm_crypto_ops; profile->max_dun_bytes_supported = 4; - profile->key_types_supported = BLK_CRYPTO_KEY_TYPE_RAW; + profile->key_types_supported = qcom_ice_get_supported_key_type(ice); profile->dev = dev; /* @@ -2012,9 +2007,49 @@ static int sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile *profile, return qcom_ice_evict_key(msm_host->ice, slot); } +static int sdhci_msm_ice_derive_sw_secret(struct blk_crypto_profile *profile, + const u8 *eph_key, size_t eph_key_size, + u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]) +{ + struct sdhci_msm_host *msm_host = sdhci_msm_host_from_crypto_profile(profile); + + return qcom_ice_derive_sw_secret(msm_host->ice, eph_key, eph_key_size, + sw_secret); +} + +static int sdhci_msm_ice_import_key(struct blk_crypto_profile *profile, + const u8 *raw_key, size_t raw_key_size, + u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) +{ + struct sdhci_msm_host *msm_host = sdhci_msm_host_from_crypto_profile(profile); + + return qcom_ice_import_key(msm_host->ice, raw_key, raw_key_size, lt_key); +} + +static int sdhci_msm_ice_generate_key(struct blk_crypto_profile *profile, + u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) +{ + struct sdhci_msm_host *msm_host = sdhci_msm_host_from_crypto_profile(profile); + + return qcom_ice_generate_key(msm_host->ice, lt_key); +} + +static int sdhci_msm_ice_prepare_key(struct blk_crypto_profile *profile, + const u8 *lt_key, size_t lt_key_size, + u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) +{ + struct sdhci_msm_host *msm_host = sdhci_msm_host_from_crypto_profile(profile); + + return qcom_ice_prepare_key(msm_host->ice, lt_key, lt_key_size, eph_key); +} + static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops = { .keyslot_program = sdhci_msm_ice_keyslot_program, .keyslot_evict = sdhci_msm_ice_keyslot_evict, + .derive_sw_secret = sdhci_msm_ice_derive_sw_secret, + .import_key = sdhci_msm_ice_import_key, + .generate_key = sdhci_msm_ice_generate_key, + .prepare_key = sdhci_msm_ice_prepare_key, }; #else /* CONFIG_MMC_CRYPTO */ From 0180327588d1c05e19bd81c2669abbdbda2f29c7 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 13:51:12 +0530 Subject: [PATCH 0239/1330] FROMLIST: dt-bindings: crypto: qcom,ice: Require power-domain and iface clk Update the inline-crypto engine DT binding to reflect that power-domain and clock-names are now mandatory. Also update the maximum number of clocks that can be specified to two. These new fields are mandatory because ICE needs to vote on the power domain before it attempts to vote on the core and iface clocks to avoid clock 'stuck' issues. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-1-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- .../bindings/crypto/qcom,inline-crypto-engine.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 061ff718b23d6..1078de779c16e 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -29,12 +29,20 @@ properties: maxItems: 1 clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + power-domains: maxItems: 1 required: - compatible - reg - clocks + - clock-names + - power-domains additionalProperties: false @@ -46,6 +54,10 @@ examples: compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x01d88000 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ... From 4bd84272a967fe129aa9e4db67dc31bf688ffd1b Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 14:25:10 +0530 Subject: [PATCH 0240/1330] FROMLIST: arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for lemans. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-3-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index e202558085783..588c9b69748a5 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2763,7 +2763,11 @@ compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 94c62ebc300bb784c6d805d13ffc8364945e3a0f Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Fri, 23 Jan 2026 18:46:25 +0530 Subject: [PATCH 0241/1330] FROMLIST: arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for monaco. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-4-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 934a97001f6ce..97eb3ea6eed40 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2734,7 +2734,11 @@ compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; crypto: crypto@1dfa000 { From b24e331fa0269a68dae08f52830152d0ab41cec0 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 14:27:25 +0530 Subject: [PATCH 0242/1330] FROMLIST: arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for sc7180. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-5-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 45b9864e3304b..74eb895cf4da7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1605,7 +1605,11 @@ compatible = "qcom,sc7180-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d90000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ipa: ipa@1e40000 { From a905e9d319f36b96d417888a04ebb953374093e7 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 16:15:04 +0530 Subject: [PATCH 0243/1330] FROMLIST: arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for kodiak. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-6-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 80e9481471f24..a8f5b50f33cd9 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2579,7 +2579,11 @@ compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From e1cbae0492d0cd1fb5cbf43604649391c75534ec Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 14:30:05 +0530 Subject: [PATCH 0244/1330] FROMLIST: arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for sm8450. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-7-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index dd60843e022ef..5d99712f23393 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5374,7 +5374,11 @@ compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From efa83d2c09b38df0e832587262d8d542b2319edd Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 14:31:52 +0530 Subject: [PATCH 0245/1330] FROMLIST: arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for sm8550. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-8-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 42f9deaadd86a..04dc9d6a251a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2449,7 +2449,11 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From 43f24bbbf7397fb38f17081fbcaad30876671a70 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 14:32:31 +0530 Subject: [PATCH 0246/1330] FROMLIST: arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for sm8650. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-9-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 64a7480291d84..802c92bc51e10 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4081,7 +4081,11 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 16921441f16ca94861674982c216a702d3690f58 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 14:33:19 +0530 Subject: [PATCH 0247/1330] FROMLIST: arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for sm8750. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-10-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 4efdead3583f9..baaf4ca1dbfdf 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2083,7 +2083,11 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "ice_core_clk", + "iface_clk"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From b1be15cf8a20d852ace65a1aee1b82c54d243579 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 20 Jan 2026 15:28:59 +0530 Subject: [PATCH 0248/1330] FROMLIST: soc: qcom: ice: Add explicit power-domain and clock voting calls for ICE Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver de-coupled from the QCOM UFS driver, it should explicitly vote for it's needed resources during probe, specifically the UFS_PHY_GDSC power-domain and the 'core' and 'iface' clocks. Also updated the suspend and resume callbacks to handle votes on these resources. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-11-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev --- drivers/soc/qcom/ice.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cadd..4b50d05ca02a3 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include @@ -108,6 +110,7 @@ struct qcom_ice { void __iomem *base; struct clk *core_clk; + struct clk *iface_clk; bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; @@ -310,12 +313,20 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev = ice->dev; int err; + pm_runtime_get_sync(dev); err = clk_prepare_enable(ice->core_clk); if (err) { dev_err(dev, "failed to enable core clock (%d)\n", err); return err; } + + err = clk_prepare_enable(ice->iface_clk); + if (err) { + dev_err(dev, "failed to enable iface clock (%d)\n", + err); + return err; + } qcom_ice_hwkm_init(ice); return qcom_ice_wait_bist_status(ice); } @@ -323,7 +334,9 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); int qcom_ice_suspend(struct qcom_ice *ice) { + clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); + pm_runtime_put_sync(ice->dev); ice->hwkm_init_complete = false; return 0; @@ -584,6 +597,10 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); + engine->iface_clk = devm_clk_get_enabled(dev, "iface_clk"); + if (IS_ERR(engine->iface_clk)) + return ERR_CAST(engine->iface_clk); + if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); @@ -725,6 +742,9 @@ static int qcom_ice_probe(struct platform_device *pdev) return PTR_ERR(base); } + devm_pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + engine = qcom_ice_create(&pdev->dev, base); if (IS_ERR(engine)) return PTR_ERR(engine); From fdc95d23cba16cfa3f44c120e88188c71ad7e57d Mon Sep 17 00:00:00 2001 From: Debraj Mukhopadhyay Date: Fri, 16 Jan 2026 17:40:04 +0530 Subject: [PATCH 0249/1330] mmc: Avoid reprogram all keys to Inline Crypto Engine for MMC runtime suspend resume Crypto reprogram all keys is called for each MMC runtime suspend/resume in current upstream design. If this is implemented as a non-interruptible call to TEE for security, the cpu core is blocked for execution while this call executes although the crypto engine already has the keys. For example, glitches in audio/video streaming applications have been observed due to this. Add the flag MMC_CAP2_CRYPTO_NO_REPROG as part of host->caps2 to control reprogramming keys to crypto engine for socs which dont require this feature. Link: https://lore.kernel.org/all/20260116121004.1829223-1-neeraj.soni@oss.qualcomm.com/ Signed-off-by: Seshu Madhavi Puppala Co-developed-by: Ram Prakash Gupta Signed-off-by: Ram Prakash Gupta Co-developed-by: Sarthak Garg Signed-off-by: Sarthak Garg Signed-off-by: Debraj Mukhopadhyay Signed-off-by: Neeraj Soni Acked-by: Adrian Hunter --- drivers/mmc/core/crypto.c | 2 +- drivers/mmc/host/sdhci-msm.c | 6 ++++++ include/linux/mmc/host.h | 5 +---- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/core/crypto.c b/drivers/mmc/core/crypto.c index fec4fbf16a5b6..a5a90bfc634ee 100644 --- a/drivers/mmc/core/crypto.c +++ b/drivers/mmc/core/crypto.c @@ -15,7 +15,7 @@ void mmc_crypto_set_initial_state(struct mmc_host *host) { /* Reset might clear all keys, so reprogram all the keys. */ - if (host->caps2 & MMC_CAP2_CRYPTO) + if ((host->caps2 & MMC_CAP2_CRYPTO) && !(host->caps2 & MMC_CAP2_CRYPTO_NO_REPROG)) blk_crypto_reprogram_all_keys(&host->crypto_profile); } diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 98356c17e5386..d9338387edd58 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1947,6 +1947,7 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, } mmc->caps2 |= MMC_CAP2_CRYPTO; + mmc->caps2 |= MMC_CAP2_CRYPTO_NO_REPROG; return 0; } @@ -2564,6 +2565,11 @@ static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host) usleep_range(200, 210); reset_control_put(reset); +#ifdef CONFIG_MMC_CRYPTO + if (host->mmc->caps2 & MMC_CAP2_CRYPTO) + blk_crypto_reprogram_all_keys(&host->mmc->crypto_profile); +#endif + return ret; } diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index ba84f02c2a101..83d92fb64417f 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -457,12 +457,9 @@ struct mmc_host { #define MMC_CAP2_CQE_DCMD (1 << 24) /* CQE can issue a direct command */ #define MMC_CAP2_AVOID_3_3V (1 << 25) /* Host must negotiate down from 3.3V */ #define MMC_CAP2_MERGE_CAPABLE (1 << 26) /* Host can merge a segment over the segment size */ -#ifdef CONFIG_MMC_CRYPTO #define MMC_CAP2_CRYPTO (1 << 27) /* Host supports inline encryption */ -#else -#define MMC_CAP2_CRYPTO 0 -#endif #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */ +#define MMC_CAP2_CRYPTO_NO_REPROG (1 << 29) /* Host handles inline crypto key reprogramming */ bool uhs2_sd_tran; /* UHS-II flag for SD_TRAN state */ bool uhs2_app_cmd; /* UHS-II flag for APP command */ From a3778a4fada3b609d3f6da1a463d5aed58a8e43b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 18 Feb 2026 18:05:42 +0100 Subject: [PATCH 0250/1330] FROMLIST: arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, DisplayPort and Display Clock Controller. Link: https://lore.kernel.org/r/20260218-sm8750-display-dts-v4-1-1743e9848864@oss.qualcomm.com Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Reviewed-by: Taniya Das --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 437 +++++++++++++++++++++++++++ 1 file changed, 437 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index baaf4ca1dbfdf..cf87484a24819 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3,7 +3,9 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include +#include #include #include #include @@ -3005,6 +3007,441 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8750-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8750-dpu"; + reg = <0 0x0ae01000 0 0x93000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz = /bits/ 64 <207000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-140630000 { + opp-hz = /bits/ 64 <140630000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,sm8750-dsi-phy-3nm"; + reg = <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x280>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&bi_tcxo_div2>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae96000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,sm8750-dsi-phy-3nm"; + reg = <0x0 0x0ae97000 0x0 0x200>, + <0x0 0x0ae97200 0x0 0x280>, + <0x0 0x0ae97500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,sm8750-dp", "qcom,sm8650-dp"; + reg = <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0xc0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x9c>, + <0x0 0xaf57000 0x0 0x9c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&dp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8750-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; From db9074dae6dc4517a2fe86f329cc8ce1aaf3e71e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 18 Feb 2026 18:05:43 +0100 Subject: [PATCH 0251/1330] FROMLIST: arm64: dts: qcom: sm8750-mtp: Enable display Enable display on MTP8750 board with Novatek NT37801 panel. Link: https://lore.kernel.org/r/20260218-sm8750-display-dts-v4-2-1743e9848864@oss.qualcomm.com Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 63 +++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index cb718331496ee..050a85df7358d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -937,6 +937,48 @@ qcom,dmic-sample-rate = <4800000>; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3g_1p2>; + + status = "okay"; + + panel@0 { + compatible = "novatek,nt37801"; + reg = <0>; + + reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p0>; + + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l3i_0p88>; + + status = "okay"; +}; + &pm8550_flash { status = "okay"; @@ -1225,6 +1267,27 @@ bias-pull-up; }; + mdp_vsync: mdp-vsync-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio101"; function = "gpio"; From d90f58626ccd55c965df86f2dac0772656a526a7 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 3 Feb 2026 15:46:32 +0800 Subject: [PATCH 0252/1330] FROMLIST: arm64: dts: qcom: sm8750: enable ETR and CTCU devices Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Link: https://lore.kernel.org/all/20260204-enable-ctcu-and-etr-v3-3-0bb95c590ae1@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 177 +++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index cf87484a24819..632eb66acd017 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4015,6 +4015,35 @@ #reset-cells = <1>; }; + ctcu@10001000 { + compatible = "qcom,sm8750-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x10001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm@10002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x10002000 0x0 0x1000>, @@ -4128,6 +4157,122 @@ }; }; + replicator@10046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc@10048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x04e0 0x0>; + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@1004e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x1004e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x1004f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x0500 0x0>; + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + tpdm@10800000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x10800000 0x0 0x1000>; @@ -4798,6 +4943,38 @@ }; }; }; + + out-ports { + port { + tmc_etf_out: endpoint { + remote-endpoint = <&swao_rep_in>; + }; + }; + }; + }; + + replicator@10b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10b06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = <&tmc_etf_out>; + }; + }; + }; + + out-ports { + port { + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + }; }; tpda@10b08000 { From fded269a491376c0e2b11fa1f011b1343683a474 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sun, 22 Feb 2026 22:07:57 +0530 Subject: [PATCH 0253/1330] FROMLIST: arm64: dts: qcom: sm8750: Add camera clock controller The camera clock controller is split into cambistmclk and camcc. The cambist clock controller handles the mclks and the rest of the clocks of camera are part of the camcc clock controller. Add the camcc clock controller device node for SM8750 SoC. Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260220-sm8750_camcc_dt-v2-1-e4b7faf35854@oss.qualcomm.com Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 632eb66acd017..64199a0cc8d9d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5,6 +5,8 @@ #include #include +#include +#include #include #include #include @@ -2073,6 +2075,23 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; }; + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,sm8750-cambistmclkcc"; + reg = <0x0 0x1760000 0x0 0x6000>; + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK> , + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mmss_noc: interconnect@1780000 { compatible = "qcom,sm8750-mmss-noc"; reg = <0x0 0x01780000 0x0 0x5b800>; @@ -3442,6 +3461,23 @@ #power-domain-cells = <1>; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8750-camcc"; + reg = <0x0 0xade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; From d1ea41930ee61bf3de563017cb784558b78ad233 Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Fri, 20 Feb 2026 12:06:40 +0530 Subject: [PATCH 0254/1330] FROMLIST: arm64: dts: qcom: qcm6490-idp: Fix WCD9370 reset GPIO polarity The WCD9370 audio codec reset line on QCM6490 IDP should be active-low, but the device tree described it as active-high. As a result, the codec is kept in reset and fails to reset the SoundWire, leading to timeouts and ASoC card probe failure (-ETIMEDOUT). Fix the reset GPIO polarity to GPIO_ACTIVE_LOW so the codec can properly initialize. Link: https://lore.kernel.org/all/20260220090220.2992193-1-ravi.hothi@oss.qualcomm.com/ Fixes: aa04c298619f ("arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec") Signed-off-by: Ravi Hothi From ee92db0f4806fbed8baaeecee5d8cb3c654e2c2a Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 2 Mar 2026 17:30:34 +0530 Subject: [PATCH 0255/1330] dt-bindings: arm: qcom,ids: Add SoC ID for Shikra IoT variants Document the IDs used by Shikra SoC IoT variants: - CQ2390M: Shikra Retail with modem - CQ2390S: Shikra Retail without modem - IQ2390S: Shikra Industrial without modem Signed-off-by: Komal Bajaj --- include/dt-bindings/arm/qcom,ids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 8776844e0eeb3..31577bf12e760 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -294,6 +294,9 @@ #define QCOM_ID_QCS8275 675 #define QCOM_ID_QCS9075 676 #define QCOM_ID_QCS615 680 +#define QCOM_ID_CQ2390M 756 +#define QCOM_ID_CQ2390S 758 +#define QCOM_ID_IQ2390S 759 /* * The board type and revision information, used by Qualcomm bootloaders and From 9ad894a8387884e5da803fec9da3a794262d63c1 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 3 Mar 2026 14:25:56 +0530 Subject: [PATCH 0256/1330] soc: qcom: socinfo: Add SoC ID for Shikra IoT variants Add SoC ID for Shikra IoT variants: CQ2390M, CQ2390S and IQ2390S. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/socinfo.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 003a2304d535c..17bc07f9aaf6d 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -522,6 +522,9 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QCS8275) }, { qcom_board_id(QCS9075) }, { qcom_board_id(QCS615) }, + { qcom_board_id(CQ2390M) }, + { qcom_board_id(CQ2390S) }, + { qcom_board_id(IQ2390S) }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) From 479ec60cff410cc4a3349c780e6dc5257bf2000b Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 2 Mar 2026 18:43:41 +0530 Subject: [PATCH 0257/1330] dt-bindings: arm-smmu: Add compatible for Shikra SoC Qualcomm Shikra SoC implements arm,mmu-500. Document its compatible. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index cdbd23b5c08c1..7a7224a252f97 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -54,6 +54,7 @@ properties: - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - qcom,sdx75-smmu-500 + - qcom,shikra-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 From e8adb0fc31f195ba8d779a4147f5fadf1defe1ce Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 3 Mar 2026 14:46:00 +0530 Subject: [PATCH 0258/1330] dt-bindings: firmware: qcom,scm: Document SCM on Shikra SoC Document the SCM compatible on the Shikra SoC. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index d66459f1d84e4..4c45c207fc58e 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -62,6 +62,7 @@ properties: - qcom,scm-sdx55 - qcom,scm-sdx65 - qcom,scm-sdx75 + - qcom,scm-shikra - qcom,scm-sm6115 - qcom,scm-sm6125 - qcom,scm-sm6350 From 924508e23b6803bf35384fdba7416153b4103b6a Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Sat, 28 Feb 2026 12:29:05 +0530 Subject: [PATCH 0259/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: use DP controller native HPD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The base device tree configures the edp_hot_plug_det pin using the "edp_hot" function on GPIO 60. However, on qcs6490-rb3gen2 this external HPD GPIO does not generate a connect event when a display is already connected at boot, causing the DP/eDP display to remain disabled. The DP controller’s native HPD correctly detects the connected sink in this scenario, so continue using the DP controller native HPD on the qcs6490-rb3gen2 platform instead of the external HPD GPIO. Link: https://lore.kernel.org/all/20260228-edp_hpd_rb3_gen2_for_next-v1-1-aebc047eddc1@oss.qualcomm.com/ Signed-off-by: Vishnu Saini --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index af4925ffa40c9..b714394f9a469 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -49,8 +49,6 @@ label = "DP"; type = "mini"; - hpd-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; - port { dp_connector_in: endpoint { remote-endpoint = <&mdss_edp_out>; @@ -1714,7 +1712,6 @@ /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ &edp_hot_plug_det { - function = "gpio"; bias-disable; }; From f91403eea2fadb0a97565b2ea2b0c681348b2f81 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 3 Mar 2026 16:11:55 +0530 Subject: [PATCH 0260/1330] dt-bindings: arm: qcom: Document Shikra and its evk boards Document the device tree binding for the Shikra EVK platform, which is built around a modular System-on-Module (SoM) mounted on a common carrier board. The SoM integrates the Shikra SoC, PMICs, and essential GPIOs, while the EVK carrier board provides additional peripherals such as UART and USB interfaces. Shikra EVK supports three SoM variants: retail with modem, retail without modem, and an industrial non-modem variant. Signed-off-by: Komal Bajaj --- .../devicetree/bindings/arm/qcom.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 19e9469235e0e..2809529cb3525 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -912,6 +912,24 @@ properties: - const: qcom,qcs9100 - const: qcom,sa8775p + - items: + - enum: + - qcom,shikra-cqm-evk + - const: qcom,shikra-cqm-som + - const: qcom,shikra + + - items: + - enum: + - qcom,shikra-cqs-evk + - const: qcom,shikra-cqs-som + - const: qcom,shikra + + - items: + - enum: + - qcom,shikra-iqs-evk + - const: qcom,shikra-iqs-som + - const: qcom,shikra + - items: - enum: - google,blueline From 5c813686169e78d94618afd66517734632992960 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 8 Jan 2026 10:00:04 +0800 Subject: [PATCH 0261/1330] QCLINUX: qcom-dcc: Add driver support for Data Capture and Compare unit(DCC) The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the dcc sram. In case of a system crash or a manual software trigger by the user through the debugfs interface, the dcc captures and stores the values at these addresses. This patch contains the driver which has all the methods pertaining to the debugfs interface, auxiliary functions to support all the four fundamental operations of dcc namely read, write, read/modify/write and loop. The probe method here instantiates all the resources necessary for dcc to operate mainly the dedicated dcc sram where it stores the values. The DCC driver can be used for debugging purposes without going for a reboot since it can perform software triggers as well based on user inputs. Also add the documentation for debugfs entries which explains the functionalities of each debugfs file that has been created for dcc. The following is the justification of using debugfs interface over the other alternatives like sysfs/ioctls i) As can be seen from the debugfs attribute descriptions, some of the debugfs attribute files here contains multiple arguments which needs to be accepted from the user. This goes against the design style of sysfs. ii) The user input patterns have been made simple and convenient in this case with the use of debugfs interface as user doesn't need to shuffle between different files to execute one instruction as was the case on using other alternatives. Signed-off-by: Jie Gan --- drivers/misc/Kconfig | 8 + drivers/misc/Makefile | 1 + drivers/misc/qcom-dcc.c | 1610 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 1619 insertions(+) create mode 100644 drivers/misc/qcom-dcc.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 5cc79d1517af5..62b73f320df6d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -309,6 +309,14 @@ config QCOM_FASTRPC applications DSP processor. Say M if you want to enable this module. +config QCOM_DCC + tristate "Qualcomm Technologies, Inc. Data Capture and Compare (DCC) engine driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This option enables the driver for the Data Capture and Compare engine. DCC + driver provides interfaces to configure DCC block and read back the captured + data from the DCC's internal SRAM. The module name for this is qcom-dcc. + config SGI_GRU tristate "SGI GRU driver" depends on X86_UV && SMP diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b32a2597d2467..338ed270b7cfc 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -75,3 +75,4 @@ obj-$(CONFIG_MCHP_LAN966X_PCI) += lan966x-pci.o obj-y += keba/ obj-y += amd-sbi/ obj-$(CONFIG_MISC_RP1) += rp1/ +obj-$(CONFIG_QCOM_DCC) += qcom-dcc.o diff --git a/drivers/misc/qcom-dcc.c b/drivers/misc/qcom-dcc.c new file mode 100644 index 0000000000000..a511faac5d4b0 --- /dev/null +++ b/drivers/misc/qcom-dcc.c @@ -0,0 +1,1610 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* + * DCC(Data Capture and Compare) is a DMA engine designed for debugging + * purposes. + * In case of a system crash or manual software triggers by the user the + * DCC hardware stores the value at the register addresses which can be + * used for debugging purposes. + * The DCC driver provides the user with debugfs interface to configure the + * register addresses. The options that the DCC hardware provides include + * reading from registers, writing to registers, first reading and then + * writing to registers and looping through the values of the same + * register. + * + * In certain cases a register write needs to be executed for accessing the + * rest of the registers, also the user might want to record the changing + * values of a register with time for which he has the option to use the + * loop feature. + * + * The options mentioned above are exposed to the user by debugfs files + * once the driver is probed. The details and usage of this debugfs files + * are documented in Documentation/ABI/testing/debugfs-driver-dcc. + * + * As an example let us consider a couple of debug scenarios where DCC has + * been proved to be effective for debugging purposes:- + * + * i)TimeStamp Related Issue + * + * On SC7180, there was a coresight timestamp issue where it would + * occasionally be all 0 instead of proper timestamp values. + * + * Proper timestamp: + * Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = + * 0x13004d8f5b7aa; CC=0x9e + * + * Zero timestamp: + * Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2 + * + * Now this is a non-fatal issue and doesn't need a system reset, but still + * needs to be rootcaused and fixed for those who do care about coresight + * etm traces. + * Since this is a timestamp issue, we would be looking for any timestamp + * related clocks and such. + * + * We get all the clk register details from IP documentation and configure + * it via DCC config debugfs node. Before that we set the current + * linked list. + * + * Program the linked list with the addresses + * echo R 0x10c004 > /sys/kernel/debug/qcom-dcc/../3/config + * echo R 0x10c008 > /sys/kernel/debug/qcom-dcc/../3/config + * echo R 0x10c00c > /sys/kernel/debug/qcom-dcc/../3/config + * echo R 0x10c010 > /sys/kernel/debug/qcom-dcc/../3/config + * ..... and so on for other timestamp related clk registers + * + * Other way of specifying is in "addr len" pair, in below case it + * specifies to capture 4 words starting 0x10C004 + * + * echo R 0x10C004 4 > /sys/kernel/debug/qcom-dcc/../3/config + * + * Configuration can be saved to a file and reuse it later. + * cat /sys/kernel/debug/qcom-dcc/../3/config > config_3 + * Post reboot, write the file to config. + * echo config_3 > /sys/kernel/debug/qcom-dcc/../3/config + * + * Enable DCC + * echo 1 > /sys/kernel/debug/qcom-dcc/../3/enable + * + * Run the timestamp test for working case + * + * Send SW trigger + * echo 1 > /sys/kernel/debug/qcom-dcc/../trigger + * + * Read SRAM + * cat /dev/dcc_sram > dcc_sram1.bin + * + * Run the timestamp test for non-working case + * + * Send SW trigger + * echo 1 > /sys/kernel/debug/qcom-dcc/../trigger + * + * Read SRAM + * cat /dev/dcc_sram > dcc_sram2.bin + * + * Get the parser from + * https://git.codelinaro.org/clo/le/platform/vendor/qcom-opensource/tools/-/tree/opensource-tools.lnx.1.0.r176-rel/dcc_parser + * + * Parse the SRAM bin + * python dcc_parser.py -s dcc_sram1.bin --v2 -o output/ python + * dcc_parser.py -s dcc_sram2.bin --v2 -o output/ + * + * Sample parsed output of dcc_sram1.bin: + * + * + * 03/14/21 + * Linux DCC Parser + * + * + * + * + * + * + * next_ll_offset : 0x1c + * + * ii)NOC register errors + * + * A particular class of registers called NOC which are functional + * registers was reporting errors while logging the values.To trace these + * errors the DCC has been used effectively. + * The steps followed were similar to the ones mentioned above. + * In addition to NOC registers a few other dependent registers were + * configured in DCC to monitor it's values during a crash. A look at the + * dependent register values revealed that the crash was happening due to a + * secured access to one of these dependent registers. + * All these debugging activity and finding the root cause was achieved + * using DCC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STATUS_READY_TIMEOUT 5000 /* microseconds */ + +/* DCC registers */ +#define DCC_HW_INFO 0x04 +#define DCC_LL_NUM_INFO 0x10 +#define DCC_LL_LOCK 0x00 +#define DCC_LL_CFG 0x04 +#define DCC_LL_BASE 0x08 +#define DCC_FD_BASE 0x0c +#define DCC_LL_OFFSET 0x80 +#define DCC_LL_TIMEOUT 0x10 +#define DCC_LL_INT_ENABLE 0x18 +#define DCC_LL_INT_STATUS 0x1c +#define DCC_LL_SW_TRIGGER 0x2c +#define DCC_LL_BUS_ACCESS_STATUS 0x30 + +/* Default value used if a bit 6 in the HW_INFO register is set. */ +#define DCC_FIX_LOOP_OFFSET 16 + +/* Mask to find version info from HW_Info register */ +#define DCC_VER_INFO_MASK BIT(9) + +#define MAX_DCC_OFFSET GENMASK(9, 2) +#define MAX_DCC_LEN GENMASK(6, 0) +#define MAX_LOOP_CNT GENMASK(7, 0) +#define MAX_LOOP_ADDR 10 + +#define DCC_ADDR_DESCRIPTOR 0x00 +#define DCC_ADDR_LIMIT 27 +#define DCC_WORD_SIZE sizeof(u32) +#define DCC_ADDR_RANGE_MASK GENMASK(31, 4) +#define DCC_LOOP_DESCRIPTOR BIT(30) +#define DCC_RD_MOD_WR_DESCRIPTOR BIT(31) +#define DCC_LINK_DESCRIPTOR GENMASK(31, 30) +#define DCC_STATUS_MASK GENMASK(1, 0) +#define DCC_LOCK_MASK BIT(0) +#define DCC_LOOP_OFFSET_MASK BIT(6) +#define DCC_TRIGGER_MASK BIT(9) + +#define DCC_WRITE_MASK BIT(15) +#define DCC_WRITE_OFF_MASK GENMASK(7, 0) +#define DCC_WRITE_LEN_MASK GENMASK(14, 8) + +#define DCC_READ_IND 0x00 +#define DCC_WRITE_IND (BIT(28)) + +#define DCC_AHB_IND 0x00 +#define DCC_APB_IND BIT(29) + +#define DCC_MAX_LINK_LIST 8 + +#define DCC_VER_MASK2 GENMASK(5, 0) + +#define DCC_SRAM_WORD_LENGTH 4 + +#define DCC_RD_MOD_WR_ADDR 0xC105E + +#define MEM_MAP_VER1 0x1 +#define MEM_MAP_VER2 0x2 +#define MEM_MAP_VER3 0x3 + +#define LINE_BUFFER_MAX_SZ 50 +enum dcc_descriptor_type { + DCC_READ_TYPE, + DCC_LOOP_TYPE, + DCC_READ_WRITE_TYPE, + DCC_WRITE_TYPE +}; + +/** + * struct dcc_config_entry - configuration information related to each dcc instruction + * @base: Base address of the register to be configured in dcc + * @offset: Offset to the base address to be configured in dcc + * @len: Length of the address in words of 4 bytes to be configured in dcc + * @loop_cnt: The number of times to loop on the register address in case + of loop instructions + * @write_val: The value to be written on the register address in case of + write instructions + * @mask: Mask corresponding to the value to be written in case of + write instructions + * @apb_bus: Type of bus to be used for the instruction, can be either + 'apb' if 1 or 'ahb' if 0 + * @desc_type: Stores the type of dcc instruction + * @list: This is used to append this instruction to the list of + instructions + */ +struct dcc_config_entry { + u32 base; + u32 offset; + u32 len; + u32 loop_cnt; + u32 write_val; + u32 mask; + bool apb_bus; + enum dcc_descriptor_type desc_type; + struct list_head list; +}; + +/** + * struct dcc_drvdata - configuration information related to a dcc device + * @base: Base Address of the dcc device + * @dev: The device attached to the driver data + * @mutex: Lock to protect access and manipulation of dcc_drvdata + * @ram_base: Base address for the SRAM dedicated for the dcc device + * @ram_size: Total size of the SRAM dedicated for the dcc device + * @ram_offset: Offset to the SRAM dedicated for dcc device + * @ram_cfg: Used for address limit calculation for dcc + * @ram_start: Starting address of DCC SRAM + * @mem_map_ver: Memory map version of DCC hardware + * @sram_dev: Miscellaneous device equivalent of dcc SRAM + * @cfg_head: Points to the head of the linked list of addresses + * @dbg_dir: The dcc debugfs directory under which all the debugfs files are placed + * @max_link_list: Total number of linkedlists supported by the DCC configuration + * @loop_shift: Loop offset bits range for the addresses + * @enable_bitmap: Bitmap to capture the enabled status of each linked list of addresses + */ +struct dcc_drvdata { + void __iomem *base; + void __iomem *ram_base; + struct device *dev; + /* Lock to protect access and manipulation of dcc_drvdata */ + struct mutex mutex; + size_t ram_size; + u32 ram_offset; + unsigned int ram_cfg; + unsigned int ram_start; + u64 mem_map_ver; + struct miscdevice sram_dev; + struct list_head *cfg_head; + struct dentry *dbg_dir; + size_t max_link_list; + u8 loop_shift; + unsigned long *enable_bitmap; + char **temp_buff_ptr; +}; + +struct dcc_cfg_attr { + u32 addr; + u32 prev_addr; + u32 prev_off; + u32 link; + u32 sram_offset; +}; + +struct dcc_cfg_loop_attr { + u32 loop_cnt; + u32 loop_len; + u32 loop_off; + bool loop_start; +}; + +static inline u32 dcc_status(int version) +{ + return version == 1 ? 0x0c : 0x1c; +} + +static inline u32 dcc_list_offset(int version) +{ + if (version == 1) + return 0x1c; + else if (version == 2) + return 0x2c; + else + return 0x34; +} + +static inline void dcc_list_writel(struct dcc_drvdata *drvdata, + u32 val, u32 ll, u32 off) +{ + u32 offset = dcc_list_offset(drvdata->mem_map_ver) + off; + + writel(val, drvdata->base + ll * DCC_LL_OFFSET + offset); +} + +static inline u32 dcc_list_readl(struct dcc_drvdata *drvdata, u32 ll, u32 off) +{ + u32 offset = dcc_list_offset(drvdata->mem_map_ver) + off; + + return readl(drvdata->base + ll * DCC_LL_OFFSET + offset); +} + +static void dcc_sram_write_auto(struct dcc_drvdata *drvdata, + u32 val, u32 *off) +{ + /* If the overflow condition is met increment the offset + * and return to indicate that overflow has occurred + */ + if (*off > drvdata->ram_size - 4) { + *off += 4; + return; + } + + writel(val, drvdata->ram_base + *off); + + *off += 4; +} + +static int dcc_sw_trigger(struct dcc_drvdata *drvdata) +{ + void __iomem *addr; + int i; + u32 status; + u32 ll_cfg; + u32 tmp_ll_cfg; + u32 val; + int ret = 0; + + mutex_lock(&drvdata->mutex); + + for (i = 0; i < drvdata->max_link_list; i++) { + if (!test_bit(i, drvdata->enable_bitmap)) + continue; + ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); + if (drvdata->mem_map_ver == MEM_MAP_VER3) + tmp_ll_cfg = ll_cfg & ~BIT(8); + else + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + + dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); + dcc_list_writel(drvdata, 1, i, DCC_LL_SW_TRIGGER); + dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); + } + + addr = drvdata->base + dcc_status(drvdata->mem_map_ver); + if (readl_poll_timeout(addr, val, !FIELD_GET(DCC_STATUS_MASK, val), + 1, STATUS_READY_TIMEOUT)) { + dev_err(drvdata->dev, "DCC is busy after receiving sw trigger\n"); + ret = -EBUSY; + goto out_unlock; + } + + for (i = 0; i < drvdata->max_link_list; i++) { + if (!test_bit(i, drvdata->enable_bitmap)) + continue; + + status = dcc_list_readl(drvdata, i, DCC_LL_BUS_ACCESS_STATUS); + if (!status) + continue; + + dev_err(drvdata->dev, "Read access error for list %d err: 0x%x\n", + i, status); + ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); + if (drvdata->mem_map_ver == MEM_MAP_VER3) + tmp_ll_cfg = ll_cfg & ~BIT(8); + else + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + + dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); + dcc_list_writel(drvdata, DCC_STATUS_MASK, i, DCC_LL_BUS_ACCESS_STATUS); + dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); + ret = -ENODATA; + break; + } + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg) +{ + cfg->addr = 0x00; + cfg->link = 0; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; +} + +static void dcc_emit_read_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg) +{ + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + /* Reset link and prev_off */ + dcc_ll_cfg_reset_link(cfg); + } + + cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->mask, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); + + cfg->addr = 0; +} + +static void dcc_emit_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + struct dcc_cfg_loop_attr *cfg_loop, + u32 *total_len) +{ + int loop; + + /* Check if we need to write link of prev entry */ + if (cfg->link) + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + if (cfg_loop->loop_start) { + loop = (cfg->sram_offset - cfg_loop->loop_off) / 4; + loop |= (cfg_loop->loop_cnt << drvdata->loop_shift) & + GENMASK(DCC_ADDR_LIMIT, drvdata->loop_shift); + loop |= DCC_LOOP_DESCRIPTOR; + *total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt; + + dcc_sram_write_auto(drvdata, loop, &cfg->sram_offset); + + cfg_loop->loop_start = false; + cfg_loop->loop_len = 0; + cfg_loop->loop_off = 0; + } else { + cfg_loop->loop_start = true; + cfg_loop->loop_cnt = entry->loop_cnt - 1; + cfg_loop->loop_len = *total_len; + cfg_loop->loop_off = cfg->sram_offset; + } + + /* Reset link and prev_off */ + dcc_ll_cfg_reset_link(cfg); +} + +static void dcc_emit_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg) +{ + u32 off; + + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + /* Reset link and prev_off */ + cfg->addr = 0x00; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; + } + + off = entry->offset / 4; + /* write new offset-length pair to correct position */ + cfg->link |= ((off & DCC_WRITE_OFF_MASK) | DCC_WRITE_MASK | + FIELD_PREP(DCC_WRITE_LEN_MASK, entry->len)); + cfg->link |= DCC_LINK_DESCRIPTOR; + + /* Address type */ + cfg->addr = (entry->base >> 4) & GENMASK(DCC_ADDR_LIMIT, 0); + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND; + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); + + cfg->addr = 0x00; + cfg->link = 0; +} + +static int dcc_emit_read(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + u32 *pos, u32 *total_len) +{ + u32 off; + u32 temp_off; + + cfg->addr = (entry->base >> 4) & GENMASK(27, 0); + + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND; + + off = entry->offset / 4; + + *total_len += entry->len * 4; + + if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) { + /* Check if we need to write prev link entry */ + if (cfg->link) + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset); + + /* Write address */ + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + /* Reset link and prev_off */ + cfg->link = 0; + cfg->prev_off = 0; + } + + if ((off - cfg->prev_off) > 0xff || entry->len > MAX_DCC_LEN) { + dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n", + entry->base, entry->offset); + return -EINVAL; + } + + if (cfg->link) { + /* + * link already has one offset-length so new + * offset-length needs to be placed at + * bits [29:15] + */ + *pos = 15; + + /* Clear bits [31:16] */ + cfg->link &= GENMASK(14, 0); + } else { + /* + * link is empty, so new offset-length needs + * to be placed at bits [15:0] + */ + *pos = 0; + cfg->link = 1 << 15; + } + + /* write new offset-length pair to correct position */ + temp_off = (off - cfg->prev_off) & GENMASK(7, 0); + cfg->link |= (temp_off | ((entry->len << 8) & GENMASK(14, 8))) << *pos; + + cfg->link |= DCC_LINK_DESCRIPTOR; + + if (*pos) { + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + cfg->link = 0; + } + + cfg->prev_off = off + entry->len - 1; + cfg->prev_addr = cfg->addr; + return 0; +} + +static int dcc_emit_config(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + int ret; + u32 total_len, pos; + struct dcc_config_entry *entry; + struct dcc_cfg_attr cfg = {0}; + struct dcc_cfg_loop_attr cfg_loop = {0}; + + cfg.sram_offset = drvdata->ram_cfg * 4; + total_len = 0; + + list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + dcc_emit_read_write(drvdata, entry, &cfg); + break; + + case DCC_LOOP_TYPE: + dcc_emit_loop(drvdata, entry, &cfg, &cfg_loop, &total_len); + break; + + case DCC_WRITE_TYPE: + dcc_emit_write(drvdata, entry, &cfg); + break; + + case DCC_READ_TYPE: + ret = dcc_emit_read(drvdata, entry, &cfg, &pos, &total_len); + if (ret) + goto err; + break; + } + } + + if (cfg.link) + dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); + + if (cfg_loop.loop_start) { + dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n"); + ret = -EINVAL; + goto err; + } + + /* Handling special case of list ending with a rd_mod_wr */ + if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) { + cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0); + cfg.addr |= DCC_ADDR_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg.addr, &cfg.sram_offset); + } + + /* Setting zero to indicate end of the list */ + cfg.link = DCC_LINK_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); + + /* Check if sram offset exceeds the ram size */ + if (cfg.sram_offset > drvdata->ram_size) + goto overstep; + + /* Update ram_cfg and check if the data will overstep */ + drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4; + + if (cfg.sram_offset + total_len > drvdata->ram_size) { + cfg.sram_offset += total_len; + goto overstep; + } + + drvdata->ram_start = cfg.sram_offset / 4; + return 0; +overstep: + ret = -EINVAL; + memset_io(drvdata->ram_base, 0, drvdata->ram_size); + +err: + return ret; +} + +static bool dcc_valid_list(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + u32 lock_reg; + + if (list_empty(&drvdata->cfg_head[curr_list])) + return false; + + if (test_bit(curr_list, drvdata->enable_bitmap)) { + dev_err(drvdata->dev, "List %d is already enabled\n", curr_list); + return false; + } + + lock_reg = dcc_list_readl(drvdata, curr_list, DCC_LL_LOCK); + if (lock_reg & DCC_LOCK_MASK) { + dev_err(drvdata->dev, "List %d is already locked\n", curr_list); + return false; + } + + return true; +} + +static bool is_dcc_enabled(struct dcc_drvdata *drvdata) +{ + int list; + + for (list = 0; list < drvdata->max_link_list; list++) + if (test_bit(list, drvdata->enable_bitmap)) + return true; + + return false; +} + +static int dcc_enable(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + int ret; + u32 ram_cfg_base; + + mutex_lock(&drvdata->mutex); + + if (!dcc_valid_list(drvdata, curr_list)) { + ret = -EINVAL; + goto out_unlock; + } + + /* Fill dcc sram with the poison value. + * This helps in understanding bus + * hang from registers returning a zero + */ + if (!is_dcc_enabled(drvdata)) + memset_io(drvdata->ram_base, 0xde, drvdata->ram_size); + + /* 1. Take ownership of the list */ + dcc_list_writel(drvdata, DCC_LOCK_MASK, curr_list, DCC_LL_LOCK); + + /* 2. Program linked-list in the SRAM */ + ram_cfg_base = drvdata->ram_cfg; + ret = dcc_emit_config(drvdata, curr_list); + if (ret) { + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_LOCK); + goto out_unlock; + } + + /* 3. Program DCC_RAM_CFG reg */ + dcc_list_writel(drvdata, ram_cfg_base + + drvdata->ram_offset / 4, curr_list, DCC_LL_BASE); + dcc_list_writel(drvdata, drvdata->ram_start + + drvdata->ram_offset / 4, curr_list, DCC_FD_BASE); + dcc_list_writel(drvdata, 0xFFF, curr_list, DCC_LL_TIMEOUT); + + /* 4. Clears interrupt status register */ + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_INT_ENABLE); + dcc_list_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), + curr_list, DCC_LL_INT_STATUS); + + set_bit(curr_list, drvdata->enable_bitmap); + + /* 5. Configure trigger */ + if (drvdata->mem_map_ver == MEM_MAP_VER3) + dcc_list_writel(drvdata, BIT(8), + curr_list, DCC_LL_CFG); + else + dcc_list_writel(drvdata, DCC_TRIGGER_MASK, + curr_list, DCC_LL_CFG); + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void dcc_disable(struct dcc_drvdata *drvdata, int curr_list) +{ + mutex_lock(&drvdata->mutex); + + if (!test_bit(curr_list, drvdata->enable_bitmap)) + goto out_unlock; + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_CFG); + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_BASE); + dcc_list_writel(drvdata, 0, curr_list, DCC_FD_BASE); + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_LOCK); + clear_bit(curr_list, drvdata->enable_bitmap); +out_unlock: + mutex_unlock(&drvdata->mutex); +} + +static u32 dcc_filp_curr_list(const struct file *filp) +{ + struct dentry *dentry = file_dentry(filp); + int curr_list, ret; + + ret = kstrtoint(dentry->d_parent->d_name.name, 0, &curr_list); + if (ret) + return ret; + + return curr_list; +} + +static ssize_t enable_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf; + int curr_list = dcc_filp_curr_list(filp); + struct dcc_drvdata *drvdata = filp->private_data; + + if (curr_list < 0) + return curr_list; + + mutex_lock(&drvdata->mutex); + if (test_bit(curr_list, drvdata->enable_bitmap)) + buf = "Y\n"; + else + buf = "N\n"; + mutex_unlock(&drvdata->mutex); + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); +} + +static ssize_t enable_write(struct file *filp, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret = 0, curr_list; + bool val; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) + return curr_list; + + ret = kstrtobool_from_user(userbuf, count, &val); + if (ret < 0) + return ret; + + if (val) { + ret = dcc_enable(drvdata, curr_list); + if (ret) + return ret; + } else { + dcc_disable(drvdata, curr_list); + } + + return count; +} + +static const struct file_operations enable_fops = { + .read = enable_read, + .write = enable_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t trigger_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + int ret; + unsigned int val; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = kstrtouint_from_user(user_buf, count, 0, &val); + if (ret < 0) + return ret; + + if (val != 1) + return -EINVAL; + + ret = dcc_sw_trigger(drvdata); + if (ret < 0) + return ret; + + return count; +} + +static const struct file_operations trigger_fops = { + .write = trigger_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int len, bool apb_bus, int curr_list) +{ + int ret = 0; + struct dcc_config_entry *entry, *pentry; + unsigned int base, offset; + + mutex_lock(&drvdata->mutex); + + if (!len || len > drvdata->ram_size / DCC_WORD_SIZE) { + dev_err(drvdata->dev, "DCC: Invalid length\n"); + ret = -EINVAL; + goto out_unlock; + } + + base = addr & DCC_ADDR_RANGE_MASK; + + if (!list_empty(&drvdata->cfg_head[curr_list])) { + pentry = list_last_entry(&drvdata->cfg_head[curr_list], + struct dcc_config_entry, list); + + if (pentry->desc_type == DCC_READ_TYPE && + addr >= (pentry->base + pentry->offset) && + addr <= (pentry->base + pentry->offset + MAX_DCC_OFFSET)) { + /* Re-use base address from last entry */ + base = pentry->base; + + if ((pentry->len * 4 + pentry->base + pentry->offset) + == addr) { + len += pentry->len; + + if (len > MAX_DCC_LEN) + pentry->len = MAX_DCC_LEN; + else + pentry->len = len; + + addr = pentry->base + pentry->offset + + pentry->len * 4; + len -= pentry->len; + } + } + } + + offset = addr - base; + + while (len) { + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto out_unlock; + } + + entry->base = base; + entry->offset = offset; + entry->len = min_t(u32, len, MAX_DCC_LEN); + entry->desc_type = DCC_READ_TYPE; + entry->apb_bus = apb_bus; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, + &drvdata->cfg_head[curr_list]); + + len -= entry->len; + offset += MAX_DCC_LEN * 4; + } + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t dcc_config_add_read(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + bool bus; + int len, nval; + unsigned int base; + char apb_bus[4]; + + nval = sscanf(buf, "%x %i %3s", &base, &len, apb_bus); + if (nval <= 0 || nval > 3) + return -EINVAL; + + if (nval == 1) { + len = 1; + bus = false; + } else if (nval == 2) { + bus = false; + } else if (!strcmp("apb", apb_bus)) { + bus = true; + } else if (!strcmp("ahb", apb_bus)) { + bus = false; + } else { + return -EINVAL; + } + + return dcc_config_add(drvdata, base, len, bus, curr_list); +} + +static void dcc_config_reset(struct dcc_drvdata *drvdata) +{ + struct dcc_config_entry *entry, *temp; + int curr_list; + + mutex_lock(&drvdata->mutex); + + for (curr_list = 0; curr_list < drvdata->max_link_list; curr_list++) { + list_for_each_entry_safe(entry, temp, + &drvdata->cfg_head[curr_list], list) { + list_del(&entry->list); + } + } + drvdata->ram_start = 0; + drvdata->ram_cfg = 0; + mutex_unlock(&drvdata->mutex); +} + +static ssize_t config_reset_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + unsigned int val; + int ret; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = kstrtouint_from_user(user_buf, count, 0, &val); + if (ret < 0) + return ret; + + if (val) + dcc_config_reset(drvdata); + + return count; +} + +static const struct file_operations config_reset_fops = { + .write = config_reset_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t ready_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf; + struct dcc_drvdata *drvdata = filp->private_data; + + if (!is_dcc_enabled(drvdata)) + return -EINVAL; + + if (!FIELD_GET(BIT(1), readl(drvdata->base + dcc_status(drvdata->mem_map_ver)))) + buf = "Y\n"; + else + buf = "N\n"; + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf) + 1); +} + +static const struct file_operations ready_fops = { + .read = ready_read, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t loop_offset_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char buf[4]; + struct dcc_drvdata *drvdata = filp->private_data; + + snprintf(buf, sizeof(buf), "%d", drvdata->loop_shift); + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf) + 1); +} + +static const struct file_operations loop_offset_fops = { + .read = loop_offset_read, + .open = simple_open, + .llseek = generic_file_llseek, +}; +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt, int curr_list) +{ + struct dcc_config_entry *entry; + + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT); + entry->desc_type = DCC_LOOP_TYPE; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + return 0; +} + +static ssize_t dcc_config_add_loop(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret, i = 0; + char *token, *input; + char delim[2] = " "; + unsigned int val[MAX_LOOP_ADDR]; + + input = buf; + + while ((token = strsep(&input, delim)) && i < MAX_LOOP_ADDR) { + ret = kstrtouint(token, 0, &val[i++]); + if (ret) + return ret; + } + + if (token) { + dev_err(drvdata->dev, "Max limit %u of loop address exceeded\n", + MAX_LOOP_ADDR); + return -EINVAL; + } + + if (val[1] < 1 || val[1] > 8 || val[1] > (i - 2)) + return -EINVAL; + + ret = dcc_add_loop(drvdata, val[0], curr_list); + if (ret) + return ret; + + for (i = 0; i < val[1]; i++) + dcc_config_add(drvdata, val[i + 2], 1, false, curr_list); + + return dcc_add_loop(drvdata, 1, curr_list); +} + +static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask, + unsigned int val, int curr_list) +{ + int ret = 0; + struct dcc_config_entry *entry; + + mutex_lock(&drvdata->mutex); + + if (list_empty(&drvdata->cfg_head[curr_list])) { + dev_err(drvdata->dev, "DCC: No read address programmed\n"); + ret = -EPERM; + goto out_unlock; + } + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto out_unlock; + } + + entry->desc_type = DCC_READ_WRITE_TYPE; + entry->mask = mask; + entry->write_val = val; + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t dcc_config_add_read_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret; + int nval; + unsigned int addr, mask, val; + + nval = sscanf(buf, "%x %x %x", &addr, &mask, &val); + + if (nval <= 1 || nval > 3) + return -EINVAL; + + ret = dcc_config_add(drvdata, addr, 1, false, curr_list); + if (ret) + return ret; + + return dcc_rd_mod_wr_add(drvdata, mask, val, curr_list); +} + +static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int write_val, int apb_bus, int curr_list) +{ + struct dcc_config_entry *entry; + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->desc_type = DCC_WRITE_TYPE; + entry->base = addr & GENMASK(31, 4); + entry->offset = addr - entry->base; + entry->write_val = write_val; + entry->len = 1; + entry->apb_bus = apb_bus; + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + return 0; +} + +static ssize_t dcc_config_add_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + bool bus; + int nval; + unsigned int addr, write_val; + char apb_bus[4]; + + nval = sscanf(buf, "%x %x %3s", &addr, &write_val, apb_bus); + + if (nval <= 1 || nval > 3) + return -EINVAL; + + if (nval == 2) + bus = false; + + if (nval == 3) { + if (!strcmp("apb", apb_bus)) + bus = true; + else if (!strcmp("ahb", apb_bus)) + bus = false; + else + return -EINVAL; + } + + return dcc_add_write(drvdata, addr, write_val, bus, curr_list); +} + +static int config_show(struct seq_file *m, void *data) +{ + struct dcc_drvdata *drvdata = m->private; + struct dcc_config_entry *entry, *next_entry, *prev_entry, *loop_entry; + int index = 0, curr_list, i; + unsigned int loop_val[MAX_LOOP_ADDR]; + + curr_list = dcc_filp_curr_list(m->file); + if (curr_list < 0) + return curr_list; + + mutex_lock(&drvdata->mutex); + + list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { + index++; + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + prev_entry = list_prev_entry(entry, list); + seq_printf(m, "RW 0x%x 0x%x 0x%x\n", + prev_entry->base + prev_entry->offset, + entry->mask, + entry->write_val); + break; + case DCC_LOOP_TYPE: + loop_entry = entry; + loop_val[0] = loop_entry->loop_cnt; + loop_entry = list_next_entry(loop_entry, list); + for (i = 0; i < (MAX_LOOP_ADDR-2); + i++, loop_entry = list_next_entry(loop_entry, list)) { + if (loop_entry->desc_type == DCC_READ_TYPE) { + loop_val[i+2] = loop_entry->base + loop_entry->offset; + } else if (loop_entry->desc_type == DCC_LOOP_TYPE) { + loop_val[i+2] = loop_entry->loop_cnt; + loop_val[1] = i; + entry = loop_entry; + break; + } + } + seq_printf(m, "L 0x%x 0x%x", loop_val[0], loop_val[1]); + for (i = 0; i < loop_val[1]; i++) + seq_printf(m, " 0x%x", loop_val[i+2]); + seq_puts(m, "\n"); + break; + case DCC_WRITE_TYPE: + seq_printf(m, "W 0x%x 0x%x %s\n", + entry->base + entry->offset, + entry->write_val, + entry->apb_bus ? "apb":"ahb"); + break; + case DCC_READ_TYPE: + if (entry->len == 1) { + next_entry = list_next_entry(entry, list); + if (next_entry && next_entry->desc_type == DCC_READ_WRITE_TYPE) + continue; + } + seq_printf(m, "R 0x%x 0x%x %s\n", + entry->base + entry->offset, + entry->len, + entry->apb_bus ? "apb":"ahb"); + } + } + mutex_unlock(&drvdata->mutex); + return 0; +} + +static int config_open(struct inode *inode, struct file *file) +{ + struct dcc_drvdata *drvdata = inode->i_private; + + return single_open(file, config_show, drvdata); +} + +static ssize_t config_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + int ret, curr_list; + char *token, *line; + char *buf, *bufp, *temp_buff; + char *delim = " "; + struct dcc_drvdata *drvdata = filp->f_inode->i_private; + ssize_t processed_len = 0; + + if (count == 0) + return -EINVAL; + buf = kzalloc(count+1, GFP_KERNEL); + if (buf) + bufp = buf; + else + return -ENOMEM; + + ret = copy_from_user(buf, user_buf, count); + if (ret) + goto err; + + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) { + ret = curr_list; + goto err; + } + + while (bufp[0] != '\0') { + /* Parse line by line */ + line = strsep(&bufp, "\n"); + /* When one complete line could be parsed */ + if (line && bufp) { + processed_len += strlen(line) + 1; + if (drvdata->temp_buff_ptr && drvdata->temp_buff_ptr[curr_list]) { + temp_buff = drvdata->temp_buff_ptr[curr_list]; + /* Size of combined string must not be greater than + * allowed line size. + */ + if (strlen(line) + strlen(temp_buff) + 1 > LINE_BUFFER_MAX_SZ) { + dev_err(drvdata->dev, "Invalid input\n"); + ret = -EINVAL; + goto err; + } + strlcat(temp_buff, line, PAGE_SIZE); + line = temp_buff; + kfree(temp_buff); + drvdata->temp_buff_ptr[curr_list] = NULL; + } + + token = strsep(&line, delim); + + if (!strcmp("R", token)) { + ret = dcc_config_add_read(drvdata, line, curr_list); + } else if (!strcmp("W", token)) { + ret = dcc_config_add_write(drvdata, line, curr_list); + } else if (!strcmp("RW", token)) { + ret = dcc_config_add_read_write(drvdata, line, curr_list); + } else if (!strcmp("L", token)) { + ret = dcc_config_add_loop(drvdata, line, curr_list); + } else { + dev_err(drvdata->dev, "%s is not a correct input\n", token); + ret = -EINVAL; + } + + if (ret) + goto err; + } else { + /* Save the incomplete line to a temporary buffer and rejoin it later */ + if (!drvdata->temp_buff_ptr) { + drvdata->temp_buff_ptr = devm_kcalloc(drvdata->dev, + drvdata->max_link_list, + sizeof(char *), + GFP_KERNEL); + if (!drvdata->temp_buff_ptr) { + ret = -ENOMEM; + goto err; + } + } + drvdata->temp_buff_ptr[curr_list] = kzalloc(LINE_BUFFER_MAX_SZ, + GFP_KERNEL); + temp_buff = drvdata->temp_buff_ptr[curr_list]; + if (!temp_buff) { + ret = -ENOMEM; + goto err; + } + if ((count - processed_len) >= LINE_BUFFER_MAX_SZ) { + dev_err(drvdata->dev, "Invalid input\n"); + ret = -EINVAL; + goto err; + } + memcpy(temp_buff, line, count - processed_len); + temp_buff[count - processed_len + 1] = '\0'; + processed_len += (strlen(temp_buff) + 1); + break; + } + } + + kfree(buf); + return processed_len; + +err: + kfree(buf); + if (drvdata->temp_buff_ptr && drvdata->temp_buff_ptr[curr_list]) { + kfree(drvdata->temp_buff_ptr[curr_list]); + drvdata->temp_buff_ptr[curr_list] = NULL; + } + return ret; +} + +static const struct file_operations config_fops = { + .open = config_open, + .read = seq_read, + .write = config_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static void dcc_delete_debug_dir(struct dcc_drvdata *drvdata) +{ + debugfs_remove_recursive(drvdata->dbg_dir); +}; + +static void dcc_create_debug_dir(struct dcc_drvdata *drvdata) +{ + int i; + char list_num[10]; + struct dentry *dcc_dev, *list; + struct device *dev = drvdata->dev; + + drvdata->dbg_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); + dcc_dev = debugfs_create_dir(dev_name(dev), drvdata->dbg_dir); + + for (i = 0; i < drvdata->max_link_list; i++) { + snprintf(list_num, sizeof(list_num), "%d", i); + list = debugfs_create_dir(list_num, dcc_dev); + debugfs_create_file("enable", 0600, list, drvdata, &enable_fops); + debugfs_create_file("config", 0600, list, drvdata, &config_fops); + } + + debugfs_create_file("trigger", 0200, drvdata->dbg_dir, drvdata, &trigger_fops); + debugfs_create_file("ready", 0400, drvdata->dbg_dir, drvdata, &ready_fops); + debugfs_create_file("config_reset", 0200, drvdata->dbg_dir, drvdata, &config_reset_fops); + debugfs_create_file("loop_offset", 0400, drvdata->dbg_dir, drvdata, &loop_offset_fops); +} + +static ssize_t dcc_sram_read(struct file *file, char __user *data, + size_t len, loff_t *ppos) +{ + unsigned char *buf; + struct dcc_drvdata *drvdata; + + drvdata = container_of(file->private_data, struct dcc_drvdata, + sram_dev); + + /* EOF check */ + if (*ppos >= drvdata->ram_size) + return 0; + + if ((*ppos + len) > drvdata->ram_size) + len = (drvdata->ram_size - *ppos); + + buf = kzalloc(len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + memcpy_fromio(buf, drvdata->ram_base + *ppos, len); + + if (copy_to_user(data, buf, len)) { + kfree(buf); + return -EFAULT; + } + + *ppos += len; + + kfree(buf); + + return len; +} + +static void dcc_configure_list(struct dcc_drvdata *drvdata, struct device_node *np) +{ + const char *prop; + int ret, curr_list, index = 0; + char *token, *bufp; + char *delim = " "; + u32 len, processed_len = 0; + + ret = of_property_read_u32(np, "qcom,curr-link-list", + &curr_list); + if (ret) + return; + + if(!of_get_property(np, "qcom,link-list", &len)) + return; + + bufp = kzalloc(len+1, GFP_KERNEL); + if (!bufp) + return; + + while (!of_property_read_string_index(np, "qcom,link-list", index, &prop)) { + strncpy(bufp, prop, strlen(prop)); + bufp[strlen(prop)] = '\0'; + + processed_len += strlen(bufp) + 1; + + token = strsep(&bufp, delim); + + if (!strcmp("R", token)) { + ret = dcc_config_add_read(drvdata, bufp, curr_list); + } else if (!strcmp("W", token)) { + ret = dcc_config_add_write(drvdata, bufp, curr_list); + } else if (!strcmp("RW", token)) { + ret = dcc_config_add_read_write(drvdata, bufp, curr_list); + } else if (!strcmp("L", token)) { + ret = dcc_config_add_loop(drvdata, bufp, curr_list); + } else { + dev_err(drvdata->dev, "%s is not a correct input\n", token); + ret = -EINVAL; + } + + if (ret < 0) + dev_err(drvdata->dev, "Configure line %s failed\n", prop); + + index++; + } + + dcc_enable(drvdata, curr_list); + kfree(bufp); +} + +static const struct file_operations dcc_sram_fops = { + .owner = THIS_MODULE, + .read = dcc_sram_read, +}; + +static int dcc_sram_dev_init(struct dcc_drvdata *drvdata) +{ + drvdata->sram_dev.minor = MISC_DYNAMIC_MINOR; + drvdata->sram_dev.name = "dcc_sram"; + drvdata->sram_dev.fops = &dcc_sram_fops; + + return misc_register(&drvdata->sram_dev); +} + +static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata) +{ + misc_deregister(&drvdata->sram_dev); +} + +static int dcc_probe(struct platform_device *pdev) +{ + u32 val; + int ret = 0, i; + struct device *dev = &pdev->dev; + struct dcc_drvdata *drvdata; + struct resource *res; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &pdev->dev; + platform_set_drvdata(pdev, drvdata); + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); + + drvdata->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); + if (IS_ERR(drvdata->ram_base)) + return PTR_ERR(drvdata->ram_base); + + drvdata->ram_size = resource_size(res); + ret = of_property_read_u32(pdev->dev.of_node, "qcom,dcc-offset", + &drvdata->ram_offset); + if (ret) + return -EINVAL; + + drvdata->mem_map_ver = (u64)of_device_get_match_data(&pdev->dev); + + switch (drvdata->mem_map_ver) { + case MEM_MAP_VER3: + case MEM_MAP_VER2: + drvdata->max_link_list = readl(drvdata->base + DCC_LL_NUM_INFO); + if (!drvdata->max_link_list) + return -EINVAL; + break; + case MEM_MAP_VER1: + drvdata->max_link_list = DCC_MAX_LINK_LIST; + break; + default: + dev_err(drvdata->dev, "Unsupported memory map version.\n"); + return -EINVAL; + } + + val = readl(drvdata->base + DCC_HW_INFO); + /* Either set the fixed loop offset or calculate + * it from the total number of words in dcc_sram. + * Max consecutive addresses dcc can loop is + * equivalent to the words in dcc_sram. + */ + if (val & DCC_LOOP_OFFSET_MASK) + drvdata->loop_shift = DCC_FIX_LOOP_OFFSET; + else + drvdata->loop_shift = get_bitmask_order((drvdata->ram_offset + + drvdata->ram_size) / DCC_SRAM_WORD_LENGTH - 1); + + mutex_init(&drvdata->mutex); + + drvdata->enable_bitmap = devm_kcalloc(dev, BITS_TO_LONGS(drvdata->max_link_list), + sizeof(*drvdata->enable_bitmap), GFP_KERNEL); + if (!drvdata->enable_bitmap) + return -ENOMEM; + + drvdata->cfg_head = devm_kcalloc(dev, drvdata->max_link_list, + sizeof(*drvdata->cfg_head), GFP_KERNEL); + if (!drvdata->cfg_head) + return -ENOMEM; + + for (i = 0; i < drvdata->max_link_list; i++) + INIT_LIST_HEAD(&drvdata->cfg_head[i]); + + ret = dcc_sram_dev_init(drvdata); + if (ret) { + dev_err(drvdata->dev, "DCC: sram node not registered.\n"); + return ret; + } + + dcc_create_debug_dir(drvdata); + dcc_configure_list(drvdata, pdev->dev.of_node); + + return 0; +} + +static void dcc_remove(struct platform_device *pdev) +{ + struct dcc_drvdata *drvdata = platform_get_drvdata(pdev); + + dcc_delete_debug_dir(drvdata); + dcc_sram_dev_exit(drvdata); + dcc_config_reset(drvdata); +} + +static const struct of_device_id dcc_match_table[] = { + { .compatible = "qcom,dcc-v1", .data = (void *)MEM_MAP_VER1 }, + { .compatible = "qcom,dcc-v2", .data = (void *)MEM_MAP_VER2 }, + { .compatible = "qcom,dcc-v3", .data = (void *)MEM_MAP_VER3 }, + { } +}; +MODULE_DEVICE_TABLE(of, dcc_match_table); + +static struct platform_driver dcc_driver = { + .probe = dcc_probe, + .remove = dcc_remove, + .driver = { + .name = "qcom-dcc", + .of_match_table = dcc_match_table, + }, +}; + +module_platform_driver(dcc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver"); From 3020c65a8483ba2752b27a327768bc434aeabc8a Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 8 Jan 2026 11:28:06 +0800 Subject: [PATCH 0262/1330] QCLINUX: add qcom_debug.config for debug features The config file is created to contain specific debug features such as DCC/memory dump driver. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom_debug.config | 1 + 1 file changed, 1 insertion(+) create mode 100644 arch/arm64/configs/qcom_debug.config diff --git a/arch/arm64/configs/qcom_debug.config b/arch/arm64/configs/qcom_debug.config new file mode 100644 index 0000000000000..874f80f29d314 --- /dev/null +++ b/arch/arm64/configs/qcom_debug.config @@ -0,0 +1 @@ +CONFIG_QCOM_DCC=m From 90ae84b1aeb859ed21f907301c6e4182533e3d25 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 8 Jan 2026 17:47:45 +0800 Subject: [PATCH 0263/1330] QCLINUX: qcom-dcc: add qcom-dcc dev driver Create qcom-dcc dev driver for matching the qcom-dcc driver without DT. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom_debug.config | 1 + drivers/misc/Kconfig | 8 +- drivers/misc/Makefile | 1 + drivers/misc/qcom-dcc-dev.c | 116 +++++++++++++++++++++++++++ drivers/misc/qcom-dcc.c | 79 ++---------------- drivers/misc/qcom-dcc.h | 20 +++++ 6 files changed, 153 insertions(+), 72 deletions(-) create mode 100644 drivers/misc/qcom-dcc-dev.c create mode 100644 drivers/misc/qcom-dcc.h diff --git a/arch/arm64/configs/qcom_debug.config b/arch/arm64/configs/qcom_debug.config index 874f80f29d314..eb2b32af3b40b 100644 --- a/arch/arm64/configs/qcom_debug.config +++ b/arch/arm64/configs/qcom_debug.config @@ -1 +1,2 @@ CONFIG_QCOM_DCC=m +CONFIG_QCOM_DCC_DEV=m diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 62b73f320df6d..02388dcebba1f 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -310,13 +310,19 @@ config QCOM_FASTRPC module. config QCOM_DCC - tristate "Qualcomm Technologies, Inc. Data Capture and Compare (DCC) engine driver" + tristate "Qualcomm Data Capture and Compare (DCC) engine driver" depends on ARCH_QCOM || COMPILE_TEST help This option enables the driver for the Data Capture and Compare engine. DCC driver provides interfaces to configure DCC block and read back the captured data from the DCC's internal SRAM. The module name for this is qcom-dcc. +config QCOM_DCC_DEV + tristate "Qualcomm Data Capture and Compare (DCC) engine device instance" + depends on QCOM_DCC + help + This is the device instance of the QCOM DCC driver. + config SGI_GRU tristate "SGI GRU driver" depends on X86_UV && SMP diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 338ed270b7cfc..812746940d628 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -76,3 +76,4 @@ obj-y += keba/ obj-y += amd-sbi/ obj-$(CONFIG_MISC_RP1) += rp1/ obj-$(CONFIG_QCOM_DCC) += qcom-dcc.o +obj-$(CONFIG_QCOM_DCC_DEV) += qcom-dcc-dev.o diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c new file mode 100644 index 0000000000000..e0eb2e61d652b --- /dev/null +++ b/drivers/misc/qcom-dcc-dev.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include "qcom-dcc.h" + +#define DEV_NAME "qcom-dcc" + +static struct platform_device *dcc_pdev; + +static const struct dcc_pdata talos_pdata = { + .base = 0x010a2000, + .size = 0x00001000, + .ram_base = 0x010ae000, + .ram_size = 0x00002000, + .dcc_offset = 0x6000, + .map_ver = 0x1, +}; + +static const struct dcc_pdata lemans_pdata = { + .base = 0x040ff000, + .size = 0x00001000, + .ram_base = 0x040b8800, + .ram_size = 0x00006000, + .dcc_offset = 0x38800, + .map_ver = 0x3, +}; + +static const struct dcc_pdata kodiak_pdata = { + .base = 0x0117f000, + .size = 0x00001000, + .ram_base = 0x01112000, + .ram_size = 0x00006000, + .dcc_offset = 0x12000, + .map_ver = 0x2, +}; + +static int __init dcc_dev_init(void) +{ + int ret; + u32 soc_id; + + dcc_pdev = platform_device_alloc(DEV_NAME, -1); + if (!dcc_pdev) + return -ENOMEM; + + ret = qcom_smem_get_soc_id(&soc_id); + if (ret) + goto fail; + + switch (soc_id) { + case 475: + case 497: + case 498: + case 515: + ret = platform_device_add_data(dcc_pdev, &kodiak_pdata, sizeof(kodiak_pdata)); + if (ret) + goto fail; + + break; + case 534: + case 606: + case 667: + case 674: + case 675: + case 676: + ret = platform_device_add_data(dcc_pdev, &lemans_pdata, sizeof(lemans_pdata)); + if (ret) + goto fail; + + break; + case 377: + case 380: + case 384: + case 401: + case 406: + case 680: + ret = platform_device_add_data(dcc_pdev, &talos_pdata, sizeof(talos_pdata)); + if (ret) + goto fail; + + break; + default: + pr_err("DCC: Invalid SoC ID\n"); + ret = -EINVAL; + goto fail; + } + + ret = platform_device_add(dcc_pdev); + if (ret) + goto fail; + + pr_info("DCC platform device has registered\n"); + + return 0; + +fail: + pr_err("Failed to register DCC platform device\n"); + platform_device_put(dcc_pdev); + + return ret; +} + +static void __exit dcc_dev_exit(void) +{ + platform_device_unregister(dcc_pdev); +} + +module_init(dcc_dev_init); +module_exit(dcc_dev_exit); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver, device stub"); diff --git a/drivers/misc/qcom-dcc.c b/drivers/misc/qcom-dcc.c index a511faac5d4b0..e75f98b90d8f7 100644 --- a/drivers/misc/qcom-dcc.c +++ b/drivers/misc/qcom-dcc.c @@ -135,6 +135,8 @@ #include #include +#include "qcom-dcc.h" + #define STATUS_READY_TIMEOUT 5000 /* microseconds */ /* DCC registers */ @@ -1423,57 +1425,6 @@ static ssize_t dcc_sram_read(struct file *file, char __user *data, return len; } -static void dcc_configure_list(struct dcc_drvdata *drvdata, struct device_node *np) -{ - const char *prop; - int ret, curr_list, index = 0; - char *token, *bufp; - char *delim = " "; - u32 len, processed_len = 0; - - ret = of_property_read_u32(np, "qcom,curr-link-list", - &curr_list); - if (ret) - return; - - if(!of_get_property(np, "qcom,link-list", &len)) - return; - - bufp = kzalloc(len+1, GFP_KERNEL); - if (!bufp) - return; - - while (!of_property_read_string_index(np, "qcom,link-list", index, &prop)) { - strncpy(bufp, prop, strlen(prop)); - bufp[strlen(prop)] = '\0'; - - processed_len += strlen(bufp) + 1; - - token = strsep(&bufp, delim); - - if (!strcmp("R", token)) { - ret = dcc_config_add_read(drvdata, bufp, curr_list); - } else if (!strcmp("W", token)) { - ret = dcc_config_add_write(drvdata, bufp, curr_list); - } else if (!strcmp("RW", token)) { - ret = dcc_config_add_read_write(drvdata, bufp, curr_list); - } else if (!strcmp("L", token)) { - ret = dcc_config_add_loop(drvdata, bufp, curr_list); - } else { - dev_err(drvdata->dev, "%s is not a correct input\n", token); - ret = -EINVAL; - } - - if (ret < 0) - dev_err(drvdata->dev, "Configure line %s failed\n", prop); - - index++; - } - - dcc_enable(drvdata, curr_list); - kfree(bufp); -} - static const struct file_operations dcc_sram_fops = { .owner = THIS_MODULE, .read = dcc_sram_read, @@ -1499,7 +1450,7 @@ static int dcc_probe(struct platform_device *pdev) int ret = 0, i; struct device *dev = &pdev->dev; struct dcc_drvdata *drvdata; - struct resource *res; + const struct dcc_pdata *pdata = dev_get_platdata(dev); drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) @@ -1508,21 +1459,17 @@ static int dcc_probe(struct platform_device *pdev) drvdata->dev = &pdev->dev; platform_set_drvdata(pdev, drvdata); - drvdata->base = devm_platform_ioremap_resource(pdev, 0); + drvdata->base = devm_ioremap(dev, pdata->base, pdata->size); if (IS_ERR(drvdata->base)) return PTR_ERR(drvdata->base); - drvdata->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); + drvdata->ram_base = devm_ioremap(dev, pdata->ram_base, pdata->ram_size); if (IS_ERR(drvdata->ram_base)) return PTR_ERR(drvdata->ram_base); - drvdata->ram_size = resource_size(res); - ret = of_property_read_u32(pdev->dev.of_node, "qcom,dcc-offset", - &drvdata->ram_offset); - if (ret) - return -EINVAL; - - drvdata->mem_map_ver = (u64)of_device_get_match_data(&pdev->dev); + drvdata->ram_size = pdata->ram_size; + drvdata->ram_offset = pdata->dcc_offset; + drvdata->mem_map_ver = pdata->map_ver; switch (drvdata->mem_map_ver) { case MEM_MAP_VER3: @@ -1573,7 +1520,6 @@ static int dcc_probe(struct platform_device *pdev) } dcc_create_debug_dir(drvdata); - dcc_configure_list(drvdata, pdev->dev.of_node); return 0; } @@ -1587,20 +1533,11 @@ static void dcc_remove(struct platform_device *pdev) dcc_config_reset(drvdata); } -static const struct of_device_id dcc_match_table[] = { - { .compatible = "qcom,dcc-v1", .data = (void *)MEM_MAP_VER1 }, - { .compatible = "qcom,dcc-v2", .data = (void *)MEM_MAP_VER2 }, - { .compatible = "qcom,dcc-v3", .data = (void *)MEM_MAP_VER3 }, - { } -}; -MODULE_DEVICE_TABLE(of, dcc_match_table); - static struct platform_driver dcc_driver = { .probe = dcc_probe, .remove = dcc_remove, .driver = { .name = "qcom-dcc", - .of_match_table = dcc_match_table, }, }; diff --git a/drivers/misc/qcom-dcc.h b/drivers/misc/qcom-dcc.h new file mode 100644 index 0000000000000..513c95dc742b5 --- /dev/null +++ b/drivers/misc/qcom-dcc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _QCOM_DCC_H +#define _QCOM_DCC_H + +#include + +struct dcc_pdata { + phys_addr_t base; + resource_size_t size; + phys_addr_t ram_base; + resource_size_t ram_size; + u32 dcc_offset; + u8 map_ver; +}; + +#endif From 4e30a444c81130b60fe130d27de32f59ec168bed Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 9 Jan 2026 14:42:21 +0800 Subject: [PATCH 0264/1330] QCLINUX: memory-dump: add QCOM memory dump driver The memory dump driver allows various client subsystems to register respective dump regions. At the time of deadlocks or cpu hangs these dump regions are captured to give a snapshot of the system at the time of the crash. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom_debug.config | 1 + drivers/firmware/qcom/Kconfig | 9 + drivers/firmware/qcom/Makefile | 1 + drivers/firmware/qcom/memory_dump_v2.c | 1143 +++++++++++++++++++++ include/linux/firmware/qcom/memory_dump.h | 136 +++ 5 files changed, 1290 insertions(+) create mode 100644 drivers/firmware/qcom/memory_dump_v2.c create mode 100644 include/linux/firmware/qcom/memory_dump.h diff --git a/arch/arm64/configs/qcom_debug.config b/arch/arm64/configs/qcom_debug.config index eb2b32af3b40b..2e85e8df0469b 100644 --- a/arch/arm64/configs/qcom_debug.config +++ b/arch/arm64/configs/qcom_debug.config @@ -1,2 +1,3 @@ CONFIG_QCOM_DCC=m CONFIG_QCOM_DCC_DEV=m +CONFIG_QCOM_MEMORY_DUMP_V2=m diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index b477d54b495a6..531c6d2598ce0 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -74,4 +74,13 @@ config QCOM_QSEECOM_UEFISECAPP Select Y here to provide access to EFI variables on the aforementioned platforms. +config QCOM_MEMORY_DUMP_V2 + tristate "QCOM Memory Dump V2 Support" + depends on QCOM_TZMEM + help + This enables memory dump feature. It allows various client + subsystems to register respective dump regions. At the time + of deadlocks or cpu hangs these dump regions are captured to + give a snapshot of the system at the time of the crash. + endmenu diff --git a/drivers/firmware/qcom/Makefile b/drivers/firmware/qcom/Makefile index 0be40a1abc13c..c5e17ba255937 100644 --- a/drivers/firmware/qcom/Makefile +++ b/drivers/firmware/qcom/Makefile @@ -8,3 +8,4 @@ qcom-scm-objs += qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o obj-$(CONFIG_QCOM_TZMEM) += qcom_tzmem.o obj-$(CONFIG_QCOM_QSEECOM) += qcom_qseecom.o obj-$(CONFIG_QCOM_QSEECOM_UEFISECAPP) += qcom_qseecom_uefisecapp.o +obj-$(CONFIG_QCOM_MEMORY_DUMP_V2) += memory_dump_v2.o diff --git a/drivers/firmware/qcom/memory_dump_v2.c b/drivers/firmware/qcom/memory_dump_v2.c new file mode 100644 index 0000000000000..baf4c980f39fb --- /dev/null +++ b/drivers/firmware/qcom/memory_dump_v2.c @@ -0,0 +1,1143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2017, 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MSM_DUMP_TABLE_VERSION MSM_DUMP_MAKE_VERSION(2, 0) + +#define SCM_CMD_DEBUG_LAR_UNLOCK 0x4 + +#define CPUSS_REGDUMP 0xEF +#define SPR_DUMP_CPU0 0x1F0 +#define SPR_DUMP_CPU1 0x1F1 +#define SPR_DUMP_CPU2 0x1F2 +#define SPR_DUMP_CPU3 0x1F3 +#define SPR_DUMP_CPU4 0x1F4 +#define SPR_DUMP_CPU5 0x1F5 +#define SPR_DUMP_CPU6 0x1F6 +#define SPR_DUMP_CPU7 0x1F7 +#define SPR_DATA_HEADER_SIZE 5 +#define SPR_DATA_HEADER_TAIL_SIZE 1 +#define SPR_INPUT_DATA_TAIL_SIZE 1 +#define SPR_INPUT_DATA_SIZE 1 +#define SPR_OUTPUT_DATA_SIZE 2 +#define MAX_CORE_NUM 8 + +#define INPUT_DATA_BY_HLOS 0x00C0FFEE +#define FORMAT_VERSION_1 0x1 +#define FORMAT_VERSION_2 0x2 +#define CORE_REG_NUM_DEFAULT 0x1 + +#define MAGIC_INDEX 0 +#define FORMAT_VERSION_INDEX 1 +#define SYS_REG_INPUT_INDEX 2 +#define OUTPUT_DUMP_INDEX 3 +#define PERCORE_INDEX 4 +#define SYSTEM_REGS_INPUT_INDEX 5 + +#define CMD_REPEAT_READ (0x2 << 24) +#define CMD_DELAY (0x1 << 24) +#define CMD_READ 0x0 +#define CMD_READ_WORD 0x1 +#define CMD_WRITE 0x2 +#define CMD_EXTRA 0x3 + +#define CMD_MASK 0x3 +#define OFFSET_MASK GENMASK(31, 2) +#define EXTRA_CMD_MASK GENMASK(31, 24) +#define EXTRA_VALUE_MASK GENMASK(23, 0) +#define MAX_EXTRA_VALUE 0xffffff + +struct sprs_dump_data { + void *dump_vaddr; + u32 size; + u32 sprs_data_index; + u32 used_memory; +}; + +struct cpuss_regdump_data { + void *dump_vaddr; + u32 size; + u32 core_reg_num; + u32 core_reg_used_num; + u32 core_reg_end_index; + u32 sys_reg_size; + u32 used_memory; +}; + +struct cpuss_dump_data { + struct mutex mutex; + struct cpuss_regdump_data *cpussregdata; + struct sprs_dump_data *sprdata[MAX_CORE_NUM]; +}; + +struct reg_dump_data { + uint32_t magic; + uint32_t version; + uint32_t system_regs_input_index; + uint32_t regdump_output_byte_offset; +}; + +struct msm_dump_table { + uint32_t version; + uint32_t num_entries; + struct msm_dump_entry entries[MAX_NUM_ENTRIES]; +}; + +struct msm_memory_dump { + uint64_t table_phys; + struct msm_dump_table *table; +}; + +/** + * Set bit 0 if percore reg dump initialized. + * Set bit 1 if spr dump initialized. + */ +#define PERCORE_REG_INITIALIZED BIT(0) +#define SPRS_INITIALIZED BIT(1) + +static struct msm_memory_dump memdump; + +/** + * reset_sprs_dump_table - reset the sprs dump table + * + * This function calculates system_regs_input_index and + * regdump_output_byte_offset to store into the dump memory. + * It also updates members of cpudata by the parameter core_reg_num. + * + * Returns 0 on success, or -ENOMEM on error of no enough memory. + */ +static int reset_sprs_dump_table(struct device *dev) +{ + int ret = 0; + struct reg_dump_data *p; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + int i = 0; + + if (!cpudata) + return -EFAULT; + + mutex_lock(&cpudata->mutex); + + for (i = 0; i < MAX_CORE_NUM; i++) { + if (cpudata->sprdata[i]) { + cpudata->sprdata[i]->sprs_data_index = 0; + cpudata->sprdata[i]->used_memory = (SPR_DATA_HEADER_SIZE + + SPR_INPUT_DATA_TAIL_SIZE) * sizeof(uint32_t); + memset(cpudata->sprdata[i]->dump_vaddr, 0xDE, + cpudata->sprdata[i]->size); + p = (struct reg_dump_data *)cpudata->sprdata[i]->dump_vaddr; + p->magic = INPUT_DATA_BY_HLOS; + p->version = FORMAT_VERSION_1; + p->system_regs_input_index = SYSTEM_REGS_INPUT_INDEX; + p->regdump_output_byte_offset = (SPR_DATA_HEADER_SIZE + + SPR_INPUT_DATA_TAIL_SIZE) * sizeof(uint32_t); + memset((uint32_t *)cpudata->sprdata[i]->dump_vaddr + + PERCORE_INDEX, 0x0, (SPR_DATA_HEADER_TAIL_SIZE + + SPR_INPUT_DATA_TAIL_SIZE) * sizeof(uint32_t)); + } + } + + mutex_unlock(&cpudata->mutex); + return ret; +} + + +/** + * update_reg_dump_table - update the register dump table + * @core_reg_num: the number of per-core registers + * + * This function calculates system_regs_input_index and + * regdump_output_byte_offset to store into the dump memory. + * It also updates members of cpudata by the parameter core_reg_num. + * + * Returns 0 on success, or -ENOMEM on error of no enough memory. + */ +static int update_reg_dump_table(struct device *dev, u32 core_reg_num) +{ + int ret = 0; + u32 system_regs_input_index = SYSTEM_REGS_INPUT_INDEX + + core_reg_num * 2; + u32 regdump_output_byte_offset = (system_regs_input_index + 1) + * sizeof(uint32_t); + struct reg_dump_data *p; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + mutex_lock(&cpudata->mutex); + + if (regdump_output_byte_offset >= cpudata->cpussregdata->size || + regdump_output_byte_offset / sizeof(uint32_t) + < system_regs_input_index + 1) { + ret = -ENOMEM; + goto err; + } + + cpudata->cpussregdata->core_reg_num = core_reg_num; + cpudata->cpussregdata->core_reg_used_num = 0; + cpudata->cpussregdata->core_reg_end_index = PERCORE_INDEX; + cpudata->cpussregdata->sys_reg_size = 0; + cpudata->cpussregdata->used_memory = regdump_output_byte_offset; + + memset(cpudata->cpussregdata->dump_vaddr, 0xDE, cpudata->cpussregdata->size); + p = (struct reg_dump_data *)cpudata->cpussregdata->dump_vaddr; + p->magic = INPUT_DATA_BY_HLOS; + p->version = FORMAT_VERSION_2; + p->system_regs_input_index = system_regs_input_index; + p->regdump_output_byte_offset = regdump_output_byte_offset; + memset((uint32_t *)cpudata->cpussregdata->dump_vaddr + PERCORE_INDEX, 0x0, + (system_regs_input_index - PERCORE_INDEX + 1) + * sizeof(uint32_t)); + +err: + mutex_unlock(&cpudata->mutex); + return ret; +} + +static ssize_t core_reg_num_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + if (!cpudata) + return -EFAULT; + + mutex_lock(&cpudata->mutex); + + ret = scnprintf(buf, PAGE_SIZE, "%u\n", cpudata->cpussregdata->core_reg_num); + + mutex_unlock(&cpudata->mutex); + return ret; +} + +static ssize_t core_reg_num_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + unsigned int val; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + if (kstrtouint(buf, 16, &val)) + return -EINVAL; + + mutex_lock(&cpudata->mutex); + + if (cpudata->cpussregdata->core_reg_used_num || cpudata->cpussregdata->sys_reg_size) { + dev_err(dev, "Couldn't set core_reg_num, register available in list\n"); + ret = -EPERM; + goto err; + } + if (val == cpudata->cpussregdata->core_reg_num) { + mutex_unlock(&cpudata->mutex); + return size; + } + + mutex_unlock(&cpudata->mutex); + + ret = update_reg_dump_table(dev, val); + if (ret) { + dev_err(dev, "Couldn't set core_reg_num, no enough memory\n"); + return ret; + } + + return size; + +err: + mutex_unlock(&cpudata->mutex); + return ret; +} +static DEVICE_ATTR_RW(core_reg_num); + +/** + * This function shows configs of per-core and system registers. + */ +static ssize_t register_config_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char local_buf[64]; + int len = 0, count = 0; + int index, system_index_start, index_end; + uint32_t register_offset, val; + uint32_t *p, cmd; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + buf[0] = '\0'; + + if (!cpudata) + return -EFAULT; + + mutex_lock(&cpudata->mutex); + + p = (uint32_t *)cpudata->cpussregdata->dump_vaddr; + + /* print per-core & system registers */ + len = scnprintf(local_buf, 64, "per-core registers:\n"); + strlcat(buf, local_buf, PAGE_SIZE); + count += len; + + system_index_start = *(p + SYS_REG_INPUT_INDEX); + index_end = system_index_start + + cpudata->cpussregdata->sys_reg_size / sizeof(uint32_t) + 1; + for (index = PERCORE_INDEX; index < index_end;) { + if (index == system_index_start) { + len = scnprintf(local_buf, 64, "system registers:\n"); + if ((count + len) > PAGE_SIZE) { + dev_err(dev, "Couldn't write complete config\n"); + break; + } + + strlcat(buf, local_buf, PAGE_SIZE); + count += len; + } + + register_offset = *(p + index); + if (register_offset == 0) { + index++; + continue; + } + + cmd = register_offset & CMD_MASK; + register_offset &= OFFSET_MASK; + + switch (cmd) { + case CMD_READ: + val = *(p + index + 1); + len = scnprintf(local_buf, 64, + "0x%x, 0x%x, r\n", + register_offset, val); + index += 2; + break; + case CMD_READ_WORD: + len = scnprintf(local_buf, 64, + "0x%x, 0x%x, r\n", + register_offset, 0x4); + index++; + break; + case CMD_WRITE: + val = *(p + index + 1); + len = scnprintf(local_buf, 64, + "0x%x, 0x%x, w\n", + register_offset, val); + index += 2; + break; + case CMD_EXTRA: + val = *(p + index + 1); + cmd = val & EXTRA_CMD_MASK; + val &= EXTRA_VALUE_MASK; + if (cmd == CMD_DELAY) + len = scnprintf(local_buf, 64, + "0x%x, 0x%x, d\n", + register_offset, val); + else + len = scnprintf(local_buf, 64, + "0x%x, 0x%x, R\n", + register_offset, val); + index += 2; + break; + } + + if ((count + len) > PAGE_SIZE) { + dev_err(dev, "Couldn't write complete config\n"); + break; + } + + strlcat(buf, local_buf, PAGE_SIZE); + count += len; + } + + mutex_unlock(&cpudata->mutex); + return count; +} + +static int config_cpuss_register(struct device *dev, + uint32_t *p, uint32_t index, char cmd, + uint32_t register_offset, uint32_t val) +{ + int ret = 0; + + switch (cmd) { + case 'r': + if (val > 4) { + *(p + index) = register_offset; + *(p + index + 1) = val; + } else { + *(p + index) = register_offset | CMD_READ_WORD; + } + break; + case 'R': + if (val > MAX_EXTRA_VALUE) { + dev_err(dev, "repeat read time exceeded the limit\n"); + ret = -EINVAL; + return ret; + } + *(p + index) = register_offset | CMD_EXTRA; + *(p + index + 1) = val | CMD_REPEAT_READ; + break; + case 'd': + if (val > MAX_EXTRA_VALUE) { + dev_err(dev, "sleep time exceeded the limit\n"); + ret = -EINVAL; + return ret; + } + *(p + index) = CMD_EXTRA; + *(p + index + 1) = val | CMD_DELAY; + break; + case 'w': + *(p + index) = register_offset | CMD_WRITE; + *(p + index + 1) = val; + break; + default: + dev_err(dev, "Don't support this command\n"); + ret = -EINVAL; + } + return ret; +} +/** + * This function sets configs of per-core or system registers. + */ +static ssize_t register_config_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + uint32_t register_offset, val, reserve_size = 4, per_core = 0; + int nval; + char cmd; + uint32_t num_cores; + u32 extra_memory; + u32 used_memory; + u32 system_reg_end_index; + uint32_t *p; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + nval = sscanf(buf, "%x %x %c %u", ®ister_offset, + &val, &cmd, &per_core); + if (nval < 2) + return -EINVAL; + if (nval == 2) + cmd = 'r'; + if (per_core > 1) + return -EINVAL; + if (register_offset & 0x3) { + dev_err(dev, "Invalid address, must be 4 byte aligned\n"); + return -EINVAL; + } + + if (cmd == 'r' || cmd == 'R') { + if (val == 0) { + dev_err(dev, "Invalid length of 0\n"); + return -EINVAL; + } + if (cmd == 'r' && val & 0x3) { + dev_err(dev, "Invalid length, must be 4 byte aligned\n"); + return -EINVAL; + } + if (cmd == 'R') + reserve_size = val * 4; + else + reserve_size = val; + } + + mutex_lock(&cpudata->mutex); + + p = (uint32_t *)cpudata->cpussregdata->dump_vaddr; + if (per_core) { /* per-core register */ + if (cpudata->cpussregdata->core_reg_used_num == + cpudata->cpussregdata->core_reg_num) { + dev_err(dev, "Couldn't add per-core config, out of range\n"); + ret = -EINVAL; + goto err; + } + + num_cores = num_possible_cpus(); + extra_memory = reserve_size * num_cores; + used_memory = cpudata->cpussregdata->used_memory + extra_memory; + if (extra_memory / num_cores < reserve_size || + used_memory > cpudata->cpussregdata->size || + used_memory < cpudata->cpussregdata->used_memory) { + dev_err(dev, "Couldn't add per-core reg config, no enough memory\n"); + ret = -ENOMEM; + goto err; + } + + ret = config_cpuss_register(dev, p, cpudata->cpussregdata->core_reg_end_index, + cmd, register_offset, val); + if (ret) + goto err; + + if (cmd == 'r' && val == 4) + cpudata->cpussregdata->core_reg_end_index++; + else + cpudata->cpussregdata->core_reg_end_index += 2; + + cpudata->cpussregdata->core_reg_used_num++; + cpudata->cpussregdata->used_memory = used_memory; + } else { /* system register */ + system_reg_end_index = *(p + SYS_REG_INPUT_INDEX) + + cpudata->cpussregdata->sys_reg_size / sizeof(uint32_t); + + if (cmd == 'r' && reserve_size == 4) + extra_memory = sizeof(uint32_t) + reserve_size; + else + extra_memory = sizeof(uint32_t) * 2 + reserve_size; + + used_memory = cpudata->cpussregdata->used_memory + extra_memory; + if (extra_memory < reserve_size || + used_memory > cpudata->cpussregdata->size || + used_memory < cpudata->cpussregdata->used_memory) { + dev_err(dev, "Couldn't add system reg config, no enough memory\n"); + ret = -ENOMEM; + goto err; + } + + ret = config_cpuss_register(dev, p, system_reg_end_index, + cmd, register_offset, val); + if (ret) + goto err; + + if (cmd == 'r' && val == 4) { + system_reg_end_index++; + cpudata->cpussregdata->sys_reg_size += sizeof(uint32_t); + } else { + system_reg_end_index += 2; + cpudata->cpussregdata->sys_reg_size += sizeof(uint32_t) * 2; + } + + cpudata->cpussregdata->used_memory = used_memory; + *(p + system_reg_end_index) = 0x0; + *(p + OUTPUT_DUMP_INDEX) = (system_reg_end_index + 1) + * sizeof(uint32_t); + } + + ret = size; + +err: + mutex_unlock(&cpudata->mutex); + return ret; +} +static DEVICE_ATTR_RW(register_config); + +static ssize_t format_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + struct reg_dump_data *p; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + if (!cpudata) + return -EFAULT; + + mutex_lock(&cpudata->mutex); + p = (struct reg_dump_data *)cpudata->cpussregdata->dump_vaddr; + ret = scnprintf(buf, PAGE_SIZE, "%u\n", p->version); + + mutex_unlock(&cpudata->mutex); + return ret; +} +static DEVICE_ATTR_RO(format_version); +/** + * This function resets the register dump table. + */ +static ssize_t register_reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned int val; + + if (kstrtouint(buf, 16, &val)) + return -EINVAL; + if (val != 1) + return -EINVAL; + + update_reg_dump_table(dev, CORE_REG_NUM_DEFAULT); + + return size; +} +static DEVICE_ATTR_WO(register_reset); + +/** + * This function shows configs of per-core spr dump. + */ +static ssize_t spr_config_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char local_buf[64]; + int len = 0, count = 0; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + int i = 0, index = 0; + uint32_t *p; + + buf[0] = '\0'; + + if (!cpudata) + return -EFAULT; + + mutex_lock(&cpudata->mutex); + + len = scnprintf(local_buf, 64, "spr data list below:\n"); + strlcat(buf, local_buf, PAGE_SIZE); + count += len; + + for (i = 0; i < MAX_CORE_NUM; i++) { + if (count > PAGE_SIZE) { + dev_err(dev, "Couldn't write complete config\n"); + break; + } + if (!cpudata->sprdata[i]) { + dev_err(dev, "SPR data pinter for CPU%d is empty\n", i); + continue; + } + p = (uint32_t *)cpudata->sprdata[i]->dump_vaddr; + len = scnprintf(local_buf, 64, "spr data for CPU[%d] below:\n", i); + strlcat(buf, local_buf, PAGE_SIZE); + count += len; + index = 0; + while (index < cpudata->sprdata[i]->sprs_data_index) { + if (count > PAGE_SIZE) { + dev_err(dev, "Couldn't write complete config\n"); + break; + } + len = scnprintf(local_buf, 64, "%d\n", *(p + SPR_DATA_HEADER_SIZE + index)); + strlcat(buf, local_buf, PAGE_SIZE); + count += len; + index++; + } + } + + mutex_unlock(&cpudata->mutex); + return count; +} + +/** + * This function sets configs for sprs dump. + */ +static ssize_t spr_config_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret = 0; + uint32_t spr_data, cpu_num; + uint32_t index; + int nval; + uint32_t *p; + u32 reserved = 0; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + nval = sscanf(buf, "%d %d", &spr_data, &cpu_num); + if (nval != 2) + return -EINVAL; + if (!cpudata) + return -EFAULT; + + if (cpu_num >= MAX_CORE_NUM) { + dev_err(dev, "Input the wrong CPU number\n"); + return -EINVAL; + } + reserved = (SPR_INPUT_DATA_SIZE + SPR_OUTPUT_DATA_SIZE) * sizeof(uint32_t); + + mutex_lock(&cpudata->mutex); + if (cpudata->sprdata[cpu_num]) { + p = (uint32_t *)cpudata->sprdata[cpu_num]->dump_vaddr; + index = cpudata->sprdata[cpu_num]->sprs_data_index; + + if (cpudata->sprdata[cpu_num]->size > + cpudata->sprdata[cpu_num]->used_memory + reserved) { + p = (uint32_t *)cpudata->sprdata[cpu_num]->dump_vaddr; + *(p + OUTPUT_DUMP_INDEX) = (SPR_DATA_HEADER_SIZE + + index + SPR_INPUT_DATA_TAIL_SIZE + 1) * sizeof(uint32_t); + *(p + SPR_DATA_HEADER_SIZE + index) = spr_data; + *(p + SPR_DATA_HEADER_SIZE + index + 1) = 0; + cpudata->sprdata[cpu_num]->sprs_data_index++; + cpudata->sprdata[cpu_num]->used_memory = + cpudata->sprdata[cpu_num]->used_memory + reserved; + } else { + dev_err(dev, "Couldn't add SPR config, no enough memory\n"); + ret = -ENOMEM; + goto err; + } + } + ret = size; + +err: + mutex_unlock(&cpudata->mutex); + return ret; +} +static DEVICE_ATTR_RW(spr_config); + +/** + * This function resets the sprs dump table. + */ +static ssize_t sprs_register_reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned int val; + + if (kstrtouint(buf, 16, &val)) + return -EINVAL; + if (val != 1) + return -EINVAL; + + reset_sprs_dump_table(dev); + + return size; +} +static DEVICE_ATTR_WO(sprs_register_reset); + +static ssize_t sprs_format_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char local_buf[64]; + int len = 0, count = 0, i = 0; + struct reg_dump_data *p; + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + buf[0] = '\0'; + + if (!cpudata) + return -EFAULT; + + mutex_lock(&cpudata->mutex); + + for (i = 0; i < MAX_CORE_NUM; i++) { + if (cpudata->sprdata[i]) { + p = (struct reg_dump_data *)cpudata->sprdata[i]->dump_vaddr; + len = scnprintf(local_buf, 64, + "SPR data format version for cpu%d is %d\n", i, p->version); + strlcat(buf, local_buf, PAGE_SIZE); + count += len; + } + } + + mutex_unlock(&cpudata->mutex); + return count; +} +static DEVICE_ATTR_RO(sprs_format_version); + + +static const struct device_attribute *register_dump_attrs[] = { + &dev_attr_core_reg_num, + &dev_attr_register_config, + &dev_attr_register_reset, + &dev_attr_format_version, + NULL, +}; + +static const struct device_attribute *spr_dump_attrs[] = { + &dev_attr_spr_config, + &dev_attr_sprs_register_reset, + &dev_attr_sprs_format_version, + NULL, +}; + +static int memory_dump_create_files(struct device *dev, + const struct device_attribute **attrs) +{ + int ret = 0; + int i, j; + + for (i = 0; attrs[i] != NULL; i++) { + ret = device_create_file(dev, attrs[i]); + if (ret) { + dev_err(dev, "Couldn't create sysfs attribute: %s\n", + attrs[i]->attr.name); + for (j = 0; j < i; j++) + device_remove_file(dev, attrs[j]); + break; + } + } + return ret; +} + +static void cpuss_create_nodes(struct platform_device *pdev, + int initialized) +{ + if (initialized & PERCORE_REG_INITIALIZED) { + if (memory_dump_create_files(&pdev->dev, register_dump_attrs)) + dev_err(&pdev->dev, "Fail to create files for cpuss register dump\n"); + } + if (initialized & SPRS_INITIALIZED) { + if (memory_dump_create_files(&pdev->dev, spr_dump_attrs)) + dev_err(&pdev->dev, "Fail to create files for spr dump\n"); + } +} + +uint32_t msm_dump_table_version(void) +{ + return MSM_DUMP_TABLE_VERSION; +} +EXPORT_SYMBOL_GPL(msm_dump_table_version); + +static int msm_dump_table_register(struct msm_dump_entry *entry) +{ + struct msm_dump_entry *e; + struct msm_dump_table *table = memdump.table; + + if (!table || table->num_entries >= MAX_NUM_ENTRIES) + return -EINVAL; + + e = &table->entries[table->num_entries]; + e->id = entry->id; + e->type = MSM_DUMP_TYPE_TABLE; + e->addr = entry->addr; + table->num_entries++; + + return 0; +} + +static struct msm_dump_table *msm_dump_get_table(enum msm_dump_table_ids id) +{ + struct msm_dump_table *table = memdump.table; + int i; + unsigned long offset; + + if (!table) { + pr_err("mem dump base table does not exist\n"); + return ERR_PTR(-EINVAL); + } + + for (i = 0; i < MAX_NUM_ENTRIES; i++) { + if (table->entries[i].id == id) + break; + } + if (i == MAX_NUM_ENTRIES || !table->entries[i].addr) { + pr_err("mem dump base table entry %d invalid\n", id); + return ERR_PTR(-EINVAL); + } + + offset = table->entries[i].addr - memdump.table_phys; + /* Get the apps table pointer */ + table = (void *)memdump.table + offset; + + return table; +} + +static int register_dump_table_entry(enum msm_dump_table_ids id, + struct msm_dump_entry *entry) +{ + struct msm_dump_entry *e; + struct msm_dump_table *table; + + table = msm_dump_get_table(id); + if (IS_ERR(table)) + return PTR_ERR(table); + + if (!table || table->num_entries >= MAX_NUM_ENTRIES) + return -EINVAL; + + e = &table->entries[table->num_entries]; + e->id = entry->id; + e->type = MSM_DUMP_TYPE_DATA; + e->addr = entry->addr; + table->num_entries++; + + return 0; +} + +/** + * msm_dump_data_register_nominidump - register to dump data framework + * @id: ID of the dump table. + * @entry: dump entry to be registered + * This api will register the entry passed to dump table only + */ +int msm_dump_data_register_nominidump(enum msm_dump_table_ids id, + struct msm_dump_entry *entry) +{ + return register_dump_table_entry(id, entry); +} +EXPORT_SYMBOL_GPL(msm_dump_data_register_nominidump); + +#define MSM_DUMP_TOTAL_SIZE_OFFSET 0x724 +static int init_memdump_imem_area(size_t size) +{ + struct device_node *np; + void __iomem *imem_base; + + np = of_find_compatible_node(NULL, NULL, + "qcom,msm-imem-mem-dump-table"); + if (!np) { + pr_err("mem dump base table DT node does not exist\n"); + return -ENODEV; + } + + imem_base = of_iomap(np, 0); + if (!imem_base) { + pr_err("mem dump base table imem offset mapping failed\n"); + return -ENOMEM; + } + + memcpy_toio(imem_base, &memdump.table_phys, + sizeof(memdump.table_phys)); + memcpy_toio(imem_base + MSM_DUMP_TOTAL_SIZE_OFFSET, + &size, sizeof(size_t)); + + /* Ensure write to imem_base is complete before unmapping */ + mb(); + pr_info("MSM Memory Dump base table set up in IMEM\n"); + + iounmap(imem_base); + return 0; +} + +static int init_memory_dump(void *dump_vaddr, phys_addr_t phys_addr) +{ + struct msm_dump_table *table; + struct msm_dump_entry entry; + int ret; + + memdump.table = dump_vaddr; + memdump.table->version = MSM_DUMP_TABLE_VERSION; + memdump.table_phys = phys_addr; + dump_vaddr += sizeof(*table); + phys_addr += sizeof(*table); + table = dump_vaddr; + table->version = MSM_DUMP_TABLE_VERSION; + entry.id = MSM_DUMP_TABLE_APPS; + entry.addr = phys_addr; + ret = msm_dump_table_register(&entry); + if (ret) { + pr_err("mem dump apps data table register failed\n"); + return ret; + } + pr_info("MSM Memory Dump apps data table set up\n"); + + return 0; +} + +static int mem_dump_reserve_mem(struct device *dev) +{ + struct device_node *mem_node; + int ret; + + mem_node = of_parse_phandle(dev->of_node, "memory-region", 0); + if (mem_node) { + ret = of_reserved_mem_device_init_by_idx(dev, + dev->of_node, 0); + of_node_put(dev->of_node); + if (ret) { + dev_err(dev, + "Failed to initialize reserved mem, ret %d\n", + ret); + return ret; + } + } + return 0; +} + +static int cpuss_regdump_init(struct device *dev, + void *dump_vaddr, u32 size) +{ + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + + cpudata->cpussregdata = devm_kzalloc(dev, + sizeof(struct cpuss_regdump_data), GFP_KERNEL); + + if (cpudata->cpussregdata) { + cpudata->cpussregdata->dump_vaddr = dump_vaddr; + cpudata->cpussregdata->size = size; + return 0; + } + return -ENOMEM; +} + +static int sprs_dump_init(struct device *dev, + void *dump_vaddr, u32 size, u32 id) +{ + struct cpuss_dump_data *cpudata = dev_get_drvdata(dev); + int core_num = 0; + + core_num = id - SPR_DUMP_CPU0; + + cpudata->sprdata[core_num] = devm_kzalloc(dev, + sizeof(struct sprs_dump_data), GFP_KERNEL); + if (cpudata->sprdata[core_num]) { + cpudata->sprdata[core_num]->dump_vaddr = dump_vaddr; + cpudata->sprdata[core_num]->size = size; + return 0; + } + return -ENOMEM; +} + +static int cpuss_dump_init(struct platform_device *pdev, + void *dump_vaddr, u32 size, u32 id) +{ + struct cpuss_dump_data *cpudata = dev_get_drvdata(&pdev->dev); + static int initialized; + + if (!cpudata) { + cpudata = devm_kzalloc(&pdev->dev, + sizeof(struct cpuss_dump_data), GFP_KERNEL); + if (cpudata) { + mutex_init(&cpudata->mutex); + platform_set_drvdata(pdev, cpudata); + } else + return initialized; + } + + if (id == CPUSS_REGDUMP) { + if (!cpuss_regdump_init(&pdev->dev, dump_vaddr, size)) + initialized |= PERCORE_REG_INITIALIZED; + } else { + if (!sprs_dump_init(&pdev->dev, dump_vaddr, size, id)) + initialized |= SPRS_INITIALIZED; + } + + return initialized; +} + +#define MSM_DUMP_DATA_SIZE sizeof(struct msm_dump_data) +static int mem_dump_alloc(struct platform_device *pdev) +{ + struct device_node *child_node; + const struct device_node *node = pdev->dev.of_node; + struct msm_dump_data *dump_data; + struct msm_dump_entry dump_entry; + size_t total_size; + u32 size, id; + int ret, no_of_nodes; + dma_addr_t dma_handle; + phys_addr_t phys_addr; + struct sg_table mem_dump_sgt; + void *dump_vaddr; + u64 shm_bridge_handle; + int initialized = 0; + + if (mem_dump_reserve_mem(&pdev->dev) != 0) + return -ENOMEM; + total_size = size = ret = no_of_nodes = 0; + /* For dump table registration with IMEM */ + total_size = sizeof(struct msm_dump_table) * 2; + for_each_available_child_of_node(node, child_node) { + ret = of_property_read_u32(child_node, "qcom,dump-size", &size); + if (ret) { + dev_err(&pdev->dev, "Unable to find size for %s\n", + child_node->name); + continue; + } + + total_size += size; + no_of_nodes++; + } + + total_size += (MSM_DUMP_DATA_SIZE * no_of_nodes); + total_size = ALIGN(total_size, SZ_4K); + dump_vaddr = dmam_alloc_coherent(&pdev->dev, total_size, + &dma_handle, GFP_KERNEL); + if (!dump_vaddr) + return -ENOMEM; + + dma_get_sgtable(&pdev->dev, &mem_dump_sgt, dump_vaddr, + dma_handle, total_size); + phys_addr = page_to_phys(sg_page(mem_dump_sgt.sgl)); + sg_free_table(&mem_dump_sgt); + + memset(dump_vaddr, 0x0, total_size); + ret = qcom_tzmem_shm_bridge_create(phys_addr, total_size, &shm_bridge_handle); + if (ret) { + dev_err(&pdev->dev, "Failed to create shm bridge.ret=%d\n", ret); + return ret; + } + + ret = init_memory_dump(dump_vaddr, phys_addr); + if (ret) { + dev_err(&pdev->dev, "Memory Dump table set up is failed\n"); + qcom_tzmem_shm_bridge_delete(shm_bridge_handle); + return ret; + } + + ret = init_memdump_imem_area(total_size); + if (ret) { + qcom_tzmem_shm_bridge_delete(shm_bridge_handle); + return ret; + } + + dump_vaddr += (sizeof(struct msm_dump_table) * 2); + phys_addr += (sizeof(struct msm_dump_table) * 2); + for_each_available_child_of_node(node, child_node) { + ret = of_property_read_u32(child_node, "qcom,dump-size", &size); + if (ret) + continue; + + ret = of_property_read_u32(child_node, "qcom,dump-id", &id); + if (ret) { + dev_err(&pdev->dev, "Unable to find id for %s\n", + child_node->name); + continue; + } + + dump_data = dump_vaddr; + dump_data->addr = phys_addr + MSM_DUMP_DATA_SIZE; + dump_data->len = size; + dump_entry.id = id; + strscpy(dump_data->name, child_node->name, + sizeof(dump_data->name)); + dump_entry.addr = phys_addr; + ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS, + &dump_entry); + if (ret) + dev_err(&pdev->dev, "Data dump setup failed, id = %d\n", + id); + + if ((id == CPUSS_REGDUMP) || + ((id >= SPR_DUMP_CPU0) && (id <= SPR_DUMP_CPU7))) + initialized = cpuss_dump_init(pdev, + (dump_vaddr + MSM_DUMP_DATA_SIZE), size, id); + + dump_vaddr += (size + MSM_DUMP_DATA_SIZE); + phys_addr += (size + MSM_DUMP_DATA_SIZE); + } + + cpuss_create_nodes(pdev, initialized); + + if (initialized & SPRS_INITIALIZED) + reset_sprs_dump_table(&pdev->dev); + + return ret; +} + +static int mem_dump_probe(struct platform_device *pdev) +{ + int ret; + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (ret < 0) + return ret; + + ret = mem_dump_alloc(pdev); + return ret; +} + +static const struct of_device_id mem_dump_match_table[] = { + {.compatible = "qcom,mem-dump",}, + {} +}; + +static struct platform_driver mem_dump_driver = { + .probe = mem_dump_probe, + .driver = { + .name = "msm_mem_dump", + .of_match_table = mem_dump_match_table, + }, +}; + +module_platform_driver(mem_dump_driver); + +MODULE_DESCRIPTION("Memory Dump V2 Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/firmware/qcom/memory_dump.h b/include/linux/firmware/qcom/memory_dump.h new file mode 100644 index 0000000000000..ebb7c89d2f243 --- /dev/null +++ b/include/linux/firmware/qcom/memory_dump.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012, 2014-2017, 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __MSM_MEMORY_DUMP_H +#define __MSM_MEMORY_DUMP_H + +#include +#include + +enum dump_client_type { + MSM_CPU_CTXT = 0, + MSM_L1_CACHE, + MSM_L2_CACHE, + MSM_OCMEM, + MSM_TMC_ETFETB, + MSM_ETM0_REG, + MSM_ETM1_REG, + MSM_ETM2_REG, + MSM_ETM3_REG, + MSM_TMC0_REG, /* TMC_ETR */ + MSM_TMC1_REG, /* TMC_ETF */ + MSM_LOG_BUF, + MSM_LOG_BUF_FIRST_IDX, + MAX_NUM_CLIENTS, +}; + +struct msm_client_dump { + enum dump_client_type id; + unsigned long start_addr; + unsigned long end_addr; +}; + +#ifdef CONFIG_QCOM_MEMORY_DUMP +extern int msm_dump_tbl_register(struct msm_client_dump *client_entry); +#else +static inline int msm_dump_tbl_register(struct msm_client_dump *entry) +{ + return -EIO; +} +#endif + + +#if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2) +extern uint32_t msm_dump_table_version(void); +#else +static inline uint32_t msm_dump_table_version(void) +{ + return 0; +} +#endif + +#define MSM_DUMP_MAKE_VERSION(ma, mi) ((ma << 20) | mi) +#define MSM_DUMP_MAJOR(val) (val >> 20) +#define MSM_DUMP_MINOR(val) (val & 0xFFFFF) + + +#define MAX_NUM_ENTRIES 0x150 + +enum msm_dump_data_ids { + MSM_DUMP_DATA_CPU_CTX = 0x00, + MSM_DUMP_DATA_L1_INST_CACHE = 0x60, + MSM_DUMP_DATA_L1_DATA_CACHE = 0x80, + MSM_DUMP_DATA_ETM_REG = 0xA0, + MSM_DUMP_DATA_L2_CACHE = 0xC0, + MSM_DUMP_DATA_L3_CACHE = 0xD0, + MSM_DUMP_DATA_OCMEM = 0xE0, + MSM_DUMP_DATA_CNSS_WLAN = 0xE1, + MSM_DUMP_DATA_WIGIG = 0xE2, + MSM_DUMP_DATA_PMIC = 0xE4, + MSM_DUMP_DATA_DBGUI_REG = 0xE5, + MSM_DUMP_DATA_DCC_REG = 0xE6, + MSM_DUMP_DATA_DCC_SRAM = 0xE7, + MSM_DUMP_DATA_MISC = 0xE8, + MSM_DUMP_DATA_VSENSE = 0xE9, + MSM_DUMP_DATA_RPM = 0xEA, + MSM_DUMP_DATA_SCANDUMP = 0xEB, + MSM_DUMP_DATA_RPMH = 0xEC, + MSM_DUMP_DATA_TMC_ETF = 0xF0, + MSM_DUMP_DATA_TMC_ETF_SWAO = 0xF1, + MSM_DUMP_DATA_TMC_REG = 0x100, + MSM_DUMP_DATA_TMC_ETF_SWAO_REG = 0x102, + MSM_DUMP_DATA_LOG_BUF = 0x110, + MSM_DUMP_DATA_LOG_BUF_FIRST_IDX = 0x111, + MSM_DUMP_DATA_SCANDUMP_PER_CPU = 0x130, + MSM_DUMP_DATA_LLCC_PER_INSTANCE = 0x140, + MSM_DUMP_DATA_MAX = MAX_NUM_ENTRIES, +}; + +enum msm_dump_table_ids { + MSM_DUMP_TABLE_APPS, + MSM_DUMP_TABLE_MAX = MAX_NUM_ENTRIES, +}; + +enum msm_dump_type { + MSM_DUMP_TYPE_DATA, + MSM_DUMP_TYPE_TABLE, +}; + +struct msm_dump_data { + uint32_t version; + uint32_t magic; + char name[32]; + uint64_t addr; + uint64_t len; + uint32_t reserved; +}; + +struct msm_dump_entry { + uint32_t id; + char name[32]; + uint32_t type; + uint64_t addr; +}; + +#if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2) +extern int msm_dump_data_register(enum msm_dump_table_ids id, + struct msm_dump_entry *entry); +extern int msm_dump_data_register_nominidump(enum msm_dump_table_ids id, + struct msm_dump_entry *entry); +#else +static inline int msm_dump_data_register(enum msm_dump_table_ids id, + struct msm_dump_entry *entry) +{ + return -EINVAL; +} +static inline int msm_dump_data_register_nominidump(enum msm_dump_table_ids id, + struct msm_dump_entry *entry) +{ + return -EINVAL; +} +#endif + +#endif From c82575ba49338da8d5edf740e5d3d2e36dc42bac Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 12 Jan 2026 11:30:00 +0800 Subject: [PATCH 0265/1330] QCLINUX: mem-dump: add memory dump device driver Create memory dump device driver for matching the memory dump v2 driver without DT configuration. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom_debug.config | 1 + drivers/firmware/qcom/Kconfig | 6 + drivers/firmware/qcom/Makefile | 1 + drivers/firmware/qcom/memory_dump_dev.c | 379 ++++++++++++++++++++++ drivers/firmware/qcom/memory_dump_v2.c | 67 ++-- include/linux/firmware/qcom/memory_dump.h | 13 + 6 files changed, 420 insertions(+), 47 deletions(-) create mode 100644 drivers/firmware/qcom/memory_dump_dev.c diff --git a/arch/arm64/configs/qcom_debug.config b/arch/arm64/configs/qcom_debug.config index 2e85e8df0469b..d50f78f3a3ea2 100644 --- a/arch/arm64/configs/qcom_debug.config +++ b/arch/arm64/configs/qcom_debug.config @@ -1,3 +1,4 @@ CONFIG_QCOM_DCC=m CONFIG_QCOM_DCC_DEV=m CONFIG_QCOM_MEMORY_DUMP_V2=m +CONFIG_QCOM_MEMORY_DUMP_DEV=m diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index 531c6d2598ce0..39f63ef92e01a 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -83,4 +83,10 @@ config QCOM_MEMORY_DUMP_V2 of deadlocks or cpu hangs these dump regions are captured to give a snapshot of the system at the time of the crash. +config QCOM_MEMORY_DUMP_DEV + tristate "QCOM Memory Dump V2 device stub" + depends on QCOM_MEMORY_DUMP_V2 + help + Device stub for memory dump V2 driver. + endmenu diff --git a/drivers/firmware/qcom/Makefile b/drivers/firmware/qcom/Makefile index c5e17ba255937..01b293cae79ed 100644 --- a/drivers/firmware/qcom/Makefile +++ b/drivers/firmware/qcom/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_QCOM_TZMEM) += qcom_tzmem.o obj-$(CONFIG_QCOM_QSEECOM) += qcom_qseecom.o obj-$(CONFIG_QCOM_QSEECOM_UEFISECAPP) += qcom_qseecom_uefisecapp.o obj-$(CONFIG_QCOM_MEMORY_DUMP_V2) += memory_dump_v2.o +obj-$(CONFIG_QCOM_MEMORY_DUMP_DEV) += memory_dump_dev.o diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c new file mode 100644 index 0000000000000..556ebafae5280 --- /dev/null +++ b/drivers/firmware/qcom/memory_dump_dev.c @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#define DEV_NAME "msm_mem_dump" + +static struct platform_device *mem_dump_pdev; + +enum dump_ids { + C0_CONTEXT = 0x0, + C100_CONTEXT = 0x1, + C200_CONTEXT = 0x2, + C300_CONTEXT = 0x3, + C400_CONTEXT = 0x4, + C500_CONTEXT = 0x5, + C600_CONTEXT = 0x6, + C700_CONTEXT = 0x7, + L1_ITLB10000 = 0x24, + L1_ITLB10100 = 0x25, + L1_ITLB10200 = 0x26, + L1_ITLB10300 = 0x27, + L1_DTLB10000 = 0x44, + L1_DTLB10100 = 0x45, + L1_DTLB10200 = 0x46, + L1_DTLB10300 = 0x47, + L1_ICACHE0 = 0x60, + L1_ICACHE100 = 0x61, + L1_ICACHE200 = 0x62, + L1_ICACHE300 = 0x63, + L1_ICACHE10000 = 0x64, + L1_ICACHE10100 = 0x65, + L1_ICACHE10200 = 0x66, + L1_ICACHE10300 = 0x67, + L1_DCACHE0 = 0x80, + L1_DCACHE100 = 0x81, + L1_DCACHE200 = 0x82, + L1_DCACHE300 = 0x83, + L1_DCACHE10000 = 0x84, + L1_DCACHE10100 = 0x85, + L1_DCACHE10200 = 0x86, + L1_DCACHE10300 = 0x87, + L2_CACHE10000 = 0xc4, + L2_CACHE10100 = 0xc5, + L2_CACHE10200 = 0xc6, + L2_CACHE10300 = 0xc7, + PMIC = 0xe4, + MISC_DATA = 0xe8, + RPM_SW = 0xea, + RPMH = 0xec, + CPUSS_REG = 0xef, + TMC_ETF = 0xf0, + ETF_SWAO = 0xf1, + ETF_LPASS = 0xf4, + FCM = 0xee, + ETR_REG = 0x100, + ETF_REG = 0x101, + ETFSWAO_REG = 0x102, + ETFLPASS_REG = 0x104, + L2_TLB0 = 0x120, + L2_TLB100 = 0x121, + L2_TLB200 = 0x122, + L2_TLB300 = 0x123, + L2_TLB10000 = 0x124, + L2_TLB10100 = 0x125, + L2_TLB10200 = 0x126, + L2_TLB10300 = 0x127, + C0_SCANDUMP = 0x130, + C100_SCANDUMP = 0x131, + C200_SCANDUMP = 0x132, + C300_SCANDUMP = 0x133, + C10000_SCANDUMP = 0x134, + C10100_SCANDUMP = 0x135, + C10200_SCANDUMP = 0x136, + C10300_SCANDUMP = 0x137, + LLCC1_D_CACHE = 0x140, + LLCC2_D_CACHE = 0x141, + MHM_SCAN = 0x161, + GEMNOC = 0x162, + OSM_REG = 0x163, + PCU_REG = 0x164, + FSM_DATA = 0x165, +}; + +static const struct dump_item lemans_items[] = { + { C0_CONTEXT, 0x800, "c0-context" }, + { C0_SCANDUMP, 0x40000, "c0-scandump" }, + { C100_CONTEXT, 0x800, "c100-context" }, + { C100_SCANDUMP, 0x40000, "c100-scandump" }, + { C200_CONTEXT, 0x800, "c200-context" }, + { C200_SCANDUMP, 0x40000, "c200-scandump" }, + { C300_CONTEXT, 0x800, "c300-context" }, + { C300_SCANDUMP, 0x40000, "c300-scandump" }, + { C400_CONTEXT, 0x800, "c400-context" }, + { C500_CONTEXT, 0x800, "c500-context" }, + { C600_CONTEXT, 0x800, "c600-context" }, + { C700_CONTEXT, 0x800, "c700-context" }, + { C10000_SCANDUMP, 0x40000, "c10000-scandump" }, + { C10100_SCANDUMP, 0x40000, "c10100-scandump" }, + { C10200_SCANDUMP, 0x40000, "c10200-scandump" }, + { C10300_SCANDUMP, 0x40000, "c10300-scandump" }, + { CPUSS_REG, 0x20000, "cpuss-reg" }, + { ETF_SWAO, 0x10000, "etf-swao" }, + { ETFSWAO_REG, 0x1000, "etfswao-reg" }, + { ETR_REG, 0x1000, "etr-reg" }, + { FCM, 0x8400, "fcm" }, + { L1_DCACHE0, 0x12100, "l1-dcache0" }, + { L1_DCACHE100, 0x12100, "l1-dcache100" }, + { L1_DCACHE200, 0x12100, "l1-dcache200" }, + { L1_DCACHE300, 0x12100, "l1-dcache300" }, + { L1_DCACHE10000, 0x12100, "l1-dcache10000" }, + { L1_DCACHE10100, 0x12100, "l1-dcache10100" }, + { L1_DCACHE10200, 0x12100, "l1-dcache10200" }, + { L1_DCACHE10300, 0x12100, "l1-dcache10300" }, + { L1_DTLB10000, 0x300, "l1-dtlb10000" }, + { L1_DTLB10100, 0x300, "l1-dtlb10100" }, + { L1_DTLB10200, 0x300, "l1-dtlb10200" }, + { L1_DTLB10300, 0x300, "l1-dtlb10300" }, + { L1_ICACHE0, 0x26100, "l1-icache0" }, + { L1_ICACHE100, 0x26100, "l1-icache100" }, + { L1_ICACHE200, 0x26100, "l1-icache200" }, + { L1_ICACHE300, 0x26100, "l1-icache300" }, + { L1_ICACHE10000, 0x26100, "l1-icache10000" }, + { L1_ICACHE10100, 0x26100, "l1-icache10100" }, + { L1_ICACHE10200, 0x26100, "l1-icache10200" }, + { L1_ICACHE10300, 0x26100, "l1-icache10300" }, + { L1_ITLB10000, 0x300, "l1-itlb10000" }, + { L1_ITLB10100, 0x300, "l1-itlb10100" }, + { L1_ITLB10200, 0x300, "l1-itlb10200" }, + { L1_ITLB10300, 0x300, "l1-itlb10300" }, + { L2_CACHE10000, 0x90100, "l2-cache10000" }, + { L2_CACHE10100, 0x90100, "l2-cache10100" }, + { L2_CACHE10200, 0x90100, "l2-cache10200" }, + { L2_CACHE10300, 0x90100, "l2-cache10300" }, + { L2_TLB0, 0x6100, "l2-tlb0" }, + { L2_TLB100, 0x6100, "l2-tlb100" }, + { L2_TLB200, 0x6100, "l2-tlb200" }, + { L2_TLB300, 0x6100, "l2-tlb300" }, + { L2_TLB10000, 0x6100, "l2-tlb10000" }, + { L2_TLB10100, 0x6100, "l2-tlb10100" }, + { L2_TLB10200, 0x6100, "l2-tlb10200" }, + { L2_TLB10300, 0x6100, "l2-tlb10300" }, + { MISC_DATA, 0x1000, "misc-data" }, + { PMIC, 0x80000, "pmic" }, + { RPM_SW, 0x28000, "rpm-sw" }, + { RPMH, 0x2000000, "rpmh" }, +}; + +static const struct dump_item talos_items[] = { + { C0_CONTEXT, 0x800, "c0-context" }, + { C100_CONTEXT, 0x800, "c100-context" }, + { C200_CONTEXT, 0x800, "c200-context" }, + { C300_CONTEXT, 0x800, "c300-context" }, + { C400_CONTEXT, 0x800, "c400-context" }, + { C500_CONTEXT, 0x800, "c500-context" }, + { C600_CONTEXT, 0x800, "c600-context" }, + { C700_CONTEXT, 0x800, "c700-context" }, + { RPMH, 0x2000000, "rpmh" }, + { RPM_SW, 0x28000, "rpm-sw" }, + { PMIC, 0x10000, "pmic" }, + { FCM, 0x8400, "fcm" }, + { TMC_ETF, 0x8000, "tmc-etf" }, + { ETF_SWAO, 0x8000, "etf-swao" }, + { ETR_REG, 0x1000, "etr-reg" }, + { ETF_REG, 0x1000, "etf-reg" }, + { ETFSWAO_REG, 0x1000, "etfswao-reg" }, + { MISC_DATA, 0x1000, "misc-data" }, + { L1_ICACHE0, 0x8800, "l1-icache0" }, + { L1_ICACHE100, 0x8800, "l1-icache100" }, + { L1_ICACHE200, 0x8800, "l1-icache200" }, + { L1_ICACHE300, 0x8800, "l1-icache300" }, + { L1_ICACHE10000, 0x8800, "l1-icache400" }, + { L1_ICACHE10100, 0x8800, "l1-icache500" }, + { L1_ICACHE10200, 0x11000, "l1-icache600" }, + { L1_ICACHE10300, 0x11000, "l1-icache700" }, + { L1_DCACHE0, 0x9000, "l1-dcache0" }, + { L1_DCACHE100, 0x9000, "l1-dcache100" }, + { L1_DCACHE200, 0x9000, "l1-dcache200" }, + { L1_DCACHE300, 0x9000, "l1-dcache300" }, + { L1_DCACHE10000, 0x9000, "l1-dcache400" }, + { L1_DCACHE10100, 0x9000, "l1-dcache500" }, + { L1_DCACHE10200, 0x12000, "l1-dcache600" }, + { L1_DCACHE10300, 0x12000, "l1-dcache700" }, + { L1_ITLB10200, 0x300, "l1-itlb600" }, + { L1_ITLB10300, 0x300, "l1-itlb700" }, + { L1_DTLB10200, 0x480, "l1-dtlb600" }, + { L1_DTLB10300, 0x480, "l1-dtlb700" }, + { L2_CACHE10200, 0x48000, "l2-cache600" }, + { L2_CACHE10300, 0x48000, "l2-cache700" }, + { L2_TLB0, 0x5000, "l2-tlb0" }, + { L2_TLB100, 0x5000, "l2-tlb100" }, + { L2_TLB200, 0x5000, "l2-tlb200" }, + { L2_TLB300, 0x5000, "l2-tlb300" }, + { L2_TLB10000, 0x5000, "l2-tlb400" }, + { L2_TLB10100, 0x5000, "l2-tlb500" }, + { L2_TLB10200, 0x7800, "l2-tlb600" }, + { L2_TLB10300, 0x7800, "l2-tlb700" }, + { LLCC1_D_CACHE, 0x6c000, "llcc1-d-cache" }, +}; + +static const struct dump_item kodiak_items[] = { + { C0_CONTEXT, 0x800, "c0-context" }, + { C0_SCANDUMP, 0x10100, "c0-scandump" }, + { C100_CONTEXT, 0x800, "c100-context" }, + { C100_SCANDUMP, 0x10100, "c100-scandump" }, + { C200_CONTEXT, 0x800, "c200-context" }, + { C200_SCANDUMP, 0x10100, "c200-scandump" }, + { C300_CONTEXT, 0x800, "c300-context" }, + { C300_SCANDUMP, 0x10100, "c300-scandump" }, + { C400_CONTEXT, 0x800, "c400-context" }, + { C10000_SCANDUMP, 0x40000, "c400-scandump" }, + { C500_CONTEXT, 0x800, "c500-context" }, + { C10100_SCANDUMP, 0x40000, "c500-scandump" }, + { C600_CONTEXT, 0x800, "c600-context" }, + { C10200_SCANDUMP, 0x40000, "c600-scandump" }, + { C700_CONTEXT, 0x800, "c700-context" }, + { C10300_SCANDUMP, 0x40000, "c700-scandump" }, + { CPUSS_REG, 0x30000, "cpuss-reg" }, + { ETF_LPASS, 0x4000, "etf-lpass" }, + { ETFLPASS_REG, 0x1000, "etflpass-reg" }, + { ETF_SWAO, 0x10000, "etf-swao" }, + { ETFSWAO_REG, 0x1000, "etfswao-reg" }, + { ETR_REG, 0x1000, "etr-reg" }, + { FCM, 0x8400, "fcm" }, + { FSM_DATA, 0x400, "fsm-data" }, + { GEMNOC, 0x100000, "gemnoc" }, + { L1_DCACHE0, 0x9100, "l1-dcache0" }, + { L1_DCACHE100, 0x9100, "l1-dcache100" }, + { L1_DCACHE200, 0x9100, "l1-dcache200" }, + { L1_DCACHE300, 0x9100, "l1-dcache300" }, + { L1_DCACHE10000, 0x9100, "l1-dcache400" }, + { L1_DCACHE10100, 0x9100, "l1-dcache500" }, + { L1_DCACHE10200, 0x9100, "l1-dcache600" }, + { L1_DCACHE10300, 0x12100, "l1-dcache700" }, + { L1_DTLB10000, 0x300, "l1-dtlb400" }, + { L1_DTLB10100, 0x300, "l1-dtlb500" }, + { L1_DTLB10200, 0x300, "l1-dtlb600" }, + { L1_DTLB10300, 0x3a0, "l1-dtlb700" }, + { L1_ICACHE0, 0x10900, "l1-icache0" }, + { L1_ICACHE100, 0x10900, "l1-icache100" }, + { L1_ICACHE200, 0x10900, "l1-icache200" }, + { L1_ICACHE300, 0x10900, "l1-icache300" }, + { L1_ICACHE10000, 0x15100, "l1-icache400" }, + { L1_ICACHE10100, 0x15100, "l1-icache500" }, + { L1_ICACHE10200, 0x15100, "l1-icache600" }, + { L1_ICACHE10300, 0x32100, "l1-icache700" }, + { L1_ITLB10000, 0x300, "l1-itlb400" }, + { L1_ITLB10100, 0x300, "l1-itlb500" }, + { L1_ITLB10200, 0x300, "l1-itlb600" }, + { L1_ITLB10300, 0x400, "l1-itlb700" }, + { L2_CACHE10000, 0x90100, "l2-cache400" }, + { L2_CACHE10100, 0x90100, "l2-cache500" }, + { L2_CACHE10200, 0x90100, "l2-cache600" }, + { L2_CACHE10300, 0x120100, "l2-cache700" }, + { L2_TLB0, 0x5b00, "l2-tlb0" }, + { L2_TLB100, 0x5b00, "l2-tlb100" }, + { L2_TLB200, 0x5b00, "l2-tlb200" }, + { L2_TLB300, 0x5b00, "l2-tlb300" }, + { L2_TLB10000, 0x6100, "l2-tlb400" }, + { L2_TLB10100, 0x6100, "l2-tlb500" }, + { L2_TLB10200, 0x6100, "l2-tlb600" }, + { L2_TLB10300, 0xc100, "l2-tlb700" }, + { LLCC1_D_CACHE, 0x1141c0, "llcc1-d-cache" }, + { LLCC2_D_CACHE, 0x1141c0, "llcc2-d-cache" }, + { MHM_SCAN, 0x20000, "mhm-scan" }, + { MISC_DATA, 0x1000, "misc-data" }, + { OSM_REG, 0x400, "osm-reg" }, + { PCU_REG, 0x400, "pcu-reg" }, + { PMIC, 0x200000, "pmic" }, + { RPM_SW, 0x28000, "rpm-sw" }, + { RPMH, 0x2000000, "rpmh" }, +}; + +static const struct dump_table lemans_dump_table = { + .items = lemans_items, + .num_of_items = ARRAY_SIZE(lemans_items), + .imem_base = 0x146d8010, + .imem_size = 0x8, +}; + +static const struct dump_table talos_dump_table = { + .items = talos_items, + .num_of_items = ARRAY_SIZE(lemans_items), + .imem_base = 0x146aa010, + .imem_size = 0x8, +}; + +static const struct dump_table kodiak_dump_table = { + .items = kodiak_items, + .num_of_items = ARRAY_SIZE(kodiak_items), + .imem_base = 0x146aa010, + .imem_size = 0x8, +}; + +static int __init mem_dump_dev_init(void) +{ + int ret; + u32 soc_id; + + mem_dump_pdev = platform_device_alloc(DEV_NAME, -1); + if (!mem_dump_pdev) + return -ENOMEM; + + ret = qcom_smem_get_soc_id(&soc_id); + if (ret) + goto fail; + + switch (soc_id) { + case 377: + case 380: + case 384: + case 401: + case 406: + case 680: + ret = platform_device_add_data(mem_dump_pdev, + &talos_dump_table, sizeof(talos_dump_table)); + if (ret) + goto fail; + + break; + case 534: + case 606: + case 667: + case 674: + case 675: + case 676: + ret = platform_device_add_data(mem_dump_pdev, + &lemans_dump_table, sizeof(lemans_dump_table)); + if (ret) + goto fail; + + break; + case 475: + case 497: + case 498: + case 515: + ret = platform_device_add_data(mem_dump_pdev, + &kodiak_dump_table, sizeof(kodiak_dump_table)); + if (ret) + goto fail; + + break; + default: + dev_err(&mem_dump_pdev->dev, "Invalid SoC ID\n"); + ret = -EINVAL; + goto fail; + } + + ret = platform_device_add(mem_dump_pdev); + if (ret) + goto fail; + + dev_info(&mem_dump_pdev->dev, "Register platform device successfully\n"); + + return 0; + +fail: + dev_err(&mem_dump_pdev->dev, + "Failed to register memory dump platform device\n"); + platform_device_put(mem_dump_pdev); + + return ret; +} + +static void __exit mem_dump_dev_exit(void) +{ + platform_device_unregister(mem_dump_pdev); +} + +module_init(mem_dump_dev_init); +module_exit(mem_dump_dev_exit); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm Technologies Inc. Memory Dump driver V2, device stub"); diff --git a/drivers/firmware/qcom/memory_dump_v2.c b/drivers/firmware/qcom/memory_dump_v2.c index baf4c980f39fb..470d6047ee656 100644 --- a/drivers/firmware/qcom/memory_dump_v2.c +++ b/drivers/firmware/qcom/memory_dump_v2.c @@ -865,19 +865,11 @@ int msm_dump_data_register_nominidump(enum msm_dump_table_ids id, EXPORT_SYMBOL_GPL(msm_dump_data_register_nominidump); #define MSM_DUMP_TOTAL_SIZE_OFFSET 0x724 -static int init_memdump_imem_area(size_t size) +static int init_memdump_imem_area(const struct dump_table *table, size_t size) { - struct device_node *np; void __iomem *imem_base; - np = of_find_compatible_node(NULL, NULL, - "qcom,msm-imem-mem-dump-table"); - if (!np) { - pr_err("mem dump base table DT node does not exist\n"); - return -ENODEV; - } - - imem_base = of_iomap(np, 0); + imem_base = ioremap(table->imem_base, table->imem_size); if (!imem_base) { pr_err("mem dump base table imem offset mapping failed\n"); return -ENOMEM; @@ -924,13 +916,17 @@ static int init_memory_dump(void *dump_vaddr, phys_addr_t phys_addr) static int mem_dump_reserve_mem(struct device *dev) { struct device_node *mem_node; + struct reserved_mem *rmem; int ret; - mem_node = of_parse_phandle(dev->of_node, "memory-region", 0); + mem_node = of_find_node_by_path("/reserved-memory/mem-dump-region"); if (mem_node) { - ret = of_reserved_mem_device_init_by_idx(dev, - dev->of_node, 0); - of_node_put(dev->of_node); + rmem = of_reserved_mem_lookup(mem_node); + of_node_put(mem_node); + if (!rmem || !rmem->ops || !rmem->ops->device_init) + return -EINVAL; + + ret = rmem->ops->device_init(rmem, dev); if (ret) { dev_err(dev, "Failed to initialize reserved mem, ret %d\n", @@ -1005,34 +1001,26 @@ static int cpuss_dump_init(struct platform_device *pdev, #define MSM_DUMP_DATA_SIZE sizeof(struct msm_dump_data) static int mem_dump_alloc(struct platform_device *pdev) { - struct device_node *child_node; - const struct device_node *node = pdev->dev.of_node; struct msm_dump_data *dump_data; struct msm_dump_entry dump_entry; size_t total_size; u32 size, id; - int ret, no_of_nodes; + int i, ret, no_of_nodes; dma_addr_t dma_handle; phys_addr_t phys_addr; struct sg_table mem_dump_sgt; void *dump_vaddr; u64 shm_bridge_handle; int initialized = 0; + const struct dump_table *table = dev_get_platdata(&pdev->dev); if (mem_dump_reserve_mem(&pdev->dev) != 0) return -ENOMEM; total_size = size = ret = no_of_nodes = 0; /* For dump table registration with IMEM */ total_size = sizeof(struct msm_dump_table) * 2; - for_each_available_child_of_node(node, child_node) { - ret = of_property_read_u32(child_node, "qcom,dump-size", &size); - if (ret) { - dev_err(&pdev->dev, "Unable to find size for %s\n", - child_node->name); - continue; - } - - total_size += size; + for (i = 0; i < table->num_of_items; i++) { + total_size += table->items[i].size; no_of_nodes++; } @@ -1062,7 +1050,7 @@ static int mem_dump_alloc(struct platform_device *pdev) return ret; } - ret = init_memdump_imem_area(total_size); + ret = init_memdump_imem_area(table, total_size); if (ret) { qcom_tzmem_shm_bridge_delete(shm_bridge_handle); return ret; @@ -1070,24 +1058,15 @@ static int mem_dump_alloc(struct platform_device *pdev) dump_vaddr += (sizeof(struct msm_dump_table) * 2); phys_addr += (sizeof(struct msm_dump_table) * 2); - for_each_available_child_of_node(node, child_node) { - ret = of_property_read_u32(child_node, "qcom,dump-size", &size); - if (ret) - continue; - - ret = of_property_read_u32(child_node, "qcom,dump-id", &id); - if (ret) { - dev_err(&pdev->dev, "Unable to find id for %s\n", - child_node->name); - continue; - } - + for (i = 0; i < table->num_of_items; i++) { + size = table->items[i].size; + id = table->items[i].dump_id; dump_data = dump_vaddr; dump_data->addr = phys_addr + MSM_DUMP_DATA_SIZE; dump_data->len = size; dump_entry.id = id; - strscpy(dump_data->name, child_node->name, - sizeof(dump_data->name)); + strscpy(dump_data->name, table->items[i].name, + sizeof(table->items[i].name)); dump_entry.addr = phys_addr; ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS, &dump_entry); @@ -1124,16 +1103,10 @@ static int mem_dump_probe(struct platform_device *pdev) return ret; } -static const struct of_device_id mem_dump_match_table[] = { - {.compatible = "qcom,mem-dump",}, - {} -}; - static struct platform_driver mem_dump_driver = { .probe = mem_dump_probe, .driver = { .name = "msm_mem_dump", - .of_match_table = mem_dump_match_table, }, }; diff --git a/include/linux/firmware/qcom/memory_dump.h b/include/linux/firmware/qcom/memory_dump.h index ebb7c89d2f243..e72436feb0544 100644 --- a/include/linux/firmware/qcom/memory_dump.h +++ b/include/linux/firmware/qcom/memory_dump.h @@ -115,6 +115,19 @@ struct msm_dump_entry { uint64_t addr; }; +struct dump_item { + u32 dump_id; + size_t size; + const char *name; +}; + +struct dump_table { + const struct dump_item *items; + u32 num_of_items; + phys_addr_t imem_base; + resource_size_t imem_size; +}; + #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2) extern int msm_dump_data_register(enum msm_dump_table_ids id, struct msm_dump_entry *entry); From 5a2498865e55dedff36f944aed645715b9c428af Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 2 Feb 2026 18:16:25 +0800 Subject: [PATCH 0266/1330] QCLINUX: memory-dump: add logic for reserving CMA memory Memory dump driver needs a large CMA memory zone for storing memory dump table. Add codes for reserving CMA memory during the init stage. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom_debug.config | 2 +- arch/arm64/mm/init.c | 4 ++ drivers/firmware/qcom/Kconfig | 1 + drivers/firmware/qcom/memory_dump_v2.c | 58 +++++++++-------------- include/linux/firmware/qcom/memory_dump.h | 4 +- 5 files changed, 31 insertions(+), 38 deletions(-) diff --git a/arch/arm64/configs/qcom_debug.config b/arch/arm64/configs/qcom_debug.config index d50f78f3a3ea2..48ae2fb9737ac 100644 --- a/arch/arm64/configs/qcom_debug.config +++ b/arch/arm64/configs/qcom_debug.config @@ -1,4 +1,4 @@ CONFIG_QCOM_DCC=m CONFIG_QCOM_DCC_DEV=m -CONFIG_QCOM_MEMORY_DUMP_V2=m +CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_MEMORY_DUMP_DEV=m diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index b9b248d24fd10..2118ab09dd88c 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -48,6 +48,7 @@ #include #include #include +#include /* * We need to be able to catch inadvertent references to memstart_addr @@ -324,6 +325,9 @@ void __init bootmem_init(void) * reserved, so do it here. */ arch_reserve_crashkernel(); +#if defined(CONFIG_QCOM_MEMORY_DUMP_V2) + reserve_memdump_cma(); +#endif memblock_dump_all(); } diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index 39f63ef92e01a..dd20fed163e3f 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -77,6 +77,7 @@ config QCOM_QSEECOM_UEFISECAPP config QCOM_MEMORY_DUMP_V2 tristate "QCOM Memory Dump V2 Support" depends on QCOM_TZMEM + depends on CMA help This enables memory dump feature. It allows various client subsystems to register respective dump regions. At the time diff --git a/drivers/firmware/qcom/memory_dump_v2.c b/drivers/firmware/qcom/memory_dump_v2.c index 470d6047ee656..831d1aea86e09 100644 --- a/drivers/firmware/qcom/memory_dump_v2.c +++ b/drivers/firmware/qcom/memory_dump_v2.c @@ -18,6 +18,10 @@ #include #include #include +#include +#include +#include +#include #define MSM_DUMP_TABLE_VERSION MSM_DUMP_MAKE_VERSION(2, 0) @@ -913,30 +917,6 @@ static int init_memory_dump(void *dump_vaddr, phys_addr_t phys_addr) return 0; } -static int mem_dump_reserve_mem(struct device *dev) -{ - struct device_node *mem_node; - struct reserved_mem *rmem; - int ret; - - mem_node = of_find_node_by_path("/reserved-memory/mem-dump-region"); - if (mem_node) { - rmem = of_reserved_mem_lookup(mem_node); - of_node_put(mem_node); - if (!rmem || !rmem->ops || !rmem->ops->device_init) - return -EINVAL; - - ret = rmem->ops->device_init(rmem, dev); - if (ret) { - dev_err(dev, - "Failed to initialize reserved mem, ret %d\n", - ret); - return ret; - } - } - return 0; -} - static int cpuss_regdump_init(struct device *dev, void *dump_vaddr, u32 size) { @@ -998,6 +978,18 @@ static int cpuss_dump_init(struct platform_device *pdev, return initialized; } +struct cma *memdump_cma; +void __init reserve_memdump_cma(void) +{ + unsigned long long cma_size = 0x3000000; + unsigned long long request_size = roundup(cma_size, PAGE_SIZE); + + if (cma_declare_contiguous(0, request_size, 0, 0, 0, false, + "memdump", &memdump_cma)) { + pr_warn("memdump CMA reservation failed\n"); + } +} + #define MSM_DUMP_DATA_SIZE sizeof(struct msm_dump_data) static int mem_dump_alloc(struct platform_device *pdev) { @@ -1006,16 +998,13 @@ static int mem_dump_alloc(struct platform_device *pdev) size_t total_size; u32 size, id; int i, ret, no_of_nodes; - dma_addr_t dma_handle; phys_addr_t phys_addr; - struct sg_table mem_dump_sgt; void *dump_vaddr; u64 shm_bridge_handle; int initialized = 0; const struct dump_table *table = dev_get_platdata(&pdev->dev); + struct page *reserved_page; - if (mem_dump_reserve_mem(&pdev->dev) != 0) - return -ENOMEM; total_size = size = ret = no_of_nodes = 0; /* For dump table registration with IMEM */ total_size = sizeof(struct msm_dump_table) * 2; @@ -1026,15 +1015,12 @@ static int mem_dump_alloc(struct platform_device *pdev) total_size += (MSM_DUMP_DATA_SIZE * no_of_nodes); total_size = ALIGN(total_size, SZ_4K); - dump_vaddr = dmam_alloc_coherent(&pdev->dev, total_size, - &dma_handle, GFP_KERNEL); - if (!dump_vaddr) + reserved_page = cma_alloc(memdump_cma, total_size >> PAGE_SHIFT, + 0, false); + if (!reserved_page) return -ENOMEM; - - dma_get_sgtable(&pdev->dev, &mem_dump_sgt, dump_vaddr, - dma_handle, total_size); - phys_addr = page_to_phys(sg_page(mem_dump_sgt.sgl)); - sg_free_table(&mem_dump_sgt); + phys_addr = page_to_phys(reserved_page); + dump_vaddr = page_to_virt(reserved_page); memset(dump_vaddr, 0x0, total_size); ret = qcom_tzmem_shm_bridge_create(phys_addr, total_size, &shm_bridge_handle); diff --git a/include/linux/firmware/qcom/memory_dump.h b/include/linux/firmware/qcom/memory_dump.h index e72436feb0544..ead7add4265c5 100644 --- a/include/linux/firmware/qcom/memory_dump.h +++ b/include/linux/firmware/qcom/memory_dump.h @@ -33,6 +33,9 @@ struct msm_client_dump { unsigned long end_addr; }; +void __init reserve_memdump_cma(void); +extern struct cma *memdump_cma; + #ifdef CONFIG_QCOM_MEMORY_DUMP extern int msm_dump_tbl_register(struct msm_client_dump *client_entry); #else @@ -42,7 +45,6 @@ static inline int msm_dump_tbl_register(struct msm_client_dump *entry) } #endif - #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2) extern uint32_t msm_dump_table_version(void); #else From 79a54df024f9dbd55c3fabe5fd692f15eb695825 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 9 Feb 2026 13:44:34 +0800 Subject: [PATCH 0267/1330] QCLINUX: qcom-dcc: add device configuration for Pakala Add device configuration to enable DCC on Pakala platform. Signed-off-by: Jie Gan --- drivers/misc/qcom-dcc-dev.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index e0eb2e61d652b..0c2369a4843ae 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -39,6 +39,15 @@ static const struct dcc_pdata kodiak_pdata = { .map_ver = 0x2, }; +static const struct dcc_pdata pakala_pdata = { + .base = 0x100ff000, + .size = 0x00001000, + .ram_base = 0x10084000, + .ram_size = 0x4000, + .dcc_offset = 0x4000, + .map_ver = 0x3, +}; + static int __init dcc_dev_init(void) { int ret; @@ -83,6 +92,15 @@ static int __init dcc_dev_init(void) if (ret) goto fail; + break; + case 618: + case 639: + case 705: + case 706: + ret = platform_device_add_data(dcc_pdev, &pakala_pdata, sizeof(pakala_pdata)); + if (ret) + goto fail; + break; default: pr_err("DCC: Invalid SoC ID\n"); From 834bebeab792c07e6617cb1e5e034840ccf61b55 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 9 Feb 2026 14:10:29 +0800 Subject: [PATCH 0268/1330] QCLINUX: memory-dump: add memory dump table for Pakala Add memory dump table configuration to enable memory dump function on Pakala platform. Signed-off-by: Jie Gan --- drivers/firmware/qcom/memory_dump_dev.c | 50 +++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c index 556ebafae5280..1626a67017990 100644 --- a/drivers/firmware/qcom/memory_dump_dev.c +++ b/drivers/firmware/qcom/memory_dump_dev.c @@ -57,12 +57,15 @@ enum dump_ids { CPUSS_REG = 0xef, TMC_ETF = 0xf0, ETF_SWAO = 0xf1, + ETF_SLPI = 0xf3, ETF_LPASS = 0xf4, FCM = 0xee, ETR_REG = 0x100, ETF_REG = 0x101, ETFSWAO_REG = 0x102, + ETFSLPI_REG = 0x103, ETFLPASS_REG = 0x104, + ETR1_REG = 0x105, L2_TLB0 = 0x120, L2_TLB100 = 0x121, L2_TLB200 = 0x122, @@ -86,6 +89,7 @@ enum dump_ids { OSM_REG = 0x163, PCU_REG = 0x164, FSM_DATA = 0x165, + SCANDUMP_SMMU = 0x220, }; static const struct dump_item lemans_items[] = { @@ -277,6 +281,35 @@ static const struct dump_item kodiak_items[] = { { RPMH, 0x2000000, "rpmh" }, }; +static const struct dump_item pakala_items[] = { + { C0_CONTEXT, 0x800, "c0-context" }, + { C100_CONTEXT, 0x800, "c100-context" }, + { C200_CONTEXT, 0x800, "c200-context" }, + { C300_CONTEXT, 0x800, "c300-context" }, + { C400_CONTEXT, 0x800, "c400-context" }, + { C500_CONTEXT, 0x800, "c500-context" }, + { C600_CONTEXT, 0x800, "c600-context" }, + { C700_CONTEXT, 0x800, "c700-context" }, + { RPMH, 0x400000, "rpmh" }, + { RPM_SW, 0x28000, "rpm-sw" }, + { PMIC, 0x200000, "pmic" }, + { FCM, 0x8400, "fcm" }, + { MISC_DATA, 0x1000, "misc-data" }, + { ETF_SWAO, 0x10000, "etf-swao" }, + { ETR_REG, 0x1000, "etr-reg" }, + { ETFSWAO_REG, 0x1000, "etfswao-reg" }, + { ETR1_REG, 0x1000, "etr1-reg" }, + { ETF_SLPI, 0x4000, "etf-slpi" }, + { ETFSLPI_REG, 0x1000, "etfslpi-reg" }, + { ETF_LPASS, 0x4000, "etf-lpass" }, + { ETFLPASS_REG, 0x1000, "etflpass-reg" }, + { OSM_REG, 0x400, "osm-reg" }, + { PCU_REG, 0x400, "pcu-reg" }, + { FSM_DATA, 0x400, "fsm-data" }, + { SCANDUMP_SMMU, 0x40000, "scandump-smmu" }, + { C0_SCANDUMP, 0x380000, "apps-scandump" }, +}; + static const struct dump_table lemans_dump_table = { .items = lemans_items, .num_of_items = ARRAY_SIZE(lemans_items), @@ -298,6 +331,13 @@ static const struct dump_table kodiak_dump_table = { .imem_size = 0x8, }; +static const struct dump_table pakala_dump_table = { + .items = pakala_items, + .num_of_items = ARRAY_SIZE(pakala_items), + .imem_base = 0x14680010, + .imem_size = 0x8, +}; + static int __init mem_dump_dev_init(void) { int ret; @@ -345,6 +385,16 @@ static int __init mem_dump_dev_init(void) if (ret) goto fail; + break; + case 618: + case 639: + case 705: + case 706: + ret = platform_device_add_data(mem_dump_pdev, + &pakala_dump_table, sizeof(pakala_dump_table)); + if (ret) + goto fail; + break; default: dev_err(&mem_dump_pdev->dev, "Invalid SoC ID\n"); From b25f5e2fc483a5b9e61a24f29a68153df46589b0 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 9 Feb 2026 14:58:04 +0800 Subject: [PATCH 0269/1330] QCLINUX: qcom-dcc: add device configuration for Kaanapali Add device configuration to enable DCC on Kaanapali platform. Signed-off-by: Jie Gan --- drivers/misc/qcom-dcc-dev.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index 0c2369a4843ae..5ed2a117b9e81 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -48,6 +48,15 @@ static const struct dcc_pdata pakala_pdata = { .map_ver = 0x3, }; +static const struct dcc_pdata kaanapali_pdata = { + .base = 0x100ff000, + .size = 0x1000, + .ram_base = 0x10080000, + .ram_size = 0x8000, + .dcc_offset = 0x0, + .map_ver = 0x3, +}; + static int __init dcc_dev_init(void) { int ret; @@ -101,6 +110,18 @@ static int __init dcc_dev_init(void) if (ret) goto fail; + break; + case 660: + case 661: + case 704: + case 722: + case 723: + case 730: + case 743: + ret = platform_device_add_data(dcc_pdev, &kaanapali_pdata, sizeof(kaanapali_pdata)); + if (ret) + goto fail; + break; default: pr_err("DCC: Invalid SoC ID\n"); From 20f216e90cbea32ae2db769ae57eaf188a76295e Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 9 Feb 2026 15:16:19 +0800 Subject: [PATCH 0270/1330] QCLINUX: memory-dump: add memory dump table for Kaanapali Add memory dump table configuration to enable memory dump function on Kaanapali platform. Signed-off-by: Jie Gan --- drivers/firmware/qcom/memory_dump_dev.c | 49 +++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c index 1626a67017990..d02e6af6c03a0 100644 --- a/drivers/firmware/qcom/memory_dump_dev.c +++ b/drivers/firmware/qcom/memory_dump_dev.c @@ -310,6 +310,35 @@ static const struct dump_item pakala_items[] = { { C0_SCANDUMP, 0x380000, "apps-scandump" }, }; +static const struct dump_item kaanapali_items[] = { + { C0_CONTEXT, 0x800, "c0-context" }, + { C100_CONTEXT, 0x800, "c100-context" }, + { C200_CONTEXT, 0x800, "c200-context" }, + { C300_CONTEXT, 0x800, "c300-context" }, + { C400_CONTEXT, 0x800, "c400-context" }, + { C500_CONTEXT, 0x800, "c500-context" }, + { C600_CONTEXT, 0x800, "c600-context" }, + { C700_CONTEXT, 0x800, "c700-context" }, + { RPMH, 0x400000, "rpmh" }, + { RPM_SW, 0x28000, "rpm-sw" }, + { PMIC, 0x200000, "pmic" }, + { FCM, 0x8400, "fcm" }, + { MISC_DATA, 0x1000, "misc-data" }, + { ETF_SWAO, 0x10000, "etf-swao" }, + { ETR_REG, 0x1000, "etr-reg" }, + { ETFSWAO_REG, 0x1000, "etfswao-reg" }, + { ETR1_REG, 0x1000, "etr1-reg" }, + { ETF_SLPI, 0x4000, "etf-slpi" }, + { ETFSLPI_REG, 0x1000, "etfslpi-reg" }, + { ETF_LPASS, 0x4000, "etf-lpass" }, + { ETFLPASS_REG, 0x1000, "etflpass-reg" }, + { OSM_REG, 0x400, "osm-reg" }, + { PCU_REG, 0x400, "pcu-reg" }, + { FSM_DATA, 0x400, "fsm-data" }, + { SCANDUMP_SMMU, 0x40000, "scandump-smmu" }, + { C0_SCANDUMP, 0x380000, "apps-scandump" }, +}; + static const struct dump_table lemans_dump_table = { .items = lemans_items, .num_of_items = ARRAY_SIZE(lemans_items), @@ -338,6 +367,13 @@ static const struct dump_table pakala_dump_table = { .imem_size = 0x8, }; +static const struct dump_table kaanapali_dump_table = { + .items = kaanapali_items, + .num_of_items = ARRAY_SIZE(kaanapali_items), + .imem_base = 0x14680010, + .imem_size = 0x8, +}; + static int __init mem_dump_dev_init(void) { int ret; @@ -395,6 +431,19 @@ static int __init mem_dump_dev_init(void) if (ret) goto fail; + break; + case 660: + case 661: + case 704: + case 722: + case 723: + case 730: + case 743: + ret = platform_device_add_data(mem_dump_pdev, + &kaanapali_dump_table, sizeof(kaanapali_dump_table)); + if (ret) + goto fail; + break; default: dev_err(&mem_dump_pdev->dev, "Invalid SoC ID\n"); From eabf058dec714def778b6df6cb684403e7d66eb1 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 9 Feb 2026 15:32:10 +0800 Subject: [PATCH 0271/1330] QCLINUX: qcom-dcc: add device configuration for Hamoa Add device configuration to enable DCC on Hamoa platform. Signed-off-by: Jie Gan --- drivers/misc/qcom-dcc-dev.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index 5ed2a117b9e81..ff19dac70011f 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -57,6 +57,15 @@ static const struct dcc_pdata kaanapali_pdata = { .map_ver = 0x3, }; +static const struct dcc_pdata hamoa_pdata = { + .base = 0x100ff000, + .size = 0x1000, + .ram_base = 0x10080000, + .ram_size = 0x18000, + .dcc_offset = 0x0, + .map_ver = 0x3, +}; + static int __init dcc_dev_init(void) { int ret; @@ -122,6 +131,16 @@ static int __init dcc_dev_init(void) if (ret) goto fail; + break; + case 555: + case 615: + case 616: + case 709: + case 710: + ret = platform_device_add_data(dcc_pdev, &hamoa_pdata, sizeof(hamoa_pdata)); + if (ret) + goto fail; + break; default: pr_err("DCC: Invalid SoC ID\n"); From 085b09778eeed438258a28fbd8efbc84d41a76f8 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 9 Feb 2026 15:45:31 +0800 Subject: [PATCH 0272/1330] QCLINUX: memory-dump: add memory dump table for Hamoa Add memory dump table configuration to enable memory dump function on Hamoa platform. Signed-off-by: Jie Gan --- drivers/firmware/qcom/memory_dump_dev.c | 34 +++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c index d02e6af6c03a0..0f89cb201b783 100644 --- a/drivers/firmware/qcom/memory_dump_dev.c +++ b/drivers/firmware/qcom/memory_dump_dev.c @@ -339,6 +339,22 @@ static const struct dump_item kaanapali_items[] = { { C0_SCANDUMP, 0x380000, "apps-scandump" }, }; +static const struct dump_item hamoa_items[] = { + { C0_CONTEXT, 0x800, "c0-context" }, + { C100_CONTEXT, 0x800, "c100-context" }, + { C200_CONTEXT, 0x800, "c200-context" }, + { C300_CONTEXT, 0x800, "c300-context" }, + { C400_CONTEXT, 0x800, "c400-context" }, + { C500_CONTEXT, 0x800, "c500-context" }, + { C600_CONTEXT, 0x800, "c600-context" }, + { C700_CONTEXT, 0x800, "c700-context" }, + { RPMH, 0xc10000, "rpmh" }, + { PMIC, 0x200000, "pmic" }, + { ETF_SWAO, 0x10000, "etf-swao" }, + { ETR_REG, 0x1000, "etr-reg" }, + { ETFSWAO_REG, 0x1000, "etfswao-reg" }, +}; + static const struct dump_table lemans_dump_table = { .items = lemans_items, .num_of_items = ARRAY_SIZE(lemans_items), @@ -374,6 +390,13 @@ static const struct dump_table kaanapali_dump_table = { .imem_size = 0x8, }; +static const struct dump_table hamoa_dump_table = { + .items = hamoa_items, + .num_of_items = ARRAY_SIZE(hamoa_items), + .imem_base = 0x146aa010, + .imem_size = 0x8, +}; + static int __init mem_dump_dev_init(void) { int ret; @@ -444,6 +467,17 @@ static int __init mem_dump_dev_init(void) if (ret) goto fail; + break; + case 555: + case 615: + case 616: + case 709: + case 710: + ret = platform_device_add_data(mem_dump_pdev, + &hamoa_dump_table, sizeof(hamoa_dump_table)); + if (ret) + goto fail; + break; default: dev_err(&mem_dump_pdev->dev, "Invalid SoC ID\n"); From 1d10dc1327890fa18dde35180e507a827ed4b843 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 4 Mar 2026 09:15:02 +0800 Subject: [PATCH 0273/1330] QCLINUX: memory-dump: fix array size issue for Talos Fix the wrong arrary size issue for Talos. Signed-off-by: Jie Gan --- drivers/firmware/qcom/memory_dump_dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c index 0f89cb201b783..78fb377800bc9 100644 --- a/drivers/firmware/qcom/memory_dump_dev.c +++ b/drivers/firmware/qcom/memory_dump_dev.c @@ -364,7 +364,7 @@ static const struct dump_table lemans_dump_table = { static const struct dump_table talos_dump_table = { .items = talos_items, - .num_of_items = ARRAY_SIZE(lemans_items), + .num_of_items = ARRAY_SIZE(talos_items), .imem_base = 0x146aa010, .imem_size = 0x8, }; From fd30232ae7e954fe00530ef70ea7b53a0f80bee6 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 4 Mar 2026 12:39:18 +0530 Subject: [PATCH 0274/1330] dt-bindings: sram: qcom,imem: Add the Shikra compatible Add compatible for Shikra SoC IMEM. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 6a627c57ae2fe..977db8d7b78b6 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -36,6 +36,7 @@ properties: - qcom,sdx55-imem - qcom,sdx65-imem - qcom,sdx75-imem + - qcom,shikra-imem - qcom,sm6115-imem - qcom,sm6125-imem - qcom,sm6350-imem From b27409c1f9a3e9a34dd64784711baaa48b41c87c Mon Sep 17 00:00:00 2001 From: Shuai Zhang Date: Mon, 2 Feb 2026 17:03:05 +0800 Subject: [PATCH 0275/1330] FROMLIST: driver: bluetooth:btusb: Allow firmwarea re-download when version matches Since USB can disconnect at any time, if it disconnects during the BT firmware download, the BT controller firmware version may still be updated even without completing the download. When USB reconnects, the BT host detects the same version as in the firmware file, which prevents the firmware from being downloaded again. Therefore, remove the equality check to ensure that after USB reconnection, the BT host can still download the firmware. Signed-off-by: Shuai Zhang Link: https://lore.kernel.org/all/20260108074353.1027877-1-shuai.zhang@oss.qualcomm.com/ --- drivers/bluetooth/btusb.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c index 9c89a82046a7d..49152391d4a59 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c @@ -3541,11 +3541,8 @@ static int btusb_setup_qca_load_rampatch(struct hci_dev *hdev, "firmware rome 0x%x build 0x%x", rver_rom, rver_patch, ver_rom, ver_patch); - /* Allow rampatch when the patch version equals the firmware version. - * A firmware download may be aborted by a transient USB error (e.g. - * disconnect) after the controller updates version info but before - * completion. - * Allowing equal versions enables re-flashing during recovery. + /* Allow rampatch if version is greater than or equal to firmware version. + * Equal versions are acceptable for re-flashing or recovery scenarios. */ if (rver_rom != ver_rom || rver_patch < ver_patch) { bt_dev_err(hdev, "rampatch file version did not match with firmware"); From 092e9f87d14354e81892ad23022cc687c79b9afe Mon Sep 17 00:00:00 2001 From: Jinwang Li Date: Mon, 5 Jan 2026 20:25:05 +0800 Subject: [PATCH 0276/1330] FROMLIST: driver: bluetooth: hci_qca: Cleanup on all setup failures The setup process previously combined error handling and retry gating under one condition. As a result, the final failed attempt exited without performing cleanup. Update the failure path to always perform power and port cleanup on setup failure, and reopen the port only when retrying. Fixes: 9e80587aba4c ("Bluetooth: hci_qca: Enhance retry logic in qca_setup") Signed-off-by: Jinwang Li Reviewed-by: Bartosz Golaszewski Link: https://lore.kernel.org/all/20260205062600.590342-1-jinwang.li@oss.qualcomm.com/ From 83e2f1edf58546ed8f857ebb95cd0bd6a3a957f0 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 4 Mar 2026 12:15:34 +0530 Subject: [PATCH 0277/1330] WORKAROUND: Revert "PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller" commit f5cd8a929c825("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller") removed MSI & MSIX capability for Root port as dwc controller doesn't support to generate interrupt. Due to this pci framework is falling back to legacy IRQ's. Now controller can generate to interrupts with legacy IRQ's, and actually causing console flood with PCIe continous AER errorsi, these errors will not cause any functional issues. To avoid these errors revert this temporarly untill actual issue got root caused and fixed. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d615249b1f989..5ca1ddd12b7da 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1165,17 +1165,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) dw_pcie_dbi_ro_wr_dis(pci); - /* - * The iMSI-RX module does not support receiving MSI or MSI-X generated - * by the Root Port. If iMSI-RX is used as the MSI controller, remove - * the MSI and MSI-X capabilities of the Root Port to allow the drivers - * to fall back to INTx instead. - */ - if (pp->use_imsi_rx && !pp->keep_rp_msi_en) { - dw_pcie_remove_capability(pci, PCI_CAP_ID_MSI); - dw_pcie_remove_capability(pci, PCI_CAP_ID_MSIX); - } - return 0; } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); From 70a62568238538f5c897ed36cb5f0d73e9ee6b80 Mon Sep 17 00:00:00 2001 From: Sushrut Shree Trivedi Date: Thu, 12 Feb 2026 16:14:01 +0530 Subject: [PATCH 0278/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Add a node for the TC9563 PCIe switch connected to PCIe0. The switch has three downstream ports.Two embedded Ethernet devices are present on one of the downstream ports. All the ports present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, which are on by default and are added as fixed regulators. TC9563 can be configured through I2C. Signed-off-by: Sushrut Shree Trivedi Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/lkml/20260212-industrial-mezzanine-pcie-v3-1-1e152937a76a@oss.qualcomm.com/ --- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index cc8ee16431679..41006fb4dcc03 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -5,6 +5,7 @@ /dts-v1/; /plugin/; +#include #include #include @@ -60,6 +61,37 @@ }; }; + vreg_0p9: regulator-vreg-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-always-on; + regulator-boot-on; + vin-supply = <&vreg_dc_12v>; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + vin-supply = <&vreg_dc_12v>; + }; + + vreg_dc_12v: regulator-vreg-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "VREG_DC_12V"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { @@ -125,3 +157,112 @@ spi-max-frequency = <20000000>; }; }; + +&pcie0 { + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>, + <0x208 &apps_smmu 0x1c04 0x1>, + <0x210 &apps_smmu 0x1c05 0x1>, + <0x218 &apps_smmu 0x1c06 0x1>, + <0x300 &apps_smmu 0x1c07 0x1>, + <0x400 &apps_smmu 0x1c08 0x1>, + <0x500 &apps_smmu 0x1c09 0x1>, + <0x501 &apps_smmu 0x1c10 0x1>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie0_port { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c1 0x77>; + + resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + + }; +}; + +&tlmm { + pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { + pins = "gpio78"; + function = "gpio"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; +}; From e27f7f9e976f52d1e76ffd3cc163337c6d42c54d Mon Sep 17 00:00:00 2001 From: Sushrut Shree Trivedi Date: Thu, 12 Feb 2026 16:14:02 +0530 Subject: [PATCH 0279/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Add a node for the second TC9563 PCIe switch on PCIe1, which is connected in cascade to the first TC9563 switch via the former's downstream port. Two embedded Ethernet devices are present on one of the downstream ports of this second switch as well. All the ports present in the node represent the downstream ports and embedded endpoints. The second TC9563 is powered up via the same LDO regulators as the first one, and these can be controlled via two GPIOs, which are already present as fixed regulators. This TC9563 can also be configured through I2C. Signed-off-by: Sushrut Shree Trivedi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/lkml/20260212-industrial-mezzanine-pcie-v3-2-1e152937a76a@oss.qualcomm.com/ --- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 105 ++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +- 2 files changed, 106 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 41006fb4dcc03..b37fb86108f67 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -255,6 +255,100 @@ }; }; +&pcie1 { + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x408 &apps_smmu 0x1c90 0x1>, + <0x410 &apps_smmu 0x1c91 0x1>, + <0x418 &apps_smmu 0x1c92 0x1>, + <0x500 &apps_smmu 0x1c93 0x1>, + <0x600 &apps_smmu 0x1c94 0x1>, + <0x700 &apps_smmu 0x1c95 0x1>, + <0x701 &apps_smmu 0x1c96 0x1>, + <0x800 &apps_smmu 0x1c97 0x1>, + <0x900 &apps_smmu 0x1c98 0x1>, + <0x901 &apps_smmu 0x1c99 0x1>; +}; + +&pcie1_switch0_dsp1 { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x30000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + i2c-parent = <&i2c1 0x33>; + + resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x40800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x41000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x41800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + &tlmm { pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { pins = "gpio78"; @@ -265,4 +359,15 @@ output-enable; power-source = <0>; }; + + pcie1_tc9563_resx_n: pcie1-tc9563-resx-state { + pins = "gpio124"; + function = "gpio"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index b714394f9a469..d8b9b343cfa52 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -850,7 +850,7 @@ pinctrl-0 = <&tc9563_resx_n>; pinctrl-names = "default"; - pcie@1,0 { + pcie1_switch0_dsp1: pcie@1,0 { reg = <0x20800 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; From 731b440c4a08ffb84c3a64a9db740a340d646990 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Tue, 17 Feb 2026 16:49:08 +0530 Subject: [PATCH 0280/1330] FROMLIST: PCI: qcom: Add .get_ltssm() helper For older targets like sc7280, we see reading DBI after sending PME turn off message is causing NOC error. To avoid unsafe DBI accesses, introduce qcom_pcie_get_ltssm(), which retrieves the LTSSM state from the PARF_LTSSM register instead. Link: https://lore.kernel.org/r/20260217-d3cold-v2-3-89b322864043@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4a824998bef8f..871eeca189ba9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -132,6 +132,7 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +#define PARF_LTSSM_STATE_MASK GENMASK(5, 0) /* PARF_NO_SNOOP_OVERRIDE register fields */ #define WR_NO_SNOOP_OVERRIDE_EN BIT(1) @@ -1267,6 +1268,15 @@ static bool qcom_pcie_link_up(struct dw_pcie *pci) return val & PCI_EXP_LNKSTA_DLLLA; } +static enum dw_pcie_ltssm qcom_pcie_get_ltssm(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + u32 val; + + val = readl(pcie->parf + PARF_LTSSM); + return (enum dw_pcie_ltssm)FIELD_GET(PARF_LTSSM_STATE_MASK, val); +} + static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) { struct qcom_pcie_port *port; @@ -1527,6 +1537,7 @@ static const struct qcom_pcie_cfg cfg_fw_managed = { static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, + .get_ltssm = qcom_pcie_get_ltssm, }; static int qcom_pcie_icc_init(struct qcom_pcie *pcie) From a036967fd700dc8c2d822c8880a5d27abc36f014 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 28 Nov 2025 16:02:40 +0530 Subject: [PATCH 0281/1330] FROMLIST: remoteproc: qcom: Fix NULL pointer issue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is a scenario, when fatal interrupt triggers rproc crash handling while a user-space recovery is initiated in parallel. The overlapping recovery/stop sequences race on rproc state and subdevice teardown, resulting in a NULL pointer dereference in the GLINK SMEM unregister path. Process-A Process-B fatal error interrupt happens rproc_crash_handler_work() mutex_lock_interruptible(&rproc->lock); ... rproc->state = RPROC_CRASHED; ... mutex_unlock(&rproc->lock); rproc_trigger_recovery() mutex_lock_interruptible(&rproc->lock); qcom_pas_stop() qcom_q6v5_pas 20c00000.remoteproc: failed to shutdown: -22 remoteproc remoteproc3: can't stop rproc: -22 mutex_unlock(&rproc->lock); echo enabled > /sys/class/remoteproc/remoteprocX/recovery recovery_store() rproc_trigger_recovery() mutex_lock_interruptible(&rproc->lock); rproc_stop() glink_subdev_stop() qcom_glink_smem_unregister() ==| | V Unable to handle kernel NULL pointer dereference at virtual address 0000000000000358 It is tempting to introduce a remoteproc state that could be set from the ->ops->stop() callback, which would have avoided the second attempt and prevented the crash. However, making remoteproc recovery dependent on manual intervention or a system reboot is not ideal. We should always try to recover the remote processor if possible. A failure in the ->ops->stop() callback might be temporary or caused by a timeout, and a recovery attempt could still succeed, as seen in similar scenarios. Therefore, instead of adding a restrictive state, let’s add a NULL check at the appropriate places to avoid a kernel crash and allow the system to move forward gracefully. Link: https://lore.kernel.org/r/20251128103240.1723386-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Mukesh Ojha Reviewed-by: Bryan O'Donoghue --- drivers/remoteproc/qcom_common.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/remoteproc/qcom_common.c b/drivers/remoteproc/qcom_common.c index 6c31140268acb..7b558d6ac644e 100644 --- a/drivers/remoteproc/qcom_common.c +++ b/drivers/remoteproc/qcom_common.c @@ -209,6 +209,9 @@ static void glink_subdev_stop(struct rproc_subdev *subdev, bool crashed) { struct qcom_rproc_glink *glink = to_glink_subdev(subdev); + if (!glink->edge) + return; + qcom_glink_smem_unregister(glink->edge); glink->edge = NULL; } @@ -320,6 +323,9 @@ static void smd_subdev_stop(struct rproc_subdev *subdev, bool crashed) { struct qcom_rproc_subdev *smd = to_smd_subdev(subdev); + if (!smd->edge) + return; + qcom_smd_unregister_edge(smd->edge); smd->edge = NULL; } From c32a4946bd2d3613e007999713d8702d81392708 Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Tue, 23 Dec 2025 18:02:21 +0530 Subject: [PATCH 0282/1330] FROMLIST: remoteproc: qcom: probe all child devices Generalise the qcom,bam-dmux child node support by probing all remoteproc children with of_platform_populate(). This will be used to enable support for devices which are best represented as subnodes of the remoteproc, such as those representing QMI clients. Signed-off-by: Casey Connolly Link: https://lore.kernel.org/r/20251223123227.1317244-3-gaurav.kohli@oss.qualcomm.com --- drivers/remoteproc/qcom_q6v5.c | 4 ++++ drivers/remoteproc/qcom_q6v5_mss.c | 8 -------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index 58d5b85e58cda..a02839c7ed8c2 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -6,6 +6,7 @@ * Copyright (C) 2014 Sony Mobile Communications AB * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -351,6 +352,8 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev, return dev_err_probe(&pdev->dev, PTR_ERR(q6v5->path), "failed to acquire interconnect path\n"); + of_platform_populate(q6v5->dev->of_node, NULL, NULL, q6v5->dev); + return 0; } EXPORT_SYMBOL_GPL(qcom_q6v5_init); @@ -361,6 +364,7 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_init); */ void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5) { + of_platform_depopulate(q6v5->dev); qmp_put(q6v5->qmp); } EXPORT_SYMBOL_GPL(qcom_q6v5_deinit); diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index 91940977ca898..d40565c1cc623 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -238,7 +238,6 @@ struct q6v5 { struct qcom_rproc_pdm pdm_subdev; struct qcom_rproc_ssr ssr_subdev; struct qcom_sysmon *sysmon; - struct platform_device *bam_dmux; bool need_mem_protection; bool has_alt_reset; bool has_mba_logs; @@ -2029,7 +2028,6 @@ static int q6v5_alloc_memory_region(struct q6v5 *qproc) static int q6v5_probe(struct platform_device *pdev) { const struct rproc_hexagon_res *desc; - struct device_node *node; struct q6v5 *qproc; struct rproc *rproc; const char *mba_image; @@ -2163,10 +2161,6 @@ static int q6v5_probe(struct platform_device *pdev) if (ret) goto remove_sysmon_subdev; - node = of_get_compatible_child(pdev->dev.of_node, "qcom,bam-dmux"); - qproc->bam_dmux = of_platform_device_create(node, NULL, &pdev->dev); - of_node_put(node); - return 0; remove_sysmon_subdev: @@ -2186,8 +2180,6 @@ static void q6v5_remove(struct platform_device *pdev) struct q6v5 *qproc = platform_get_drvdata(pdev); struct rproc *rproc = qproc->rproc; - if (qproc->bam_dmux) - of_platform_device_destroy(&qproc->bam_dmux->dev, NULL); rproc_del(rproc); qcom_q6v5_deinit(&qproc->q6v5); From d817983704d7f82d75bee9ea2c0ee2c971a2c4ee Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Wed, 4 Mar 2026 22:29:25 +0530 Subject: [PATCH 0283/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Add IFP Mezzanine The Interface Plus [IFP] Mezzanine is an hardware expansion add-on board designed to be stacked on top of Lemans EVK. It has following peripherals : - 4x Type A USB ports in host mode. - TC9563 PCIe switch, which has following three downstream ports (DSP) : - 1st DSP is routed to an M.2 E-key connector, intended for WLAN modules. - 2nd DSP is routed to an M.2 B-key connector, intended for cellular modems. - 3rd DSP with support for Dual Ethernet ports. - eMMC. - Additional 2.5GbE Ethernet PHY connected to native EMAC with support for MAC Address configuration via NVMEM. - EEPROM. - LVDS Display. - 2*mini DP. Add support for following peripherals : - TC9563 PCIe Switch. - Additional 2.5GbE Ethernet Port. - EEPROM. Enable support for USB hub, LVDS display and mini-DP later once dependent changes are available in lemans-evk core-kit. Written with inputs from : Mohd Ayaan Anwar - Ethernet. Krishna Chaitanya Chundru - PCIe Monish Chunara - EEPROM. Link: https://lore.kernel.org/r/20260304165925.1535938-2-umang.chheda@oss.qualcomm.com Signed-off-by: Umang Chheda Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 263 ++++++++++++++++++ 2 files changed, 267 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 530db9f71be06..db4952600c2d8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -43,6 +43,10 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb + +lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso new file mode 100644 index 0000000000000..268fc6b05d4b4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine"; + + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +ðernet1 { + phy-handle = <&hsgmii_phy1>; + phy-mode = "2500base-x"; + + pinctrl-0 = <ðernet1_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + + nvmem-cells = <&mac_addr1>; + nvmem-cell-names = "mac-address"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy1: ethernet-phy@18 { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x18>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&i2c18 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@52 { + compatible = "giantec,gt24c256c", "atmel,24c256"; + reg = <0x52>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_addr1: mac-addr@0 { + reg = <0x0 0x6>; + }; + }; + }; +}; + +&pcie0 { + iommu-map = <0x0 &pcie_smmu 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x1>, + <0x208 &pcie_smmu 0x2 0x1>, + <0x210 &pcie_smmu 0x3 0x1>, + <0x218 &pcie_smmu 0x4 0x1>, + <0x300 &pcie_smmu 0x5 0x1>, + <0x400 &pcie_smmu 0x6 0x1>, + <0x500 &pcie_smmu 0x7 0x1>, + <0x501 &pcie_smmu 0x8 0x1>; +}; + +&pcieport0 { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c18 0x77>; + + resx-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&serdes1 { + phy-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&tlmm { + ethernet1_default: ethernet1-default-state { + ethernet1-mdc-pins { + pins = "gpio20"; + function = "emac1_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet1-mdio-pins { + pins = "gpio21"; + function = "emac1_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + tc9563_resx_n: tc9563-resx-state { + pins = "gpio140"; + function = "gpio"; + bias-disable; + /* Reset pin of tc9563 is active low hence set default + * state of this pin to output-high. + */ + output-high; + }; +}; From 7aad4581229bcea9f0df2bd8376e60c58538586a Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Wed, 11 Feb 2026 13:49:19 +0530 Subject: [PATCH 0284/1330] PENDING: arm64: dts: qcom: Add EL2 support for Iris for lemans Add support for IRIS on lemans when Linux host running at EL2. Signed-off-by: Vikash Garodia --- arch/arm64/boot/dts/qcom/lemans-el2.dtso | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-el2.dtso b/arch/arm64/boot/dts/qcom/lemans-el2.dtso index 621ad930cf547..3efbdda9348b3 100644 --- a/arch/arm64/boot/dts/qcom/lemans-el2.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-el2.dtso @@ -15,7 +15,9 @@ }; &iris { - status = "disabled"; + video-firmware { + iommus = <&apps_smmu 0x0882 0x0400>; + }; }; &remoteproc_adsp { From 6564b59190e39150757ce07a67320c5cf9599c0a Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Thu, 26 Feb 2026 11:38:33 +0530 Subject: [PATCH 0285/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Enable GPIO expander interrupt for Lemans EVK Enable PCA9538 expander as interrupt controller on Lemans EVK and configure the corresponding TLMM pins via pinctrl to operate as GPIO inputs with internal pull-ups. Link: https://lore.kernel.org/r/20260226060835.608239-2-swati.agarwal@oss.qualcomm.com Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 44 +++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index ab4f50ac7e5e7..76d83ad5a57ab 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -652,6 +652,11 @@ reg = <0x38>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 138 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander0_int>; + pinctrl-names = "default"; }; expander1: gpio@39 { @@ -659,6 +664,11 @@ reg = <0x39>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 19 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander1_int>; + pinctrl-names = "default"; }; expander2: gpio@3a { @@ -666,6 +676,11 @@ reg = <0x3a>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 139 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander2_int>; + pinctrl-names = "default"; }; expander3: gpio@3b { @@ -673,6 +688,11 @@ reg = <0x3b>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander3_int>; + pinctrl-names = "default"; }; eeprom@50 { @@ -919,6 +939,30 @@ }; }; + expander0_int: expander0-int-state { + pins = "gpio138"; + function = "gpio"; + bias-pull-up; + }; + + expander1_int: expander1-int-state { + pins = "gpio19"; + function = "gpio"; + bias-pull-up; + }; + + expander2_int: expander2-int-state { + pins = "gpio139"; + function = "gpio"; + bias-pull-up; + }; + + expander3_int: expander3-int-state { + pins = "gpio39"; + function = "gpio"; + bias-pull-up; + }; + pcie0_default_state: pcie0-default-state { clkreq-pins { pins = "gpio1"; From 148eb7bc91874a8a203b9741a46407df857b577e Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Thu, 26 Feb 2026 11:38:34 +0530 Subject: [PATCH 0286/1330] FROMLIST: arm64: dts: qcom: lemans: Add role-switch support and HS endpoint for tertiary USB controller Enable usb-role-switch for the tertiary USB controller on Lemans. Additionally, add a port node with an HS endpoint so the controller can be linked through the DT graph to the corresponding connector. Link: https://lore.kernel.org/r/20260226060835.608239-3-swati.agarwal@oss.qualcomm.com Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/lemans.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 588c9b69748a5..f79405d1fea17 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4279,7 +4279,14 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; + usb-role-switch; + status = "disabled"; + + port { + usb_2_dwc3_hs: endpoint { + }; + }; }; tcsr_mutex: hwlock@1f40000 { From b0caeb902ee09c2ec69c29db0ae9bdf73b9fec5c Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Thu, 26 Feb 2026 11:38:35 +0530 Subject: [PATCH 0287/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Enable the tertiary USB controller Enable the tertiary usb controller connected to micro usb port in OTG mode on Lemans EVK platform. Link: https://lore.kernel.org/r/20260226060835.608239-4-swati.agarwal@oss.qualcomm.com Reviewed-by: Konrad Dybcio Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 52 +++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 76d83ad5a57ab..733acc8502d0f 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -108,6 +108,25 @@ }; }; + connector-2 { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + + id-gpios = <&pmm8654au_2_gpios 11 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&expander3 3 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb2_vbus>; + + pinctrl-0 = <&usb2_id>; + pinctrl-names = "default"; + + port { + usb2_con_hs_ep: endpoint { + remote-endpoint = <&usb_2_dwc3_hs>; + }; + }; + }; + edp0-connector { compatible = "dp-connector"; label = "EDP0"; @@ -172,6 +191,15 @@ }; }; + usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&pmm8654au_1_gpios 9 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + vbus_supply_regulator_0: regulator-vbus-supply-0 { compatible = "regulator-fixed"; regulator-name = "vbus_supply_0"; @@ -833,6 +861,14 @@ bias-pull-up; power-source = <0>; }; + + usb2_id: usb2-id-state { + pins = "gpio11"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; }; &qup_i2c19_default { @@ -1217,6 +1253,22 @@ status = "okay"; }; +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3_hs { + remote-endpoint = <&usb2_con_hs_ep>; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; From 6cd5b86766b4f43caeb46ba5b0b20b91398d1f34 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Mon, 16 Feb 2026 00:23:43 +0530 Subject: [PATCH 0288/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Enable wakeup for primary USB controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the "wakeup-source" property to the primary port controller node so its interrupt can wake the system from low‑power states on lemans EVK platform. Link: https://lore.kernel.org/all/20260215183325.3836178-3-swati.agarwal@oss.qualcomm.com/ Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 733acc8502d0f..7f379d9b82d78 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -616,6 +616,8 @@ pinctrl-0 = <&usb_id>, <&usb0_intr_state>; pinctrl-names = "default"; + wakeup-source; + ports { #address-cells = <1>; #size-cells = <0>; From 1ee5f5edc75c7db429c4f8574c8009d106c48b43 Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Tue, 17 Feb 2026 12:44:19 +0530 Subject: [PATCH 0289/1330] FROMLIST: arm64: dts: qcom: lemans: add mdss1 display device nodes Add devicetree changes to enable second Mobile Display Subsystem (mdss1), Display Processing Unit(DPU), Display Port(DP) controllers and eDP PHYs on the Qualcomm Lemans platform. Signed-off-by: Mahadevan P Signed-off-by: Mani Chandana Ballary Kuntumalla Link: https://lore.kernel.org/all/20260217071420.2240380-2-mkuntuma@qti.qualcomm.com/ Signed-off-by: Yash Gupta --- arch/arm64/boot/dts/qcom/lemans.dtsi | 315 ++++++++++++++++++++++++++- 1 file changed, 313 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index f79405d1fea17..96989086f0e9f 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -7064,6 +7064,317 @@ }; }; + mdss1: display-subsystem@22000000 { + compatible = "qcom,sa8775p-mdss"; + reg = <0x0 0x22000000 0x0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1800 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + display-controller@22001000 { + compatible = "qcom,sa8775p-dpu"; + reg = <0x0 0x22001000 0x0 0x8f000>, + <0x0 0x220b0000 0x0 0x3000>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdss1_mdp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + interrupt-parent = <&mdss1>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu1_intf0_out: endpoint { + remote-endpoint = <&mdss1_dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu1_intf4_out: endpoint { + remote-endpoint = <&mdss1_dp1_in>; + }; + }; + }; + + mdss1_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss1_dp0_phy: phy@220c2a00 { + compatible = "qcom,sa8775p-edp-phy"; + + reg = <0x0 0x220c2a00 0x0 0x200>, + <0x0 0x220c2200 0x0 0xd0>, + <0x0 0x220c2600 0x0 0xd0>, + <0x0 0x220c2000 0x0 0x1c8>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp1_phy: phy@220c5a00 { + compatible = "qcom,sa8775p-edp-phy"; + + reg = <0x0 0x220c5a00 0x0 0x200>, + <0x0 0x220c5200 0x0 0xd0>, + <0x0 0x220c5600 0x0 0xd0>, + <0x0 0x220c5000 0x0 0x1c8>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp0: displayport-controller@22154000 { + compatible = "qcom,sa8775p-dp"; + + reg = <0x0 0x22154000 0x0 0x104>, + <0x0 0x22154200 0x0 0x0c0>, + <0x0 0x22155000 0x0 0x770>, + <0x0 0x22156000 0x0 0x09c>, + <0x0 0x22157000 0x0 0x09c>, + <0x0 0x22158000 0x0 0x09c>, + <0x0 0x22159000 0x0 0x09c>, + <0x0 0x2215a000 0x0 0x23c>, + <0x0 0x2215b000 0x0 0x23c>; + + interrupt-parent = <&mdss1>; + interrupts = <12>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>; + phys = <&mdss1_dp0_phy>; + phy-names = "dp"; + + operating-points-v2 = <&mdss1_dp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss1_dp0_in: endpoint { + remote-endpoint = <&dpu1_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss1_dp0_out: endpoint { }; + }; + }; + + mdss1_dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss1_dp1: displayport-controller@2215c000 { + compatible = "qcom,sa8775p-dp"; + + reg = <0x0 0x2215c000 0x0 0x104>, + <0x0 0x2215c200 0x0 0x0c0>, + <0x0 0x2215d000 0x0 0x770>, + <0x0 0x2215e000 0x0 0x09c>, + <0x0 0x2215f000 0x0 0x09c>, + <0x0 0x22160000 0x0 0x09c>, + <0x0 0x22161000 0x0 0x09c>, + <0x0 0x22162000 0x0 0x23c>, + <0x0 0x22163000 0x0 0x23c>; + + interrupt-parent = <&mdss1>; + interrupts = <13>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp1_phy 1>; + phys = <&mdss1_dp1_phy>; + phy-names = "dp"; + + operating-points-v2 = <&mdss1_dp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss1_dp1_in: endpoint { + remote-endpoint = <&dpu1_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss1_dp1_out: endpoint { }; + }; + }; + + }; + }; + dispcc1: clock-controller@22100000 { compatible = "qcom,sa8775p-dispcc1"; reg = <0x0 0x22100000 0x0 0x20000>; @@ -7071,13 +7382,13 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>, + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd SA8775P_MMCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; ethernet1: ethernet@23000000 { From 94c1cc98aef928cb79ca2394b20b89e988bcebd2 Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Tue, 17 Feb 2026 12:44:20 +0530 Subject: [PATCH 0290/1330] FROMLIST: arm64: dts: qcom: lemans-ride: Enable mdss1 display Port This change enables DP controllers, DPTX0 and DPTX1 alongside their corresponding PHYs of mdss1 which corresponds to edp2 and edp3. Signed-off-by: Mani Chandana Ballary Kuntumalla Link: https://lore.kernel.org/all/20260217071420.2240380-3-mkuntuma@qti.qualcomm.com/ Signed-off-by: Yash Gupta --- .../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 73 +++++++++++++++++ .../boot/dts/qcom/lemans-ride-common.dtsi | 80 +++++++++++++++++++ 2 files changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 268fc6b05d4b4..39001ce99c023 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -11,6 +11,30 @@ &{/} { model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine"; + dp2-connector { + compatible = "dp-connector"; + label = "eDP2"; + type = "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "eDP3"; + type = "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_out>; + }; + }; + }; + vreg_0p9: regulator-0v9 { compatible = "regulator-fixed"; regulator-name = "VREG_0P9"; @@ -141,6 +165,43 @@ }; }; + +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 = <&dp2_hot_plug_det>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 = <&dp3_hot_plug_det>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdss1_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp2_connector_in>; +}; + +&mdss1_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp3_connector_in>; +}; + +&mdss1_dp0_phy { + status = "okay"; +}; + +&mdss1_dp1_phy { + status = "okay"; +}; + &pcie0 { iommu-map = <0x0 &pcie_smmu 0x0 0x1>, <0x100 &pcie_smmu 0x1 0x1>, @@ -235,6 +296,18 @@ }; &tlmm { + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins = "gpio104"; + function = "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins = "gpio103"; + function = "edp3_hot"; + bias-disable; + }; + ethernet1_default: ethernet1-default-state { ethernet1-mdc-pins { pins = "gpio20"; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index e020cc85089d3..c72a01fdc75de 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -180,6 +180,30 @@ }; }; + dp2-connector { + compatible = "dp-connector"; + label = "eDP2"; + type = "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "eDP3"; + type = "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_out>; + }; + }; + }; + dp-dsi0-connector { compatible = "dp-connector"; label = "DSI0"; @@ -639,6 +663,50 @@ status = "okay"; }; +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 = <&dp2_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp2_connector_in>; +}; + +&mdss1_dp0_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 = <&dp3_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp3_connector_in>; +}; + +&mdss1_dp1_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + &pmm8654au_0_gpios { gpio-line-names = "DS_EN", "POFF_COMPLETE", @@ -820,6 +888,18 @@ bias-disable; }; + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins = "gpio104"; + function = "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins = "gpio103"; + function = "edp3_hot"; + bias-disable; + }; + io_expander_intr_active: io-expander-intr-active-state { pins = "gpio98"; function = "gpio"; From eb1a9c25d2c60e24eabf9167450e717c8c517960 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 3 Mar 2026 22:13:14 +0530 Subject: [PATCH 0291/1330] FROMLIST: arm64: dts: qcom: monaco-evk: Add IFP Mezzanine The IFP Mezzanine is an hardware expansion add-on board designed to be stacked on top of Monaco EVK. It has following peripherals : - 4x Type A USB ports in host mode. - TC9563 PCIe switch, which has following three downstream ports (DSP) : - 1st DSP is routed to an M.2 E-Key connector, intended for WLAN modules. - 2nd DSP is routed to an M.2 B-key connector, intended for cellular modems. - 3rd DSP with support for Dual Ethernet ports. - EEPROM. - LVDS Display. - 2*mini DP. Add support for following peripherals : - TC9563 PCIe Switch. - EEPROM. Enable support for USB hub, LVDS display and mini-DP later once dependent changes are available in monaco-evk core-kit. Written with inputs from : Krishna Chaitanya Chundru - PCIe Monish Chunara - EEPROM. Link: https://lore.kernel.org/r/20260303164314.886733-2-umang.chheda@oss.qualcomm.com Signed-off-by: Umang Chheda Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 3 + .../dts/qcom/monaco-evk-ifp-mezzanine.dtso | 149 ++++++++++++++++++ 2 files changed, 152 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index db4952600c2d8..db3f80d7c6b49 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -57,6 +57,9 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-el2.dtb monaco-evk-camera-imx577-dtbs := monaco-evk.dtb monaco-evk-camera-imx577.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb +monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso new file mode 100644 index 0000000000000..e6beb4393430b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + model = "Qualcomm Technologies, Inc. Monaco-EVK IFP Mezzanine"; + + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c15 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom1: eeprom@52 { + compatible = "giantec,gt24c256c", "atmel,24c256"; + reg = <0x52>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&pcie0 { + iommu-map = <0x0 &pcie_smmu 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x1>, + <0x208 &pcie_smmu 0x2 0x1>, + <0x210 &pcie_smmu 0x3 0x1>, + <0x218 &pcie_smmu 0x4 0x1>, + <0x300 &pcie_smmu 0x5 0x1>, + <0x400 &pcie_smmu 0x6 0x1>, + <0x500 &pcie_smmu 0x7 0x1>, + <0x501 &pcie_smmu 0x8 0x1>; +}; + +&pcieport0 { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c15 0x77>; + + resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&tlmm { + tc9563_resx_n: tc9563-resx-state { + pins = "gpio124"; + function = "gpio"; + bias-disable; + /* Reset pin of tc9563 is active low hence set default + * state of this pin to output-high. + */ + output-high; + }; +}; From 23790a78b081821c13ebfb2eb6d08a8d1a4ab6df Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Thu, 12 Feb 2026 10:27:38 +0530 Subject: [PATCH 0292/1330] FROMLIST: arm64: dts: qcom: monaco-evk: Enable GPIO expander interrupt for Monaco EVK Enable PCA9538 expander as interrupt controller on Monaco EVK and configure the corresponding TLMM pins via pinctrl to operate as GPIO inputs with internal pull-ups. Link: https://lore.kernel.org/all/20260210155329.3044455-2-swati.agarwal@oss.qualcomm.com/ Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 77 +++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index acf2e7c36f143..006c8b8cb5876 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -456,6 +456,11 @@ reg = <0x38>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 56 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander0_int>; + pinctrl-names = "default"; }; expander1: gpio@39 { @@ -463,6 +468,11 @@ reg = <0x39>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander1_int>; + pinctrl-names = "default"; }; expander2: gpio@3a { @@ -470,6 +480,11 @@ reg = <0x3a>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 95 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander2_int>; + pinctrl-names = "default"; }; expander3: gpio@3b { @@ -477,6 +492,11 @@ reg = <0x3b>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander3_int>; + pinctrl-names = "default"; }; expander4: gpio@3c { @@ -484,6 +504,11 @@ reg = <0x3c>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 96 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander4_int>; + pinctrl-names = "default"; }; expander5: gpio@3d { @@ -491,6 +516,11 @@ reg = <0x3d>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander5_int>; + pinctrl-names = "default"; }; expander6: gpio@3e { @@ -498,6 +528,11 @@ reg = <0x3e>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 52 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander6_int>; + pinctrl-names = "default"; }; }; @@ -619,6 +654,48 @@ &tlmm { + expander0_int: expander0-int-state { + pins = "gpio56"; + function = "gpio"; + bias-pull-up; + }; + + expander1_int: expander1-int-state { + pins = "gpio16"; + function = "gpio"; + bias-pull-up; + }; + + expander2_int: expander2-int-state { + pins = "gpio95"; + function = "gpio"; + bias-pull-up; + }; + + expander3_int: expander3-int-state { + pins = "gpio24"; + function = "gpio"; + bias-pull-up; + }; + + expander4_int: expander4-int-state { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; + }; + + expander5_int: expander5-int-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + expander6_int: expander6-int-state { + pins = "gpio52"; + function = "gpio"; + bias-pull-up; + }; + pcie0_default_state: pcie0-default-state { wake-pins { pins = "gpio0"; From 1eb2b3839f60220ed6e86f03930a5f02bc9d0350 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Thu, 12 Feb 2026 10:32:48 +0530 Subject: [PATCH 0293/1330] FROMLIST: arm64: dts: qcom: monaco-evk: Enable the tertiary USB controller Enable the tertiary usb controller connected to micro usb port in OTG mode on Monaco EVK platform. Link: https://lore.kernel.org/all/20260210155329.3044455-3-swati.agarwal@oss.qualcomm.com/ Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 53 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/monaco.dtsi | 7 ++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 006c8b8cb5876..8940b0ff66bfa 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -28,6 +28,25 @@ stdout-path = "serial0:115200n8"; }; + connector-2 { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + + id-gpios = <&pmm8620au_0_gpios 9 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&expander6 7 GPIO_ACTIVE_HIGH>; + vbus-supply = <&vbus_supply_regulator_2>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_id>; + + port { + usb2_con_hs_ep: endpoint { + remote-endpoint = <&usb_2_dwc3_hs>; + }; + }; + }; + dmic: audio-codec-0 { compatible = "dmic-codec"; #sound-dai-cells = <0>; @@ -103,6 +122,15 @@ }; }; + vbus_supply_regulator_2: vbus-supply-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "vbus_supply_2"; + gpio = <&pmm8650au_1_gpios 7 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + vreg_cam1_2p8: vreg-cam1-2p8 { compatible = "regulator-fixed"; regulator-name = "vreg_cam1_2p8"; @@ -602,6 +630,16 @@ wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; }; +&pmm8620au_0_gpios { + usb2_id: usb2-id-state { + pins = "gpio9"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + &qup_i2c0_data_clk { drive-strength = <2>; bias-pull-up; @@ -832,3 +870,18 @@ status = "okay"; }; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3_hs { + remote-endpoint = <&usb2_con_hs_ep>; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 97eb3ea6eed40..1ec22116735ae 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5245,7 +5245,14 @@ qcom,select-utmi-as-pipe-clk; wakeup-source; + usb-role-switch; + status = "disabled"; + + port { + usb_2_dwc3_hs: endpoint { + }; + }; }; iris: video-codec@aa00000 { From b1deb11387de7de159b091c2b2c19845411f0f61 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 27 Jan 2026 12:35:52 +0530 Subject: [PATCH 0294/1330] BACKPORT: arm64: dts: qcom: monaco-evk: Enable primary USB controller in host mode Enable primary USB controller in host mode on monaco EVK Platform. Primary USB controller is connected to a Genesys Logic USB HUB GL3590 having 4 ports. The ports of hub that are present on lemans EVK standalone board are used as follows:- 1) port-1 is connected to HD3SS3220 Type-C port controller. 2) port-4 is used for the M.2 E key on corekit. Standard core kit uses UART for Bluetooth. This port is to be used only if user optionally replaces the WiFi card with the NFA765 chip which uses USB for Bluetooth. Remaining 2 ports will become functional when the interface plus mezzanine board is stacked on top of corekit: 3) port-2 is connected to another hub which is present on the mezz through which 4 type-A ports are connected. 4) port-3 is used for the M.2 B key for a 5G card when the mezz is connected. Mark the second USB controller as host only capable and add the HD3SS3220 Type-C port controller along with Type-c connector for controlling vbus supply. In hardware, there are dip switches provided to operate between USB port 0 and port 1 for primary Type-C USB controller. By default, switches will be off operating at USB0 port. After bootup to HLOS, it will be operated in USB1 port. Added support in the software for both HS and SS switches as usb1-hs-high-gpio14 and usb1-ss-high-gpio5. Also, added bootup-high-gpio7 pin for USB1 hub reset to get detected after bootup. Link: https://lore.kernel.org/all/20260210152548.769951-1-loic.poulain@oss.qualcomm.com/ Signed-off-by: Loic Poulain Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 203 +++++++++++++++++++++++- 1 file changed, 201 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 8940b0ff66bfa..5248086304419 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -28,6 +28,45 @@ stdout-path = "serial0:115200n8"; }; + connector-1 { + compatible = "usb-c-connector"; + label = "USB1-Type-C"; + data-role = "host"; + power-role = "source"; + + vbus-supply = <&vbus_supply_regulator_1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_con_ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_1_in_ep>; + }; + }; + + port@1 { + reg = <1>; + + usb1_hs_in: endpoint { + remote-endpoint = <&usb_hub_2_1>; + }; + + }; + + port@2 { + reg = <2>; + + usb1_ss_in: endpoint { + remote-endpoint = <&usb_hub_3_1>; + }; + }; + }; + }; + connector-2 { compatible = "gpio-usb-b-connector", "usb-b-connector"; label = "micro-USB"; @@ -122,7 +161,16 @@ }; }; - vbus_supply_regulator_2: vbus-supply-regulator-2 { + vbus_supply_regulator_1: regulator-vbus-supply-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus_supply_1"; + gpio = <&expander1 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vbus_supply_regulator_2: regulator-vbus-supply-2 { compatible = "regulator-fixed"; regulator-name = "vbus_supply_2"; gpio = <&pmm8650au_1_gpios 7 GPIO_ACTIVE_HIGH>; @@ -438,6 +486,38 @@ }; }; }; + + usb-typec@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + + interrupts = <45 IRQ_TYPE_EDGE_FALLING>; + + id-gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb1_id>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_1_in_ep: endpoint { + remote-endpoint = <&usb1_con_ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_1_out_ep: endpoint { + }; + }; + }; + }; }; &i2c1 { @@ -549,6 +629,13 @@ interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&expander5_int>; pinctrl-names = "default"; + + gpio5-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb1-ss-high-gpio5"; + }; }; expander6: gpio@3e { @@ -561,6 +648,7 @@ interrupts-extended = <&tlmm 52 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&expander6_int>; pinctrl-names = "default"; + wakeup-source; }; }; @@ -734,6 +822,20 @@ bias-pull-up; }; + gpio7_hog: gpio7-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bootup-high-gpio7"; + }; + + gpio14_hog: gpio14-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb1-hs-high-gpio14"; + }; + pcie0_default_state: pcie0-default-state { wake-pins { pins = "gpio0"; @@ -809,6 +911,12 @@ drive-strength = <2>; bias-pull-up; }; + + usb1_id: usb1-id-state { + pins = "gpio13"; + function = "gpio"; + bias-pull-up; + }; }; &uart2 { @@ -851,9 +959,100 @@ }; &usb_1 { - dr_mode = "peripheral"; + dr_mode = "host"; + + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + usb_hub_2_x: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + + peer-hub = <&usb_hub_3_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_2_1: endpoint { + remote-endpoint = <&usb1_hs_in>; + }; + }; + + /* + * Port-2 and port-3 are not connected to anything on corekit. + */ + port@2 { + reg = <2>; + + usb_hub_2_2: endpoint { + }; + }; + + port@3 { + reg = <3>; + + usb_hub_2_3: endpoint { + }; + }; + + /* + * Port-4 is connected to M.2 E key connector on corekit. + */ + port@4 { + reg = <4>; + + usb_hub_2_4: endpoint { + }; + }; + }; + }; + + usb_hub_3_x: hub@2 { + compatible = "usb5e3,625"; + reg = <2>; + + peer-hub = <&usb_hub_2_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_3_1: endpoint { + remote-endpoint = <&usb1_ss_in>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_3_2: endpoint { + }; + }; + + port@3 { + reg = <3>; + + usb_hub_3_3: endpoint { + }; + }; + + port@4 { + reg = <4>; + + usb_hub_3_4: endpoint { + }; + }; + }; + }; }; &usb_1_hsphy { From 556527609ddd6a6b2a647195bbae9bf9fd29585c Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 5 Mar 2026 16:04:23 +0530 Subject: [PATCH 0295/1330] WORKAROUND: soc: qcom: smem_dramc: Fix v3 DDR freq table out-of-bounds Some SMEM v3 DDR details blobs contain 14 frequency entries, while the parser assumes MAX_DDR_FREQ_NUM_V3. This can lead to out-of-bounds reads and hangs during smem_dram_parse(). Handle the 14-entry v3 layout explicitly and parse it with the correct bounds based on the SMEM item size. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/smem_dramc.c | 45 +++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/drivers/soc/qcom/smem_dramc.c b/drivers/soc/qcom/smem_dramc.c index 017bb894a91b6..dc2cd7e13b88e 100644 --- a/drivers/soc/qcom/smem_dramc.c +++ b/drivers/soc/qcom/smem_dramc.c @@ -78,7 +78,7 @@ struct ddr_freq_table { /* V3 */ struct ddr_freq_plan_v3 { - struct ddr_freq_table ddr_freq[MAX_DDR_FREQ_NUM_V3]; /* NOTE: some have 14 like v5 */ + struct ddr_freq_table ddr_freq[MAX_DDR_FREQ_NUM_V3]; u8 num_ddr_freqs; phys_addr_t clk_period_address; }; @@ -91,6 +91,21 @@ struct ddr_details_v3 { u8 num_channels; }; +/* Some V3 structs have an additional frequency level */ +struct ddr_freq_plan_v3_14freqs { + struct ddr_freq_table ddr_freq[MAX_DDR_FREQ_NUM_V3 + 1]; + u8 num_ddr_freqs; + phys_addr_t clk_period_address; +}; + +struct ddr_details_v3_14freqs { + u8 manufacturer_id; + u8 device_type; + struct ddr_part_details ddr_params[MAX_CHAN_NUM]; + struct ddr_freq_plan_v3_14freqs ddr_freq_tbl; + u8 num_channels; +}; + /* V4 */ struct ddr_details_v4 { u8 manufacturer_id; @@ -201,16 +216,11 @@ int qcom_smem_dram_get_hbb(void) } EXPORT_SYMBOL_GPL(qcom_smem_dram_get_hbb); -static void smem_dram_parse_v3_data(struct smem_dram *dram, void *data, bool additional_freq_entry) +static void smem_dram_parse_v3_data(struct smem_dram *dram, void *data) { - /* This may be 13 or 14 */ - int num_freq_entries = MAX_DDR_FREQ_NUM_V3; struct ddr_details_v3 *details = data; - if (additional_freq_entry) - num_freq_entries++; - - for (int i = 0; i < num_freq_entries; i++) { + for (int i = 0; i < MAX_DDR_FREQ_NUM_V3; i++) { struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i]; if (freq_entry->freq_khz && freq_entry->enabled) @@ -218,6 +228,18 @@ static void smem_dram_parse_v3_data(struct smem_dram *dram, void *data, bool add } } +static void smem_dram_parse_v3_14freqs_data(struct smem_dram *dram, void *data) +{ + struct ddr_details_v3_14freqs *details = data; + + for (int i = 0; i < MAX_DDR_FREQ_NUM_V3 + 1; i++) { + struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i]; + + if (freq_entry->freq_khz && freq_entry->enabled) + dram->frequencies[dram->num_frequencies++] = 1000 * freq_entry->freq_khz; + } +} + static void smem_dram_parse_v4_data(struct smem_dram *dram, void *data) { struct ddr_details_v4 *details = data; @@ -273,8 +295,7 @@ static int smem_dram_infer_struct_version(size_t size) if (size == sizeof(struct ddr_details_v3)) return INFO_V3; - if (size == sizeof(struct ddr_details_v3) - + sizeof(struct ddr_freq_table)) + if (size == sizeof(struct ddr_details_v3_14freqs)) return INFO_V3_WITH_14_FREQS; if (size == sizeof(struct ddr_details_v4)) @@ -374,10 +395,10 @@ struct dentry *smem_dram_parse(struct device *dev) switch (ver) { case INFO_V3: - smem_dram_parse_v3_data(dram, data, false); + smem_dram_parse_v3_data(dram, data); break; case INFO_V3_WITH_14_FREQS: - smem_dram_parse_v3_data(dram, data, true); + smem_dram_parse_v3_14freqs_data(dram, data); break; case INFO_V4: smem_dram_parse_v4_data(dram, data); From ea3747e1f2ba497fa40f7c589932ad557245c510 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Thu, 8 Jan 2026 18:21:59 +0530 Subject: [PATCH 0296/1330] FROMLIST: dt-bindings: can: microchip,mcp251xfd: allow gpio-hog child nodes The MCP251XFD can expose two pins as GPIOs. The binding already declares gpio-controller and #gpio-cells for the device. Whitelist GPIO hog child nodes using patternProperties so boards can set default GPIO states at boot via DT, consistent with other GPIO controllers (e.g. microchip,mpfs-gpio). Signed-off-by: Viken Dadhaniya Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20260108125200.2803112-2-viken.dadhaniya@oss.qualcomm.com/ --- .../devicetree/bindings/net/can/microchip,mcp251xfd.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml index 2d13638ebc6a6..49d6f6bbe1939 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml @@ -54,6 +54,12 @@ properties: "#gpio-cells": const: 2 +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + required: - compatible - reg From 127842518d7263ad6513679d5941e22b5ff6510c Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Thu, 8 Jan 2026 18:22:00 +0530 Subject: [PATCH 0297/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform. The controller is connected via SPI3 and uses a 40 MHz oscillator. A GPIO hog for GPIO0 is included to configure the CAN transceiver in Normal mode during boot. Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/all/20260108125200.2803112-3-viken.dadhaniya@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index d8b9b343cfa52..cdc3977daa5c4 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -44,6 +44,14 @@ stdout-path = "serial0:115200n8"; }; + clocks { + mcp2518fd_osc: can-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + dp-connector { compatible = "dp-connector"; label = "DP"; @@ -1156,6 +1164,28 @@ }; }; +&spi3 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mcp2518fd_osc>; + spi-max-frequency = <10000000>; + vdd-supply = <&vreg_l11c_2p8>; + gpio-controller; + #gpio-cells = <2>; + + gpio0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "mcp251xfd-gpio0"; + }; + }; +}; + &swr2 { status = "okay"; From 90e4ccd8fb5c6277c3bf546b516976d6a083dcb5 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Wed, 25 Feb 2026 13:11:57 +0530 Subject: [PATCH 0298/1330] FROMLIST: drm/msm/a6xx: Fix the bogus protect error on X2-85 Update the X2-85 gpu's register protect count configuration with the correct count_max value to avoid blocking the entire MMIO region from the UMD. Protect configurations are a bit complicated on A8xx. There are 2 set of protect registers with different counts: Global and Pipe-specific. The last-span-unbound feature is available only on the Pipe-specific protect registers. Due to this, we cannot use the BUILD_BUG sanity check for A8x protect configurations, so remove the A840 entry from there. Link: https://lore.kernel.org/lkml/20260225-glymur-protect-fix-v1-1-0deddedf9277@oss.qualcomm.com/ Fixes: 01ff3bf27215 ("drm/msm/a8xx: Add support for Adreno X2-85 GPU") Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio From 10f6c034f8b44cd566573615c7bba24a50ae32ff Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Tue, 27 Jan 2026 03:22:06 +0000 Subject: [PATCH 0299/1330] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm Mahua platform. Mahua is a derivative of the Glymur SoC. Many interconnect nodes are identical and continue to use Glymur fallback compatibles. Mahua introduces SoC-specific configurations and topologies for several NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs. This updates the existing Glymur yaml schema to include Mahua-specific compatible strings, using two-cell "fallback" compatibles wherever the hardware is identical with Glymur. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260127-mahua_icc-v2-1-f0d8ddf7afca@oss.qualcomm.com --- .../interconnect/qcom,glymur-rpmh.yaml | 132 +++++++++++++++--- 1 file changed, 109 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml index d55a7bcf5591e..723ae547ae060 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR +title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs maintainers: - Raviteja Laggyshetty @@ -21,28 +21,98 @@ description: | properties: compatible: - enum: - - qcom,glymur-aggre1-noc - - qcom,glymur-aggre2-noc - - qcom,glymur-aggre3-noc - - qcom,glymur-aggre4-noc - - qcom,glymur-clk-virt - - qcom,glymur-cnoc-cfg - - qcom,glymur-cnoc-main - - qcom,glymur-hscnoc - - qcom,glymur-lpass-ag-noc - - qcom,glymur-lpass-lpiaon-noc - - qcom,glymur-lpass-lpicx-noc - - qcom,glymur-mc-virt - - qcom,glymur-mmss-noc - - qcom,glymur-nsinoc - - qcom,glymur-nsp-noc - - qcom,glymur-oobm-ss-noc - - qcom,glymur-pcie-east-anoc - - qcom,glymur-pcie-east-slv-noc - - qcom,glymur-pcie-west-anoc - - qcom,glymur-pcie-west-slv-noc - - qcom,glymur-system-noc + oneOf: + - items: + - enum: + - qcom,mahua-clk-virt + - const: qcom,glymur-clk-virt + - items: + - enum: + - qcom,mahua-cnoc-main + - const: qcom,glymur-cnoc-main + - items: + - enum: + - qcom,mahua-system-noc + - const: qcom,glymur-system-noc + - items: + - enum: + - qcom,mahua-pcie-east-anoc + - const: qcom,glymur-pcie-east-anoc + - items: + - enum: + - qcom,mahua-aggre1-noc + - const: qcom,glymur-aggre1-noc + - items: + - enum: + - qcom,mahua-aggre2-noc + - const: qcom,glymur-aggre2-noc + - items: + - enum: + - qcom,mahua-aggre3-noc + - const: qcom,glymur-aggre3-noc + - items: + - enum: + - qcom,mahua-aggre4-noc + - const: qcom,glymur-aggre4-noc + - items: + - enum: + - qcom,mahua-mmss-noc + - const: qcom,glymur-mmss-noc + - items: + - enum: + - qcom,mahua-pcie-east-slv-noc + - const: qcom,glymur-pcie-east-slv-noc + - items: + - enum: + - qcom,mahua-lpass-lpiaon-noc + - const: qcom,glymur-lpass-lpiaon-noc + - items: + - enum: + - qcom,mahua-lpass-lpicx-noc + - const: qcom,glymur-lpass-lpicx-noc + - items: + - enum: + - qcom,mahua-lpass-ag-noc + - const: qcom,glymur-lpass-ag-noc + - items: + - enum: + - qcom,mahua-nsinoc + - const: qcom,glymur-nsinoc + - items: + - enum: + - qcom,mahua-oobm-ss-noc + - const: qcom,glymur-oobm-ss-noc + - items: + - enum: + - qcom,mahua-nsp-noc + - const: qcom,glymur-nsp-noc + - enum: + - qcom,glymur-aggre1-noc + - qcom,glymur-aggre2-noc + - qcom,glymur-aggre3-noc + - qcom,glymur-aggre4-noc + - qcom,glymur-clk-virt + - qcom,glymur-cnoc-cfg + - qcom,glymur-cnoc-main + - qcom,glymur-hscnoc + - qcom,glymur-lpass-ag-noc + - qcom,glymur-lpass-lpiaon-noc + - qcom,glymur-lpass-lpicx-noc + - qcom,glymur-mc-virt + - qcom,glymur-mmss-noc + - qcom,glymur-nsinoc + - qcom,glymur-nsp-noc + - qcom,glymur-oobm-ss-noc + - qcom,glymur-pcie-east-anoc + - qcom,glymur-pcie-east-slv-noc + - qcom,glymur-pcie-west-anoc + - qcom,glymur-pcie-west-slv-noc + - qcom,glymur-system-noc + - qcom,mahua-mc-virt + - qcom,mahua-cnoc-cfg + - qcom,mahua-pcie-west-anoc + - qcom,mahua-pcie-west-slv-noc + - qcom,mahua-hscnoc reg: maxItems: 1 @@ -63,6 +133,7 @@ allOf: enum: - qcom,glymur-clk-virt - qcom,glymur-mc-virt + - qcom,mahua-mc-virt then: properties: reg: false @@ -85,6 +156,20 @@ allOf: - description: aggre PCIE_4 WEST AXI clock - description: aggre PCIE_6 WEST AXI clock + - if: + properties: + compatible: + contains: + enum: + - qcom,mahua-pcie-west-anoc + then: + properties: + clocks: + items: + - description: aggre PCIE_3B WEST AXI clock + - description: aggre PCIE_4 WEST AXI clock + - description: aggre PCIE_6 WEST AXI clock + - if: properties: compatible: @@ -132,6 +217,7 @@ allOf: contains: enum: - qcom,glymur-pcie-west-anoc + - qcom,mahua-pcie-west-anoc - qcom,glymur-pcie-east-anoc - qcom,glymur-aggre2-noc - qcom,glymur-aggre4-noc From bcce8c2d12f7f9bdb6eace8008b8d086fe491c4d Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Tue, 27 Jan 2026 03:22:07 +0000 Subject: [PATCH 0300/1330] interconnect: qcom: glymur: Add Mahua SoC support Mahua is a derivative of the Glymur SoC. Extend the Glymur driver to support Mahua by: 1. Adding new node definitions for interconnects that differ from Glymur (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC). 2. Reusing existing Glymur definitions for identical NoCs. 3. Overriding the channel and buswidth, with Mahua specific values for the differing NoCs Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260127-mahua_icc-v2-2-f0d8ddf7afca@oss.qualcomm.com --- drivers/interconnect/qcom/glymur.c | 38 ++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom/glymur.c index e5c07795a6c67..cfe061c1a75a6 100644 --- a/drivers/interconnect/qcom/glymur.c +++ b/drivers/interconnect/qcom/glymur.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "bcm-voter.h" @@ -1985,7 +1986,7 @@ static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { &bcm_cn1, }; -static struct qcom_icc_node * const cnoc_cfg_nodes[] = { +static struct qcom_icc_node *cnoc_cfg_nodes[] = { [MASTER_CNOC_CFG] = &qsm_cfg, [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, @@ -2093,7 +2094,7 @@ static struct qcom_icc_bcm * const hscnoc_bcms[] = { &bcm_sh1, }; -static struct qcom_icc_node * const hscnoc_nodes[] = { +static struct qcom_icc_node *hscnoc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_PCIE_TCU] = &alm_pcie_qtc, [MASTER_SYS_TCU] = &alm_sys_tcu, @@ -2377,7 +2378,7 @@ static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = { &bcm_sn6, }; -static struct qcom_icc_node * const pcie_west_anoc_nodes[] = { +static struct qcom_icc_node *pcie_west_anoc_nodes[] = { [MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg, [MASTER_PCIE_2] = &xm_pcie_2, [MASTER_PCIE_3A] = &xm_pcie_3a, @@ -2409,7 +2410,7 @@ static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] = { &bcm_sn6, }; -static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] = { +static struct qcom_icc_node *pcie_west_slv_noc_nodes[] = { [MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west, [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg, [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg, @@ -2470,6 +2471,28 @@ static const struct qcom_icc_desc glymur_system_noc = { .num_bcms = ARRAY_SIZE(system_noc_bcms), }; +static int glymur_qnoc_probe(struct platform_device *pdev) +{ + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) { + llcc_mc.channels = 8; + ebi.channels = 8; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) { + qns_llcc.channels = 8; + chm_apps.channels = 4; + qnm_pcie_west.buswidth = 32; + hscnoc_nodes[MASTER_WLAN_Q6] = NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) { + qns_pcie_west_mem_noc.buswidth = 32; + pcie_west_anoc_nodes[MASTER_PCIE_3A] = NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-cnoc-cfg")) { + cnoc_cfg_nodes[SLAVE_PCIE_3A_CFG] = NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-slv-noc")) { + pcie_west_slv_noc_nodes[SLAVE_PCIE_3A] = NULL; + } + + return qcom_icc_rpmh_probe(pdev); +} + static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc}, { .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc}, @@ -2477,12 +2500,15 @@ static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc}, { .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt}, { .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg}, + { .compatible = "qcom,mahua-cnoc-cfg", .data = &glymur_cnoc_cfg}, { .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main}, { .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc}, + { .compatible = "qcom,mahua-hscnoc", .data = &glymur_hscnoc}, { .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc}, { .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc}, { .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc}, { .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt}, + { .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt}, { .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc}, { .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc}, { .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc}, @@ -2490,14 +2516,16 @@ static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc}, { .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc}, { .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc}, + { .compatible = "qcom,mahua-pcie-west-anoc", .data = &glymur_pcie_west_anoc}, { .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc}, + { .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc}, { .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc}, { } }; MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { - .probe = qcom_icc_rpmh_probe, + .probe = glymur_qnoc_probe, .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-glymur", From 373ad0e67bf6ae4a4ef4023d733297ae29f6815a Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 27 Jan 2026 14:31:14 +0530 Subject: [PATCH 0301/1330] FROMLIST: dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some QCS8300 interconnect nodes have QoS registers located inside a block whose interface is clock-gated. For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock‑gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Odelu Kukatla Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260127090116.1438780-2-odelu.kukatla@oss.qualcomm.com --- .../interconnect/qcom,qcs8300-rpmh.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml index e9f528d6d9a8c..88fe172771102 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml @@ -35,6 +35,10 @@ properties: reg: maxItems: 1 + clocks: + minItems: 1 + maxItems: 4 + required: - compatible @@ -54,6 +58,64 @@ allOf: required: - reg + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre QUP PRIM AXI clock + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-gem-noc + then: + properties: + clocks: + items: + - description: GCC DDRSS GPU AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-clk-virt + - qcom,qcs8300-config-noc + - qcom,qcs8300-dc-noc + - qcom,qcs8300-gpdsp-anoc + - qcom,qcs8300-lpass-ag-noc + - qcom,qcs8300-mc-virt + - qcom,qcs8300-mmss-noc + - qcom,qcs8300-nspa-noc + - qcom,qcs8300-pcie-anoc + - qcom,qcs8300-system-noc + then: + properties: + clocks: false + unevaluatedProperties: false examples: @@ -63,6 +125,7 @@ examples: reg = <0x9100000 0xf7080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc_ddrss_gpu_axi_clk>; }; clk_virt: interconnect-0 { From 7ff5b0fad5b544c78d9e9630af20a3c2215ed582 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 27 Jan 2026 14:31:15 +0530 Subject: [PATCH 0302/1330] FROMLIST: interconnect: qcom: qcs8300: enable QoS configuration Enable QoS configuration for master ports with predefined priority and urgency forwarding. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260127090116.1438780-3-odelu.kukatla@oss.qualcomm.com --- drivers/interconnect/qcom/qcs8300.c | 375 ++++++++++++++++++++++++++++ 1 file changed, 375 insertions(+) diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qcom/qcs8300.c index bc403a9bf68c6..ebf1671825721 100644 --- a/drivers/interconnect/qcom/qcs8300.c +++ b/drivers/interconnect/qcom/qcs8300.c @@ -186,6 +186,13 @@ static struct qcom_icc_node qxm_qup3 = { .name = "qxm_qup3", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; @@ -194,6 +201,13 @@ static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; @@ -202,6 +216,13 @@ static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; @@ -210,6 +231,13 @@ static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; @@ -218,6 +246,13 @@ static struct qcom_icc_node xm_usb2_2 = { .name = "xm_usb2_2", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; @@ -226,6 +261,13 @@ static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x17000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; @@ -234,6 +276,13 @@ static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -242,6 +291,13 @@ static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x17000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -250,6 +306,13 @@ static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -258,6 +321,13 @@ static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -266,6 +336,13 @@ static struct qcom_icc_node qxm_crypto_0 = { .name = "qxm_crypto_0", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -274,6 +351,13 @@ static struct qcom_icc_node qxm_crypto_1 = { .name = "qxm_crypto_1", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1a000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -282,6 +366,13 @@ static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -290,6 +381,13 @@ static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -298,6 +396,13 @@ static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x19000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -390,6 +495,13 @@ static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xaf000 }, + .prio_fwd_disable = 1, + .prio = 1, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -398,6 +510,13 @@ static struct qcom_icc_node alm_pcie_tcu = { .name = "alm_pcie_tcu", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb0000 }, + .prio_fwd_disable = 1, + .prio = 3, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -406,6 +525,13 @@ static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb1000 }, + .prio_fwd_disable = 1, + .prio = 6, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -423,6 +549,13 @@ static struct qcom_icc_node qnm_cmpnoc0 = { .name = "qnm_cmpnoc0", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf6000, 0xf7000 }, + .prio_fwd_disable = 1, + .prio = 0, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -448,6 +581,13 @@ static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf0000, 0xf1000 }, + .prio_fwd_disable = 1, + .prio = 0, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -456,6 +596,13 @@ static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf2000, 0xf3000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 2, .link_nodes = { &qns_llcc, &qns_pcie }, }; @@ -464,6 +611,13 @@ static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf4000, 0xf5000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -473,6 +627,13 @@ static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb3000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -481,6 +642,13 @@ static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb4000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_llcc }, }; @@ -489,6 +657,13 @@ static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb5000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -541,6 +716,13 @@ static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_mem_noc_hf }, }; @@ -549,6 +731,13 @@ static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; @@ -557,6 +746,13 @@ static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a080 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; @@ -565,6 +761,13 @@ static struct qcom_icc_node qnm_mdp0_0 = { .name = "qnm_mdp0_0", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa080 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_mem_noc_hf }, }; @@ -573,6 +776,13 @@ static struct qcom_icc_node qnm_mdp0_1 = { .name = "qnm_mdp0_1", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa180 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_mem_noc_hf }, }; @@ -597,6 +807,13 @@ static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a100 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; @@ -605,6 +822,13 @@ static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a200 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; @@ -613,6 +837,13 @@ static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a280 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; @@ -637,6 +868,13 @@ static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_pcie_mem_noc }, }; @@ -645,6 +883,13 @@ static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_pcie_mem_noc }, }; @@ -653,6 +898,13 @@ static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_gemnoc_sf }, }; @@ -677,6 +929,13 @@ static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = { &qns_gemnoc_sf }, }; @@ -693,6 +952,13 @@ static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_gemnoc_gc }, }; @@ -701,6 +967,13 @@ static struct qcom_icc_node xm_gic = { .name = "xm_gic", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = { &qns_gemnoc_gc }, }; @@ -1599,11 +1872,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, }; +static const struct regmap_config qcs8300_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_aggre1_noc = { + .config = &qcs8300_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -1624,11 +1907,21 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, }; +static const struct regmap_config qcs8300_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1a080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_aggre2_noc = { + .config = &qcs8300_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -1740,7 +2033,16 @@ static struct qcom_icc_node * const config_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; +static const struct regmap_config qcs8300_config_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x13080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_config_noc = { + .config = &qcs8300_config_noc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1753,7 +2055,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, }; +static const struct regmap_config qcs8300_dc_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_dc_noc = { + .config = &qcs8300_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1786,11 +2097,21 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, }; +static const struct regmap_config qcs8300_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf7080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_gem_noc = { + .config = &qcs8300_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = { @@ -1803,7 +2124,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = { [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, }; +static const struct regmap_config qcs8300_gpdsp_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xd080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_gpdsp_anoc = { + .config = &qcs8300_gpdsp_anoc_regmap_config, .nodes = gpdsp_anoc_nodes, .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), .bcms = gpdsp_anoc_bcms, @@ -1826,7 +2156,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; +static const struct regmap_config qcs8300_lpass_ag_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17200, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_lpass_ag_noc = { + .config = &qcs8300_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1872,7 +2211,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, }; +static const struct regmap_config qcs8300_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40000, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_mmss_noc = { + .config = &qcs8300_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1892,7 +2240,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = { [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; +static const struct regmap_config qcs8300_nspa_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x16080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_nspa_noc = { + .config = &qcs8300_nspa_noc_regmap_config, .nodes = nspa_noc_nodes, .num_nodes = ARRAY_SIZE(nspa_noc_nodes), .bcms = nspa_noc_bcms, @@ -1909,7 +2266,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, }; +static const struct regmap_config qcs8300_pcie_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xc080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_pcie_anoc = { + .config = &qcs8300_pcie_anoc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1937,7 +2303,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; +static const struct regmap_config qcs8300_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x15080, + .fast_io = true, +}; + static const struct qcom_icc_desc qcs8300_system_noc = { + .config = &qcs8300_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, From 1922d24b6624284e4c45c480b5b6fea1685bb7a9 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 27 Jan 2026 14:31:16 +0530 Subject: [PATCH 0303/1330] FROMLIST: arm64: dts: qcom: qcs8300: Add clocks for QoS configuration Add clocks which need to be enabled for configuring QoS on qcs8300 SoC. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260127090116.1438780-4-odelu.kukatla@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 1ec22116735ae..dfdf5996be68a 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2245,6 +2245,10 @@ reg = <0x0 0x016c0000 0x0 0x17080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -2252,6 +2256,7 @@ reg = <0x0 0x01700000 0x0 0x1a080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; pcie_anoc: interconnect@1760000 { @@ -5116,6 +5121,7 @@ reg = <0x0 0x9100000 0x0 0xf7080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; }; llcc: system-cache-controller@9200000 { From 4fa2678794de1e1de1942aed98f24d131f11ec3c Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 9 Nov 2025 20:07:14 +0530 Subject: [PATCH 0304/1330] power: reset: reboot-mode: Remove devres based allocations Devres APIs are intended for use in drivers, and they should be avoided in shared subsystem code which is being used by multiple drivers. Avoid using devres based allocations in the reboot-mode subsystem and manually free the resources. Replace devm_kzalloc with kzalloc and handle memory cleanup explicitly. Fixes: 4fcd504edbf7 ("power: reset: add reboot mode driver") Signed-off-by: Shivendra Pratap Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-1-46e085bca4cc@oss.qualcomm.com --- drivers/power/reset/reboot-mode.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c index fba53f638da04..ac4223794083f 100644 --- a/drivers/power/reset/reboot-mode.c +++ b/drivers/power/reset/reboot-mode.c @@ -3,6 +3,8 @@ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd */ +#define pr_fmt(fmt) "reboot-mode: " fmt + #include #include #include @@ -71,6 +73,7 @@ static int reboot_mode_notify(struct notifier_block *this, int reboot_mode_register(struct reboot_mode_driver *reboot) { struct mode_info *info; + struct mode_info *next; struct property *prop; struct device_node *np = reboot->dev->of_node; size_t len = strlen(PREFIX); @@ -82,29 +85,27 @@ int reboot_mode_register(struct reboot_mode_driver *reboot) if (strncmp(prop->name, PREFIX, len)) continue; - info = devm_kzalloc(reboot->dev, sizeof(*info), GFP_KERNEL); + info = kzalloc(sizeof(*info), GFP_KERNEL); if (!info) { ret = -ENOMEM; goto error; } if (of_property_read_u32(np, prop->name, &info->magic)) { - dev_err(reboot->dev, "reboot mode %s without magic number\n", - info->mode); - devm_kfree(reboot->dev, info); + pr_err("reboot mode %s without magic number\n", info->mode); + kfree(info); continue; } info->mode = kstrdup_const(prop->name + len, GFP_KERNEL); if (!info->mode) { ret = -ENOMEM; - goto error; + goto err_info; } else if (info->mode[0] == '\0') { kfree_const(info->mode); ret = -EINVAL; - dev_err(reboot->dev, "invalid mode name(%s): too short!\n", - prop->name); - goto error; + pr_err("invalid mode name(%s): too short!\n", prop->name); + goto err_info; } list_add_tail(&info->list, &reboot->head); @@ -115,9 +116,14 @@ int reboot_mode_register(struct reboot_mode_driver *reboot) return 0; +err_info: + kfree(info); error: - list_for_each_entry(info, &reboot->head, list) + list_for_each_entry_safe(info, next, &reboot->head, list) { + list_del(&info->list); kfree_const(info->mode); + kfree(info); + } return ret; } @@ -130,11 +136,15 @@ EXPORT_SYMBOL_GPL(reboot_mode_register); int reboot_mode_unregister(struct reboot_mode_driver *reboot) { struct mode_info *info; + struct mode_info *next; unregister_reboot_notifier(&reboot->reboot_notifier); - list_for_each_entry(info, &reboot->head, list) + list_for_each_entry_safe(info, next, &reboot->head, list) { + list_del(&info->list); kfree_const(info->mode); + kfree(info); + } return 0; } From 567bd60cfdeff35787c318e53fffd9a9194bee92 Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 9 Nov 2025 20:07:15 +0530 Subject: [PATCH 0305/1330] power: reset: reboot-mode: Add firmware node based registration The reboot-mode driver does not have a strict requirement for device-based registration. It primarily uses the device's of_node to read mode- properties. Remove the dependency on struct device and introduce support for firmware node (fwnode) based registration. This enables drivers that are not associated with a struct device to leverage the reboot-mode framework. Signed-off-by: Shivendra Pratap Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-2-46e085bca4cc@oss.qualcomm.com --- drivers/power/reset/reboot-mode.c | 19 ++++++++++++++++--- include/linux/reboot-mode.h | 4 +++- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c index ac4223794083f..eff60d6e04df2 100644 --- a/drivers/power/reset/reboot-mode.c +++ b/drivers/power/reset/reboot-mode.c @@ -8,10 +8,12 @@ #include #include #include +#include #include #include #include #include +#include #define PREFIX "mode-" @@ -67,18 +69,26 @@ static int reboot_mode_notify(struct notifier_block *this, /** * reboot_mode_register - register a reboot mode driver * @reboot: reboot mode driver + * @fwnode: Firmware node with reboot-mode configuration * * Returns: 0 on success or a negative error code on failure. */ -int reboot_mode_register(struct reboot_mode_driver *reboot) +int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle *fwnode) { struct mode_info *info; struct mode_info *next; + struct device_node *np; struct property *prop; - struct device_node *np = reboot->dev->of_node; size_t len = strlen(PREFIX); int ret; + if (!fwnode) + return -EINVAL; + + np = to_of_node(fwnode); + if (!np) + return -EINVAL; + INIT_LIST_HEAD(&reboot->head); for_each_property_of_node(np, prop) { @@ -168,11 +178,14 @@ int devm_reboot_mode_register(struct device *dev, struct reboot_mode_driver **dr; int rc; + if (!reboot->dev || !reboot->dev->of_node) + return -EINVAL; + dr = devres_alloc(devm_reboot_mode_release, sizeof(*dr), GFP_KERNEL); if (!dr) return -ENOMEM; - rc = reboot_mode_register(reboot); + rc = reboot_mode_register(reboot, of_fwnode_handle(reboot->dev->of_node)); if (rc) { devres_free(dr); return rc; diff --git a/include/linux/reboot-mode.h b/include/linux/reboot-mode.h index 4a2abb38d1d61..22f707ade4ba9 100644 --- a/include/linux/reboot-mode.h +++ b/include/linux/reboot-mode.h @@ -2,6 +2,8 @@ #ifndef __REBOOT_MODE_H__ #define __REBOOT_MODE_H__ +#include + struct reboot_mode_driver { struct device *dev; struct list_head head; @@ -9,7 +11,7 @@ struct reboot_mode_driver { struct notifier_block reboot_notifier; }; -int reboot_mode_register(struct reboot_mode_driver *reboot); +int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle *fwnode); int reboot_mode_unregister(struct reboot_mode_driver *reboot); int devm_reboot_mode_register(struct device *dev, struct reboot_mode_driver *reboot); From 52e73197e19565a59e932151847c20782d00343e Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 9 Nov 2025 20:07:16 +0530 Subject: [PATCH 0306/1330] power: reset: reboot-mode: Add support for 64 bit magic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Current reboot-mode supports a single 32-bit argument for any supported mode. Some reboot-mode based drivers may require passing two independent 32-bit arguments during a reboot sequence, for uses-cases, where a mode requires an additional argument. Such drivers may not be able to use the reboot-mode driver. For example, ARM PSCI vendor-specific resets, need two arguments for its operation – reset_type and cookie, to complete the reset operation. If a driver wants to implement this firmware-based reset, it cannot use reboot-mode framework. Introduce 64-bit magic values in reboot-mode driver to accommodate dual 32-bit arguments when specified via device tree. In cases, where no second argument is passed from device tree, keep the upper 32-bit of magic un-changed(0) to maintain backward compatibility. Update the current drivers using reboot-mode for a 64-bit magic value. Reviewed-by: Umang Chheda Reviewed-by: Nirmesh Kumar Singh Signed-off-by: Shivendra Pratap Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-3-46e085bca4cc@oss.qualcomm.com --- drivers/power/reset/nvmem-reboot-mode.c | 11 ++++++++--- drivers/power/reset/qcom-pon.c | 11 ++++++++--- drivers/power/reset/reboot-mode.c | 19 +++++++++++++------ drivers/power/reset/syscon-reboot-mode.c | 11 ++++++++--- include/linux/reboot-mode.h | 3 ++- 5 files changed, 39 insertions(+), 16 deletions(-) diff --git a/drivers/power/reset/nvmem-reboot-mode.c b/drivers/power/reset/nvmem-reboot-mode.c index d260715fccf67..4479c874077c7 100644 --- a/drivers/power/reset/nvmem-reboot-mode.c +++ b/drivers/power/reset/nvmem-reboot-mode.c @@ -17,14 +17,19 @@ struct nvmem_reboot_mode { struct nvmem_cell *cell; }; -static int nvmem_reboot_mode_write(struct reboot_mode_driver *reboot, - unsigned int magic) +static int nvmem_reboot_mode_write(struct reboot_mode_driver *reboot, u64 magic) { struct nvmem_reboot_mode *nvmem_rbm; size_t buf_len; + u32 magic_32; void *buf; int ret; + if (magic > U32_MAX) + return -EINVAL; + + magic_32 = magic; + nvmem_rbm = container_of(reboot, struct nvmem_reboot_mode, reboot); buf = nvmem_cell_read(nvmem_rbm->cell, &buf_len); @@ -35,7 +40,7 @@ static int nvmem_reboot_mode_write(struct reboot_mode_driver *reboot, if (buf_len > sizeof(magic)) return -EINVAL; - ret = nvmem_cell_write(nvmem_rbm->cell, &magic, buf_len); + ret = nvmem_cell_write(nvmem_rbm->cell, &magic_32, sizeof(magic_32)); if (ret < 0) dev_err(reboot->dev, "update reboot mode bits failed\n"); diff --git a/drivers/power/reset/qcom-pon.c b/drivers/power/reset/qcom-pon.c index 7e108982a582e..d0ed9431a0231 100644 --- a/drivers/power/reset/qcom-pon.c +++ b/drivers/power/reset/qcom-pon.c @@ -27,17 +27,22 @@ struct qcom_pon { long reason_shift; }; -static int qcom_pon_reboot_mode_write(struct reboot_mode_driver *reboot, - unsigned int magic) +static int qcom_pon_reboot_mode_write(struct reboot_mode_driver *reboot, u64 magic) { struct qcom_pon *pon = container_of (reboot, struct qcom_pon, reboot_mode); + u32 magic_32; int ret; + if (magic > U32_MAX || (magic << pon->reason_shift) > U32_MAX) + return -EINVAL; + + magic_32 = magic << pon->reason_shift; + ret = regmap_update_bits(pon->regmap, pon->baseaddr + PON_SOFT_RB_SPARE, GENMASK(7, pon->reason_shift), - magic << pon->reason_shift); + magic_32); if (ret < 0) dev_err(pon->dev, "update reboot mode bits failed\n"); diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c index eff60d6e04df2..873ac45cd7659 100644 --- a/drivers/power/reset/reboot-mode.c +++ b/drivers/power/reset/reboot-mode.c @@ -19,12 +19,11 @@ struct mode_info { const char *mode; - u32 magic; + u64 magic; struct list_head list; }; -static unsigned int get_reboot_mode_magic(struct reboot_mode_driver *reboot, - const char *cmd) +static u64 get_reboot_mode_magic(struct reboot_mode_driver *reboot, const char *cmd) { const char *normal = "normal"; struct mode_info *info; @@ -56,7 +55,7 @@ static int reboot_mode_notify(struct notifier_block *this, unsigned long mode, void *cmd) { struct reboot_mode_driver *reboot; - unsigned int magic; + u64 magic; reboot = container_of(this, struct reboot_mode_driver, reboot_notifier); magic = get_reboot_mode_magic(reboot, cmd); @@ -80,6 +79,8 @@ int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle struct device_node *np; struct property *prop; size_t len = strlen(PREFIX); + u32 magic_arg1; + u32 magic_arg2; int ret; if (!fwnode) @@ -101,12 +102,18 @@ int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle goto error; } - if (of_property_read_u32(np, prop->name, &info->magic)) { - pr_err("reboot mode %s without magic number\n", info->mode); + if (of_property_read_u32(np, prop->name, &magic_arg1)) { + pr_err("reboot mode without magic number\n"); kfree(info); continue; } + if (of_property_read_u32_index(np, prop->name, 1, &magic_arg2)) + magic_arg2 = 0; + + info->magic = magic_arg2; + info->magic = (info->magic << 32) | magic_arg1; + info->mode = kstrdup_const(prop->name + len, GFP_KERNEL); if (!info->mode) { ret = -ENOMEM; diff --git a/drivers/power/reset/syscon-reboot-mode.c b/drivers/power/reset/syscon-reboot-mode.c index e0772c9f70f7a..3cbd000c51223 100644 --- a/drivers/power/reset/syscon-reboot-mode.c +++ b/drivers/power/reset/syscon-reboot-mode.c @@ -20,16 +20,21 @@ struct syscon_reboot_mode { u32 mask; }; -static int syscon_reboot_mode_write(struct reboot_mode_driver *reboot, - unsigned int magic) +static int syscon_reboot_mode_write(struct reboot_mode_driver *reboot, u64 magic) { struct syscon_reboot_mode *syscon_rbm; + u32 magic_32; int ret; + if (magic > U32_MAX) + return -EINVAL; + + magic_32 = magic; + syscon_rbm = container_of(reboot, struct syscon_reboot_mode, reboot); ret = regmap_update_bits(syscon_rbm->map, syscon_rbm->offset, - syscon_rbm->mask, magic); + syscon_rbm->mask, magic_32); if (ret < 0) dev_err(reboot->dev, "update reboot mode bits failed\n"); diff --git a/include/linux/reboot-mode.h b/include/linux/reboot-mode.h index 22f707ade4ba9..e0d3e8a54050a 100644 --- a/include/linux/reboot-mode.h +++ b/include/linux/reboot-mode.h @@ -3,11 +3,12 @@ #define __REBOOT_MODE_H__ #include +#include struct reboot_mode_driver { struct device *dev; struct list_head head; - int (*write)(struct reboot_mode_driver *reboot, unsigned int magic); + int (*write)(struct reboot_mode_driver *reboot, u64 magic); struct notifier_block reboot_notifier; }; From 2193cbf5c12a2ce8a221e682b576c828829f14fa Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 9 Nov 2025 20:07:17 +0530 Subject: [PATCH 0307/1330] Documentation: ABI: Add sysfs-class-reboot-mode-reboot_modes Add ABI documentation for /sys/class/reboot-mode/*/reboot_modes, a read-only sysfs attribute exposing the list of supported reboot-mode arguments. This file is created by reboot-mode framework and provides a user-readable interface to query available reboot-mode arguments. Reviewed-by: Sebastian Reichel Signed-off-by: Shivendra Pratap Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-4-46e085bca4cc@oss.qualcomm.com --- .../sysfs-class-reboot-mode-reboot_modes | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-class-reboot-mode-reboot_modes diff --git a/Documentation/ABI/testing/sysfs-class-reboot-mode-reboot_modes b/Documentation/ABI/testing/sysfs-class-reboot-mode-reboot_modes new file mode 100644 index 0000000000000..6a3fc379afae3 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-reboot-mode-reboot_modes @@ -0,0 +1,39 @@ +What: /sys/class/reboot-mode//reboot_modes +Date: August 2025 +KernelVersion: 6.17.0-rc1 +Contact: linux-pm@vger.kernel.org + Description: + This interface exposes the reboot-mode arguments + registered with the reboot-mode framework. It is + a read-only interface and provides a space + separated list of reboot-mode arguments supported + on the current platform. + Example: + recovery fastboot bootloader + + The exact sysfs path may vary depending on the + name of the driver that registers the arguments. + Example: + /sys/class/reboot-mode/nvmem-reboot-mode/reboot_modes + /sys/class/reboot-mode/syscon-reboot-mode/reboot_modes + /sys/class/reboot-mode/qcom-pon/reboot_modes + + The supported arguments can be used by userspace + to invoke device reset using the reboot() system + call, with the "argument" as string to "*arg" + parameter along with LINUX_REBOOT_CMD_RESTART2. + Example: + reboot(LINUX_REBOOT_MAGIC1, LINUX_REBOOT_MAGIC2, + LINUX_REBOOT_CMD_RESTART2, "bootloader"); + + A driver can expose the supported arguments by + registering them with the reboot-mode framework + using the property names that follow the + mode- format. + Example: + mode-bootloader, mode-recovery. + + This attribute is useful for scripts or initramfs + logic that need to programmatically determine + which reboot-mode arguments are valid before + triggering a reboot. From 55d6de58a64ae41f092bb99c3c92489f7adecafe Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 9 Nov 2025 20:07:18 +0530 Subject: [PATCH 0308/1330] power: reset: reboot-mode: Expose sysfs for registered reboot_modes Currently, there is no standardized mechanism for userspace to discover which reboot-modes are supported on a given platform. This limitation forces tools and scripts to rely on hardcoded assumptions about the supported reboot-modes. Create a class 'reboot-mode' and a device under it to expose a sysfs interface to show the available reboot mode arguments to userspace. Use the driver_name field of the struct reboot_mode_driver to create the device. For device-based drivers, configure the device driver name as driver_name. This results in the creation of: /sys/class/reboot-mode//reboot_modes This read-only sysfs file will exposes the list of supported reboot modes arguments provided by the driver, enabling userspace to query the list of arguments. Signed-off-by: Shivendra Pratap Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-5-46e085bca4cc@oss.qualcomm.com --- drivers/power/reset/reboot-mode.c | 62 ++++++++++++++++++++++++++++++- include/linux/reboot-mode.h | 2 + 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c index 873ac45cd7659..582aa7f8ed7fa 100644 --- a/drivers/power/reset/reboot-mode.c +++ b/drivers/power/reset/reboot-mode.c @@ -6,6 +6,7 @@ #define pr_fmt(fmt) "reboot-mode: " fmt #include +#include #include #include #include @@ -23,6 +24,8 @@ struct mode_info { struct list_head list; }; +static struct class *rb_class; + static u64 get_reboot_mode_magic(struct reboot_mode_driver *reboot, const char *cmd) { const char *normal = "normal"; @@ -65,6 +68,51 @@ static int reboot_mode_notify(struct notifier_block *this, return NOTIFY_DONE; } +static ssize_t reboot_modes_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct reboot_mode_driver *reboot; + struct mode_info *info; + ssize_t size = 0; + + reboot = (struct reboot_mode_driver *)dev_get_drvdata(dev); + if (!reboot) + return -ENODATA; + + list_for_each_entry(info, &reboot->head, list) + size += sysfs_emit_at(buf, size, "%s ", info->mode); + + if (size) { + size += sysfs_emit_at(buf, size - 1, "\n"); + return size; + } + + return -ENODATA; +} +static DEVICE_ATTR_RO(reboot_modes); + +static int create_reboot_mode_device(struct reboot_mode_driver *reboot) +{ + int ret = 0; + + if (!rb_class) { + rb_class = class_create("reboot-mode"); + if (IS_ERR(rb_class)) + return PTR_ERR(rb_class); + } + + reboot->reboot_dev = device_create(rb_class, NULL, 0, (void *)reboot, reboot->driver_name); + if (IS_ERR(reboot->reboot_dev)) + return PTR_ERR(reboot->reboot_dev); + + ret = device_create_file(reboot->reboot_dev, &dev_attr_reboot_modes); + if (ret) { + device_unregister(reboot->reboot_dev); + return ret; + } + + return ret; +} + /** * reboot_mode_register - register a reboot mode driver * @reboot: reboot mode driver @@ -83,13 +131,17 @@ int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle u32 magic_arg2; int ret; - if (!fwnode) + if (!fwnode || !reboot->driver_name) return -EINVAL; np = to_of_node(fwnode); if (!np) return -EINVAL; + ret = create_reboot_mode_device(reboot); + if (ret) + return ret; + INIT_LIST_HEAD(&reboot->head); for_each_property_of_node(np, prop) { @@ -142,6 +194,8 @@ int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle kfree(info); } + device_remove_file(reboot->reboot_dev, &dev_attr_reboot_modes); + device_unregister(reboot->reboot_dev); return ret; } EXPORT_SYMBOL_GPL(reboot_mode_register); @@ -155,6 +209,9 @@ int reboot_mode_unregister(struct reboot_mode_driver *reboot) struct mode_info *info; struct mode_info *next; + if (!reboot->reboot_dev) + return -EINVAL; + unregister_reboot_notifier(&reboot->reboot_notifier); list_for_each_entry_safe(info, next, &reboot->head, list) { @@ -163,6 +220,8 @@ int reboot_mode_unregister(struct reboot_mode_driver *reboot) kfree(info); } + device_remove_file(reboot->reboot_dev, &dev_attr_reboot_modes); + device_unregister(reboot->reboot_dev); return 0; } EXPORT_SYMBOL_GPL(reboot_mode_unregister); @@ -192,6 +251,7 @@ int devm_reboot_mode_register(struct device *dev, if (!dr) return -ENOMEM; + reboot->driver_name = reboot->dev->driver->name; rc = reboot_mode_register(reboot, of_fwnode_handle(reboot->dev->of_node)); if (rc) { devres_free(dr); diff --git a/include/linux/reboot-mode.h b/include/linux/reboot-mode.h index e0d3e8a54050a..81c149edf40fb 100644 --- a/include/linux/reboot-mode.h +++ b/include/linux/reboot-mode.h @@ -7,6 +7,8 @@ struct reboot_mode_driver { struct device *dev; + struct device *reboot_dev; + const char *driver_name; struct list_head head; int (*write)(struct reboot_mode_driver *reboot, u64 magic); struct notifier_block reboot_notifier; From 53af8158b9fd10cb7e456479d05ce3460f9f4b2b Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Sun, 9 Nov 2025 20:07:20 +0530 Subject: [PATCH 0309/1330] firmware: psci: Implement vendor-specific resets as reboot-mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SoC vendors have different types of resets which are controlled through various hardware registers. For instance, Qualcomm SoC may have a requirement that reboot with “bootloader” command should reboot the device to bootloader flashing mode and reboot with “edl” should reboot the device into Emergency flashing mode. Setting up such reboots on Qualcomm devices can be inconsistent across SoC platforms and may require setting different HW registers, where some of these registers may not be accessible to HLOS. These knobs evolve over product generations and require more drivers. PSCI spec defines, SYSTEM_RESET2, vendor-specific reset which can help align this requirement. Add support for PSCI SYSTEM_RESET2, vendor-specific resets and align the implementation to allow user-space initiated reboots to trigger these resets. Implement the PSCI vendor-specific resets by registering to the reboot-mode framework. As psci init is done at early kernel init, reboot-mode registration cannot be done at the time of psci init. This is because reboot-mode creates a “reboot-mode” class for exposing sysfs, which can fail at early kernel init. To overcome this, introduce a late_initcall to register PSCI vendor-specific resets as reboot modes. Implement a reboot-mode write function that sets reset_type and cookie values during the reboot notifier callback. Introduce a firmware-based call for SYSTEM_RESET2 vendor-specific reset in the psci_sys_reset path, using reset_type and cookie if supported by secure firmware. Register a panic notifier and clear vendor_reset valid status during panic. This is needed for any kernel panic that occurs post reboot_notifiers. By using the above implementation, userspace will be able to issue such resets using the reboot() system call with the "*arg" parameter as a string based command. The commands can be defined in PSCI device tree node under “reboot-mode” and are based on the reboot-mode based commands. Reviewed-by: Umang Chheda Reviewed-by: Kathiravan Thirumoorthy Reviewed-by: Nirmesh Kumar Singh Signed-off-by: Shivendra Pratap Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-7-46e085bca4cc@oss.qualcomm.com --- drivers/firmware/psci/Kconfig | 2 + drivers/firmware/psci/psci.c | 92 ++++++++++++++++++++++++++++++++++- 2 files changed, 93 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/psci/Kconfig b/drivers/firmware/psci/Kconfig index 97944168b5e66..93ff7b071a0c3 100644 --- a/drivers/firmware/psci/Kconfig +++ b/drivers/firmware/psci/Kconfig @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only config ARM_PSCI_FW bool + select POWER_RESET + select REBOOT_MODE config ARM_PSCI_CHECKER bool "ARM PSCI checker" diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c index 38ca190d4a22d..ff82e7f4c27d1 100644 --- a/drivers/firmware/psci/psci.c +++ b/drivers/firmware/psci/psci.c @@ -8,15 +8,18 @@ #include #include +#include #include #include #include #include #include +#include #include #include #include #include +#include #include #include @@ -51,6 +54,24 @@ static int resident_cpu = -1; struct psci_operations psci_ops; static enum arm_smccc_conduit psci_conduit = SMCCC_CONDUIT_NONE; +struct psci_vendor_sysreset2 { + u32 reset_type; + u32 cookie; + bool valid; +}; + +static struct psci_vendor_sysreset2 vendor_reset; + +static int psci_panic_event(struct notifier_block *nb, unsigned long v, void *p) +{ + vendor_reset.valid = false; + return NOTIFY_DONE; +} + +static struct notifier_block psci_panic_block = { + .notifier_call = psci_panic_event +}; + bool psci_tos_resident_on(int cpu) { return cpu == resident_cpu; @@ -309,7 +330,10 @@ static int get_set_conduit_method(const struct device_node *np) static int psci_sys_reset(struct notifier_block *nb, unsigned long action, void *data) { - if ((reboot_mode == REBOOT_WARM || reboot_mode == REBOOT_SOFT) && + if (vendor_reset.valid && psci_system_reset2_supported) { + invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), vendor_reset.reset_type, + vendor_reset.cookie, 0); + } else if ((reboot_mode == REBOOT_WARM || reboot_mode == REBOOT_SOFT) && psci_system_reset2_supported) { /* * reset_type[31] = 0 (architectural) @@ -547,6 +571,72 @@ static const struct platform_suspend_ops psci_suspend_ops = { .enter = psci_system_suspend_enter, }; +static int psci_set_vendor_sys_reset2(struct reboot_mode_driver *reboot, u64 magic) +{ + u32 magic_32; + + if (psci_system_reset2_supported) { + magic_32 = magic & GENMASK(31, 0); + vendor_reset.reset_type = PSCI_1_1_RESET_TYPE_VENDOR_START | magic_32; + vendor_reset.cookie = (magic >> 32) & GENMASK(31, 0); + vendor_reset.valid = true; + } + + return NOTIFY_DONE; +} + +static int __init psci_init_vendor_reset(void) +{ + struct reboot_mode_driver *reboot; + struct device_node *psci_np; + struct device_node *np; + int ret; + + if (!psci_system_reset2_supported) + return -EINVAL; + + psci_np = of_find_compatible_node(NULL, NULL, "arm,psci-1.0"); + if (!psci_np) + return -ENODEV; + + np = of_find_node_by_name(psci_np, "reboot-mode"); + if (!np) { + of_node_put(psci_np); + return -ENODEV; + } + + ret = atomic_notifier_chain_register(&panic_notifier_list, &psci_panic_block); + if (ret) + goto err_notifier; + + reboot = kzalloc(sizeof(*reboot), GFP_KERNEL); + if (!reboot) { + ret = -ENOMEM; + goto err_kzalloc; + } + + reboot->write = psci_set_vendor_sys_reset2; + reboot->driver_name = "psci"; + + ret = reboot_mode_register(reboot, of_fwnode_handle(np)); + if (ret) + goto err_register; + + of_node_put(psci_np); + of_node_put(np); + return 0; + +err_register: + kfree(reboot); +err_kzalloc: + atomic_notifier_chain_unregister(&panic_notifier_list, &psci_panic_block); +err_notifier: + of_node_put(psci_np); + of_node_put(np); + return ret; +} +late_initcall(psci_init_vendor_reset) + static void __init psci_init_system_reset2(void) { int ret; From 51f54053e847b2857bb8c733f9535602317e648a Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 19 Feb 2026 18:53:26 +0530 Subject: [PATCH 0310/1330] FROMLIST: dt-bindings: arm: qcom: Document Glymur SoC and board Document Glymur SoC bindings and Compute Reference Device (CRD) board id Link: https://lore.kernel.org/all/20260219-upstream_v3_glymur_introduction-v8-0-8ce4e489ebb6@oss.qualcomm.com/ Signed-off-by: Pankaj Patil Acked-by: Krzysztof Kozlowski Signed-off-by: Pradyot Kumar Nayak --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2809529cb3525..5c26f2807b78e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - enum: + - qcom,glymur-crd + - const: qcom,glymur + - items: - enum: - fairphone,fp6 From e73fd16ef67443a3799bc8a361f96994bbf195d1 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 19 Feb 2026 18:53:28 +0530 Subject: [PATCH 0311/1330] FROMLIST: arm64: dts: qcom: Introduce Glymur base dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce the base device tree support for Glymur – Qualcomm's next-generation compute SoC. The new glymur.dtsi describes the core SoC components, including: - CPUs and CPU topology - Interrupt controller and TLMM - GCC,DISPCC and RPMHCC clock controllers - Reserved memory and interconnects - APPS and PCIe SMMU and firmware SCM - Watchdog, RPMHPD, APPS RSC and SRAM - PSCI and PMU nodes - QUPv3 serial engines - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS - PDP0 mailbox, IPCC and AOSS - Display clock controller - SPMI PMIC arbiter with SPMI0/1/2 buses - SMP2P nodes - TSENS and thermal zones (8 instances, 92 sensors) Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, PMH0110, PMIC's along with temp-alarm and GPIO nodes needed on Glymur Enabled PCIe controllers and associated PHY to support boot to shell with nvme storage, List of PCIe instances enabled: - PCIe3b - PCIe4 - PCIe5 - PCIe6 Link: https://lore.kernel.org/all/20260219-upstream_v3_glymur_introduction-v8-0-8ce4e489ebb6@oss.qualcomm.com/ Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Jyothi Kumar Seerapu Signed-off-by: Jyothi Kumar Seerapu Co-developed-by: Maulik Shah Signed-off-by: Maulik Shah Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Taniya Das Signed-off-by: Taniya Das Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Co-developed-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Manaf Meethalavalappu Pallikunhi Co-developed-by: Jishnu Prakash Signed-off-by: Jishnu Prakash Reviewed-by: Konrad Dybcio Signed-off-by: Pankaj Patil Reviewed-by: Dmitry Baryshkov Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 5913 ++++++++++++++++++ arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 187 + arch/arm64/boot/dts/qcom/pmh0101.dtsi | 68 + arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 144 + arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 144 + arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 + arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 + 7 files changed, 6571 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/glymur.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmcx0102.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmh0101.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmk8850.dtsi create mode 100644 arch/arm64/boot/dts/qcom/smb2370.dtsi diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi new file mode 100644 index 0000000000000..e269cec7942c8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -0,0 +1,5913 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "glymur-ipcc.h" + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&cpu_pd0>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&cpu_pd1>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&cpu_pd2>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&cpu_pd3>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x400>; + enable-method = "psci"; + power-domains = <&cpu_pd4>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x500>; + enable-method = "psci"; + power-domains = <&cpu_pd5>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu6: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10000>; + enable-method = "psci"; + power-domains = <&cpu_pd6>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10100>; + enable-method = "psci"; + power-domains = <&cpu_pd7>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10200>; + enable-method = "psci"; + power-domains = <&cpu_pd8>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu9: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10300>; + enable-method = "psci"; + power-domains = <&cpu_pd9>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu10: cpu@10400 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10400>; + enable-method = "psci"; + power-domains = <&cpu_pd10>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu11: cpu@10500 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10500>; + enable-method = "psci"; + power-domains = <&cpu_pd11>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu12: cpu@20000 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20000>; + enable-method = "psci"; + power-domains = <&cpu_pd12>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu13: cpu@20100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20100>; + enable-method = "psci"; + power-domains = <&cpu_pd13>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu14: cpu@20200 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20200>; + enable-method = "psci"; + power-domains = <&cpu_pd14>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu15: cpu@20300 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20300>; + enable-method = "psci"; + power-domains = <&cpu_pd15>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu16: cpu@20400 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20400>; + enable-method = "psci"; + power-domains = <&cpu_pd16>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu17: cpu@20500 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20500>; + enable-method = "psci"; + power-domains = <&cpu_pd17>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + + core2 { + cpu = <&cpu8>; + }; + + core3 { + cpu = <&cpu9>; + }; + + core4 { + cpu = <&cpu10>; + }; + + core5 { + cpu = <&cpu11>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu12>; + }; + + core1 { + cpu = <&cpu13>; + }; + + core2 { + cpu = <&cpu14>; + }; + + core3 { + cpu = <&cpu15>; + }; + + core4 { + cpu = <&cpu16>; + }; + + core5 { + cpu = <&cpu17>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_c4: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "ret"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <180>; + exit-latency-us = <320>; + min-residency-us = <1000>; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x01000054>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <9000>; + }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x0200c354>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-glymur", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x4000>; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,glymur-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,glymur-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd8: power-domain-cpu8 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd9: power-domain-cpu9 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd10: power-domain-cpu10 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd11: power-domain-cpu11 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd12: power-domain-cpu12 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd13: power-domain-cpu13 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd14: power-domain-cpu14 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd15: power-domain-cpu15 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd16: power-domain-cpu16 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd17: power-domain-cpu17 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cluster0_pd: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + cluster1_pd: power-domain-cpu-cluster1 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + cluster2_pd: power-domain-cpu-cluster2 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + system_pd: power-domain-system { + #power-domain-cells = <0>; + domain-idle-states = <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pdp_mem: pdp@81400000 { + reg = <0x0 0x81400000 0x0 0x100000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared@81e00000 { + reg = <0x0 0x81e00000 0x0 0x200000>; + no-map; + }; + + oobdaretag_mem: oobdaretag@86e10000 { + reg = <0x0 0x86e10000 0x0 0x360000>; + no-map; + }; + + oob_secure_mem: oob-secure@87170000 { + reg = <0x0 0x87170000 0x0 0xbc0000>; + no-map; + }; + + oobdtbqc_mem: oobdtbqc@87d30000 { + reg = <0x0 0x87d30000 0x0 0x20000>; + no-map; + }; + + oobdtboem_mem: oobdtboem@87d50000 { + reg = <0x0 0x87d50000 0x0 0x20000>; + no-map; + }; + + oob_nonsecure_mem: oob-nonsecure@87e00000 { + reg = <0x0 0x87e00000 0x0 0xc00000>; + no-map; + }; + + spss_region_mem: spss@88a00000 { + reg = <0x0 0x88a00000 0x0 0x400000>; + no-map; + }; + + soccpdtb_mem: soccpdtb@892e0000 { + reg = <0x0 0x892e0000 0x0 0x20000>; + no-map; + }; + + soccp_mem: soccp@89300000 { + reg = <0x0 0x89300000 0x0 0x400000>; + no-map; + }; + + cvp_mem: cvp@89700000 { + reg = <0x0 0x89700000 0x0 0x700000>; + no-map; + }; + + adspslpi_mem: adspslpi@89e00000 { + reg = <0x0 0x89e00000 0x0 0x3a00000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { + reg = <0x0 0x8d800000 0x0 0x80000>; + no-map; + }; + + cdsp_mem: cdsp@8d900000 { + reg = <0x0 0x8d900000 0x0 0x4000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { + reg = <0x0 0x91900000 0x0 0x80000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@919fe000 { + reg = <0x0 0x919fe000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@91a00000 { + reg = <0x0 0x91a00000 0x0 0x800000>; + no-map; + }; + + av1_encoder_mem: av1-encoder@92200000 { + reg = <0x0 0x92200000 0x0 0x700000>; + no-map; + }; + + video_mem: video@92900000 { + reg = <0x0 0x92900000 0x0 0xc00000>; + no-map; + }; + + smem_mem: smem@ffe00000 { + compatible = "qcom,smem"; + reg = <0x0 0xffe00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-soccp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <617>, <616>; + qcom,local-pid = <0>; + qcom,remote-pid = <19>; + + soccp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + soccp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + gcc: clock-controller@100000 { + compatible = "qcom,glymur-gcc"; + reg = <0x0 0x00100000 0x0 0x1f9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ + <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ + <&sleep_clk>, /* Sleep */ + <0>, /* USB 0 Phy DP0 GMUX */ + <0>, /* USB 0 Phy DP1 GMUX */ + <0>, /* USB 0 Phy PCIE PIPEGMUX */ + <0>, /* USB 0 Phy PIPEGMUX */ + <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 1 Phy DP0 GMUX 2 */ + <0>, /* USB 1 Phy DP1 GMUX 2 */ + <0>, /* USB 1 Phy PCIE PIPEGMUX */ + <0>, /* USB 1 Phy PIPEGMUX */ + <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 2 Phy DP0 GMUX 2 */ + <0>, /* USB 2 Phy DP1 GMUX 2 */ + <0>, /* USB 2 Phy PCIE PIPEGMUX */ + <0>, /* USB 2 Phy PIPEGMUX */ + <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ + <0>, /* PCIe 3a */ + <&pcie3b_phy>, /* PCIe 3b */ + <&pcie4_phy>, /* PCIe 4 */ + <&pcie5_phy>, /* PCIe 5 */ + <&pcie6_phy>, /* PCIe 6 */ + <0>, /* QUSB4 0 PHY RX 0 */ + <0>, /* QUSB4 0 PHY RX 1 */ + <0>, /* QUSB4 1 PHY RX 0 */ + <0>, /* QUSB4 1 PHY RX 1 */ + <0>, /* QUSB4 2 PHY RX 0 */ + <0>, /* QUSB4 2 PHY RX 1 */ + <0>, /* UFS PHY RX Symbol 0 */ + <0>, /* UFS PHY RX Symbol 1 */ + <0>, /* UFS PHY TX Symbol 0 */ + <0>, /* USB3 PHY 0 */ + <0>, /* USB3 PHY 1 */ + <0>, /* USB3 PHY 2 */ + <0>, /* USB3 UNI PHY pipe 0 */ + <0>, /* USB3 UNI PHY pipe 1 */ + <0>, /* USB4 PHY 0 pcie pipe */ + <0>, /* USB4 PHY 0 Max pipe */ + <0>, /* USB4 PHY 1 pcie pipe */ + <0>, /* USB4 PHY 1 Max pipe */ + <0>, /* USB4 PHY 2 pcie */ + <0>; /* USB4 PHY 2 Max */ + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpi_dma2: dma-controller@800000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xd76 0x0>; + }; + + qupv3_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xd63 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c16: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c16_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi16: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c17: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c17_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi17: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c18: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c18_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi18: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c19: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c19_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi19: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart19: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart19_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c20: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c20_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi20: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c21: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c21_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi21: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart21: serial@894000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart21_default>; + pinctrl-names = "default"; + }; + + i2c22: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c22_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi22: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart22: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart22_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c23: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0089c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c23_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi23: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0089c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xcb6 0x0>; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xca3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart14: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart14_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma0: dma-controller@b00000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00b00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xd36 0x0>; + }; + + qupv3_0: geniqup@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00bc0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xd23 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@b80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@b80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@b84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@b84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@b88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@b88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart2: serial@b88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c3: i2c@b8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@b8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c4: i2c@b90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@b90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c5: i2c@b94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@b94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c6: i2c@b98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@b98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c7: i2c@b9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@b9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,glymur-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x17080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,glymur-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x6600>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,glymur-system-noc"; + reg = <0x0 0x01680000 0x0 0x1c080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_west_anoc: interconnect@16c0000 { + compatible = "qcom,glymur-pcie-west-anoc"; + reg = <0x0 0x016c0000 0x0 0xf580>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; + }; + + pcie_east_anoc: interconnect@16d0000 { + compatible = "qcom,glymur-pcie-east-anoc"; + reg = <0x0 0x016d0000 0x0 0xf300>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,glymur-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + aggre2_noc: interconnect@1720000 { + compatible = "qcom,glymur-aggre2-noc"; + reg = <0x0 0x01720000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + }; + + aggre3_noc: interconnect@1700000 { + compatible = "qcom,glymur-aggre3-noc"; + reg = <0x0 0x01700000 0x0 0x1d400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + aggre4_noc: interconnect@1740000 { + compatible = "qcom,glymur-aggre4-noc"; + reg = <0x0 0x01740000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,glymur-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_east_slv_noc: interconnect@1900000 { + compatible = "qcom,glymur-pcie-east-slv-noc"; + reg = <0x0 0x01900000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_west_slv_noc: interconnect@1920000 { + compatible = "qcom,glymur-pcie-west-slv-noc"; + reg = <0x0 0x01920000 0x0 0xf180>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie4: pci@1bf0000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01bf0000 0x0 0x3000>, + <0x0 0x78000000 0x0 0xf20>, + <0x0 0x78000f40 0x0 0xa8>, + <0x0 0x78001000 0x0 0x4000>, + <0x0 0x78005000 0x0 0x100000>, + <0x0 0x01bf3000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, + <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, + <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <4>; + num-lanes = <2>; + + operating-points-v2 = <&pcie4_opp_table>; + + msi-map = <0x0 &gic_its 0xc0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_4_BCR>, + <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_4_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + status = "disabled"; + + pcie4_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + }; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie4_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie4_phy: phy@1bf6000 { + compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01bf6000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_2_CLKREF_EN>, + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK>, + <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_4_PHY_BCR>, + <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie4_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie5: pci@1b40000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01b40000 0x0 0x3000>, + <0x0 0x7a000000 0x0 0xf20>, + <0x0 0x7a000f40 0x0 0xa8>, + <0x0 0x7a001000 0x0 0x4000>, + <0x0 0x7a100000 0x0 0x100000>, + <0x0 0x01b43000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, + <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, + <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <5>; + num-lanes = <4>; + + operating-points-v2 = <&pcie5_opp_table>; + + msi-map = <0x0 &gic_its 0xd0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_5_BCR>, + <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_5_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie5_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + opp-level = <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + opp-level = <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <15753000 1>; + opp-level = <5>; + }; + }; + + pcie5_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie5_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie5_phy: phy@1b50000 { + compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg = <0x0 0x01b50000 0x0 0x10000>; + + clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_5_PHY_BCR>, + <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie5_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie6: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x7e000000 0x0 0xf20>, + <0x0 0x7e000f40 0x0 0xa8>, + <0x0 0x7e001000 0x0 0x4000>, + <0x0 0x7e100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, + <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, + <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <6>; + num-lanes = <2>; + + operating-points-v2 = <&pcie6_opp_table>; + + msi-map = <0x0 &gic_its 0xe0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_6_AUX_CLK>, + <&gcc GCC_PCIE_6_CFG_AHB_CLK>, + <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_6_SLV_AXI_CLK>, + <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_6_BCR>, + <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_6_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + status = "disabled"; + + pcie6_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + }; + + pcie6_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie6_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie6_phy: phy@1c06000 { + compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01c06000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, + <&gcc GCC_PCIE_6_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_4_CLKREF_EN>, + <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_6_PIPE_CLK>, + <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_6_PHY_BCR>, + <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie6_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie3b: pci@1b80000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01b80000 0x0 0x3000>, + <0x0 0x74000000 0x0 0xf20>, + <0x0 0x74000f40 0x0 0xa8>, + <0x0 0x74001000 0x0 0x4000>, + <0x0 0x74100000 0x0 0x100000>, + <0x0 0x01b83000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, + <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, + <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <7>; + num-lanes = <4>; + + operating-points-v2 = <&pcie3b_opp_table>; + + msi-map = <0x0 &gic_its 0xf0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_3B_BCR>, + <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_3B_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie3b_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + opp-level = <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + opp-level = <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <15753000 1>; + opp-level = <5>; + }; + }; + + pcie3b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie3b_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie3b_phy: phy@f10000 { + compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg = <0x0 0x00f10000 0x0 0x10000>; + + clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie3b_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fd5000 { + compatible = "qcom,glymur-tcsr", + "syscon"; + reg = <0x0 0x1fd5000 0x0 0x21000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + hsc_noc: interconnect@2000000 { + compatible = "qcom,glymur-hscnoc"; + reg = <0x0 0x02000000 0x0 0x93a080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + ipcc: mailbox@3e04000 { + compatible = "qcom,glymur-ipcc", "qcom,ipcc"; + reg = <0x0 0x03e04000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,glymur-lpass-lpiaon-noc"; + reg = <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,glymur-lpass-lpicx-noc"; + reg = <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,glymur-lpass-ag-noc"; + reg = <0x0 0x07e40000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,glymur-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,glymur-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x10000>; + qcom,pdc-ranges = <0 745 51>, + <51 527 47>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <171 4104 36>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c22c000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c22d000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <9>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22e000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22f000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <8>; + + #thermal-sensor-cells = <1>; + }; + + tsens4: thermal-sensor@c230000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens5: thermal-sensor@c231000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <8>; + + #thermal-sensor-cells = <1>; + }; + + tsens6: thermal-sensor@c232000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c232000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens7: thermal-sensor@c233000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c233000 0x0 0x1000>, + <0x0 0x0c229000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <15>; + + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c30f000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c30f000 0x0 0x400>; + }; + + arbiter@c400000 { + compatible = "qcom,glymur-spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c900000 0x0 0x400000>, + <0x0 0x0c4c0000 0x0 0x400000>, + <0x0 0x0c403000 0x0 0x8000>; + reg-names = "core", + "chnls", + "obsrvr", + "chnl_map"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + qcom,channel = <0>; + qcom,ee = <0>; + + spmi_bus0: spmi@c426000 { + reg = <0x0 0x0c426000 0x0 0x4000>, + <0x0 0x0c8c0000 0x0 0x10000>, + <0x0 0x0c42a000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c437000 { + reg = <0x0 0x0c437000 0x0 0x4000>, + <0x0 0x0c8d0000 0x0 0x10000>, + <0x0 0x0c43b000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus2: spmi@c48000 { + reg = <0x0 0x0c448000 0x0 0x4000>, + <0x0 0x0c8e0000 0x0 0x10000>, + <0x0 0x0c44c000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,glymur-tlmm"; + reg = <0x0 0x0f100000 0x0 0xf00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 249>; + wakeup-parent = <&pdc>; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio0", "gpio1"; + function = "qup0_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup0_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio16", "gpio17"; + function = "qup0_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio6", "gpio7"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio14", "gpio15"; + function = "qup0_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins = "gpio40", "gpio41"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins = "gpio54", "gpio55"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins = "gpio64", "gpio65"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins = "gpio68", "gpio69"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c18_data_clk: qup-i2c18-data-clk-state { + /* SDA, SCL */ + pins = "gpio72", "gpio73"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins = "gpio76", "gpio77"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins = "gpio84", "gpio85"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins = "gpio88", "gpio89"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio3"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio7"; + function = "qup0_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio4", "gpio5", "gpio6"; + function = "qup0_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio8", "gpio9", "gpio10"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio15"; + function = "qup0_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio12", "gpio13", "gpio14"; + function = "qup0_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio19"; + function = "qup0_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio16", "gpio17", "gpio18"; + function = "qup0_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio23"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio20", "gpio21", "gpio22"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio5"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio6", "gpio7", "gpio4"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio13"; + function = "qup0_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio14", "gpio15", "gpio12"; + function = "qup0_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio35"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio39"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio36", "gpio37", "gpio38"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio43"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio40", "gpio41", "gpio42"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio47"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio51"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio48", "gpio49", "gpio50"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio56", "gpio57", "gpio58"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio53"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio54", "gpio55", "gpio52"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins = "gpio67"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio64", "gpio65", "gpio66"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins = "gpio71"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio68", "gpio69", "gpio70"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi18_cs: qup-spi18-cs-state { + pins = "gpio75"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi18_data_clk: qup-spi18-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio72", "gpio73", "gpio74"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins = "gpio79"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio76", "gpio77", "gpio78"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins = "gpio83"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio81", "gpio82"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio84", "gpio85", "gpio86"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi22_cs: qup-spi22-cs-state { + pins = "gpio91"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi22_data_clk: qup-spi22-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio88", "gpio89", "gpio90"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi23_cs: qup-spi23-cs-state { + pins = "gpio83"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi23_data_clk: qup-spi23-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio81", "gpio82"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + tx-pins { + pins = "gpio10"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart14_default: qup-uart14-default-state { + cts-pins { + pins = "gpio56"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio58"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart19_default: qup-uart19-default-state { + cts-pins { + pins = "gpio76"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio77"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio78"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio79"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart21_default: qup-uart21-default-state { + tx-pins { + pins = "gpio86"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart22_default: qup-uart22-default-state { + tx-pins { + pins = "gpio90"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio91"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,glymur-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-coherent; + }; + + pcie_smmu: iommu@15480000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x15480000 0x0 0x20000>; + interrupts = , + , + ; + interrupt-names = "eventq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <1>; + }; + + intc: interrupt-controller@17000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17040000 0x0 0x40000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + watchdog@17600000 { + compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; + reg = <0x0 0x17600000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; + interrupts = ; + #mbox-cells = <1>; + }; + + timer@17810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17810000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x0 0x20000000>; + + frame@17811000 { + reg = <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + + interrupts = , + ; + + frame-number = <0>; + }; + + frame@17813000 { + reg = <0x0 0x17813000 0x1000>; + + interrupts = ; + + frame-number = <1>; + + status = "disabled"; + }; + + frame@17815000 { + reg = <0x0 0x17815000 0x1000>; + + interrupts = ; + + frame-number = <2>; + + status = "disabled"; + }; + + frame@17817000 { + reg = <0x0 0x17817000 0x1000>; + + interrupts = ; + + frame-number = <3>; + + status = "disabled"; + }; + + frame@17819000 { + reg = <0x0 0x17819000 0x1000>; + + interrupts = ; + + frame-number = <4>; + + status = "disabled"; + }; + + frame@1781b000 { + reg = <0x0 0x1781b000 0x1000>; + + interrupts = ; + + frame-number = <5>; + + status = "disabled"; + }; + + frame@1781d000 { + reg = <0x0 0x1781d000 0x1000>; + + interrupts = ; + + frame-number = <6>; + + status = "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible = "qcom,rpmh-rsc"; + label = "apps_rsc"; + reg = <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + power-domains = <&system_pd>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,glymur-rpmh-clk"; + + clocks = <&xo_board>; + clock-names = "xo"; + + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,glymur-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + }; + }; + }; + + nsi_noc: interconnect@1d600000 { + compatible = "qcom,glymur-nsinoc"; + reg = <0x0 0x1d600000 0x0 0x14080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + oobm_ss_noc: interconnect@1f300000 { + compatible = "qcom,glymur-oobm-ss-noc"; + reg = <0x0 0x1f300000 0x0 0x49a00>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system-cache-controller@20400000 { + compatible = "qcom,glymur-llcc"; + reg = <0x0 0x21800000 0x0 0x100000>, + <0x0 0x21a00000 0x0 0x100000>, + <0x0 0x21c00000 0x0 0x100000>, + <0x0 0x21e00000 0x0 0x100000>, + <0x0 0x22800000 0x0 0x100000>, + <0x0 0x22a00000 0x0 0x100000>, + <0x0 0x22c00000 0x0 0x100000>, + <0x0 0x22e00000 0x0 0x100000>, + <0x0 0x23800000 0x0 0x100000>, + <0x0 0x23a00000 0x0 0x100000>, + <0x0 0x23c00000 0x0 0x100000>, + <0x0 0x23e00000 0x0 0x100000>, + <0x0 0x20400000 0x0 0x100000>, + <0x0 0x20600000 0x0 0x100000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc6_base", + "llcc7_base", + "llcc8_base", + "llcc9_base", + "llcc10_base", + "llcc11_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = ; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,glymur-nsp-noc"; + reg = <0x0 0x320c0000 0x0 0x21280>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + imem: sram@81e08000 { + compatible = "mmio-sram"; + reg = <0x0 0x81e08600 0x0 0x300>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81e08600 0x300>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x180>; + }; + + cpu_scp_lpri1: scp-sram-section@180 { + compatible = "arm,scmi-shmem"; + reg = <0x180 0x180>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; + + thermal_zones: thermal-zones { + aoss-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpu-0-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpu-0-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpu-0-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpu-0-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + cpu-0-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + cpu-0-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + cpu-0-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + cpu-0-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + cpu-0-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + cpu-0-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + cpu-0-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + cpu-0-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-0-0-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpullc-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpullc-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + qmx-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + qmx-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + qmx-0-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-0-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + ddr-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-0-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + video-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-1-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + video-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + aoss-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + cpu-1-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + cpu-1-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + cpu-1-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + cpu-1-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-0-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + cpu-1-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-1-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + cpu-1-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-0-thermal { + thermal-sensors = <&tsens2 7>; + + trips { + cpu-1-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-1-thermal { + thermal-sensors = <&tsens2 8>; + + trips { + cpu-1-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-4-0-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + cpu-1-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-4-1-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + cpu-1-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-5-0-thermal { + thermal-sensors = <&tsens2 11>; + + trips { + cpu-1-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-5-1-thermal { + thermal-sensors = <&tsens2 12>; + + trips { + cpu-1-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + aoss-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + cpullc-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + cpullc-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + qmx-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + qmx-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors = <&tsens3 5>; + + trips { + qmx-1-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors = <&tsens3 6>; + + trips { + qmx-1-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors = <&tsens3 7>; + + trips { + qmx-1-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-4-thermal { + thermal-sensors = <&tsens4 0>; + + trips { + aoss-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-0-0-thermal { + thermal-sensors = <&tsens4 1>; + + trips { + cpu-2-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-0-1-thermal { + thermal-sensors = <&tsens4 2>; + + trips { + cpu-2-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-1-0-thermal { + thermal-sensors = <&tsens4 3>; + + trips { + cpu-2-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-1-1-thermal { + thermal-sensors = <&tsens4 4>; + + trips { + cpu-2-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-2-0-thermal { + thermal-sensors = <&tsens4 5>; + + trips { + cpu-2-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-2-1-thermal { + thermal-sensors = <&tsens4 6>; + + trips { + cpu-2-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-3-0-thermal { + thermal-sensors = <&tsens4 7>; + + trips { + cpu-2-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-3-1-thermal { + thermal-sensors = <&tsens4 8>; + + trips { + cpu-2-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-4-0-thermal { + thermal-sensors = <&tsens4 9>; + + trips { + cpu-2-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-4-1-thermal { + thermal-sensors = <&tsens4 10>; + + trips { + cpu-2-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-5-0-thermal { + thermal-sensors = <&tsens4 11>; + + trips { + cpu-2-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-5-1-thermal { + thermal-sensors = <&tsens4 12>; + + trips { + cpu-2-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-5-thermal { + thermal-sensors = <&tsens5 0>; + + trips { + aoss-5-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-2-0-thermal { + thermal-sensors = <&tsens5 1>; + + trips { + cpullc-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuillc-2-1-thermal { + thermal-sensors = <&tsens5 2>; + + trips { + cpullc-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-0-thermal { + thermal-sensors = <&tsens5 3>; + + trips { + qmx-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-1-thermal { + thermal-sensors = <&tsens5 4>; + + trips { + qmx-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-2-thermal { + thermal-sensors = <&tsens5 5>; + + trips { + qmx-2-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-3-thermal { + thermal-sensors = <&tsens5 6>; + + trips { + qmx-2-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-4-thermal { + thermal-sensors = <&tsens5 7>; + + trips { + qmx-2-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-6-thermal { + thermal-sensors = <&tsens6 0>; + + trips { + aoss-6-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors = <&tsens6 1>; + + trips { + nsphvx-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors = <&tsens6 2>; + + trips { + nsphvx-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors = <&tsens6 3>; + + trips { + nsphvx-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors = <&tsens6 4>; + + trips { + nsphvx-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors = <&tsens6 5>; + + trips { + nsphmx-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors = <&tsens6 6>; + + trips { + nsphmx-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors = <&tsens6 7>; + + trips { + nsphmx-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors = <&tsens6 8>; + + trips { + nsphmx-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors = <&tsens6 9>; + + trips { + camera-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors = <&tsens6 10>; + + trips { + camera-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-1-thermal { + thermal-sensors = <&tsens6 11>; + + trips { + ddr-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-2-thermal { + thermal-sensors = <&tsens6 12>; + + trips { + ddr-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-7-thermal { + thermal-sensors = <&tsens7 0>; + + trips { + aoss-7-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-0-0-thermal { + thermal-sensors = <&tsens7 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-0-1-thermal { + thermal-sensors = <&tsens7 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-0-2-thermal { + thermal-sensors = <&tsens7 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-1-0-thermal { + thermal-sensors = <&tsens7 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-1-1-thermal { + thermal-sensors = <&tsens7 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-1-2-thermal { + thermal-sensors = <&tsens7 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-2-0-thermal { + thermal-sensors = <&tsens7 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-2-1-thermal { + thermal-sensors = <&tsens7 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-2-2-thermal { + thermal-sensors = <&tsens7 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-3-0-thermal { + thermal-sensors = <&tsens7 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-3-1-thermal { + thermal-sensors = <&tsens7 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-3-2-thermal { + thermal-sensors = <&tsens7 12>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors = <&tsens7 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors = <&tsens7 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi new file mode 100644 index 0000000000000..c3ccd2b756099 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmcx0102-c0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_c_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102-c1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_c_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102-d0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_d_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102-d1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_d_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmcx0102_c_e0: pmic@2 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_c_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_c_e0_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_c_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmcx0102_d_e0: pmic@3 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_d_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_d_e0_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_d_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmcx0102_c_e1: pmic@2 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_c_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_c_e1_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_c_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmcx0102_d_e1: pmic@3 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_d_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_d_e1_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_d_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0101.dtsi b/arch/arm64/boot/dts/qcom/pmh0101.dtsi new file mode 100644 index 0000000000000..b1ec413259583 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0101.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0101-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0101_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmic@1 { + compatible = "qcom,pmh0101", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0101_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0101_gpios: gpio@8800 { + compatible = "qcom,pmh0101-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0101_gpios 0 0 18>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmh0101_flash: led-controller@ee00 { + compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; + + pmh0101_pwm: pwm { + compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi new file mode 100644 index 0000000000000..d89cceda53a3f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/{ + thermal_zones { + pmh0104-i0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_i_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0104-j0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_j_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0104-l1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_l_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmh0104_i_e0: pmic@8 { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_i_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_i_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_i_e0_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0104_j_e0: pmic@9 { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_j_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_j_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_j_e0_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmh0104_l_e1: pmic@b { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_l_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_l_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_l_e1_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi new file mode 100644 index 0000000000000..7655bc0303482 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0110-f0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_f_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-f1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_f_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-h0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_h_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmh0110_f_e0: pmic@5 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_f_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_h_e0: pmic@7 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_h_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_h_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmh0110_f_e1: pmic@5 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_f_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmk8850.dtsi b/arch/arm64/boot/dts/qcom/pmk8850.dtsi new file mode 100644 index 0000000000000..c7ba72fd48bc8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8850.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +&spmi_bus0 { + pmic@0 { + compatible = "qcom,pmk8850", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8850_pon: pon@1300 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, + <0x800>; + reg-names = "hlos", + "pbs"; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8850_gpios: gpio@b800 { + compatible = "qcom,pmk8850-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8850_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmk8850_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, + <0x6200>; + reg-names = "rtc", + "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pmk8850_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qcom/smb2370.dtsi new file mode 100644 index 0000000000000..80f3fdae57050 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +&spmi_bus2 { + smb2370_j_e2: pmic@9 { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_j_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2370_k_e2: pmic@a { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_k_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2370_l_e2: pmic@b { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_l_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; From 75f19da11480495e2143c1acff7fa840da1b766e Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 19 Feb 2026 18:53:29 +0530 Subject: [PATCH 0312/1330] FROMLIST: arm64: dts: qcom: glymur: Enable Glymur CRD board support Add initial device tree support for the Glymur Compute Reference Device(CRD) board, with this board dts glymur crd can boot to shell with rootfs on nvme and uart21 as serial console Features enabled are: - Board and sleep clocks - Volume up/down keys - Regulators 0 - 4 - Power supplies and sideband signals (PERST, WAKE, CLKREQ) for PCIe3b/4/5/6 controllers and PHYs Link: https://lore.kernel.org/all/20260219-upstream_v3_glymur_introduction-v8-0-8ce4e489ebb6@oss.qualcomm.com/ Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Jyothi Kumar Seerapu Signed-off-by: Jyothi Kumar Seerapu Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Pankaj Patil Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur-crd.dts | 598 ++++++++++++++++++++++++ 2 files changed, 599 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/glymur-crd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index db3f80d7c6b49..cd7fcf1556bc6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts new file mode 100644 index 0000000000000..8779453190122 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "glymur.dtsi" +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ + +/ { + model = "Qualcomm Technologies, Inc. Glymur CRD"; + compatible = "qcom,glymur-crd", "qcom,glymur"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + i2c0 = &i2c0; + i2c1 = &i2c4; + i2c2 = &i2c5; + spi0 = &spi18; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvmesec: regulator-nvmesec { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_SEC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_sec_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WLAN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wlan_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WWAN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_reg_en>; + pinctrl-names = "default"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_bob1_e0: bob1 { + regulator-name = "vreg_bob1_e0"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <4224000>; + regulator-initial-mode = ; + }; + + vreg_bob2_e0: bob2 { + regulator-name = "vreg_bob2_e0"; + regulator-min-microvolt = <2540000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + }; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name = "vreg_l1b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_e0_2p9: ldo2 { + regulator-name = "vreg_l2b_e0_2p9"; + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l7b_e0_2p79: ldo7 { + regulator-name = "vreg_l7b_e0_2p79"; + regulator-min-microvolt = <2790000>; + regulator-max-microvolt = <2792000>; + regulator-initial-mode = ; + }; + + vreg_l8b_e0_1p50: ldo8 { + regulator-name = "vreg_l8b_e0_1p50"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_e0_2p7: ldo9 { + regulator-name = "vreg_l9b_e0_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l10b_e0_1p8: ldo10 { + regulator-name = "vreg_l10b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b_e0_1p2: ldo11 { + regulator-name = "vreg_l11b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l12b_e0_1p14: ldo12 { + regulator-name = "vreg_l12b_e0_1p14"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1144000>; + regulator-initial-mode = ; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name = "vreg_l15b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_e0_2p4: ldo17 { + regulator-name = "vreg_l17b_e0_2p4"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name = "vreg_l18b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c_e1_0p82: ldo1 { + regulator-name = "vreg_l1c_e1_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2c_e1_1p14: ldo2 { + regulator-name = "vreg_l2c_e1_1p14"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1144000>; + regulator-initial-mode = ; + }; + + vreg_l3c_e1_0p89: ldo3 { + regulator-name = "vreg_l3c_e1_0p89"; + regulator-min-microvolt = <890000>; + regulator-max-microvolt = <980000>; + regulator-initial-mode = ; + }; + + vreg_l4c_e1_0p72: ldo4 { + regulator-name = "vreg_l4c_e1_0p72"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <720000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s7f_e0_1p32: smps7 { + regulator-name = "vreg_s7f_e0_1p32"; + regulator-min-microvolt = <1320000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s8f_e0_0p95: smps8 { + regulator-name = "vreg_s8f_e0_0p95"; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s9f_e0_1p9: smps9 { + regulator-name = "vreg_s9f_e0_1p9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e0_0p82: ldo2 { + regulator-name = "vreg_l2f_e0_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l3f_e0_0p72: ldo3 { + regulator-name = "vreg_l3f_e0_0p72"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <720000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e0_0p3: ldo4 { + regulator-name = "vreg_l4f_e0_0p3"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_s7f_e1_0p3: smps7 { + regulator-name = "vreg_s7f_e1_0p3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l1f_e1_0p82: ldo1 { + regulator-name = "vreg_l1f_e1_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e1_0p83: ldo2 { + regulator-name = "vreg_l2f_e1_0p83"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e1_1p08: ldo4 { + regulator-name = "vreg_l4f_e1_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + vreg_l1h_e0_0p89: ldo1 { + regulator-name = "vreg_l1h_e0_0p89"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2h_e0_0p72: ldo2 { + regulator-name = "vreg_l2h_e0_0p72"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l3h_e0_0p32: ldo3 { + regulator-name = "vreg_l3h_e0_0p32"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name = "vreg_l4h_e0_1p2"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + }; +}; + +&pcie3b { + vddpe-3v3-supply = <&vreg_nvmesec>; + + pinctrl-0 = <&pcie3b_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3b_phy { + vdda-phy-supply = <&vreg_l3c_e1_0p89>; + vdda-pll-supply = <&vreg_l2c_e1_1p14>; + + status = "okay"; +}; + +&pcie3b_port0 { + reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + vddpe-3v3-supply = <&vreg_wlan>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0_0p82>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie6_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie6_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0101_gpios { + key_vol_up_default: key-vol-up-default-state { + pins = "gpio6"; + function = "normal"; + output-disable; + bias-pull-up; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>; /* Security SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie6_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins = "gpio156"; + function = "pcie3b_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio155"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio157"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wlan_reg_en: wlan-reg-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_reg_en: wwan-reg-en-state { + pins = "gpio246"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; From 80b01a049561baef5b76475f028b0890dcfb2645 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Mon, 23 Feb 2026 17:37:44 +0200 Subject: [PATCH 0313/1330] FROMLIST: arm64: dts: qcom: glymur: Add USB related nodes The Glymur USB system contains 3 USB type C ports, 1 USB multiport controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS DWC3 based, so describe them as flattened DWC3 QCOM nodes. Link: https://lore.kernel.org/linux-arm-msm/20260223-dts-qcom-glymur-add-usb-support-v2-1-f4e0f38db21d@oss.qualcomm.com/ Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Tested-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 691 ++++++++++++++++++++++++++- 1 file changed, 686 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index e269cec7942c8..2aa9af8c96ce6 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -750,11 +750,11 @@ <0>, /* UFS PHY RX Symbol 0 */ <0>, /* UFS PHY RX Symbol 1 */ <0>, /* UFS PHY TX Symbol 0 */ - <0>, /* USB3 PHY 0 */ - <0>, /* USB3 PHY 1 */ - <0>, /* USB3 PHY 2 */ - <0>, /* USB3 UNI PHY pipe 0 */ - <0>, /* USB3 UNI PHY pipe 1 */ + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, <0>, /* USB4 PHY 0 pcie pipe */ <0>, /* USB4 PHY 0 Max pipe */ <0>, /* USB4 PHY 1 pcie pipe */ @@ -2264,6 +2264,254 @@ }; }; + usb_hs_phy: phy@fa0000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x00fa0000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status = "disabled"; + }; + + usb_mp_hsphy0: phy@fa1000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x00fa1000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + status = "disabled"; + }; + + usb_mp_hsphy1: phy@fa2000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x00fa2000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + status = "disabled"; + }; + + usb_mp_qmpphy0: phy@fa3000 { + compatible = "qcom,glymur-qmp-usb3-uni-phy"; + reg = <0x0 0x00fa3000 0x0 0x2000>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_0_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names = "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; + + resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy", + "phy_phy"; + + clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_mp_qmpphy1: phy@fa5000 { + compatible = "qcom,glymur-qmp-usb3-uni-phy"; + reg = <0x0 0x00fa5000 0x0 0x2000>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_1_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names = "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy", + "phy_phy"; + + clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; + + #clock-cells = <0>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_0_hsphy: phy@fd3000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x00fd3000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_0_qmpphy: phy@fd5000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0x0 0x00fd5000 0x0 0x8000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB_0_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_1_hsphy: phy@fdd000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x00fdd000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status = "disabled"; + }; + + usb_1_qmpphy: phy@fde000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0x0 0x00fde000 0x0 0x8000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_1_CLKREF_EN>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains = <&gcc GCC_USB_1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,glymur-cnoc-main"; reg = <0x0 0x01500000 0x0 0x17080>; @@ -3367,6 +3615,439 @@ #interconnect-cells = <2>; }; + usb_2_hsphy: phy@88e0000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x088e0000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status = "disabled"; + }; + + usb_2_qmpphy: phy@88e1000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0x0 0x088e1000 0x0 0x8000>; + + clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_2_CLKREF_EN>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains = <&gcc GCC_USB_2_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB3PHY_PHY_TERT_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_2_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_2_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_2_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_0: usb@a600000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_EDGE_BOTH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + resets = <&gcc GCC_USB30_PRIM_BCR>; + + iommus = <&apps_smmu 0x1420 0x0>; + phys = <&usb_0_hsphy>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_1: usb@a800000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a800000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 88 IRQ_TYPE_EDGE_BOTH>, + <&pdc 87 IRQ_TYPE_EDGE_BOTH>, + <&pdc 76 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + + iommus = <&apps_smmu 0x1460 0x0>; + + phys = <&usb_1_hsphy>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_2: usb@a000000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a000000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 89 IRQ_TYPE_EDGE_BOTH>, + <&pdc 81 IRQ_TYPE_EDGE_BOTH>, + <&pdc 75 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets = <&gcc GCC_USB30_TERT_BCR>; + power-domains = <&gcc GCC_USB30_TERT_GDSC>; + + iommus = <&apps_smmu 0x420 0x0>; + + phys = <&usb_2_hsphy>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_2_dwc3_ss: endpoint { + remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_hs: usb@a2f8800 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a200000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_EDGE_BOTH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "hs_phy_irq"; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + power-domains = <&gcc GCC_USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x0ce0 0x0>; + + interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + + phys = <&usb_hs_phy>; + phy-names = "usb2-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode = "host"; + + maximum-speed = "high-speed"; + + status = "disabled"; + }; + + usb_mp: usb@a400000 { + compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; + reg = <0x0 0x0a400000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event_1", + "pwr_event_2", + "hs_phy_1", + "hs_phy_2", + "dp_hs_phy_1", + "dm_hs_phy_1", + "dp_hs_phy_2", + "dm_hs_phy_2", + "ss_phy_1", + "ss_phy_2"; + + resets = <&gcc GCC_USB30_MP_BCR>; + power-domains = <&gcc GCC_USB30_MP_GDSC>; + + iommus = <&apps_smmu 0xda0 0x0>; + + phys = <&usb_mp_hsphy0>, + <&usb_mp_qmpphy0>, + <&usb_mp_hsphy1>, + <&usb_mp_qmpphy1>; + phy-names = "usb2-0", + "usb3-0", + "usb2-1", + "usb3-1"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode = "host"; + + status = "disabled"; + }; + + dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; From 9af3242e3183837d25c39a9dc9124cdd1dc0c036 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Mon, 23 Feb 2026 17:37:45 +0200 Subject: [PATCH 0314/1330] FROMLIST: arm64: dts: qcom: glymur-crd: Enable USB support The Qualcomm Glymur Compute Reference Device comes with 3 Type-C ports, one USB Type-A, and a fingerprint reader connected over USB. Each of these 3 Type-C ports are connected to one of the USB combo PHYs and one of the M31 eUSB2 PHYs. The Type-A is connected to the USB Multi-port controller via one of the M31 eUSB2 PHYs and one USB3 UNI PHY. The fingerprint reader is connected to the USB_2 controller. All M31 eUSB2 PHYs have associated eUSB2 to USB 2.0 repeaters, which are either part of SMB2370 PMICs or dedicated NXP PTN3222. So enable all needed controllers, PHYs and repeaters, while describing their supplies. Also describe the PMIC glink graph for Type-C connectors. Link: https://lore.kernel.org/linux-arm-msm/20260223-dts-qcom-glymur-add-usb-support-v2-1-f4e0f38db21d@oss.qualcomm.com/ Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Tested-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 286 ++++++++++++++++++++++++ 1 file changed, 286 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 8779453190122..02e9520028a41 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -60,6 +60,97 @@ }; }; + pmic-glink { + compatible = "qcom,glymur-pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in2: endpoint { + remote-endpoint = <&usb_2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in2: endpoint { + remote-endpoint = <&usb_2_qmpphy_out>; + }; + }; + }; + }; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -367,6 +458,48 @@ }; }; +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + ptn3222_0: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; + + ptn3222_1: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; + + ptn3222_2: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -485,6 +618,21 @@ status = "okay"; }; +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&smb2370_l_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ @@ -596,3 +744,141 @@ bias-disable; }; }; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l3f_e0_0p72>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l1h_e0_0p89>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in2>; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l4c_e1_0p72>; + vdda12-supply = <&vreg_l4f_e1_1p08>; + + phys = <&smb2370_l_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_2_qmpphy { + vdda-phy-supply = <&vreg_l4f_e1_1p08>; + vdda-pll-supply = <&vreg_l4c_e1_0p72>; + refgen-supply = <&vreg_l1c_e1_0p82>; + + status = "okay"; +}; + +&usb_2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in2>; +}; + +&usb_hs { + status = "okay"; +}; + +&usb_hs_phy { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_2>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_0>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_1>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; From 877c3514f0e6202dedef9880fbff09b2b102be29 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 10 Feb 2026 23:37:59 +0530 Subject: [PATCH 0315/1330] FROMLIST: arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes. Link: https://lore.kernel.org/lkml/20260129001358.770053-5-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 286 +++++++++++++++++++++++++++ 1 file changed, 286 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 2aa9af8c96ce6..451b642e99549 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3594,6 +3594,122 @@ #mbox-cells = <2>; }; + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + iommus = <&apps_smmu 0x1000 0x0>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <2>; + + label = "lpass"; + + fastrpc { + compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + iommus = <&apps_smmu 0x1008 0x80>, + <&apps_smmu 0x1048 0x20>; + dma-coherent; + }; + }; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,glymur-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -5373,6 +5489,176 @@ #interconnect-cells = <2>; }; + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x10000>; + + iommus = <&apps_smmu 0x2000 0x400>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + + iommus = <&apps_smmu 0x2001 0x440>, + <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x19c1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + + iommus = <&apps_smmu 0x2002 0x440>, + <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x2003 0x440>, + <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x2004 0x440>, + <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x2005 0x440>, + <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x2006 0x440>, + <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x2007 0x440>, + <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + iommus = <&apps_smmu 0x2008 0x440>, + <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + /* note: compute-cb@9 is secure */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + + iommus = <&apps_smmu 0x200c 0x440>, + <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + + iommus = <&apps_smmu 0x200d 0x440>, + <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + + iommus = <&apps_smmu 0x200e 0x440>, + <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; + }; + }; + }; + imem: sram@81e08000 { compatible = "mmio-sram"; reg = <0x0 0x81e08600 0x0 0x300>; From 2f813131b08f6bbf1303d13d8c085dbba37d7f75 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 10 Feb 2026 23:40:07 +0530 Subject: [PATCH 0316/1330] FROMLIST: arm64: dts: qcom: glymur-crd: Enable ADSP and CDSP Enable ADSP and CDSP on Glymur CRD board. Link: https://lore.kernel.org/lkml/20260129001358.770053-6-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 02e9520028a41..b98f28ba482b7 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -633,6 +633,20 @@ vdd3-supply = <&vreg_l7b_e0_2p79>; }; +&remoteproc_adsp { + firmware-name = "qcom/glymur/adsp.mbn", + "qcom/glymur/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/cdsp.mbn", + "qcom/glymur/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ From 8938fa57a04b46822b14757e3037ddd5f54c4f3a Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 25 Feb 2026 15:54:41 +0530 Subject: [PATCH 0317/1330] PENDING: arm64: dts: qcom: glymur: Describe display related nodes The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort controllers. Describe them along with display controller and the eDP PHY. Then, attach the combo PHYs link and vco_div clocks to the Display clock controller and link up the PHYs and DP endpoints in the graph. Signed-off-by: Abel Vesa Signed-off-by: Abel Vesa Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 431 ++++++++++++++++++++++++++- 1 file changed, 423 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 451b642e99549..99c2f725edf6b 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2434,6 +2434,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2507,10 +2508,32 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; }; }; }; }; + mdss_dp3_phy: phy@faac00 { + compatible = "qcom,glymur-dp-phy"; + reg = <0 0x00faac00 0 0x1d0>, + <0 0x00faa400 0 0x128>, + <0 0x00faa800 0 0x128>, + <0 0x00faa000 0 0x358>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; cnoc_main: interconnect@1500000 { compatible = "qcom,glymur-cnoc-main"; @@ -3799,6 +3822,7 @@ reg = <2>; usb_2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; }; }; }; @@ -4163,20 +4187,411 @@ status = "disabled"; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,glymur-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1de0 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,glymur-dpu"; + reg = <0 0x0ae01000 0 0x93000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-205000000 { + opp-hz = /bits/ 64 <205000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0xc0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x9c>, + <0x0 0xaf57000 0x0 0x9c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@af5c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf5c000 0x0 0x104>, + <0x0 0xaf5c200 0x0 0xc0>, + <0x0 0xaf5d000 0x0 0x770>, + <0x0 0xaf5e000 0x0 0x9c>, + <0x0 0xaf5f000 0x0 0x9c>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp2: displayport-controller@af64000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af64000 0x0 0x104>, + <0x0 0x0af64200 0x0 0xc0>, + <0x0 0x0af65000 0x0 0x770>, + <0x0 0x0af66000 0x0 0x9c>, + <0x0 0x0af67000 0x0 0x9c>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb_2_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp3: displayport-controller@af6c000 { + compatible = "qcom,glymur-dp"; + reg = <0 0x0af6c000 0 0x200>, + <0 0x0af6c200 0 0x200>, + <0 0x0af6d000 0 0xc00>, + <0 0x0af6e000 0 0x400>, + <0 0x0af6f000 0 0x400>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + }; + }; + }; + }; + }; dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, /* dp0 */ - <0>, - <0>, /* dp1 */ - <0>, - <0>, /* dp2 */ - <0>, - <0>, /* dp3 */ - <0>, + <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>, <0>, /* dsi0 */ <0>, <0>, /* dsi1 */ From 5c2c02651267d48218a61133d0ff38294c297103 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 27 Jan 2026 18:04:09 +0530 Subject: [PATCH 0318/1330] PENDING: arm64: dts: qcom: glymur-crd: Enable eDP display support Enable the MDSS (Mobile Display SubSystem) along with the 3rd DisplayPort controller and its PHY in order to bring support for the panel on Glymur CRD platform. Also describe the voltage regulator needed by the eDP panel. Signed-off-by: Abel Vesa Signed-off-by: Pankaj Patil Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 71 +++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index b98f28ba482b7..8767431055038 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -151,6 +151,22 @@ }; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -500,6 +516,47 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna60cl08", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p83>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -652,6 +709,20 @@ <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; From 0c6e36e02e94e3d585bfa885b5b6c0b66ec50538 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 1 Oct 2025 12:00:56 +0300 Subject: [PATCH 0319/1330] PENDING: arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen Enable keyboard, trackpad and touchscreen Signed-off-by: Abel Vesa Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 8767431055038..23d21481f9261 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include + #include "glymur.dtsi" #include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ #include "pmh0101.dtsi" /* SPMI0: SID-1 */ @@ -167,6 +169,23 @@ regulator-boot-on; }; + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -474,6 +493,44 @@ }; }; +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + &i2c5 { clock-frequency = <400000>; @@ -516,6 +573,26 @@ }; }; +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + &mdss { status = "okay"; }; @@ -666,6 +743,19 @@ }; }; +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + &pmk8850_rtc { qcom,no-alarm; }; @@ -746,6 +836,33 @@ }; }; + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + pcie5_default: pcie5-default-state { clkreq-n-pins { pins = "gpio153"; From 751b9b7b736c150ccc378cd39a5f9bda25158f0d Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 25 Feb 2026 18:16:38 +0530 Subject: [PATCH 0320/1330] FROMLIST: arm64: dts: qcom: Add support for MM clock controllers for Glymur Add the device nodes for the multimedia clock controllers videocc, gpucc and gxclkctl. Link: https://lore.kernel.org/r/20260220-glymur_mmcc_dt_config-v1-1-e0e2f43a32af@oss.qualcomm.com Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 99c2f725edf6b..9978ad1c177e7 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5,7 +5,10 @@ #include #include +#include #include +#include +#include #include #include #include @@ -3606,6 +3609,30 @@ #interconnect-cells = <2>; }; + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,glymur-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + + + gpucc: clock-controller@3d90000 { + compatible = "qcom,glymur-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; ipcc: mailbox@3e04000 { compatible = "qcom,glymur-ipcc", "qcom,ipcc"; reg = <0x0 0x03e04000 0x0 0x1000>; @@ -4579,6 +4606,22 @@ }; }; + videocc: clock-controller@0aaf0000 { + compatible = "qcom,glymur-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; From f1f5e2d838dca17bf6b46119077348851e39dcf0 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Wed, 25 Feb 2026 18:34:51 +0530 Subject: [PATCH 0321/1330] PENDING: arm64: dts: qcom: Add Glymur GPU support The Adreno X2 series GPU present in Glymur SoC belongs to the A8x family. It is a new HW IP with architectural improvements as well as different set of hw configs like GMEM, num SPs, Caches sizes etc. Add the GPU and GMU nodes to describe this hardware. Signed-off-by: Akhil P Oommen Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 168 +++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 9978ad1c177e7..5ad1aac6fc4ab 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3621,6 +3621,174 @@ }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-44070001", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x2000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + }; + + opp-572000000 { + opp-hz = /bits/ 64 <572000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xe02d5ffd>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xa82e5ffd>; + }; + + opp-915000000 { + opp-hz = /bits/ 64 <915000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882d5ffd>; + }; + + opp-1070000000 { + opp-hz = /bits/ 64 <1070000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882b5ffd>; + }; + + opp-1185000000 { + opp-hz = /bits/ 64 <1185000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1550000000 { + opp-hz = /bits/ 64 <1550000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xa8295ffd>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x88295ffd>; + }; + + opp-1850000000 { + opp-hz = /bits/ 64 <1850000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x88285ffd>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"; + + reg = <0x0 0x03d37000 0x0 0x68000>; + reg-names = "gmu"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "memnoc", + "hub"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, <&gpucc GPU_CC_CX_GDSC>; + //<&gxclkctl GX_CLKCTL_GX_GDSC>; TODO: + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + opp-level = ; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + }; + + opp-725000000 { + opp-hz = /bits/ 64 <725000000>; + opp-level = ; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,glymur-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; From d6f26bc17e70d0d02299de60c3b1ee9d2b5f188f Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Wed, 25 Feb 2026 18:38:32 +0530 Subject: [PATCH 0322/1330] PENDING: arm64: dts: qcom: glymur: Add GPU smmu nodes Add the nodes to describe GPU smmu Signed-off-by: Rajendra Nayak Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 5ad1aac6fc4ab..dd1052e787f72 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3801,6 +3801,46 @@ #reset-cells = <1>; #power-domain-cells = <1>; }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + interconnects = <&hsc_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; + dma-coherent; + }; + ipcc: mailbox@3e04000 { compatible = "qcom,glymur-ipcc", "qcom,ipcc"; reg = <0x0 0x03e04000 0x0 0x1000>; From 80b9a5603b762dd4b709de195dd0a4e2ad0845ad Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 12 Feb 2026 06:15:50 +0530 Subject: [PATCH 0323/1330] PENDING: arm64: dts: glymur: Add LPASS macro codecs and pinctrl Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur. for proper sound support. Also add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Srinivas Kandagatla Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 263 +++++++++++++++++++++++++++ 1 file changed, 263 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index dd1052e787f72..7ad5dd7337e05 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -20,7 +20,9 @@ #include #include #include +#include #include +#include #include #include "glymur-ipcc.h" @@ -3965,6 +3967,267 @@ dma-coherent; }; }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1061 0x20>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + + lpass_vamacro: codec@7660000 { + compatible = "qcom,glymur-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; + reg = <0 0x07660000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_wsamacro: codec@6c90000 { + compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0 0x06c90000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA"; + }; + + swr0: soundwire@6c80000 { + compatible = "qcom,soundwire-v3.1.0"; + reg = <0 0x06c80000 0 0x10000>; + interrupts = ; + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + label = "WSA"; + + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_wsa2macro: codec@6cb0000 { + compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0 0x06cb0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA2"; + }; + + swr3: soundwire@6ca0000 { + compatible = "qcom,soundwire-v3.1.0"; + reg = <0 0x06ca0000 0 0x10000>; + interrupts = ; + clocks = <&lpass_wsa2macro>; + clock-names = "iface"; + label = "WSA2"; + + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,glymur-lpass-lpi-pinctrl", "qcom,sm8650-lpass-lpi-pinctrl"; + reg = <0 0x07760000 0 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; }; }; From 8850cc645de98993213b4b72da2249f0d1878107 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 19 Feb 2026 14:53:58 +0530 Subject: [PATCH 0324/1330] PENDING: arm64: dts: qcom: glymur-crd: add Audio sound card node Add the sound card of Glymur-crd board with the routing for Speakers. Add device nodes for the sound support with WSA884x smart speakers and playback via speakers and recording via DMIC microphones. Co-developed-by: Mohammad Rafi Shaik Signed-off-by: Mohammad Rafi Shaik Tested-by: Mohammad Rafi Shaik Signed-off-by: Srinivas Kandagatla Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 110 ++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 23d21481f9261..d1d641d54d6df 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -247,6 +247,54 @@ pinctrl-0 = <&wwan_reg_en>; pinctrl-names = "default"; }; + + sound { + compatible = "qcom,glymur-sndcard"; + model = "GLYMUR-CRD"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; }; &apps_rsc { @@ -634,6 +682,12 @@ status = "okay"; }; +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + qcom,dmic-sample-rate = <4800000>; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -780,6 +834,62 @@ vdd3-supply = <&vreg_l7b_e0_2p79>; }; +&swr0 { + status = "okay"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + &remoteproc_adsp { firmware-name = "qcom/glymur/adsp.mbn", "qcom/glymur/adsp_dtb.mbn"; From 399097de267894662364c7990aed9438314e1304 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 12 Feb 2026 14:30:53 +0800 Subject: [PATCH 0325/1330] WORKAROUND: arm64: dts: qcom: glymur: Add refgen and qref supplies for PCIe PHY on Glymur Add refgen and qref power supplies in each pcie phy devicetree node. For some instance, refgen and qref may share LDOs with phy LDOs, so add additional power supplies. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index d1d641d54d6df..08867176cc3bd 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -700,6 +700,10 @@ &pcie3b_phy { vdda-phy-supply = <&vreg_l3c_e1_0p89>; vdda-pll-supply = <&vreg_l2c_e1_1p14>; + vdda-qref-supply = <&vreg_l1f_e1_0p82>; + vdda-qref2-supply = <&vreg_l2f_e1_0p83>; + vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>; + vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>; status = "okay"; }; @@ -722,6 +726,8 @@ vdda-phy-supply = <&vreg_l1c_e1_0p82>; vdda-pll-supply = <&vreg_l4f_e1_1p08>; + vdda-qref-supply = <&vreg_l1f_e1_0p82>; + vdda-qref2-supply = <&vreg_l2f_e1_0p83>; status = "okay"; }; @@ -743,6 +749,7 @@ vdda-phy-supply = <&vreg_l2f_e0_0p82>; vdda-pll-supply = <&vreg_l4h_e0_1p2>; + vdda-qref-supply = <&vreg_l3f_e0_0p72>; status = "okay"; }; @@ -764,6 +771,8 @@ vdda-phy-supply = <&vreg_l1c_e1_0p82>; vdda-pll-supply = <&vreg_l4f_e1_1p08>; + vdda-qref-supply = <&vreg_l1f_e1_0p82>; + vdda-qref2-supply = <&vreg_l2f_e1_0p83>; status = "okay"; }; From b4971d6d5d7241db5f138efec5dab7308c070396 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Wed, 4 Mar 2026 10:17:04 +0530 Subject: [PATCH 0326/1330] FROMLIST: arm64: dts: qcom: glymur: Add remoteproc for SoCCP Add remoteproc PAS loader for SoCCP Link: https://patchwork.kernel.org/project/linux-arm-msm/patch/20250925-v3_glymur_introduction-v1-24-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Sibi Sankar Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 7 ++++ arch/arm64/boot/dts/qcom/glymur.dtsi | 53 +++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 08867176cc3bd..6ceaa44028790 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -913,6 +913,13 @@ status = "okay"; }; +&remoteproc_soccp { + firmware-name = "qcom/glymur/soccp.mbn", + "qcom/glymur/soccp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 7ad5dd7337e05..b2e114337b246 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2269,6 +2269,59 @@ }; }; + remoteproc_soccp: remoteproc-soccp@d00000 { + compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas"; + reg = <0x0 0x00d00000 0x0 0x200000>; + + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "pong", + "wake-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + memory-region = <&soccp_mem>, + <&soccpdtb_mem>; + + qcom,smem-states = <&soccp_smp2p_out 0>, + <&soccp_smp2p_out 10>, + <&soccp_smp2p_out 9>, + <&soccp_smp2p_out 8>; + qcom,smem-state-names = "stop", + "wakeup", + "sleep", + "ping"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <19>; + label = "soccp"; + + }; + }; + usb_hs_phy: phy@fa0000 { compatible = "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; From 6771a0a05c55f34716ed44998d52090428a31c9e Mon Sep 17 00:00:00 2001 From: Pragnesh Papaniya Date: Wed, 4 Mar 2026 13:35:14 +0530 Subject: [PATCH 0327/1330] FROMLIST: arm64: dts: qcom: glymur: Add glymur BWMONs Add the CPU BWMON nodes for glymur SoCs. Link: https://lore.kernel.org/linux-arm-msm/20260302-glymur_bwmon_dt-v1-1-f4939d75bd47@oss.qualcomm.com/ Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 87 ++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index b2e114337b246..48adc83c9aff7 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2593,6 +2593,93 @@ status = "disabled"; }; + /* cluster0 */ + bwmon_cluster0: pmu@100c400 { + compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x0100c400 0x0 0x600>; + + interrupts = ; + + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000>; + }; + + opp-1 { + opp-peak-kBps = <2188800>; + }; + + opp-2 { + opp-peak-kBps = <5414400>; + }; + + opp-3 { + opp-peak-kBps = <6220800>; + }; + + opp-4 { + opp-peak-kBps = <6835200>; + }; + + opp-5 { + opp-peak-kBps = <8371200>; + }; + + opp-6 { + opp-peak-kBps = <10944000>; + }; + + opp-7 { + opp-peak-kBps = <12748800>; + }; + + opp-8 { + opp-peak-kBps = <14745600>; + }; + + opp-9 { + opp-peak-kBps = <16896000>; + }; + + opp-10 { + opp-peak-kBps = <19046400>; + }; + }; + }; + + /* cluster1 */ + bwmon_cluster1: pmu@100d400 { + compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x0100d400 0x0 0x600>; + + interrupts = ; + + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + /* cluster2 */ + bwmon_cluster2: pmu@100e400 { + compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x0100e400 0x0 0x600>; + + interrupts = ; + + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,glymur-cnoc-main"; reg = <0x0 0x01500000 0x0 0x17080>; From 44762eacc4bf800b04ed7ded9b0883ec134b78d1 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Tue, 10 Mar 2026 12:19:00 +0530 Subject: [PATCH 0328/1330] PENDING: arm64: dts: qcom: glymur: Upgrade dispcc opp entry to turbo Switch opp entry for dispcc to turbo Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 48adc83c9aff7..4416229911ba7 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5255,7 +5255,7 @@ <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_turbo>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From f0875ab52e88321ef902c43a28862714fb8ee031 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 4 Mar 2026 00:02:20 -0800 Subject: [PATCH 0329/1330] FROMLIST: arch: arm64: dts: qcom: Add support for PCIe3a Describe PCIe3a controller and PHY. Also add required system resources like regulators, clocks, interrupts and registers configuration for PCIe3a. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-5-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur.dtsi | 314 ++++++++++++++++++++++++++- 1 file changed, 313 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 4416229911ba7..4886e87ebd490 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -741,7 +741,7 @@ <0>, /* USB 2 Phy PCIE PIPEGMUX */ <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ - <0>, /* PCIe 3a */ + <&pcie3a_phy>, /* PCIe 3a */ <&pcie3b_phy>, /* PCIe 3b */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ @@ -2776,6 +2776,318 @@ #interconnect-cells = <2>; }; + pcie3a: pci@1c10000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x70000000 0x0 0xf20>, + <0x0 0x70000f40 0x0 0xa8>, + <0x0 0x70001000 0x0 0x4000>, + <0x0 0x70100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>, + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>; + bus-range = <0 0xff>; + + dma-coherent; + + linux,pci-domain = <3>; + num-lanes = <8>; + + operating-points-v2 = <&pcie3a_opp_table>; + + msi-map = <0x0 &gic_its 0xb0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x30000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 848 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 849 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 850 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 851 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_3A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3A QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_3A_BCR>, + <&gcc GCC_PCIE_3A_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_3A_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie3a_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* GEN 1 x8 */ + opp-20000000-1 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x8 */ + opp-40000000-2 { + opp-hz = /bits/ 64 <40000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <4000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* GEN 3 x8 */ + opp-64000000-3 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* GEN 4 x8 */ + opp-128000000-4 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <15753000 1>; + opp-level = <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + opp-level = <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + opp-level = <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <15753000 1>; + opp-level = <5>; + }; + + /* GEN 5 x8 */ + opp-256000000-5 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <31506000 1>; + opp-level = <5>; + }; + }; + + pcie3a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie3a_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie3a_phy: phy@f00000 { + compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg = <0 0x00f00000 0 0x10000>; + + clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "phy_b_aux"; + + resets = <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr", + "phy_b", + "phy_b_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie3a_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + pcie4: pci@1bf0000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; From 79706fb5b35b53525b67be374fc8fe32727f0ab4 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Nandam Date: Wed, 21 Jan 2026 15:56:06 +0530 Subject: [PATCH 0330/1330] FROMLIST: arm64: defconfig: Enable Qualcomm WCD937x headphone codec as module Enable the Qualcomm WCD937x headphone audio codec as a loadable module, as it is now required on the QCM6490 IDP platform. Link: https://lore.kernel.org/all/20260121102606.1753970-1-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e1e67dd61fb3c..3537fd0e2eef6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1163,6 +1163,7 @@ CONFIG_SND_SOC_TLV320AIC32X4_I2C=m CONFIG_SND_SOC_TLV320AIC3X_I2C=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WCD937X_SDW=m CONFIG_SND_SOC_WCD939X_SDW=m CONFIG_SND_SOC_WM8524=m CONFIG_SND_SOC_WM8904=m From 6012d43022b869d158849c5ed6e460f88bf2def3 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Mon, 2 Mar 2026 18:33:59 +0530 Subject: [PATCH 0331/1330] QCLINUX: qcom.config: enable CONFIG_CMA for qcom chipsets CMA imposes system-wide memory constraints by reserving boot-time memory and restricting it to movable allocations. This alters allocator behavior even when CMA is not explicitly used. Since CMA sizing and applicability are platform-specific, mm/Kconfig intentionally provides no default opt-in for CONFIG_CMA. Enable CONFIG_CMA for all qcom chipsets Signed-off-by: Bibek Kumar Patro bibek.patro@oss.qualcomm.com --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 54195f5b6277a..83aaf47886dba 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -11,6 +11,7 @@ CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_CFG80211_CERTIFICATION_ONUS=y +CONFIG_CMA=y CONFIG_CONNECTOR=y CONFIG_CORESIGHT_CORESIGHT_TNOC=m CONFIG_CORESIGHT_CTCU=m From f374811af5b6eab1621c0b82b65c2120d1df3803 Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Mon, 2 Mar 2026 16:36:16 +0530 Subject: [PATCH 0332/1330] QCLINUX: arm64: dts: qcom: add labels to sensor DTSI Add DT labels to sensor nodes in the Lemans and Kodiak DTSI files to enable phandle references. Monaco changes are already handled. Signed-off-by: Nihal Kumar Gupta --- arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi | 8 ++++---- .../boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi index 2a650bc52d1fc..e1ee2ba8c78e6 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi @@ -125,7 +125,7 @@ }; /*cam0a-ov9282*/ - qcom,cam-sensor1 { + rb8_slot0: qcom,cam-sensor1 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <0>; sensor-position-roll = <0>; @@ -439,7 +439,7 @@ }; /*cam1-ov9282*/ - qcom,cam-sensor21 { + rb8_slot1: qcom,cam-sensor21 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <1>; sensor-position-roll = <0>; @@ -755,7 +755,7 @@ }; /*cam2-ov9282*/ - qcom,cam-sensor22 { + rb8_slot2: qcom,cam-sensor22 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; sensor-position-roll = <0>; @@ -994,7 +994,7 @@ }; /*cam3-ov9282*/ - qcom,cam-sensor23 { + rb8_slot3: qcom,cam-sensor23 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <3>; sensor-position-roll = <0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi index 8b75b1a441db4..026b97b58377d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-camera-sensor.dtsi @@ -55,7 +55,7 @@ }; /*cam0a-ov9282*/ - qcom,cam-sensor1 { + rb3_slot0a: qcom,cam-sensor1 { compatible = "qcom,cam-sensor"; cell-index = <1>; csiphy-sd-index = <0>; @@ -92,7 +92,7 @@ }; /*cam1-ov9282*/ - qcom,cam-sensor6 { + rb3_slot1: qcom,cam-sensor6 { compatible = "qcom,cam-sensor"; cell-index = <6>; csiphy-sd-index = <1>; @@ -254,7 +254,7 @@ }; /*cam3-imx577*/ - qcom,cam-sensor0 { + rb3_slot3: qcom,cam-sensor0 { compatible = "qcom,cam-sensor"; cell-index = <0>; csiphy-sd-index = <3>; @@ -345,7 +345,7 @@ }; /*cam0b-ov9282*/ - qcom,cam-sensor7 { + rb3_slot0b: qcom,cam-sensor7 { compatible = "qcom,cam-sensor"; cell-index = <7>; csiphy-sd-index = <0>; @@ -383,7 +383,7 @@ }; /*cam2-imx577*/ - qcom,cam-sensor8 { + rb3_slot2: qcom,cam-sensor8 { compatible = "qcom,cam-sensor"; cell-index = <8>; csiphy-sd-index = <2>; From 1de044c76ecba6c282c1904bd78e8d62c3933b2d Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 27 Jan 2026 14:31:16 +0530 Subject: [PATCH 0333/1330] FROMLIST: arm64: dts: qcom: qcs8300: Add clocks for QoS configuration Add clocks which need to be enabled for configuring QoS on qcs8300 SoC. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260127090116.1438780-4-odelu.kukatla@oss.qualcomm.com From 205cf557d68fc1c88114065a98084af42e31e9b9 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 26 Feb 2026 01:13:41 -0800 Subject: [PATCH 0334/1330] FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode The Glymur SoC has pcie3a and pcie3b PHYs that can operate in two modes: 1. Independent 4-lane mode: Each PHY operates as a separate PCIe Gen5 4-lane interface, compatible with qcom,glymur-qmp-gen5x4-pcie-phy 2. Bifurcation mode (8-lane): pcie3a phy acts as leader and pcie3b phy as follower to form a single 8-lane PCIe Gen5 interface In bifurcation mode, the hardware design requires controlling additional resources beyond the standard pcie3a PHY configuration: - pcie3b's aux_clk (phy_b_aux) - pcie3b's phy_gdsc power domain - pcie3b's bcr/nocsr reset Add qcom,glymur-qmp-gen5x8-pcie-phy compatible string to document this 8-lane bifurcation configuration. The phy_b_aux clock is used as the 6th clock instead of pipediv2, requiring the clock-names enum to be extended to support both [phy_b_aux, pipediv2] options at index 5. This follows the existing pattern used for [rchng, refgen] clocks at index 3. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-1-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu --- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 46 +++++++++++++++---- 1 file changed, 37 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 83df98c352702..25717bc9be988 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -68,20 +69,23 @@ properties: - const: ref - enum: [rchng, refgen] - const: pipe - - const: pipediv2 + - enum: [phy_b_aux, pipediv2] power-domains: - maxItems: 1 + minItems: 1 + maxItems: 2 resets: minItems: 1 - maxItems: 2 + maxItems: 4 reset-names: minItems: 1 items: - const: phy - const: phy_nocsr + - const: phy_b + - const: phy_b_nocsr vdda-phy-supply: true @@ -183,7 +187,7 @@ allOf: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy - - qcom,kaanapali-qmp-gen3x2-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy @@ -202,6 +206,17 @@ allOf: clock-names: minItems: 6 + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + power-domains: + minItems: 2 + - if: properties: compatible: @@ -224,11 +239,24 @@ allOf: reset-names: minItems: 2 else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 + if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + resets: + minItems: 4 + reset-names: + minItems: 4 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 - if: properties: From 9f52061c83058019d00a0d6b42679221f049e460 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 4 Dec 2025 18:53:17 -0800 Subject: [PATCH 0335/1330] FROMLIST: phy: qcom: qmp-pcie: Add multiple power-domains support The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in a bifurcated configuration. Each PHY has its own power domain (phy_gdsc) that must be powered on before initialization per hardware requirements. Current PHY power management assumes a single power domain per PHY, preventing proper setup for this dual-PHY scenario. Add support for multiple power domains by using devm_pm_domain_attach_list() to attach power domains manually, while maintaining compatibility with single power domain PHYs. Enable runtime PM to allow power domain control when the PCIe driver calls phy_power_on/phy_power_off: - Single power domain: QMP PHY platform device directly attaches to power domain and controls it during runtime resume/suspend - Multiple power domains: devm_pm_domain_attach_list() creates virtual devices as power domain suppliers, linked to the QMP PHY platform device as consumer This ensures power domains are properly attached and turned on/off for both single and multiple power domain configurations. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-2-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index fed2fc9bb3110..7369c291be51a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -3334,6 +3335,8 @@ struct qmp_pcie { struct clk_fixed_rate pipe_clk_fixed; struct clk_fixed_rate aux_clk_fixed; + + struct dev_pm_domain_list *pd_list; }; static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val) @@ -5348,6 +5351,16 @@ static int qmp_pcie_probe(struct platform_device *pdev) WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); WARN_ON_ONCE(!qmp->cfg->phy_status); + ret = devm_pm_domain_attach_list(dev, NULL, &qmp->pd_list); + if (ret < 0 && ret != -EEXIST) { + dev_err(dev, "Failed to attach power domain\n"); + return ret; + } + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + ret = qmp_pcie_clk_init(qmp); if (ret) return ret; From 65f16d9ee2eb73fc83a5da7217a971bdaae17118 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 23 Oct 2025 06:15:38 -0700 Subject: [PATCH 0336/1330] FROMLIST: phy: qcom: qmp-pcie: Support multiple nocsr resets Refactor nocsr reset handling to support multiple nocsr resets required for PHY configurations with bifurcated operation modes. The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in bifurcation, where each PHY requires its own nocsr reset to be controlled simultaneously. The current implementation only supports a single nocsr reset per PHY configuration. Add num_nocsr and nocsr_list fields to struct qmp_phy_cfg to represent the number and names of a group of nocsr reset names. Initialize these fields for all PHYs that have nocsr resets, allowing the driver to correctly acquire multiple nocsr resets during probe and control them as an array by using reset_control_bulk APIs. The refactoring maintains backward compatibility for existing single nocsr reset configurations while enabling support for multi-PHY scenarios like Glymur's 8-lane bifurcation mode. Additionally, introduces x1e80100_qmp_gen3x2_pciephy_cfg as a separate configuration from sm8550_qmp_gen3x2_pciephy_cfg since the x1e80100 Gen3x2 PHY requires nocsr reset support while the sm8550 Gen3x2 PHY does not. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-3-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 85 +++++++++++++++++++++--- 1 file changed, 75 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 7369c291be51a..c9dac005a344a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3281,6 +3281,11 @@ struct qmp_phy_cfg { /* resets to be requested */ const char * const *reset_list; int num_resets; + + /* nocsr resets to be requested */ + const char * const *nocsr_reset_list; + int num_nocsr_resets; + /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -3327,7 +3332,7 @@ struct qmp_pcie { int num_pipe_clks; struct reset_control_bulk_data *resets; - struct reset_control *nocsr_reset; + struct reset_control_bulk_data *nocsr_reset; struct regulator_bulk_data *vregs; struct phy *phy; @@ -3394,6 +3399,10 @@ static const char * const sdm845_pciephy_reset_l[] = { "phy", }; +static const char * const sm8550_pciephy_nocsr_reset_l[] = { + "phy_nocsr", +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { .serdes = 0, .pcs = 0x1800, @@ -4350,6 +4359,8 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { }, .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, @@ -4382,6 +4393,8 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { }, .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, @@ -4482,6 +4495,35 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { .phy_status = PHYSTATUS_4_20, }; +static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v5, + + .tbls = { + .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_v5_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .lanes = 2, @@ -4504,6 +4546,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, @@ -4537,6 +4581,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, @@ -4568,6 +4614,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, @@ -4583,6 +4631,8 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, @@ -4626,6 +4676,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), @@ -4642,6 +4694,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), @@ -4770,7 +4824,7 @@ static int qmp_pcie_init(struct phy *phy) } } - ret = reset_control_assert(qmp->nocsr_reset); + ret = reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset); if (ret) { dev_err(qmp->dev, "no-csr reset assert failed\n"); goto err_assert_reset; @@ -4807,7 +4861,7 @@ static int qmp_pcie_exit(struct phy *phy) const struct qmp_phy_cfg *cfg = qmp->cfg; if (qmp->nocsr_reset) - reset_control_assert(qmp->nocsr_reset); + reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset); else reset_control_bulk_assert(cfg->num_resets, qmp->resets); @@ -4851,7 +4905,7 @@ static int qmp_pcie_power_on(struct phy *phy) if (ret) return ret; - ret = reset_control_deassert(qmp->nocsr_reset); + ret = reset_control_bulk_deassert(cfg->num_nocsr_resets, qmp->nocsr_reset); if (ret) { dev_err(qmp->dev, "no-csr reset deassert failed\n"); goto err_disable_pipe_clk; @@ -5000,14 +5054,25 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) for (i = 0; i < cfg->num_resets; i++) qmp->resets[i].id = cfg->reset_list[i]; - ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, + qmp->resets); if (ret) return dev_err_probe(dev, ret, "failed to get resets\n"); - qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr"); - if (IS_ERR(qmp->nocsr_reset)) - return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), - "failed to get no-csr reset\n"); + if (!cfg->num_nocsr_resets) + return 0; + qmp->nocsr_reset = devm_kcalloc(dev, cfg->num_nocsr_resets, + sizeof(*qmp->nocsr_reset), GFP_KERNEL); + if (!qmp->nocsr_reset) + return -ENOMEM; + + for (i = 0; i < cfg->num_nocsr_resets; i++) + qmp->nocsr_reset[i].id = cfg->nocsr_reset_list[i]; + + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_nocsr_resets, + qmp->nocsr_reset); + if (ret) + return dev_err_probe(dev, ret, "failed to get no-csr reset\n"); return 0; } @@ -5521,7 +5586,7 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { .data = &sm8750_qmp_gen3x2_pciephy_cfg, }, { .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", - .data = &sm8550_qmp_gen3x2_pciephy_cfg, + .data = &x1e80100_qmp_gen3x2_pciephy_cfg, }, { .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", .data = &x1e80100_qmp_gen4x2_pciephy_cfg, From adaba247f62f9cbeb4d874c96f60f9aaa235b848 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 23 Oct 2025 06:15:39 -0700 Subject: [PATCH 0337/1330] FROMLIST: phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur The third PCIe controller on Glymur SoC supports 8-lane operation via bifurcation of two PHYs (each requires separate power domian, resets and aux clk). Add dedicated reset/no_csr reset list ("phy_b", "phy_b_nocsr") and clock ("phy_b_aux") required for 8-lane operation. Introduce new glymur_qmp_gen5x8_pciephy_cfg configuration to enable PCIe Gen5 x8 mode. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-4-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 30 +++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index c9dac005a344a..474a11b15c2a5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3378,7 +3378,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) /* list of clocks required by phy */ static const char * const qmp_pciephy_clk_l[] = { - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "phy_b_aux", }; /* list of regulators */ @@ -3403,6 +3403,14 @@ static const char * const sm8550_pciephy_nocsr_reset_l[] = { "phy_nocsr", }; +static const char * const glymur_pciephy_reset_l[] = { + "phy", "phy_b" +}; + +static const char * const glymur_pciephy_nocsr_reset_l[] = { + "phy_nocsr", "phy_b_nocsr", +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { .serdes = 0, .pcs = 0x1800, @@ -4705,6 +4713,23 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { .phy_status = PHYSTATUS_4_20, }; +static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg = { + .lanes = 8, + + .offsets = &qmp_pcie_offsets_v8_50, + + .reset_list = glymur_pciephy_reset_l, + .num_resets = ARRAY_SIZE(glymur_pciephy_reset_l), + .nocsr_reset_list = glymur_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(glymur_pciephy_nocsr_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + + .regs = pciephy_v8_50_regs_layout, + + .phy_status = PHYSTATUS_4_20, +}; + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -5482,6 +5507,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy", .data = &glymur_qmp_gen5x4_pciephy_cfg, + }, { + .compatible = "qcom,glymur-qmp-gen5x8-pcie-phy", + .data = &glymur_qmp_gen5x8_pciephy_cfg, }, { .compatible = "qcom,ipq6018-qmp-pcie-phy", .data = &ipq6018_pciephy_cfg, From c9aea145c69b0399700ffbc0374cb243e622bbd2 Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Tue, 10 Mar 2026 17:05:55 +0530 Subject: [PATCH 0338/1330] FROMLIST: dt-bindings: mmc: sdhci-msm: Add ICE phandle Starting with sc7280(kodiak), the ICE will have its own device-tree node. So add the qcom,ice property to reference it. To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE register region in the SDHCI node. Older SoCs without ICE remain valid as no additional requirement is imposed. Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Co-developed-by: Abhinaba Rakshit Signed-off-by: Abhinaba Rakshit Signed-off-by: Neeraj Soni Link: https://lore.kernel.org/all/20260310113557.348502-2-neeraj.soni@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 95 +++++++++++++------ 1 file changed, 67 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 938be8228d668..cc9f7724bdf0e 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -140,6 +140,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: platform specific settings for DLL_CONFIG reg. + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the Inline Crypto Engine (ICE) hardware block for this controller. + iommus: minItems: 1 maxItems: 8 @@ -193,35 +198,69 @@ allOf: enum: - qcom,sdhci-msm-v4 then: - properties: - reg: - minItems: 2 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 2 - items: - - const: hc - - const: core - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + else: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice else: - properties: - reg: - minItems: 1 - items: - - description: Host controller register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 1 - items: - - const: hc - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice unevaluatedProperties: false From acaf62d13154abf5e3e8ce8645366e0e9839aaaf Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Tue, 10 Mar 2026 17:05:56 +0530 Subject: [PATCH 0339/1330] FROMLIST: arm64: dts: qcom: kodiak: enable the inline crypto engine for SDHC Add an ICE node to kodiak SoC description and enable it by adding a phandle to the SDHC node. Signed-off-by: Neeraj Soni Link: https://lore.kernel.org/all/20260310113557.348502-3-neeraj.soni@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index a8f5b50f33cd9..a67a550302c6f 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -1050,6 +1050,8 @@ qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; + qcom,ice = <&sdhc_ice>; + mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; @@ -1076,6 +1078,13 @@ }; }; + sdhc_ice: crypto@7c8000 { + compatible = "qcom,sc7280-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x007c8000 0x0 0x18000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>; + }; + gpi_dma0: dma-controller@900000 { #dma-cells = <3>; compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; From 0d02e3d6b592f713edaf38c192c56675e7339ebd Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Tue, 10 Mar 2026 17:05:57 +0530 Subject: [PATCH 0340/1330] FROMLIST: arm64: dts: qcom: monaco: enable the inline crypto engine for SDHC Add an ICE node to monaco SoC description and enable it by adding a phandle to the SDHC node. Signed-off-by: Neeraj Soni Link: https://lore.kernel.org/all/20260310113557.348502-4-neeraj.soni@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh --- arch/arm64/boot/dts/qcom/monaco.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index dfdf5996be68a..7213c27405e83 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4763,6 +4763,8 @@ supports-cqe; dma-coherent; + qcom,ice = <&sdhc_ice>; + status = "disabled"; sdhc1_opp_table: opp-table { @@ -4790,6 +4792,13 @@ }; }; + sdhc_ice: crypto@87c8000 { + compatible = "qcom,qcs8300-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x087c8000 0x0 0x18000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>; + }; + usb_1_hsphy: phy@8904000 { compatible = "qcom,qcs8300-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; From be092f1feb3899be0b32ab00588b17ce10dae8cc Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Mon, 12 Jan 2026 20:48:47 -0800 Subject: [PATCH 0341/1330] FROMLIST: media: dt-bindings: Add CAMSS device for Kaanapali Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Kaanapali platform. The Kaanapali platform provides: - 3 x VFE (Video Front End), 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite - 3 x CSID (CSI Decoder) - 2 x CSID Lite - 6 x CSIPHY (CSI Physical Layer) - 2 x ICP (Image Control Processor) - 1 x IPE (Image Processing Engine) - 2 x JPEG DMA & Downscaler - 2 x JPEG Encoder - 1 x OFE (Offline Front End) - 5 x RT CDM (Camera Data Mover) - 3 x TPG (Test Pattern Generator) Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260112-kaanapali-camss-v12-1-15b7af73401e@oss.qualcomm.com/ --- .../bindings/media/qcom,kaanapali-camss.yaml | 646 ++++++++++++++++++ 1 file changed, 646 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml new file mode 100644 index 0000000000000..7108a4f12f580 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml @@ -0,0 +1,646 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + Kaanapali camera subsystem includes submodules such as CSIPHY (CSI Physical Layer) + and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol. + + The subsystem also integrates a set of real-time image processing engines and + their associated configuration modules, as well as non-real-time engines. + + Additionally, it encompasses a test pattern generator (TPG) submodule. + +properties: + compatible: + const: qcom,kaanapali-camss + + reg: + items: + - description: Registers for CSID 0 + - description: Registers for CSID 1 + - description: Registers for CSID 2 + - description: Registers for CSID Lite 0 + - description: Registers for CSID Lite 1 + - description: Registers for CSIPHY 0 + - description: Registers for CSIPHY 1 + - description: Registers for CSIPHY 2 + - description: Registers for CSIPHY 3 + - description: Registers for CSIPHY 4 + - description: Registers for CSIPHY 5 + - description: Registers for VFE (Video Front End) 0 + - description: Registers for VFE 1 + - description: Registers for VFE 2 + - description: Registers for VFE Lite 0 + - description: Registers for VFE Lite 1 + - description: Registers for ICP (Imaging Control Processor) 0 + - description: Registers for ICP 0 SYS + - description: Registers for ICP 1 + - description: Registers for ICP 1 SYS + - description: Registers for IPE (Image Processing Engine) + - description: Registers for JPEG DMA & Downscaler + - description: Registers for JPEG Encoder + - description: Registers for OFE (Offline Front End) + - description: Registers for RT CDM (Camera Data Mover) 0 + - description: Registers for RT CDM 1 + - description: Registers for RT CDM 2 + - description: Registers for RT CDM 3 + - description: Registers for RT CDM 4 + - description: Registers for TPG 0 + - description: Registers for TPG 1 + - description: Registers for TPG 2 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: icp0 + - const: icp0_sys + - const: icp1 + - const: icp1_sys + - const: ipe + - const: jpeg_dma + - const: jpeg_enc + - const: ofe + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + clocks: + maxItems: 60 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: camnoc_rt_vfe0 + - const: camnoc_rt_vfe1 + - const: camnoc_rt_vfe2 + - const: camnoc_rt_vfe_lite + - const: cpas_ahb + - const: cpas_fast_ahb + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: gcc_axi_hf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + - const: camnoc_ipe_nps + - const: camnoc_ofe + - const: gcc_axi_sf + - const: icp0 + - const: icp0_ahb + - const: icp1 + - const: icp1_ahb + - const: ipe_nps + - const: ipe_nps_ahb + - const: ipe_nps_fast_ahb + - const: ipe_pps + - const: ipe_pps_fast_ahb + - const: jpeg + - const: ofe_ahb + - const: ofe_anchor + - const: ofe_anchor_fast_ahb + - const: ofe_hdr + - const: ofe_hdr_fast_ahb + - const: ofe_main + - const: ofe_main_fast_ahb + - const: vfe0_bayer + - const: vfe0_bayer_fast_ahb + - const: vfe1_bayer + - const: vfe1_bayer_fast_ahb + - const: vfe2_bayer + - const: vfe2_bayer_fast_ahb + + interrupts: + maxItems: 30 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: camnoc_nrt + - const: camnoc_rt + - const: icp0 + - const: icp1 + - const: jpeg_dma + - const: jpeg_enc + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_mnoc + - const: cam_sf_icp_mnoc + - const: cam_sf_mnoc + + iommus: + items: + - description: VFE non-protected stream + - description: ICP0 shared stream + - description: ICP1 shared stream + - description: IPE CDM non-protected stream + - description: IPE non-protected stream + - description: JPEG non-protected stream + - description: OFE CDM non-protected stream + - description: OFE non-protected stream + - description: VFE / VFE Lite CDM non-protected stream + + power-domains: + items: + - description: + IFE0 GDSC - Global Distributed Switch Controller for IFE0. + - description: + IFE1 GDSC - Global Distributed Switch Controller for IFE1. + - description: + IFE2 GDSC - Global Distributed Switch Controller for IFE2. + - description: + Titan GDSC - Global Distributed Switch Controller for the entire camss. + - description: + IPE GDSC - Global Distributed Switch Controller for IPE. + - description: + OFE GDSC - Block Global Distributed Switch Controller for OFE. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + - const: ipe + - const: ofe + + vdd-csiphy0-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY0 core block. + + vdd-csiphy0-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 pll block. + + vdd-csiphy1-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY1 core block. + + vdd-csiphy1-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY1 pll block. + + vdd-csiphy2-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY2 core block. + + vdd-csiphy2-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 pll block. + + vdd-csiphy3-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY3 core block. + + vdd-csiphy3-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 pll block. + + vdd-csiphy4-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY4 core block. + + vdd-csiphy4-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY4 pll block. + + vdd-csiphy5-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY5 core block. + + vdd-csiphy5-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY5 pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + +patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input ports for receiving CSI data on CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@9253000 { + compatible = "qcom,kaanapali-camss"; + + reg = <0x0 0x09253000 0x0 0x5e80>, + <0x0 0x09263000 0x0 0x5e80>, + <0x0 0x09273000 0x0 0x5e80>, + <0x0 0x092d3000 0x0 0x3880>, + <0x0 0x092e7000 0x0 0x3880>, + <0x0 0x09523000 0x0 0x2000>, + <0x0 0x09525000 0x0 0x2000>, + <0x0 0x09527000 0x0 0x2000>, + <0x0 0x09529000 0x0 0x2000>, + <0x0 0x0952b000 0x0 0x2000>, + <0x0 0x0952d000 0x0 0x2000>, + <0x0 0x09151000 0x0 0x20000>, + <0x0 0x09171000 0x0 0x20000>, + <0x0 0x09191000 0x0 0x20000>, + <0x0 0x092dc000 0x0 0x1300>, + <0x0 0x092f0000 0x0 0x1300>, + <0x0 0x0900e000 0x0 0x1000>, + <0x0 0x0900d000 0x0 0x1000>, + <0x0 0x0902e000 0x0 0x1000>, + <0x0 0x0902d000 0x0 0x1000>, + <0x0 0x090d7000 0x0 0x20000>, + <0x0 0x0904e000 0x0 0x1000>, + <0x0 0x0904d000 0x0 0x1000>, + <0x0 0x09057000 0x0 0x40000>, + <0x0 0x09147000 0x0 0x580>, + <0x0 0x09148000 0x0 0x580>, + <0x0 0x09149000 0x0 0x580>, + <0x0 0x0914a000 0x0 0x580>, + <0x0 0x0914b000 0x0 0x580>, + <0x0 0x093fd000 0x0 0x400>, + <0x0 0x093fe000 0x0 0x400>, + <0x0 0x093ff000 0x0 0x400>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "icp0", + "icp0_sys", + "icp1", + "icp1_sys", + "ipe", + "jpeg_dma", + "jpeg_enc", + "ofe", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + clocks = <&camcc_cam_cc_camnoc_nrt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>, + <&camcc_cam_cc_cam_top_ahb_clk>, + <&camcc_cam_cc_cam_top_fast_ahb_clk>, + <&camcc_cam_cc_csid_clk>, + <&camcc_cam_cc_csid_csiphy_rx_clk>, + <&camcc_cam_cc_csiphy0_clk>, + <&camcc_cam_cc_csi0phytimer_clk>, + <&camcc_cam_cc_csiphy1_clk>, + <&camcc_cam_cc_csi1phytimer_clk>, + <&camcc_cam_cc_csiphy2_clk>, + <&camcc_cam_cc_csi2phytimer_clk>, + <&camcc_cam_cc_csiphy3_clk>, + <&camcc_cam_cc_csi3phytimer_clk>, + <&camcc_cam_cc_csiphy4_clk>, + <&camcc_cam_cc_csi4phytimer_clk>, + <&camcc_cam_cc_csiphy5_clk>, + <&camcc_cam_cc_csi5phytimer_clk>, + <&gcc_gcc_camera_hf_axi_clk>, + <&camcc_cam_cc_vfe_0_main_clk>, + <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_main_clk>, + <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_main_clk>, + <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_lite_clk>, + <&camcc_cam_cc_vfe_lite_ahb_clk>, + <&camcc_cam_cc_vfe_lite_cphy_rx_clk>, + <&camcc_cam_cc_vfe_lite_csid_clk>, + <&camcc_cam_cc_qdss_debug_xo_clk>, + <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>, + <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>, + <&gcc_gcc_camera_sf_axi_clk>, + <&camcc_cam_cc_icp_0_clk>, + <&camcc_cam_cc_icp_0_ahb_clk>, + <&camcc_cam_cc_icp_1_clk>, + <&camcc_cam_cc_icp_1_ahb_clk>, + <&camcc_cam_cc_ipe_nps_clk>, + <&camcc_cam_cc_ipe_nps_ahb_clk>, + <&camcc_cam_cc_ipe_nps_fast_ahb_clk>, + <&camcc_cam_cc_ipe_pps_clk>, + <&camcc_cam_cc_ipe_pps_fast_ahb_clk>, + <&camcc_cam_cc_jpeg_clk>, + <&camcc_cam_cc_ofe_ahb_clk>, + <&camcc_cam_cc_ofe_anchor_clk>, + <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>, + <&camcc_cam_cc_ofe_hdr_clk>, + <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>, + <&camcc_cam_cc_ofe_main_clk>, + <&camcc_cam_cc_ofe_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_0_bayer_clk>, + <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_bayer_clk>, + <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_bayer_clk>, + <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>; + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "camnoc_rt_vfe0", + "camnoc_rt_vfe1", + "camnoc_rt_vfe2", + "camnoc_rt_vfe_lite", + "cpas_ahb", + "cpas_fast_ahb", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_axi_hf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo", + "camnoc_ipe_nps", + "camnoc_ofe", + "gcc_axi_sf", + "icp0", + "icp0_ahb", + "icp1", + "icp1_ahb", + "ipe_nps", + "ipe_nps_ahb", + "ipe_nps_fast_ahb", + "ipe_pps", + "ipe_pps_fast_ahb", + "jpeg", + "ofe_ahb", + "ofe_anchor", + "ofe_anchor_fast_ahb", + "ofe_hdr", + "ofe_hdr_fast_ahb", + "ofe_main", + "ofe_main_fast_ahb", + "vfe0_bayer", + "vfe0_bayer_fast_ahb", + "vfe1_bayer", + "vfe1_bayer_fast_ahb", + "vfe2_bayer", + "vfe2_bayer_fast_ahb"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "camnoc_nrt", + "camnoc_rt", + "icp0", + "icp1", + "jpeg_dma", + "jpeg_enc", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + interconnects = <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf_icp QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cam_ahb", + "cam_hf_mnoc", + "cam_sf_icp_mnoc", + "cam_sf_mnoc"; + + iommus = <&apps_smmu 0x1c00 0x00>, + <&apps_smmu 0x18c0 0x00>, + <&apps_smmu 0x1980 0x00>, + <&apps_smmu 0x1840 0x00>, + <&apps_smmu 0x1800 0x00>, + <&apps_smmu 0x18a0 0x00>, + <&apps_smmu 0x1880 0x00>, + <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1860 0x00>; + + power-domains = <&camcc_cam_cc_ife_0_gdsc>, + <&camcc_cam_cc_ife_1_gdsc>, + <&camcc_cam_cc_ife_2_gdsc>, + <&camcc_cam_cc_titan_top_gdsc>, + <&camcc_cam_cc_ipe_gdsc>, + <&camcc_cam_cc_ofe_gdsc>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top", + "ipe", + "ofe"; + + vdd-csiphy0-0p8-supply = <&vreg_0p8_supply>; + vdd-csiphy0-1p2-supply = <&vreg_1p2_supply>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy_ep0: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; From e649290b85f9d9bd1ab588bd5f142dd4a7b0b599 Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Mon, 12 Jan 2026 20:48:48 -0800 Subject: [PATCH 0342/1330] FROMLIST: media: qcom: camss: Add Kaanapali compatible camss driver Add support for Kaanapali in the camss driver. Add high level resource information along with the bus bandwidth votes. Module level detailed resource information will be enumerated in the following patches of the series. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260112-kaanapali-camss-v12-2-15b7af73401e@oss.qualcomm.com/ --- drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 4bc5e298b81c4..dd6fa71073e43 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,6 +34,20 @@ static const struct parent_dev_ops vfe_parent_dev_ops; +static const struct resources_icc icc_res_kaanapali[] = { + { + .name = "cam_ahb", + .icc_bw_tbl.avg = 150000, + .icc_bw_tbl.peak = 300000, + }, + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */ + { + .name = "cam_hf_mnoc", + .icc_bw_tbl.avg = 471860, + .icc_bw_tbl.peak = 925857, + }, +}; + static const struct camss_subdev_resources csiphy_res_8x16[] = { /* CSIPHY0 */ { @@ -5108,6 +5122,13 @@ static void camss_remove(struct platform_device *pdev) camss_genpd_cleanup(camss); } +static const struct camss_resources kaanapali_resources = { + .version = CAMSS_KAANAPALI, + .pd_name = "top", + .icc_res = icc_res_kaanapali, + .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), +}; + static const struct camss_resources msm8916_resources = { .version = CAMSS_8x16, .legacy_phy = true, @@ -5338,6 +5359,7 @@ static const struct camss_resources x1e80100_resources = { }; static const struct of_device_id camss_dt_match[] = { + { .compatible = "qcom,kaanapali-camss", .data = &kaanapali_resources }, { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8939-camss", .data = &msm8939_resources }, { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 24ec3ad7990e7..ddc1eabc06c3c 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -93,6 +93,7 @@ enum camss_version { CAMSS_8550, CAMSS_8650, CAMSS_8775P, + CAMSS_KAANAPALI, CAMSS_X1E80100, }; From 633cc0d4b104de1d66d805fe4b4e3a145d80d99b Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Mon, 12 Jan 2026 20:48:49 -0800 Subject: [PATCH 0343/1330] FROMLIST: media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Add more detailed resource information for CSIPHY devices in the camss driver along with the support for v2.4.0 in the 2 phase CSIPHY driver that is responsible for the PHY lane register configuration, module reset and interrupt handling. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260112-kaanapali-camss-v12-3-15b7af73401e@oss.qualcomm.com/ --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 124 +++++++++++++++++ drivers/media/platform/qcom/camss/camss.c | 125 ++++++++++++++++++ 2 files changed, 249 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 4154832745525..c51ffcd93ce18 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -684,6 +684,123 @@ csiphy_lane_regs lane_regs_sm8650[] = { {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, }; +/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */ +static const struct +csiphy_lane_regs lane_regs_2_4_0[] = { + /* LN 0 */ + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 2 */ + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 4 */ + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 6 */ + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN CLK */ + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ static const struct csiphy_lane_regs lane_regs_x1e80100[] = { @@ -1019,6 +1136,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: ret = true; break; @@ -1134,6 +1252,12 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs = &lane_regs_sa8775p[0]; regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); break; + case CAMSS_KAANAPALI: + regs->lane_regs = &lane_regs_2_4_0[0]; + regs->lane_array_size = ARRAY_SIZE(lane_regs_2_4_0); + regs->offset = 0x1000; + regs->common_status_offset = 0x138; + break; default: break; } diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index dd6fa71073e43..9bbd8e9a50e5b 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,6 +34,129 @@ static const struct parent_dev_ops vfe_parent_dev_ops; +static const struct camss_subdev_resources csiphy_res_kaanapali[] = { + /* CSIPHY0 */ + { + .regulators = { + { .supply = "vdd-csiphy0-0p8", .init_load_uA = 151020 }, + { .supply = "vdd-csiphy0-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy0", "csiphy0_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .csiphy = { + .id = 0, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators = { + { .supply = "vdd-csiphy1-0p8", .init_load_uA = 151020 }, + { .supply = "vdd-csiphy1-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy1", "csiphy1_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .csiphy = { + .id = 1, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators = { + { .supply = "vdd-csiphy2-0p8", .init_load_uA = 151020 }, + { .supply = "vdd-csiphy2-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy2", "csiphy2_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .csiphy = { + .id = 2, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators = { + { .supply = "vdd-csiphy3-0p8", .init_load_uA = 151020 }, + { .supply = "vdd-csiphy3-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy3", "csiphy3_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" }, + .csiphy = { + .id = 3, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY4 */ + { + .regulators = { + { .supply = "vdd-csiphy4-0p8", .init_load_uA = 151020 }, + { .supply = "vdd-csiphy4-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy4", "csiphy4_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy4" }, + .interrupt = { "csiphy4" }, + .csiphy = { + .id = 4, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY5 */ + { + .regulators = { + { .supply = "vdd-csiphy5-0p8", .init_load_uA = 151020 }, + { .supply = "vdd-csiphy5-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy5", "csiphy5_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy5" }, + .interrupt = { "csiphy5" }, + .csiphy = { + .id = 5, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, +}; + static const struct resources_icc icc_res_kaanapali[] = { { .name = "cam_ahb", @@ -5125,8 +5248,10 @@ static void camss_remove(struct platform_device *pdev) static const struct camss_resources kaanapali_resources = { .version = CAMSS_KAANAPALI, .pd_name = "top", + .csiphy_res = csiphy_res_kaanapali, .icc_res = icc_res_kaanapali, .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), + .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali), }; static const struct camss_resources msm8916_resources = { From 0cae082327a97de0f07f925b1420743c6d580075 Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Mon, 12 Jan 2026 20:48:50 -0800 Subject: [PATCH 0344/1330] FROMLIST: media: qcom: camss: csid: Add support for CSID gen4 Add more detailed resource information for CSID devices along with the driver for CSID gen4 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. And aggregate a common definition 'CSI2_RX_CFG0_PHY_SEL_BASE_IDX' into csid header file. In this CSID version, RUP and AUP update values are split into two registers along with a SET register. Accordingly, enhance the CSID interface to accommodate both the legacy combined reg_update and the split RUP and AUP updates. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260112-kaanapali-camss-v12-4-15b7af73401e@oss.qualcomm.com/ --- drivers/media/platform/qcom/camss/Makefile | 1 + .../platform/qcom/camss/camss-csid-680.c | 1 - .../platform/qcom/camss/camss-csid-gen3.c | 1 - .../platform/qcom/camss/camss-csid-gen4.c | 376 ++++++++++++++++++ .../media/platform/qcom/camss/camss-csid.h | 11 +- drivers/media/platform/qcom/camss/camss.c | 80 ++++ 6 files changed, 467 insertions(+), 3 deletions(-) create mode 100644 drivers/media/platform/qcom/camss/camss-csid-gen4.c diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 5e349b4915130..ba9faa635bd72 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -10,6 +10,7 @@ qcom-camss-objs += \ camss-csid-680.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ + camss-csid-gen4.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ camss-csiphy.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/media/platform/qcom/camss/camss-csid-680.c index 3ad3a174bcfb8..86134a23cd4e9 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-680.c +++ b/drivers/media/platform/qcom/camss/camss-csid-680.c @@ -101,7 +101,6 @@ #define CSI2_RX_CFG0_DL2_INPUT_SEL 12 #define CSI2_RX_CFG0_DL3_INPUT_SEL 16 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSI2_RX_CFG0_PHY_TYPE_SEL 24 #define CSID_CSI2_RX_CFG1 0x204 diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c index bd059243790ed..76a4b62eca1b8 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -103,7 +103,6 @@ #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ (0x34C + 0x100 * (rdi)) :\ (0x54C + 0x100 * (rdi))) -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy, int vc) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/media/platform/qcom/camss/camss-csid-gen4.c new file mode 100644 index 0000000000000..b000bd3e9c2ec --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-gen4.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0x108 +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10C +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x110 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x114 +#define CSID_AUP_CMD 0x118 +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x11C +#define RUP_SET BIT(0) +#define MUP BIT(4) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS 0x180 +#define CSID_TOP_IRQ_MASK 0x184 +#define CSID_TOP_IRQ_CLEAR 0x188 +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0 +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16 +#define CSID_BUF_DONE_IRQ_MASK 0x1A4 +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8 +#define CSID_BUF_DONE_IRQ_SET 0x1AC + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0 +#define CSID_CSI2_RX_IRQ_MASK 0x1B4 +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8 +#define CSID_CSI2_RX_IRQ_SET 0x1BC + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 0x880 +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSID_CSI2_RX_CFG1 0x884 +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_GEN4 (csid_is_lite(csid) ? 4 : 5) + +/* RDI Configuration */ +#define CSID_RDI_CFG0(rdi) \ + ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi)) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) \ + ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi)) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) \ + ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi)) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi))) +#define INFO_RUP_DONE BIT(23) + +static void __csid_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + csid->aup_update |= CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_reg_update(struct csid_device *csid, int port_id) +{ + csid->rup_update |= CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val = CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val = readl(csid->base + CSID_CSI2_RX_CFG1); + val |= CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val = 0; + + if (enable) + val = RDI_CTRL_START_CMD; + + writel(val, csid->base + CSID_RDI_CTRL(rdi)); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi) +{ + u32 val; + + /* Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc) +{ + u32 val; + u8 lane_cnt = csid->phy.lane_cnt; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc]; + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt = 4; + + val = RDI_CFG0_TIMESTAMP_EN; + val |= RDI_CFG0_TIMESTAMP_STB_SEL; + val |= RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |= vc << RDI_CFG0_VC; + val |= format->data_type << RDI_CFG0_DT; + writel(val, csid->base + CSID_RDI_CFG0(vc)); + + val = RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + CSID_RDI_CFG1(vc)); + + /* Configure pixel store using dedicated register in gen4 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, vc); + + val = 0; + writel(val, csid->base + CSID_RDI_CTRL(vc)); + + val = readl(csid->base + CSID_RDI_CFG0(vc)); + + if (enable) + val |= RDI_CFG0_EN; + + writel(val, csid->base + CSID_RDI_CFG0(vc)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i; + u8 vc; + + __csid_configure_rx(csid, &csid->phy); + + for (vc = 0; vc < MSM_CSID_MAX_SRC_STREAMS_GEN4; vc++) { + if (csid->phy.en_vc & BIT(vc)) { + __csid_configure_rdi_stream(csid, enable, vc); + __csid_configure_rx_vc(csid, vc); + + for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++) + __csid_aup_update(csid, vc); + + __csid_reg_update(csid, vc); + + __csid_ctrl_rdi(csid, enable, vc); + } + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid = dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val = readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done = val & INFO_RST_DONE; + + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val = IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val = 0; + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val = IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val = RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val = SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time = wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_gen4 = { + .configure_stream = csid_configure_stream, + .configure_testgen_pattern = csid_configure_testgen_pattern, + .hw_version = csid_hw_version, + .isr = csid_isr, + .reset = csid_reset, + .src_pad_code = csid_src_pad_code, + .subdev_init = csid_subdev_init, + .reg_update = csid_subdev_reg_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index aedc96ed84b2f..75a113050eb1a 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -27,6 +27,8 @@ /* CSID hardware can demultiplex up to 4 outputs */ #define MSM_CSID_MAX_SRC_STREAMS 4 +/* CSIPHY to hardware PHY selector mapping */ +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSID_RESET_TIMEOUT_MS 500 enum csid_testgen_mode { @@ -154,7 +156,13 @@ struct csid_device { void __iomem *base; u32 irq; char irq_name[30]; - u32 reg_update; + union { + u32 reg_update; + struct { + u32 rup_update; + u32 aup_update; + }; + }; struct camss_clock *clock; int nclocks; struct regulator_bulk_data *supplies; @@ -217,6 +225,7 @@ extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; +extern const struct csid_hw_ops csid_ops_gen4; /* * csid_is_lite - Check if CSID is CSID lite. diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 9bbd8e9a50e5b..3f2a5bb649e5f 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -157,6 +157,84 @@ static const struct camss_subdev_resources csiphy_res_kaanapali[] = { }, }; +static const struct camss_subdev_resources csid_res_kaanapali[] = { + /* CSID0 */ + { + .regulators = {}, + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_gen4, + .formats = &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators = {}, + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_gen4, + .formats = &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators = {}, + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_gen4, + .formats = &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .regulators = {}, + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid_lite0" }, + .interrupt = { "csid_lite0" }, + .csid = { + .is_lite = true, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_gen4, + .formats = &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .regulators = {}, + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid_lite1" }, + .interrupt = { "csid_lite1" }, + .csid = { + .is_lite = true, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_gen4, + .formats = &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_kaanapali[] = { { .name = "cam_ahb", @@ -5249,9 +5327,11 @@ static const struct camss_resources kaanapali_resources = { .version = CAMSS_KAANAPALI, .pd_name = "top", .csiphy_res = csiphy_res_kaanapali, + .csid_res = csid_res_kaanapali, .icc_res = icc_res_kaanapali, .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali), + .csid_num = ARRAY_SIZE(csid_res_kaanapali), }; static const struct camss_resources msm8916_resources = { From b710f5c8ac5c96b5b98f0a4337450bdcdda3bc0a Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Mon, 12 Jan 2026 20:48:51 -0800 Subject: [PATCH 0345/1330] FROMLIST: media: qcom: camss: vfe: Add support for VFE gen4 Add Video Front End (VFE) version gen4 as found on the Kaanapali SoC. The FULL front end modules in Kaanapali camera subsystem are called TFEs (Thin Front End), however, retaining the name VFE at places to maintain consistency and avoid unnecessary code changes. This change limits the VFE output lines to 3 for now as constrained by the CAMSS driver framework. Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be issued after all of the CSID configuration has been done. Additionally, the number of AUP_UPDATEs should match the number of buffers enqueued to the write master while it's being enabled. Although the real time data from TFE goes through the RT_CAMNOC, we are required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for the PDX_NOC, that follows both the RT and NRT NOCs in this architecture, to ensure that both of the latter are idle after reset. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260112-kaanapali-camss-v12-5-15b7af73401e@oss.qualcomm.com/ --- drivers/media/platform/qcom/camss/Makefile | 1 + .../platform/qcom/camss/camss-vfe-gen4.c | 197 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss-vfe.c | 9 +- drivers/media/platform/qcom/camss/camss-vfe.h | 2 + drivers/media/platform/qcom/camss/camss.c | 143 +++++++++++++ 5 files changed, 350 insertions(+), 2 deletions(-) create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-gen4.c diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index ba9faa635bd72..ed8001ef90a68 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -23,6 +23,7 @@ qcom-camss-objs += \ camss-vfe-480.o \ camss-vfe-680.o \ camss-vfe-gen3.o \ + camss-vfe-gen4.o \ camss-vfe-gen1.o \ camss-vfe-vbif.o \ camss-vfe.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c new file mode 100644 index 0000000000000..d73d70898710a --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-vfe-gen4.c + * + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen4 + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include + +#include "camss.h" +#include "camss-vfe.h" + +/* VFE-gen4 Bus Register Base Addresses */ +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000) + +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) + +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128) + +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100) +#define WM_CFG_EN BIT(0) +#define WM_VIR_FRM_EN BIT(1) +#define WM_CFG_MODE BIT(16) +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100) +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100) +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100) +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100) + +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100) +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100) + +/* VFE lite has no such registers */ +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x100) + +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100) +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100) + +/* + * IFE write master client IDs + * + * VIDEO_FULL 0 + * VIDEO_DC4_Y 1 + * VIDEO_DC4_C 2 + * VIDEO_DC16_Y 3 + * VIDEO_DC16_C 4 + * DISPLAY_DS2_Y 5 + * DISPLAY_DS2_C 6 + * FD_Y 7 + * FD_C 8 + * PIXEL_RAW 9 + * STATS_AEC_BG 10 + * STATS_AEC_BHIST 11 + * STATS_TINTLESS_BG 12 + * STATS_AWB_BG 13 + * STATS_AWB_BFW 14 + * STATS_AF_BHIST 15 + * STATS_ALSC_BG 16 + * STATS_FLICKER_BAYERRS 17 + * STATS_TMC_BHIST 18 + * PDAF_0 19 + * PDAF_1 20 + * PDAF_2 21 + * PDAF_3 22 + * RDI0 23 + * RDI1 24 + * RDI2 25 + * RDI3 26 + * RDI4 27 + * + * IFE Lite write master client IDs + * + * RDI0 0 + * RDI1 1 + * RDI2 2 + * RDI3 3 + * GAMMA 4 + * STATES_BE 5 + */ +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) + +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) +{ + struct v4l2_pix_format_mplane *pix = + &line->video_out.active_fmt.fmt.pix_mp; + + wm = RDI_WM(wm); + + /* no clock gating at bus input */ + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); + + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); + + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8, + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); + + /* no dropped frames, one irq per frame */ + if (!vfe_is_lite(vfe)) { + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); + } + + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); + + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); + + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) +{ + wm = RDI_WM(wm); + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) +{ + wm = RDI_WM(wm); + writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); + + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr); +} + +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) +{ + int port_id = line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, false); +} + +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) +{ + int port_id = line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, true); +} + +static const struct camss_video_ops vfe_video_ops_gen4 = { + .queue_buffer = vfe_queue_buffer_v2, + .flush_buffers = vfe_flush_buffers, +}; + +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) +{ + vfe->video_ops = vfe_video_ops_gen4; +} + +static void vfe_global_reset(struct vfe_device *vfe) +{ + vfe_isr_reset_ack(vfe); +} + +static irqreturn_t vfe_isr(int irq, void *dev) +{ + /* nop */ + return IRQ_HANDLED; +} + +static int vfe_halt(struct vfe_device *vfe) +{ + /* rely on vfe_disable_output() to stop the VFE */ + return 0; +} + +const struct vfe_hw_ops vfe_ops_gen4 = { + .global_reset = vfe_global_reset, + .hw_version = vfe_hw_version, + .isr = vfe_isr, + .pm_domain_off = vfe_pm_domain_off, + .pm_domain_on = vfe_pm_domain_on, + .reg_update = vfe_reg_update, + .reg_update_clear = vfe_reg_update_clear, + .subdev_init = vfe_subdev_init, + .vfe_disable = vfe_disable, + .vfe_enable = vfe_enable_v2, + .vfe_halt = vfe_halt, + .vfe_wm_start = vfe_wm_start, + .vfe_wm_stop = vfe_wm_stop, + .vfe_buf_done = vfe_buf_done, + .vfe_wm_update = vfe_wm_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 5baf0e3d4bc46..99630ffa1db57 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -352,6 +352,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: @@ -524,7 +525,8 @@ int vfe_enable_output_v2(struct vfe_line *line) spin_lock_irqsave(&vfe->output_lock, flags); - ops->reg_update_clear(vfe, line->id); + if (ops->reg_update_clear) + ops->reg_update_clear(vfe, line->id); if (output->state > VFE_OUTPUT_RESERVED) { dev_err(vfe->camss->dev, @@ -551,7 +553,9 @@ int vfe_enable_output_v2(struct vfe_line *line) output->gen2.active_num++; ops->vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); - ops->reg_update(vfe, line->id); + + if (!vfe->res->reg_update_after_csid_config) + ops->reg_update(vfe, line->id); } spin_unlock_irqrestore(&vfe->output_lock, flags); @@ -2011,6 +2015,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: ret = 16; break; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h index ae9dad353a378..c402ef170c81b 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -133,6 +133,7 @@ struct vfe_isr_ops { struct vfe_subdev_resources { bool is_lite; + bool reg_update_after_csid_config; u8 line_num; bool has_pd; char *pd_name; @@ -249,6 +250,7 @@ extern const struct vfe_hw_ops vfe_ops_340; extern const struct vfe_hw_ops vfe_ops_480; extern const struct vfe_hw_ops vfe_ops_680; extern const struct vfe_hw_ops vfe_ops_gen3; +extern const struct vfe_hw_ops vfe_ops_gen4; int vfe_get(struct vfe_device *vfe); void vfe_put(struct vfe_device *vfe); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 3f2a5bb649e5f..9db2d0ddfb9ae 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -235,6 +235,147 @@ static const struct camss_subdev_resources csid_res_kaanapali[] = { } }; +/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks + * to operate on any TFE Full. + */ +static const struct camss_subdev_resources vfe_res_kaanapali[] = { + /* VFE0 - TFE Full */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "vfe0_fast_ahb", "vfe0", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .reg_update_after_csid_config = true, + .has_pd = true, + .pd_name = "ife0", + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE1 - TFE Full */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "vfe1_fast_ahb", "vfe1", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .reg_update_after_csid_config = true, + .has_pd = true, + .pd_name = "ife1", + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE2 - TFE Full */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "vfe2_fast_ahb", "vfe2", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe2" }, + .interrupt = { "vfe2" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .reg_update_after_csid_config = true, + .has_pd = true, + .pd_name = "ife2", + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE3 - IFE Lite */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite", + "camnoc_rt_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .reg_update_after_csid_config = true, + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE4 - IFE Lite */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite", + "camnoc_rt_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .reg_update_after_csid_config = true, + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, +}; + static const struct resources_icc icc_res_kaanapali[] = { { .name = "cam_ahb", @@ -5328,10 +5469,12 @@ static const struct camss_resources kaanapali_resources = { .pd_name = "top", .csiphy_res = csiphy_res_kaanapali, .csid_res = csid_res_kaanapali, + .vfe_res = vfe_res_kaanapali, .icc_res = icc_res_kaanapali, .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali), .csid_num = ARRAY_SIZE(csid_res_kaanapali), + .vfe_num = ARRAY_SIZE(vfe_res_kaanapali), }; static const struct camss_resources msm8916_resources = { From fb4722725db9da71bf2f5d0e1d3d0d8127b841a8 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 4 Mar 2026 00:21:56 -0800 Subject: [PATCH 0346/1330] FROMLIST: phy: qcom: qmp-pcie: Add multiple power-domains support The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in a bifurcated configuration. Each PHY has its own power domain (phy_gdsc) that must be powered on before initialization per hardware requirements. Current PHY power management assumes a single power domain per PHY, preventing proper setup for this dual-PHY scenario. Add support for multiple power domains by using devm_pm_domain_attach_list() to attach power domains manually, while maintaining compatibility with single power domain PHYs. Enable runtime PM to allow power domain control when the PCIe driver calls phy_power_on/phy_power_off: - Single power domain: QMP PHY platform device directly attaches to power domain and controls it during runtime resume/suspend - Multiple power domains: devm_pm_domain_attach_list() creates virtual devices as power domain suppliers, linked to the QMP PHY platform device as consumer This ensures power domains are properly attached and turned on/off for both single and multiple power domain configurations. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-2-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu From 93f104c002b2312c39355b18dcb522cffc361410 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 4 Mar 2026 00:21:57 -0800 Subject: [PATCH 0347/1330] FROMLIST: phy: qcom: qmp-pcie: Support multiple nocsr resets Refactor nocsr reset handling to support multiple nocsr resets required for PHY configurations with bifurcated operation modes. The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in bifurcation, where each PHY requires its own nocsr reset to be controlled simultaneously. The current implementation only supports a single nocsr reset per PHY configuration. Add num_nocsr and nocsr_list fields to struct qmp_phy_cfg to represent the number and names of a group of nocsr reset names. Initialize these fields for all PHYs that have nocsr resets, allowing the driver to correctly acquire multiple nocsr resets during probe and control them as an array by using reset_control_bulk APIs. The refactoring maintains backward compatibility for existing single nocsr reset configurations while enabling support for multi-PHY scenarios like Glymur's 8-lane bifurcation mode. Additionally, introduces x1e80100_qmp_gen3x2_pciephy_cfg as a separate configuration from sm8550_qmp_gen3x2_pciephy_cfg since the x1e80100 Gen3x2 PHY requires nocsr reset support while the sm8550 Gen3x2 PHY does not. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-3-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 474a11b15c2a5..29bc0fe5ce37e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4669,6 +4669,8 @@ static const struct qmp_phy_cfg qmp_v8_gen3x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v8_regs_layout, From 17ca93228290e440e76add12f6265c95d7f6fcbc Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 4 Mar 2026 00:21:58 -0800 Subject: [PATCH 0348/1330] FROMLIST: phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur The third PCIe controller on Glymur SoC supports 8-lane operation via bifurcation of two PHYs (each requires separate power domian, resets and aux clk). Add dedicated reset/no_csr reset list ("phy_b", "phy_b_nocsr") and clock ("phy_b_aux") required for 8-lane operation. Introduce new glymur_qmp_gen5x8_pciephy_cfg configuration to enable PCIe Gen5 x8 mode. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-4-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu From 406e204b1f73643e2df04475756d4b4849103d2c Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 12 Feb 2026 14:19:12 +0800 Subject: [PATCH 0349/1330] WORKAROUND: phy: qcom: qmp-pcie: Add vdda-refgen and vdda-qref supplies for Glymur The PCIe QMP PHYs on Glymur require stable reference voltage provided by refgen and reference clk provided by qref. The refgen and qref requires power supplies. Add support for vdda-refgen0p9, vdda-refgen1p2 and vdda-qref2 supplies in sm8550_qmp_phy_vreg_l list. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 29bc0fe5ce37e..ef652918704b3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3387,7 +3387,7 @@ static const char * const qmp_phy_vreg_l[] = { }; static const char * const sm8550_qmp_phy_vreg_l[] = { - "vdda-phy", "vdda-pll", "vdda-qref", + "vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2", "vdda-qref","vdda-qref2", }; /* list of resets */ @@ -4688,8 +4688,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v8_50_regs_layout, @@ -4706,8 +4706,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v8_regs_layout, @@ -4724,8 +4724,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg = { .num_resets = ARRAY_SIZE(glymur_pciephy_reset_l), .nocsr_reset_list = glymur_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(glymur_pciephy_nocsr_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v8_50_regs_layout, From 21aafea1fdbe1ef03453ce3529408b8749df0bd2 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Mon, 16 Mar 2026 17:24:55 +0530 Subject: [PATCH 0350/1330] WORKAROUND: remoteproc: qcom: Fix RB8 device hung issue A race condition is occasionally observed on the RB8 platform where the APPS processor removes its turbo vote from the LCX and LMX rails immediately after receiving the handover interrupt from firmware. At that moment, the ADSP firmware vote has not yet been applied to these rails, causing the PMIC shut down and leading the device to hang. Keep the vote of lcx and lmx rails to SVS_L1 from APPS side instead of completely removing it as a WA until actual fix is available. Signed-off-by: Umang Chheda --- drivers/remoteproc/qcom_q6v5_pas.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 46204da046fad..82d0fef763975 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -184,6 +184,18 @@ static void qcom_pas_pds_disable(struct qcom_pas *pas, struct device **pds, int i; for (i = 0; i < pd_count; i++) { + /* + * There is a race condition which occurs sometimes for RB8 platform when APPS + * removes it's vote on handover INT from fw - ADSP F/W side vote is not yet + * applied on the lcx and lmx rails because of which PMIC shutdowns shut and device + * goes into hung state. Carry this WA until a proper fix is finalized. + */ + if (of_device_is_compatible(dev_of_node(pas->dev), "qcom,sa8775p-adsp-pas")) { + /* Apply SVS_L1 vote to keep lcx and lmx rails ON */ + dev_pm_genpd_set_performance_state(pds[i], 192); + return; + } + dev_pm_genpd_set_performance_state(pds[i], 0); pm_runtime_put(pds[i]); } From ee13bd0a15acc817e7b45848da59286b431ad989 Mon Sep 17 00:00:00 2001 From: Anvesh Jain P Date: Mon, 16 Mar 2026 18:51:22 +0530 Subject: [PATCH 0351/1330] FROMLIST: arm64: dts: qcom: glymur-crd: Add Embedded controller node Add embedded controller node for Glymur CRDs which adds fan control, temperature sensors, access to EC state changes through SCI events and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/lkml/20260313-v04-add-driver-for-ec-v4-3-ca9d0efd62aa@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Anvesh Jain P --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 6ceaa44028790..3f656436f417a 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -641,6 +641,22 @@ }; }; +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + embedded-controller@76 { + compatible = "qcom,glymur-crd-ec", "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; +}; + &mdss { status = "okay"; }; @@ -925,6 +941,12 @@ <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_bl_en: edp-bl-en-state { pins = "gpio18"; function = "gpio"; From b71c1aff82070cd104c15e045f210b628456f949 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 17 Mar 2026 18:27:36 +0530 Subject: [PATCH 0352/1330] dt-bindings: pinctrl: Document the Shikra Top Level Mode Multiplexer Document the Top Level Mode Multiplexer on the Shikra platform. Signed-off-by: Komal Bajaj --- .../bindings/pinctrl/qcom,shikra-tlmm.yaml | 139 ++++++++++++++++++ 1 file changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml new file mode 100644 index 0000000000000..8f9489b81a674 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Shikra TLMM block + +maintainers: + - Komal Bajaj + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,shikra-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 83 + + gpio-line-names: + maxItems: 166 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-shikra-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-shikra-tlmm-state" + additionalProperties: false + +$defs: + qcom-shikra-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_char_start, + atest_gpsadc, atest_tsens, atest_tsens2, atest_usb, cam_mclk, + cci_async_in0, cci_i2c_scl0, cci_i2c_scl1, cci_i2c_sda0, + cci_i2c_sda1, cci_timer, char_exec_pending, char_exec_release, + cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out_clk, + ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop, + ddr_pxi0, ddr_pxi1, dmic0_clk, dmic0_data, dmic1_clk, dmic1_data, + emac0_dll, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, + emac0_phy, emac0_ptp, emac1_dll, emac1_mcg0, emac1_mcg1, + emac1_mcg2, emac1_mcg3, emac1_phy, emac1_ptp, ext_mclk, gcc_gp1, + gcc_gp2, gcc_gp3, gsm0_tx, i2s0_clk, i2s0_data0, i2s0_data1, + i2s0_data2, i2s0_data3, i2s0_ws, i2s1_clk, i2s1_data0, i2s1_data1, + i2s1_ws, i2s2_clk, i2s2_data0, i2s2_data1, i2s2_ws, i2s3_clk, + i2s3_data0, i2s3_data1, i2s3_ws, jitter_bist, m_voc, mdp_vsync, + mdp_vsync_e, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte, nav_gpio, + pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n, phase_flag, + pll_bist, pll_bypassnl, pll_clk, pll_reset_n, prng_rosc, pwm_0, + pwm_1, pwm_2, pwm_3, pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9, + qdss_cti, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, + qup0_se5, qup0_se6, qup0_se7, qup0_se8, qup0_se9, rgmii0_mdc, + rgmii0_mdio, rgmii0_rx_ctl, rgmii0_rxc, rgmii0_rxd0, rgmii0_rxd1, + rgmii0_rxd2, rgmii0_rxd3, rgmii0_tx_ctl, rgmii0_txc, rgmii0_txd0, + rgmii0_txd1, rgmii0_txd2, rgmii0_txd3, rgmii1_mdc, rgmii1_mdio, + rgmii1_rx_ctl, rgmii1_rxc, rgmii1_rxd0, rgmii1_rxd1, rgmii1_rxd2, + rgmii1_rxd3, rgmii1_tx_ctl, rgmii1_txc, rgmii1_txd0, rgmii1_txd1, + rgmii1_txd2, rgmii1_txd3, sd_write_protect, sdc1_tb_trig, + sdc2_tb_trig, ssbi_wtr0, ssbi_wtr1, ssbi_wtr2, ssbi_wtr3, + swr0_rx_clk, swr0_rx_data0, swr0_rx_data1, swr0_tx_clk, + swr0_tx_data0, tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, + tgu_ch3_trigout, tsc_async, tsense_pwm, uim1_clk, uim1_data, + uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, + uim2_reset, unused_adsp, unused_gsm1, usb0_phy_ps, vfr_1, + vsense_trigger_mirnat, wlan1_adc0, wlan1_adc1 ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@500000 { + compatible = "qcom,shikra-tlmm"; + reg = <0x00500000 0x800000>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 166>; + + qup-uart0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + }; +... From ef7a82daecda5803f3efe75c296252bf7ec9b46a Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 17 Mar 2026 16:11:34 +0530 Subject: [PATCH 0353/1330] pinctrl: qcom: Add Shikra pinctrl driver Add pinctrl driver for TLMM block found in the Shikra SoC. Signed-off-by: Komal Bajaj --- drivers/pinctrl/qcom/Kconfig.msm | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-shikra.c | 1776 +++++++++++++++++++++++++ 3 files changed, 1785 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-shikra.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 3e9e02774001b..5bf42e71225b2 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -341,6 +341,14 @@ config PINCTRL_SDX75 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX75 platform. +config PINCTRL_SHIKRA + tristate "Qualcomm Technologies Inc Shikra pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc Shikra platform. + config PINCTRL_SM4450 tristate "Qualcomm Technologies Inc SM4450 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4269d1781015e..591a429cfd49d 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o +obj-$(CONFIG_PINCTRL_SHIKRA) += pinctrl-shikra.o obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c new file mode 100644 index 0000000000000..d1ea0bb0dc41f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-shikra.c @@ -0,0 +1,1776 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, wake_off, bit) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_enable_bit = 7, \ + .intr_wakeup_present_bit = 6, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc shikra_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "SDC1_DATA"), + PINCTRL_PIN(163, "SDC1_RCLK"), + PINCTRL_PIN(164, "SDC1_CMD"), + PINCTRL_PIN(165, "SDC1_CLK"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); + +static const unsigned int sdc1_data_pins[] = { 162 }; +static const unsigned int sdc1_rclk_pins[] = { 163 }; +static const unsigned int sdc1_cmd_pins[] = { 164 }; +static const unsigned int sdc1_clk_pins[] = { 165 }; +static const unsigned int sdc2_clk_pins[] = { 166 }; +static const unsigned int sdc2_cmd_pins[] = { 167 }; +static const unsigned int sdc2_data_pins[] = { 168 }; + +enum shikra_functions { + msm_mux_gpio, + msm_mux_agera_pll, + msm_mux_atest_bbrx, + msm_mux_atest_char, + msm_mux_atest_gpsadc, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb, + msm_mux_cam_mclk, + msm_mux_cci_async_in0, + msm_mux_cci_i2c_scl0, + msm_mux_cci_i2c_scl1, + msm_mux_cci_i2c_sda0, + msm_mux_cci_i2c_sda1, + msm_mux_cci_timer, + msm_mux_char_exec_pending, + msm_mux_char_exec_release, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dac_calib, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_dmic0_clk, + msm_mux_dmic0_data, + msm_mux_dmic1_clk, + msm_mux_dmic1_data, + msm_mux_emac0_dll, + msm_mux_emac0_mcg0, + msm_mux_emac0_mcg1, + msm_mux_emac0_mcg2, + msm_mux_emac0_mcg3, + msm_mux_emac0_phy, + msm_mux_emac0_ptp, + msm_mux_emac1_dll, + msm_mux_emac1_mcg0, + msm_mux_emac1_mcg1, + msm_mux_emac1_mcg2, + msm_mux_emac1_mcg3, + msm_mux_emac1_phy, + msm_mux_emac1_ptp, + msm_mux_ext_mclk, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gsm0_tx, + msm_mux_i2s0_clk, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_data2, + msm_mux_i2s0_data3, + msm_mux_i2s0_ws, + msm_mux_i2s1_clk, + msm_mux_i2s1_data0, + msm_mux_i2s1_data1, + msm_mux_i2s1_ws, + msm_mux_i2s2_clk, + msm_mux_i2s2_data0, + msm_mux_i2s2_data1, + msm_mux_i2s2_ws, + msm_mux_i2s3_clk, + msm_mux_i2s3_data0, + msm_mux_i2s3_data1, + msm_mux_i2s3_ws, + msm_mux_jitter_bist, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync_s, + msm_mux_mpm_pwr, + msm_mux_mss_lte, + msm_mux_nav_gpio, + msm_mux_pa_indicator_or, + msm_mux_pbs_in, + msm_mux_pbs_out, + msm_mux_pcie0_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_clk, + msm_mux_pll_reset_n, + msm_mux_prng_rosc, + msm_mux_pwm_0, + msm_mux_pwm_1, + msm_mux_pwm_2, + msm_mux_pwm_3, + msm_mux_pwm_4, + msm_mux_pwm_5, + msm_mux_pwm_6, + msm_mux_pwm_7, + msm_mux_pwm_8, + msm_mux_pwm_9, + msm_mux_qdss_cti, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup0_se6, + msm_mux_qup0_se7, + msm_mux_qup0_se8, + msm_mux_qup0_se9, + msm_mux_rgmii0_mdc, + msm_mux_rgmii0_mdio, + msm_mux_rgmii0_rx_ctl, + msm_mux_rgmii0_rxc, + msm_mux_rgmii0_rxd0, + msm_mux_rgmii0_rxd1, + msm_mux_rgmii0_rxd2, + msm_mux_rgmii0_rxd3, + msm_mux_rgmii0_tx_ctl, + msm_mux_rgmii0_txc, + msm_mux_rgmii0_txd0, + msm_mux_rgmii0_txd1, + msm_mux_rgmii0_txd2, + msm_mux_rgmii0_txd3, + msm_mux_rgmii1_mdc, + msm_mux_rgmii1_mdio, + msm_mux_rgmii1_rx_ctl, + msm_mux_rgmii1_rxc, + msm_mux_rgmii1_rxd0, + msm_mux_rgmii1_rxd1, + msm_mux_rgmii1_rxd2, + msm_mux_rgmii1_rxd3, + msm_mux_rgmii1_tx_ctl, + msm_mux_rgmii1_txc, + msm_mux_rgmii1_txd0, + msm_mux_rgmii1_txd1, + msm_mux_rgmii1_txd2, + msm_mux_rgmii1_txd3, + msm_mux_sd_write_protect, + msm_mux_sdc1_tb_trig, + msm_mux_sdc2_tb_trig, + msm_mux_ssbi_wtr0, + msm_mux_ssbi_wtr1, + msm_mux_ssbi_wtr2, + msm_mux_ssbi_wtr3, + msm_mux_swr0_rx_clk, + msm_mux_swr0_rx_data0, + msm_mux_swr0_rx_data1, + msm_mux_swr0_tx_clk, + msm_mux_swr0_tx_data0, + msm_mux_tgu_ch0_trigout, + msm_mux_tgu_ch1_trigout, + msm_mux_tgu_ch2_trigout, + msm_mux_tgu_ch3_trigout, + msm_mux_tsc_async, + msm_mux_tsense_pwm, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_unused_adsp, + msm_mux_unused_gsm1, + msm_mux_usb0_phy_ps, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", +}; + +static const char *const agera_pll_groups[] = { + "gpio22", "gpio23", +}; + +static const char *const atest_bbrx_groups[] = { + "gpio58", "gpio59", +}; + +static const char *const atest_char_groups[] = { + "gpio56", "gpio57", "gpio54", "gpio55", "gpio62", +}; + +static const char *const atest_gpsadc_groups[] = { + "gpio60", "gpio96", +}; + +static const char *const atest_tsens_groups[] = { + "gpio1", +}; + +static const char *const atest_tsens2_groups[] = { + "gpio2", +}; + +static const char *const atest_usb_groups[] = { + "gpio96", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio60", "gpio61", "gpio53", "gpio58", "gpio59", +}; + +static const char *const cam_mclk_groups[] = { + "gpio34", "gpio35", "gpio96", "gpio98", +}; + +static const char *const cci_async_in0_groups[] = { + "gpio39", +}; + +static const char *const cci_i2c_scl0_groups[] = { + "gpio37", +}; + +static const char *const cci_i2c_scl1_groups[] = { + "gpio42", +}; + +static const char *const cci_i2c_sda0_groups[] = { + "gpio36", +}; + +static const char *const cci_i2c_sda1_groups[] = { + "gpio41", +}; + +static const char *const cci_timer_groups[] = { + "gpio38", "gpio47", "gpio40", "gpio43", +}; + +static const char *const char_exec_pending_groups[] = { + "gpio13", +}; + +static const char *const char_exec_release_groups[] = { + "gpio12", +}; + +static const char *const cri_trng_groups[] = { + "gpio20", +}; + +static const char *const cri_trng0_groups[] = { + "gpio6", +}; + +static const char *const cri_trng1_groups[] = { + "gpio7", +}; + +static const char *const dac_calib_groups[] = { + "gpio3", "gpio4", "gpio17", "gpio18", "gpio19", + "gpio64", "gpio66", "gpio66", "gpio68", "gpio69", + "gpio70", "gpio89", "gpio5", "gpio90", "gpio88", + "gpio117", "gpio97", "gpio118", "gpio116", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio14", "gpio15", + "gpio16", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio61", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio4", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio1", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio2", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio3", +}; + +static const char *const ddr_pxi0_groups[] = { + "gpio98", "gpio99", +}; + +static const char *const ddr_pxi1_groups[] = { + "gpio100", "gpio101", +}; + +static const char *const dmic0_clk_groups[] = { + "gpio96", +}; + +static const char *const dmic0_data_groups[] = { + "gpio97", +}; + +static const char *const dmic1_clk_groups[] = { + "gpio98", +}; + +static const char *const dmic1_data_groups[] = { + "gpio99", +}; + +static const char *const emac0_dll_groups[] = { + "gpio60", "gpio61", +}; + +static const char *const emac0_mcg0_groups[] = { + "gpio46", +}; + +static const char *const emac0_mcg1_groups[] = { + "gpio45", +}; + +static const char *const emac0_mcg2_groups[] = { + "gpio44", +}; + +static const char *const emac0_mcg3_groups[] = { + "gpio43", +}; + +static const char *const emac0_phy_groups[] = { + "gpio120", +}; + +static const char *const emac0_ptp_groups[] = { + "gpio60", "gpio63", "gpio69", "gpio85", +}; + +static const char *const emac1_dll_groups[] = { + "gpio58", "gpio59", +}; + +static const char *const emac1_mcg0_groups[] = { + "gpio29", +}; + +static const char *const emac1_mcg1_groups[] = { + "gpio28", +}; + +static const char *const emac1_mcg2_groups[] = { + "gpio40", +}; + +static const char *const emac1_mcg3_groups[] = { + "gpio47", +}; + +static const char *const emac1_phy_groups[] = { + "gpio136", +}; + +static const char *const emac1_ptp_groups[] = { + "gpio31", "gpio33", "gpio60", "gpio68", +}; + +static const char *const ext_mclk_groups[] = { + "gpio103", "gpio104", "gpio110", "gpio114", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio45", "gpio110", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio61", "gpio88", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio53", "gpio89", +}; + +static const char *const gsm0_tx_groups[] = { + "gpio75", +}; + +static const char *const i2s0_clk_groups[] = { + "gpio105", +}; + +static const char *const i2s0_data0_groups[] = { + "gpio107", +}; + +static const char *const i2s0_data1_groups[] = { + "gpio108", +}; + +static const char *const i2s0_data2_groups[] = { + "gpio109", +}; + +static const char *const i2s0_data3_groups[] = { + "gpio110", +}; + +static const char *const i2s0_ws_groups[] = { + "gpio106", +}; + +static const char *const i2s1_clk_groups[] = { + "gpio96", +}; + +static const char *const i2s1_data0_groups[] = { + "gpio98", +}; + +static const char *const i2s1_data1_groups[] = { + "gpio99", +}; + +static const char *const i2s1_ws_groups[] = { + "gpio97", +}; + +static const char *const i2s2_clk_groups[] = { + "gpio100", +}; + +static const char *const i2s2_data0_groups[] = { + "gpio102", +}; + +static const char *const i2s2_data1_groups[] = { + "gpio103", +}; + +static const char *const i2s2_ws_groups[] = { + "gpio101", +}; + +static const char *const i2s3_clk_groups[] = { + "gpio111", +}; + +static const char *const i2s3_data0_groups[] = { + "gpio113", +}; + +static const char *const i2s3_data1_groups[] = { + "gpio114", +}; + +static const char *const i2s3_ws_groups[] = { + "gpio112", +}; + +static const char *const jitter_bist_groups[] = { + "gpio96", "gpio99", +}; + +static const char *const m_voc_groups[] = { + "gpio0", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio94", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync_s_groups[] = { + "gpio95", +}; + +static const char *const mpm_pwr_groups[] = { + "gpio1", +}; + +static const char *const mss_lte_groups[] = { + "gpio115", "gpio116", +}; + +static const char *const nav_gpio_groups[] = { + "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92", + "gpio95", "gpio100", "gpio101", "gpio104", +}; + +static const char *const pa_indicator_or_groups[] = { + "gpio61", +}; + +static const char *const pbs_in_groups[] = { + "gpio49", "gpio50", "gpio59", "gpio60", "gpio61", + "gpio62", "gpio63", "gpio51", "gpio48", "gpio74", + "gpio74", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio58", +}; + +static const char *const pbs_out_groups[] = { + "gpio24", "gpio22", "gpio23", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio117", +}; + +static const char *const phase_flag_groups[] = { + "gpio1", "gpio2", "gpio56", "gpio11", "gpio62", + "gpio63", "gpio63", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio74", "gpio3", "gpio57", "gpio31", + "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", "gpio29", "gpio29", "gpio54", "gpio16", + "gpio17", "gpio102", "gpio55", "gpio0", "gpio48", + "gpio49", "gpio50", +}; + +static const char *const pll_bist_groups[] = { + "gpio43", "gpio44", +}; + +static const char *const pll_bypassnl_groups[] = { + "gpio76", +}; + +static const char *const pll_clk_groups[] = { + "gpio14", "gpio22", +}; + +static const char *const pll_reset_n_groups[] = { + "gpio74", +}; + +static const char *const prng_rosc_groups[] = { + "gpio27", "gpio28", +}; + +static const char *const pwm_0_groups[] = { + "gpio32", "gpio55", +}; + +static const char *const pwm_1_groups[] = { + "gpio40", "gpio54", +}; + +static const char *const pwm_2_groups[] = { + "gpio62", "gpio57", +}; + +static const char *const pwm_3_groups[] = { + "gpio77", +}; + +static const char *const pwm_4_groups[] = { + "gpio79", +}; + +static const char *const pwm_5_groups[] = { + "gpio80", +}; + +static const char *const pwm_6_groups[] = { + "gpio87", "gpio56", +}; + +static const char *const pwm_7_groups[] = { + "gpio45", "gpio53", +}; + +static const char *const pwm_8_groups[] = { + "gpio102", "gpio58", +}; + +static const char *const pwm_9_groups[] = { + "gpio61", "gpio68", +}; + +static const char *const qdss_cti_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95", +}; + +static const char *const qup0_se0_groups[] = { + "gpio2", "gpio3", "gpio0", "gpio1", +}; + +static const char *const qup0_se1_groups[] = { + "gpio5", "gpio4", "gpio4", "gpio28", "gpio5", "gpio29", +}; + +static const char *const qup0_se2_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31", +}; + +static const char *const qup0_se3_groups[] = { + "gpio10", "gpio11", "gpio11", "gpio10", +}; + +static const char *const qup0_se4_groups[] = { + "gpio12", "gpio13", "gpio13", "gpio12", +}; + +static const char *const qup0_se5_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char *const qup0_se6_groups[] = { + "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", + "gpio31", +}; + +static const char *const qup0_se7_groups[] = { + "gpio20", "gpio21", "gpio21", "gpio20", +}; + +static const char *const qup0_se8_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char *const qup0_se9_groups[] = { + "gpio27", "gpio48", "gpio26", "gpio49", "gpio26", + "gpio50", "gpio27", "gpio51", +}; + +static const char *const rgmii0_mdc_groups[] = { + "gpio134", +}; + +static const char *const rgmii0_mdio_groups[] = { + "gpio133", +}; + +static const char *const rgmii0_rx_ctl_groups[] = { + "gpio122", +}; + +static const char *const rgmii0_rxc_groups[] = { + "gpio121", +}; + +static const char *const rgmii0_rxd0_groups[] = { + "gpio123", +}; + +static const char *const rgmii0_rxd1_groups[] = { + "gpio124", +}; + +static const char *const rgmii0_rxd2_groups[] = { + "gpio125", +}; + +static const char *const rgmii0_rxd3_groups[] = { + "gpio126", +}; + +static const char *const rgmii0_tx_ctl_groups[] = { + "gpio128", +}; + +static const char *const rgmii0_txc_groups[] = { + "gpio127", +}; + +static const char *const rgmii0_txd0_groups[] = { + "gpio129", +}; + +static const char *const rgmii0_txd1_groups[] = { + "gpio130", +}; + +static const char *const rgmii0_txd2_groups[] = { + "gpio131", +}; + +static const char *const rgmii0_txd3_groups[] = { + "gpio132", +}; + +static const char *const rgmii1_mdc_groups[] = { + "gpio150", +}; + +static const char *const rgmii1_mdio_groups[] = { + "gpio149", +}; + +static const char *const rgmii1_rx_ctl_groups[] = { + "gpio138", +}; + +static const char *const rgmii1_rxc_groups[] = { + "gpio137", +}; + +static const char *const rgmii1_rxd0_groups[] = { + "gpio139", +}; + +static const char *const rgmii1_rxd1_groups[] = { + "gpio140", +}; + +static const char *const rgmii1_rxd2_groups[] = { + "gpio141", +}; + +static const char *const rgmii1_rxd3_groups[] = { + "gpio142", +}; + +static const char *const rgmii1_tx_ctl_groups[] = { + "gpio144", +}; + +static const char *const rgmii1_txc_groups[] = { + "gpio143", +}; + +static const char *const rgmii1_txd0_groups[] = { + "gpio145", +}; + +static const char *const rgmii1_txd1_groups[] = { + "gpio146", +}; + +static const char *const rgmii1_txd2_groups[] = { + "gpio147", +}; + +static const char *const rgmii1_txd3_groups[] = { + "gpio148", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio109", +}; + +static const char *const sdc1_tb_trig_groups[] = { + "gpio33", +}; + +static const char *const sdc2_tb_trig_groups[] = { + "gpio32", +}; + +static const char *const ssbi_wtr0_groups[] = { + "gpio70", +}; + +static const char *const ssbi_wtr1_groups[] = { + "gpio71", +}; + +static const char *const ssbi_wtr2_groups[] = { + "gpio68", +}; + +static const char *const ssbi_wtr3_groups[] = { + "gpio69", +}; + +static const char *const swr0_rx_clk_groups[] = { + "gpio107", +}; + +static const char *const swr0_rx_data0_groups[] = { + "gpio108", +}; + +static const char *const swr0_rx_data1_groups[] = { + "gpio109", +}; + +static const char *const swr0_tx_clk_groups[] = { + "gpio105", +}; + +static const char *const swr0_tx_data0_groups[] = { + "gpio106", +}; + +static const char *const tgu_ch0_trigout_groups[] = { + "gpio14", +}; + +static const char *const tgu_ch1_trigout_groups[] = { + "gpio15", +}; + +static const char *const tgu_ch2_trigout_groups[] = { + "gpio16", +}; + +static const char *const tgu_ch3_trigout_groups[] = { + "gpio17", +}; + +static const char *const tsc_async_groups[] = { + "gpio45", "gpio46", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio21", +}; + +static const char *const uim1_clk_groups[] = { + "gpio82", +}; + +static const char *const uim1_data_groups[] = { + "gpio81", +}; + +static const char *const uim1_present_groups[] = { + "gpio84", +}; + +static const char *const uim1_reset_groups[] = { + "gpio83", +}; + +static const char *const uim2_clk_groups[] = { + "gpio78", +}; + +static const char *const uim2_data_groups[] = { + "gpio77", +}; + +static const char *const uim2_present_groups[] = { + "gpio80", +}; + +static const char *const uim2_reset_groups[] = { + "gpio79", +}; + +static const char *const unused_adsp_groups[] = { + "gpio35", +}; + +static const char *const unused_gsm1_groups[] = { + "gpio64", +}; + +static const char *const usb0_phy_ps_groups[] = { + "gpio90", +}; + +static const char *const vfr_1_groups[] = { + "gpio59", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio58", +}; + +static const char *const wlan1_adc0_groups[] = { + "gpio14", +}; + +static const char *const wlan1_adc1_groups[] = { + "gpio15", +}; + + +static const struct pinfunction shikra_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_bbrx), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_gpsadc), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in0), + MSM_PIN_FUNCTION(cci_i2c_scl0), + MSM_PIN_FUNCTION(cci_i2c_scl1), + MSM_PIN_FUNCTION(cci_i2c_sda0), + MSM_PIN_FUNCTION(cci_i2c_sda1), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(char_exec_pending), + MSM_PIN_FUNCTION(char_exec_release), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dac_calib), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(dmic1_clk), + MSM_PIN_FUNCTION(dmic1_data), + MSM_PIN_FUNCTION(emac0_dll), + MSM_PIN_FUNCTION(emac0_mcg0), + MSM_PIN_FUNCTION(emac0_mcg1), + MSM_PIN_FUNCTION(emac0_mcg2), + MSM_PIN_FUNCTION(emac0_mcg3), + MSM_PIN_FUNCTION(emac0_phy), + MSM_PIN_FUNCTION(emac0_ptp), + MSM_PIN_FUNCTION(emac1_dll), + MSM_PIN_FUNCTION(emac1_mcg0), + MSM_PIN_FUNCTION(emac1_mcg1), + MSM_PIN_FUNCTION(emac1_mcg2), + MSM_PIN_FUNCTION(emac1_mcg3), + MSM_PIN_FUNCTION(emac1_phy), + MSM_PIN_FUNCTION(emac1_ptp), + MSM_PIN_FUNCTION(ext_mclk), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(i2s0_clk), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_data2), + MSM_PIN_FUNCTION(i2s0_data3), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(i2s1_clk), + MSM_PIN_FUNCTION(i2s1_data0), + MSM_PIN_FUNCTION(i2s1_data1), + MSM_PIN_FUNCTION(i2s1_ws), + MSM_PIN_FUNCTION(i2s2_clk), + MSM_PIN_FUNCTION(i2s2_data0), + MSM_PIN_FUNCTION(i2s2_data1), + MSM_PIN_FUNCTION(i2s2_ws), + MSM_PIN_FUNCTION(i2s3_clk), + MSM_PIN_FUNCTION(i2s3_data0), + MSM_PIN_FUNCTION(i2s3_data1), + MSM_PIN_FUNCTION(i2s3_ws), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync_s), + MSM_PIN_FUNCTION(mpm_pwr), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator_or), + MSM_PIN_FUNCTION(pbs_in), + MSM_PIN_FUNCTION(pbs_out), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(pll_reset_n), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwm_0), + MSM_PIN_FUNCTION(pwm_1), + MSM_PIN_FUNCTION(pwm_2), + MSM_PIN_FUNCTION(pwm_3), + MSM_PIN_FUNCTION(pwm_4), + MSM_PIN_FUNCTION(pwm_5), + MSM_PIN_FUNCTION(pwm_6), + MSM_PIN_FUNCTION(pwm_7), + MSM_PIN_FUNCTION(pwm_8), + MSM_PIN_FUNCTION(pwm_9), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup0_se6), + MSM_PIN_FUNCTION(qup0_se7), + MSM_PIN_FUNCTION(qup0_se8), + MSM_PIN_FUNCTION(qup0_se9), + MSM_PIN_FUNCTION(rgmii0_mdc), + MSM_PIN_FUNCTION(rgmii0_mdio), + MSM_PIN_FUNCTION(rgmii0_rx_ctl), + MSM_PIN_FUNCTION(rgmii0_rxc), + MSM_PIN_FUNCTION(rgmii0_rxd0), + MSM_PIN_FUNCTION(rgmii0_rxd1), + MSM_PIN_FUNCTION(rgmii0_rxd2), + MSM_PIN_FUNCTION(rgmii0_rxd3), + MSM_PIN_FUNCTION(rgmii0_tx_ctl), + MSM_PIN_FUNCTION(rgmii0_txc), + MSM_PIN_FUNCTION(rgmii0_txd0), + MSM_PIN_FUNCTION(rgmii0_txd1), + MSM_PIN_FUNCTION(rgmii0_txd2), + MSM_PIN_FUNCTION(rgmii0_txd3), + MSM_PIN_FUNCTION(rgmii1_mdc), + MSM_PIN_FUNCTION(rgmii1_mdio), + MSM_PIN_FUNCTION(rgmii1_rx_ctl), + MSM_PIN_FUNCTION(rgmii1_rxc), + MSM_PIN_FUNCTION(rgmii1_rxd0), + MSM_PIN_FUNCTION(rgmii1_rxd1), + MSM_PIN_FUNCTION(rgmii1_rxd2), + MSM_PIN_FUNCTION(rgmii1_rxd3), + MSM_PIN_FUNCTION(rgmii1_tx_ctl), + MSM_PIN_FUNCTION(rgmii1_txc), + MSM_PIN_FUNCTION(rgmii1_txd0), + MSM_PIN_FUNCTION(rgmii1_txd1), + MSM_PIN_FUNCTION(rgmii1_txd2), + MSM_PIN_FUNCTION(rgmii1_txd3), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc1_tb_trig), + MSM_PIN_FUNCTION(sdc2_tb_trig), + MSM_PIN_FUNCTION(ssbi_wtr0), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(ssbi_wtr2), + MSM_PIN_FUNCTION(ssbi_wtr3), + MSM_PIN_FUNCTION(swr0_rx_clk), + MSM_PIN_FUNCTION(swr0_rx_data0), + MSM_PIN_FUNCTION(swr0_rx_data1), + MSM_PIN_FUNCTION(swr0_tx_clk), + MSM_PIN_FUNCTION(swr0_tx_data0), + MSM_PIN_FUNCTION(tgu_ch0_trigout), + MSM_PIN_FUNCTION(tgu_ch1_trigout), + MSM_PIN_FUNCTION(tgu_ch2_trigout), + MSM_PIN_FUNCTION(tgu_ch3_trigout), + MSM_PIN_FUNCTION(tsc_async), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(unused_adsp), + MSM_PIN_FUNCTION(unused_gsm1), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup shikra_groups[] = { + [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _, 0, -1), + [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist_fail, _, phase_flag, atest_tsens, _, _, _, + _, _, 0, -1), + [2] = PINGROUP(2, qup0_se0, ddr_bist_start, _, phase_flag, atest_tsens2, _, _, _, _, _, _, + 0, -1), + [3] = PINGROUP(3, qup0_se0, ddr_bist_stop, _, phase_flag, dac_calib, _, _, _, _, _, _, + 0, -1), + [4] = PINGROUP(4, qup0_se1, qup0_se1, ddr_bist_complete, _, phase_flag, dac_calib, _, _, + _, _, _, 0, -1), + [5] = PINGROUP(5, qup0_se1, qup0_se1, _, phase_flag, dac_calib, _, _, _, _, _, _, 0, -1), + [6] = PINGROUP(6, qup0_se2, cri_trng0, _, phase_flag, dac_calib, _, _, _, _, _, _, 0, -1), + [7] = PINGROUP(7, qup0_se2, cri_trng1, _, phase_flag, dac_calib, _, _, _, _, _, _, 0, -1), + [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _, 0, -1), + [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _, 0, -1), + [10] = PINGROUP(10, qup0_se3, qup0_se3, _, _, _, _, _, _, _, _, _, 0, -1), + [11] = PINGROUP(11, qup0_se3, qup0_se3, _, phase_flag, _, _, _, _, _, _, _, 0, -1), + [12] = PINGROUP(12, qup0_se4, qup0_se4, char_exec_release, _, _, _, _, _, _, _, _, 0, -1), + [13] = PINGROUP(13, qup0_se4, qup0_se4, char_exec_pending, _, _, _, _, _, _, _, _, 0, -1), + [14] = PINGROUP(14, qup0_se5, pll_clk, tgu_ch0_trigout, dac_calib, wlan1_adc0, _, _, _, _, + _, _, 0, -1), + [15] = PINGROUP(15, qup0_se5, tgu_ch1_trigout, _, dac_calib, wlan1_adc1, _, _, _, _, _, _, + 0, -1), + [16] = PINGROUP(16, qup0_se5, tgu_ch2_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _, + 0, -1), + [17] = PINGROUP(17, qup0_se5, tgu_ch3_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _, + 0, -1), + [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _, 0, -1), + [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _, 0, -1), + [20] = PINGROUP(20, qup0_se7, qup0_se7, cri_trng, _, _, _, _, _, _, _, _, 0, -1), + [21] = PINGROUP(21, qup0_se7, qup0_se7, tsense_pwm, _, _, _, _, _, _, _, _, 0, -1), + [22] = PINGROUP(22, qup0_se8, pll_clk, agera_pll, pbs_out, _, _, _, _, _, _, _, 0, -1), + [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _, 0, -1), + [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _, 0, -1), + [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _, 0, -1), + [26] = PINGROUP(26, qup0_se9, qup0_se9, _, _, _, _, _, _, _, _, _, 0, -1), + [27] = PINGROUP(27, qup0_se9, qup0_se9, prng_rosc, _, _, _, _, _, _, _, _, 0, -1), + [28] = PINGROUP(28, qup0_se1, qup0_se6, emac1_mcg1, prng_rosc, _, phase_flag, qdss_cti, + _, _, _, _, 0, -1), + [29] = PINGROUP(29, qup0_se1, qup0_se6, emac1_mcg0, _, phase_flag, qdss_cti, _, _, _, _, + _, 0, -1), + [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _, 0, -1), + [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp, emac1_ptp, _, phase_flag, qdss_cti, _, + _, _, _, 0, -1), + [32] = PINGROUP(32, pwm_0, sdc2_tb_trig, _, _, _, _, _, _, _, _, _, 0, -1), + [33] = PINGROUP(33, emac1_ptp, emac1_ptp, sdc1_tb_trig, _, _, _, _, _, _, _, _, 0, -1), + [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _, 0, -1), + [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _, 0, -1), + [36] = PINGROUP(36, cci_i2c_sda0, _, _, _, _, _, _, _, _, _, _, 0, -1), + [37] = PINGROUP(37, cci_i2c_scl0, _, _, _, _, _, _, _, _, _, _, 0, -1), + [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _, 0, -1), + [39] = PINGROUP(39, cci_async_in0, _, _, _, _, _, _, _, _, _, _, 0, -1), + [40] = PINGROUP(40, cci_timer, emac1_mcg2, pwm_1, _, _, _, _, _, _, _, _, 0, -1), + [41] = PINGROUP(41, cci_i2c_sda1, _, _, _, _, _, _, _, _, _, _, 0, -1), + [42] = PINGROUP(42, cci_i2c_scl1, _, _, _, _, _, _, _, _, _, _, 0, -1), + [43] = PINGROUP(43, cci_timer, emac0_mcg3, pll_bist, _, _, _, _, _, _, _, _, 0, -1), + [44] = PINGROUP(44, emac0_mcg2, pll_bist, _, _, _, _, _, _, _, _, _, 0, -1), + [45] = PINGROUP(45, tsc_async, emac0_mcg1, pwm_7, gcc_gp1, _, _, _, _, _, _, _, 0, -1), + [46] = PINGROUP(46, tsc_async, emac0_mcg0, _, _, _, _, _, _, _, _, _, 0, -1), + [47] = PINGROUP(47, cci_timer, emac1_mcg3, _, _, _, _, _, _, _, _, _, 0, -1), + [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _, 0, -1), + [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _, 0, -1), + [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _, 0, -1), + [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _, 0, -1), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [53] = PINGROUP(53, _, nav_gpio, gcc_gp3, pwm_7, _, pbs_in, atest_usb, _, _, _, _, 0, -1), + [54] = PINGROUP(54, _, pwm_1, _, pbs_in, phase_flag, atest_char, _, _, _, _, _, 0, -1), + [55] = PINGROUP(55, _, pwm_0, _, pbs_in, phase_flag, atest_char, _, _, _, _, _, 0, -1), + [56] = PINGROUP(56, _, pwm_6, _, pbs_in, phase_flag, atest_char, _, _, _, _, _, 0, -1), + [57] = PINGROUP(57, _, pwm_2, _, pbs_in, phase_flag, atest_char, _, _, _, _, _, 0, -1), + [58] = PINGROUP(58, _, nav_gpio, pwm_8, _, pbs_in, atest_bbrx, atest_usb, + vsense_trigger_mirnat, emac1_dll, _, _, 0, -1), + [59] = PINGROUP(59, _, vfr_1, _, pbs_in, atest_bbrx, atest_usb, emac1_dll, _, _, _, _, + 0, -1), + [60] = PINGROUP(60, _, emac1_ptp, emac1_ptp, emac0_ptp, emac0_ptp, _, pbs_in, + atest_gpsadc, atest_usb, emac0_dll, _, 0, -1), + [61] = PINGROUP(61, _, pwm_9, gcc_gp2, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb, + emac0_dll, _, _, _, 0, -1), + [62] = PINGROUP(62, _, pwm_2, _, pbs_in, phase_flag, atest_char, _, _, _, _, + _, 0, -1), + [63] = PINGROUP(63, _, nav_gpio, emac0_ptp, emac0_ptp, _, pbs_in, phase_flag, dac_calib, + _, _, _, 0, -1), + [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _, 0, -1), + [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _, 0, -1), + [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [68] = PINGROUP(68, _, ssbi_wtr2, emac1_ptp, emac1_ptp, pwm_9, dac_calib, _, _, _, _, _, + 0, -1), + [69] = PINGROUP(69, _, ssbi_wtr3, emac0_ptp, emac0_ptp, _, phase_flag, dac_calib, _, _, _, + _, 0, -1), + [70] = PINGROUP(70, _, ssbi_wtr0, _, phase_flag, dac_calib, _, _, _, _, _, _, 0, -1), + [71] = PINGROUP(71, _, ssbi_wtr1, nav_gpio, _, phase_flag, _, _, _, _, _, _, 0, -1), + [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _, 0, -1), + [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [74] = PINGROUP(74, pll_reset_n, _, pbs_in, phase_flag, _, _, _, _, _, _, _, 0, -1), + [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _, 0, -1), + [76] = PINGROUP(76, pll_bypassnl, _, _, _, _, _, _, _, _, _, _, 0, -1), + [77] = PINGROUP(77, uim2_data, pwm_3, _, _, _, _, _, _, _, _, _, 0, -1), + [78] = PINGROUP(78, uim2_clk, _, _, _, _, _, _, _, _, _, _, 0, -1), + [79] = PINGROUP(79, uim2_reset, pwm_4, _, _, _, _, _, _, _, _, _, 0, -1), + [80] = PINGROUP(80, uim2_present, pwm_5, _, _, _, _, _, _, _, _, _, 0, -1), + [81] = PINGROUP(81, uim1_data, _, _, _, _, _, _, _, _, _, _, 0, -1), + [82] = PINGROUP(82, uim1_clk, _, _, _, _, _, _, _, _, _, _, 0, -1), + [83] = PINGROUP(83, uim1_reset, _, _, _, _, _, _, _, _, _, _, 0, -1), + [84] = PINGROUP(84, uim1_present, _, _, _, _, _, _, _, _, _, _, 0, -1), + [85] = PINGROUP(85, emac0_ptp, emac0_ptp, _, _, _, _, _, _, _, _, _, 0, -1), + [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync, mdp_vsync, _, _, _, _, _, _, _, _, 0, -1), + [87] = PINGROUP(87, _, pwm_6, _, _, _, _, _, _, _, _, _, 0, -1), + [88] = PINGROUP(88, gcc_gp2, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), + [89] = PINGROUP(89, gcc_gp3, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), + [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), + [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _, 0, -1), + [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _, 0, -1), + [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _, 0, -1), + [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _, 0, -1), + [96] = PINGROUP(96, dmic0_clk, cam_mclk, i2s1_clk, jitter_bist, atest_gpsadc, atest_usb, _, + _, _, _, _, 0, -1), + [97] = PINGROUP(97, dmic0_data, i2s1_ws, dac_calib, _, _, _, _, _, _, _, _, 0, -1), + [98] = PINGROUP(98, dmic1_clk, cam_mclk, i2s1_data0, _, _, atest_usb, ddr_pxi0, _, _, _, + _, 0, -1), + [99] = PINGROUP(99, dmic1_data, i2s1_data1, jitter_bist, _, atest_usb, ddr_pxi0, _, _, _, + _, _, 0, -1), + [100] = PINGROUP(100, i2s2_clk, nav_gpio, _, _, atest_usb, ddr_pxi1, _, _, _, _, _, 0, -1), + [101] = PINGROUP(101, i2s2_ws, nav_gpio, _, _, atest_usb, ddr_pxi1, _, _, _, _, _, 0, -1), + [102] = PINGROUP(102, i2s2_data0, pwm_8, _, phase_flag, _, _, _, _, _, _, _, 0, -1), + [103] = PINGROUP(103, ext_mclk, i2s2_data1, _, _, _, _, _, _, _, _, _, 0, -1), + [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _, 0, -1), + [105] = PINGROUP(105, swr0_tx_clk, i2s0_clk, _, _, _, _, _, _, _, _, _, 0, -1), + [106] = PINGROUP(106, swr0_tx_data0, i2s0_ws, _, _, _, _, _, _, _, _, _, 0, -1), + [107] = PINGROUP(107, swr0_rx_clk, i2s0_data0, _, _, _, _, _, _, _, _, _, 0, -1), + [108] = PINGROUP(108, swr0_rx_data0, i2s0_data1, _, _, _, _, _, _, _, _, _, 0, -1), + [109] = PINGROUP(109, swr0_rx_data1, i2s0_data2, sd_write_protect, _, _, _, _, _, _, _, _, + 0, -1), + [110] = PINGROUP(110, ext_mclk, i2s0_data3, _, gcc_gp1, _, _, _, _, _, _, _, 0, -1), + [111] = PINGROUP(111, i2s3_clk, _, _, _, _, _, _, _, _, _, _, 0, -1), + [112] = PINGROUP(112, i2s3_ws, _, _, _, _, _, _, _, _, _, _, 0, -1), + [113] = PINGROUP(113, i2s3_data0, _, _, _, _, _, _, _, _, _, _, 0, -1), + [114] = PINGROUP(114, ext_mclk, i2s3_data1, _, _, _, _, _, _, _, _, _, 0, -1), + [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _, 0, -1), + [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), + [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), + [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _, 0, -1), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [120] = PINGROUP(120, emac0_phy, _, _, _, _, _, _, _, _, _, _, 0, -1), + [121] = PINGROUP(121, rgmii0_rxc, _, _, _, _, _, _, _, _, _, _, 0, -1), + [122] = PINGROUP(122, rgmii0_rx_ctl, _, _, _, _, _, _, _, _, _, _, 0, -1), + [123] = PINGROUP(123, rgmii0_rxd0, _, _, _, _, _, _, _, _, _, _, 0, -1), + [124] = PINGROUP(124, rgmii0_rxd1, _, _, _, _, _, _, _, _, _, _, 0, -1), + [125] = PINGROUP(125, rgmii0_rxd2, _, _, _, _, _, _, _, _, _, _, 0, -1), + [126] = PINGROUP(126, rgmii0_rxd3, _, _, _, _, _, _, _, _, _, _, 0, -1), + [127] = PINGROUP(127, rgmii0_txc, _, _, _, _, _, _, _, _, _, _, 0, -1), + [128] = PINGROUP(128, rgmii0_tx_ctl, _, _, _, _, _, _, _, _, _, _, 0, -1), + [129] = PINGROUP(129, rgmii0_txd0, _, _, _, _, _, _, _, _, _, _, 0, -1), + [130] = PINGROUP(130, rgmii0_txd1, _, _, _, _, _, _, _, _, _, _, 0, -1), + [131] = PINGROUP(131, rgmii0_txd2, _, _, _, _, _, _, _, _, _, _, 0, -1), + [132] = PINGROUP(132, rgmii0_txd3, _, _, _, _, _, _, _, _, _, _, 0, -1), + [133] = PINGROUP(133, rgmii0_mdio, _, _, _, _, _, _, _, _, _, _, 0, -1), + [134] = PINGROUP(134, rgmii0_mdc, _, _, _, _, _, _, _, _, _, _, 0, -1), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [136] = PINGROUP(136, emac1_phy, _, _, _, _, _, _, _, _, _, _, 0, -1), + [137] = PINGROUP(137, rgmii1_rxc, _, _, _, _, _, _, _, _, _, _, 0, -1), + [138] = PINGROUP(138, rgmii1_rx_ctl, _, _, _, _, _, _, _, _, _, _, 0, -1), + [139] = PINGROUP(139, rgmii1_rxd0, _, _, _, _, _, _, _, _, _, _, 0, -1), + [140] = PINGROUP(140, rgmii1_rxd1, _, _, _, _, _, _, _, _, _, _, 0, -1), + [141] = PINGROUP(141, rgmii1_rxd2, _, _, _, _, _, _, _, _, _, _, 0, -1), + [142] = PINGROUP(142, rgmii1_rxd3, _, _, _, _, _, _, _, _, _, _, 0, -1), + [143] = PINGROUP(143, rgmii1_txc, _, _, _, _, _, _, _, _, _, _, 0, -1), + [144] = PINGROUP(144, rgmii1_tx_ctl, _, _, _, _, _, _, _, _, _, _, 0, -1), + [145] = PINGROUP(145, rgmii1_txd0, _, _, _, _, _, _, _, _, _, _, 0, -1), + [146] = PINGROUP(146, rgmii1_txd1, _, _, _, _, _, _, _, _, _, _, 0, -1), + [147] = PINGROUP(147, rgmii1_txd2, _, _, _, _, _, _, _, _, _, _, 0, -1), + [148] = PINGROUP(148, rgmii1_txd3, _, _, _, _, _, _, _, _, _, _, 0, -1), + [149] = PINGROUP(149, rgmii1_mdio, _, _, _, _, _, _, _, _, _, _, 0, -1), + [150] = PINGROUP(150, rgmii1_mdc, _, _, _, _, _, _, _, _, _, _, 0, -1), + [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _, 0, -1), + [162] = SDC_QDSD_PINGROUP(sdc1_data, 0x1AC000, 9, 0), + [163] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1AC004, 0, 0), + [164] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1AC000, 11, 3), + [165] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1AC000, 13, 6), + [166] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1AA000, 14, 6), + [167] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1AA000, 11, 3), + [168] = SDC_QDSD_PINGROUP(sdc2_data, 0x1AA000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map shikra_pdc_map[] = { + +}; + +static const struct msm_pinctrl_soc_data shikra_tlmm = { + .pins = shikra_pins, + .npins = ARRAY_SIZE(shikra_pins), + .functions = shikra_functions, + .nfunctions = ARRAY_SIZE(shikra_functions), + .groups = shikra_groups, + .ngroups = ARRAY_SIZE(shikra_groups), + .ngpios = 166, + .wakeirq_map = shikra_pdc_map, + .nwakeirq_map = ARRAY_SIZE(shikra_pdc_map), + .egpio_func = 11, +}; + +static int shikra_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &shikra_tlmm); +} + +static const struct of_device_id shikra_tlmm_of_match[] = { + { .compatible = "qcom,shikra-tlmm", .data = &shikra_tlmm }, + {}, +}; + +static struct platform_driver shikra_tlmm_driver = { + .driver = { + .name = "shikra-tlmm", + .of_match_table = shikra_tlmm_of_match, + }, + .probe = shikra_tlmm_probe, +}; + +static int __init shikra_tlmm_init(void) +{ + return platform_driver_register(&shikra_tlmm_driver); +} +arch_initcall(shikra_tlmm_init); + +static void __exit shikra_tlmm_exit(void) +{ + platform_driver_unregister(&shikra_tlmm_driver); +} +module_exit(shikra_tlmm_exit); + +MODULE_DESCRIPTION("QTI Shikra TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match); From 357c3c116b2a91771e07f6ecf17c022c9dccdb19 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 3 Mar 2026 18:26:31 +0530 Subject: [PATCH 0354/1330] arm64: dts: qcom: Introduce Shikra Soc base dtsi Introduce the initial support for the Qualcomm Shikra SoC. The initial submission enables support for: - CPUs nodes with PSCI idle states - Interrupt-controller - Top Level Mode Multiplexer (TLMM) - System Timer Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 240 +++++++++++++++++++++++++++ 1 file changed, 240 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra.dtsi diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi new file mode 100644 index 0000000000000..d5076652660aa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a78c"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&l2_3>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <486>; + + l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu3>; + }; + }; + }; + + l3: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + tlmm: pinctrl@500000 { + compatible = "qcom,shikra-tlmm"; + reg = <0x0 0x00500000 0x0 0x800000>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 185>; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + }; + + sram@c11e000 { + compatible = "qcom,shikra-imem", "syscon", "simple-mfd"; + reg = <0x0 0x0c11e000 0x0 0x1000>; + ranges = <0x0 0x0 0x0c11e000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xf200000 0x0 0x10000>, /* GICD */ + <0x0 0xf240000 0x0 0x80000>; /* GICR * 4 regions */ + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0f420000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x10000000>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@f423000 { + reg = <0x0f423000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = , + , + , + ; + }; +}; From 8ba3477129ed308a052f04f50b99e24ac5a6b2f6 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 3 Mar 2026 19:05:13 +0530 Subject: [PATCH 0355/1330] arm64: dts: qcom: Add Shikra IoT SoM platforms The Shikra SoM is a compact compute module integrating the SoC and essential components optimized for IoT applications, designed to mount on carrier boards. Shikra supports three SoM variants: two retail options (with and without modem) and one industrial variant , represented by the following device trees: - shikra-cqm-som.dtsi : Retail SoM with modem - shikra-cqs-som.dtsi : Retail SoM without modem - shikra-iqs-som.dtsi : Industrial SoM without modem Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi create mode 100644 arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi create mode 100644 arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi new file mode 100644 index 0000000000000..75ae79daf3b45 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "shikra.dtsi" + +/* Modem, Cocos + Kunlun PMIC */ diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi new file mode 100644 index 0000000000000..be745fe517e88 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "shikra.dtsi" + +/* APQ (No Modem), Cocos + Kunlun PMIC */ diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi new file mode 100644 index 0000000000000..a916caa73d823 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "shikra.dtsi" + +/* APQ (No Modem), Wailua PMIC */ From ab603176c5a9448e60e7f52f143df41245e6240a Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 3 Mar 2026 19:37:13 +0530 Subject: [PATCH 0356/1330] arm64: dts: qcom: Add Shikra EVK boards Add device trees for the Shikra EVK platform, which combines Shikra SoM with a common carrier board. Introduce DTS files for CQM, CQS and IQS EVK variants: - shikra-cqm-evk.dts - shikra-cqs-evk.dts - shikra-iqs-evk.dts Also add a shared include file, shikra-evk.dtsi, which contains the common daughter card nodes used across Shikra EVK variants. Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/Makefile | 3 +++ arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 21 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 21 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 21 +++++++++++++++++++++ 5 files changed, 80 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts create mode 100644 arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts create mode 100644 arch/arm64/boot/dts/qcom/shikra-evk.dtsi create mode 100644 arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cd7fcf1556bc6..fe5c8c0ab5a26 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -309,6 +309,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-huawei-matebook-e-2019.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts new file mode 100644 index 0000000000000..1bd1717a9d1f0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-cqm-som.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shikra CQM EVK"; + compatible = "qcom,shikra-cqm-evk", "qcom,shikra-cqm-som", "qcom,shikra"; + chassis-type = "embedded"; + + aliases { + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts new file mode 100644 index 0000000000000..89fd8d0ccdc56 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-cqs-som.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shikra CQS EVK"; + compatible = "qcom,shikra-cqs-evk", "qcom,shikra-cqs-som", "qcom,shikra"; + chassis-type = "embedded"; + + aliases { + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi new file mode 100644 index 0000000000000..cf7460e1125d6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Common daughter cards nodes to be added: + * QPS615 DC + * MIC DC + * Display DC + * Camera DC + * USB hub DC + * Sensor DC + * NFC DC + */ diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts new file mode 100644 index 0000000000000..f0e9da31909dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-iqs-som.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shikra IQS EVK"; + compatible = "qcom,shikra-iqs-evk", "qcom,shikra-iqs-som", "qcom,shikra"; + chassis-type = "embedded"; + + aliases { + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; From a75a5849257781503323d28506ba0251a0bcfefc Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Mon, 2 Feb 2026 14:30:57 +0800 Subject: [PATCH 0357/1330] FROMLIST: wifi: ath12k: fix incorrect channel survey index A wrong channel survey index was introduced in ath12k_mac_op_get_survey by [1], which can cause ACS to fail. The index is decremented before being used, resulting in an incorrect value when accessing the channel survey data. Fix the index handling to ensure the correct survey entry is used and avoid ACS failures. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: 4f242b1d6996 ("wifi: ath12k: support get_survey mac op for single wiphy") # [1] Signed-off-by: Yingying Tang --- drivers/net/wireless/ath/ath12k/mac.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c index 6869e9860776d..dd9a7ddb66e68 100644 --- a/drivers/net/wireless/ath/ath12k/mac.c +++ b/drivers/net/wireless/ath/ath12k/mac.c @@ -13337,6 +13337,7 @@ int ath12k_mac_op_get_survey(struct ieee80211_hw *hw, int idx, struct ath12k *ar; struct ieee80211_supported_band *sband; struct survey_info *ar_survey; + int orig_idx = idx; lockdep_assert_wiphy(hw->wiphy); @@ -13371,7 +13372,7 @@ int ath12k_mac_op_get_survey(struct ieee80211_hw *hw, int idx, return -ENOENT; } - ar_survey = &ar->survey[idx]; + ar_survey = &ar->survey[orig_idx]; ath12k_mac_update_bss_chan_survey(ar, &sband->channels[idx]); From 55b7a94da2611bb949c97bf51d1a1a82a32da3ee Mon Sep 17 00:00:00 2001 From: Baochen Qiang Date: Wed, 25 Feb 2026 14:25:40 +0800 Subject: [PATCH 0358/1330] FROMLIST: wifi: ath12k: prepare REO update element only for primary link Commit [1] introduces dp->reo_cmd_update_rx_queue_list for the purpose of tracking all pending REO queue flush commands. The helper ath12k_dp_prepare_reo_update_elem() allocates an element and populates it with REO queue information, then add it to the list. The element would be helpful during clean up stage to finally unmap/free the corresponding REO queue buffer. In MLO scenarios with more than one links, for non dp_primary_link_only chips like WCN7850, that helper is called for each link peer. This results in multiple elements added to the list but all of them pointing to the same REO queue buffer. Consequently the same buffer gets unmap/freed multiple times: BUG kmalloc-2k (Tainted: G B W O ): Object already free ----------------------------------------------------------------------------- Allocated in ath12k_wifi7_dp_rx_assign_reoq+0xce/0x280 [ath12k_wifi7] age=7436 cpu=10 pid=16130 __kmalloc_noprof ath12k_wifi7_dp_rx_assign_reoq ath12k_dp_rx_peer_tid_setup ath12k_dp_peer_setup ath12k_mac_station_add ath12k_mac_op_sta_state [...] Freed in ath12k_dp_rx_tid_cleanup.part.0+0x25/0x40 [ath12k] age=1 cpu=27 pid=16137 kfree ath12k_dp_rx_tid_cleanup.part.0 ath12k_dp_rx_reo_cmd_list_cleanup ath12k_dp_cmn_device_deinit ath12k_core_stop ath12k_core_hw_group_cleanup ath12k_pci_remove Fix this by allowing list addition for primary link only. Note dp_primary_link_only chips like QCN9274 are not affected by this change, because that's what they were doing in the first place. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: 3bf2e57e7d6c ("wifi: ath12k: Add Retry Mechanism for REO RX Queue Update Failures") # [1] Closes: https://bugzilla.kernel.org/show_bug.cgi?id=221011 Signed-off-by: Baochen Qiang Signed-off-by: Yingying Tang --- drivers/net/wireless/ath/ath12k/dp_rx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.c b/drivers/net/wireless/ath/ath12k/dp_rx.c index 244d5230a5bd8..40d85d1689750 100644 --- a/drivers/net/wireless/ath/ath12k/dp_rx.c +++ b/drivers/net/wireless/ath/ath12k/dp_rx.c @@ -565,6 +565,9 @@ static int ath12k_dp_prepare_reo_update_elem(struct ath12k_dp *dp, lockdep_assert_held(&dp->dp_lock); + if (!peer->primary_link) + return 0; + elem = kzalloc_obj(*elem, GFP_ATOMIC); if (!elem) return -ENOMEM; From 8e36aa64d8f2f62e30d5a528d65c28db6eeaaca1 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Fri, 13 Mar 2026 14:59:50 +0530 Subject: [PATCH 0359/1330] QCLINUX: arm64: dts: qcom: lemans: Fix comment typo in camx EL2 dtso. Fix a typo in the camx EL2 device tree by removing comments all together. The mistake was masked by a later comment terminator. Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso b/arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso index 83b5605f026a8..c7ddbc01a0070 100644 --- a/arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-camx-el2.dtso @@ -7,7 +7,6 @@ /plugin/; / { - /* cam_cpas label -> /soc@0/qcom,cam-cpas * fragment@0 { target-path = "/soc@0/qcom,cam-cpas"; __overlay__ { @@ -15,7 +14,6 @@ }; }; - /* cam_icp_firmware label -> /soc@0/qcom,cam-icp */ fragment@1 { target-path = "/soc@0/qcom,cam-icp"; __overlay__ { From 9523181c5a84f708fc6e2927db1dd67fa1219c7b Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Fri, 13 Mar 2026 19:24:42 +0530 Subject: [PATCH 0360/1330] QCLINUX: arm64: dts: qcom: monaco: Add CamX EL2 overlay Add camx el2 DT overlay for lemans platforms. The overlay updates the ICP firmware node with Secure SMMU SID and disables secure QoS updates for CPAS in EL2/KVM configurations. Wire up the new overlay-built DTBs in the qcom DT Makefile so the corresponding *-camx-el2.dtb targets are generated. Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/Makefile | 4 +++ arch/arm64/boot/dts/qcom/monaco-camx-el2.dtso | 25 +++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-camx-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index fe5c8c0ab5a26..aaae2764012ec 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -447,6 +447,10 @@ monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb +monaco-camx-el2-dtbs := monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb + qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-camx-el2.dtso b/arch/arm64/boot/dts/qcom/monaco-camx-el2.dtso new file mode 100644 index 0000000000000..c7ddbc01a0070 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-camx-el2.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path = "/soc@0/qcom,cam-cpas"; + __overlay__ { + enable-secure-qos-update = <0>; + }; + }; + + fragment@1 { + target-path = "/soc@0/qcom,cam-icp"; + __overlay__ { + camera-firmware { + iommus = <&apps_smmu 0x08c1 0x0400>; + }; + }; + }; +}; From 2bc7d229486bcf0cffb9061391598ada6be7237d Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 20 Mar 2026 15:31:12 +0800 Subject: [PATCH 0361/1330] FROMLIST: coresight: platform: check the availability of the endpoint before parse Check endpoint availability before parsing it. If parsing a connected endpoint fails, the probe is deferred until the endpoint becomes available, or eventually fails. In some legacy cases, a replicator has two output ports where one is disabled and the other is available. The replicator probe always fails because the disabled endpoint never becomes available for parsing. In addition, there is no need to defer probing a device that is connected to a disabled device, which improves probe performance. Link: https://lore.kernel.org/all/20260320-add-availability-check-v1-1-b2e39cdeb6e0@oss.qualcomm.com/ Reviewed-by: Leo Yan Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-platform.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index 0db64c5f49959..2c2571652a788 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -220,6 +220,8 @@ static int of_coresight_parse_endpoint(struct device *dev, rparent = of_coresight_get_port_parent(rep); if (!rparent) break; + if (!of_device_is_available(rparent)) + break; if (of_graph_parse_endpoint(rep, &rendpoint)) break; From 4266000ff8eb5aad49dd55d4b5825dbc3e8981ea Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Thu, 11 Dec 2025 11:41:01 -0800 Subject: [PATCH 0362/1330] FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Glymur compatible Define a Glymur compatible string for the QMP combo PHY, along with resource requirements. Acked-by: Rob Herring (Arm) Signed-off-by: Wesley Cheng Link: https://lore.kernel.org/all/20251209-linux-next-12825-v8-1-42133596bda0@oss.qualcomm.com/ From a1ea19c21c87747a066b775165bed0e398426d19 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Thu, 11 Dec 2025 11:47:27 -0800 Subject: [PATCH 0363/1330] FROMLIST: dt-bindings: phy: qcom-m31-eusb2: Add Glymur compatible Add the Glymur compatible to the M31 eUSB2 PHY, and use the SM8750 as the fallback. Signed-off-by: Wesley Cheng Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20251209-linux-next-12825-v8-3-42133596bda0@oss.qualcomm.com/ From 46b93312fefcccba610fab756fb998d54b8d9a53 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Sat, 20 Dec 2025 12:05:35 +0530 Subject: [PATCH 0364/1330] usb: misc: onboard_usb_hub: Add Genesys Logic GL3590 hub support Add support for the GL3590 4 ports USB3.2 hub. This allows to control its reset pins with a gpio. Signed-off-by: Swati Agarwal --- drivers/usb/misc/onboard_usb_dev.c | 1 + drivers/usb/misc/onboard_usb_dev.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/usb/misc/onboard_usb_dev.c b/drivers/usb/misc/onboard_usb_dev.c index ba37eb99efbaf..b52dafeefcda9 100644 --- a/drivers/usb/misc/onboard_usb_dev.c +++ b/drivers/usb/misc/onboard_usb_dev.c @@ -661,6 +661,7 @@ static const struct usb_device_id onboard_dev_id_table[] = { { USB_DEVICE(VENDOR_ID_GENESYS, 0x0608) }, /* Genesys Logic GL850G USB 2.0 HUB */ { USB_DEVICE(VENDOR_ID_GENESYS, 0x0610) }, /* Genesys Logic GL852G USB 2.0 HUB */ { USB_DEVICE(VENDOR_ID_GENESYS, 0x0620) }, /* Genesys Logic GL3523 USB 3.1 HUB */ + { USB_DEVICE(VENDOR_ID_GENESYS, 0x0625) }, /* Genesys Logic GL3590 USB 3.2 HUB */ { USB_DEVICE(VENDOR_ID_MICROCHIP, 0x2412) }, /* USB2412 USB 2.0 HUB */ { USB_DEVICE(VENDOR_ID_MICROCHIP, 0x2514) }, /* USB2514B USB 2.0 HUB */ { USB_DEVICE(VENDOR_ID_MICROCHIP, 0x2517) }, /* USB2517 USB 2.0 HUB */ diff --git a/drivers/usb/misc/onboard_usb_dev.h b/drivers/usb/misc/onboard_usb_dev.h index 1a1e86e60e042..978acc662ce41 100644 --- a/drivers/usb/misc/onboard_usb_dev.h +++ b/drivers/usb/misc/onboard_usb_dev.h @@ -147,6 +147,7 @@ static const struct of_device_id onboard_dev_match[] = { { .compatible = "usb5e3,608", .data = &genesys_gl850g_data, }, { .compatible = "usb5e3,610", .data = &genesys_gl852g_data, }, { .compatible = "usb5e3,620", .data = &genesys_gl852g_data, }, + { .compatible = "usb5e3,625", .data = &genesys_gl852g_data, }, { .compatible = "usb5e3,626", .data = &genesys_gl852g_data, }, { .compatible = "usbbda,179", .data = &realtek_rtl8188etv_data, }, { .compatible = "usbbda,411", .data = &realtek_rts5411_data, }, From c3dc1b2ae7b6c5d4968c066640152155a0516971 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Sat, 20 Dec 2025 12:05:34 +0530 Subject: [PATCH 0365/1330] dt-bindings: usb: Add binding for Genesys Logic GL3590 hub Add the binding for the USB3.2 Genesys Logic GL3590 hub. Signed-off-by: Swati Agarwal --- .../devicetree/bindings/usb/genesys,gl850g.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml index 9a94b2a74a1eb..a184e1074c7c4 100644 --- a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml +++ b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml @@ -15,6 +15,7 @@ properties: - usb5e3,608 - usb5e3,610 - usb5e3,620 + - usb5e3,625 - usb5e3,626 reg: true @@ -69,6 +70,17 @@ allOf: peer-hub: true vdd-supply: true + - if: + properties: + compatible: + contains: + enum: + - usb5e3,625 + then: + properties: + peer-hub: true + vdd-supply: false + unevaluatedProperties: false examples: From 07ffa28c5df52845d91a1b5613d3681a459bcac1 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:22 -0800 Subject: [PATCH 0366/1330] FROMLIST: dt-bindings: soc: qcom: eud: Restructure to model multi-path hardware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Qualcomm Embedded USB Debugger (EUD) can intercept one or two independent High-Speed UTMI paths, depending on the SoC. Each path is distinct with its own HS-PHY interface, connector/controller wiring, and UTMI routing behavior. The EUD hardware sits between the USB2 PHY and the USB controller on each path. The existing binding models only a single UTMI path and does not provide a way to associate the required High-Speed USB PHY. EUD relies on the HS-PHY on the selected UTMI path for link signalling and correct operation of the hardware. Historically, EUD has worked on platforms that use a single UTMI path because the USB controller maintains ownership of the PHY during enumeration and normal operation. This implicit relationship allowed EUD to function even though the dependency on the PHY was not described in the binding. However, this behavior is not guaranteed by hardware. The current binding description is not sufficient for SoCs that expose two independent UTMI paths, where the PHY association and port wiring must be explicitly described. Introduce per-path eud-path child nodes so each UTMI path can describe its HS-PHY, port connections, and the role‑switching capability of its associated USB port. Signed-off-by: Elson Serrao Link: https://lore.kernel.org/linux-usb/20260126233830.2193816-2-elson.serrao@oss.qualcomm.com/ --- .../bindings/soc/qcom/qcom,eud.yaml | 100 +++++++++++++----- 1 file changed, 74 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index 84218636c0d8d..0507252dbf27e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -10,8 +10,11 @@ maintainers: - Souradeep Chowdhury description: - This binding is used to describe the Qualcomm Embedded USB Debugger, which is - mini USB-hub implemented on chip to support USB-based debug capabilities. + This binding describes the Qualcomm Embedded USB Debugger (EUD), an on-chip + mini USB hub that enables USB-based debug capabilities. The EUD block is + positioned between the High-Speed USB PHY and the USB controller, where it + intercepts the UTMI interface to support debug and bypass modes. EUD can be + supported on up to two High-Speed USB ports. properties: compatible: @@ -29,26 +32,62 @@ properties: description: EUD interrupt maxItems: 1 - ports: - $ref: /schemas/graph.yaml#/properties/ports + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^eud-path@[0-1]$": + type: object description: - These ports is to be attached to the endpoint of the DWC3 controller node - and type C connector node. The controller has the "usb-role-switch" - property. + Represents one High-Speed UTMI path that EUD intercepts. This node models + the physical data path intercepted by EUD and provides graph endpoints to + link the USB controller and the external connector associated with this path. properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: This port is to be attached to the DWC3 controller. + reg: + maxItems: 1 + description: Path number + + phys: + maxItems: 1 + description: High-Speed USB PHY associated with this data path. + + usb-role-switch: + type: boolean + description: + Set this property if the USB port on this path is role switch capable. + In device role, debug mode inserts the EUD hub into the UTMI path. In + host role, the EUD hub is bypassed and UTMI traffic flows directly + between the PHY and the USB controller. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: + These ports are to be attached to the endpoint of the USB controller node + and USB connector node. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: This port is to be attached to the USB controller. - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: This port is to be attached to the type C connector. + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: This port is to be attached to the USB connector. + + required: + - reg + - phys + - ports + + additionalProperties: false required: - compatible - reg - - ports additionalProperties: false @@ -58,21 +97,30 @@ examples: compatible = "qcom,sc7280-eud", "qcom,eud"; reg = <0x88e0000 0x2000>, <0x88e2000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + eud-path@0 { + reg = <0>; + phys = <&usb_1_hsphy>; + usb-role-switch; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - eud_ep: endpoint { - remote-endpoint = <&usb2_role_switch>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; }; - }; - port@1 { - reg = <1>; - eud_con: endpoint { - remote-endpoint = <&con_eud>; + port@1 { + reg = <1>; + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; }; }; }; From e054e56d8c27e9555e043cb40904380831c4e4cb Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:23 -0800 Subject: [PATCH 0367/1330] FROMLIST: usb: misc: qcom_eud: add sysfs attribute for port selection EUD can be mapped to either the primary USB port or the secondary USB port depending on the value of the EUD_PORT_SEL register. Add a 'port' sysfs attribute to allow userspace to select which port EUD should operate on and update the ABI documentation. This is needed for systems with dual USB ports where EUD needs to be accessible on either port depending on the system configuration and use case. Signed-off-by: Elson Serrao Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/linux-usb/20260126233830.2193816-3-elson.serrao@oss.qualcomm.com/ --- Documentation/ABI/testing/sysfs-driver-eud | 16 ++++++++ drivers/usb/misc/qcom_eud.c | 43 ++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI/testing/sysfs-driver-eud index 2bab0db2d2f0f..67223f73ee606 100644 --- a/Documentation/ABI/testing/sysfs-driver-eud +++ b/Documentation/ABI/testing/sysfs-driver-eud @@ -7,3 +7,19 @@ Description: EUD based on a 1 or a 0 value. By enabling EUD, the user is able to activate the mini-usb hub of EUD for debug and trace capabilities. + +What: /sys/bus/platform/drivers/qcom_eud/.../port +Date: January 2026 +Contact: Elson Serrao +Description: + Selects which USB port the Embedded USB Debugger (EUD) + is mapped to on platforms providing multiple High-Speed + USB ports. + + Valid values: + 0 - Primary USB port + 1 - Secondary USB port + + The attribute is writable only while EUD is disabled. + Reading the attribute returns the currently selected + USB port number. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 926419ca560fc..1a136f8f1ae52 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -23,8 +23,11 @@ #define EUD_REG_VBUS_INT_CLR 0x0080 #define EUD_REG_CSR_EUD_EN 0x1014 #define EUD_REG_SW_ATTACH_DET 0x1018 +#define EUD_REG_PORT_SEL 0x1028 #define EUD_REG_EUD_EN2 0x0000 +#define EUD_MAX_PORTS 2 + #define EUD_ENABLE BIT(0) #define EUD_INT_PET_EUD BIT(0) #define EUD_INT_VBUS BIT(2) @@ -40,6 +43,7 @@ struct eud_chip { int irq; bool enabled; bool usb_attached; + u8 port_idx; }; static int enable_eud(struct eud_chip *priv) @@ -104,8 +108,47 @@ static ssize_t enable_store(struct device *dev, static DEVICE_ATTR_RW(enable); +static ssize_t port_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct eud_chip *chip = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u\n", chip->port_idx); +} + +static ssize_t port_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct eud_chip *chip = dev_get_drvdata(dev); + u8 port; + int ret; + + ret = kstrtou8(buf, 0, &port); + if (ret) + return ret; + + /* Only port 0 and port 1 are valid */ + if (port >= EUD_MAX_PORTS) + return -EINVAL; + + /* Port selection must be done before enabling EUD */ + if (chip->enabled) { + dev_err(chip->dev, "Cannot change port while EUD is enabled\n"); + return -EBUSY; + } + + writel(port, chip->base + EUD_REG_PORT_SEL); + chip->port_idx = port; + + return count; +} + +static DEVICE_ATTR_RW(port); + static struct attribute *eud_attrs[] = { &dev_attr_enable.attr, + &dev_attr_port.attr, NULL, }; ATTRIBUTE_GROUPS(eud); From 13063fb7271992be1725638f3bb66f384619e328 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:24 -0800 Subject: [PATCH 0368/1330] FROMLIST: usb: misc: qcom_eud: add per-path High-Speed PHY control EUD hardware can support multiple High-Speed USB paths, each routed through its own PHY. The active path is selected in hardware via the EUD_PORT_SEL register. As a High-Speed hub, EUD requires access to the High-Speed PHY associated with the active UTMI path. To support this multi-path capability, the driver must manage PHY resources on a per-path basis, ensuring that the PHY for the currently selected path is properly initialized and powered. This patch restructures the driver to implement per-path PHY management. The driver now powers the appropriate PHY based on the selected and enabled UTMI path, ensuring correct operation when EUD is enabled. Supporting this requires describing the available UTMI paths and their corresponding PHYs in Device Tree. This updates DT requirements and is not backward compatible with older DTs that lacked this description. Historically, EUD appeared to work on single-path systems because the USB controller kept the PHY initialized. However, EUD is designed to operate independently of the USB controller and therefore requires explicit PHY control. Signed-off-by: Elson Serrao Link: https://lore.kernel.org/linux-usb/20260126233830.2193816-4-elson.serrao@oss.qualcomm.com/ --- drivers/usb/misc/qcom_eud.c | 130 +++++++++++++++++++++++++++++++++++- 1 file changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 1a136f8f1ae52..5cebb64f4a672 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -34,26 +35,96 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +struct eud_path { + struct eud_chip *chip; + struct phy *phy; + u8 num; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; void __iomem *base; + struct eud_path *paths[EUD_MAX_PORTS]; phys_addr_t mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + bool phy_enabled; u8 port_idx; }; +static int eud_phy_enable(struct eud_chip *chip) +{ + struct eud_path *path; + struct phy *phy; + int ret; + + if (chip->phy_enabled) + return 0; + + path = chip->paths[chip->port_idx]; + if (!path || !path->phy) { + dev_err(chip->dev, "No PHY configured for port %u\n", chip->port_idx); + return -ENODEV; + } + + phy = path->phy; + + ret = phy_init(phy); + if (ret) { + dev_err(chip->dev, "Failed to initialize USB2 PHY for port %u: %d\n", + chip->port_idx, ret); + return ret; + } + + ret = phy_power_on(phy); + if (ret) { + dev_err(chip->dev, "Failed to power on USB2 PHY for port %u: %d\n", + chip->port_idx, ret); + phy_exit(phy); + return ret; + } + + chip->phy_enabled = true; + + return 0; +} + +static void eud_phy_disable(struct eud_chip *chip) +{ + struct eud_path *path; + struct phy *phy; + + if (!chip->phy_enabled) + return; + + path = chip->paths[chip->port_idx]; + if (!path || !path->phy) + return; + + phy = path->phy; + + phy_power_off(phy); + phy_exit(phy); + chip->phy_enabled = false; +} + static int enable_eud(struct eud_chip *priv) { int ret; - ret = qcom_scm_io_writel(priv->mode_mgr + EUD_REG_EUD_EN2, 1); + ret = eud_phy_enable(priv); if (ret) return ret; + ret = qcom_scm_io_writel(priv->mode_mgr + EUD_REG_EUD_EN2, 1); + if (ret) { + eud_phy_disable(priv); + return ret; + } + writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); @@ -70,6 +141,8 @@ static int disable_eud(struct eud_chip *priv) return ret; writel(0, priv->base + EUD_REG_CSR_EUD_EN); + eud_phy_disable(priv); + return 0; } @@ -132,6 +205,12 @@ static ssize_t port_store(struct device *dev, if (port >= EUD_MAX_PORTS) return -EINVAL; + /* Check if the corresponding path is available */ + if (!chip->paths[port]) { + dev_err(chip->dev, "EUD not supported on selected port\n"); + return -EOPNOTSUPP; + } + /* Port selection must be done before enabling EUD */ if (chip->enabled) { dev_err(chip->dev, "Cannot change port while EUD is enabled\n"); @@ -231,8 +310,45 @@ static void eud_role_switch_release(void *data) usb_role_switch_put(chip->role_sw); } +static int eud_init_path(struct eud_chip *chip, struct device_node *np) +{ + struct eud_path *path; + u32 path_num; + int ret; + + ret = of_property_read_u32(np, "reg", &path_num); + if (ret) { + dev_err(chip->dev, "Missing 'reg' property in path node\n"); + return ret; + } + + if (path_num >= EUD_MAX_PORTS) { + dev_err(chip->dev, "Invalid path number: %u (max %d)\n", + path_num, EUD_MAX_PORTS - 1); + return -EINVAL; + } + + path = devm_kzalloc(chip->dev, sizeof(*path), GFP_KERNEL); + if (!path) + return -ENOMEM; + + path->chip = chip; + path->num = path_num; + + path->phy = devm_of_phy_get(chip->dev, np, NULL); + if (IS_ERR(path->phy)) + return dev_err_probe(chip->dev, PTR_ERR(path->phy), + "Failed to get PHY for path %d\n", path_num); + + chip->paths[path_num] = path; + + return 0; +} + static int eud_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; + struct device_node *child; struct eud_chip *chip; struct resource *res; int ret; @@ -252,6 +368,18 @@ static int eud_probe(struct platform_device *pdev) if (ret) return ret; + for_each_child_of_node(np, child) { + ret = eud_init_path(chip, child); + if (ret) { + of_node_put(child); + return ret; + } + } + + /* Primary path is mandatory. Secondary is optional */ + if (!chip->paths[0]) + return -ENODEV; + chip->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(chip->base)) return PTR_ERR(chip->base); From 75a1221db6b518bf2c3b0358ce76a737f145dd16 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:25 -0800 Subject: [PATCH 0369/1330] FROMLIST: usb: misc: qcom_eud: add per-path role switch support The EUD hardware can support multiple High-Speed USB paths, each connected to different USB controllers. The current implementation uses a single chip-level role switch, which cannot properly handle multi-path configurations where each path needs independent role management. Since EUD is physically present between the USB connector and the controller, it should also relay the role change requests from the connector. Restructure the driver to support per-path role switches and remove the chip-level role switch. Additionally, as EUD need not modify the USB role upon enabling, remove the unnecessary role switch call from enable_eud(). Signed-off-by: Elson Serrao Link: https://lore.kernel.org/linux-usb/20260126233830.2193816-5-elson.serrao@oss.qualcomm.com/ --- drivers/usb/misc/qcom_eud.c | 80 ++++++++++++++++++++++++++++++++----- 1 file changed, 70 insertions(+), 10 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 5cebb64f4a672..a58022f50484f 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -38,12 +38,15 @@ struct eud_path { struct eud_chip *chip; struct phy *phy; + struct usb_role_switch *controller_sw; + struct usb_role_switch *eud_sw; + enum usb_role curr_role; + char name[16]; u8 num; }; struct eud_chip { struct device *dev; - struct usb_role_switch *role_sw; void __iomem *base; struct eud_path *paths[EUD_MAX_PORTS]; phys_addr_t mode_mgr; @@ -129,7 +132,7 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); + return 0; } static int disable_eud(struct eud_chip *priv) @@ -287,15 +290,21 @@ static irqreturn_t handle_eud_irq(int irq, void *data) static irqreturn_t handle_eud_irq_thread(int irq, void *data) { struct eud_chip *chip = data; + struct eud_path *path; int ret; + path = chip->paths[chip->port_idx]; + if (!path || !path->controller_sw) + goto clear_irq; + if (chip->usb_attached) - ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_DEVICE); + ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_DEVICE); else - ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_HOST); + ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_HOST); if (ret) dev_err(chip->dev, "failed to set role switch\n"); +clear_irq: /* set and clear vbus_int_clr[0] to clear interrupt */ writel(BIT(0), chip->base + EUD_REG_VBUS_INT_CLR); writel(0, chip->base + EUD_REG_VBUS_INT_CLR); @@ -303,15 +312,45 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) return IRQ_HANDLED; } +static int eud_role_switch_set(struct usb_role_switch *sw, enum usb_role role) +{ + struct eud_path *path = usb_role_switch_get_drvdata(sw); + int ret; + + /* Forward the role request to the USB controller */ + ret = usb_role_switch_set_role(path->controller_sw, role); + if (ret) { + dev_err(path->chip->dev, "Failed to set role %s for port %u: %d\n", + usb_role_string(role), path->num, ret); + return ret; + } + + path->curr_role = role; + + return 0; +} + static void eud_role_switch_release(void *data) { struct eud_chip *chip = data; + int i; - usb_role_switch_put(chip->role_sw); + for (i = 0; i < EUD_MAX_PORTS; i++) { + struct eud_path *path = chip->paths[i]; + + if (!path) + continue; + + if (path->eud_sw) + usb_role_switch_unregister(path->eud_sw); + if (path->controller_sw) + usb_role_switch_put(path->controller_sw); + } } static int eud_init_path(struct eud_chip *chip, struct device_node *np) { + struct usb_role_switch_desc role_sw_desc = {}; struct eud_path *path; u32 path_num; int ret; @@ -342,6 +381,32 @@ static int eud_init_path(struct eud_chip *chip, struct device_node *np) chip->paths[path_num] = path; + path->curr_role = USB_ROLE_NONE; + + if (!of_property_read_bool(np, "usb-role-switch")) + return 0; + + /* Fetch the USB controller's role switch */ + path->controller_sw = fwnode_usb_role_switch_get(of_fwnode_handle(np)); + if (IS_ERR(path->controller_sw)) + return dev_err_probe(chip->dev, PTR_ERR(path->controller_sw), + "Failed to get controller role switch for path %d\n", + path_num); + + /* Create a role switch */ + role_sw_desc.fwnode = of_fwnode_handle(np); + role_sw_desc.set = eud_role_switch_set; + role_sw_desc.driver_data = path; + snprintf(path->name, sizeof(path->name), "eud-path%u", path_num); + role_sw_desc.name = path->name; + + path->eud_sw = usb_role_switch_register(chip->dev, &role_sw_desc); + if (IS_ERR(path->eud_sw)) { + dev_err(chip->dev, "Failed to register EUD role switch for path %d: %ld\n", + path_num, PTR_ERR(path->eud_sw)); + return PTR_ERR(path->eud_sw); + } + return 0; } @@ -359,11 +424,6 @@ static int eud_probe(struct platform_device *pdev) chip->dev = &pdev->dev; - chip->role_sw = usb_role_switch_get(&pdev->dev); - if (IS_ERR(chip->role_sw)) - return dev_err_probe(chip->dev, PTR_ERR(chip->role_sw), - "failed to get role switch\n"); - ret = devm_add_action_or_reset(chip->dev, eud_role_switch_release, chip); if (ret) return ret; From 7534d6cafffcdc0024b079d7f9dff57899f59011 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:26 -0800 Subject: [PATCH 0370/1330] FROMLIST: usb: misc: qcom_eud: improve enable_store API Currently enable_store() allows operations irrespective of the EUD state, which can result in redundant operations. Avoid this by adding duplicate state checks to skip requests when EUD is already in the desired state. Additionally, improve error handling with explicit logging to provide better feedback. Signed-off-by: Elson Serrao Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/linux-usb/20260126233830.2193816-6-elson.serrao@oss.qualcomm.com/ --- drivers/usb/misc/qcom_eud.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index a58022f50484f..0ea6491f963ce 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -168,18 +168,27 @@ static ssize_t enable_store(struct device *dev, if (kstrtobool(buf, &enable)) return -EINVAL; + /* Skip operation if already in desired state */ + if (chip->enabled == enable) + return count; + if (enable) { ret = enable_eud(chip); - if (!ret) - chip->enabled = enable; - else - disable_eud(chip); - + if (ret) { + dev_err(chip->dev, "failed to enable eud\n"); + return ret; + } } else { ret = disable_eud(chip); + if (ret) { + dev_err(chip->dev, "failed to disable eud\n"); + return ret; + } } - return ret < 0 ? ret : count; + chip->enabled = enable; + + return count; } static DEVICE_ATTR_RW(enable); From 2b868c17f72c24e53925041d216ee4c59095eec8 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:27 -0800 Subject: [PATCH 0371/1330] FROMLIST: usb: misc: qcom_eud: add host mode coordination EUD functions by presenting itself as a USB device to the host PC for debugging, making it incompatible in USB host mode configurations. Enabling EUD, when in host mode can also cause the USB controller to misbehave as the EUD hub can only have one upstream facing port. Handle below two scenarios to prevent these conflicts: 1. Prevent user from enabling EUD via sysfs when the USB port is in host mode. 2. Automatically disable EUD when USB port switches to host mode and re-enable it when exiting host mode. This ensures consistent state management without creating conflicts between the EUD debug hub and the USB controller. Signed-off-by: Elson Serrao Link: https://lore.kernel.org/linux-usb/20260126233830.2193816-7-elson.serrao@oss.qualcomm.com/ --- drivers/usb/misc/qcom_eud.c | 79 ++++++++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 0ea6491f963ce..3f1cc7ea2a6ae 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -49,12 +49,15 @@ struct eud_chip { struct device *dev; void __iomem *base; struct eud_path *paths[EUD_MAX_PORTS]; + /* serializes EUD control operations */ + struct mutex state_lock; phys_addr_t mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; bool phy_enabled; + bool eud_disabled_for_host; u8 port_idx; }; @@ -162,32 +165,66 @@ static ssize_t enable_store(struct device *dev, const char *buf, size_t count) { struct eud_chip *chip = dev_get_drvdata(dev); + struct eud_path *path; bool enable; int ret; if (kstrtobool(buf, &enable)) return -EINVAL; + mutex_lock(&chip->state_lock); + /* Skip operation if already in desired state */ - if (chip->enabled == enable) + if (chip->enabled == enable) { + mutex_unlock(&chip->state_lock); return count; + } + + /* + * Handle double-disable scenario: User is disabling EUD that was already + * disabled due to host mode. Since the hardware is already disabled, we + * only need to clear the host-disabled flag to prevent unwanted re-enabling + * when exiting host mode. This respects the user's explicit disable request. + */ + if (!enable && chip->eud_disabled_for_host) { + chip->eud_disabled_for_host = false; + chip->enabled = false; + mutex_unlock(&chip->state_lock); + return count; + } if (enable) { + /* + * EUD functions by presenting itself as a USB device to the host PC for + * debugging, making it incompatible in USB host mode configuration. + * Prevent enabling EUD in this configuration to avoid hardware conflicts. + */ + path = chip->paths[chip->port_idx]; + if (path && path->curr_role == USB_ROLE_HOST) { + dev_err(chip->dev, "EUD not usable in host mode configuration\n"); + mutex_unlock(&chip->state_lock); + return -EBUSY; + } + ret = enable_eud(chip); if (ret) { dev_err(chip->dev, "failed to enable eud\n"); + mutex_unlock(&chip->state_lock); return ret; } } else { ret = disable_eud(chip); if (ret) { dev_err(chip->dev, "failed to disable eud\n"); + mutex_unlock(&chip->state_lock); return ret; } } chip->enabled = enable; + mutex_unlock(&chip->state_lock); + return count; } @@ -324,18 +361,56 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) static int eud_role_switch_set(struct usb_role_switch *sw, enum usb_role role) { struct eud_path *path = usb_role_switch_get_drvdata(sw); + struct eud_chip *chip = path->chip; int ret; + mutex_lock(&chip->state_lock); + + /* + * EUD must be disabled when USB operates in host mode. EUD functions by + * presenting itself as a USB device to the host PC for debugging, making + * it incompatible in host mode configuration. + * + * chip->enabled preserves user's sysfs configuration and is not modified + * during host mode transitions to maintain user intent. + */ + + /* Only act if EUD is enabled and this is the active path */ + if (chip->enabled && path->num == chip->port_idx) { + if (role == USB_ROLE_HOST && !chip->eud_disabled_for_host) { + ret = disable_eud(chip); + if (ret) { + dev_err(chip->dev, "Failed to disable EUD for host mode: %d\n", + ret); + mutex_unlock(&chip->state_lock); + return ret; + } + chip->eud_disabled_for_host = true; + } else if (role != USB_ROLE_HOST && chip->eud_disabled_for_host) { + ret = enable_eud(chip); + if (ret) { + dev_err(chip->dev, "Failed to re-enable EUD after host mode: %d\n", + ret); + mutex_unlock(&chip->state_lock); + return ret; + } + chip->eud_disabled_for_host = false; + } + } + /* Forward the role request to the USB controller */ ret = usb_role_switch_set_role(path->controller_sw, role); if (ret) { dev_err(path->chip->dev, "Failed to set role %s for port %u: %d\n", usb_role_string(role), path->num, ret); + mutex_unlock(&chip->state_lock); return ret; } path->curr_role = role; + mutex_unlock(&chip->state_lock); + return 0; } @@ -433,6 +508,8 @@ static int eud_probe(struct platform_device *pdev) chip->dev = &pdev->dev; + mutex_init(&chip->state_lock); + ret = devm_add_action_or_reset(chip->dev, eud_role_switch_release, chip); if (ret) return ret; From 4916b0eba664e1408b988c4375daa2840aa9bb83 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:28 -0800 Subject: [PATCH 0372/1330] FROMLIST: usb: misc: qcom_eud: fix virtual attach/detach event handling EUD provides virtual USB attach/detach events to simulate cable plug/unplug while maintaining the physical debug connection. However, the current implementation incorrectly sets the USB role to HOST on virtual detach, which doesn't represent the disconnected state. Fix the virtual detach handling by setting the USB role to NONE instead of HOST, correctly representing the disconnected state. Signed-off-by: Elson Serrao Reviewed-by: Konrad Dybcio https://lore.kernel.org/linux-usb/20260126233830.2193816-8-elson.serrao@oss.qualcomm.com/ --- drivers/usb/misc/qcom_eud.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 3f1cc7ea2a6ae..60f566427abe2 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -343,10 +343,26 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) if (!path || !path->controller_sw) goto clear_irq; + /* + * EUD virtual attach/detach event handling for low power debugging: + * + * When EUD is enabled in debug mode, the device remains physically + * connected to the PC throughout the debug session, keeping the USB + * controller active. This prevents testing of low power scenarios that + * require USB disconnection. + * + * EUD solves this by providing virtual USB attach/detach events while + * maintaining the physical connection. These events are triggered from + * the Host PC via the enumerated EUD control interface and delivered + * to the EUD driver as interrupts. + * + * These notifications are forwarded to the USB controller through role + * switch framework. + */ if (chip->usb_attached) ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_DEVICE); else - ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_HOST); + ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_NONE); if (ret) dev_err(chip->dev, "failed to set role switch\n"); From 598c4a4718f80bfd4125b2beb3541fe7e032fbad Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:29 -0800 Subject: [PATCH 0373/1330] FROMLIST: arm64: dts: qcom: kodiak: Align EUD node with binding The EUD node does not match the current binding and maps USB endpoints to the secondary controller. This SoC supports EUD only on the primary High-Speed USB path. The binding also requires a per-path PHY reference. Model the primary UTMI path as a child node with the required PHY and an empty ports graph. Leave endpoint mapping to board DTS files, and remove the secondary mapping and associated ports so the description conforms to the binding. Signed-off-by: Elson Serrao iLink: https://lore.kernel.org/linux-usb/20260126233830.2193816-9-elson.serrao@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 33 +++++++++++++++++----------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index a67a550302c6f..6181222b641bc 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -4307,12 +4307,6 @@ phy-names = "usb2-phy"; maximum-speed = "high-speed"; usb-role-switch; - - port { - usb2_role_switch: endpoint { - remote-endpoint = <&eud_ep>; - }; - }; }; qspi: spi@88dc000 { @@ -4636,16 +4630,29 @@ <0 0x88e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; + eud0: eud-path@0 { + reg = <0>; + phys = <&usb_1_hsphy>; - port@0 { - reg = <0>; - eud_ep: endpoint { - remote-endpoint = <&usb2_role_switch>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + eud_usb0: endpoint { + }; + }; + + port@1 { + reg = <1>; + eud_con0: endpoint { + }; }; }; }; From 0eca1c634d3303d971c4bafdba06dbdc34cfae4e Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Mon, 26 Jan 2026 15:38:30 -0800 Subject: [PATCH 0374/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable EUD debug functionality On this board, EUD resides on the primary High-Speed USB data path between the connector and the DWC3 controller. Update the device tree connections to correctly map the connector and controller endpoints, and describe role-switch capability on the EUD primary path. Signed-off-by: Elson Serrao Link: https://lore.kernel.org/linux-usb/20260126233830.2193816-10-elson.serrao@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index cdc3977daa5c4..a45ac8c7dcc35 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -200,7 +200,7 @@ reg = <0>; pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; + remote-endpoint = <&eud_con0>; }; }; @@ -1673,13 +1673,29 @@ }; &usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; + remote-endpoint = <&eud_usb0>; }; &usb_1_dwc3_ss { remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; +&eud_con0 { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&eud_usb0 { + remote-endpoint = <&usb_1_dwc3_hs>; +}; + +&eud { + status = "okay"; +}; + +&eud0 { + usb-role-switch; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c_0p88>; vdda33-supply = <&vreg_l2b_3p072>; From cb2e2b822942412d1d4b19eaf8afd210a660729b Mon Sep 17 00:00:00 2001 From: Jan Remmet Date: Fri, 23 Jan 2026 15:52:37 +0100 Subject: [PATCH 0375/1330] FROMLIST: usb: typec: hd3ss3220: Enable VBUS based on role state For systems where the ID pin isn't available as gpio use the ATTACHED_STATE register instead to control vbus. >From the datasheet: "This is an additional method to communicate attach other than the ID pin. These bits can be read by the application to determine what was attached." Use this method if id-gpios property is not set, but the connector node has vbus-supply defined. Check regulator state as peripheral and detach can disable vbus. Signed-off-by: Jan Remmet From 459c6cdd4452467d845390e0c8fc79b392c3aec7 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Mon, 16 Feb 2026 01:35:33 +0530 Subject: [PATCH 0376/1330] FROMLIST: usb: typec: hd3ss3220: Add wakeup support from system suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The HD3SS3220's interrupt is disabled during system suspend, so a USB‑C cable connect/attach event cannot wake the system. This prevents resume from low‑power modes when the port controller is expected to act as a wakeup source. Add wakeup support by: - Initialize the device as wakeup‑capable. - Enable the HD3SS3220 IRQ as a wakeup interrupt. - Add suspend/resume callbacks to enable or disable the IRQ for wakeup depending on the device's wakeup configuration. With this, USB‑C cable insertion correctly wakes the system from suspend. Link: https://lore.kernel.org/all/20260215183325.3836178-2-swati.agarwal@oss.qualcomm.com/ Signed-off-by: Swati Agarwal --- drivers/usb/typec/hd3ss3220.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/usb/typec/hd3ss3220.c b/drivers/usb/typec/hd3ss3220.c index 3e39b800e6b5f..b56df9349f89b 100644 --- a/drivers/usb/typec/hd3ss3220.c +++ b/drivers/usb/typec/hd3ss3220.c @@ -501,6 +501,11 @@ static int hd3ss3220_probe(struct i2c_client *client) if (hd3ss3220->poll) schedule_delayed_work(&hd3ss3220->output_poll_work, HZ); + if (client->irq && device_property_read_bool(hd3ss3220->dev, "wakeup-source")) { + device_init_wakeup(&client->dev, true); + enable_irq_wake(client->irq); + } + dev_info(&client->dev, "probed revision=0x%x\n", ret); return 0; @@ -525,6 +530,35 @@ static void hd3ss3220_remove(struct i2c_client *client) usb_role_switch_put(hd3ss3220->role_sw); } +static int __maybe_unused hd3ss3220_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + + if (device_may_wakeup(dev)) + enable_irq_wake(client->irq); + else + disable_irq(client->irq); + + return 0; +} + +static int __maybe_unused hd3ss3220_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + + if (device_may_wakeup(dev)) + disable_irq_wake(client->irq); + else + enable_irq(client->irq); + + return 0; +} + +static const struct dev_pm_ops hd3ss3220_pm_ops = { + .suspend = hd3ss3220_suspend, + .resume = hd3ss3220_resume, +}; + static const struct of_device_id dev_ids[] = { { .compatible = "ti,hd3ss3220"}, {} @@ -535,6 +569,7 @@ static struct i2c_driver hd3ss3220_driver = { .driver = { .name = "hd3ss3220", .of_match_table = dev_ids, + .pm = &hd3ss3220_pm_ops, }, .probe = hd3ss3220_probe, .remove = hd3ss3220_remove, From 9a4d9055a7de14508000699e5afb587a49b71256 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Fri, 20 Feb 2026 16:01:25 +0530 Subject: [PATCH 0377/1330] Revert "FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable EUD debug functionality" This reverts commit e65028c6aae9f531066bdfc487454ed45e0834a9. Issue is observed with this commit e65028c6aae9f531066bdfc487454ed45e0834a9 leading to crash, with following call stack [ 19.706310][ T73] Call trace: [ 19.706312][ T73] usb_role_switch_unregister+0x28/0x70 (P) [ 19.706319][ T73] eud_role_switch_release+0x30/0x78 [qcom_eud] [ 19.884972][ T73] devm_action_release+0x1c/0x30 [ 19.884981][ T73] release_nodes+0x70/0x120 [ 19.884987][ T73] devres_release_all+0x98/0xf0 [ 19.884995][ T73] device_unbind_cleanup+0x20/0x98 [ 19.885000][ T73] really_probe+0x184/0x3f0 [ 19.885005][ T73] __driver_probe_device+0x88/0x190 [ 19.885010][ T73] driver_probe_device+0x44/0x120 [ 19.885015][ T73] __device_attach_driver+0xc4/0x178 [ 19.885020][ T73] bus_for_each_drv+0x90/0xf8 [ 19.885027][ T73] __device_attach+0xa8/0x1d8 [ 19.885032][ T73] device_initial_probe+0x58/0x68 [ 19.885037][ T73] bus_probe_device+0x40/0xb8 [ 19.885041][ T73] deferred_probe_work_func+0xbc/0x128 [ 19.885046][ T73] process_one_work+0x180/0x450 [ 19.885055][ T73] worker_thread+0x26c/0x388 [ 19.885062][ T73] kthread+0x120/0x140 [ 19.885068][ T73] ret_from_fork+0x10/0x20 [ 19.885079][ T73] Code: f9000bf3 aa0003f3 b140041f 54000168 (390c901f) [ 19.885083][ T73] ---[ end trace 0000000000000000 ]--- [ 19.885088][ T73] Kernel panic - not syncing: Oops: Fatal exception [ 19.885091][ T73] SMP: stopping secondary CPUs Revert commit for now. Signed-off-by: Salendarsingh Gaud --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a45ac8c7dcc35..cdc3977daa5c4 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -200,7 +200,7 @@ reg = <0>; pmic_glink_hs_in: endpoint { - remote-endpoint = <&eud_con0>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -1673,29 +1673,13 @@ }; &usb_1_dwc3_hs { - remote-endpoint = <&eud_usb0>; + remote-endpoint = <&pmic_glink_hs_in>; }; &usb_1_dwc3_ss { remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; -&eud_con0 { - remote-endpoint = <&pmic_glink_hs_in>; -}; - -&eud_usb0 { - remote-endpoint = <&usb_1_dwc3_hs>; -}; - -&eud { - status = "okay"; -}; - -&eud0 { - usb-role-switch; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c_0p88>; vdda33-supply = <&vreg_l2b_3p072>; From 295017b4c9fa0d655cf968289abb7157f49a6ce8 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Fri, 20 Feb 2026 16:02:45 +0530 Subject: [PATCH 0378/1330] Revert "FROMLIST: arm64: dts: qcom: kodiak: Align EUD node with binding" This reverts commit 09ed0b6ddc99b87f0fb3141a9c4d55f015329c5c. Issue is observed with this commit 09ed0b6ddc99b87f0fb3141a9c4d55f015329c5c leading to crash, with following call stack [ 19.706310][ T73] Call trace: [ 19.706312][ T73] usb_role_switch_unregister+0x28/0x70 (P) [ 19.706319][ T73] eud_role_switch_release+0x30/0x78 [qcom_eud] [ 19.884972][ T73] devm_action_release+0x1c/0x30 [ 19.884981][ T73] release_nodes+0x70/0x120 [ 19.884987][ T73] devres_release_all+0x98/0xf0 [ 19.884995][ T73] device_unbind_cleanup+0x20/0x98 [ 19.885000][ T73] really_probe+0x184/0x3f0 [ 19.885005][ T73] __driver_probe_device+0x88/0x190 [ 19.885010][ T73] driver_probe_device+0x44/0x120 [ 19.885015][ T73] __device_attach_driver+0xc4/0x178 [ 19.885020][ T73] bus_for_each_drv+0x90/0xf8 [ 19.885027][ T73] __device_attach+0xa8/0x1d8 [ 19.885032][ T73] device_initial_probe+0x58/0x68 [ 19.885037][ T73] bus_probe_device+0x40/0xb8 [ 19.885041][ T73] deferred_probe_work_func+0xbc/0x128 [ 19.885046][ T73] process_one_work+0x180/0x450 [ 19.885055][ T73] worker_thread+0x26c/0x388 [ 19.885062][ T73] kthread+0x120/0x140 [ 19.885068][ T73] ret_from_fork+0x10/0x20 [ 19.885079][ T73] Code: f9000bf3 aa0003f3 b140041f 54000168 (390c901f) [ 19.885083][ T73] ---[ end trace 0000000000000000 ]--- [ 19.885088][ T73] Kernel panic - not syncing: Oops: Fatal exception [ 19.885091][ T73] SMP: stopping secondary CPUs Revert commit for now. Signed-off-by: Salendarsingh Gaud --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 33 +++++++++++----------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 6181222b641bc..a67a550302c6f 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -4307,6 +4307,12 @@ phy-names = "usb2-phy"; maximum-speed = "high-speed"; usb-role-switch; + + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; + }; + }; }; qspi: spi@88dc000 { @@ -4630,29 +4636,16 @@ <0 0x88e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - eud0: eud-path@0 { - reg = <0>; - phys = <&usb_1_hsphy>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - eud_usb0: endpoint { - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@1 { - reg = <1>; - eud_con0: endpoint { - }; + port@0 { + reg = <0>; + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; }; }; }; From 26108ca6912c10bb5b18983d1d5a59e630b8897a Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 18 Dec 2025 00:09:52 -0800 Subject: [PATCH 0379/1330] FROMLIST: arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block The APSS debug block is built with CoreSight devices like ETM, replicator, funnel and TMC ETF. Add dt nodes for these devices to enable ETM trace. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-12-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Jie Gan Co-developed-by: Yuanfang Zhang Signed-off-by: Yuanfang Zhang --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 926 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/purwa.dtsi | 12 + 2 files changed, 938 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index c3cd5b767cdb5..5517ca306c8a0 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -307,6 +307,210 @@ }; }; + etm-0 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&ncc0_0_rep_in>; + }; + }; + }; + }; + + etm-1 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&ncc0_1_rep_in>; + }; + }; + }; + }; + + etm-2 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&ncc0_2_rep_in>; + }; + }; + }; + }; + + etm-3 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&ncc0_3_rep_in>; + }; + }; + }; + }; + + etm-4 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&ncc1_0_rep_in>; + }; + }; + }; + }; + + etm-5 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&ncc1_1_rep_in>; + }; + }; + }; + }; + + etm-6 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&ncc1_2_rep_in>; + }; + }; + }; + }; + + etm-7 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&ncc1_3_rep_in>; + }; + }; + }; + }; + + etm8: etm-8 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu8>; + qcom,skip-power-up; + + out-ports { + port { + etm8_out: endpoint { + remote-endpoint = <&ncc2_0_rep_in>; + }; + }; + }; + }; + + etm9: etm-9 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu9>; + qcom,skip-power-up; + + out-ports { + port { + etm9_out: endpoint { + remote-endpoint = <&ncc2_1_rep_in>; + }; + }; + }; + }; + + etm10: etm-10 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu10>; + qcom,skip-power-up; + + out-ports { + port { + etm10_out: endpoint { + remote-endpoint = <&ncc2_2_rep_in>; + }; + }; + }; + }; + + etm11: etm-11 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu11>; + qcom,skip-power-up; + + out-ports { + port { + etm11_out: endpoint { + remote-endpoint = <&ncc2_3_rep_in>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-x1e80100", "qcom,scm"; @@ -7456,6 +7660,14 @@ }; }; + port@4 { + reg = <4>; + + funnel1_in4: endpoint { + remote-endpoint = <&apss_funnel_out>; + }; + }; + port@5 { reg = <5>; @@ -8746,6 +8958,720 @@ }; }; + apss_funnel: funnel@12080000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x12080000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + apss_funnel_in0: endpoint { + remote-endpoint = <&ncc0_etf_out>; + }; + }; + + port@1 { + reg = <1>; + + apss_funnel_in1: endpoint { + remote-endpoint = <&ncc1_etf_out>; + }; + }; + + port@2 { + reg = <2>; + + apss_funnel_in2: endpoint { + remote-endpoint = <&ncc2_etf_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = <&funnel1_in4>; + }; + }; + }; + }; + + funnel@13401000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x13401000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + ncc0_2_funnel_in2: endpoint { + remote-endpoint = <&ncc0_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc0_2_funnel_out: endpoint { + remote-endpoint = <&ncc0_etf_in>; + }; + }; + }; + }; + + tmc@13409000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x0 0x13409000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_etf_in: endpoint { + remote-endpoint = <&ncc0_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc0_etf_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + replicator@13490000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x13490000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_0_rep_in: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + }; + + out-ports { + port { + ncc0_0_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in0>; + }; + }; + }; + }; + + replicator@134a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x134a0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_1_rep_in: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; + + out-ports { + port { + ncc0_1_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in1>; + }; + }; + }; + }; + + replicator@134b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x134b0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_2_rep_in: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + }; + + out-ports { + port { + ncc0_2_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in2>; + }; + }; + }; + }; + + replicator@134c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x134c0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_3_rep_in: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + ncc0_3_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in3>; + }; + }; + }; + }; + + funnel@134d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x134d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ncc0_1_funnel_in0: endpoint { + remote-endpoint = <&ncc0_0_rep_out>; + }; + }; + + port@1 { + reg = <1>; + + ncc0_1_funnel_in1: endpoint { + remote-endpoint = <&ncc0_1_rep_out>; + }; + }; + + port@2 { + reg = <2>; + + ncc0_1_funnel_in2: endpoint { + remote-endpoint = <&ncc0_2_rep_out>; + }; + }; + + port@3 { + reg = <3>; + + ncc0_1_funnel_in3: endpoint { + remote-endpoint = <&ncc0_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc0_1_funnel_out: endpoint { + remote-endpoint = <&ncc0_2_funnel_in2>; + }; + }; + }; + }; + + funnel@13901000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x13901000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + ncc1_2_funnel_in2: endpoint { + remote-endpoint = <&ncc1_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc1_2_funnel_out: endpoint { + remote-endpoint = <&ncc1_etf_in>; + }; + }; + }; + }; + + tmc@13909000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x0 0x13909000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_etf_in: endpoint { + remote-endpoint = <&ncc1_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc1_etf_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + replicator@13990000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x13990000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_0_rep_in: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + }; + + out-ports { + port { + ncc1_0_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in0>; + }; + }; + }; + }; + + replicator@139a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x139a0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_1_rep_in: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + }; + + out-ports { + port { + ncc1_1_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in1>; + }; + }; + }; + }; + + replicator@139b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x139b0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_2_rep_in: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + }; + + out-ports { + port { + ncc1_2_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in2>; + }; + }; + }; + }; + + replicator@139c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x139c0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_3_rep_in: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + + out-ports { + port { + ncc1_3_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in3>; + }; + }; + }; + }; + + funnel@139d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x139d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ncc1_1_funnel_in0: endpoint { + remote-endpoint = <&ncc1_0_rep_out>; + }; + }; + + port@1 { + reg = <1>; + + ncc1_1_funnel_in1: endpoint { + remote-endpoint = <&ncc1_1_rep_out>; + }; + }; + + port@2 { + reg = <2>; + + ncc1_1_funnel_in2: endpoint { + remote-endpoint = <&ncc1_2_rep_out>; + }; + }; + + port@3 { + reg = <3>; + + ncc1_1_funnel_in3: endpoint { + remote-endpoint = <&ncc1_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc1_1_funnel_out: endpoint { + remote-endpoint = <&ncc1_2_funnel_in2>; + }; + }; + }; + }; + + cluster2_funnel_l2: funnel@13e01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x13e01000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + ncc2_2_funnel_in2: endpoint { + remote-endpoint = <&ncc2_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc2_2_funnel_out: endpoint { + remote-endpoint = <&ncc2_etf_in>; + }; + }; + }; + }; + + cluster2_etf: tmc@13e09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x0 0x13e09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_etf_in: endpoint { + remote-endpoint = <&ncc2_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc2_etf_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + cluster2_rep_2_0: replicator@13e90000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x13e90000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_0_rep_in: endpoint { + remote-endpoint = <&etm8_out>; + }; + }; + }; + + out-ports { + port { + ncc2_0_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in0>; + }; + }; + }; + }; + + cluster2_rep_2_1: replicator@13ea0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x13ea0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_1_rep_in: endpoint { + remote-endpoint = <&etm9_out>; + }; + }; + }; + + out-ports { + port { + ncc2_1_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in1>; + }; + }; + }; + }; + + cluster2_rep_2_2: replicator@13eb0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x13eb0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_2_rep_in: endpoint { + remote-endpoint = <&etm10_out>; + }; + }; + }; + + out-ports { + port { + ncc2_2_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in2>; + }; + }; + }; + }; + + cluster2_rep_2_3: replicator@13ec0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x13ec0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_3_rep_in: endpoint { + remote-endpoint = <&etm11_out>; + }; + }; + }; + + out-ports { + port { + ncc2_3_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in3>; + }; + }; + }; + }; + + cluster2_funnel_l1: funnel@13ed0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x13ed0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ncc2_1_funnel_in0: endpoint { + remote-endpoint = <&ncc2_0_rep_out>; + }; + }; + + port@1 { + reg = <1>; + + ncc2_1_funnel_in1: endpoint { + remote-endpoint = <&ncc2_1_rep_out>; + }; + }; + + port@2 { + reg = <2>; + + ncc2_1_funnel_in2: endpoint { + remote-endpoint = <&ncc2_2_rep_out>; + }; + }; + + port@3 { + reg = <3>; + + ncc2_1_funnel_in3: endpoint { + remote-endpoint = <&ncc2_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc2_1_funnel_out: endpoint { + remote-endpoint = <&ncc2_2_funnel_in2>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 2cecd2dd0de8c..38f2df9e42b60 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -21,6 +21,18 @@ /delete-node/ &gpu_speed_bin; /delete-node/ &pcie3_phy; /delete-node/ &thermal_zones; +/delete-node/ &etm8; +/delete-node/ &etm9; +/delete-node/ &etm10; +/delete-node/ &etm11; +/delete-node/ &cluster2_funnel_l1; +/delete-node/ &cluster2_funnel_l2; +/delete-node/ &cluster2_etf; +/delete-node/ &cluster2_rep_2_0; +/delete-node/ &cluster2_rep_2_1; +/delete-node/ &cluster2_rep_2_2; +/delete-node/ &cluster2_rep_2_3; +/delete-node/ &apss_funnel_in2; &gcc { compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; From 3f01b64d6d13ce321d9d4be649d320d9deb121fd Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 4 Feb 2026 10:22:02 +0800 Subject: [PATCH 0380/1330] FROMLIST: arm64: dts: qcom: hamoa: enable ETR and CTCU devices Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device. The CTCU serves as the control unit for the ETR device, managing its behavior to determine how trace data is collected. Link: https://lore.kernel.org/all/20260204-enable-ctcu-and-etr-v3-2-0bb95c590ae1@oss.qualcomm.com/ Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 +++++++++++++++++++++++++++- 1 file changed, 159 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 5517ca306c8a0..2dddb6bdb1951 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -7509,6 +7509,35 @@ }; }; + ctcu@10001000 { + compatible = "qcom,x1e80100-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x10001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm@10002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x10002000 0x0 0x1000>, @@ -7731,6 +7760,122 @@ }; }; + replicator@10046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc_etr: tmc@10048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04e0 0x0>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@1004e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x1004e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x1004f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x0500 0x0>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + tpdm@10800000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x10800000 0x0 0x1000>; @@ -8044,7 +8189,20 @@ }; out-ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + + port@1 { + reg = <1>; + swao_rep_out1: endpoint { remote-endpoint = <&eud_in>; }; From 9d3363a8b486cdb38452798977f5d71c6cd74669 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Mon, 2 Feb 2026 15:35:45 +0800 Subject: [PATCH 0381/1330] FROMLIST: dt-bindings: arm: qcom: Document PURWA-IOT-EVK board Document the device tree bindings for the PURWA-IOT-EVK board, which uses the Qualcomm X1P42100 SoC. Link: https://lore.kernel.org/all/20260202073555.1345260-1-yijie.yang@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yijie Yang --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 5c26f2807b78e..44c0b082737df 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1147,6 +1147,12 @@ properties: - const: microsoft,denali - const: qcom,x1e80100 + - items: + - enum: + - qcom,purwa-iot-evk + - const: qcom,purwa-iot-som + - const: qcom,x1p42100 + - items: - enum: - asus,zenbook-a14-ux3407qa-lcd From 0051a31776b9058f486a5a682333634294fa3afe Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Mon, 2 Feb 2026 15:35:46 +0800 Subject: [PATCH 0382/1330] FROMLIST: firmware: qcom: scm: Allow QSEECOM on PURWA-IOT-EVK Add the Purwa-IoT-EVK board to the list to enable access to EFI variables. Guarantee that subsystems relying on SCM services can access secure-world features. This change improves reliability and prevents missing functionality or boot-time issues by making service availability explicit. Link: https://lore.kernel.org/all/20260202073555.1345260-2-yijie.yang@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Signed-off-by: Yijie Yang --- drivers/firmware/qcom/qcom_scm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index bebebe8cd9812..25aa63f3235ee 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2312,6 +2312,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "microsoft,romulus13", }, { .compatible = "microsoft,romulus15", }, { .compatible = "qcom,hamoa-iot-evk" }, + { .compatible = "qcom,purwa-iot-evk" }, { .compatible = "qcom,sc8180x-primus" }, { .compatible = "qcom,x1e001de-devkit" }, { .compatible = "qcom,x1e80100-crd" }, From 6c85675b1c7062013130acd9c7b48f0bb16fec9d Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Mon, 2 Feb 2026 15:35:47 +0800 Subject: [PATCH 0383/1330] FROMLIST: arm64: dts: qcom: Add PURWA-IOT-SOM platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PURWA-IOT-SOM is a compact computing module that integrates a System on Chip (SoC) — specifically the x1p42100 — along with essential components optimized for IoT applications. It is designed to be mounted on carrier boards, enabling the development of complete embedded systems. Purwa uses a slightly different Iris HW revision (8.1.2 on Hamoa, 8.1.11 on Purwa). Support will be added later. Make the following peripherals on the SOM enabled: - Regulators on the SOM - Reserved memory regions - PCIe3, PCIe4, PCIe5, PCIe6a - USB0 through USB6 and their PHYs - ADSP, CDSP - Graphic Link: https://lore.kernel.org/all/20260202073555.1345260-3-yijie.yang@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 685 ++++++++++++++++++++ 1 file changed, 685 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi new file mode 100644 index 0000000000000..fb90beb1096f6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -0,0 +1,685 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" +#include +#include + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; +}; + +&apps_rsc { + /* PMC8380C_B */ + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_C */ + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_D */ + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_E */ + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_F */ + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_I */ + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_J */ + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/gen71500_zap.mbn"; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie5 { + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + + }; + }; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; From 152735bacbf3181db447952a1a6a0692c037dde8 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Mon, 2 Feb 2026 15:35:48 +0800 Subject: [PATCH 0384/1330] FROMLIST: arm64: dts: qcom: Add base PURWA-IOT-EVK board The PURWA-IOT-EVK is an evaluation platform for IoT products, composed of the Purwa IoT SoM and a carrier board. Together, they form a complete embedded system capable of booting to UART. PURWA-IOT-EVK uses the PS8833 as a retimer for USB0, unlike HAMOA-IOT-EVK. Meanwhile, USB0 bypasses the SBU selector FSUSB42. Make the following peripherals on the carrier board enabled: - UART - On-board regulators - USB Type-C mux - Pinctrl - Embedded USB (EUSB) repeaters - NVMe - pmic-glink - USB DisplayPorts - Bluetooth - WLAN - Audio - PCIe ports for PCIe3 through PCIe6a - TPM Link: https://lore.kernel.org/all/20260202073555.1345260-4-yijie.yang@oss.qualcomm.com/ Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 1549 ++++++++++++++++++++ 2 files changed, 1550 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/purwa-iot-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index aaae2764012ec..2d937df6b29a4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -146,6 +146,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb +dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts new file mode 100644 index 0000000000000..fe539b1f45677 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -0,0 +1,1549 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include "purwa-iot-som.dtsi" +#include + +/ { + model = "Qualcomm Technologies, Inc. Purwa IoT EVK"; + compatible = "qcom,purwa-iot-evk", "qcom,purwa-iot-som", "qcom,x1p42100"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector3 { + compatible = "usb-a-connector"; + label = "USB-3-Type-A"; + power-role = "source"; + + vbus-supply = <®ulator_usb3_vbus>; + + port { + connector_3_in: endpoint { + }; + }; + }; + + connector6 { + compatible = "usb-a-connector"; + label = "USB-6-Type-A"; + power-role = "source"; + + vbus-supply = <®ulator_usb6_vbus>; + + port { + connector_4_in: endpoint { + }; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss2_con_sbu_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_bl_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_pcie_12v: regulator-pcie-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pcie_x8_12v>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_main_3p3_en>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_aux_3p3_en>; + pinctrl-names = "default"; + }; + + /* Left unused as the retimer is not used on this board. */ + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + regulator_usb3_vbus: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB3_VBUS"; + gpio = <&pm8550ve_9_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb3_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + + regulator_usb6_vbus: regulator-usb6-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB6_VBUS"; + gpio = <&pm8550ve_9_gpios 5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb6_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the EVK mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "SDX_VPH_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-EVK"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, + <&left_tweeter>, + <&swr0 0>, + <&lpass_wsamacro 0>, + <&right_woofer>, + <&right_tweeter>, + <&swr3 0>, + <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK5>; + + vdd-supply = <&vreg_rtmr2_1p15>; + vdd33-supply = <&vreg_rtmr2_3p3>; + vdd33-cap-supply = <&vreg_rtmr2_3p3>; + vddar-supply = <&vreg_rtmr2_1p15>; + vddat-supply = <&vreg_rtmr2_1p15>; + vddio-supply = <&vreg_rtmr2_1p8>; + + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr2_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&lpass_tlmm { + spkr_0_sd_n_active: spkr-0-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_3_sd_n_active: spkr-3-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie3_port0 { + vpcie12v-supply = <&vreg_pcie_12v>; + vpcie3v3-supply = <&vreg_pcie_3v3>; + vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; + + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_wwan>; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb3_en: usb3-en-state { + pins = "gpio4"; + function = "normal"; + qcom,drive-strength = ; + output-enable; + power-source = <0>; + }; + + usb6_en: usb6-en-state { + pins = "gpio5"; + function = "normal"; + qcom,drive-strength = ; + output-enable; + power-source = <0>; + }; +}; + +&pm8550_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; + + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + bias-pull-down; + power-source = <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins = "gpio6"; + function = "normal"; + output-enable; + bias-pull-down; + power-source = <0>; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&spi11 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_0_sd_n_active>; + pinctrl-names = "default"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_3_sd_n_active>; + pinctrl-names = "default"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins = "gpio185"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { + pins = "gpio189"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { + pins = "gpio126"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { + pins = "gpio187"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + mode-pins { + pins = "gpio166"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_bt_en: wcn-bt-en-state { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_en: wcn-wlan-en-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_sw_en: wwan-sw-en-state { + pins = "gpio221"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* Switches USB signal routing between the USB connector and the Wi-Fi card. */ + wcn_usb_sw_n: wcn-usb-sw-n-state { + pins = "gpio225"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&uart21 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_hsphy { + phys = <&smb2360_0_eusb2_repeater>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_hsphy { + phys = <&smb2360_1_eusb2_repeater>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_hsphy { + phys = <&smb2360_2_eusb2_repeater>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&retimer_ss2_ss_in>; +}; + +&usb_2_hsphy { + phys = <&eusb5_repeater>; + + pinctrl-0 = <&wcn_usb_sw_n>; + pinctrl-names = "default"; +}; + +&usb_mp_hsphy0 { + phys = <&eusb3_repeater>; +}; + +&usb_mp_hsphy1 { + phys = <&eusb6_repeater>; +}; From cca366caa1ac810789960effa1deeaf16c77da5c Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Wed, 11 Feb 2026 18:59:25 +0530 Subject: [PATCH 0385/1330] FROMLIST: arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC Add UFS host controller and PHY nodes for x1e80100 SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Taniya Das Reviewed-by: Manivannan Sadhasivam Signed-off-by: Pradeep P V K Link: https://lore.kernel.org/all/20260211132926.3716716-1-pradeep.pragallapati@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 122 +++++++++++++++++++++++++++- 1 file changed, 119 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 2dddb6bdb1951..1b96aa24ef88d 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -1041,9 +1041,9 @@ <0>, <0>, <0>, - <0>, - <0>, - <0>; + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; @@ -4075,6 +4075,122 @@ status = "disabled"; }; + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,x1e80100-qmp-ufs-phy", + "qcom,sm8550-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_PHY_CLKREF_EN>; + + clock-names = "ref", + "ref_aux", + "qref"; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,x1e80100-ufshc", + "qcom,sm8550-ufshc", + "qcom,ufshc"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 = <&ufs_opp_table>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x1a0 0>; + dma-coherent; + + lanes-per-direction = <2>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; From 6199794e6e0e993308161cf645689623bf356426 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Wed, 11 Feb 2026 18:59:26 +0530 Subject: [PATCH 0386/1330] FROMLIST: arm64: dts: qcom: hamoa-iot-evk: Enable UFS Enable UFS for HAMOA-IOT-EVK board. Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Pradeep P V K Link: https://lore.kernel.org/all/20260211132926.3716716-1-pradeep.pragallapati@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 2390648a248f7..fccf1d1bdc606 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -1461,6 +1461,24 @@ status = "okay"; }; +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + &usb_1_ss0_dwc3_hs { remote-endpoint = <&pmic_glink_ss0_hs_in>; }; From 3c1ad088987ca0b178f55e5a7797f41e5ca80cc0 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Wed, 11 Feb 2026 15:00:45 +0530 Subject: [PATCH 0387/1330] FROMLIST: arm64: dts: qcom: hamoa-iot-evk: Add SDC2 node for hamoa iot evk board Enable SD Card host controller for hamoa iot evk board. Link: https://lore.kernel.org/all/20260211093045.2595126-1-sarthak.garg@oss.qualcomm.com/ Signed-off-by: Sarthak Garg Signed-off-by: Pradeep P V K --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index fccf1d1bdc606..1427e342e9047 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -1144,6 +1144,22 @@ status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &smb2360_0 { status = "okay"; }; @@ -1326,6 +1342,13 @@ bias-disable; }; + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { pins = "gpio188"; function = "gpio"; From f8c49cf0973027d65a4729b16f2eed054b9905d6 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Mon, 9 Feb 2026 17:11:39 +0800 Subject: [PATCH 0388/1330] FROMLIST: arm64: dts: qcom: hamoa-evk: Add DP0/DP1 audio DAI links Add DAI links for DP0 and DP1 playback and set sound-name-prefix for both DisplayPort endpoints in the hamoa-evk DTS. Link: https://lore.kernel.org/all/20260209091139.622756-1-le.qi@oss.qualcomm.com/ Signed-off-by: Le Qi Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 1427e342e9047..e6c7b0ed385de 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -616,6 +616,38 @@ sound-dai = <&q6apm>; }; }; + + dp0-dai-link { + link-name = "DP0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dp1-dai-link { + link-name = "DP1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; usb-1-ss0-sbu-mux { @@ -902,6 +934,7 @@ &mdss_dp0 { status = "okay"; + sound-name-prefix = "Display Port0"; }; &mdss_dp0_out { @@ -910,6 +943,7 @@ &mdss_dp1 { status = "okay"; + sound-name-prefix = "Display Port1"; }; &mdss_dp1_out { From 68a56c2041bd6e8e417d08036b3d4b4126626557 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 28 Jan 2026 00:56:37 +0530 Subject: [PATCH 0389/1330] FROMLIST: arm64: dts: qcom: x1e80100: Add CAMCC block definition Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue Signed-off-by: Jagadeesh Kona Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-6-b23de57df5ba@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 264 +++++++++++----------------- 1 file changed, 98 insertions(+), 166 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 1b96aa24ef88d..80c70c470da7a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5865,7 +5865,7 @@ }; camss: isp@acb7000 { - compatible = "qcom,x1e80100-camss", "simple-mfd"; + compatible = "qcom,x1e80100-camss"; reg = <0 0x0acb7000 0 0x2000>, <0 0x0acb9000 0 0x2000>, @@ -5880,8 +5880,8 @@ <0 0x0acf6000 0 0x1000>, <0 0x0acf7000 0 0x1000>, <0 0x0acf8000 0 0x1000>, - <0 0x0ac62000 0 0xf000>, - <0 0x0ac71000 0 0xf000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>, <0 0x0acc7000 0 0x2000>, <0 0x0accb000 0 0x2000>; @@ -5964,32 +5964,32 @@ "vfe_lite_csid"; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names = "csid0", - "csid1", - "csid2", - "csid_lite0", - "csid_lite1", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", - "vfe0", - "vfe1", - "vfe_lite0", - "vfe_lite1"; + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, @@ -6005,14 +6005,10 @@ "sf_icp_mnoc"; iommus = <&apps_smmu 0x800 0x60>, - <&apps_smmu 0x820 0x60>, - <&apps_smmu 0x840 0x60>, <&apps_smmu 0x860 0x60>, - <&apps_smmu 0x18a0 0x0>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x19a0 0x20>; phys = <&csiphy0 PHY_TYPE_DPHY>, <&csiphy1 PHY_TYPE_DPHY>, <&csiphy2 PHY_TYPE_DPHY>, <&csiphy4 PHY_TYPE_DPHY>; @@ -6068,166 +6064,102 @@ }; }; }; + }; - csiphy0: phy@ace4000 { - compatible = "qcom,x1e80100-csi2-phy"; - reg = <0 0x0ace4000 0 0x2000>; - - clocks = <&camcc CAM_CC_CSIPHY0_CLK>, - <&camcc CAM_CC_CSI0PHYTIMER_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>; - clock-names = "csiphy", - "csiphy_timer", - "camnoc_axi", - "cpas_ahb"; - - operating-points-v2 = <&csiphy_mxc_opp_table>; - - interrupts = ; - - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, - <&rpmhpd RPMHPD_MXC>, - <&rpmhpd RPMHPD_MMCX>; - power-domain-names = "top", - "mx", - "mmcx"; - - #phy-cells = <1>; - - status = "disabled"; - }; - - csiphy1: phy@ace6000 { - compatible = "qcom,x1e80100-csi2-phy"; - reg = <0 0x0ace6000 0 0x2000>; - - clocks = <&camcc CAM_CC_CSIPHY1_CLK>, - <&camcc CAM_CC_CSI1PHYTIMER_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>; - clock-names = "csiphy", - "csiphy_timer", - "camnoc_axi", - "cpas_ahb"; + csiphy0: csiphy@ace4000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace4000 0 0x2000>; - operating-points-v2 = <&csiphy_mxc_opp_table>; + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; - interrupts = ; + operating-points-v2 = <&csiphy_opp_table>; - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, - <&rpmhpd RPMHPD_MXC>, - <&rpmhpd RPMHPD_MMCX>; - power-domain-names = "top", - "mx", - "mmcx"; + interrupts = ; - #phy-cells = <1>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - status = "disabled"; - }; + #phy-cells = <1>; - csiphy2: phy@ace8000 { - compatible = "qcom,x1e80100-csi2-phy"; - reg = <0 0x0ace8000 0 0x2000>; + status = "disabled"; + }; - clocks = <&camcc CAM_CC_CSIPHY2_CLK>, - <&camcc CAM_CC_CSI2PHYTIMER_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>; - clock-names = "csiphy", - "csiphy_timer", - "camnoc_axi", - "cpas_ahb"; + csiphy1: csiphy@ace6000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace6000 0 0x2000>; - operating-points-v2 = <&csiphy_mxc_opp_table>; + clocks = <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; - interrupts = ; + operating-points-v2 = <&csiphy_opp_table>; - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, - <&rpmhpd RPMHPD_MXC>, - <&rpmhpd RPMHPD_MMCX>; - power-domain-names = "top", - "mx", - "mmcx"; + interrupts = ; - #phy-cells = <1>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - status = "disabled"; - }; + #phy-cells = <1>; - csiphy4: phy@acec000 { - compatible = "qcom,x1e80100-csi2-phy"; - reg = <0 0x0acec000 0 0x2000>; + status = "disabled"; + }; - clocks = <&camcc CAM_CC_CSIPHY4_CLK>, - <&camcc CAM_CC_CSI4PHYTIMER_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>; - clock-names = "csiphy", - "csiphy_timer", - "camnoc_axi", - "cpas_ahb"; + csiphy2: csiphy@ace8000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace8000 0 0x2000>; - operating-points-v2 = <&csiphy_mxa_opp_table>; + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; - interrupts = ; + operating-points-v2 = <&csiphy_opp_table>; - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, - <&rpmhpd RPMHPD_MX>, - <&rpmhpd RPMHPD_MMCX>; - power-domain-names = "top", - "mx", - "mmcx"; + interrupts = ; - #phy-cells = <1>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - status = "disabled"; - }; + #phy-cells = <1>; - csiphy_mxc_opp_table: opp-table-mxc { - compatible = "operating-points-v2"; + status = "disabled"; + }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_low_svs_d1>, - <&rpmhpd_opp_low_svs_d1>; - }; + csiphy4: csiphy@acec000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0acec000 0 0x2000>; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - required-opps = <&rpmhpd_opp_low_svs>, - <&rpmhpd_opp_low_svs>; - }; + clocks = <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - required-opps = <&rpmhpd_opp_low_svs>, - <&rpmhpd_opp_low_svs>; - }; - }; + operating-points-v2 = <&csiphy_opp_table>; - csiphy_mxa_opp_table: opp-table-mxa { - compatible = "operating-points-v2"; + interrupts = ; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_low_svs_d1>, - <&rpmhpd_opp_low_svs_d1>; - }; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - required-opps = <&rpmhpd_opp_low_svs>, - <&rpmhpd_opp_low_svs>; - }; + #phy-cells = <1>; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - required-opps = <&rpmhpd_opp_low_svs>, - <&rpmhpd_opp_low_svs>; - }; - }; + status = "disabled"; }; camcc: clock-controller@ade0000 { From dda92550f9936f3a04df733c89ffdf574d0c80f8 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 28 Jan 2026 00:56:38 +0530 Subject: [PATCH 0390/1330] FROMLIST: arm64: dts: qcom: Update compatible for videocc and camcc nodes on purwa Update the compatible for videocc and camcc nodes to match with their respective purwa(X1P42100) specific drivers. Signed-off-by: Jagadeesh Kona Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-7-b23de57df5ba@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/purwa.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 38f2df9e42b60..4f9357787fee7 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -6,6 +6,8 @@ /* X1P42100 is heavily based on hamoa, with some meaningful differences */ #include "hamoa.dtsi" +#include + /delete-node/ &bwmon_cluster0; /delete-node/ &cluster_pd2; /delete-node/ &cpu_map_cluster2; @@ -34,10 +36,18 @@ /delete-node/ &cluster2_rep_2_3; /delete-node/ &apss_funnel_in2; +&camcc { + compatible = "qcom,x1p42100-camcc"; +}; + &gcc { compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; }; +&videocc { + compatible = "qcom,x1p42100-videocc"; +}; + &gmu { compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu"; }; From acf6b77226b471f9fa74dd2549c1e9e55299a2ec Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 10 Feb 2026 12:33:21 +0530 Subject: [PATCH 0391/1330] FROMLIST: arm64: dts: qcom: x1e80100: Add '#cooling-cells' for CPU nodes Enable passive cooling for CPUs in the X1E80100 SoC by adding the '#cooling-cells' property. This will allow the OS to mitigate the CPU power dissipation with the help of SCMI DVFS. Signed-off-by: Manivannan Sadhasivam Tested-by: Gaurav Kohli Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260210070321.17033-1-manivannan.sadhasivam@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 80c70c470da7a..aa43f78c36bd6 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -77,6 +77,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -93,6 +94,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -103,6 +105,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -113,6 +116,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu4: cpu@10000 { @@ -123,6 +127,7 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -139,6 +144,7 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu6: cpu@10200 { @@ -149,6 +155,7 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu7: cpu@10300 { @@ -159,6 +166,7 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu8: cpu@20000 { @@ -169,6 +177,7 @@ next-level-cache = <&l2_2>; power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_2: l2-cache { compatible = "cache"; @@ -185,6 +194,7 @@ next-level-cache = <&l2_2>; power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu10: cpu@20200 { @@ -195,6 +205,7 @@ next-level-cache = <&l2_2>; power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu11: cpu@20300 { @@ -205,6 +216,7 @@ next-level-cache = <&l2_2>; power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu-map { From 8b6ef5682b435825a27fa48288d7e1142a931019 Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Wed, 25 Feb 2026 21:41:13 -0800 Subject: [PATCH 0392/1330] FROMLIST: arm64: dts: qcom: hamoa: Add PSCI SYSTEM_RESET2 types Add support for SYSTEM_RESET2 vendor-specific resets as reboot-modes in the psci node. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Signed-off-by: Xin Liu Link: https://lore.kernel.org/all/20260226054113.4156874-1-xin.liu@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index aa43f78c36bd6..1056c4cc4ac51 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -668,6 +668,11 @@ #power-domain-cells = <0>; /* TODO: system-wide idle states */ }; + + reboot-mode { + mode-bootloader = <0x80010001 0x2>; + mode-edl = <0x80000000 0x1>; + }; }; reserved-memory { From 4db7588f401aa29f8bd309bd735f610af6d6d363 Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Mon, 26 Jan 2026 22:24:25 -0800 Subject: [PATCH 0393/1330] FROMLIST: arm64: dts: qcom: hamoa: Add EL2 overlay for hamoa-evk Add support for building an EL2 combined DTB for the hamoa-evk in the Qualcomm DTS Makefile. The new hamoa-iot-evk-el2.dtb is generated by combining the base hamoa-iot-evk.dtb with the x1-el2.dtbo overlay, enabling EL2-specific configurations required by the platform. Reviewed-by: Konrad Dybcio Signed-off-by: Xin Liu Link: https://lore.kernel.org/all/20260127062425.1084673-1-xin.liu@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2d937df6b29a4..f6ea863b5b452 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -15,6 +15,10 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb + +hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb From 38418ed467ea7bde469ba1dce33875475131dba9 Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Mon, 2 Feb 2026 22:32:44 -0800 Subject: [PATCH 0394/1330] FROMLIST: arm64: dts: qcom: hamoa: Add remoteproc IOMMUS in EL2 device trees All the existing variants Hamoa boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add remoteproc IOMMUS to the EL2 device trees to generate the corresponding -el2.dtb files. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Xin Liu Link: https://lore.kernel.org/all/20260203063244.1498699-1-xin.liu@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/x1-el2.dtso | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index 175679be01eba..ee006742d6f3b 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -52,6 +52,14 @@ status = "okay"; }; +&remoteproc_adsp { + iommus = <&apps_smmu 0x1000 0x80>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x0c00 0x0>; +}; + /* * The "SBSA watchdog" is implemented in software in Gunyah * and can't be used when running in EL2. From 83ce0dbdf97879623e7f83d1d568027eb4244722 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:51:08 +0000 Subject: [PATCH 0395/1330] FROMLIST: arm64: dts: qcom: x1e80100: Add MIPI CSI PHY nodes Add csiphy nodes for - csiphy0 - csiphy1 - csiphy2 - csiphy4 The irregular naming of the PHYs comes directly from the hardware which for whatever reason skipped csiphy3. Separating the nodes from CAMSS as we have done with the sensor I2C bus aka the CCI interface is justified since the CSIPHYs have their own pinouts and voltage rails. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-x1e-camss-csi2-phy-dtsi-v1-3-f3f7ddfbf849@linaro.org/ --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 1056c4cc4ac51..eddfba5f8492b 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -929,6 +929,25 @@ }; }; + csiphy_opp_table: opp-table-csiphy { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + qup_opp_table_100mhz: opp-table-qup100mhz { compatible = "operating-points-v2"; From c3a8869f609ffda2e27d874dea4dd484221bc768 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:51:09 +0000 Subject: [PATCH 0396/1330] FROMLIST: arm64: dts: qcom: x1e80100: Add CAMSS block definition Add dtsi to describe the xe180100 CAMSS block 4 x CSIPHY 3 x TPG 2 x CSID 2 x CSID Lite 2 x IFE 2 x IFE Lite Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/all/20260226-x1e-camss-csi2-phy-dtsi-v1-4-f3f7ddfbf849@linaro.org/ From 8f58e241d52875bc751ebb9c26d53756879ea0bc Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:51:10 +0000 Subject: [PATCH 0397/1330] FROMLIST: arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m regulators Add pmic,id = m rpmh to regulator definitions. This regulator set provides vreg_l3m_1p8 the regulator for the ov08x40 RGB sensor on the CRD. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-x1e-camss-csi2-phy-dtsi-v1-5-f3f7ddfbf849@linaro.org/ From f4e3114d197685f057026cab8580bf36e32ddee6 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:51:11 +0000 Subject: [PATCH 0398/1330] FROMLIST: arm64: dts: qcom: x1e80100-crd: Add ov08x40 RGB sensor on CSIPHY4 Define ov08x40 on cci1_i2c1. The RGB sensor appears on the AON CCI pins connected to CSIPHY4 in four lane mode. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-x1e-camss-csi2-phy-dtsi-v1-6-f3f7ddfbf849@linaro.org/ From 544b2c2ef8fa38287c17b5dc2ffc3c358bfc57ee Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Feb 2026 14:51:14 +0000 Subject: [PATCH 0399/1330] FROMLIST: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add pm8010 camera PMIC with voltage levels for IR and RGB camera Add voltage regulators-8 for Camera on slim7x including: - vreg_l7m_2p8 - vreg_l2m_1p2 - vreg_l4m_1p8 Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard Link: https://lore.kernel.org/all/20260226-x1e-camss-csi2-phy-dtsi-v1-9-f3f7ddfbf849@linaro.org/ From a464bc7bccb5a02db9a141377c6cff121dd003b2 Mon Sep 17 00:00:00 2001 From: Tingguo Cheng Date: Fri, 27 Feb 2026 13:29:39 +0800 Subject: [PATCH 0400/1330] FROMLIST: arm64: dts: qcom: hamoa-iot-som: Add pm8010 L4M regulator Add pm8010 L4M regulator which is used by Camera I2C pull-up. Signed-off-by: Tingguo Cheng Signed-off-by: Wenmeng Liu Link: https://lore.kernel.org/all/20260227-hamoa_evk-v1-1-36f895a24d8f@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index b8e3e04a6fbd4..5d9af325c931e 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -376,6 +376,21 @@ regulator-initial-mode = ; }; }; + + /* PM8010_M */ + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + + vreg_l4m_1p8: ldo4 { + regulator-name = "vrer_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + }; }; &iris { From 752ee44785e1370a5cce0e3e577028a20b28b5e7 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 27 Feb 2026 13:29:40 +0800 Subject: [PATCH 0401/1330] FROMLIST: arm64: dts: qcom: hamoa-iot-evk-camera-imx577: Add DT overlay Enable IMX577 via CCI on Hamoa EVK Core Kit. The Hamoa EVK board does not include a camera sensor by default, this DTSO has enabled the Arducam 12.3MP IMX577 Mini Camera Module on the CSI-1 interface. Signed-off-by: Wenmeng Liu Link: https://lore.kernel.org/all/20260227-hamoa_evk-v1-2-36f895a24d8f@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/Makefile | 3 + .../dts/qcom/hamoa-iot-evk-camera-imx577.dtso | 81 +++++++++++++++++++ arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 16 ++++ 3 files changed, 100 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/hamoa-iot-evk-camera-imx577.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f6ea863b5b452..29a569a54a218 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -15,9 +15,12 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-camera-imx577.dtbo +hamoa-iot-evk-camera-imx577-dtbs := hamoa-iot-evk.dtb hamoa-iot-evk-camera-imx577.dtbo hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-camera-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk-camera-imx577.dtso b/arch/arm64/boot/dts/qcom/hamoa-iot-evk-camera-imx577.dtso new file mode 100644 index 0000000000000..f45a7fbd14b1f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk-camera-imx577.dtso @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + vreg_cam1_1p8: regulator-cam1 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1"; + startup-delay-us = <1000>; + enable-active-high; + gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>; + }; +}; + +&camss { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + csiphy1_ep: endpoint@0 { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep>; + }; + }; + }; +}; + +&cci0 { + status = "okay"; +}; + +&cci0_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 110 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam1_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + dvdd-supply = <&vreg_cam1_1p8>; + dovdd-supply = <&vreg_l4m_1p8>; + + port { + imx577_ep: endpoint { + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; + +&csiphy1 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index e6c7b0ed385de..801bff722e3c5 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -1324,6 +1324,22 @@ }; &tlmm { + cam1_default: cam1-default-state { + mclk-pins { + pins = "gpio97"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + rst-pins { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From 04034ed9e9df888f4cd28727cd993f5967aba7c7 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Mon, 2 Mar 2026 17:00:28 +0530 Subject: [PATCH 0402/1330] FROMLIST: arm64: dts: qcom: hamoa-iot-evk: Update TSENS thermal zone configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hamoa IOT boards support a different thermal junction temperature specification compared to the base Hamoa platform due to package level differences. Update the passive trip thresholds to 105°C to align with the higher temperature specification. Signed-off-by: Gaurav Kohli Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/linux-devicetree/20260302-higher_tj-v1-1-4c0d288f8e7f@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 801bff722e3c5..79be3d347f471 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -1602,3 +1602,69 @@ &usb_mp_hsphy1 { phys = <&eusb6_repeater>; }; + +&thermal_zones { + gpuss-0-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-1-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-2-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-3-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-4-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-5-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-6-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-7-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; +}; From 5c6c3ce3095cda10711a4a26ff2846fb6dcdaa96 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 29 Dec 2025 17:22:34 +0800 Subject: [PATCH 0403/1330] FROMLIST: arm64: dts: qcom: glymur: add coresight nodes Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF. These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and some small subsystems, such as GCC, IPCC, PMU and so on. Link: https://lore.kernel.org/all/20260318-add-coresight-dt-nodes-for-glymur-v2-1-d76e08f21fa5@oss.qualcomm.com/ Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1515 ++++++++++++++++++++++---- 1 file changed, 1306 insertions(+), 209 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 4886e87ebd490..5ecde8f62fed9 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -346,6 +346,18 @@ }; }; + dummy-sink { + compatible = "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = <&swao_rep_out1>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-glymur", "qcom,scm"; @@ -6457,263 +6469,1292 @@ }; }; - apps_smmu: iommu@15000000 { - compatible = "qcom,glymur-smmu-500", - "qcom,smmu-500", - "arm,mmu-500"; - reg = <0x0 0x15000000 0x0 0x100000>; - - #iommu-cells = <2>; - #global-interrupts = <1>; - - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + stm: stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; - dma-coherent; - }; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; - pcie_smmu: iommu@15480000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x15480000 0x0 0x20000>; - interrupts = , - , - ; - interrupt-names = "eventq", "cmdq-sync", "gerror"; - dma-coherent; - #iommu-cells = <1>; + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; }; - intc: interrupt-controller@17000000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x17000000 0x0 0x10000>, - <0x0 0x17080000 0x0 0x480000>; + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; - interrupts = ; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; - #interrupt-cells = <3>; - interrupt-controller; + in-ports { + #address-cells = <1>; + #size-cells = <0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + port@1 { + reg = <1>; - gic_its: msi-controller@17040000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0x17040000 0x0 0x40000>; + qdss_tpda_in1: endpoint { + remote-endpoint = <&spdm_tpdm_out>; + }; + }; + }; - msi-controller; - #msi-cells = <1>; + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = <&funnel0_in6>; + }; + }; }; }; - watchdog@17600000 { - compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; - reg = <0x0 0x17600000 0x0 0x1000>; - clocks = <&sleep_clk>; - interrupts = ; - }; + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; - pdp0_mbox: mailbox@17610000 { - compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; - reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; - interrupts = ; - #mbox-cells = <1>; - }; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; - timer@17810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17810000 0x0 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x0 0x20000000>; + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; - frame@17811000 { - reg = <0x0 0x17811000 0x1000>, - <0x0 0x17812000 0x1000>; + out-ports { + port { + spdm_tpdm_out: endpoint { + remote-endpoint = <&qdss_tpda_in1>; + }; + }; + }; + }; - interrupts = , - ; + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; - frame-number = <0>; - }; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; - frame@17813000 { - reg = <0x0 0x17813000 0x1000>; + in-ports { + #address-cells = <1>; + #size-cells = <0>; - interrupts = ; + port@0 { + reg = <0>; - frame-number = <1>; + funnel0_in0: endpoint { + remote-endpoint = <&tn_ag_out>; + }; + }; - status = "disabled"; - }; + port@6 { + reg = <6>; - frame@17815000 { - reg = <0x0 0x17815000 0x1000>; + funnel0_in6: endpoint { + remote-endpoint = <&qdss_tpda_out>; + }; + }; - interrupts = ; + port@7 { + reg = <7>; - frame-number = <2>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; - status = "disabled"; + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&aoss_funnel_in6>; + }; + }; }; + }; - frame@17817000 { - reg = <0x0 0x17817000 0x1000>; + tpdm@1102c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1102c000 0x0 0x1000>; - interrupts = ; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; - frame-number = <3>; + qcom,dsb-msrs-num = <32>; - status = "disabled"; + out-ports { + port { + gcc_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in36>; + }; + }; }; + }; - frame@17819000 { - reg = <0x0 0x17819000 0x1000>; + tpdm@11180000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11180000 0x0 0x1000>; - interrupts = ; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; - frame-number = <4>; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; - status = "disabled"; + out-ports { + port { + cdsp_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in0>; + }; + }; }; + }; - frame@1781b000 { - reg = <0x0 0x1781b000 0x1000>; + tpdm@11185000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11185000 0x0 0x1000>; - interrupts = ; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; - frame-number = <5>; + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; - status = "disabled"; + out-ports { + port { + cdsp_dpm1_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in5>; + }; + }; }; + }; - frame@1781d000 { - reg = <0x0 0x1781d000 0x1000>; + tpdm@11186000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11186000 0x0 0x1000>; - interrupts = ; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; - frame-number = <6>; + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; - status = "disabled"; + out-ports { + port { + cdsp_dpm2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in6>; + }; + }; }; }; - apps_rsc: rsc@18900000 { - compatible = "qcom,rpmh-rsc"; - label = "apps_rsc"; - reg = <0x0 0x18900000 0x0 0x10000>, - <0x0 0x18910000 0x0 0x10000>, + tpda@11188000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11188000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + cdsp_tpda_in0: endpoint { + remote-endpoint = <&cdsp_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + cdsp_tpda_in1: endpoint { + remote-endpoint = <&cdsp_llm_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + cdsp_tpda_in2: endpoint { + remote-endpoint = <&cdsp_llm2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + cdsp_tpda_in3: endpoint { + remote-endpoint = <&cdsp_cmsr_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + cdsp_tpda_in4: endpoint { + remote-endpoint = <&cdsp_cmsr2_tpdm_out>; + }; + }; + + port@5 { + reg = <5>; + + cdsp_tpda_in5: endpoint { + remote-endpoint = <&cdsp_dpm1_tpdm_out>; + }; + }; + + port@6 { + reg = <6>; + + cdsp_tpda_in6: endpoint { + remote-endpoint = <&cdsp_dpm2_tpdm_out>; + }; + }; + }; + + out-ports { + port { + cdsp_tpda_out: endpoint { + remote-endpoint = <&cdsp_funnel_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11189000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + cdsp_funnel_in0: endpoint { + remote-endpoint = <&cdsp_tpda_out>; + }; + }; + }; + + out-ports { + port { + cdsp_funnel_out: endpoint { + remote-endpoint = <&tn_ag_in53>; + }; + }; + }; + }; + + cti@11193000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x11193000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@111ab000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x111ab000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@111d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + qm_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in35>; + }; + }; + }; + }; + + tn@11200000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x0 0x11200000 0x0 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + + tn_ag_in6: endpoint { + remote-endpoint = <&mm_dsb_tpdm_out>; + }; + }; + + port@10 { + reg = <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint = <&east_dsb_tpdm_out>; + }; + }; + + port@21 { + reg = <0x21>; + + tn_ag_in33: endpoint { + remote-endpoint = <&west_dsb_tpdm_out>; + }; + }; + + port@23 { + reg = <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint = <&qm_tpdm_out>; + }; + }; + + port@24 { + reg = <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint = <&gcc_tpdm_out>; + }; + }; + + port@32 { + reg = <0x32>; + + tn_ag_in50: endpoint { + remote-endpoint = <&pcie_rscc_tpda_out>; + }; + }; + + port@35 { + reg = <0x35>; + + tn_ag_in53: endpoint { + remote-endpoint = <&cdsp_funnel_out>; + }; + }; + + port@3f { + reg = <0x3f>; + + tn_ag_in63: endpoint { + remote-endpoint = <¢er_dsb_tpdm_out>; + }; + }; + + port@40 { + reg = <0x40>; + + tn_ag_in64: endpoint { + remote-endpoint = <&ipcc_cmb_tpdm_out>; + }; + }; + + port@41 { + reg = <0x41>; + + tn_ag_in65: endpoint { + remote-endpoint = <&qrng_tpdm_out>; + }; + }; + + port@42 { + reg = <0x42>; + + tn_ag_in66: endpoint { + remote-endpoint = <&pmu_tpdm_out>; + }; + }; + + port@43 { + reg = <0x43>; + + tn_ag_in67: endpoint { + remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; + }; + }; + + port@44 { + reg = <0x44>; + + tn_ag_in68: endpoint { + remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; + }; + }; + + port@45 { + reg = <0x45>; + + tn_ag_in69: endpoint { + remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; + }; + }; + + port@4b { + reg = <0x4b>; + + tn_ag_in75: endpoint { + remote-endpoint = <&south_dsb2_tpdm_out>; + }; + }; + + port@52 { + reg = <0x52>; + + tn_ag_in82: endpoint { + remote-endpoint = <&south_dsb_tpdm_out>; + }; + }; + + port@53 { + reg = <0x53>; + + tn_ag_in83: endpoint { + remote-endpoint = <¢er_dsb1_tpdm_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint = <&funnel0_in0>; + }; + }; + }; + }; + + tpdm@11207000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11207000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + mm_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in6>; + }; + }; + }; + }; + + tpdm@1120b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1120b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + east_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@11213000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11213000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + west_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in33>; + }; + }; + }; + }; + + tpdm@11219000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11219000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + center_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in63>; + }; + }; + }; + }; + + tpdm@1121a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + ipcc_cmb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in64>; + }; + }; + }; + }; + + tpdm@1121b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qrng_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in65>; + }; + }; + }; + }; + + tpdm@1121c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + pmu_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in66>; + }; + }; + }; + }; + + tpdm@1121d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb0_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in67>; + }; + }; + }; + }; + + tpdm@1121e000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb1_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in68>; + }; + }; + }; + }; + + tpdm@1121f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb2_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in69>; + }; + }; + }; + }; + + tpdm@11220000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11220000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + center_dsb1_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in83>; + }; + }; + }; + }; + + tpdm@11224000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11224000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + south_dsb2_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in75>; + }; + }; + }; + }; + + tpdm@11228000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11228000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + south_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in82>; + }; + }; + }; + }; + + tpdm@11470000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11470000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + pcie_rscc_tpdm_out: endpoint { + remote-endpoint = <&pcie_rscc_tpda_in0>; + }; + }; + }; + }; + + tpda@11471000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11471000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + pcie_rscc_tpda_in0: endpoint { + remote-endpoint = <&pcie_rscc_tpdm_out>; + }; + }; + }; + + out-ports { + port { + pcie_rscc_tpda_out: endpoint { + remote-endpoint = <&tn_ag_in50>; + }; + }; + }; + }; + + tpdm@11c03000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c03000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio4_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in4>; + }; + }; + }; + }; + + funnel@11c04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11c04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + + aoss_funnel_in5: endpoint { + remote-endpoint = <&aoss_tpda_out>; + }; + }; + + port@6 { + reg = <6>; + + aoss_funnel_in6: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + }; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint = <&etf0_in>; + }; + }; + }; + }; + + tmc_etf: tmc@11c05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x11c05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint = <&aoss_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint = <&swao_rep_in>; + }; + }; + }; + }; + + replicator@11c06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x11c06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = <&etf0_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + swao_rep_out1: endpoint { + remote-endpoint = <&eud_in>; + }; + }; + }; + }; + + tpda@11c08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11c08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + aoss_tpda_in0: endpoint { + remote-endpoint = <&swao_prio0_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + aoss_tpda_in1: endpoint { + remote-endpoint = <&swao_prio1_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + aoss_tpda_in2: endpoint { + remote-endpoint = <&swao_prio2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + aoss_tpda_in3: endpoint { + remote-endpoint = <&swao_prio3_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + aoss_tpda_in4: endpoint { + remote-endpoint = <&swao_prio4_tpdm_out>; + }; + }; + + port@5 { + reg = <5>; + + aoss_tpda_in5: endpoint { + remote-endpoint = <&swao_tpdm_out>; + }; + }; + }; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = <&aoss_funnel_in5>; + }; + }; + }; + }; + + tpdm@11c09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio0_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@11c0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio1_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@11c0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio2_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@11c0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio3_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@11c0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + swao_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in5>; + }; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,glymur-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-coherent; + }; + + pcie_smmu: iommu@15480000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x15480000 0x0 0x20000>; + interrupts = , + , + ; + interrupt-names = "eventq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <1>; + }; + + intc: interrupt-controller@17000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17040000 0x0 0x40000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + watchdog@17600000 { + compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; + reg = <0x0 0x17600000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; + interrupts = ; + #mbox-cells = <1>; + }; + + timer@17810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17810000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x0 0x20000000>; + + frame@17811000 { + reg = <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + + interrupts = , + ; + + frame-number = <0>; + }; + + frame@17813000 { + reg = <0x0 0x17813000 0x1000>; + + interrupts = ; + + frame-number = <1>; + + status = "disabled"; + }; + + frame@17815000 { + reg = <0x0 0x17815000 0x1000>; + + interrupts = ; + + frame-number = <2>; + + status = "disabled"; + }; + + frame@17817000 { + reg = <0x0 0x17817000 0x1000>; + + interrupts = ; + + frame-number = <3>; + + status = "disabled"; + }; + + frame@17819000 { + reg = <0x0 0x17819000 0x1000>; + + interrupts = ; + + frame-number = <4>; + + status = "disabled"; + }; + + frame@1781b000 { + reg = <0x0 0x1781b000 0x1000>; + + interrupts = ; + + frame-number = <5>; + + status = "disabled"; + }; + + frame@1781d000 { + reg = <0x0 0x1781d000 0x1000>; + + interrupts = ; + + frame-number = <6>; + + status = "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible = "qcom,rpmh-rsc"; + label = "apps_rsc"; + reg = <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, <0x0 0x18920000 0x0 0x10000>; reg-names = "drv-0", "drv-1", @@ -8258,4 +9299,60 @@ }; }; }; + + tpdm-cdsp-llm { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + cdsp_llm_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + cdsp_llm2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in2>; + }; + }; + }; + }; + + tpdm-cdsp-cmsr { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + cdsp_cmsr_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in3>; + }; + }; + }; + }; + + tpdm-cdsp-cmsr2 { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + cdsp_cmsr2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in4>; + }; + }; + }; + }; }; From 930fbf57931621886c483aeaa17a237b683c167b Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 2 Mar 2026 15:23:32 +0800 Subject: [PATCH 0404/1330] QCLINUX: qcom-dcc: add device configuration for Glymur Add device configuration to enable DCC on Glymur platform. Signed-off-by: Jie Gan --- drivers/misc/qcom-dcc-dev.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index ff19dac70011f..5da18b4d221dd 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -66,6 +66,15 @@ static const struct dcc_pdata hamoa_pdata = { .map_ver = 0x3, }; +static const struct dcc_pdata glymur_pdata = { + .base = 0x100ff000, + .size = 0x1000, + .ram_base = 0x10080000, + .ram_size = 0x8000, + .dcc_offset = 0x0, + .map_ver = 0x3, +}; + static int __init dcc_dev_init(void) { int ret; @@ -141,6 +150,16 @@ static int __init dcc_dev_init(void) if (ret) goto fail; + break; + case 662: + case 698: + case 699: + case 718: + case 719: + ret = platform_device_add_data(dcc_pdev, &glymur_pdata, sizeof(glymur_pdata)); + if (ret) + goto fail; + break; default: pr_err("DCC: Invalid SoC ID\n"); From b7889064bb2362153a9d5296105d81aeeab1fc5f Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 2 Mar 2026 15:14:07 +0800 Subject: [PATCH 0405/1330] QCLINUX: memory-dump: add support for Glymur Glymur is sharing the same dump table content with Hamoa. So add Glymur's chip IDs for registering the dump table in memory. Signed-off-by: Jie Gan --- drivers/firmware/qcom/memory_dump_dev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c index 78fb377800bc9..0c0cb06462cc5 100644 --- a/drivers/firmware/qcom/memory_dump_dev.c +++ b/drivers/firmware/qcom/memory_dump_dev.c @@ -468,11 +468,18 @@ static int __init mem_dump_dev_init(void) goto fail; break; + /* Hamoa chip IDs */ case 555: case 615: case 616: case 709: case 710: + /* Glymur chip IDs */ + case 662: + case 698: + case 699: + case 718: + case 719: ret = platform_device_add_data(mem_dump_pdev, &hamoa_dump_table, sizeof(hamoa_dump_table)); if (ret) From 613f643c798f11f00244206be97ed7b590506d0d Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 28 Jan 2026 15:22:25 +0530 Subject: [PATCH 0406/1330] FROMLIST: dt-bindings: phy: qcom-edp: Add reference clock for sa8775p eDP PHY The initial sa8775p eDP PHY binding contribution missed adding support for voting on the eDP reference clock. This went unnoticed because the UFS PHY driver happened to enable the same clock. After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off calls"), the eDP reference clock is no longer kept enabled, which results in the following PHY power-on failure: phy phy-aec2a00.phy.10: phy poweron failed --> -110 To fix this, explicit voting for the eDP reference clock is required. This patch adds the eDP reference clock for sa8775p eDP PHY and updates the corresponding example node. Link: https://lore.kernel.org/all/20260128114853.2543416-2-quic_riteshk@quicinc.com/ Signed-off-by: Ritesh Kumar --- .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml | 6 ++++-- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index e2730a2f25cfb..6c827cf9692b9 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -200,9 +200,11 @@ examples: <0x0aec2000 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 4a1daae3d8d47..0bf8bf4f66acf 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -74,6 +74,7 @@ allOf: compatible: enum: - qcom,glymur-dp-phy + - qcom,sa8775p-edp-phy - qcom,x1e80100-dp-phy then: properties: From 2fa035249a3e8eba325a44e115b4c359a1d7c629 Mon Sep 17 00:00:00 2001 From: Gopi Botlagunta Date: Fri, 21 Nov 2025 19:12:06 +0530 Subject: [PATCH 0407/1330] FROMLIST: drm/bridge: lt9611uxc: Increase EDID wait time from 500ms to 1000ms EDID interrupt was coming 600-650 ms after HPD interrupt, resulting into EDID read timeout and default resolution of 1024x768 on display. Signed-off-by: Gopi Botlagunta Link: https://lore.kernel.org/all/20251121-hdmibridge-v1-1-14c63890f362@oss.qualcomm.com/ --- drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index 11aab07d88df6..ed06375c4c6f5 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -381,7 +381,7 @@ lt9611uxc_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connect static int lt9611uxc_wait_for_edid(struct lt9611uxc *lt9611uxc) { return wait_event_interruptible_timeout(lt9611uxc->wq, lt9611uxc->edid_read, - msecs_to_jiffies(500)); + msecs_to_jiffies(1000)); } static int lt9611uxc_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) From 9f7971a21f33787919aefcf3b2ffb878bcba1244 Mon Sep 17 00:00:00 2001 From: Nilesh Laad Date: Wed, 26 Nov 2025 17:01:18 +0530 Subject: [PATCH 0408/1330] FROMLIST: drm/bridge: lt9611uxc: extend mode valid checks Currently valid mode checks are only for hdisplay and vdisplay, add htotal and vtotal to filter only specific modes. Link:https://lore.kernel.org/lkml/20251126-lt9611uxc-modes-v2-1-34bf9b351921@oss.qualcomm.com/ Signed-off-by: Nilesh Laad Signed-off-by: Mahadevan P --- drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 36 ++++++++++++---------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index ed06375c4c6f5..cc2c9367f6d9d 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -88,7 +88,9 @@ static const struct regmap_config lt9611uxc_regmap_config = { struct lt9611uxc_mode { u16 hdisplay; + u16 htotal; u16 vdisplay; + u16 vtotal; u8 vrefresh; }; @@ -97,22 +99,22 @@ struct lt9611uxc_mode { * Enumerate them here to check whether the mode is supported. */ static struct lt9611uxc_mode lt9611uxc_modes[] = { - { 1920, 1080, 60 }, - { 1920, 1080, 30 }, - { 1920, 1080, 25 }, - { 1366, 768, 60 }, - { 1360, 768, 60 }, - { 1280, 1024, 60 }, - { 1280, 800, 60 }, - { 1280, 720, 60 }, - { 1280, 720, 50 }, - { 1280, 720, 30 }, - { 1152, 864, 60 }, - { 1024, 768, 60 }, - { 800, 600, 60 }, - { 720, 576, 50 }, - { 720, 480, 60 }, - { 640, 480, 60 }, + { 1920, 2200, 1080, 1125, 60 }, + { 1920, 2200, 1080, 1125, 30 }, + { 1920, 2640, 1080, 1125, 25 }, + { 1366, 1792, 768, 798, 60 }, + { 1360, 1792, 768, 795, 60 }, + { 1280, 1688, 1024, 1066, 60 }, + { 1280, 1680, 800, 831, 60 }, + { 1280, 1650, 720, 750, 60 }, + { 1280, 1980, 720, 750, 50 }, + { 1280, 3300, 720, 750, 30 }, + { 1152, 1600, 864, 900, 60 }, + { 1024, 1344, 768, 806, 60 }, + { 800, 1056, 600, 628, 60 }, + { 720, 864, 576, 625, 50 }, + { 720, 858, 480, 525, 60 }, + { 640, 800, 480, 525, 60 }, }; static struct lt9611uxc *bridge_to_lt9611uxc(struct drm_bridge *bridge) @@ -236,7 +238,9 @@ static struct lt9611uxc_mode *lt9611uxc_find_mode(const struct drm_display_mode for (i = 0; i < ARRAY_SIZE(lt9611uxc_modes); i++) { if (lt9611uxc_modes[i].hdisplay == mode->hdisplay && + lt9611uxc_modes[i].htotal == mode->htotal && lt9611uxc_modes[i].vdisplay == mode->vdisplay && + lt9611uxc_modes[i].vtotal == mode->vtotal && lt9611uxc_modes[i].vrefresh == drm_mode_vrefresh(mode)) { return <9611uxc_modes[i]; } From f699f369b8ec73e9eecc49251c2fd8774e1f37a8 Mon Sep 17 00:00:00 2001 From: Nilesh Laad Date: Wed, 26 Nov 2025 18:52:37 +0530 Subject: [PATCH 0409/1330] FROMLIST: drm/bridge: lt9611uxc: add support for 4K@30 resolution Add 3840x2160@30 mode in lt9611uxc modes to add support for 4K@30 resolution. Link:https://lore.kernel.org/r/20251126-lt9611uxc-4k30-v2-1-3de0ea58c24e@oss.qualcomm.com Signed-off-by: Nilesh Laad Signed-off-by: Mahadevan P --- drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index cc2c9367f6d9d..cd1a948d18afa 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -99,6 +99,7 @@ struct lt9611uxc_mode { * Enumerate them here to check whether the mode is supported. */ static struct lt9611uxc_mode lt9611uxc_modes[] = { + { 3840, 4400, 2160, 2250, 30 }, { 1920, 2200, 1080, 1125, 60 }, { 1920, 2200, 1080, 1125, 30 }, { 1920, 2640, 1080, 1125, 25 }, From 1d0853bcdab33a7768a75157762dfd27cd614bc1 Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Sun, 28 Dec 2025 17:10:39 +0530 Subject: [PATCH 0410/1330] FROMLIST: dt-bindings: bridge: lt8713sx: Add bindings Add bindings for lt8713sx. Co-developed-by: Prahlad Valluru Signed-off-by: Prahlad Valluru Signed-off-by: Vishnu Saini Link: https://lore.kernel.org/all/20251228-lt8713sx-bridge-driver-v3-1-9169fbef0e5b@oss.qualcomm.com/ --- .../display/bridge/lontium,lt8713sx.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/lontium,lt8713sx.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt8713sx.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt8713sx.yaml new file mode 100644 index 0000000000000..0a6dc56e337cb --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt8713sx.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/lontium,lt8713sx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lontium LT8713SX Type-C/DP1.4 to Type-C/DP1.4/HDMI2.0/DP++ bridge-hub + +maintainers: + - Tony + +description: + The Lontium LT8713SX is a Type-C/DP1.4 to Type-C/DP1.4/HDMI2.0 converter + that integrates one DP input and up to three configurable output interfaces + (DP1.4 / HDMI2.0 / DP++), with SST/MST functionality and audio support. + +properties: + compatible: + enum: + - lontium,lt8713sx + + reg: + maxItems: 1 + + vcc-supply: + description: Regulator for 3.3V vcc. + + vdd-supply: + description: Regulator for 1.1V vdd. + + reset-gpios: + description: GPIO connected to active low RESET pin. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + DP port for DP input from soc to bridge chip + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + DP port for DP output from bridge + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + Additional DP port for DP output from bridge + + required: + - port@0 + +required: + - compatible + - reg + - ports + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + bridge@4f { + compatible = "lontium,lt8713sx"; + reg = <0x4f>; + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt8713sx_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + + port@1 { + reg = <1>; + lt8713sx_dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + + port@2 { + reg = <2>; + lt8713sx_dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; + }; + }; + }; From 9f56859027528bc2838be24bf8ad347bfb933b73 Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Sun, 28 Dec 2025 17:10:40 +0530 Subject: [PATCH 0411/1330] FROMLIST: drm/bridge: add support for lontium lt8713sx bridge driver The lt8713sx is a Type-C/DP1.4 to Type-C/DP1.4/HDMI2.0 converter, with three configurable DP1.4/HDMI2.0/DP++ output interfaces and audio output interface. Driver is required for firmware upgrade in the bridge chip. Co-developed-by: Prahlad Valluru Signed-off-by: Prahlad Valluru Signed-off-by: Vishnu Saini Link: https://lore.kernel.org/all/20251228-lt8713sx-bridge-driver-v3-2-9169fbef0e5b@oss.qualcomm.com/ --- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/lontium-lt8713sx.c | 682 ++++++++++++++++++++++ 3 files changed, 693 insertions(+) create mode 100644 drivers/gpu/drm/bridge/lontium-lt8713sx.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 39385deafc68e..297bdf68dfff7 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -191,6 +191,16 @@ config DRM_LONTIUM_LT9611UXC HDMI signals Please say Y if you have such hardware. +config DRM_LONTIUM_LT8713SX + tristate "Lontium LT8713SX DP MST bridge" + depends on OF + select REGMAP_I2C + help + Driver for Lontium LT8713SX DP MST bridge + chip firmware upgrade, which converts Type-C/DP1.4 + to 3 configurable Type-C/DP1.4/HDMI2.0 outputs + Please say Y if you have such hardware. + config DRM_ITE_IT66121 tristate "ITE IT66121 HDMI bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 909c21cc3acd3..dc2ff31797b36 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o +obj-$(CONFIG_DRM_LONTIUM_LT8713SX) += lontium-lt8713sx.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o obj-$(CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER) += microchip-lvds.o diff --git a/drivers/gpu/drm/bridge/lontium-lt8713sx.c b/drivers/gpu/drm/bridge/lontium-lt8713sx.c new file mode 100644 index 0000000000000..6ea54ff3733d4 --- /dev/null +++ b/drivers/gpu/drm/bridge/lontium-lt8713sx.c @@ -0,0 +1,682 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define FW_FILE "lt8713sx_fw.bin" + +#define REG_PAGE_CONTROL 0xff + +#define MAX_OUTPUT_PORTS 3 +#define LT8713SX_PAGE_SIZE 256 + +DECLARE_CRC8_TABLE(lt8713sx_crc_table); + +struct lt8713sx { + struct device *dev; + struct drm_bridge bridge; + struct drm_bridge *next_bridge[MAX_OUTPUT_PORTS]; + int num_outputs; + + struct regmap *regmap; + /* Protects all accesses to registers by stopping the on-chip MCU */ + struct mutex ocm_lock; + + struct gpio_desc *reset_gpio; + struct gpio_desc *enable_gpio; + + struct i2c_client *client; + const struct firmware *fw; + + u8 *fw_buffer; + + u32 main_crc_value; + u32 bank_crc_value[17]; + + int bank_num; +}; + +static void lt8713sx_reset(struct lt8713sx *lt8713sx); + +static const struct regmap_range lt8713sx_ranges[] = { + { + .range_min = 0x0000, + .range_max = 0xffff + }, +}; + +static const struct regmap_access_table lt8713sx_table = { + .yes_ranges = lt8713sx_ranges, + .n_yes_ranges = ARRAY_SIZE(lt8713sx_ranges), +}; + +static const struct regmap_range_cfg lt8713sx_range_cfg = { + .name = "lt8713sx", + .range_min = 0x0000, + .range_max = 0xffff, + .selector_reg = REG_PAGE_CONTROL, + .selector_mask = 0xff, + .selector_shift = 0, + .window_start = 0, + .window_len = 0x100, +}; + +static const struct regmap_config lt8713sx_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = <8713sx_table, + .ranges = <8713sx_range_cfg, + .num_ranges = 1, + .cache_type = REGCACHE_NONE, + .max_register = 0xffff, +}; + +static void lt8713sx_i2c_enable(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe0ee, 0x01); +} + +static void lt8713sx_i2c_disable(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe0ee, 0x00); +} + +static u32 calculate_crc(const u8 *upgrade_data, u64 len, u64 crc_size) +{ + u8 crc = 0x00; + u8 pad = 0xff; + + crc = crc8(lt8713sx_crc_table, upgrade_data, len, crc); + + /* pad remaining bytes */ + crc_size -= len; + while (crc_size--) + crc = crc8(lt8713sx_crc_table, &pad, 1, crc); + + return crc; +} + +static int lt8713sx_prepare_firmware_data(struct lt8713sx *lt8713sx) +{ + int ret = 0; + u64 sz_12k = 12 * SZ_1K; + + ret = request_firmware(<8713sx->fw, FW_FILE, lt8713sx->dev); + if (ret < 0) { + dev_err(lt8713sx->dev, "request firmware failed\n"); + return ret; + } + + dev_dbg(lt8713sx->dev, "Firmware size: %zu bytes\n", lt8713sx->fw->size); + + if (lt8713sx->fw->size > SZ_256K - 1) { + dev_err(lt8713sx->dev, "Firmware size exceeds 256KB limit\n"); + release_firmware(lt8713sx->fw); + return -EINVAL; + } + + lt8713sx->fw_buffer = kvmalloc(SZ_256K, GFP_KERNEL); + if (!lt8713sx->fw_buffer) { + release_firmware(lt8713sx->fw); + return -ENOMEM; + } + + memset(lt8713sx->fw_buffer, 0xff, SZ_256K); + + if (lt8713sx->fw->size < SZ_64K) { + memcpy(lt8713sx->fw_buffer, lt8713sx->fw->data, lt8713sx->fw->size); + lt8713sx->fw_buffer[SZ_64K - 1] = + calculate_crc(lt8713sx->fw->data, lt8713sx->fw->size, SZ_64K - 1); + lt8713sx->main_crc_value = lt8713sx->fw_buffer[SZ_64K - 1]; + dev_dbg(lt8713sx->dev, + "Main Firmware Data Crc=0x%02X\n", lt8713sx->main_crc_value); + + } else { + /* main firmware */ + memcpy(lt8713sx->fw_buffer, lt8713sx->fw->data, SZ_64K - 1); + lt8713sx->fw_buffer[SZ_64K - 1] = + calculate_crc(lt8713sx->fw_buffer, SZ_64K - 1, SZ_64K - 1); + lt8713sx->main_crc_value = lt8713sx->fw_buffer[SZ_64K - 1]; + dev_dbg(lt8713sx->dev, + "Main Firmware Data Crc=0x%02X\n", lt8713sx->main_crc_value); + + /* bank firmware */ + memcpy(lt8713sx->fw_buffer + SZ_64K, + lt8713sx->fw->data + SZ_64K, + lt8713sx->fw->size - SZ_64K); + + lt8713sx->bank_num = (lt8713sx->fw->size - SZ_64K + sz_12k - 1) / sz_12k; + dev_dbg(lt8713sx->dev, "Bank Number Total is %d.\n", lt8713sx->bank_num); + + for (int i = 0; i < lt8713sx->bank_num; i++) { + lt8713sx->bank_crc_value[i] = + calculate_crc(lt8713sx->fw_buffer + SZ_64K + i * sz_12k, + sz_12k, sz_12k); + dev_dbg(lt8713sx->dev, "Bank number:%d; Firmware Data Crc:0x%02X\n", + i, lt8713sx->bank_crc_value[i]); + } + } + return 0; +} + +static void lt8713sx_config_parameters(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe0ee, 0x01); + regmap_write(lt8713sx->regmap, 0xe05e, 0xc1); + regmap_write(lt8713sx->regmap, 0xe058, 0x00); + regmap_write(lt8713sx->regmap, 0xe059, 0x50); + regmap_write(lt8713sx->regmap, 0xe05a, 0x10); + regmap_write(lt8713sx->regmap, 0xe05a, 0x00); + regmap_write(lt8713sx->regmap, 0xe058, 0x21); +} + +static void lt8713sx_wren(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe103, 0xbf); + regmap_write(lt8713sx->regmap, 0xe103, 0xff); + regmap_write(lt8713sx->regmap, 0xe05a, 0x04); + regmap_write(lt8713sx->regmap, 0xe05a, 0x00); +} + +static void lt8713sx_wrdi(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe05a, 0x08); + regmap_write(lt8713sx->regmap, 0xe05a, 0x00); +} + +static void lt8713sx_fifo_reset(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe103, 0xbf); + regmap_write(lt8713sx->regmap, 0xe103, 0xff); +} + +static void lt8713sx_disable_sram_write(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe055, 0x00); +} + +static void lt8713sx_sram_to_flash(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe05a, 0x30); + regmap_write(lt8713sx->regmap, 0xe05a, 0x00); +} + +static void lt8713sx_i2c_to_sram(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe055, 0x80); + regmap_write(lt8713sx->regmap, 0xe05e, 0xc0); + regmap_write(lt8713sx->regmap, 0xe058, 0x21); +} + +static u8 lt8713sx_read_flash_status(struct lt8713sx *lt8713sx) +{ + u32 flash_status = 0; + + regmap_write(lt8713sx->regmap, 0xe103, 0x3f); + regmap_write(lt8713sx->regmap, 0xe103, 0xff); + + regmap_write(lt8713sx->regmap, 0xe05e, 0x40); + regmap_write(lt8713sx->regmap, 0xe056, 0x05); /* opcode=read status register */ + regmap_write(lt8713sx->regmap, 0xe055, 0x25); + regmap_write(lt8713sx->regmap, 0xe055, 0x01); + regmap_write(lt8713sx->regmap, 0xe058, 0x21); + + regmap_read(lt8713sx->regmap, 0xe05f, &flash_status); + dev_dbg(lt8713sx->dev, "flash_status:%x\n", flash_status); + + return flash_status; +} + +static void lt8713sx_block_erase(struct lt8713sx *lt8713sx) +{ + u32 i = 0; + u8 flash_status = 0; + u8 blocknum = 0x00; + u32 flashaddr = 0x00; + + for (blocknum = 0; blocknum < 8; blocknum++) { + flashaddr = blocknum * SZ_32K; + regmap_write(lt8713sx->regmap, 0xe0ee, 0x01); + regmap_write(lt8713sx->regmap, 0xe05a, 0x04); + regmap_write(lt8713sx->regmap, 0xe05a, 0x00); + regmap_write(lt8713sx->regmap, 0xe05b, flashaddr >> 16); + regmap_write(lt8713sx->regmap, 0xe05c, flashaddr >> 8); + regmap_write(lt8713sx->regmap, 0xe05d, flashaddr); + regmap_write(lt8713sx->regmap, 0xe05a, 0x01); + regmap_write(lt8713sx->regmap, 0xe05a, 0x00); + msleep(100); + i = 0; + while (1) { + flash_status = lt8713sx_read_flash_status(lt8713sx); + if ((flash_status & 0x01) == 0) + break; + + if (i > 50) + break; + + i++; + msleep(50); + } + } + dev_dbg(lt8713sx->dev, "erase flash done.\n"); +} + +static void lt8713sx_load_main_fw_to_sram(struct lt8713sx *lt8713sx) +{ + regmap_write(lt8713sx->regmap, 0xe0ee, 0x01); + regmap_write(lt8713sx->regmap, 0xe068, 0x00); + regmap_write(lt8713sx->regmap, 0xe069, 0x00); + regmap_write(lt8713sx->regmap, 0xe06a, 0x00); + regmap_write(lt8713sx->regmap, 0xe065, 0x00); + regmap_write(lt8713sx->regmap, 0xe066, 0xff); + regmap_write(lt8713sx->regmap, 0xe067, 0xff); + regmap_write(lt8713sx->regmap, 0xe06b, 0x00); + regmap_write(lt8713sx->regmap, 0xe06c, 0x00); + regmap_write(lt8713sx->regmap, 0xe060, 0x01); + msleep(200); + regmap_write(lt8713sx->regmap, 0xe060, 0x00); +} + +static void lt8713sx_load_bank_fw_to_sram(struct lt8713sx *lt8713sx, u64 addr) +{ + regmap_write(lt8713sx->regmap, 0xe0ee, 0x01); + regmap_write(lt8713sx->regmap, 0xe068, ((addr & 0xff0000) >> 16)); + regmap_write(lt8713sx->regmap, 0xe069, ((addr & 0x00ff00) >> 8)); + regmap_write(lt8713sx->regmap, 0xe06a, (addr & 0x0000ff)); + regmap_write(lt8713sx->regmap, 0xe065, 0x00); + regmap_write(lt8713sx->regmap, 0xe066, 0x30); + regmap_write(lt8713sx->regmap, 0xe067, 0x00); + regmap_write(lt8713sx->regmap, 0xe06b, 0x00); + regmap_write(lt8713sx->regmap, 0xe06c, 0x00); + regmap_write(lt8713sx->regmap, 0xe060, 0x01); + msleep(50); + regmap_write(lt8713sx->regmap, 0xe060, 0x00); +} + +static int lt8713sx_write_data(struct lt8713sx *lt8713sx, const u8 *data, u64 filesize) +{ + int page = 0, num = 0, i = 0, val; + + page = (filesize % LT8713SX_PAGE_SIZE) ? + ((filesize / LT8713SX_PAGE_SIZE) + 1) : (filesize / LT8713SX_PAGE_SIZE); + + dev_dbg(lt8713sx->dev, + "Writing to Sram=%u pages, total size = %llu bytes\n", page, filesize); + + for (num = 0; num < page; num++) { + dev_dbg(lt8713sx->dev, "page[%d]\n", num); + lt8713sx_i2c_to_sram(lt8713sx); + + for (i = 0; i < LT8713SX_PAGE_SIZE; i++) { + if ((num * LT8713SX_PAGE_SIZE + i) < filesize) + val = *(data + (num * LT8713SX_PAGE_SIZE + i)); + else + val = 0xff; + regmap_write(lt8713sx->regmap, 0xe059, val); + } + + lt8713sx_wren(lt8713sx); + lt8713sx_sram_to_flash(lt8713sx); + } + + lt8713sx_wrdi(lt8713sx); + lt8713sx_disable_sram_write(lt8713sx); + + return 0; +} + +static void lt8713sx_main_upgrade_result(struct lt8713sx *lt8713sx) +{ + u32 main_crc_result; + + regmap_read(lt8713sx->regmap, 0xe023, &main_crc_result); + + dev_dbg(lt8713sx->dev, "Main CRC HW: 0x%02X\n", main_crc_result); + dev_dbg(lt8713sx->dev, "Main CRC FW: 0x%02X\n", lt8713sx->main_crc_value); + + if (main_crc_result == lt8713sx->main_crc_value) + dev_dbg(lt8713sx->dev, "Main Firmware Upgrade Success.\n"); + else + dev_err(lt8713sx->dev, "Main Firmware Upgrade Failed.\n"); +} + +static void lt8713sx_bank_upgrade_result(struct lt8713sx *lt8713sx, u8 banknum) +{ + u32 bank_crc_result; + + regmap_read(lt8713sx->regmap, 0xe023, &bank_crc_result); + + dev_dbg(lt8713sx->dev, "Bank %d CRC Result: 0x%02X\n", banknum, bank_crc_result); + + if (bank_crc_result == lt8713sx->bank_crc_value[banknum]) + dev_dbg(lt8713sx->dev, "Bank %d Firmware Upgrade Success.\n", banknum); + else + dev_err(lt8713sx->dev, "Bank %d Firmware Upgrade Failed.\n", banknum); +} + +static void lt8713sx_bank_result_check(struct lt8713sx *lt8713sx) +{ + int i; + u64 addr = 0x010000; + + for (i = 0; i < lt8713sx->bank_num; i++) { + lt8713sx_load_bank_fw_to_sram(lt8713sx, addr); + lt8713sx_bank_upgrade_result(lt8713sx, i); + addr += 0x3000; + } +} + +static int lt8713sx_firmware_upgrade(struct lt8713sx *lt8713sx) +{ + int ret; + + lt8713sx_config_parameters(lt8713sx); + + lt8713sx_block_erase(lt8713sx); + + if (lt8713sx->fw->size < SZ_64K) { + ret = lt8713sx_write_data(lt8713sx, lt8713sx->fw_buffer, SZ_64K); + if (ret < 0) { + dev_err(lt8713sx->dev, "Failed to write firmware data: %d\n", ret); + return ret; + } + } else { + ret = lt8713sx_write_data(lt8713sx, lt8713sx->fw_buffer, lt8713sx->fw->size); + if (ret < 0) { + dev_err(lt8713sx->dev, "Failed to write firmware data: %d\n", ret); + return ret; + } + } + dev_dbg(lt8713sx->dev, "Write Data done.\n"); + + return 0; +} + +static int lt8713sx_firmware_update(struct lt8713sx *lt8713sx) +{ + int ret = 0; + + mutex_lock(<8713sx->ocm_lock); + lt8713sx_i2c_enable(lt8713sx); + + ret = lt8713sx_prepare_firmware_data(lt8713sx); + if (ret < 0) { + dev_err(lt8713sx->dev, "Failed to prepare firmware data: %d\n", ret); + goto error; + } + + ret = lt8713sx_firmware_upgrade(lt8713sx); + if (ret < 0) { + dev_err(lt8713sx->dev, "Upgrade failure.\n"); + goto error; + } else { + /* Validate CRC */ + lt8713sx_load_main_fw_to_sram(lt8713sx); + lt8713sx_main_upgrade_result(lt8713sx); + lt8713sx_wrdi(lt8713sx); + lt8713sx_fifo_reset(lt8713sx); + lt8713sx_bank_result_check(lt8713sx); + lt8713sx_wrdi(lt8713sx); + } + +error: + lt8713sx_i2c_disable(lt8713sx); + if (!ret) + lt8713sx_reset(lt8713sx); + + kvfree(lt8713sx->fw_buffer); + lt8713sx->fw_buffer = NULL; + + if (lt8713sx->fw) { + release_firmware(lt8713sx->fw); + lt8713sx->fw = NULL; + } + mutex_unlock(<8713sx->ocm_lock); + + return ret; +} + +static void lt8713sx_reset(struct lt8713sx *lt8713sx) +{ + dev_dbg(lt8713sx->dev, "reset bridge.\n"); + gpiod_set_value_cansleep(lt8713sx->reset_gpio, 1); + msleep(20); + + gpiod_set_value_cansleep(lt8713sx->reset_gpio, 0); + msleep(20); + + dev_dbg(lt8713sx->dev, "reset done.\n"); +} + +static int lt8713sx_regulator_enable(struct lt8713sx *lt8713sx) +{ + int ret; + + ret = devm_regulator_get_enable(lt8713sx->dev, "vdd"); + if (ret < 0) + return dev_err_probe(lt8713sx->dev, ret, "failed to enable vdd regulator\n"); + + usleep_range(1000, 10000); + + ret = devm_regulator_get_enable(lt8713sx->dev, "vcc"); + if (ret < 0) + return dev_err_probe(lt8713sx->dev, ret, "failed to enable vcc regulator\n"); + return 0; +} + +static int lt8713sx_bridge_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) +{ + struct lt8713sx *lt8713sx = container_of(bridge, struct lt8713sx, bridge); + int i, ret; + + for (i = 0; i < lt8713sx->num_outputs; i++) { + if (!lt8713sx->next_bridge[i]) + continue; + + ret = drm_bridge_attach(encoder, + lt8713sx->next_bridge[i], + bridge, flags); + if (ret) + return ret; + } + + return 0; +} + +static int lt8713sx_get_ports(struct lt8713sx *lt8713sx) +{ + struct device *dev = lt8713sx->dev; + struct device_node *port, *ports, *ep, *remote; + int i = 0; + u32 reg; + + ports = of_get_child_by_name(dev->of_node, "ports"); + if (!ports) + return -ENODEV; + + for_each_child_of_node(ports, port) { + if (of_property_read_u32(port, "reg", ®)) + continue; + + if (reg == 0) + continue; + + if (i >= ARRAY_SIZE(lt8713sx->next_bridge)) { + of_node_put(port); + break; + } + + ep = of_graph_get_next_endpoint(port, NULL); + if (!ep) + continue; + + remote = of_graph_get_remote_port_parent(ep); + of_node_put(ep); + + if (!remote) + continue; + + lt8713sx->next_bridge[i] = of_drm_find_bridge(remote); + of_node_put(remote); + if (lt8713sx->next_bridge[i]) + i++; + } + lt8713sx->num_outputs = i; + dev_dbg(dev, "Enabled %d output ports", i); + + of_node_put(ports); + return 0; +}; + +static int lt8713sx_gpio_init(struct lt8713sx *lt8713sx) +{ + struct device *dev = lt8713sx->dev; + + lt8713sx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(lt8713sx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(lt8713sx->reset_gpio), + "failed to acquire reset gpio\n"); + + /* power enable gpio */ + lt8713sx->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); + if (IS_ERR(lt8713sx->enable_gpio)) + return dev_err_probe(dev, PTR_ERR(lt8713sx->enable_gpio), + "failed to acquire enable gpio\n"); + return 0; +} + +static ssize_t lt8713sx_firmware_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct lt8713sx *lt8713sx = dev_get_drvdata(dev); + int ret; + + ret = lt8713sx_firmware_update(lt8713sx); + if (ret < 0) + return ret; + return len; +} + +static DEVICE_ATTR_WO(lt8713sx_firmware); + +static struct attribute *lt8713sx_attrs[] = { + &dev_attr_lt8713sx_firmware.attr, + NULL, +}; + +static const struct attribute_group lt8713sx_attr_group = { + .attrs = lt8713sx_attrs, +}; + +static const struct attribute_group *lt8713sx_attr_groups[] = { + <8713sx_attr_group, + NULL, +}; + +static const struct drm_bridge_funcs lt8713sx_bridge_funcs = { + .attach = lt8713sx_bridge_attach, +}; + +static int lt8713sx_probe(struct i2c_client *client) +{ + struct lt8713sx *lt8713sx; + struct device *dev = &client->dev; + int ret; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + return dev_err_probe(dev, -ENODEV, "device doesn't support I2C\n"); + + lt8713sx = devm_drm_bridge_alloc(dev, struct lt8713sx, bridge, <8713sx_bridge_funcs); + if (IS_ERR(lt8713sx)) + return PTR_ERR(lt8713sx); + + lt8713sx->dev = dev; + lt8713sx->client = client; + i2c_set_clientdata(client, lt8713sx); + + ret = devm_mutex_init(lt8713sx->dev, <8713sx->ocm_lock); + if (ret) + return ret; + + lt8713sx->regmap = devm_regmap_init_i2c(client, <8713sx_regmap_config); + if (IS_ERR(lt8713sx->regmap)) + return dev_err_probe(dev, PTR_ERR(lt8713sx->regmap), "regmap i2c init failed\n"); + + ret = lt8713sx_get_ports(lt8713sx); + if (ret < 0) + return ret; + + ret = lt8713sx_gpio_init(lt8713sx); + if (ret < 0) + return ret; + + ret = lt8713sx_regulator_enable(lt8713sx); + if (ret) + return ret; + + lt8713sx_reset(lt8713sx); + + lt8713sx->bridge.funcs = <8713sx_bridge_funcs; + lt8713sx->bridge.of_node = dev->of_node; + lt8713sx->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; + drm_bridge_add(<8713sx->bridge); + + crc8_populate_msb(lt8713sx_crc_table, 0x31); + + return 0; +} + +static void lt8713sx_remove(struct i2c_client *client) +{ + struct lt8713sx *lt8713sx = i2c_get_clientdata(client); + + drm_bridge_remove(<8713sx->bridge); +} + +static struct i2c_device_id lt8713sx_id[] = { + { "lontium,lt8713sx", 0 }, + { /* sentinel */ } +}; + +static const struct of_device_id lt8713sx_match_table[] = { + { .compatible = "lontium,lt8713sx" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, lt8713sx_match_table); + +static struct i2c_driver lt8713sx_driver = { + .driver = { + .name = "lt8713sx", + .of_match_table = lt8713sx_match_table, + .dev_groups = lt8713sx_attr_groups, + }, + .probe = lt8713sx_probe, + .remove = lt8713sx_remove, + .id_table = lt8713sx_id, +}; + +module_i2c_driver(lt8713sx_driver); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("lt8713sx drm bridge driver"); +MODULE_AUTHOR("Tony "); +MODULE_FIRMWARE(FW_FILE); From 5aebd79c696a1f75e9cb319a149859dfc5bcfcf7 Mon Sep 17 00:00:00 2001 From: Yi Zhang Date: Fri, 23 Jan 2026 15:54:56 +0530 Subject: [PATCH 0412/1330] FROMLIST: dt-bindings: bridge: lt9211: Add bindings Add bindings for lt9211c. Signed-off-by: Gopi Botlagunta Signed-off-by: Yi Zhang Link: https://lore.kernel.org/all/20251224-add-lt9211c-bridge-v4-1-406e73ec28c5@oss.qualcomm.com/ --- .../display/bridge/lontium,lt9211.yaml | 42 ++++++++++++++++++- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml index 9a6e9b25d14a9..98079df61cbb3 100644 --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml @@ -4,19 +4,20 @@ $id: http://devicetree.org/schemas/display/bridge/lontium,lt9211.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge. +title: Lontium LT9211/LT9211C DSI/LVDS/DPI to DSI/LVDS/DPI bridge. maintainers: - Marek Vasut description: | - The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS + The LT9211 and LT9211C are bridge devices which convert Single/Dual-Link DSI/LVDS or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI. properties: compatible: enum: - lontium,lt9211 + - lontium,lt9211c reg: maxItems: 1 @@ -91,6 +92,43 @@ examples: vccio-supply = <<9211_1v8>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + }; + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + lvds-bridge@3b { + compatible = "lontium,lt9211c"; + reg = <0x3b>; + + reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; + + vccio-supply = <<9211c_1v8>; + ports { #address-cells = <1>; #size-cells = <0>; From 9552f9038ab94dfeff4cde30fcedbfd1803aa9e5 Mon Sep 17 00:00:00 2001 From: Yi Zhang Date: Wed, 28 Jan 2026 15:13:23 +0530 Subject: [PATCH 0413/1330] FROMLIST: drm/bridge: add support for lontium lt9211c bridge LT9211c is a Single/Dual-Link DSI/LVDS or Single DPI input to Single-link/Dual-Link DSI/LVDS or Single DPI output bridge chip. Extend the existing lontium-lt9211 driver to support DSI-to-LVDS bridge configuration. Signed-off-by: Yi Zhang Signed-off-by: Nilesh Laad Signed-off-by: Gopi Botlagunta Link: https://lore.kernel.org/lkml/20251224-add-lt9211c-bridge-v4-2-406e73ec28c5@oss.qualcomm.com/ --- drivers/gpu/drm/bridge/lontium-lt9211.c | 903 ++++++++++++++++++++++-- 1 file changed, 835 insertions(+), 68 deletions(-) diff --git a/drivers/gpu/drm/bridge/lontium-lt9211.c b/drivers/gpu/drm/bridge/lontium-lt9211.c index 03fc8fd10f20a..95fefab9c0216 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9211.c +++ b/drivers/gpu/drm/bridge/lontium-lt9211.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -28,28 +29,48 @@ #include #include -#define REG_PAGE_CONTROL 0xff -#define REG_CHIPID0 0x8100 -#define REG_CHIPID0_VALUE 0x18 -#define REG_CHIPID1 0x8101 -#define REG_CHIPID1_VALUE 0x01 -#define REG_CHIPID2 0x8102 -#define REG_CHIPID2_VALUE 0xe3 +#define REG_PAGE_CONTROL 0xff +#define REG_CHIPID0 0x8100 +#define REG_CHIPID0_VALUE 0x18 +#define REG_CHIPID1 0x8101 +#define REG_CHIPID1_VALUE 0x01 +#define REG_CHIPID2 0x8102 +#define REG_CHIPID2_VALUE 0xe3 -#define REG_DSI_LANE 0xd000 +/* LT9211C chip ID values */ +#define REG_CHIPID0_LT9211C_VALUE 0x21 +#define REG_CHIPID1_LT9211C_VALUE 0x03 +#define REG_CHIPID2_LT9211C_VALUE 0xe1 + +#define REG_DSI_LANE 0xd000 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */ -#define REG_DSI_LANE_COUNT(n) ((n) & 3) +#define REG_DSI_LANE_COUNT(n) ((n) & 3) + +/* Chip type enum */ +enum lt9211_chip_type { + LT9211, + LT9211C, +}; struct lt9211 { - struct drm_bridge bridge; - struct device *dev; - struct regmap *regmap; - struct mipi_dsi_device *dsi; - struct drm_bridge *panel_bridge; - struct gpio_desc *reset_gpio; - struct regulator *vccio; - bool lvds_dual_link; - bool lvds_dual_link_even_odd_swap; + struct drm_bridge bridge; + struct device *dev; + struct regmap *regmap; + struct mipi_dsi_device *dsi; + struct drm_bridge *panel_bridge; + struct gpio_desc *reset_gpio; + struct regulator *vccio; + bool lvds_dual_link; + bool lvds_dual_link_even_odd_swap; + + /* LT9211C specific fields */ + enum lt9211_chip_type chip_type; + struct workqueue_struct *wq; + struct delayed_work lt9211_dw; + struct drm_display_mode mode; + bool bpp24; + bool jeida; + bool de; }; static const struct regmap_range lt9211_rw_ranges[] = { @@ -86,13 +107,56 @@ static const struct regmap_config lt9211_regmap_config = { .val_bits = 8, .rd_table = <9211_rw_table, .wr_table = <9211_rw_table, - .volatile_table = <9211_rw_table, + .volatile_table = <9211_rw_table, .ranges = <9211_range, .num_ranges = 1, .cache_type = REGCACHE_MAPLE, .max_register = 0xda00, }; +static const struct regmap_range lt9211c_rw_ranges[] = { + regmap_reg_range(0xff, 0xff), + regmap_reg_range(0x8100, 0x8182), + regmap_reg_range(0x8200, 0x82aa), + regmap_reg_range(0x8500, 0x85ff), + regmap_reg_range(0x8600, 0x86a0), + regmap_reg_range(0x8700, 0x8746), + regmap_reg_range(0xd000, 0xd0a7), + regmap_reg_range(0xd400, 0xd42c), + regmap_reg_range(0xd800, 0xd838), + regmap_reg_range(0xd9c0, 0xd9d5), +}; + +static const struct regmap_access_table lt9211c_rw_table = { + .yes_ranges = lt9211c_rw_ranges, + .n_yes_ranges = ARRAY_SIZE(lt9211c_rw_ranges), +}; + +static const struct regmap_range_cfg lt9211c_range = { + .name = "lt9211c", + .range_min = 0x0000, + .range_max = 0xda00, + .selector_reg = REG_PAGE_CONTROL, + .selector_mask = 0xff, + .selector_shift = 0, + .window_start = 0, + .window_len = 0x100, +}; + +static const struct regmap_config lt9211c_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .rd_table = <9211c_rw_table, + .wr_table = <9211c_rw_table, + .volatile_table = <9211c_rw_table, + .ranges = <9211c_range, + .num_ranges = 1, + .cache_type = REGCACHE_RBTREE, + .max_register = 0xda00, +}; + +static void lt9211_delayed_work_func(struct work_struct *work); + static struct lt9211 *bridge_to_lt9211(struct drm_bridge *bridge) { return container_of(bridge, struct lt9211, bridge); @@ -120,14 +184,24 @@ static int lt9211_read_chipid(struct lt9211 *ctx) return ret; } - /* Test for known Chip ID. */ - if (chipid[0] != REG_CHIPID0_VALUE || chipid[1] != REG_CHIPID1_VALUE) { - dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n", - chipid[0], chipid[1], chipid[2]); - return -EINVAL; + /* Test for LT9211 Chip ID. */ + if (chipid[0] == REG_CHIPID0_VALUE && chipid[1] == REG_CHIPID1_VALUE && + chipid[2] == REG_CHIPID2_VALUE) { + dev_dbg(ctx->dev, "Detected LT9211 chip\n"); + return 0; } - return 0; + /* Test for LT9211C Chip ID. */ + if (chipid[0] == REG_CHIPID0_LT9211C_VALUE && + chipid[1] == REG_CHIPID1_LT9211C_VALUE && + chipid[2] == REG_CHIPID2_LT9211C_VALUE) { + dev_dbg(ctx->dev, "Detected LT9211C chip\n"); + return 0; + } + + dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n", chipid[0], + chipid[1], chipid[2]); + return -EINVAL; } static int lt9211_system_init(struct lt9211 *ctx) @@ -250,9 +324,9 @@ static int lt9211_autodetect_rx(struct lt9211 *ctx, height = (buf[3] << 8) | buf[4]; format = buf[2] & 0xf; - if (format == 0x3) { /* YUV422 16bit */ + if (format == 0x3) { /* YUV422 16bit */ width /= 2; - } else if (format == 0xa) { /* RGB888 24bit */ + } else if (format == 0xa) { /* RGB888 24bit */ width /= 3; } else { dev_err(ctx->dev, "Unsupported DSI pixel format 0x%01x\n", @@ -476,7 +550,7 @@ static void lt9211_atomic_enable(struct drm_bridge *bridge, /* Deassert reset */ gpiod_set_value(ctx->reset_gpio, 1); - usleep_range(20000, 21000); /* Very long post-reset delay. */ + usleep_range(20000, 21000); /* Very long post-reset delay. */ /* Get the LVDS format from the bridge state. */ bridge_state = drm_atomic_get_new_bridge_state(state, bridge); @@ -504,8 +578,8 @@ static void lt9211_atomic_enable(struct drm_bridge *bridge, lvds_format_24bpp = true; lvds_format_jeida = false; dev_warn(ctx->dev, - "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", - bridge_state->output_bus_cfg.format); + "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", + bridge_state->output_bus_cfg.format); break; } @@ -518,35 +592,42 @@ static void lt9211_atomic_enable(struct drm_bridge *bridge, crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; crtc_state = drm_atomic_get_new_crtc_state(state, crtc); mode = &crtc_state->adjusted_mode; - ret = lt9211_read_chipid(ctx); if (ret) return; - ret = lt9211_system_init(ctx); - if (ret) + if (ctx->chip_type == LT9211C && ctx->wq) { + drm_mode_copy(&ctx->mode, mode); + /* LT9211C must enable after mipi clock enable */ + queue_delayed_work(ctx->wq, &ctx->lt9211_dw, + msecs_to_jiffies(100)); + dev_dbg(ctx->dev, "LT9211C enabled.\n"); return; + } + ret = lt9211_system_init(ctx); + if (ret) + return; - ret = lt9211_configure_rx(ctx); - if (ret) - return; + ret = lt9211_configure_rx(ctx); + if (ret) + return; - ret = lt9211_autodetect_rx(ctx, mode); - if (ret) - return; + ret = lt9211_autodetect_rx(ctx, mode); + if (ret) + return; - ret = lt9211_configure_timing(ctx, mode); - if (ret) - return; + ret = lt9211_configure_timing(ctx, mode); + if (ret) + return; - ret = lt9211_configure_plls(ctx, mode); - if (ret) - return; + ret = lt9211_configure_plls(ctx, mode); + if (ret) + return; ret = lt9211_configure_tx(ctx, lvds_format_jeida, lvds_format_24bpp, - bus_flags & DRM_BUS_FLAG_DE_HIGH); - if (ret) - return; + bus_flags & DRM_BUS_FLAG_DE_HIGH); + if (ret) + return; dev_dbg(ctx->dev, "LT9211 enabled.\n"); } @@ -562,7 +643,7 @@ static void lt9211_atomic_disable(struct drm_bridge *bridge, * and assure lengthy 10ms reset low timing. */ gpiod_set_value(ctx->reset_gpio, 0); - usleep_range(10000, 11000); /* Very long reset duration. */ + usleep_range(10000, 11000); /* Very long reset duration. */ ret = regulator_disable(ctx->vccio); if (ret) @@ -585,7 +666,7 @@ lt9211_mode_valid(struct drm_bridge *bridge, return MODE_OK; } -#define MAX_INPUT_SEL_FORMATS 1 +#define MAX_INPUT_SEL_FORMATS 1 static u32 * lt9211_atomic_get_input_bus_fmts(struct drm_bridge *bridge, @@ -612,14 +693,14 @@ lt9211_atomic_get_input_bus_fmts(struct drm_bridge *bridge, } static const struct drm_bridge_funcs lt9211_funcs = { - .attach = lt9211_attach, - .mode_valid = lt9211_mode_valid, - .atomic_enable = lt9211_atomic_enable, - .atomic_disable = lt9211_atomic_disable, + .attach = lt9211_attach, + .mode_valid = lt9211_mode_valid, + .atomic_enable = lt9211_atomic_enable, + .atomic_disable = lt9211_atomic_disable, .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_get_input_bus_fmts = lt9211_atomic_get_input_bus_fmts, - .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_reset = drm_atomic_helper_bridge_reset, }; static int lt9211_parse_dt(struct lt9211 *ctx) @@ -671,11 +752,6 @@ static int lt9211_parse_dt(struct lt9211 *ctx) static int lt9211_host_attach(struct lt9211 *ctx) { - const struct mipi_dsi_device_info info = { - .type = "lt9211", - .channel = 0, - .node = NULL, - }; struct device *dev = ctx->dev; struct device_node *host_node; struct device_node *endpoint; @@ -684,6 +760,8 @@ static int lt9211_host_attach(struct lt9211 *ctx) int dsi_lanes; int ret; + /* Check if the compatible string matches lt9211c */ + endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); host_node = of_graph_get_remote_port_parent(endpoint); @@ -697,7 +775,22 @@ static int lt9211_host_attach(struct lt9211 *ctx) if (dsi_lanes < 0) return dsi_lanes; - dsi = devm_mipi_dsi_device_register_full(dev, host, &info); + if (ctx->chip_type == LT9211C) { + const struct mipi_dsi_device_info info = { + .type = "lt9211c", + .channel = 0, + .node = NULL, + }; + dsi = devm_mipi_dsi_device_register_full(dev, host, &info); + } else { + const struct mipi_dsi_device_info info = { + .type = "lt9211", + .channel = 0, + .node = NULL, + }; + dsi = devm_mipi_dsi_device_register_full(dev, host, &info); + } + if (IS_ERR(dsi)) return dev_err_probe(dev, PTR_ERR(dsi), "failed to create dsi device\n"); @@ -706,10 +799,16 @@ static int lt9211_host_attach(struct lt9211 *ctx) dsi->lanes = dsi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO_NO_HSA | - MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | - MIPI_DSI_MODE_NO_EOT_PACKET; + + if (ctx->chip_type == LT9211C) { + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM; + } else { + dsi->mode_flags = + MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO_NO_HSA | + MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | + MIPI_DSI_MODE_NO_EOT_PACKET; + } ret = devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { @@ -731,6 +830,7 @@ static int lt9211_probe(struct i2c_client *client) return PTR_ERR(ctx); ctx->dev = dev; + ctx->chip_type = LT9211; /* * Put the chip in reset, pull nRST line low, @@ -741,16 +841,32 @@ static int lt9211_probe(struct i2c_client *client) if (IS_ERR(ctx->reset_gpio)) return PTR_ERR(ctx->reset_gpio); - usleep_range(10000, 11000); /* Very long reset duration. */ + usleep_range(10000, 11000); /* Very long reset duration. */ ret = lt9211_parse_dt(ctx); + if (ret) return ret; - ctx->regmap = devm_regmap_init_i2c(client, <9211_regmap_config); + if (of_device_is_compatible(dev->of_node, "lontium,lt9211c")) { + ctx->chip_type = LT9211C; + ctx->regmap = + devm_regmap_init_i2c(client, <9211c_regmap_config); + } else { + ctx->chip_type = LT9211; + ctx->regmap = + devm_regmap_init_i2c(client, <9211_regmap_config); + } if (IS_ERR(ctx->regmap)) return PTR_ERR(ctx->regmap); + /* Initialize LT9211C-specific fields */ + ctx->wq = create_workqueue("lt9211_work"); + if (!ctx->wq) + return -ENOMEM; + + INIT_DELAYED_WORK(&ctx->lt9211_dw, lt9211_delayed_work_func); + dev_set_drvdata(dev, ctx); i2c_set_clientdata(client, ctx); @@ -768,17 +884,668 @@ static void lt9211_remove(struct i2c_client *client) { struct lt9211 *ctx = i2c_get_clientdata(client); + if (ctx->wq) + destroy_workqueue(ctx->wq); + drm_bridge_remove(&ctx->bridge); } +static int lt9211c_configure_rx(struct lt9211 *ctx) +{ + unsigned int pval; + + const struct reg_sequence lt9211c_rx_phy_seq[] = { + { REG_DSI_LANE, REG_DSI_LANE_COUNT(ctx->dsi->lanes) }, + { 0x8201, 0x11 }, + { 0x8218, 0x48 }, + { 0x8201, 0x91 }, + { 0x8202, 0x00 }, + { 0x8203, 0xee }, + { 0x8209, 0x21 }, + { 0x8204, 0x44 }, + { 0x8205, 0xc4 }, + { 0x8206, 0x44 }, + { 0x8213, 0x0c }, + + { 0xd001, 0x00 }, + { 0xd002, 0x0e }, + { 0xd005, 0x00 }, + { 0xd00a, 0x59 }, + { 0xd00b, 0x20 }, + }; + + const struct reg_sequence lt9211c_rx_phy_reset_seq[] = { + { 0x8109, 0xde }, + { 0x8109, 0xdf }, + }; + + const struct reg_sequence lt9211c_rx_clk_sel_seq[] = { + { 0x85e9, 0x88 }, + { 0x8180, 0x51 }, + { 0x8181, 0x10 }, + { 0x8632, 0x03 }, + }; + + const struct reg_sequence lt9211c_rx_input_sel_seq[] = { + { 0xd004, 0x00 }, + { 0xd021, 0x46 }, + }; + + const struct reg_sequence lt9211c_rx_dig_seq[] = { + { 0x853f, 0x08 }, + { 0x8540, 0x04 }, + { 0x8541, 0x03 }, + { 0x8542, 0x02 }, + { 0x8543, 0x01 }, + { 0x8545, 0x04 }, + { 0x8546, 0x03 }, + { 0x8547, 0x02 }, + { 0x8548, 0x01 }, + { 0x8544, 0x00 }, + { 0x8549, 0x00 }, + }; + + int ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_rx_phy_seq, + ARRAY_SIZE(lt9211c_rx_phy_seq)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_rx_phy_reset_seq, + ARRAY_SIZE(lt9211c_rx_phy_reset_seq)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_rx_clk_sel_seq, + ARRAY_SIZE(lt9211c_rx_clk_sel_seq)); + if (ret) + return ret; + + ret = regmap_read(ctx->regmap, 0x8180, &pval); + if (ret) + return ret; + + ret = regmap_write(ctx->regmap, 0x8180, (pval & 0xfc | 0x03)); + if (ret) + return ret; + + ret = regmap_read(ctx->regmap, 0x8680, &pval); + if (ret) + return ret; + + ret = regmap_write(ctx->regmap, 0x863f, (pval & 0xf8)); + if (ret) + return ret; + + ret = regmap_write(ctx->regmap, 0x863f, 0x05); + if (ret) + return ret; + + ret = regmap_read(ctx->regmap, 0x8530, &pval); + if (ret) + return ret; + + ret = regmap_write(ctx->regmap, 0x8530, (pval & 0xf8 | 0x11)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_rx_input_sel_seq, + ARRAY_SIZE(lt9211c_rx_input_sel_seq)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_rx_dig_seq, + ARRAY_SIZE(lt9211c_rx_dig_seq)); + if (ret) + return ret; + + /* Give the chip time to lock onto RX stream. */ + msleep(100); + + return 0; +} + +static int lt9211c_autodetect_rx(struct lt9211 *ctx, + const struct drm_display_mode *mode) +{ + u16 width, height; + u8 buf[5]; + u8 format; + u8 bc[3]; + u8 sot[8]; + int ret; + + /* Read the SOT from the chip. */ + ret = regmap_bulk_read(ctx->regmap, 0xd088, sot, sizeof(sot)); + if (ret) + return ret; + + dev_dbg(ctx->dev, "Sot Num = 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", sot[0], + sot[2], sot[4], sot[6]); + + dev_dbg(ctx->dev, "Sot Data = 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", sot[1], + sot[3], sot[5], sot[7]); + /* HS Settle Set */ + if (sot[0] > 0x10 && sot[0] < 0x50) + regmap_write(ctx->regmap, 0xd002, sot[0] - 5); + else + regmap_write(ctx->regmap, 0xd002, 0x08); + + /* Width/Height/Format Auto-detection */ + ret = regmap_bulk_read(ctx->regmap, 0xd082, buf, sizeof(buf)); + if (ret) + return ret; + + width = (buf[0] << 8) | buf[1]; + height = (buf[3] << 8) | buf[4]; + format = buf[2] & 0xf; + + if (format == 0x3) { /* YUV422 16bit */ + width /= 2; + } else if (format == 0xa) { /* RGB888 24bit */ + width /= 3; + } else { + dev_err(ctx->dev, "Unsupported DSI format 0x%01x\n", format); + return -EINVAL; + } + + if (width != mode->hdisplay) { + dev_err(ctx->dev, + "RX: Detected DSI width (%d) does not match mode hdisplay (%d)\n", + width, mode->hdisplay); + return -EINVAL; + } + + if (height != mode->vdisplay) { + dev_err(ctx->dev, + "RX: Detected DSI height (%d) does not match mode vdisplay (%d)\n", + height, mode->vdisplay); + return -EINVAL; + } + + dev_dbg(ctx->dev, "RX: %dx%d format=0x%01x\n", width, height, format); + return 0; +} + +static int lt9211c_configure_timing(struct lt9211 *ctx, + const struct drm_display_mode *mode) +{ + const struct reg_sequence lt9211c_timing[] = { + { 0xd00d, (mode->vtotal >> 8) & 0xff }, + { 0xd00e, mode->vtotal & 0xff }, + { 0xd00f, (mode->vdisplay >> 8) & 0xff }, + { 0xd010, mode->vdisplay & 0xff }, + { 0xd011, (mode->htotal >> 8) & 0xff }, + { 0xd012, mode->htotal & 0xff }, + { 0xd013, (mode->hdisplay >> 8) & 0xff }, + { 0xd014, mode->hdisplay & 0xff }, + { 0xd015, (mode->vsync_end - mode->vsync_start) & 0xff }, + { 0xd04c, ((mode->hsync_end - mode->hsync_start) >> 8) & 0xff }, + { 0xd016, (mode->hsync_end - mode->hsync_start) & 0xff }, + { 0xd017, ((mode->vsync_start - mode->vdisplay) >> 8) & 0xff }, + { 0xd018, (mode->vsync_start - mode->vdisplay) & 0xff }, + { 0xd019, ((mode->hsync_start - mode->hdisplay) >> 8) & 0xff }, + { 0xd01a, (mode->hsync_start - mode->hdisplay) & 0xff }, + }; + + return regmap_multi_reg_write(ctx->regmap, lt9211c_timing, + ARRAY_SIZE(lt9211c_timing)); +} + +static int lt9211c_configure_plls(struct lt9211 *ctx, + const struct drm_display_mode *mode) +{ + const struct reg_sequence lt9211c_dessc_pll_reset[] = { + { 0x8103, 0xfe, 2000 }, + { 0x8103, 0xff, 0 }, + }; + + const struct reg_sequence lt9211c_pcr_cali_seq[] = { + { 0xd00a, 0x5f }, + { 0xd01e, 0x51 }, + { 0xd023, 0x80 }, + { 0xd024, 0x70 }, + { 0xd025, 0x80 }, + { 0xd02a, 0x10 }, + { 0xd021, 0x4f }, + { 0xd022, 0xf0 }, + { 0xd038, 0x04 }, + { 0xd039, 0x08 }, + { 0xd03a, 0x10 }, + { 0xd03b, 0x20 }, + { 0xd03f, 0x04 }, + { 0xd040, 0x08 }, + { 0xd041, 0x10 }, + { 0xd042, 0x20 }, + { 0xd02b, 0xA0 }, + }; + + const struct reg_sequence lt9211c_pcr_reset_seq[] = { + { 0xd009, 0xdb }, + { 0xd009, 0xdf }, + { 0xd008, 0x80 }, + { 0xd008, 0x00 }, + }; + + unsigned int pval; + int ret; + u8 div; + u32 pcr_m; + u32 pcr_k; + u32 pcr_up; + u32 pcr_down; + + /* DeSSC PLL reference clock is 25 MHz XTal. */ + ret = regmap_write(ctx->regmap, 0x8226, 0x20); + if (ret) + return ret; + + /* Prediv = 0 */ + ret = regmap_write(ctx->regmap, 0x8227, 0x40); + if (ret) + return ret; + + if (mode->clock < 22000) { + ret = regmap_write(ctx->regmap, 0x822f, 0x07); + ret |= regmap_write(ctx->regmap, 0x822c, 0x01); + div = 16; + } else if (mode->clock < 44000) { + ret = regmap_write(ctx->regmap, 0x822f, 0x07); + div = 16; + } else if (mode->clock < 88000) { + ret = regmap_write(ctx->regmap, 0x822f, 0x06); + div = 8; + } else if (mode->clock < 176000) { + ret = regmap_write(ctx->regmap, 0x822f, 0x05); + div = 4; + } else { + ret = regmap_write(ctx->regmap, 0x822f, 0x04); + div = 2; + } + + if (ret) + return ret; + + pcr_m = (mode->clock * div) / 25; + pcr_k = pcr_m % 1000; + pcr_m /= 1000; + + pcr_up = pcr_m + 1; + pcr_down = pcr_m - 1; + + pcr_k <<= 14; + + ret = regmap_write(ctx->regmap, 0xd008, 0x00); + if (ret < 0) + return ret; + + /* 0xd026: pcr_m */ + ret = regmap_write(ctx->regmap, 0xd026, (0x80 | (u8)pcr_m) & 0x7f); + if (ret < 0) + return ret; + + /* 0xd027 0xd028 0xd029: pcr_k */ + ret = regmap_write(ctx->regmap, 0xd027, (pcr_k >> 16) & 0xff); + if (ret < 0) + return ret; + + ret = regmap_write(ctx->regmap, 0xd028, (pcr_k >> 8) & 0xff); + if (ret < 0) + return ret; + + ret = regmap_write(ctx->regmap, 0xd029, pcr_k & 0xff); + if (ret < 0) + return ret; + + /* 0xd02d: pcr_m overflow limit setting */ + ret = regmap_write(ctx->regmap, 0xd02d, pcr_up); + if (ret < 0) + return ret; + + /* 0xd031: pcr_m underflow limit setting */ + ret = regmap_write(ctx->regmap, 0xd031, pcr_down); + if (ret < 0) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_dessc_pll_reset, + ARRAY_SIZE(lt9211c_dessc_pll_reset)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_pcr_cali_seq, + ARRAY_SIZE(lt9211c_pcr_cali_seq)); + if (ret) + return ret; + + if (mode->clock < 44000) { + ret = regmap_write(ctx->regmap, 0xd00c, 0x60); + ret |= regmap_write(ctx->regmap, 0xd01b, 0x00); + ret |= regmap_write(ctx->regmap, 0xd01c, 0x60); + } else { + ret = regmap_write(ctx->regmap, 0xd00c, 0x40); + ret |= regmap_write(ctx->regmap, 0xd01b, 0x00); + ret |= regmap_write(ctx->regmap, 0xd01c, 0x40); + } + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_pcr_reset_seq, + ARRAY_SIZE(lt9211c_pcr_reset_seq)); + if (ret) + return ret; + + /* PCR stability test takes seconds. */ + ret = regmap_read_poll_timeout(ctx->regmap, 0xd087, pval, + ((pval & 0x18) == 0x18), 20000, 3000000); + if (ret) + dev_err(ctx->dev, "PCR unstable, ret=%i\n", ret); + + ret = regmap_write(ctx->regmap, 0x8180, 0x51); + if (ret) + return ret; + + ret = regmap_write(ctx->regmap, 0x863f, 0x00); + if (ret) + return ret; + + ret = regmap_write(ctx->regmap, 0x863f, 0x01); + if (ret) + return ret; + + ret = regmap_read_poll_timeout(ctx->regmap, 0x8640, pval, + ((pval & 0x01) == 0x01), 50000, 250000); + if (ret) + dev_err(ctx->dev, "Video check not stable, ret=%i\n", ret); + + return ret; +} + +static int lt9211c_configure_tx(struct lt9211 *ctx, + const struct drm_display_mode *mode) +{ + const struct reg_sequence lt9211c_tx_phy_off_seq[] = { + { 0x8236, 0x00 }, + { 0x8237, 0x00 }, + { 0x8108, 0x6f }, + { 0x8103, 0xbf }, + }; + + const struct reg_sequence lt9211c_tx_phy_seq[] = { + { 0x8236, 0x03 }, + { 0x8237, 0x44 }, + { 0x8238, 0x14 }, + { 0x8239, 0x31 }, + { 0x823a, 0xc8 }, + { 0x823b, 0x00 }, + { 0x823c, 0x0f }, + { 0x8246, 0x40 }, + { 0x8247, 0x40 }, + { 0x8248, 0x40 }, + { 0x8249, 0x40 }, + { 0x824a, 0x40 }, + { 0x824b, 0x40 }, + { 0x824c, 0x40 }, + { 0x824d, 0x40 }, + { 0x824e, 0x40 }, + { 0x824f, 0x40 }, + { 0x8250, 0x40 }, + { 0x8251, 0x40 }, + }; + + const struct reg_sequence lt9211c_tx_mltx_reset[] = { + { 0x8103, 0xbf }, + { 0x8103, 0xff }, + }; + + const struct reg_sequence lt9211c_tx_dig_seq[] = { + { 0x854a, 0x01 }, + { 0x854b, 0x00 }, + { 0x854c, 0x10 }, + { 0x854d, 0x20 }, + { 0x854e, 0x50 }, + { 0x854f, 0x30 }, + { 0x8550, 0x46 }, + { 0x8551, 0x10 }, + { 0x8552, 0x20 }, + { 0x8553, 0x50 }, + { 0x8554, 0x30 }, + { 0x8555, 0x00 }, + { 0x8556, 0x20 }, + + { 0x8568, 0x00 }, + { 0x856e, 0x10 | (ctx->de ? BIT(6) : 0) }, + { 0x856f, 0x81 | (ctx->jeida ? BIT(6) : 0) | + (ctx->lvds_dual_link ? BIT(4) : 0) | + (ctx->bpp24 ? BIT(2) : 0) }, + }; + + const struct reg_sequence lt9211c_tx_ssc_seq[] = { + { 0x8234, 0x00 }, + { 0x856e, 0x10 }, + { 0x8181, 0x15 }, + { 0x871e, 0x00 }, + { 0x8717, 0x02 }, + { 0x8718, 0x04 }, + { 0x8719, 0xd4 }, + { 0x871A, 0x00 }, + { 0x871B, 0x12 }, + { 0x871C, 0x00 }, + { 0x871D, 0x24 }, + { 0x871F, 0x1c }, + { 0x8720, 0x00 }, + { 0x8721, 0x00 }, + { 0x871e, 0x02 }, + }; + + const struct reg_sequence lt9211c_tx_pll_reset_seq[] = { + { 0x810c, 0xfe, 2000 }, + { 0x810c, 0xff, 0 }, + }; + + const struct reg_sequence lt9211c_tx_sw_reset_seq[] = { + { 0x8108, 0x6f, 2000 }, + { 0x8108, 0x7f, 0 }, + }; + + unsigned int pval; + int ret; + u32 phy_clk; + u8 pixclk_div; + u8 pre_div; + u8 div_set; + u8 sericlk_div; + u8 val; + + dev_info(ctx->dev, + "dual_link=%d,even_odd_swap=%d,bpp24=%d,jeida=%d,de=%d\n", + ctx->lvds_dual_link, ctx->lvds_dual_link_even_odd_swap, + ctx->bpp24, ctx->jeida, ctx->de); + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_tx_phy_off_seq, + ARRAY_SIZE(lt9211c_tx_phy_off_seq)); + if (ret) + return ret; + + ret = regmap_read(ctx->regmap, 0x8530, &pval); + if (ret) + return ret; + + ret = regmap_write(ctx->regmap, 0x8530, (pval & 0x3f | 0x40)); + if (ret) + return ret; + + /* [7]0:txpll normal work; txpll ref clk sel pix clk */ + ret = regmap_write(ctx->regmap, 0x8230, 0x00); + if (ret) + return ret; + + if (ctx->lvds_dual_link) + phy_clk = (u32)(mode->clock * 7 / 2); + else + phy_clk = (u32)(mode->clock * 7); + + /* 0x8231: prediv sel */ + if (mode->clock < 20000) { + val = 0x28; + pre_div = 1; + } else if (mode->clock < 40000) { + val = 0x28; + pre_div = 1; + } else if (mode->clock < 80000) { + val = 0x29; + pre_div = 2; + } else if (mode->clock < 160000) { + val = 0x2a; + pre_div = 4; + } else if (mode->clock < 320000) { + val = 0x2b; + pre_div = 8; + } else { + val = 0x2f; + pre_div = 16; + } + ret = regmap_write(ctx->regmap, 0x8231, val); + if (ret < 0) + return ret; + + /* 0x8232: serickdiv sel */ + if (phy_clk < 80000) { + val = 0x32; + sericlk_div = 16; + } else if (phy_clk < 160000) { + val = 0x22; + sericlk_div = 8; + } else if (phy_clk < 320000) { + val = 0x12; + sericlk_div = 4; + } else if (phy_clk < 640000) { + val = 0x02; + sericlk_div = 2; + } else { + val = 0x42; + sericlk_div = 1; + } + ret = regmap_write(ctx->regmap, 0x8232, val); + if (ret < 0) + return ret; + + /* 0x8233: pix_mux sel & pix_div sel + * To avoid floating point operations, The pixclk_div is enlarged by 10 times + */ + if (mode->clock > 150000) { + val = 0x04; + pixclk_div = 35; + } else { + pixclk_div = + (u8)((phy_clk * sericlk_div * 10) / (mode->clock * 7)); + if (pixclk_div <= 10) + val = 0x00; + else if (pixclk_div <= 20) + val = 0x01; + else if (pixclk_div <= 40) + val = 0x02; + else + val = 0x03; + } + ret = regmap_write(ctx->regmap, 0x8233, val); + if (ret < 0) + return ret; + + ret = regmap_write(ctx->regmap, 0x8234, 0x01); + if (ret < 0) + return ret; + + /* 0x8235: div set */ + div_set = (u8)(phy_clk * sericlk_div / mode->clock / pre_div); + ret = regmap_write(ctx->regmap, 0x8235, div_set); + if (ret < 0) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_tx_ssc_seq, + ARRAY_SIZE(lt9211c_tx_ssc_seq)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_tx_pll_reset_seq, + ARRAY_SIZE(lt9211c_tx_pll_reset_seq)); + if (ret) + return ret; + + ret = regmap_read_poll_timeout(ctx->regmap, 0x8739, pval, pval & 0x04, + 10000, 1000000); + if (ret) { + dev_err(ctx->dev, "TX PLL unstable, ret=%i\n", ret); + return ret; + } + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_tx_phy_seq, + ARRAY_SIZE(lt9211c_tx_phy_seq)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_tx_mltx_reset, + ARRAY_SIZE(lt9211c_tx_mltx_reset)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_tx_dig_seq, + ARRAY_SIZE(lt9211c_tx_dig_seq)); + if (ret) + return ret; + + ret = regmap_multi_reg_write(ctx->regmap, lt9211c_tx_sw_reset_seq, + ARRAY_SIZE(lt9211c_tx_sw_reset_seq)); + if (ret) + return ret; + + return 0; +} + +static void lt9211_delayed_work_func(struct work_struct *work) +{ + struct delayed_work *dw = to_delayed_work(work); + struct lt9211 *ctx = container_of(dw, struct lt9211, lt9211_dw); + int ret; + const struct drm_display_mode *mode = &ctx->mode; + + /* For LT9211C */ + if (ctx->chip_type != LT9211C) { + dev_err(ctx->dev, "LT9211: Delayed work called for non-LT9211C chip\n"); + return; + } + ret = lt9211c_configure_rx(ctx); + if (ret) + return; + + ret = lt9211c_autodetect_rx(ctx, mode); + if (ret) + return; + + ret = lt9211c_configure_timing(ctx, mode); + if (ret) + return; + + ret = lt9211c_configure_plls(ctx, mode); + if (ret) + return; + + ret = lt9211c_configure_tx(ctx, mode); + if (ret) + return; + +} + static const struct i2c_device_id lt9211_id[] = { { "lontium,lt9211" }, + { "lontium,lt9211c" }, {}, }; MODULE_DEVICE_TABLE(i2c, lt9211_id); static const struct of_device_id lt9211_match_table[] = { { .compatible = "lontium,lt9211" }, + { .compatible = "lontium,lt9211c" }, {}, }; MODULE_DEVICE_TABLE(of, lt9211_match_table); From a4dafeb756ff83235bc28b6dc435c0cb4cfb6ff7 Mon Sep 17 00:00:00 2001 From: Nilesh Laad Date: Wed, 28 Jan 2026 18:28:20 +0530 Subject: [PATCH 0414/1330] FROMLIST: drm/bridge: lt9611uxc: reset edid_read on disconnect Currently edid_read has value from previous connect session and resulting in drm using older edid before new edid is available in lt9611uxc. Reset edid_read so that correct status is updated and correct edid is available for drm. Link: https://lore.kernel.org/lkml/20260202-lt9611uxc-reset-edid-v2-1-b1e1d72edc90@oss.qualcomm.com/ Signed-off-by: Ravi Agola Signed-off-by: Nilesh Laad --- drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index cd1a948d18afa..1c0e97030419e 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -173,6 +173,9 @@ static void lt9611uxc_hpd_work(struct work_struct *work) connected = lt9611uxc->hdmi_connected; mutex_unlock(<9611uxc->ocm_lock); + if (!connected) + lt9611uxc->edid_read = false; + drm_bridge_hpd_notify(<9611uxc->bridge, connected ? connector_status_connected : From 45d7e44cc1db5a999e37eb4993a715d683803761 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 25 Nov 2025 23:15:12 +0530 Subject: [PATCH 0415/1330] FROMLIST: clk: qcom: clk-alpha-pll: Add support for controlling Rivian PLL Add clock ops for Rivian ELU and EKO_T PLLs, add the register offsets for the Rivian ELU PLL. Since ELU and EKO_T shared the same offsets and PLL ops, reuse the Rivian EKO_T enum. Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251125-kaanapali-mmcc-v2-v2-3-fb44e78f300b@oss.qualcomm.com Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 42d3344921457..302c96b518b98 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -212,6 +212,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_pongo_elu_ops; #define clk_alpha_pll_pongo_eko_t_ops clk_alpha_pll_pongo_elu_ops extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; +#define clk_alpha_pll_rivian_elu_ops clk_alpha_pll_rivian_evo_ops +#define clk_alpha_pll_rivian_eko_t_ops clk_alpha_pll_rivian_evo_ops #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops #define clk_alpha_pll_rivian_elu_ops clk_alpha_pll_rivian_evo_ops #define clk_alpha_pll_rivian_eko_t_ops clk_alpha_pll_rivian_evo_ops From 4e130739641dcfd6839dbfa149207801b01928c6 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 24 Jan 2026 23:05:02 +0530 Subject: [PATCH 0416/1330] FROMLIST: dt-bindings: clock: qcom: Add video clock controller on Glymur SoC Add compatible string for Glymur video clock controller and the bindings for Glymur Qualcomm SoC. Add the clock resets required from the GCC clock controller for Video. Link: https://lore.kernel.org/r/20260124-glymur_videocc-v1-1-668f8b9c63be@oss.qualcomm.com Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-videocc.yaml | 3 ++ .../dt-bindings/clock/qcom,glymur-videocc.h | 45 +++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,glymur-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index e6beebd6a36ee..7bbf120d928cc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -15,6 +15,7 @@ description: | domains on SM8450. See also: + include/dt-bindings/clock/qcom,glymur-videocc.h include/dt-bindings/clock/qcom,kaanapali-videocc.h include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h @@ -23,6 +24,7 @@ description: | properties: compatible: enum: + - qcom,glymur-videocc - qcom,kaanapali-videocc - qcom,sm8450-videocc - qcom,sm8475-videocc @@ -63,6 +65,7 @@ allOf: compatible: contains: enum: + - qcom,glymur-videocc - qcom,kaanapali-videocc - qcom,sm8450-videocc - qcom,sm8550-videocc diff --git a/include/dt-bindings/clock/qcom,glymur-videocc.h b/include/dt-bindings/clock/qcom,glymur-videocc.h new file mode 100644 index 0000000000000..98c0debef8fa9 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-videocc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_FREERUN_CLK 5 +#define VIDEO_CC_MVS0_SHIFT_CLK 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS0C_FREERUN_CLK 9 +#define VIDEO_CC_MVS0C_SHIFT_CLK 10 +#define VIDEO_CC_MVS1_CLK 11 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 12 +#define VIDEO_CC_MVS1_FREERUN_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_PLL0 15 +#define VIDEO_CC_SLEEP_CLK 16 +#define VIDEO_CC_SLEEP_CLK_SRC 17 +#define VIDEO_CC_XO_CLK 18 +#define VIDEO_CC_XO_CLK_SRC 19 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 +#define VIDEO_CC_MVS1_GDSC 2 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_BCR 2 +#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 3 +#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4 +#define VIDEO_CC_MVS1_FREERUN_CLK_ARES 5 +#define VIDEO_CC_XO_CLK_ARES 6 +#define VIDEO_CC_MVS1_BCR 7 +#endif From 54802bbf2379ca6a5510acac87061b12b52bcf0b Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 24 Jan 2026 23:05:03 +0530 Subject: [PATCH 0417/1330] FROMLIST: clk: qcom: videocc-glymur: Add video clock controller driver for Glymur Add support for the video clock controller for video clients to be able to request for videocc clocks on Glymur platform. Link: https://lore.kernel.org/r/20260124-glymur_videocc-v1-2-668f8b9c63be@oss.qualcomm.com Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-glymur.c | 526 ++++++++++++++++++++++++++++++ 3 files changed, 536 insertions(+) create mode 100644 drivers/clk/qcom/videocc-glymur.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a8a86ea6bb744..20af4340b08f9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -46,6 +46,15 @@ config CLK_GLYMUR_TCSRCC Support for the TCSR clock controller on GLYMUR devices. Say Y if you want to use peripheral devices such as USB/PCIe/EDP. +config CLK_GLYMUR_VIDEOCC + tristate "Glymur Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_GLYMUR_GCC + help + Support for the video clock controller on Glymur devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config CLK_KAANAPALI_CAMCC tristate "Kaanapali Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6b0ad8832b55f..a71dfd0ddf512 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o +obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) += videocc-glymur.o obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o diff --git a/drivers/clk/qcom/videocc-glymur.c b/drivers/clk/qcom/videocc-glymur.c new file mode 100644 index 0000000000000..a504586698255 --- /dev/null +++ b/drivers/clk/qcom/videocc-glymur.c @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_SLEEP_CLK, + P_VIDEO_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco taycan_eko_t_vco[] = { + { 249600000, 2500000000, 0 }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x25c400e7, + .config_ctl_hi_val = 0x0a8060e0, + .config_ctl_hi1_val = 0xf51dea20, + .user_ctl_val = 0x00000008, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll0 = { + .offset = 0x0, + .config = &video_cc_pll0_config, + .vco_table = taycan_eko_t_vco, + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map video_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src = { + .cmd_rcgr = 0x8018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_0, + .freq_tbl = ftbl_video_cc_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_ahb_clk_src", + .parent_data = video_cc_parent_data_0, + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1965000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src = { + .cmd_rcgr = 0x8000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_1, + .freq_tbl = ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk_src", + .parent_data = video_cc_parent_data_1, + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src = { + .cmd_rcgr = 0x8120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_2, + .freq_tbl = ftbl_video_cc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_sleep_clk_src", + .parent_data = video_cc_parent_data_2, + .num_parents = ARRAY_SIZE(video_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src = { + .cmd_rcgr = 0x80f8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_0, + .freq_tbl = ftbl_video_cc_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_xo_clk_src", + .parent_data = video_cc_parent_data_0, + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src = { + .reg = 0x809c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { + .reg = 0x8060, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src = { + .reg = 0x80d8, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk = { + .halt_reg = 0x807c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x807c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x807c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_freerun_clk = { + .halt_reg = 0x808c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x808c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_freerun_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk = { + .halt_reg = 0x8114, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8114, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8114, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk = { + .halt_reg = 0x804c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x804c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_freerun_clk = { + .halt_reg = 0x805c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x805c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_freerun_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk = { + .halt_reg = 0x811c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x811c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x811c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk = { + .halt_reg = 0x80b8, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x80b8, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_freerun_clk = { + .halt_reg = 0x80c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80c8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_freerun_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_shift_clk = { + .halt_reg = 0x8118, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8118, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8118, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc = { + .gdscr = 0x8034, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs0c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc = { + .gdscr = 0x8068, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent = &video_cc_mvs0c_gdsc.pd, +}; + +static struct gdsc video_cc_mvs1_gdsc = { + .gdscr = 0x80a4, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *video_cc_glymur_clocks[] = { + [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, + [VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1_FREERUN_CLK] = &video_cc_mvs1_freerun_clk.clkr, + [VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr, + [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_glymur_gdscs[] = { + [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, + [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, +}; + +static const struct qcom_reset_map video_cc_glymur_resets[] = { + [VIDEO_CC_INTERFACE_BCR] = { 0x80dc }, + [VIDEO_CC_MVS0_BCR] = { 0x8064 }, + [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x805c, 2 }, + [VIDEO_CC_MVS0C_BCR] = { 0x8030 }, + [VIDEO_CC_MVS0_FREERUN_CLK_ARES] = { 0x808c, 2 }, + [VIDEO_CC_MVS1_FREERUN_CLK_ARES] = { 0x80c8, 2 }, + [VIDEO_CC_MVS1_BCR] = { 0x80a0 }, +}; + +static struct clk_alpha_pll *video_cc_glymur_plls[] = { + &video_cc_pll0, +}; + +static u32 video_cc_glymur_critical_cbcrs[] = { + 0x80e0, /* VIDEO_CC_AHB_CLK */ + 0x8138, /* VIDEO_CC_SLEEP_CLK */ + 0x8110, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_glymur_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9f54, + .fast_io = true, +}; + +static struct qcom_cc_driver_data video_cc_glymur_driver_data = { + .alpha_plls = video_cc_glymur_plls, + .num_alpha_plls = ARRAY_SIZE(video_cc_glymur_plls), + .clk_cbcrs = video_cc_glymur_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(video_cc_glymur_critical_cbcrs), +}; + +static struct qcom_cc_desc video_cc_glymur_desc = { + .config = &video_cc_glymur_regmap_config, + .clks = video_cc_glymur_clocks, + .num_clks = ARRAY_SIZE(video_cc_glymur_clocks), + .resets = video_cc_glymur_resets, + .num_resets = ARRAY_SIZE(video_cc_glymur_resets), + .gdscs = video_cc_glymur_gdscs, + .num_gdscs = ARRAY_SIZE(video_cc_glymur_gdscs), + .use_rpm = true, + .driver_data = &video_cc_glymur_driver_data, +}; + +static const struct of_device_id video_cc_glymur_match_table[] = { + { .compatible = "qcom,glymur-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_glymur_match_table); + +static int video_cc_glymur_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_glymur_desc); +} + +static struct platform_driver video_cc_glymur_driver = { + .probe = video_cc_glymur_probe, + .driver = { + .name = "videocc-glymur", + .of_match_table = video_cc_glymur_match_table, + }, +}; + +module_platform_driver(video_cc_glymur_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC Glymur Driver"); +MODULE_LICENSE("GPL"); From 84d72f5e9d507fb8ff754ce77a7341580337b505 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 30 Jan 2026 15:15:31 +0530 Subject: [PATCH 0418/1330] FROMLIST: dt-bindings: clock: qcom: document the Glymur GPU Clock Controller Glymur SoC has Qualcomm GX(graphics) clock controller and also the Graphics clock controller. The GX graphics clock controller helps in the recovery of the Graphics subsystem. Add bindings documentation for the Glymur Graphics Clock and Graphics power domain Controller for Glymur SoC. Link: https://lore.kernel.org/all/20260127-glymur_gpucc-v1-1-547334c81ba2@oss.qualcomm.com/ Signed-off-by: Taniya Das --- .../clock/qcom,kaanapali-gxclkctl.yaml | 1 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 4 +- include/dt-bindings/clock/qcom,glymur-gpucc.h | 51 +++++++++++++++++++ 3 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,glymur-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml index 5490a975f3db7..55bf3f8110171 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,glymur-gxclkctl - qcom,kaanapali-gxclkctl power-domains: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 6feaa32569f9a..5993804c91fa5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -13,7 +13,8 @@ description: | Qualcomm graphics clock control module provides the clocks, resets and power domains on Qualcomm SoCs. - See also:: + See also: + include/dt-bindings/clock/qcom,glymur-gpucc.h include/dt-bindings/clock/qcom,kaanapali-gpucc.h include/dt-bindings/clock/qcom,milos-gpucc.h include/dt-bindings/clock/qcom,sar2130p-gpucc.h @@ -27,6 +28,7 @@ description: | properties: compatible: enum: + - qcom,glymur-gpucc - qcom,kaanapali-gpucc - qcom,milos-gpucc - qcom,sar2130p-gpucc diff --git a/include/dt-bindings/clock/qcom,glymur-gpucc.h b/include/dt-bindings/clock/qcom,glymur-gpucc.h new file mode 100644 index 0000000000000..35f5abb848fd0 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-gpucc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GPU_SMMU_VOTE_CLK 12 +#define GPU_CC_GX_ACCU_SHIFT_CLK 13 +#define GPU_CC_GX_ACD_AHB_FF_CLK 14 +#define GPU_CC_GX_AHB_FF_CLK 15 +#define GPU_CC_GX_GMU_CLK 16 +#define GPU_CC_GX_RCG_AHB_FF_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_CB_BCR 0 +#define GPU_CC_CX_BCR 1 +#define GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_FF_BCR 3 +#define GPU_CC_GMU_BCR 4 +#define GPU_CC_GX_BCR 5 +#define GPU_CC_XO_BCR 6 + +#endif From 0d8f2d28b28c1025124c073f59e3e085f16bb763 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 30 Jan 2026 15:17:24 +0530 Subject: [PATCH 0419/1330] FROMLIST: clk: qcom: Add support for GPUCC and GXCLK for Glymur Support the graphics clock controller for Glymur for Graphics SW driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. Update the compatible for Graphics GX Clock Controller for Glymur as the GX clock controller is a reuse of the Kaanapali driver. Link: https://lore.kernel.org/all/20260127-glymur_gpucc-v1-2-547334c81ba2@oss.qualcomm.com/ Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-glymur.c | 619 ++++++++++++++++++++++++++ drivers/clk/qcom/gxclkctl-kaanapali.c | 1 + 4 files changed, 630 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-glymur.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 20af4340b08f9..c18434a06eb8c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -38,6 +38,15 @@ config CLK_GLYMUR_GCC Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. +config CLK_GLYMUR_GPUCC + tristate "GLYMUR Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_GLYMUR_GCC + help + Support for the graphics clock controller on GLYMUR devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config CLK_GLYMUR_TCSRCC tristate "GLYMUR TCSR Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a71dfd0ddf512..90ea21c3b7cf7 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o +obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) += videocc-glymur.o obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o diff --git a/drivers/clk/qcom/gpucc-glymur.c b/drivers/clk/qcom/gpucc-glymur.c new file mode 100644 index 0000000000000..6597ded955363 --- /dev/null +++ b/drivers/clk/qcom/gpucc-glymur.c @@ -0,0 +1,619 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_eko_t_vco[] = { + { 249600000, 2500000000, 0 }, +}; + +/* 1150.0 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x3b, + .alpha = 0xe555, + .config_ctl_val = 0x25c400e7, + .config_ctl_hi_val = 0x0a8060e0, + .config_ctl_hi1_val = 0xf51dea20, + .user_ctl_val = 0x00000408, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .config = &gpu_cc_pll0_config, + .vco_table = taycan_eko_t_vco, + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_gpu_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll0_out_even.clkr.hw }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src = { + .cmd_rcgr = 0x9474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_ff_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(575000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(700000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(725000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(750000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src = { + .reg = 0x9430, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x90bc, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x90bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk = { + .halt_reg = 0x9108, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9108, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_accu_shift_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk = { + .halt_reg = 0x90ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_ff_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x90d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x90e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk = { + .halt_reg = 0x9010, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_demet_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk = { + .halt_reg = 0x910c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x910c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_dpm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk = { + .halt_reg = 0x900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x900c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_freq_measure_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gpu_smmu_vote_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gpu_smmu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk = { + .halt_reg = 0x9070, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_accu_shift_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_acd_ahb_ff_clk = { + .halt_reg = 0x9068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_acd_ahb_ff_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_ahb_ff_clk = { + .halt_reg = 0x9064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_ahb_ff_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x9060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9060, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_rcg_ahb_ff_clk = { + .halt_reg = 0x906c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x906c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_rcg_ahb_ff_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93ec, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x93ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x90e8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x90f0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_rscc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_rscc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x90cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc = { + .gdscr = 0x9080, + .gds_hw_ctrl = 0x9094, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gpu_cc_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gpu_cc_glymur_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr, + [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GPU_SMMU_VOTE_CLK] = &gpu_cc_gpu_smmu_vote_clk.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_GX_ACD_AHB_FF_CLK] = &gpu_cc_gx_acd_ahb_ff_clk.clkr, + [GPU_CC_GX_AHB_FF_CLK] = &gpu_cc_gx_ahb_ff_clk.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_GX_RCG_AHB_FF_CLK] = &gpu_cc_gx_rcg_ahb_ff_clk.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr, + [GPU_CC_RSCC_HUB_AON_CLK] = &gpu_cc_rscc_hub_aon_clk.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, +}; + +static struct gdsc *gpu_cc_glymur_gdscs[] = { + [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_glymur_resets[] = { + [GPU_CC_CB_BCR] = { 0x93a0 }, + [GPU_CC_CX_BCR] = { 0x907c }, + [GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, + [GPU_CC_FF_BCR] = { 0x9470 }, + [GPU_CC_GMU_BCR] = { 0x9314 }, + [GPU_CC_GX_BCR] = { 0x905c }, + [GPU_CC_XO_BCR] = { 0x9000 }, +}; + +static struct clk_alpha_pll *gpu_cc_glymur_plls[] = { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_glymur_critical_cbcrs[] = { + 0x93a4, /* GPU_CC_CB_CLK */ + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ +}; + +static const struct regmap_config gpu_cc_glymur_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x95e8, + .fast_io = true, +}; + +static struct qcom_cc_driver_data gpu_cc_glymur_driver_data = { + .alpha_plls = gpu_cc_glymur_plls, + .num_alpha_plls = ARRAY_SIZE(gpu_cc_glymur_plls), + .clk_cbcrs = gpu_cc_glymur_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_glymur_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_glymur_desc = { + .config = &gpu_cc_glymur_regmap_config, + .clks = gpu_cc_glymur_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_glymur_clocks), + .resets = gpu_cc_glymur_resets, + .num_resets = ARRAY_SIZE(gpu_cc_glymur_resets), + .gdscs = gpu_cc_glymur_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_glymur_gdscs), + .use_rpm = true, + .driver_data = &gpu_cc_glymur_driver_data, +}; + +static const struct of_device_id gpu_cc_glymur_match_table[] = { + { .compatible = "qcom,glymur-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_glymur_match_table); + +static int gpu_cc_glymur_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_glymur_desc); +} + +static struct platform_driver gpu_cc_glymur_driver = { + .probe = gpu_cc_glymur_probe, + .driver = { + .name = "gpucc-glymur", + .of_match_table = gpu_cc_glymur_match_table, + }, +}; + +module_platform_driver(gpu_cc_glymur_driver); + +MODULE_DESCRIPTION("QTI GPUCC GLYMUR Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclkctl-kaanapali.c index c209ce5fe4f00..3ee512f34967f 100644 --- a/drivers/clk/qcom/gxclkctl-kaanapali.c +++ b/drivers/clk/qcom/gxclkctl-kaanapali.c @@ -52,6 +52,7 @@ static const struct qcom_cc_desc gx_clkctl_kaanapali_desc = { }; static const struct of_device_id gx_clkctl_kaanapali_match_table[] = { + { .compatible = "qcom,glymur-gxclkctl" }, { .compatible = "qcom,kaanapali-gxclkctl" }, { } }; From 38034f97e984294f73eea4dfaf183c4219265bee Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 28 Jan 2026 00:56:32 +0530 Subject: [PATCH 0420/1330] FROMLIST: dt-bindings: clock: qcom: Add X1P42100 video clock controller X1P42100 video clock controller has most clocks same as SM8650, but it also has few additional clocks and resets. Add device tree bindings for the video clock controller on Qualcomm X1P42100 platform by defining these additional clocks and resets on top of SM8650. Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-1-b23de57df5ba@oss.qualcomm.com --- .../bindings/clock/qcom,sm8450-videocc.yaml | 2 ++ .../dt-bindings/clock/qcom,x1p42100-videocc.h | 21 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,x1p42100-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 7bbf120d928cc..91538be4543c5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -32,6 +32,7 @@ properties: - qcom,sm8650-videocc - qcom,sm8750-videocc - qcom,x1e80100-videocc + - qcom,x1p42100-videocc clocks: items: @@ -70,6 +71,7 @@ allOf: - qcom,sm8450-videocc - qcom,sm8550-videocc - qcom,sm8750-videocc + - qcom,x1p42100-videocc then: required: - required-opps diff --git a/include/dt-bindings/clock/qcom,x1p42100-videocc.h b/include/dt-bindings/clock/qcom,x1p42100-videocc.h new file mode 100644 index 0000000000000..eb6c9b7264f8c --- /dev/null +++ b/include/dt-bindings/clock/qcom,x1p42100-videocc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H + +#include "qcom,sm8650-videocc.h" + +/* X1P42100 introduces below new clocks and resets compared to SM8650 */ + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_BSE_CLK 17 +#define VIDEO_CC_MVS0_BSE_CLK_SRC 18 +#define VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC 19 + +/* VIDEO_CC resets */ +#define VIDEO_CC_MVS0_BSE_BCR 8 + +#endif From f460b66cdc4dfba4fd222922438308bd38cdecdf Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 28 Jan 2026 00:56:33 +0530 Subject: [PATCH 0421/1330] FROMLIST: dt-bindings: clock: qcom: Add X1P42100 camera clock controller Add X1P42100 camera clock controller support and clock bindings for camera QDSS debug clocks which are applicable for both X1E80100 and X1P42100 platforms. Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-2-b23de57df5ba@oss.qualcomm.com Signed-off-by: Jagadeesh Kona Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,x1e80100-camcc.yaml | 1 + include/dt-bindings/clock/qcom,x1e80100-camcc.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml index 938a2f1ff3fca..b28614186cc09 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - qcom,x1e80100-camcc + - qcom,x1p42100-camcc reg: maxItems: 1 diff --git a/include/dt-bindings/clock/qcom,x1e80100-camcc.h b/include/dt-bindings/clock/qcom,x1e80100-camcc.h index d72fdfb06a7c7..06c316022fb0d 100644 --- a/include/dt-bindings/clock/qcom,x1e80100-camcc.h +++ b/include/dt-bindings/clock/qcom,x1e80100-camcc.h @@ -115,6 +115,9 @@ #define CAM_CC_SLEEP_CLK_SRC 105 #define CAM_CC_SLOW_AHB_CLK_SRC 106 #define CAM_CC_XO_CLK_SRC 107 +#define CAM_CC_QDSS_DEBUG_CLK 108 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 109 +#define CAM_CC_QDSS_DEBUG_XO_CLK 110 /* CAM_CC power domains */ #define CAM_CC_BPS_GDSC 0 From b07310ae3f03cb2bdbbf6c4f7002e64463c03740 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 28 Jan 2026 00:56:34 +0530 Subject: [PATCH 0422/1330] FROMLIST: clk: qcom: videocc-x1p42100: Add support for video clock controller Add support for the video clock controller for video clients to be able to request for videocc clocks on X1P42100 platform. Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-3-b23de57df5ba@oss.qualcomm.com Signed-off-by: Jagadeesh Kona Reviewed-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-x1p42100.c | 585 ++++++++++++++++++++++++++++ 3 files changed, 596 insertions(+) create mode 100644 drivers/clk/qcom/videocc-x1p42100.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index c18434a06eb8c..26570b18e94f4 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -173,6 +173,16 @@ config CLK_X1P42100_GPUCC Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config CLK_X1P42100_VIDEOCC + tristate "X1P42100 Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_X1E80100_GCC + help + Support for the video clock controller on Qualcomm Technologies, Inc. + X1P42100 devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config CLK_QCM2290_GPUCC tristate "QCM2290 Graphics Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 90ea21c3b7cf7..0b0b229fe61d0 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o obj-$(CONFIG_CLK_X1P42100_GPUCC) += gpucc-x1p42100.o +obj-$(CONFIG_CLK_X1P42100_VIDEOCC) += videocc-x1p42100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_5424) += apss-ipq5424.o diff --git a/drivers/clk/qcom/videocc-x1p42100.c b/drivers/clk/qcom/videocc-x1p42100.c new file mode 100644 index 0000000000000..2bb40ac6fcc57 --- /dev/null +++ b/drivers/clk/qcom/videocc-x1p42100.c @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, +}; + +enum { + P_BI_TCXO, + P_VIDEO_CC_PLL0_OUT_MAIN, + P_VIDEO_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + +/* 420.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config = { + .l = 0x15, + .alpha = 0xe000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll video_cc_pll0 = { + .offset = 0x0, + .config = &video_cc_pll0_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1050.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll1_config = { + .l = 0x36, + .alpha = 0xb000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll video_cc_pll1 = { + .offset = 0x1000, + .config = &video_cc_pll1_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map video_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_cc_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_bse_clk_src[] = { + F(420000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(670000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(848000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(920000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_bse_clk_src = { + .cmd_rcgr = 0x8154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_1, + .freq_tbl = ftbl_video_cc_mvs0_bse_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_bse_clk_src", + .parent_data = video_cc_parent_data_1, + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { + F(210000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(300000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(335000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(424000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(460000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src = { + .cmd_rcgr = 0x8000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_1, + .freq_tbl = ftbl_video_cc_mvs0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk_src", + .parent_data = video_cc_parent_data_1, + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { + F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs1_clk_src = { + .cmd_rcgr = 0x8018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_2, + .freq_tbl = ftbl_video_cc_mvs1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk_src", + .parent_data = video_cc_parent_data_2, + .num_parents = ARRAY_SIZE(video_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_xo_clk_src = { + .cmd_rcgr = 0x810c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_0, + .freq_tbl = ftbl_video_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_xo_clk_src", + .parent_data = video_cc_parent_data_0, + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_bse_div4_div_clk_src = { + .reg = 0x817c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_bse_div4_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_bse_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src = { + .reg = 0x80ec, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { + .reg = 0x809c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_bse_clk = { + .halt_reg = 0x8170, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8170, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_bse_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_bse_div4_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_clk = { + .halt_reg = 0x80b8, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x80b8, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk = { + .halt_reg = 0x8128, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x8128, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk = { + .halt_reg = 0x8064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk = { + .halt_reg = 0x812c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x812c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk = { + .halt_reg = 0x80e0, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x80e0, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_shift_clk = { + .halt_reg = 0x8130, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x8130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_clk = { + .halt_reg = 0x8090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_shift_clk = { + .halt_reg = 0x8134, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x8134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc = { + .gdscr = 0x804c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs0c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc = { + .gdscr = 0x80a4, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &video_cc_mvs0c_gdsc.pd, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs1c_gdsc = { + .gdscr = 0x8078, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "video_cc_mvs1c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs1_gdsc = { + .gdscr = 0x80cc, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "video_cc_mvs1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &video_cc_mvs1c_gdsc.pd, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *video_cc_x1p42100_clocks[] = { + [VIDEO_CC_MVS0_BSE_CLK] = &video_cc_mvs0_bse_clk.clkr, + [VIDEO_CC_MVS0_BSE_CLK_SRC] = &video_cc_mvs0_bse_clk_src.clkr, + [VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC] = &video_cc_mvs0_bse_div4_div_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr, + [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, + [VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr, + [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, + [VIDEO_CC_PLL1] = &video_cc_pll1.clkr, + [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_x1p42100_gdscs[] = { + [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, + [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, + [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc, +}; + +static const struct qcom_reset_map video_cc_x1p42100_resets[] = { + [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 }, + [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 }, + [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, + [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 }, + [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, + [VIDEO_CC_MVS0_BSE_BCR] = { 0x816c }, + [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 }, + [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 }, + [VIDEO_CC_XO_CLK_ARES] = { 0x8124, 2 }, +}; + +static struct clk_alpha_pll *video_cc_x1p42100_plls[] = { + &video_cc_pll0, + &video_cc_pll1, +}; + +static u32 video_cc_x1p42100_critical_cbcrs[] = { + 0x80f4, /* VIDEO_CC_AHB_CLK */ + 0x8150, /* VIDEO_CC_SLEEP_CLK */ + 0x8124, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_x1p42100_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9f54, + .fast_io = true, +}; + +static struct qcom_cc_driver_data video_cc_x1p42100_driver_data = { + .alpha_plls = video_cc_x1p42100_plls, + .num_alpha_plls = ARRAY_SIZE(video_cc_x1p42100_plls), + .clk_cbcrs = video_cc_x1p42100_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(video_cc_x1p42100_critical_cbcrs), +}; + +static const struct qcom_cc_desc video_cc_x1p42100_desc = { + .config = &video_cc_x1p42100_regmap_config, + .clks = video_cc_x1p42100_clocks, + .num_clks = ARRAY_SIZE(video_cc_x1p42100_clocks), + .resets = video_cc_x1p42100_resets, + .num_resets = ARRAY_SIZE(video_cc_x1p42100_resets), + .gdscs = video_cc_x1p42100_gdscs, + .num_gdscs = ARRAY_SIZE(video_cc_x1p42100_gdscs), + .use_rpm = true, + .driver_data = &video_cc_x1p42100_driver_data, +}; + +static const struct of_device_id video_cc_x1p42100_match_table[] = { + { .compatible = "qcom,x1p42100-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_x1p42100_match_table); + +static int video_cc_x1p42100_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_x1p42100_desc); +} + +static struct platform_driver video_cc_x1p42100_driver = { + .probe = video_cc_x1p42100_probe, + .driver = { + .name = "videocc-x1p42100", + .of_match_table = video_cc_x1p42100_match_table, + }, +}; + +module_platform_driver(video_cc_x1p42100_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC X1P42100 Driver"); +MODULE_LICENSE("GPL"); From 6db48f34955694a809bce46591b08b4d32eebde1 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 28 Jan 2026 00:56:35 +0530 Subject: [PATCH 0423/1330] FROMLIST: clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks Add support for camera QDSS debug clocks on X1E80100 platform. Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-4-b23de57df5ba@oss.qualcomm.com Signed-off-by: Jagadeesh Kona Fixes: 76126a5129b5 ("clk: qcom: Add camcc clock driver for x1e80100") Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- drivers/clk/qcom/camcc-x1e80100.c | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e80100.c index cbcc1c9fcb341..7e3fc7aee854e 100644 --- a/drivers/clk/qcom/camcc-x1e80100.c +++ b/drivers/clk/qcom/camcc-x1e80100.c @@ -1052,6 +1052,31 @@ static struct clk_rcg2 cam_cc_mclk7_clk_src = { }, }; +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_CAM_CC_PLL8_OUT_EVEN, 8, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { + .cmd_rcgr = 0x13938, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { F(345600000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), @@ -2182,6 +2207,42 @@ static struct clk_branch cam_cc_mclk7_clk = { }, }; +static struct clk_branch cam_cc_qdss_debug_clk = { + .halt_reg = 0x13a64, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13a64, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk = { + .halt_reg = 0x13a68, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13a68, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch cam_cc_sfe_0_clk = { .halt_reg = 0x133c0, .halt_check = BRANCH_HALT, @@ -2398,6 +2459,9 @@ static struct clk_regmap *cam_cc_x1e80100_clocks[] = { [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, [CAM_CC_PLL8] = &cam_cc_pll8.clkr, [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, From 4de5deec38c7054eb5082365975ceaefca658942 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 28 Jan 2026 00:56:36 +0530 Subject: [PATCH 0424/1330] FROMLIST: clk: qcom: camcc-x1p42100: Add support for camera clock controller Add support for the camera clock controller for camera clients to be able to request for camcc clocks on X1P42100 platform. Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-5-b23de57df5ba@oss.qualcomm.com Signed-off-by: Jagadeesh Kona Reviewed-by: Konrad Dybcio Reviewed-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-x1p42100.c | 2223 +++++++++++++++++++++++++++++ 3 files changed, 2234 insertions(+) create mode 100644 drivers/clk/qcom/camcc-x1p42100.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 26570b18e94f4..98bb8fb57709b 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -164,6 +164,16 @@ config CLK_X1E80100_TCSRCC Support for the TCSR clock controller on X1E80100 devices. Say Y if you want to use peripheral devices such as SD/UFS. +config CLK_X1P42100_CAMCC + tristate "X1P42100 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_X1E80100_GCC + help + Support for the camera clock controller on Qualcomm Technologies, Inc. + X1P42100 devices. + Say Y if you want to support camera devices and camera functionality + such as capturing pictures. + config CLK_X1P42100_GPUCC tristate "X1P42100 Graphics Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 0b0b229fe61d0..2a08ef4840828 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o +obj-$(CONFIG_CLK_X1P42100_CAMCC) += camcc-x1p42100.o obj-$(CONFIG_CLK_X1P42100_GPUCC) += gpucc-x1p42100.o obj-$(CONFIG_CLK_X1P42100_VIDEOCC) += videocc-x1p42100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o diff --git a/drivers/clk/qcom/camcc-x1p42100.c b/drivers/clk/qcom/camcc-x1p42100.c new file mode 100644 index 0000000000000..c1a61c2679199 --- /dev/null +++ b/drivers/clk/qcom/camcc-x1p42100.c @@ -0,0 +1,2223 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL2_OUT_MAIN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco rivian_ole_vco[] = { + { 777000000, 1285000000, 0 }, +}; + +/* 1200.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll0 = { + .offset = 0x0, + .config = &cam_cc_pll0_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { + .offset = 0x0, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll0_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 728.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll1_config = { + .l = 0x25, + .alpha = 0xeaaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll1 = { + .offset = 0x1000, + .config = &cam_cc_pll1_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { + .offset = 0x1000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll1_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll2_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x10000030, + .config_ctl_hi_val = 0x80890263, + .config_ctl_hi1_val = 0x00000217, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00100000, +}; + +static struct clk_alpha_pll cam_cc_pll2 = { + .offset = 0x2000, + .config = &cam_cc_pll2_config, + .vco_table = rivian_ole_vco, + .num_vco = ARRAY_SIZE(rivian_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_rivian_evo_ops, + }, + }, +}; + +/* 864.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll3_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll3 = { + .offset = 0x3000, + .config = &cam_cc_pll3_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { + .offset = 0x3000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll6_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll6 = { + .offset = 0x6000, + .config = &cam_cc_pll6_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { + .offset = 0x6000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll6_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL6_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, + { .hw = &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll2.clkr.hw }, + { .hw = &cam_cc_pll2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_bps_clk_src = { + .cmd_rcgr = 0x10278, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { + .cmd_rcgr = 0x138f8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src = { + .cmd_rcgr = 0x1365c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src = { + .cmd_rcgr = 0x1378c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { + .cmd_rcgr = 0x11164, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cphy_rx_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x150e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x15104, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { + .cmd_rcgr = 0x15124, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { + .cmd_rcgr = 0x15258, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { + .cmd_rcgr = 0x1538c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { + .cmd_rcgr = 0x154c0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csid_clk_src = { + .cmd_rcgr = 0x138d4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { + .cmd_rcgr = 0x10018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_fast_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_clk_src = { + .cmd_rcgr = 0x13520, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_icp_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src = { + .cmd_rcgr = 0x11018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { + .cmd_rcgr = 0x13000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0x1313c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { + F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { + .cmd_rcgr = 0x103cc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src = { + .cmd_rcgr = 0x133dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_jpeg_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), + F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src = { + .cmd_rcgr = 0x15000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src = { + .cmd_rcgr = 0x1501c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src = { + .cmd_rcgr = 0x15038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src = { + .cmd_rcgr = 0x15054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk4_clk_src = { + .cmd_rcgr = 0x15070, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk5_clk_src = { + .cmd_rcgr = 0x1508c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk6_clk_src = { + .cmd_rcgr = 0x150a8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk7_clk_src = { + .cmd_rcgr = 0x150c4, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { + .cmd_rcgr = 0x13938, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src = { + .cmd_rcgr = 0x13aa0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_4, + .freq_tbl = ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sleep_clk_src", + .parent_data = cam_cc_parent_data_4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { + .cmd_rcgr = 0x10148, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_slow_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src = { + .cmd_rcgr = 0x13a84, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_5, + .freq_tbl = ftbl_cam_cc_xo_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_xo_clk_src", + .parent_data = cam_cc_parent_data_5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_cc_bps_ahb_clk = { + .halt_reg = 0x10274, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10274, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_clk = { + .halt_reg = 0x103a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x103a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_fast_ahb_clk = { + .halt_reg = 0x10144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { + .halt_reg = 0x13920, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x13920, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x13920, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_nrt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_rt_clk = { + .halt_reg = 0x13910, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13910, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { + .halt_reg = 0x1392c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1392c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_dcd_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_xo_clk = { + .halt_reg = 0x13930, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13930, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk = { + .halt_reg = 0x13788, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13788, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk = { + .halt_reg = 0x138b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x138b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk = { + .halt_reg = 0x13a80, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x13a80, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_core_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk = { + .halt_reg = 0x138bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x138bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_bps_clk = { + .halt_reg = 0x103b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x103b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_fast_ahb_clk = { + .halt_reg = 0x138c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x138c8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_0_clk = { + .halt_reg = 0x11150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_lite_clk = { + .halt_reg = 0x13138, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13138, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ipe_nps_clk = { + .halt_reg = 0x10504, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10504, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk = { + .halt_reg = 0x150f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk = { + .halt_reg = 0x1511c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1511c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk = { + .halt_reg = 0x15250, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15250, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk = { + .halt_reg = 0x15384, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15384, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk = { + .halt_reg = 0x154b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x154b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk = { + .halt_reg = 0x155ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x155ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi5phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk = { + .halt_reg = 0x138ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x138ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_csiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk = { + .halt_reg = 0x150fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk = { + .halt_reg = 0x15120, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk = { + .halt_reg = 0x15254, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15254, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk = { + .halt_reg = 0x15388, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15388, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk = { + .halt_reg = 0x154bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x154bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk = { + .halt_reg = 0x155f0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x155f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_ahb_clk = { + .halt_reg = 0x13658, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13658, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk = { + .halt_reg = 0x1364c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1364c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_icp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk = { + .halt_reg = 0x11144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_dsp_clk = { + .halt_reg = 0x11154, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11154, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_dsp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { + .halt_reg = 0x11160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk = { + .halt_reg = 0x13278, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13278, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk = { + .halt_reg = 0x1312c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1312c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { + .halt_reg = 0x13274, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13274, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk = { + .halt_reg = 0x13268, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13268, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk = { + .halt_reg = 0x1051c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1051c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk = { + .halt_reg = 0x104f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x104f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { + .halt_reg = 0x10520, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10520, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk = { + .halt_reg = 0x10508, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10508, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { + .halt_reg = 0x10524, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10524, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk = { + .halt_reg = 0x13508, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13508, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk = { + .halt_reg = 0x15018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk = { + .halt_reg = 0x15034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk = { + .halt_reg = 0x15050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk = { + .halt_reg = 0x1506c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1506c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk4_clk = { + .halt_reg = 0x15088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk5_clk = { + .halt_reg = 0x150a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk6_clk = { + .halt_reg = 0x150c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk7_clk = { + .halt_reg = 0x150dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk = { + .halt_reg = 0x13a64, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13a64, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk = { + .halt_reg = 0x13a68, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13a68, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc = { + .gdscr = 0x13a6c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_titan_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_bps_gdsc = { + .gdscr = 0x10004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_bps_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_0_gdsc = { + .gdscr = 0x11004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc = { + .gdscr = 0x103b8, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ipe_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_x1p42100_clocks[] = { + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, + [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, + [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, + [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, + [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, + [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, + [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, + [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, + [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, + [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL6] = &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_x1p42100_gdscs[] = { + [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, + [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, + [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, + [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, +}; + +static const struct qcom_reset_map cam_cc_x1p42100_resets[] = { + [CAM_CC_BPS_BCR] = { 0x10000 }, + [CAM_CC_ICP_BCR] = { 0x1351c }, + [CAM_CC_IFE_0_BCR] = { 0x11000 }, + [CAM_CC_IPE_0_BCR] = { 0x103b4 }, +}; + +static struct clk_alpha_pll *cam_cc_x1p42100_plls[] = { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll6, +}; + +static u32 cam_cc_x1p42100_critical_cbcrs[] = { + 0x13a9c, /* CAM_CC_GDSC_CLK */ + 0x13ab8, /* CAM_CC_SLEEP_CLK */ +}; + +static const struct regmap_config cam_cc_x1p42100_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1603c, + .fast_io = true, +}; + +static struct qcom_cc_driver_data cam_cc_x1p42100_driver_data = { + .alpha_plls = cam_cc_x1p42100_plls, + .num_alpha_plls = ARRAY_SIZE(cam_cc_x1p42100_plls), + .clk_cbcrs = cam_cc_x1p42100_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(cam_cc_x1p42100_critical_cbcrs), +}; + +static struct qcom_cc_desc cam_cc_x1p42100_desc = { + .config = &cam_cc_x1p42100_regmap_config, + .clks = cam_cc_x1p42100_clocks, + .num_clks = ARRAY_SIZE(cam_cc_x1p42100_clocks), + .resets = cam_cc_x1p42100_resets, + .num_resets = ARRAY_SIZE(cam_cc_x1p42100_resets), + .gdscs = cam_cc_x1p42100_gdscs, + .num_gdscs = ARRAY_SIZE(cam_cc_x1p42100_gdscs), + .use_rpm = true, + .driver_data = &cam_cc_x1p42100_driver_data, +}; + +static const struct of_device_id cam_cc_x1p42100_match_table[] = { + { .compatible = "qcom,x1p42100-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_x1p42100_match_table); + +static int cam_cc_x1p42100_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_cc_x1p42100_desc); +} + +static struct platform_driver cam_cc_x1p42100_driver = { + .probe = cam_cc_x1p42100_probe, + .driver = { + .name = "camcc-x1p42100", + .of_match_table = cam_cc_x1p42100_match_table, + }, +}; + +module_platform_driver(cam_cc_x1p42100_driver); + +MODULE_DESCRIPTION("QTI CAMCC X1P42100 Driver"); +MODULE_LICENSE("GPL"); From e36a3ee310ebce0775340df4069cf18d52404917 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 20 Feb 2026 11:24:20 +0530 Subject: [PATCH 0425/1330] FROMLIST: dt-bindings: clock: qcom: Add SM8750 GPU clocks The SM8750 features a "traditional" GPU_CC block, much of which is controlled through the GMU microcontroller. Additionally, there's an separate GX_CC block, where the GX GDSC is moved. Update the bindings to accommodate for SM8750 SoC. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260220-gpucc_sm8750_v2-v3-1-6c5408564c3c@oss.qualcomm.com Signed-off-by: Taniya Das --- .../clock/qcom,kaanapali-gxclkctl.yaml | 1 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + include/dt-bindings/clock/qcom,sm8750-gpucc.h | 50 +++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sm8750-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml index 55bf3f8110171..466c884aa2bab 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -22,6 +22,7 @@ properties: enum: - qcom,glymur-gxclkctl - qcom,kaanapali-gxclkctl + - qcom,sm8750-gxclkctl power-domains: description: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 5993804c91fa5..be202ab4f3fcc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -23,6 +23,7 @@ description: | include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h + include/dt-bindings/reset/qcom,sm8750-gpucc.h include/dt-bindings/reset/qcom,x1e80100-gpucc.h properties: @@ -37,6 +38,7 @@ properties: - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc + - qcom,sm8750-gpucc - qcom,x1e80100-gpucc - qcom,x1p42100-gpucc diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bindings/clock/qcom,sm8750-gpucc.h new file mode 100644 index 0000000000000..e2143d905fece --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_ACD_AHB_FF_CLK 13 +#define GPU_CC_GX_AHB_FF_CLK 14 +#define GPU_CC_GX_GMU_CLK 15 +#define GPU_CC_GX_RCG_AHB_FF_CLK 16 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_GPU_CC_CB_BCR 0 +#define GPU_CC_GPU_CC_CX_BCR 1 +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GPU_CC_FF_BCR 3 +#define GPU_CC_GPU_CC_GMU_BCR 4 +#define GPU_CC_GPU_CC_GX_BCR 5 +#define GPU_CC_GPU_CC_XO_BCR 6 + +#endif From 416ee4c187f8d8d0fd618982df30084ccdc6a44c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 20 Feb 2026 11:24:21 +0530 Subject: [PATCH 0426/1330] FROMLIST: clk: qcom: Add a driver for SM8750 GPU clocks Support the graphics clock controller for SM8750 for Graphics SW driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. Update the compatible for Graphics GX Clock Controller for SM8750 as the GX clock controller is a reuse of the Kaanapali driver. Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Link: https://lore.kernel.org/r/20260220-gpucc_sm8750_v2-v3-2-6c5408564c3c@oss.qualcomm.com Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8750.c | 472 ++++++++++++++++++++++++++ drivers/clk/qcom/gxclkctl-kaanapali.c | 1 + 4 files changed, 483 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm8750.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 98bb8fb57709b..99ef623a3c936 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1519,6 +1519,15 @@ config SM_GPUCC_8650 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_8750 + tristate "SM8750 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8750 + help + Support for the graphics clock controller on SM8750 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_LPASSCC_6115 tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 2a08ef4840828..4eb79dec0ddc8 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -184,6 +184,7 @@ obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o +obj-$(CONFIG_SM_GPUCC_8750) += gpucc-sm8750.o gxclkctl-kaanapali.o obj-$(CONFIG_SM_GPUCC_MILOS) += gpucc-milos.o obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o diff --git a/drivers/clk/qcom/gpucc-sm8750.c b/drivers/clk/qcom/gpucc-sm8750.c new file mode 100644 index 0000000000000..2983683e6fbb0 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8750.c @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_elu_vco[] = { + { 249600000, 2500000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x34, + .alpha = 0x1555, + .config_ctl_val = 0x19660387, + .config_ctl_hi_val = 0x098060a0, + .config_ctl_hi1_val = 0xb416cb20, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .config = &gpu_cc_pll0_config, + .vco_table = taycan_elu_vco, + .num_vco = ARRAY_SIZE(taycan_elu_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_elu_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_gpu_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll0_out_even.clkr.hw }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .fw_name = "gpll0_out_main" }, + { .fw_name = "gpll0_out_main_div" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(687500000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93ec, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src = { + .reg = 0x942c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x90bc, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x90bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk = { + .halt_reg = 0x910c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x910c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_accu_shift_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x90d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x90e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk = { + .halt_reg = 0x9010, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_demet_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk = { + .halt_reg = 0x9110, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9110, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_dpm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk = { + .halt_reg = 0x900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x900c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_freq_measure_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk = { + .halt_reg = 0x9070, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_accu_shift_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x9060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9060, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x90e8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x90f4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90f4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc = { + .gdscr = 0x9080, + .gds_hw_ctrl = 0x9094, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x8, + .pd = { + .name = "gpu_cc_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm8750_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr, +}; + +static struct gdsc *gpu_cc_sm8750_gdscs[] = { + [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sm8750_resets[] = { + [GPU_CC_GPU_CC_XO_BCR] = { 0x9000 }, + [GPU_CC_GPU_CC_GX_BCR] = { 0x905c }, + [GPU_CC_GPU_CC_CX_BCR] = { 0x907c }, + [GPU_CC_GPU_CC_GMU_BCR] = { 0x9314 }, + [GPU_CC_GPU_CC_CB_BCR] = { 0x93a0 }, + [GPU_CC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, +}; + +static const struct regmap_config gpu_cc_sm8750_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9800, + .fast_io = true, +}; + +static struct clk_alpha_pll *gpu_cc_alpha_plls[] = { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_sm8750_critical_cbcrs[] = { + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x9064, /* GPU_CC_GX_AHB_FF_CLK */ + 0x90cc, /* GPU_CC_SLEEP_CLK */ + 0x93a4, /* GPU_CC_CB_CLK */ + 0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */ +}; + +static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = { + .alpha_plls = gpu_cc_alpha_plls, + .num_alpha_plls = ARRAY_SIZE(gpu_cc_alpha_plls), + .clk_cbcrs = gpu_cc_sm8750_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_sm8750_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_sm8750_desc = { + .config = &gpu_cc_sm8750_regmap_config, + .clks = gpu_cc_sm8750_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm8750_clocks), + .resets = gpu_cc_sm8750_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm8750_resets), + .gdscs = gpu_cc_sm8750_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8750_gdscs), + .driver_data = &gpu_cc_sm8750_driver_data, +}; + +static const struct of_device_id gpu_cc_sm8750_match_table[] = { + { .compatible = "qcom,sm8750-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8750_match_table); + +static int gpu_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_sm8750_desc); +} + +static struct platform_driver gpu_cc_sm8750_driver = { + .probe = gpu_cc_sm8750_probe, + .driver = { + .name = "sm8750-gpucc", + .of_match_table = gpu_cc_sm8750_match_table, + }, +}; +module_platform_driver(gpu_cc_sm8750_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM8750 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclkctl-kaanapali.c index 3ee512f34967f..b45ab0ac46c77 100644 --- a/drivers/clk/qcom/gxclkctl-kaanapali.c +++ b/drivers/clk/qcom/gxclkctl-kaanapali.c @@ -54,6 +54,7 @@ static const struct qcom_cc_desc gx_clkctl_kaanapali_desc = { static const struct of_device_id gx_clkctl_kaanapali_match_table[] = { { .compatible = "qcom,glymur-gxclkctl" }, { .compatible = "qcom,kaanapali-gxclkctl" }, + { .compatible = "qcom,sm8750-gxclkctl" }, { } }; MODULE_DEVICE_TABLE(of, gx_clkctl_kaanapali_match_table); From 9edc8bc34f99bad108c47a3ab44860957c88d719 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Fri, 6 Mar 2026 15:25:18 +0530 Subject: [PATCH 0427/1330] dt-bindings: power: qcom,rpmpd: document the Shikra RPM Power Domains Document the RPM Power Domains on the Shikra Platform. Signed-off-by: Rakesh Kota --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 27af5b8aa1340..5511d38e2d871 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -53,6 +53,7 @@ properties: - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd - qcom,sdx75-rpmhpd + - qcom,shikra-rpmpd - qcom,sm4450-rpmhpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd From 3f1b7e399012113e8e14cef2b1967db6cbffd56d Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Fri, 6 Mar 2026 15:53:10 +0530 Subject: [PATCH 0428/1330] soc: qcom: rpmpd: Add Shikra RPM support Shikra has the same RPM power domains as QCM2290. Add shikra support by reusing QCM2290 power domains. Signed-off-by: Rakesh Kota --- drivers/pmdomain/qcom/rpmpd.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index 98ab4f9ea9bff..f30403e629eff 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -863,6 +863,21 @@ static const struct rpmpd_desc sdm660_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; +static struct rpmpd *shikra_rpmpds[] = { + [RPMPD_VDDCX] = &cx_rwcx0_lvl, + [RPMPD_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [RPMPD_VDDCX_VFL] = &cx_rwcx0_vfl, + [RPMPD_VDDMX] = &mx_rwmx0_lvl, + [RPMPD_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [RPMPD_VDDMX_VFL] = &mx_rwmx0_vfl, +}; + +static const struct rpmpd_desc shikra_desc = { + .rpmpds = shikra_rpmpds, + .num_pds = ARRAY_SIZE(shikra_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, +}; + static struct rpmpd *sm6115_rpmpds[] = { [SM6115_VDDCX] = &cx_rwcx0_lvl, [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, From 416c2dab2680ff2d05bc21b272f21ab24219226f Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 11 Mar 2026 18:05:55 +0530 Subject: [PATCH 0429/1330] dt-bindings: regulator: qcom,smd-rpm-regulator: Document PM8150 IC Document the pm8150 compatible string and available regulators in the QCOM SMD RPM regulator documentation. Signed-off-by: Rakesh Kota --- .../devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml index b7241ce975b96..c00d481bcc079 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -35,6 +35,9 @@ description: For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob + For pm8150, s1, s2, s3, s4, s5, s6, s7, s8, s9,s10, l1, l2, l3, l4, l5, l6, + l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18 + For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1 @@ -91,6 +94,7 @@ properties: - qcom,rpm-pm6125-regulators - qcom,rpm-pm660-regulators - qcom,rpm-pm660l-regulators + - qcom,rpm-pm8150-regulators - qcom,rpm-pm8226-regulators - qcom,rpm-pm8841-regulators - qcom,rpm-pm8909-regulators From 45025e1dbd053196317a86fbee6904c16b528482 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 11 Mar 2026 17:02:20 +0530 Subject: [PATCH 0430/1330] regulator: qcom_smd: Add PM8150 regulators The PM8150 is found on boards with shikra SoCs and It provides 10 SMPS and 18 LDO regulators. Signed-off-by: Rakesh Kota --- drivers/regulator/qcom_smd-regulator.c | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c index 25ed9f713974b..03ec2bdc27a37 100644 --- a/drivers/regulator/qcom_smd-regulator.c +++ b/drivers/regulator/qcom_smd-regulator.c @@ -913,6 +913,38 @@ static const struct rpm_regulator_data rpm_pm660l_regulators[] = { { } }; +static const struct rpm_regulator_data rpm_pm8150_regulators[] = { + { "s1", QCOM_SMD_RPM_SMPA, 1, &pmic5_ftsmps520, "vdd_s1" }, + { "s2", QCOM_SMD_RPM_SMPA, 2, &pmic5_ftsmps520, "vdd_s2" }, + { "s3", QCOM_SMD_RPM_SMPA, 3, &pmic5_ftsmps520, "vdd_s3" }, + { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" }, + { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" }, + { "s6", QCOM_SMD_RPM_SMPA, 6, &pmic5_ftsmps520, "vdd_s6" }, + { "s7", QCOM_SMD_RPM_SMPA, 7, &pmic5_ftsmps520, "vdd_s7" }, + { "s8", QCOM_SMD_RPM_SMPA, 8, &pmic5_ftsmps520, "vdd_s8" }, + { "s9", QCOM_SMD_RPM_SMPA, 9, &pmic5_ftsmps520, "vdd_s9" }, + { "s10", QCOM_SMD_RPM_SMPA, 10, &pmic5_ftsmps520, "vdd_s10" }, + { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l8_l11" }, + { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_pldo660, "vdd_l2_l10" }, + { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l3_l4_l5_l18" }, + { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_nldo660, "vdd_l3_l4_l5_l18" }, + { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l3_l4_l5_l18" }, + { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l6_l9" }, + { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_pldo660, "vdd_l7_l12_l14_l15" }, + { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l1_l8_l11" }, + { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_nldo660, "vdd_l6_l9" }, + { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_pldo660, "vdd_l2_l10" }, + { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_nldo660, "vdd_l1_l8_l11" }, + { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l7_l12_l14_l15" }, + { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_pldo660, "vdd_l13_l16_l17" }, + { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l7_l12_l14_l15" }, + { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_ht_lvpldo, "vdd_l7_l12_l14_l15" }, + { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l13_l16_l17" }, + { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l13_l16_l17" }, + { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_nldo660, "vdd_l3_l4_l5_l18" }, + { } +}; + static const struct rpm_regulator_data rpm_pm8226_regulators[] = { { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8226_hfsmps, "vdd_s1" }, { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8226_ftsmps, "vdd_s2" }, @@ -1358,6 +1390,7 @@ static const struct of_device_id rpm_of_match[] = { { .compatible = "qcom,rpm-pm6125-regulators", .data = &rpm_pm6125_regulators }, { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators }, { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators }, + { .compatible = "qcom,rpm-pm8150-regulators", .data = &rpm_pm8150_regulators }, { .compatible = "qcom,rpm-pm8226-regulators", .data = &rpm_pm8226_regulators }, { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, { .compatible = "qcom,rpm-pm8909-regulators", .data = &rpm_pm8909_regulators }, From f67bcdfba66c9b3a99063cb215267212fa3bcee2 Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Wed, 10 Dec 2025 12:21:55 +0530 Subject: [PATCH 0431/1330] FROMLIST: ASoC: qcom: q6dsp-lpass-ports: Extend q6dsp-lpass-ports driver to support additional sampling rates Expand the existing constraints in the q6dsp-lpass-ports driver to allow a wider range of sampling rates, from 8000 Hz to 192000 Hz. This change improves compatibility with diverse audio hardware and provides greater flexibility for audio stream configurations. Link: https://lore.kernel.org/linux-sound/20251210065157.2775514-2-ravi.hothi@oss.qualcomm.com/ Signed-off-by: Ravi Hothi --- sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 73 +++++++++--------------- 1 file changed, 27 insertions(+), 46 deletions(-) diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c index 4eed54b071a5c..76421adb5afa2 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -10,16 +10,14 @@ #define Q6AFE_TDM_PB_DAI(pre, num, did) { \ .playback = { \ .stream_name = pre" TDM"#num" Playback", \ - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ - SNDRV_PCM_RATE_176400, \ + .rates = SNDRV_PCM_RATE_8000_192000, \ .formats = SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S24_LE | \ SNDRV_PCM_FMTBIT_S32_LE, \ .channels_min = 1, \ .channels_max = 8, \ .rate_min = 8000, \ - .rate_max = 176400, \ + .rate_max = 192000, \ }, \ .name = #did, \ .id = did, \ @@ -28,16 +26,14 @@ #define Q6AFE_TDM_CAP_DAI(pre, num, did) { \ .capture = { \ .stream_name = pre" TDM"#num" Capture", \ - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ - SNDRV_PCM_RATE_176400, \ + .rates = SNDRV_PCM_RATE_8000_192000, \ .formats = SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S24_LE | \ SNDRV_PCM_FMTBIT_S32_LE, \ .channels_min = 1, \ .channels_max = 8, \ .rate_min = 8000, \ - .rate_max = 176400, \ + .rate_max = 192000, \ }, \ .name = #did, \ .id = did, \ @@ -46,16 +42,14 @@ #define Q6AFE_CDC_DMA_RX_DAI(did) { \ .playback = { \ .stream_name = #did" Playback", \ - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ - SNDRV_PCM_RATE_176400, \ + .rates = SNDRV_PCM_RATE_8000_192000, \ .formats = SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S24_LE | \ SNDRV_PCM_FMTBIT_S32_LE, \ .channels_min = 1, \ .channels_max = 8, \ .rate_min = 8000, \ - .rate_max = 176400, \ + .rate_max = 192000, \ }, \ .name = #did, \ .id = did, \ @@ -64,16 +58,14 @@ #define Q6AFE_CDC_DMA_TX_DAI(did) { \ .capture = { \ .stream_name = #did" Capture", \ - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ - SNDRV_PCM_RATE_176400, \ + .rates = SNDRV_PCM_RATE_8000_192000, \ .formats = SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S24_LE | \ SNDRV_PCM_FMTBIT_S32_LE, \ .channels_min = 1, \ .channels_max = 8, \ .rate_min = 8000, \ - .rate_max = 176400, \ + .rate_max = 192000, \ }, \ .name = #did, \ .id = did, \ @@ -350,118 +342,108 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { }, { .playback = { .stream_name = "Primary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .id = PRIMARY_MI2S_RX, .name = "PRI_MI2S_RX", }, { .capture = { .stream_name = "Primary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .id = PRIMARY_MI2S_TX, .name = "PRI_MI2S_TX", }, { .playback = { .stream_name = "Secondary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .name = "SEC_MI2S_RX", .id = SECONDARY_MI2S_RX, }, { .capture = { .stream_name = "Secondary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .id = SECONDARY_MI2S_TX, .name = "SEC_MI2S_TX", }, { .playback = { .stream_name = "Tertiary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .name = "TERT_MI2S_RX", .id = TERTIARY_MI2S_RX, }, { .capture = { .stream_name = "Tertiary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .id = TERTIARY_MI2S_TX, .name = "TERT_MI2S_TX", }, { .playback = { .stream_name = "Quaternary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .name = "QUAT_MI2S_RX", .id = QUATERNARY_MI2S_RX, }, { .capture = { .stream_name = "Quaternary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .id = QUATERNARY_MI2S_TX, .name = "QUAT_MI2S_TX", }, { .playback = { .stream_name = "Quinary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE, .channels_min = 1, .channels_max = 8, @@ -473,13 +455,12 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { }, { .capture = { .stream_name = "Quinary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, + .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, - .rate_max = 48000, + .rate_max = 192000, }, .id = QUINARY_MI2S_TX, .name = "QUIN_MI2S_TX", From d24d3285553c9fc979d7b046527e4ab62844a3bd Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Wed, 10 Dec 2025 12:21:56 +0530 Subject: [PATCH 0432/1330] FROMLIST: ASoC: qcom: q6dsp-lpass-ports: Update constraints to support 32-bit PCM format Expand the existing constraints by introducing support for the 32-bit PCM format (SNDRV_PCM_FMTBIT_S32_LE) alongside the existing 16-bit and 24-bit formats. This enhancement enables handling of high-resolution audio streams and improves audio quality for supported hardware. Link: https://lore.kernel.org/linux-sound/20251210065157.2775514-2-ravi.hothi@oss.qualcomm.com/ Signed-off-by: Ravi Hothi --- sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 35 +++++++++++++++++------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c index 76421adb5afa2..8542e620ee02d 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -344,7 +344,8 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .stream_name = "Primary MI2S Playback", .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -357,7 +358,8 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .stream_name = "Primary MI2S Capture", .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -369,7 +371,9 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .playback = { .stream_name = "Secondary MI2S Playback", .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -382,7 +386,8 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .stream_name = "Secondary MI2S Capture", .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -394,7 +399,9 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .playback = { .stream_name = "Tertiary MI2S Playback", .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -407,7 +414,8 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .stream_name = "Tertiary MI2S Capture", .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -419,7 +427,9 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .playback = { .stream_name = "Quaternary MI2S Playback", .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -432,7 +442,8 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .stream_name = "Quaternary MI2S Capture", .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -444,7 +455,9 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .playback = { .stream_name = "Quinary MI2S Playback", .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, @@ -456,7 +469,9 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .capture = { .stream_name = "Quinary MI2S Capture", .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, .channels_max = 8, .rate_min = 8000, From 449183f09ea8eeacd8bb3117cc52bb9303386c5d Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 9 Feb 2026 16:59:46 +0530 Subject: [PATCH 0433/1330] FROMLIST: soc: qcom: pd-mapper: Add support for SA8775P Add support for the Qualcomm SA8775P SoC to the protection domain mapper. SA8775P share the same protection domain configuration as SC8280XP with an additional gpdsp domain, except for charger_pd. Add an entry to the kernel, to avoid the need for userspace to provide this service. Link: https://lore.kernel.org/all/20260209112947.930853-2-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik --- drivers/soc/qcom/qcom_pd_mapper.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c index dc10bc859ff41..65e1db12da089 100644 --- a/drivers/soc/qcom/qcom_pd_mapper.c +++ b/drivers/soc/qcom/qcom_pd_mapper.c @@ -305,6 +305,18 @@ static const struct qcom_pdm_domain_data cdsp_root_pd = { .services = { NULL }, }; +static const struct qcom_pdm_domain_data gpdsp_root_pd = { + .domain = "msm/gpdsp/root_pd", + .instance_id = 192, + .services = { NULL }, +}; + +static const struct qcom_pdm_domain_data gpdsp1_root_pd = { + .domain = "msm/gpdsp1/root_pd", + .instance_id = 241, + .services = { NULL }, +}; + static const struct qcom_pdm_domain_data slpi_root_pd = { .domain = "msm/slpi/root_pd", .instance_id = 90, @@ -401,6 +413,15 @@ static const struct qcom_pdm_domain_data *qcs404_domains[] = { NULL, }; +static const struct qcom_pdm_domain_data *sa8775p_domains[] = { + &adsp_audio_pd, + &adsp_root_pd, + &cdsp_root_pd, + &gpdsp_root_pd, + &gpdsp1_root_pd, + NULL, +}; + static const struct qcom_pdm_domain_data *sc7180_domains[] = { &adsp_audio_pd, &adsp_root_pd_pdr, @@ -572,6 +593,7 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,qcm2290", .data = qcm2290_domains, }, { .compatible = "qcom,qcm6490", .data = sc7280_domains, }, { .compatible = "qcom,qcs404", .data = qcs404_domains, }, + { .compatible = "qcom,sa8775p", .data = sa8775p_domains, }, { .compatible = "qcom,sc7180", .data = sc7180_domains, }, { .compatible = "qcom,sc7280", .data = sc7280_domains, }, { .compatible = "qcom,sc8180x", .data = sc8180x_domains, }, From 67b3f7b36645beeddeea6218ea63d27830999472 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 9 Feb 2026 16:59:47 +0530 Subject: [PATCH 0434/1330] FROMLIST: soc: qcom: pd-mapper: Add support for QCS8300 Add support for the Qualcomm QCS8300 SoC to the protection domain mapper. QCS8300 share the same protection domain configuration as SC8280XP, except charger_pd. Add an entry to the kernel, to avoid the need for userspace to provide this service. Link: https://lore.kernel.org/all/20260209112947.930853-3-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik --- drivers/soc/qcom/qcom_pd_mapper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c index 65e1db12da089..f6f13d8b885c3 100644 --- a/drivers/soc/qcom/qcom_pd_mapper.c +++ b/drivers/soc/qcom/qcom_pd_mapper.c @@ -413,6 +413,13 @@ static const struct qcom_pdm_domain_data *qcs404_domains[] = { NULL, }; +static const struct qcom_pdm_domain_data *qcs8300_domains[] = { + &adsp_audio_pd, + &adsp_root_pd, + &cdsp_root_pd, + NULL, +}; + static const struct qcom_pdm_domain_data *sa8775p_domains[] = { &adsp_audio_pd, &adsp_root_pd, @@ -593,6 +600,7 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,qcm2290", .data = qcm2290_domains, }, { .compatible = "qcom,qcm6490", .data = sc7280_domains, }, { .compatible = "qcom,qcs404", .data = qcs404_domains, }, + { .compatible = "qcom,qcs8300", .data = qcs8300_domains, }, { .compatible = "qcom,sa8775p", .data = sa8775p_domains, }, { .compatible = "qcom,sc7180", .data = sc7180_domains, }, { .compatible = "qcom,sc7280", .data = sc7280_domains, }, From cdea1f22aaf6d5ef9350d26926a634abf8bddd51 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Fri, 30 Jan 2026 14:12:31 +0800 Subject: [PATCH 0435/1330] FROMLIST: arm64: qcom: pd-mapper: Add QCS615 power domain mappings Add the QCS615 domain table to the in-kernel pd-mapper so that audio subsystems no longer rely on the userspace pd-mapper daemon. This enables proper initialization of ADSP and CDSP domains directly from the kernel. Link: https://lore.kernel.org/all/20260130061231.310113-1-le.qi@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov --- drivers/soc/qcom/qcom_pd_mapper.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c index f6f13d8b885c3..98c279386a253 100644 --- a/drivers/soc/qcom/qcom_pd_mapper.c +++ b/drivers/soc/qcom/qcom_pd_mapper.c @@ -429,6 +429,16 @@ static const struct qcom_pdm_domain_data *sa8775p_domains[] = { NULL, }; +static const struct qcom_pdm_domain_data *qcs615_domains[] = { + &adsp_audio_pd, + &adsp_root_pd, + &adsp_sensor_pd, + &cdsp_root_pd, + &mpss_root_pd, + &mpss_wlan_pd, + NULL, +}; + static const struct qcom_pdm_domain_data *sc7180_domains[] = { &adsp_audio_pd, &adsp_root_pd_pdr, @@ -600,6 +610,7 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,qcm2290", .data = qcm2290_domains, }, { .compatible = "qcom,qcm6490", .data = sc7280_domains, }, { .compatible = "qcom,qcs404", .data = qcs404_domains, }, + { .compatible = "qcom,qcs615", .data = qcs615_domains, }, { .compatible = "qcom,qcs8300", .data = qcs8300_domains, }, { .compatible = "qcom,sa8775p", .data = sa8775p_domains, }, { .compatible = "qcom,sc7180", .data = sc7180_domains, }, From 75bb4dfed4e99dcff695e316ab3f8928a9e1e4f1 Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Fri, 27 Feb 2026 17:34:47 +0530 Subject: [PATCH 0436/1330] FROMLIST: ASoC: qcom: qdsp6: Fix q6apm remove ordering during ADSP stop and start During ADSP stop and start, the kernel crashes due to the order in which ASoC components are removed. On ADSP stop, the q6apm-audio .remove callback unloads topology and removes PCM runtimes during ASoC teardown. This deletes the RTDs that contain the q6apm DAI components before their removal pass runs, leaving those components still linked to the card and causing crashes on the next rebind. Fix this by ensuring that all dependent (child) components are removed first, and the q6apm component is removed last. [ 48.105720] Unable to handle kernel NULL pointer dereference at virtual address 00000000000000d0 [ 48.114763] Mem abort info: [ 48.117650] ESR = 0x0000000096000004 [ 48.121526] EC = 0x25: DABT (current EL), IL = 32 bits [ 48.127010] SET = 0, FnV = 0 [ 48.130172] EA = 0, S1PTW = 0 [ 48.133415] FSC = 0x04: level 0 translation fault [ 48.138446] Data abort info: [ 48.141422] ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000 [ 48.147079] CM = 0, WnR = 0, TnD = 0, TagAccess = 0 [ 48.152354] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 [ 48.157859] user pgtable: 4k pages, 48-bit VAs, pgdp=00000001173cf000 [ 48.164517] [00000000000000d0] pgd=0000000000000000, p4d=0000000000000000 [ 48.171530] Internal error: Oops: 0000000096000004 [#1] SMP [ 48.177348] Modules linked in: q6prm_clocks q6apm_lpass_dais q6apm_dai snd_q6dsp_common q6prm snd_q6apm 8021q garp mrp stp llc snd_soc_hdmi_codec apr pdr_interface phy_qcom_edp fastrpc qcom_pd_mapper rpmsg_ctrl qrtr_smd rpmsg_char qcom_pdr_msg qcom_iris v4l2_mem2mem videobuf2_dma_contig ath11k_pci msm ubwc_config at24 ath11k videobuf2_memops mac80211 ocmem videobuf2_v4l2 libarc4 drm_gpuvm mhi qrtr videodev drm_exec snd_soc_sc8280xp gpu_sched videobuf2_common nvmem_qcom_spmi_sdam snd_soc_qcom_sdw drm_dp_aux_bus qcom_q6v5_pas qcom_spmi_temp_alarm snd_soc_qcom_common rtc_pm8xxx qcom_pon drm_display_helper cec qcom_pil_info qcom_stats soundwire_bus drm_client_lib mc dispcc0_sa8775p videocc_sa8775p qcom_q6v5 camcc_sa8775p snd_soc_dmic phy_qcom_sgmii_eth snd_soc_max98357a i2c_qcom_geni snd_soc_core dwmac_qcom_ethqos llcc_qcom icc_bwmon qcom_sysmon snd_compress qcom_refgen_regulator coresight_stm stmmac_platform snd_pcm_dmaengine qcom_common coresight_tmc stmmac coresight_replicator qcom_glink_smem coresight_cti stm_core [ 48.177444] coresight_funnel snd_pcm ufs_qcom phy_qcom_qmp_usb gpi phy_qcom_snps_femto_v2 coresight phy_qcom_qmp_ufs qcom_wdt gpucc_sa8775p pcs_xpcs mdt_loader qcom_ice icc_osm_l3 qmi_helpers snd_timer snd soundcore display_connector qcom_rng nvmem_reboot_mode drm_kms_helper phy_qcom_qmp_pcie sha256 cfg80211 rfkill socinfo fuse drm backlight ipv6 [ 48.301059] CPU: 2 UID: 0 PID: 293 Comm: kworker/u32:2 Not tainted 6.19.0-rc6-dirty #10 PREEMPT [ 48.310081] Hardware name: Qualcomm Technologies, Inc. Lemans EVK (DT) [ 48.316782] Workqueue: pdr_notifier_wq pdr_notifier_work [pdr_interface] [ 48.323672] pstate: 20400005 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 48.330825] pc : mutex_lock+0xc/0x54 [ 48.334514] lr : soc_dapm_shutdown_dapm+0x44/0x174 [snd_soc_core] [ 48.340794] sp : ffff800084ddb7b0 [ 48.344207] x29: ffff800084ddb7b0 x28: ffff00009cd9cf30 x27: ffff00009cd9cc00 [ 48.351544] x26: ffff000099610190 x25: ffffa31d2f19c810 x24: ffffa31d2f185098 [ 48.358869] x23: ffff800084ddb7f8 x22: 0000000000000000 x21: 00000000000000d0 [ 48.366198] x20: ffff00009ba6c338 x19: ffff00009ba6c338 x18: 00000000ffffffff [ 48.373528] x17: 000000040044ffff x16: ffffa31d4ae6dca8 x15: 072007740775076f [ 48.380853] x14: 0765076d07690774 x13: 00313a323a656369 x12: 767265733a637673 [ 48.388182] x11: 00000000000003f9 x10: ffffa31d4c7dea98 x9 : 0000000000000001 [ 48.395519] x8 : ffff00009a2aadc0 x7 : 0000000000000003 x6 : 0000000000000000 [ 48.402854] x5 : 0000000000000000 x4 : 0000000000000028 x3 : ffff000ef397a698 [ 48.410180] x2 : ffff00009a2aadc0 x1 : 0000000000000000 x0 : 00000000000000d0 [ 48.417506] Call trace: [ 48.420025] mutex_lock+0xc/0x54 (P) [ 48.423712] snd_soc_dapm_shutdown+0x44/0xbc [snd_soc_core] [ 48.429447] soc_cleanup_card_resources+0x30/0x2c0 [snd_soc_core] [ 48.435719] snd_soc_bind_card+0x4dc/0xcc0 [snd_soc_core] [ 48.441278] snd_soc_add_component+0x27c/0x2c8 [snd_soc_core] [ 48.447192] snd_soc_register_component+0x9c/0xf4 [snd_soc_core] [ 48.453371] devm_snd_soc_register_component+0x64/0xc4 [snd_soc_core] [ 48.459994] apm_probe+0xb4/0x110 [snd_q6apm] [ 48.464479] apr_device_probe+0x24/0x40 [apr] [ 48.468964] really_probe+0xbc/0x298 [ 48.472651] __driver_probe_device+0x78/0x12c [ 48.477132] driver_probe_device+0x40/0x160 [ 48.481435] __device_attach_driver+0xb8/0x134 [ 48.486011] bus_for_each_drv+0x80/0xdc [ 48.489964] __device_attach+0xa8/0x1b0 [ 48.493916] device_initial_probe+0x50/0x54 [ 48.498219] bus_probe_device+0x38/0xa0 [ 48.502170] device_add+0x590/0x760 [ 48.505761] device_register+0x20/0x30 [ 48.509623] of_register_apr_devices+0x1d8/0x318 [apr] [ 48.514905] apr_pd_status+0x2c/0x54 [apr] [ 48.519114] pdr_notifier_work+0x8c/0xe0 [pdr_interface] [ 48.524570] process_one_work+0x150/0x294 [ 48.528692] worker_thread+0x2d8/0x3d8 [ 48.532551] kthread+0x130/0x204 [ 48.535874] ret_from_fork+0x10/0x20 [ 48.539559] Code: d65f03c0 d5384102 d503201f d2800001 (c8e17c02) [ 48.545823] ---[ end trace 0000000000000000 ]--- Link: https://lore.kernel.org/all/20260227144534.278568-1-ravi.hothi@oss.qualcomm.com/ Fixes: 5477518b8a0e ("ASoC: qdsp6: audioreach: add q6apm support") Cc: stable@vger.kernel.org Signed-off-by: Ravi Hothi From e9633b96a5f270cb8f9046e0f552d09c5fd0de90 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 23 Feb 2026 18:07:27 +0000 Subject: [PATCH 0437/1330] FROMLIST: ASoC: qcom: q6apm: move component registration to unmanaged version q6apm component registers dais dynamically from ASoC toplology, which are allocated using device managed version apis. Allocating both component and dynamic dais using managed version could lead to incorrect free ordering, dai will be freed while component still holding references to it. Fix this issue by moving component to unmanged version so that the dai pointers are only freeded after the component is removed. ================================================================== BUG: KASAN: slab-use-after-free in snd_soc_del_component_unlocked+0x3d4/0x400 [snd_soc_core] Read of size 8 at addr ffff00084493a6e8 by task kworker/u48:0/3426 Tainted: [W]=WARN Hardware name: LENOVO 21N2ZC5PUS/21N2ZC5PUS, BIOS N42ET57W (1.31 ) 08/08/2024 Workqueue: pdr_notifier_wq pdr_notifier_work [pdr_interface] Call trace: show_stack+0x28/0x7c (C) dump_stack_lvl+0x60/0x80 print_report+0x160/0x4b4 kasan_report+0xac/0xfc __asan_report_load8_noabort+0x20/0x34 snd_soc_del_component_unlocked+0x3d4/0x400 [snd_soc_core] snd_soc_unregister_component_by_driver+0x50/0x88 [snd_soc_core] devm_component_release+0x30/0x5c [snd_soc_core] devres_release_all+0x13c/0x210 device_unbind_cleanup+0x20/0x190 device_release_driver_internal+0x350/0x468 device_release_driver+0x18/0x30 bus_remove_device+0x1a0/0x35c device_del+0x314/0x7f0 device_unregister+0x20/0xbc apr_remove_device+0x5c/0x7c [apr] device_for_each_child+0xd8/0x160 apr_pd_status+0x7c/0xa8 [apr] pdr_notifier_work+0x114/0x240 [pdr_interface] process_one_work+0x500/0xb70 worker_thread+0x630/0xfb0 kthread+0x370/0x6c0 ret_from_fork+0x10/0x20 Allocated by task 77: kasan_save_stack+0x40/0x68 kasan_save_track+0x20/0x40 kasan_save_alloc_info+0x44/0x58 __kasan_kmalloc+0xbc/0xdc __kmalloc_node_track_caller_noprof+0x1f4/0x620 devm_kmalloc+0x7c/0x1c8 snd_soc_register_dai+0x50/0x4f0 [snd_soc_core] soc_tplg_pcm_elems_load+0x55c/0x1eb8 [snd_soc_core] snd_soc_tplg_component_load+0x4f8/0xb60 [snd_soc_core] audioreach_tplg_init+0x124/0x1fc [snd_q6apm] q6apm_audio_probe+0x10/0x1c [snd_q6apm] snd_soc_component_probe+0x5c/0x118 [snd_soc_core] soc_probe_component+0x44c/0xaf0 [snd_soc_core] snd_soc_bind_card+0xad0/0x2370 [snd_soc_core] snd_soc_register_card+0x3b0/0x4c0 [snd_soc_core] devm_snd_soc_register_card+0x50/0xc8 [snd_soc_core] x1e80100_platform_probe+0x208/0x368 [snd_soc_x1e80100] platform_probe+0xc0/0x188 really_probe+0x188/0x804 __driver_probe_device+0x158/0x358 driver_probe_device+0x60/0x190 __device_attach_driver+0x16c/0x2a8 bus_for_each_drv+0x100/0x194 __device_attach+0x174/0x380 device_initial_probe+0x14/0x20 bus_probe_device+0x124/0x154 deferred_probe_work_func+0x140/0x220 process_one_work+0x500/0xb70 worker_thread+0x630/0xfb0 kthread+0x370/0x6c0 ret_from_fork+0x10/0x20 Freed by task 3426: kasan_save_stack+0x40/0x68 kasan_save_track+0x20/0x40 __kasan_save_free_info+0x4c/0x80 __kasan_slab_free+0x78/0xa0 kfree+0x100/0x4a4 devres_release_all+0x144/0x210 device_unbind_cleanup+0x20/0x190 device_release_driver_internal+0x350/0x468 device_release_driver+0x18/0x30 bus_remove_device+0x1a0/0x35c device_del+0x314/0x7f0 device_unregister+0x20/0xbc apr_remove_device+0x5c/0x7c [apr] device_for_each_child+0xd8/0x160 apr_pd_status+0x7c/0xa8 [apr] pdr_notifier_work+0x114/0x240 [pdr_interface] process_one_work+0x500/0xb70 worker_thread+0x630/0xfb0 kthread+0x370/0x6c0 ret_from_fork+0x10/0x20 Link: https://lore.kernel.org/all/20260223180740.444311-2-srinivas.kandagatla@oss.qualcomm.com/ Fixes: 5477518b8a0e ("ASoC: qdsp6: audioreach: add q6apm support") Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/qdsp6/q6apm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/sound/soc/qcom/qdsp6/q6apm.c b/sound/soc/qcom/qdsp6/q6apm.c index 5751e80b3b928..12c331c28c919 100644 --- a/sound/soc/qcom/qdsp6/q6apm.c +++ b/sound/soc/qcom/qdsp6/q6apm.c @@ -768,6 +768,11 @@ static void apm_remove(gpr_device_t *gdev) snd_soc_unregister_component(&gdev->dev); } +static void apm_remove(gpr_device_t *gdev) +{ + snd_soc_unregister_component(&gdev->dev); +} + struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph, uint32_t mid) { struct audioreach_graph_info *info = graph->info; From 5661f4f8117c8b664bf8a4838ba7b42c2f2c50a4 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 23 Feb 2026 18:07:28 +0000 Subject: [PATCH 0438/1330] FROMLIST: ASoC: qcom: q6apm: remove child devices when apm is removed looks like q6apm driver does not remove the child driver q6apm-dai and q6apm-bedais when the this driver is removed. Fix this by using a manage version of of_platfom_populate. With this change when the dsp is shutdown all the devices assocated with q6apm will now be removed. Link: https://lore.kernel.org/all/20260223180740.444311-3-srinivas.kandagatla@oss.qualcomm.com/ Fixes: 5477518b8a0e ("ASoC: qdsp6: audioreach: add q6apm support") Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/qdsp6/q6apm.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/sound/soc/qcom/qdsp6/q6apm.c b/sound/soc/qcom/qdsp6/q6apm.c index 12c331c28c919..712209bb36c44 100644 --- a/sound/soc/qcom/qdsp6/q6apm.c +++ b/sound/soc/qcom/qdsp6/q6apm.c @@ -755,7 +755,7 @@ static int apm_probe(gpr_device_t *gdev) return ret; } - ret = of_platform_populate(dev->of_node, NULL, NULL, dev); + ret = devm_of_platform_populate(dev); if (ret) snd_soc_unregister_component(dev); @@ -768,11 +768,6 @@ static void apm_remove(gpr_device_t *gdev) snd_soc_unregister_component(&gdev->dev); } -static void apm_remove(gpr_device_t *gdev) -{ - snd_soc_unregister_component(&gdev->dev); -} - struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph, uint32_t mid) { struct audioreach_graph_info *info = graph->info; From 60e114f19a066b6e927b7a2d9f6e403d4a605bb8 Mon Sep 17 00:00:00 2001 From: Dipa Mantre Date: Mon, 23 Mar 2026 21:06:50 +0530 Subject: [PATCH 0439/1330] QCLINUX: defconfig: Enable Qualcomm BCL driver Enable Qualcomm BCL driver config. Signed-off-by: Dipa Mantre --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 83aaf47886dba..db78d89420cd6 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -57,6 +57,7 @@ CONFIG_STM_SOURCE_FTRACE=m CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_SENSORS_AMC6821=y CONFIG_SENSORS_EMC2305=y +CONFIG_SENSORS_QCOM_BCL=y CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y From 189c1c197948561a1c44f0f3ec77e190a3d19078 Mon Sep 17 00:00:00 2001 From: gaolez Date: Wed, 18 Mar 2026 16:15:38 +0800 Subject: [PATCH 0440/1330] QCLINUX: qcom.config: Enable testmode config Enabling this option exposes the NL80211_CMD_TESTMODE command, which permits userspace applications to send vendor-specific test commands to the driver for diagnostics and validation purposes. Signed-off-by: gaolez --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index db78d89420cd6..b35310a083c26 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -36,6 +36,7 @@ CONFIG_INPUT_UINPUT=y CONFIG_KPROBES=y CONFIG_MACVLAN=y CONFIG_MACVTAP=y +CONFIG_NL80211_TESTMODE=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y CONFIG_PM_AUTOSLEEP=y From 1d70c94c2c86afb8699b820128d5d8e7ae6a2223 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Fri, 13 Mar 2026 15:53:53 +0530 Subject: [PATCH 0441/1330] FROMLIST: iommu/arm-smmu: Use pm_runtime in fault handlers Commit d4a44f0750bb ("iommu/arm-smmu: Invoke pm_runtime across the driver") enabled pm_runtime for the arm-smmu device. On systems where the SMMU sits in a power domain, all register accesses must be done while the device is runtime active to avoid unclocked register reads and potential NoC errors. So far, this has not been an issue for most SMMU clients because stall-on-fault is enabled by default. While a translation fault is being handled, the SMMU stalls further translations for that context bank, so the fault handler would not race with a powered-down SMMU. Adreno SMMU now disables stall-on-fault in the presence of fault storms to avoid saturating SMMU resources and hanging the GMU. With stall-on-fault disabled, the SMMU can generate faults while its power domain may no longer be enabled, which makes unclocked accesses to fault-status registers in the SMMU fault handlers possible. Guard the context and global fault handlers with pm_runtime_get_if_active() and pm_runtime_put_autosuspend() so that all SMMU fault register accesses are done with the SMMU powered. In case pm_runtime is not active we can safely ignore the fault as for pm runtime resume the smmu device is reset and fault registers are cleared. List: https://lore.kernel.org/all/20260313-smmu-rpm-v2-1-8c2236b402b0@oss.qualcomm.com/ Fixes: b13044092c1e ("drm/msm: Temporarily disable stall-on-fault after a page fault") Co-developed-by: Pratyush Brahma Signed-off-by: Pratyush Brahma Signed-off-by: Prakash Gupta --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 60 +++++++++++++++++---------- 1 file changed, 39 insertions(+), 21 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 0bd21d206eb3e..83a6fac172ae9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -462,10 +462,20 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) int idx = smmu_domain->cfg.cbndx; int ret; + if (!pm_runtime_get_if_active(smmu->dev)) + return IRQ_NONE; + + if (smmu->impl && smmu->impl->context_fault) { + ret = smmu->impl->context_fault(irq, dev); + goto out_power_off; + } + arm_smmu_read_context_fault_info(smmu, idx, &cfi); - if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) - return IRQ_NONE; + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) { + ret = IRQ_NONE; + goto out_power_off; + } ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); @@ -480,7 +490,12 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) ret == -EAGAIN ? 0 : ARM_SMMU_RESUME_TERMINATE); } - return IRQ_HANDLED; + ret = IRQ_HANDLED; + +out_power_off: + pm_runtime_put_autosuspend(smmu->dev); + + return ret; } static irqreturn_t arm_smmu_global_fault(int irq, void *dev) @@ -489,14 +504,25 @@ static irqreturn_t arm_smmu_global_fault(int irq, void *dev) struct arm_smmu_device *smmu = dev; static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); + int ret; + + if (!pm_runtime_get_if_active(smmu->dev)) + return IRQ_NONE; + + if (smmu->impl && smmu->impl->global_fault) { + ret = smmu->impl->global_fault(irq, dev); + goto out_power_off; + } gfsr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); gfsynr0 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); gfsynr1 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); gfsynr2 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); - if (!gfsr) - return IRQ_NONE; + if (!gfsr) { + ret = IRQ_NONE; + goto out_power_off; + } if (__ratelimit(&rs)) { if (IS_ENABLED(CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT) && @@ -513,7 +539,11 @@ static irqreturn_t arm_smmu_global_fault(int irq, void *dev) } arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); - return IRQ_HANDLED; + ret = IRQ_HANDLED; + +out_power_off: + pm_runtime_put_autosuspend(smmu->dev); + return ret; } static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, @@ -683,7 +713,6 @@ static int arm_smmu_init_domain_context(struct arm_smmu_domain *smmu_domain, enum io_pgtable_fmt fmt; struct iommu_domain *domain = &smmu_domain->domain; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; - irqreturn_t (*context_fault)(int irq, void *dev); mutex_lock(&smmu_domain->init_mutex); if (smmu_domain->smmu) @@ -850,19 +879,14 @@ static int arm_smmu_init_domain_context(struct arm_smmu_domain *smmu_domain, */ irq = smmu->irqs[cfg->irptndx]; - if (smmu->impl && smmu->impl->context_fault) - context_fault = smmu->impl->context_fault; - else - context_fault = arm_smmu_context_fault; - if (smmu->impl && smmu->impl->context_fault_needs_threaded_irq) ret = devm_request_threaded_irq(smmu->dev, irq, NULL, - context_fault, + arm_smmu_context_fault, IRQF_ONESHOT | IRQF_SHARED, "arm-smmu-context-fault", smmu_domain); else - ret = devm_request_irq(smmu->dev, irq, context_fault, IRQF_SHARED, + ret = devm_request_irq(smmu->dev, irq, arm_smmu_context_fault, IRQF_SHARED, "arm-smmu-context-fault", smmu_domain); if (ret < 0) { @@ -2125,7 +2149,6 @@ static int arm_smmu_device_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; int num_irqs, i, err; u32 global_irqs, pmu_irqs; - irqreturn_t (*global_fault)(int irq, void *dev); smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); if (!smmu) { @@ -2205,18 +2228,13 @@ static int arm_smmu_device_probe(struct platform_device *pdev) smmu->num_context_irqs = smmu->num_context_banks; } - if (smmu->impl && smmu->impl->global_fault) - global_fault = smmu->impl->global_fault; - else - global_fault = arm_smmu_global_fault; - for (i = 0; i < global_irqs; i++) { int irq = platform_get_irq(pdev, i); if (irq < 0) return irq; - err = devm_request_irq(dev, irq, global_fault, IRQF_SHARED, + err = devm_request_irq(dev, irq, arm_smmu_global_fault, IRQF_SHARED, "arm-smmu global fault", smmu); if (err) return dev_err_probe(dev, err, From 01a136b459a62fa08c4282546fd2cba7203fcdde Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 23 Mar 2026 23:05:23 +0000 Subject: [PATCH 0442/1330] FROMLIST: soc: qcom: pd-mapper: Add support for Glymur Add Protection Domains for Qualcomm Glymur SoC which has both ADSP and CDSP. Adding this entry to the kernel driver will avoid the need for userspace to provide this service. Link: https://lore.kernel.org/all/20260323230523.2209023-1-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla --- drivers/soc/qcom/qcom_pd_mapper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c index 98c279386a253..e46273bf4263a 100644 --- a/drivers/soc/qcom/qcom_pd_mapper.c +++ b/drivers/soc/qcom/qcom_pd_mapper.c @@ -372,6 +372,14 @@ static const struct qcom_pdm_domain_data mpss_wlan_pd = { }, }; +static const struct qcom_pdm_domain_data *glymur_domains[] = { + &adsp_audio_pd, + &adsp_root_pd, + &adsp_sensor_pd, + &cdsp_root_pd, + NULL, +}; + static const struct qcom_pdm_domain_data *kaanapali_domains[] = { &adsp_audio_pd, &adsp_root_pd, @@ -599,6 +607,7 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,apq8074", .data = NULL, }, { .compatible = "qcom,apq8084", .data = NULL, }, { .compatible = "qcom,apq8096", .data = msm8996_domains, }, + { .compatible = "qcom,glymur", .data = glymur_domains, }, { .compatible = "qcom,kaanapali", .data = kaanapali_domains, }, { .compatible = "qcom,msm8226", .data = NULL, }, { .compatible = "qcom,msm8909", .data = NULL, }, From c47f3a9fa0d83c84f62cc1c8eda235b490de9faf Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 25 Mar 2026 11:19:46 +0530 Subject: [PATCH 0443/1330] soc: qcom: rpmpd: Add Shikra RPM compatiable Add the rpmpd compatable string for shikra. Signed-off-by: Rakesh Kota --- drivers/pmdomain/qcom/rpmpd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index f30403e629eff..526f1e7d6a0d9 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -964,6 +964,7 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, { .compatible = "qcom,qm215-rpmpd", .data = &qm215_desc }, { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, + { .compatible = "qcom,shikra-rpmpd", .data = &shikra_desc }, { .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc }, { .compatible = "qcom,sm6125-rpmpd", .data = &sm6125_desc }, { .compatible = "qcom,sm6375-rpmpd", .data = &sm6375_desc }, From 225ba0bab5ddf515a7af581b752e400fef771564 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 24 Mar 2026 15:36:35 +0800 Subject: [PATCH 0444/1330] QCLINUX: qcom.config: update TGU config The TGU config has been changed in latest TGU driver version. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index b35310a083c26..175c16436b4a6 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -17,7 +17,6 @@ CONFIG_CORESIGHT_CORESIGHT_TNOC=m CONFIG_CORESIGHT_CTCU=m CONFIG_CORESIGHT_DUMMY=m CONFIG_CORESIGHT_SOURCE_ETM4X=m -CONFIG_CORESIGHT_TGU=m CONFIG_CORESIGHT_TPDM=m CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_GOV_TEO=y @@ -48,6 +47,7 @@ CONFIG_POWERCAP=y CONFIG_PROC_EVENTS=y CONFIG_QCA808X_PHY=m CONFIG_QCOM_QMI_COOLING=y +CONFIG_QCOM_TGU=m CONFIG_REMOTEPROC_THERMAL=y CONFIG_SCHED_DEBUG=y CONFIG_SCHEDSTATS=y From 9fc6416901ceebf91a1c2f0c12ba3d1c44663f31 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 25 Mar 2026 15:23:24 +0800 Subject: [PATCH 0445/1330] QCLINUX: qcom.config: fix the TNOC config Fix the wrong config for CORESIGHT_TNOC. Signed-off-by: Jie Gan --- arch/arm64/configs/qcom.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 175c16436b4a6..5ab3c396bb670 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -13,7 +13,7 @@ CONFIG_BT_RFCOMM_TTY=y CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CMA=y CONFIG_CONNECTOR=y -CONFIG_CORESIGHT_CORESIGHT_TNOC=m +CONFIG_CORESIGHT_TNOC=m CONFIG_CORESIGHT_CTCU=m CONFIG_CORESIGHT_DUMMY=m CONFIG_CORESIGHT_SOURCE_ETM4X=m From b60bea230f2bc4601485414b88d705856d2440f6 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Tue, 24 Mar 2026 15:49:49 +0530 Subject: [PATCH 0446/1330] FROMLIST: arm64: dts: qcom: glymur-crd: USB mode change to Host USB mode change to Host Link: https://lore.kernel.org/linux-arm-msm/20260320-dts-qcom-glymur-add-usb-support-v7-2-ba367eda6010@oss.qualcomm.com/ Signed-off-by: Abel Vesa Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 3f656436f417a..5290b6bbedb10 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -1096,6 +1096,8 @@ }; &usb_0 { + dr_mode = "host"; + status = "okay"; }; @@ -1125,6 +1127,8 @@ }; &usb_1 { + dr_mode = "host"; + status = "okay"; }; From 212d154f4e529cd5c2674d81bb291d3e46740518 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:19:50 -0700 Subject: [PATCH 0447/1330] Revert "FROMLIST: usb: misc: qcom_eud: fix virtual attach/detach event handling" This reverts commit 7104631aca14a5f01ee8f33ebbfda4c2e4047d28. Signed-off-by: Elson Serrao --- drivers/usb/misc/qcom_eud.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 60f566427abe2..3f1cc7ea2a6ae 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -343,26 +343,10 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) if (!path || !path->controller_sw) goto clear_irq; - /* - * EUD virtual attach/detach event handling for low power debugging: - * - * When EUD is enabled in debug mode, the device remains physically - * connected to the PC throughout the debug session, keeping the USB - * controller active. This prevents testing of low power scenarios that - * require USB disconnection. - * - * EUD solves this by providing virtual USB attach/detach events while - * maintaining the physical connection. These events are triggered from - * the Host PC via the enumerated EUD control interface and delivered - * to the EUD driver as interrupts. - * - * These notifications are forwarded to the USB controller through role - * switch framework. - */ if (chip->usb_attached) ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_DEVICE); else - ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_NONE); + ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_HOST); if (ret) dev_err(chip->dev, "failed to set role switch\n"); From 166d0b4c54ad984717547f5e610e03c19117beb5 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:20:22 -0700 Subject: [PATCH 0448/1330] Revert "FROMLIST: usb: misc: qcom_eud: add host mode coordination" This reverts commit 583d6fc0f35f15b14ebed9dd244a7ba4bf845496. Signed-off-by: Elson Serrao --- drivers/usb/misc/qcom_eud.c | 79 +------------------------------------ 1 file changed, 1 insertion(+), 78 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 3f1cc7ea2a6ae..0ea6491f963ce 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -49,15 +49,12 @@ struct eud_chip { struct device *dev; void __iomem *base; struct eud_path *paths[EUD_MAX_PORTS]; - /* serializes EUD control operations */ - struct mutex state_lock; phys_addr_t mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; bool phy_enabled; - bool eud_disabled_for_host; u8 port_idx; }; @@ -165,66 +162,32 @@ static ssize_t enable_store(struct device *dev, const char *buf, size_t count) { struct eud_chip *chip = dev_get_drvdata(dev); - struct eud_path *path; bool enable; int ret; if (kstrtobool(buf, &enable)) return -EINVAL; - mutex_lock(&chip->state_lock); - /* Skip operation if already in desired state */ - if (chip->enabled == enable) { - mutex_unlock(&chip->state_lock); + if (chip->enabled == enable) return count; - } - - /* - * Handle double-disable scenario: User is disabling EUD that was already - * disabled due to host mode. Since the hardware is already disabled, we - * only need to clear the host-disabled flag to prevent unwanted re-enabling - * when exiting host mode. This respects the user's explicit disable request. - */ - if (!enable && chip->eud_disabled_for_host) { - chip->eud_disabled_for_host = false; - chip->enabled = false; - mutex_unlock(&chip->state_lock); - return count; - } if (enable) { - /* - * EUD functions by presenting itself as a USB device to the host PC for - * debugging, making it incompatible in USB host mode configuration. - * Prevent enabling EUD in this configuration to avoid hardware conflicts. - */ - path = chip->paths[chip->port_idx]; - if (path && path->curr_role == USB_ROLE_HOST) { - dev_err(chip->dev, "EUD not usable in host mode configuration\n"); - mutex_unlock(&chip->state_lock); - return -EBUSY; - } - ret = enable_eud(chip); if (ret) { dev_err(chip->dev, "failed to enable eud\n"); - mutex_unlock(&chip->state_lock); return ret; } } else { ret = disable_eud(chip); if (ret) { dev_err(chip->dev, "failed to disable eud\n"); - mutex_unlock(&chip->state_lock); return ret; } } chip->enabled = enable; - mutex_unlock(&chip->state_lock); - return count; } @@ -361,56 +324,18 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) static int eud_role_switch_set(struct usb_role_switch *sw, enum usb_role role) { struct eud_path *path = usb_role_switch_get_drvdata(sw); - struct eud_chip *chip = path->chip; int ret; - mutex_lock(&chip->state_lock); - - /* - * EUD must be disabled when USB operates in host mode. EUD functions by - * presenting itself as a USB device to the host PC for debugging, making - * it incompatible in host mode configuration. - * - * chip->enabled preserves user's sysfs configuration and is not modified - * during host mode transitions to maintain user intent. - */ - - /* Only act if EUD is enabled and this is the active path */ - if (chip->enabled && path->num == chip->port_idx) { - if (role == USB_ROLE_HOST && !chip->eud_disabled_for_host) { - ret = disable_eud(chip); - if (ret) { - dev_err(chip->dev, "Failed to disable EUD for host mode: %d\n", - ret); - mutex_unlock(&chip->state_lock); - return ret; - } - chip->eud_disabled_for_host = true; - } else if (role != USB_ROLE_HOST && chip->eud_disabled_for_host) { - ret = enable_eud(chip); - if (ret) { - dev_err(chip->dev, "Failed to re-enable EUD after host mode: %d\n", - ret); - mutex_unlock(&chip->state_lock); - return ret; - } - chip->eud_disabled_for_host = false; - } - } - /* Forward the role request to the USB controller */ ret = usb_role_switch_set_role(path->controller_sw, role); if (ret) { dev_err(path->chip->dev, "Failed to set role %s for port %u: %d\n", usb_role_string(role), path->num, ret); - mutex_unlock(&chip->state_lock); return ret; } path->curr_role = role; - mutex_unlock(&chip->state_lock); - return 0; } @@ -508,8 +433,6 @@ static int eud_probe(struct platform_device *pdev) chip->dev = &pdev->dev; - mutex_init(&chip->state_lock); - ret = devm_add_action_or_reset(chip->dev, eud_role_switch_release, chip); if (ret) return ret; From 10c8560aeff90b48eb17fde862a183a0728e9869 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:20:39 -0700 Subject: [PATCH 0449/1330] Revert "FROMLIST: usb: misc: qcom_eud: improve enable_store API" This reverts commit eb5da51b8cba5fc4ed3bd699d2cce066020e3415. Signed-off-by: Elson Serrao --- drivers/usb/misc/qcom_eud.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 0ea6491f963ce..a58022f50484f 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -168,27 +168,18 @@ static ssize_t enable_store(struct device *dev, if (kstrtobool(buf, &enable)) return -EINVAL; - /* Skip operation if already in desired state */ - if (chip->enabled == enable) - return count; - if (enable) { ret = enable_eud(chip); - if (ret) { - dev_err(chip->dev, "failed to enable eud\n"); - return ret; - } + if (!ret) + chip->enabled = enable; + else + disable_eud(chip); + } else { ret = disable_eud(chip); - if (ret) { - dev_err(chip->dev, "failed to disable eud\n"); - return ret; - } } - chip->enabled = enable; - - return count; + return ret < 0 ? ret : count; } static DEVICE_ATTR_RW(enable); From 4d1b142a6c1769c3e9850de851abf5b0844fccc7 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:21:03 -0700 Subject: [PATCH 0450/1330] Revert "FROMLIST: usb: misc: qcom_eud: add per-path role switch support" This reverts commit e7e656c813d8d651e26704a10f9c56a34a2f7e13. Signed-off-by: Elson Serrao --- drivers/usb/misc/qcom_eud.c | 80 +++++-------------------------------- 1 file changed, 10 insertions(+), 70 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index a58022f50484f..5cebb64f4a672 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -38,15 +38,12 @@ struct eud_path { struct eud_chip *chip; struct phy *phy; - struct usb_role_switch *controller_sw; - struct usb_role_switch *eud_sw; - enum usb_role curr_role; - char name[16]; u8 num; }; struct eud_chip { struct device *dev; + struct usb_role_switch *role_sw; void __iomem *base; struct eud_path *paths[EUD_MAX_PORTS]; phys_addr_t mode_mgr; @@ -132,7 +129,7 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - return 0; + return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } static int disable_eud(struct eud_chip *priv) @@ -290,21 +287,15 @@ static irqreturn_t handle_eud_irq(int irq, void *data) static irqreturn_t handle_eud_irq_thread(int irq, void *data) { struct eud_chip *chip = data; - struct eud_path *path; int ret; - path = chip->paths[chip->port_idx]; - if (!path || !path->controller_sw) - goto clear_irq; - if (chip->usb_attached) - ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_DEVICE); + ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_DEVICE); else - ret = usb_role_switch_set_role(path->controller_sw, USB_ROLE_HOST); + ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_HOST); if (ret) dev_err(chip->dev, "failed to set role switch\n"); -clear_irq: /* set and clear vbus_int_clr[0] to clear interrupt */ writel(BIT(0), chip->base + EUD_REG_VBUS_INT_CLR); writel(0, chip->base + EUD_REG_VBUS_INT_CLR); @@ -312,45 +303,15 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) return IRQ_HANDLED; } -static int eud_role_switch_set(struct usb_role_switch *sw, enum usb_role role) -{ - struct eud_path *path = usb_role_switch_get_drvdata(sw); - int ret; - - /* Forward the role request to the USB controller */ - ret = usb_role_switch_set_role(path->controller_sw, role); - if (ret) { - dev_err(path->chip->dev, "Failed to set role %s for port %u: %d\n", - usb_role_string(role), path->num, ret); - return ret; - } - - path->curr_role = role; - - return 0; -} - static void eud_role_switch_release(void *data) { struct eud_chip *chip = data; - int i; - for (i = 0; i < EUD_MAX_PORTS; i++) { - struct eud_path *path = chip->paths[i]; - - if (!path) - continue; - - if (path->eud_sw) - usb_role_switch_unregister(path->eud_sw); - if (path->controller_sw) - usb_role_switch_put(path->controller_sw); - } + usb_role_switch_put(chip->role_sw); } static int eud_init_path(struct eud_chip *chip, struct device_node *np) { - struct usb_role_switch_desc role_sw_desc = {}; struct eud_path *path; u32 path_num; int ret; @@ -381,32 +342,6 @@ static int eud_init_path(struct eud_chip *chip, struct device_node *np) chip->paths[path_num] = path; - path->curr_role = USB_ROLE_NONE; - - if (!of_property_read_bool(np, "usb-role-switch")) - return 0; - - /* Fetch the USB controller's role switch */ - path->controller_sw = fwnode_usb_role_switch_get(of_fwnode_handle(np)); - if (IS_ERR(path->controller_sw)) - return dev_err_probe(chip->dev, PTR_ERR(path->controller_sw), - "Failed to get controller role switch for path %d\n", - path_num); - - /* Create a role switch */ - role_sw_desc.fwnode = of_fwnode_handle(np); - role_sw_desc.set = eud_role_switch_set; - role_sw_desc.driver_data = path; - snprintf(path->name, sizeof(path->name), "eud-path%u", path_num); - role_sw_desc.name = path->name; - - path->eud_sw = usb_role_switch_register(chip->dev, &role_sw_desc); - if (IS_ERR(path->eud_sw)) { - dev_err(chip->dev, "Failed to register EUD role switch for path %d: %ld\n", - path_num, PTR_ERR(path->eud_sw)); - return PTR_ERR(path->eud_sw); - } - return 0; } @@ -424,6 +359,11 @@ static int eud_probe(struct platform_device *pdev) chip->dev = &pdev->dev; + chip->role_sw = usb_role_switch_get(&pdev->dev); + if (IS_ERR(chip->role_sw)) + return dev_err_probe(chip->dev, PTR_ERR(chip->role_sw), + "failed to get role switch\n"); + ret = devm_add_action_or_reset(chip->dev, eud_role_switch_release, chip); if (ret) return ret; From 3a58cf7feed17125b589cac0d5427049a10bea73 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:21:33 -0700 Subject: [PATCH 0451/1330] Revert "FROMLIST: usb: misc: qcom_eud: add per-path High-Speed PHY control" This reverts commit e2541a8409a99af58825af0a54178d0b26677f5b. Signed-off-by: Elson Serrao --- drivers/usb/misc/qcom_eud.c | 130 +----------------------------------- 1 file changed, 1 insertion(+), 129 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 5cebb64f4a672..1a136f8f1ae52 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -35,95 +34,25 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) -struct eud_path { - struct eud_chip *chip; - struct phy *phy; - u8 num; -}; - struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; void __iomem *base; - struct eud_path *paths[EUD_MAX_PORTS]; phys_addr_t mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; - bool phy_enabled; u8 port_idx; }; -static int eud_phy_enable(struct eud_chip *chip) -{ - struct eud_path *path; - struct phy *phy; - int ret; - - if (chip->phy_enabled) - return 0; - - path = chip->paths[chip->port_idx]; - if (!path || !path->phy) { - dev_err(chip->dev, "No PHY configured for port %u\n", chip->port_idx); - return -ENODEV; - } - - phy = path->phy; - - ret = phy_init(phy); - if (ret) { - dev_err(chip->dev, "Failed to initialize USB2 PHY for port %u: %d\n", - chip->port_idx, ret); - return ret; - } - - ret = phy_power_on(phy); - if (ret) { - dev_err(chip->dev, "Failed to power on USB2 PHY for port %u: %d\n", - chip->port_idx, ret); - phy_exit(phy); - return ret; - } - - chip->phy_enabled = true; - - return 0; -} - -static void eud_phy_disable(struct eud_chip *chip) -{ - struct eud_path *path; - struct phy *phy; - - if (!chip->phy_enabled) - return; - - path = chip->paths[chip->port_idx]; - if (!path || !path->phy) - return; - - phy = path->phy; - - phy_power_off(phy); - phy_exit(phy); - chip->phy_enabled = false; -} - static int enable_eud(struct eud_chip *priv) { int ret; - ret = eud_phy_enable(priv); - if (ret) - return ret; - ret = qcom_scm_io_writel(priv->mode_mgr + EUD_REG_EUD_EN2, 1); - if (ret) { - eud_phy_disable(priv); + if (ret) return ret; - } writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, @@ -141,8 +70,6 @@ static int disable_eud(struct eud_chip *priv) return ret; writel(0, priv->base + EUD_REG_CSR_EUD_EN); - eud_phy_disable(priv); - return 0; } @@ -205,12 +132,6 @@ static ssize_t port_store(struct device *dev, if (port >= EUD_MAX_PORTS) return -EINVAL; - /* Check if the corresponding path is available */ - if (!chip->paths[port]) { - dev_err(chip->dev, "EUD not supported on selected port\n"); - return -EOPNOTSUPP; - } - /* Port selection must be done before enabling EUD */ if (chip->enabled) { dev_err(chip->dev, "Cannot change port while EUD is enabled\n"); @@ -310,45 +231,8 @@ static void eud_role_switch_release(void *data) usb_role_switch_put(chip->role_sw); } -static int eud_init_path(struct eud_chip *chip, struct device_node *np) -{ - struct eud_path *path; - u32 path_num; - int ret; - - ret = of_property_read_u32(np, "reg", &path_num); - if (ret) { - dev_err(chip->dev, "Missing 'reg' property in path node\n"); - return ret; - } - - if (path_num >= EUD_MAX_PORTS) { - dev_err(chip->dev, "Invalid path number: %u (max %d)\n", - path_num, EUD_MAX_PORTS - 1); - return -EINVAL; - } - - path = devm_kzalloc(chip->dev, sizeof(*path), GFP_KERNEL); - if (!path) - return -ENOMEM; - - path->chip = chip; - path->num = path_num; - - path->phy = devm_of_phy_get(chip->dev, np, NULL); - if (IS_ERR(path->phy)) - return dev_err_probe(chip->dev, PTR_ERR(path->phy), - "Failed to get PHY for path %d\n", path_num); - - chip->paths[path_num] = path; - - return 0; -} - static int eud_probe(struct platform_device *pdev) { - struct device_node *np = pdev->dev.of_node; - struct device_node *child; struct eud_chip *chip; struct resource *res; int ret; @@ -368,18 +252,6 @@ static int eud_probe(struct platform_device *pdev) if (ret) return ret; - for_each_child_of_node(np, child) { - ret = eud_init_path(chip, child); - if (ret) { - of_node_put(child); - return ret; - } - } - - /* Primary path is mandatory. Secondary is optional */ - if (!chip->paths[0]) - return -ENODEV; - chip->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(chip->base)) return PTR_ERR(chip->base); From aa46f838c05395286f27e0d0060cb6339d755424 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:21:52 -0700 Subject: [PATCH 0452/1330] Revert "FROMLIST: usb: misc: qcom_eud: add sysfs attribute for port selection" This reverts commit c042ed7b42aff071249d6a1b91cedb7170e2d2d4. Signed-off-by: Elson Serrao --- Documentation/ABI/testing/sysfs-driver-eud | 16 -------- drivers/usb/misc/qcom_eud.c | 43 ---------------------- 2 files changed, 59 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI/testing/sysfs-driver-eud index 67223f73ee606..2bab0db2d2f0f 100644 --- a/Documentation/ABI/testing/sysfs-driver-eud +++ b/Documentation/ABI/testing/sysfs-driver-eud @@ -7,19 +7,3 @@ Description: EUD based on a 1 or a 0 value. By enabling EUD, the user is able to activate the mini-usb hub of EUD for debug and trace capabilities. - -What: /sys/bus/platform/drivers/qcom_eud/.../port -Date: January 2026 -Contact: Elson Serrao -Description: - Selects which USB port the Embedded USB Debugger (EUD) - is mapped to on platforms providing multiple High-Speed - USB ports. - - Valid values: - 0 - Primary USB port - 1 - Secondary USB port - - The attribute is writable only while EUD is disabled. - Reading the attribute returns the currently selected - USB port number. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 1a136f8f1ae52..926419ca560fc 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -23,11 +23,8 @@ #define EUD_REG_VBUS_INT_CLR 0x0080 #define EUD_REG_CSR_EUD_EN 0x1014 #define EUD_REG_SW_ATTACH_DET 0x1018 -#define EUD_REG_PORT_SEL 0x1028 #define EUD_REG_EUD_EN2 0x0000 -#define EUD_MAX_PORTS 2 - #define EUD_ENABLE BIT(0) #define EUD_INT_PET_EUD BIT(0) #define EUD_INT_VBUS BIT(2) @@ -43,7 +40,6 @@ struct eud_chip { int irq; bool enabled; bool usb_attached; - u8 port_idx; }; static int enable_eud(struct eud_chip *priv) @@ -108,47 +104,8 @@ static ssize_t enable_store(struct device *dev, static DEVICE_ATTR_RW(enable); -static ssize_t port_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct eud_chip *chip = dev_get_drvdata(dev); - - return sysfs_emit(buf, "%u\n", chip->port_idx); -} - -static ssize_t port_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct eud_chip *chip = dev_get_drvdata(dev); - u8 port; - int ret; - - ret = kstrtou8(buf, 0, &port); - if (ret) - return ret; - - /* Only port 0 and port 1 are valid */ - if (port >= EUD_MAX_PORTS) - return -EINVAL; - - /* Port selection must be done before enabling EUD */ - if (chip->enabled) { - dev_err(chip->dev, "Cannot change port while EUD is enabled\n"); - return -EBUSY; - } - - writel(port, chip->base + EUD_REG_PORT_SEL); - chip->port_idx = port; - - return count; -} - -static DEVICE_ATTR_RW(port); - static struct attribute *eud_attrs[] = { &dev_attr_enable.attr, - &dev_attr_port.attr, NULL, }; ATTRIBUTE_GROUPS(eud); From afc8605f2383057c940ca2de77a74701682292c3 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:22:10 -0700 Subject: [PATCH 0453/1330] Revert "FROMLIST: dt-bindings: soc: qcom: eud: Restructure to model multi-path hardware" This reverts commit cfe135bf3401dee9bbb5c726594894cc453d28ea. Signed-off-by: Elson Serrao --- .../bindings/soc/qcom/qcom,eud.yaml | 100 +++++------------- 1 file changed, 26 insertions(+), 74 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index 0507252dbf27e..84218636c0d8d 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -10,11 +10,8 @@ maintainers: - Souradeep Chowdhury description: - This binding describes the Qualcomm Embedded USB Debugger (EUD), an on-chip - mini USB hub that enables USB-based debug capabilities. The EUD block is - positioned between the High-Speed USB PHY and the USB controller, where it - intercepts the UTMI interface to support debug and bypass modes. EUD can be - supported on up to two High-Speed USB ports. + This binding is used to describe the Qualcomm Embedded USB Debugger, which is + mini USB-hub implemented on chip to support USB-based debug capabilities. properties: compatible: @@ -32,62 +29,26 @@ properties: description: EUD interrupt maxItems: 1 - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - -patternProperties: - "^eud-path@[0-1]$": - type: object + ports: + $ref: /schemas/graph.yaml#/properties/ports description: - Represents one High-Speed UTMI path that EUD intercepts. This node models - the physical data path intercepted by EUD and provides graph endpoints to - link the USB controller and the external connector associated with this path. + These ports is to be attached to the endpoint of the DWC3 controller node + and type C connector node. The controller has the "usb-role-switch" + property. properties: - reg: - maxItems: 1 - description: Path number - - phys: - maxItems: 1 - description: High-Speed USB PHY associated with this data path. - - usb-role-switch: - type: boolean - description: - Set this property if the USB port on this path is role switch capable. - In device role, debug mode inserts the EUD hub into the UTMI path. In - host role, the EUD hub is bypassed and UTMI traffic flows directly - between the PHY and the USB controller. - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: - These ports are to be attached to the endpoint of the USB controller node - and USB connector node. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: This port is to be attached to the USB controller. + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: This port is to be attached to the DWC3 controller. - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: This port is to be attached to the USB connector. - - required: - - reg - - phys - - ports - - additionalProperties: false + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: This port is to be attached to the type C connector. required: - compatible - reg + - ports additionalProperties: false @@ -97,30 +58,21 @@ examples: compatible = "qcom,sc7280-eud", "qcom,eud"; reg = <0x88e0000 0x2000>, <0x88e2000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - eud-path@0 { - reg = <0>; - phys = <&usb_1_hsphy>; - usb-role-switch; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - eud_ep: endpoint { - remote-endpoint = <&usb2_role_switch>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; }; + }; - port@1 { - reg = <1>; - eud_con: endpoint { - remote-endpoint = <&con_eud>; - }; + port@1 { + reg = <1>; + eud_con: endpoint { + remote-endpoint = <&con_eud>; }; }; }; From 1fcd085d92059eef889daa7a0ef0a73e521c0209 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:22:28 -0700 Subject: [PATCH 0454/1330] =?UTF-8?q?FROMLIST:=20dt-bindings:=20connector:?= =?UTF-8?q?=20Add=20role=E2=80=91switch=20provider=20phandle?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an optional consumer→provider phandle on USB connectors to reference the USB role-switch provider when no direct graph link exists. The DRD controller remains the provider via its 'usb-role-switch' property. Link: https://lore.kernel.org/all/20260223191042.825136-2-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao --- .../devicetree/bindings/connector/usb-connector.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml index d97b29e49bf55..c55042f341fea 100644 --- a/Documentation/devicetree/bindings/connector/usb-connector.yaml +++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml @@ -95,6 +95,14 @@ properties: - device - dual + usb-role-switch: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the USB role-switch provider. The provider is typically + a dual-role (DRD) USB controller node that declares the boolean + 'usb-role-switch' property. Use this when the connector is not + directly linked to the provider in the OF graph. + typec-power-opmode: description: Determines the power operation mode that the Type C connector will support and will advertise through CC pins when it has no power From e8e14542aaac5b66a83de5938a89222d318753a0 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:23:13 -0700 Subject: [PATCH 0455/1330] FROMLIST: dt-bindings: soc: qcom: eud: Add support for dual-port configuration EUD hardware supports debugging on up to two USB ports depending on the SoC configuration. Debugging can be selected on either the primary or secondary USB port as controlled by the EUD_PORT_SELECT register. Extend the binding to support dual-port configurations by adding port@2 and port@3 for secondary USB controller and Type-C connector connections. Link: https://lore.kernel.org/all/20260309203337.803986-2-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao --- .../bindings/soc/qcom/qcom,eud.yaml | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index 84218636c0d8d..12560342f37fb 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -32,18 +32,27 @@ properties: ports: $ref: /schemas/graph.yaml#/properties/ports description: - These ports is to be attached to the endpoint of the DWC3 controller node - and type C connector node. The controller has the "usb-role-switch" - property. + These ports attach to endpoints of DWC3 controller nodes and Type-C + connector nodes. The controller has the "usb-role-switch" property. + EUD supports up to 2 USB ports. For single-port configurations, use + port@0 and port@1. For dual-port configurations, use all four ports. properties: port@0: $ref: /schemas/graph.yaml#/properties/port - description: This port is to be attached to the DWC3 controller. + description: This port is to be attached to the primary DWC3 controller. port@1: $ref: /schemas/graph.yaml#/properties/port - description: This port is to be attached to the type C connector. + description: This port is to be attached to the primary Type-C connector. + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: This port is to be attached to the secondary DWC3 controller. + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: This port is to be attached to the secondary Type-C connector. required: - compatible From 4b6c88fe9f15f297bf0bcebcaec48139e89777e6 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:23:36 -0700 Subject: [PATCH 0456/1330] FROMLIST: usb: misc: qcom_eud: add sysfs attribute for port selection EUD can be mapped to either the primary USB port or the secondary USB port depending on the value of the EUD_PORT_SEL register. Add a 'port' sysfs attribute to allow userspace to select which port EUD should operate on and update the ABI documentation. This is needed for systems with dual USB ports where EUD needs to be accessible on either port depending on the system configuration and use case. Link: https://lore.kernel.org/all/20260309203337.803986-3-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao Reviewed-by: Konrad Dybcio --- Documentation/ABI/testing/sysfs-driver-eud | 16 +++++++++ drivers/usb/misc/qcom_eud.c | 41 ++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI/testing/sysfs-driver-eud index 2bab0db2d2f0f..67223f73ee606 100644 --- a/Documentation/ABI/testing/sysfs-driver-eud +++ b/Documentation/ABI/testing/sysfs-driver-eud @@ -7,3 +7,19 @@ Description: EUD based on a 1 or a 0 value. By enabling EUD, the user is able to activate the mini-usb hub of EUD for debug and trace capabilities. + +What: /sys/bus/platform/drivers/qcom_eud/.../port +Date: January 2026 +Contact: Elson Serrao +Description: + Selects which USB port the Embedded USB Debugger (EUD) + is mapped to on platforms providing multiple High-Speed + USB ports. + + Valid values: + 0 - Primary USB port + 1 - Secondary USB port + + The attribute is writable only while EUD is disabled. + Reading the attribute returns the currently selected + USB port number. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 926419ca560fc..35324e1e1ea7e 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -23,8 +23,11 @@ #define EUD_REG_VBUS_INT_CLR 0x0080 #define EUD_REG_CSR_EUD_EN 0x1014 #define EUD_REG_SW_ATTACH_DET 0x1018 +#define EUD_REG_PORT_SEL 0x1028 #define EUD_REG_EUD_EN2 0x0000 +#define EUD_MAX_PORTS 2 + #define EUD_ENABLE BIT(0) #define EUD_INT_PET_EUD BIT(0) #define EUD_INT_VBUS BIT(2) @@ -40,6 +43,7 @@ struct eud_chip { int irq; bool enabled; bool usb_attached; + u8 port_idx; }; static int enable_eud(struct eud_chip *priv) @@ -104,8 +108,45 @@ static ssize_t enable_store(struct device *dev, static DEVICE_ATTR_RW(enable); +static ssize_t port_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct eud_chip *chip = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u\n", chip->port_idx); +} + +static ssize_t port_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct eud_chip *chip = dev_get_drvdata(dev); + u8 port; + int ret; + + ret = kstrtou8(buf, 0, &port); + if (ret) + return ret; + + /* Only port 0 and port 1 are valid */ + if (port >= EUD_MAX_PORTS) + return -EINVAL; + + /* Port selection must be done before enabling EUD */ + if (chip->enabled) { + dev_err(chip->dev, "Cannot change port while EUD is enabled\n"); + return -EBUSY; + } + + writel(port, chip->base + EUD_REG_PORT_SEL); + chip->port_idx = port; + + return count; +} + +static DEVICE_ATTR_RW(port); + static struct attribute *eud_attrs[] = { &dev_attr_enable.attr, + &dev_attr_port.attr, NULL, }; ATTRIBUTE_GROUPS(eud); From 5b8fe60d04a9e3f348e350a156de2ed6619eb0dc Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:25:35 -0700 Subject: [PATCH 0457/1330] FROMLIST: usb: misc: qcom_eud: add per-port High-Speed PHY control EUD hardware can support multiple High-Speed USB ports, each routed through its own PHY. The active port is selected in hardware via the EUD_PORT_SEL register. As a High-Speed hub, EUD requires access to the High-Speed PHY associated with the active port. To support this multi-port capability, the driver must manage PHY resources on a per-port basis, ensuring that the PHY for the currently selected port is properly initialized and powered. This patch adds per-port PHY management to the driver. The driver now powers the appropriate PHY based on the selected and enabled port, ensuring correct operation when EUD is enabled. Historically, EUD appeared to work on single-port systems because the USB controller kept the PHY initialized. However, EUD is designed to operate independently of the USB controller and therefore requires explicit PHY control for proper operation. Link: https://lore.kernel.org/all/20260309203337.803986-4-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao --- drivers/usb/misc/Kconfig | 1 + drivers/usb/misc/qcom_eud.c | 103 +++++++++++++++++++++++++++++++++++- 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 0b56b773dbdf7..2d9190c756f9c 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -147,6 +147,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" depends on ARCH_QCOM || COMPILE_TEST + depends on OF select QCOM_SCM select USB_ROLE_SWITCH help diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 35324e1e1ea7e..571b21323797b 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include @@ -37,23 +39,75 @@ struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + struct phy *phy[EUD_MAX_PORTS]; void __iomem *base; phys_addr_t mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + bool phy_enabled; u8 port_idx; }; +static int eud_phy_enable(struct eud_chip *chip) +{ + struct phy *phy; + int ret; + + if (chip->phy_enabled) + return 0; + + phy = chip->phy[chip->port_idx]; + + ret = phy_init(phy); + if (ret) { + dev_err(chip->dev, "Failed to initialize USB2 PHY for port %u: %d\n", + chip->port_idx, ret); + return ret; + } + + ret = phy_power_on(phy); + if (ret) { + dev_err(chip->dev, "Failed to power on USB2 PHY for port %u: %d\n", + chip->port_idx, ret); + phy_exit(phy); + return ret; + } + + chip->phy_enabled = true; + + return 0; +} + +static void eud_phy_disable(struct eud_chip *chip) +{ + struct phy *phy; + + if (!chip->phy_enabled) + return; + + phy = chip->phy[chip->port_idx]; + + phy_power_off(phy); + phy_exit(phy); + chip->phy_enabled = false; +} + static int enable_eud(struct eud_chip *priv) { int ret; - ret = qcom_scm_io_writel(priv->mode_mgr + EUD_REG_EUD_EN2, 1); + ret = eud_phy_enable(priv); if (ret) return ret; + ret = qcom_scm_io_writel(priv->mode_mgr + EUD_REG_EUD_EN2, 1); + if (ret) { + eud_phy_disable(priv); + return ret; + } + writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); @@ -70,6 +124,8 @@ static int disable_eud(struct eud_chip *priv) return ret; writel(0, priv->base + EUD_REG_CSR_EUD_EN); + eud_phy_disable(priv); + return 0; } @@ -130,6 +186,11 @@ static ssize_t port_store(struct device *dev, struct device_attribute *attr, if (port >= EUD_MAX_PORTS) return -EINVAL; + if (!chip->phy[port]) { + dev_err(chip->dev, "EUD not supported on selected port\n"); + return -EOPNOTSUPP; + } + /* Port selection must be done before enabling EUD */ if (chip->enabled) { dev_err(chip->dev, "Cannot change port while EUD is enabled\n"); @@ -222,6 +283,35 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) return IRQ_HANDLED; } +static int eud_parse_dt_port(struct eud_chip *chip, u8 port_id) +{ + struct device_node *controller_node; + struct phy *phy; + + /* + * Multiply port_id by 2 to get controller port number: + * port_id 0 -> port@0 (primary USB controller) + * port_id 1 -> port@2 (secondary USB controller) + */ + controller_node = of_graph_get_remote_node(chip->dev->of_node, + port_id * 2, -1); + if (!controller_node) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get controller node for port %u\n", port_id); + + phy = devm_of_phy_get_by_index(chip->dev, controller_node, 0); + if (IS_ERR(phy)) { + of_node_put(controller_node); + return dev_err_probe(chip->dev, PTR_ERR(phy), + "failed to get HS PHY for port %u\n", port_id); + } + chip->phy[port_id] = phy; + + of_node_put(controller_node); + + return 0; +} + static void eud_role_switch_release(void *data) { struct eud_chip *chip = data; @@ -241,6 +331,17 @@ static int eud_probe(struct platform_device *pdev) chip->dev = &pdev->dev; + /* + * Parse the DT resources for primary port. + * This is the default EUD port and is mandatory. + */ + ret = eud_parse_dt_port(chip, 0); + if (ret) + return ret; + + /* Secondary port is optional */ + eud_parse_dt_port(chip, 1); + chip->role_sw = usb_role_switch_get(&pdev->dev); if (IS_ERR(chip->role_sw)) return dev_err_probe(chip->dev, PTR_ERR(chip->role_sw), From 1dc9379a93b157edfe246f6536badb17c7ae9e70 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:25:36 -0700 Subject: [PATCH 0458/1330] FROMLIST: usb: misc: qcom_eud: add per-port role switch support The EUD hardware can support multiple High-Speed USB ports, each connected to different USB controllers. The current implementation uses a single chip-level role switch, which cannot properly handle multi-port configurations where each USB port can operate in different role. Restructure the driver to support per-port role switches. Additionally, remove the unnecessary role switch call from enable_eud() as EUD need not modify the USB role upon enabling. Link: https://lore.kernel.org/all/20260309203337.803986-5-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao --- drivers/usb/misc/qcom_eud.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 571b21323797b..c484fc88dea4d 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -38,7 +38,7 @@ struct eud_chip { struct device *dev; - struct usb_role_switch *role_sw; + struct usb_role_switch *role_sw[EUD_MAX_PORTS]; struct phy *phy[EUD_MAX_PORTS]; void __iomem *base; phys_addr_t mode_mgr; @@ -112,7 +112,7 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); + return 0; } static int disable_eud(struct eud_chip *priv) @@ -270,9 +270,9 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) int ret; if (chip->usb_attached) - ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_DEVICE); + ret = usb_role_switch_set_role(chip->role_sw[chip->port_idx], USB_ROLE_DEVICE); else - ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_HOST); + ret = usb_role_switch_set_role(chip->role_sw[chip->port_idx], USB_ROLE_HOST); if (ret) dev_err(chip->dev, "failed to set role switch\n"); @@ -287,6 +287,7 @@ static int eud_parse_dt_port(struct eud_chip *chip, u8 port_id) { struct device_node *controller_node; struct phy *phy; + struct usb_role_switch *role_sw; /* * Multiply port_id by 2 to get controller port number: @@ -307,16 +308,31 @@ static int eud_parse_dt_port(struct eud_chip *chip, u8 port_id) } chip->phy[port_id] = phy; + /* Only fetch role switch if usb-role-switch property exists */ + if (!of_property_read_bool(controller_node, "usb-role-switch")) { + of_node_put(controller_node); + return 0; + } + + role_sw = usb_role_switch_find_by_fwnode(of_fwnode_handle(controller_node)); of_node_put(controller_node); + if (!role_sw) + return dev_err_probe(chip->dev, -EPROBE_DEFER, + "failed to get role switch for port %u\n", port_id); + + chip->role_sw[port_id] = role_sw; + return 0; } static void eud_role_switch_release(void *data) { struct eud_chip *chip = data; + int i; - usb_role_switch_put(chip->role_sw); + for (i = 0; i < EUD_MAX_PORTS; i++) + usb_role_switch_put(chip->role_sw[i]); } static int eud_probe(struct platform_device *pdev) @@ -342,11 +358,6 @@ static int eud_probe(struct platform_device *pdev) /* Secondary port is optional */ eud_parse_dt_port(chip, 1); - chip->role_sw = usb_role_switch_get(&pdev->dev); - if (IS_ERR(chip->role_sw)) - return dev_err_probe(chip->dev, PTR_ERR(chip->role_sw), - "failed to get role switch\n"); - ret = devm_add_action_or_reset(chip->dev, eud_role_switch_release, chip); if (ret) return ret; From cee1bf06fcfaf9bccd2a15ed9707d5335c1885fe Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:25:36 -0700 Subject: [PATCH 0459/1330] FROMLIST: usb: misc: qcom_eud: improve enable_store API Currently enable_store() allows operations irrespective of the EUD state, which can result in redundant operations. Avoid this by adding duplicate state checks to skip requests when EUD is already in the desired state. Additionally, improve error handling with explicit logging to provide better feedback. Link: https://lore.kernel.org/all/20260309203337.803986-6-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao Reviewed-by: Konrad Dybcio --- drivers/usb/misc/qcom_eud.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index c484fc88dea4d..eee79774f5f8d 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -148,18 +148,27 @@ static ssize_t enable_store(struct device *dev, if (kstrtobool(buf, &enable)) return -EINVAL; + /* Skip operation if already in desired state */ + if (chip->enabled == enable) + return count; + if (enable) { ret = enable_eud(chip); - if (!ret) - chip->enabled = enable; - else - disable_eud(chip); - + if (ret) { + dev_err(chip->dev, "failed to enable eud\n"); + return ret; + } } else { ret = disable_eud(chip); + if (ret) { + dev_err(chip->dev, "failed to disable eud\n"); + return ret; + } } - return ret < 0 ? ret : count; + chip->enabled = enable; + + return count; } static DEVICE_ATTR_RW(enable); From a1094bc3b51d75e4fed865e91fec027e4e1ad245 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:25:36 -0700 Subject: [PATCH 0460/1330] FROMLIST: usb: misc: qcom_eud: fix virtual attach/detach event handling EUD provides virtual USB attach/detach events to simulate cable plug/unplug while maintaining the physical debug connection. However, the current implementation incorrectly sets the USB role to HOST on virtual detach, which doesn't represent the disconnected state. Fix the virtual detach handling by setting the USB role to NONE instead of HOST, correctly representing the disconnected state. Link: https://lore.kernel.org/all/20260309203337.803986-7-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao Reviewed-by: Konrad Dybcio --- drivers/usb/misc/qcom_eud.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index eee79774f5f8d..ae0c5b2f022a2 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -278,10 +278,26 @@ static irqreturn_t handle_eud_irq_thread(int irq, void *data) struct eud_chip *chip = data; int ret; + /* + * EUD virtual attach/detach event handling for low power debugging: + * + * When EUD is enabled in debug mode, the device remains physically + * connected to the PC throughout the debug session, keeping the USB + * controller active. This prevents testing of low power scenarios that + * require USB disconnection. + * + * EUD solves this by providing virtual USB attach/detach events while + * maintaining the physical connection. These events are triggered from + * the Host PC via the enumerated EUD control interface and delivered + * to the EUD driver as interrupts. + * + * These notifications are forwarded to the USB controller through role + * switch framework. + */ if (chip->usb_attached) ret = usb_role_switch_set_role(chip->role_sw[chip->port_idx], USB_ROLE_DEVICE); else - ret = usb_role_switch_set_role(chip->role_sw[chip->port_idx], USB_ROLE_HOST); + ret = usb_role_switch_set_role(chip->role_sw[chip->port_idx], USB_ROLE_NONE); if (ret) dev_err(chip->dev, "failed to set role switch\n"); From 24eca626cd406665101e4fe7984350b15228f25c Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:25:37 -0700 Subject: [PATCH 0461/1330] FROMLIST: usb: misc: qcom_eud: add host mode coordination EUD functions by presenting itself as a USB device to the host PC for debugging, making it incompatible with USB host mode configurations. Handle below two scenarios to prevent these conflicts: 1. Prevent user from enabling EUD via sysfs when the USB port is in host mode. 2. Automatically disable EUD when USB port switches to host mode and re-enable it when exiting host mode. This is achieved via the exported qcom_eud_usb_role_notify() API that allows the USB controller driver to notify EUD of role changes. This ensures consistent state management without creating conflicts between the EUD debug hub and the USB controller. Link: https://lore.kernel.org/all/20260309203337.803986-8-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao --- drivers/usb/misc/qcom_eud.c | 110 ++++++++++++++++++++++++++++++++++- include/linux/usb/qcom_eud.h | 21 +++++++ 2 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 include/linux/usb/qcom_eud.h diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index ae0c5b2f022a2..5b5cf11d6f526 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -12,11 +12,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #define EUD_REG_INT1_EN_MASK 0x0024 @@ -42,11 +44,14 @@ struct eud_chip { struct phy *phy[EUD_MAX_PORTS]; void __iomem *base; phys_addr_t mode_mgr; + /* serializes EUD control operations */ + struct mutex state_lock; unsigned int int_status; int irq; bool enabled; bool usb_attached; bool phy_enabled; + bool eud_disabled_for_host; u8 port_idx; }; @@ -142,17 +147,43 @@ static ssize_t enable_store(struct device *dev, const char *buf, size_t count) { struct eud_chip *chip = dev_get_drvdata(dev); + enum usb_role role; bool enable; int ret; if (kstrtobool(buf, &enable)) return -EINVAL; + guard(mutex)(&chip->state_lock); + /* Skip operation if already in desired state */ if (chip->enabled == enable) return count; + /* + * Handle double-disable scenario: User is disabling EUD that was already + * disabled due to host mode. Since the hardware is already disabled, we + * only need to clear the host-disabled flag to prevent unwanted re-enabling + * when exiting host mode. This respects the user's explicit disable request. + */ + if (!enable && chip->eud_disabled_for_host) { + chip->eud_disabled_for_host = false; + chip->enabled = false; + return count; + } + if (enable) { + /* + * EUD functions by presenting itself as a USB device to the host PC for + * debugging, making it incompatible with USB host mode configuration. + * Prevent enabling EUD in this configuration to avoid hardware conflicts. + */ + role = usb_role_switch_get_role(chip->role_sw[chip->port_idx]); + if (role == USB_ROLE_HOST) { + dev_err(chip->dev, "Cannot enable EUD: USB port is in host mode\n"); + return -EBUSY; + } + ret = enable_eud(chip); if (ret) { dev_err(chip->dev, "failed to enable eud\n"); @@ -351,6 +382,75 @@ static int eud_parse_dt_port(struct eud_chip *chip, u8 port_id) return 0; } +/** + * qcom_eud_usb_role_notify - Notify EUD of USB role change + * @eud_node: Device node of the EUD device + * @phy: HSUSB PHY of the port changing role + * @role: New role being set + * + * Notifies EUD that a USB port is changing roles. EUD will disable itself + * if the port is switching to HOST mode, as EUD is incompatible with host + * mode operation. This API should be called by the USB controller driver + * when it switches the USB role. + * + * The PHY parameter is used to identify which physical USB port is changing + * roles. This is important in multi-port systems where EUD may be active on + * one port while another port changes roles. + * + * This is a best-effort notification - failures are logged but do not affect + * the role change operation. + */ +void qcom_eud_usb_role_notify(struct device_node *eud_node, struct phy *phy, + enum usb_role role) +{ + struct platform_device *pdev; + struct eud_chip *chip; + int ret; + + if (!of_device_is_compatible(eud_node, "qcom,eud")) + return; + + pdev = of_find_device_by_node(eud_node); + if (!pdev) + return; + + chip = platform_get_drvdata(pdev); + if (!chip) + goto put_dev; + + mutex_lock(&chip->state_lock); + + /* Only act if this notification is for the currently active EUD port */ + if (!chip->enabled || chip->phy[chip->port_idx] != phy) { + mutex_unlock(&chip->state_lock); + goto put_dev; + } + + /* + * chip->enabled preserves user's sysfs configuration and is not modified + * during host mode transitions to preserve user intent. + */ + if (role == USB_ROLE_HOST && !chip->eud_disabled_for_host) { + ret = disable_eud(chip); + if (ret) + dev_err(chip->dev, "Failed to disable EUD for host mode: %d\n", ret); + else + chip->eud_disabled_for_host = true; + } else if (role != USB_ROLE_HOST && chip->eud_disabled_for_host) { + ret = enable_eud(chip); + if (ret) + dev_err(chip->dev, "Failed to re-enable EUD after host mode: %d\n", ret); + else + chip->eud_disabled_for_host = false; + } + + mutex_unlock(&chip->state_lock); + +put_dev: + platform_device_put(pdev); +} +EXPORT_SYMBOL_GPL(qcom_eud_usb_role_notify); + static void eud_role_switch_release(void *data) { struct eud_chip *chip = data; @@ -372,6 +472,8 @@ static int eud_probe(struct platform_device *pdev) chip->dev = &pdev->dev; + mutex_init(&chip->state_lock); + /* * Parse the DT resources for primary port. * This is the default EUD port and is mandatory. @@ -416,8 +518,14 @@ static void eud_remove(struct platform_device *pdev) { struct eud_chip *chip = platform_get_drvdata(pdev); - if (chip->enabled) + platform_set_drvdata(pdev, NULL); + + mutex_lock(&chip->state_lock); + if (chip->enabled) { disable_eud(chip); + chip->enabled = false; + } + mutex_unlock(&chip->state_lock); device_init_wakeup(&pdev->dev, false); disable_irq_wake(chip->irq); diff --git a/include/linux/usb/qcom_eud.h b/include/linux/usb/qcom_eud.h new file mode 100644 index 0000000000000..fe560426b78f3 --- /dev/null +++ b/include/linux/usb/qcom_eud.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __LINUX_USB_QCOM_EUD_H +#define __LINUX_USB_QCOM_EUD_H + +#include + +#if IS_ENABLED(CONFIG_USB_QCOM_EUD) +void qcom_eud_usb_role_notify(struct device_node *eud_node, struct phy *phy, + enum usb_role role); +#else +static inline void qcom_eud_usb_role_notify(struct device_node *eud_node, struct phy *phy, + enum usb_role role) +{ +} +#endif + +#endif /* __LINUX_USB_QCOM_EUD_H */ From f77ab9bbf6835eabebbeb64cdc5b0969711c52c6 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:25:37 -0700 Subject: [PATCH 0462/1330] FROMLIST: usb: dwc3: qcom: notify EUD driver of role changes The EUD driver needs USB role information to control its operation as it is incompatible with host mode. Notify the EUD driver when role changes occur so it can manage its state accordingly. Link: https://lore.kernel.org/all/20260309203337.803986-9-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao --- drivers/usb/dwc3/Kconfig | 1 + drivers/usb/dwc3/dwc3-qcom.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 240b15bc52cbd..1a2d7c883b50d 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -132,6 +132,7 @@ config USB_DWC3_QCOM depends on ARCH_QCOM || COMPILE_TEST depends on EXTCON || !EXTCON depends on OF + depends on USB_QCOM_EUD || !USB_QCOM_EUD default USB_DWC3 help Some Qualcomm SoCs use DesignWare Core IP for USB2/3 diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 9ac75547820d9..b51fd97521df3 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include "core.h" #include "glue.h" @@ -561,6 +563,7 @@ static int dwc3_qcom_setup_irq(struct dwc3_qcom *qcom, struct platform_device *p static void dwc3_qcom_set_role_notifier(struct dwc3 *dwc, enum usb_role next_role) { struct dwc3_qcom *qcom = to_dwc3_qcom(dwc); + struct device_node *eud_node; if (qcom->current_role == next_role) return; @@ -570,6 +573,13 @@ static void dwc3_qcom_set_role_notifier(struct dwc3 *dwc, enum usb_role next_rol return; } + /* Notify EUD of role change */ + eud_node = of_graph_get_remote_node(qcom->dev->of_node, 0, -1); + if (eud_node) { + qcom_eud_usb_role_notify(eud_node, dwc->usb2_generic_phy[0], next_role); + of_node_put(eud_node); + } + if (qcom->current_role == USB_ROLE_DEVICE) dwc3_qcom_vbus_override_enable(qcom, false); else if (qcom->current_role != USB_ROLE_DEVICE) From b16b24dc4939aa53d95aa7d0b7b562ba460b3c68 Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:25:38 -0700 Subject: [PATCH 0463/1330] FROMLIST: arm64: dts: qcom: kodiak: Fix EUD USB controller connection The EUD node is currently mapped to the secondary USB controller. This SoC only supports EUD on the primary High-Speed USB path. Fix the graph connections to properly map EUD to the primary USB controller. Add an empty connector endpoint for board DTS files to complete the connection. Also enable EUD so debug is available by default on this SoC. Link: https://lore.kernel.org/all/20260309203337.803986-10-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index a67a550302c6f..24b240492cf4c 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -4307,12 +4307,6 @@ phy-names = "usb2-phy"; maximum-speed = "high-speed"; usb-role-switch; - - port { - usb2_role_switch: endpoint { - remote-endpoint = <&eud_ep>; - }; - }; }; qspi: spi@88dc000 { @@ -4636,16 +4630,22 @@ <0 0x88e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; + eud_ep: endpoint { - remote-endpoint = <&usb2_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + eud_con: endpoint { }; }; }; @@ -4879,6 +4879,7 @@ reg = <0>; usb_1_dwc3_hs: endpoint { + remote-endpoint = <&eud_ep>; }; }; From 74b0963dd23a20131724f8649b261048da2ab8ca Mon Sep 17 00:00:00 2001 From: Elson Serrao Date: Tue, 24 Mar 2026 15:25:38 -0700 Subject: [PATCH 0464/1330] FROMLIST: arm64: dts: qcom: Map USB connector to EUD for kodiak boards Map the USB connector HS endpoint to EUD for debug functionality on all boards using kodiak.dtsi. Since the controller is no longer a direct neighbor of the connector, add usb-role-switch phandle to map the USB role switch provider for this connector. Link: https://lore.kernel.org/all/20260309203337.803986-11-elson.serrao@oss.qualcomm.com/ Signed-off-by: Elson Serrao --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 11 ++++++----- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 11 ++++++----- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 11 ++++++----- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 11 ++++++----- .../boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 11 ++++++----- arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts | 11 ++++++----- 6 files changed, 36 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 455e5c9bb072a..dbd968967dd54 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -88,6 +88,7 @@ reg = <0>; power-role = "dual"; data-role = "dual"; + usb-role-switch = <&usb_1>; ports { #address-cells = <1>; @@ -97,7 +98,7 @@ reg = <0>; pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; + remote-endpoint = <&eud_con>; }; }; @@ -1433,10 +1434,6 @@ status = "okay"; }; -&usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c>; vdda18-supply = <&vreg_l1c>; @@ -1476,3 +1473,7 @@ qcom,calibration-variant = "Fairphone_5"; status = "okay"; }; + +&eud_con { + remote-endpoint = <&pmic_glink_hs_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index bf18c48520813..ca9c1a09ca733 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -65,6 +65,7 @@ reg = <0>; power-role = "dual"; data-role = "dual"; + usb-role-switch = <&usb_1>; ports { #address-cells = <1>; @@ -74,7 +75,7 @@ reg = <0>; pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; + remote-endpoint = <&eud_con>; }; }; @@ -826,10 +827,6 @@ status = "okay"; }; -&usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c_0p88>; vdda33-supply = <&vreg_l2b_3p072>; @@ -862,3 +859,7 @@ &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; + +&eud_con { + remote-endpoint = <&pmic_glink_hs_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 797f37596bf19..eb7e228787c24 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -75,6 +75,7 @@ reg = <0>; power-role = "dual"; data-role = "dual"; + usb-role-switch = <&usb_1>; ports { #address-cells = <1>; @@ -84,7 +85,7 @@ reg = <0>; pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; + remote-endpoint = <&eud_con>; }; }; @@ -952,10 +953,6 @@ status = "okay"; }; -&usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c>; vdda18-supply = <&vreg_l1c>; @@ -986,6 +983,10 @@ remote-endpoint = <&pmic_glink_ss_in>; }; +&eud_con { + remote-endpoint = <&pmic_glink_hs_in>; +}; + &venus { firmware-name = "qcom/qcm6490/SHIFT/otter/venus.mbn"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index cdc3977daa5c4..85cc24079a24f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -191,6 +191,7 @@ reg = <0>; power-role = "dual"; data-role = "dual"; + usb-role-switch = <&usb_1>; ports { #address-cells = <1>; @@ -200,7 +201,7 @@ reg = <0>; pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; + remote-endpoint = <&eud_con>; }; }; @@ -1672,14 +1673,14 @@ status = "okay"; }; -&usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - &usb_1_dwc3_ss { remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; +&eud_con { + remote-endpoint = <&pmic_glink_hs_in>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c_0p88>; vdda33-supply = <&vreg_l2b_3p072>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index f47efca42d48d..05cd73b5bcbe2 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -84,6 +84,7 @@ reg = <0>; power-role = "dual"; data-role = "dual"; + usb-role-switch = <&usb_1>; ports { #address-cells = <1>; @@ -93,7 +94,7 @@ reg = <0>; pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; + remote-endpoint = <&eud_con>; }; }; @@ -1090,10 +1091,6 @@ status = "okay"; }; -&usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c_0p88>; vdda33-supply = <&vreg_l2b_3p072>; @@ -1127,6 +1124,10 @@ remote-endpoint = <&pmic_glink_ss_in>; }; +&eud_con { + remote-endpoint = <&pmic_glink_hs_in>; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l7b_2p952>; diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index cb59c122f6f6a..f99a47334452f 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -90,6 +90,7 @@ reg = <0>; power-role = "dual"; data-role = "dual"; + usb-role-switch = <&usb_1>; ports { #address-cells = <1>; @@ -99,7 +100,7 @@ reg = <0>; pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; + remote-endpoint = <&eud_con>; }; }; @@ -1440,10 +1441,6 @@ status = "okay"; }; -&usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - &usb_1_hsphy { vdda-pll-supply = <&vdd_a_usbhs_core>; vdda18-supply = <&vdd_a_usbhs_1p8>; @@ -1459,3 +1456,7 @@ &wifi { status = "okay"; }; + +&eud_con { + remote-endpoint = <&pmic_glink_hs_in>; +}; From 5127a35357c42a8da4ef7b4bf82198ffb3fad313 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Fri, 13 Mar 2026 18:20:40 +0530 Subject: [PATCH 0465/1330] FROMLIST: arm64: dts: qcom: purwa-iot-evk: Enable UFS Enable UFS for purwa-iot-evk board. This patch depends on [PATCH V5 2/3] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC https://lore.kernel.org/all/20260211132926.3716716-3-pradeep.pragallapati@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260323-purwa-ufs-v2-1-58fb2c168786@oss.qualcomm.com/ Signed-off-by: Pradeep P V K --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index fe539b1f45677..f26f8b6487381 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -1497,6 +1497,24 @@ status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + &usb_1_ss0_dwc3_hs { remote-endpoint = <&pmic_glink_ss0_hs_in>; }; From f19f2fabfc1b2d4c007a7d4932b36a463bda21dc Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Mon, 23 Mar 2026 16:30:17 +0530 Subject: [PATCH 0466/1330] FROMLIST: arm64: dts: qcom: purwa-iot-evk: Add SDC2 node for purwa iot evk board Enable SD Card host controller for purwa iot evk board. Signed-off-by: Sarthak Garg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260323110017.2527956-1-sarthak.garg@oss.qualcomm.com Signed-off-by: Bjorn Andersson Signed-off-by: Pradeep P V K --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index f26f8b6487381..ad503beec1d3d 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -1180,6 +1180,22 @@ status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &smb2360_0 { status = "okay"; }; @@ -1362,6 +1378,13 @@ bias-disable; }; + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { pins = "gpio188"; function = "gpio"; From 38459da95b8782fb479456d467456b758675fc65 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 24 Mar 2026 20:38:37 +0530 Subject: [PATCH 0467/1330] arm64: dts: qcom: Shikra: Add reserved memory nodes Add the reserved memory nodes for Shikra. Signed-off-by: Bibek Kumar Patro --- arch/arm64/boot/dts/qcom/shikra.dtsi | 107 ++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index d5076652660aa..52723a7b3553b 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -102,9 +102,114 @@ interrupts = ; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x1600000>; + no-map; + }; + + xblboot_mem: xblboot@85e00000 { + reg = <0x0 0x85e00000 0x0 0x100000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@85fff000 { + reg = <0x0 0x85fff000 0x0 0x1000>; + no-map; + }; + + audio_heap_mem: audio-heap@86200000 { + reg = <0x0 0x86200000 0x0 0x100000>; + no-map; + }; + + pvm_fw_mem: pvm-fw@86300000 { + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + }; + + /* UEFI region at 0x9F400000 is reclaimed by Linux */ + tz_stat_mem: tz-stat@a0000000 { + reg = <0x0 0xa0000000 0x0 0x100000>; + no-map; + }; + + qtee_mem: qtee@a1300000 { + reg = <0x0 0xa1300000 0x0 0x500000>; + no-map; + }; + + tz_apps_mem: tz-apps@a1800000 { + reg = <0x0 0xa1800000 0x0 0x2100000>; + no-map; + }; + + va_md_mem: va-md-mem { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0x1000000>; + reusable; + }; + + kinfo_mem: debug-kinfo { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; + + mpss_wlan_mem: mpss-wlan@ab000000 { + reg = <0x0 0xab000000 0x0 0x6e00000>; + no-map; + }; + + wlan_mem: wlan@b2300000 { + reg = <0x0 0xb2300000 0x0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@b2400000 { + reg = <0x0 0xb2400000 0x0 0x1900000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code@b3d00000 { + reg = <0x0 0xb3d00000 0x0 0x2000>; + no-map; + }; + + video_mem: video@b3d02000 { + reg = <0x0 0xb3d02000 0x0 0x700000>; + no-map; + }; + + lmcu_mem: lmcu@b4402000 { + reg = <0x0 0xb4402000 0x0 0x300000>; + no-map; + }; + + lmcu_dtb_mem: lmcu-dtb@b4702000 { + reg = <0x0 0xb4702000 0x0 0x40000>; + no-map; + }; + + /* Linux kernel image is loaded at 0xB5000000 */ + trust_ui_vm_mem: trust-ui-vm@f3800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf3800000 0x0 0x4000000>; + alignment = <0x0 0x400000>; + reusable; + }; + + oem_vm_mem: oem-vm@f7c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf7c00000 0x0 0x4c00000>; + alignment = <0x0 0x400000>; + reusable; + }; }; soc: soc@0 { From f9fb96c28a6d2d5426e3f318e8be77f872d383cf Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Mon, 23 Mar 2026 16:33:37 +0530 Subject: [PATCH 0468/1330] FROMLIST: arm64: dts: qcom: sm8750-mtp: Set sufficient voltage for panel nt37801 The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states VDDI=1.65V~1.95V, so set sufficient voltage for panel nt37801. Signed-off-by: Ayushi Makhija Link: https://lore.kernel.org/all/20260323102229.1546504-1-quic_amakhija@quicinc.com/ Signed-off-by: Arpit Saini --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 050a85df7358d..11d6fdc44e620 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -452,7 +452,7 @@ vreg_l12b_1p8: ldo12 { regulator-name = "vreg_l12b_1p8"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; regulator-allow-set-load; From d8884cee670cd291f36ce4fdb3e0d5dc912549b0 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Thu, 26 Mar 2026 15:11:01 +0530 Subject: [PATCH 0469/1330] dt-bindings: arm-smmu: Add adreno-smmu compatible for Shikra SoC Qualcomm Shikra SoC implements qcom,smmu-500 for adreno-smmu. Document its corresponding compatible. Signed-off-by: Bibek Kumar Patro --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 7a7224a252f97..af9fa49706b54 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -104,6 +104,7 @@ properties: - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 + - qcom,shikra-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm8150-smmu-500 From 17cc556aa53b6d163cb0bedfd99f9001f33057d1 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Tue, 27 Jan 2026 13:43:04 +0530 Subject: [PATCH 0470/1330] mailbox: qcom-apcs-ipc-mailbox: Add compatible string Add "qcom,shikra-apcs-hmss-global" compatibility string in qcom_apcs_ipc mailbox driver to match apcs_glb device node. Signed-off-by: Vishnu Santhosh --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index d3a8f6b4a03b3..8e544dbe3c5ff 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -168,6 +168,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data }, { .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data }, + { .compatible = "qcom,shikra-apcs-hmss-global", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, {} }; From 192e9418a1cac40f534517d28b586cf573024ba5 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Thu, 26 Mar 2026 12:36:51 +0530 Subject: [PATCH 0471/1330] arm64: dts: qcom: Shikra: add smmu nodes Add the apps and adreno smmu node as found in Shikra SoC. Signed-off-by: Bibek Kumar Patro --- arch/arm64/boot/dts/qcom/shikra.dtsi | 91 ++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 52723a7b3553b..9c20b1476d707 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -242,6 +242,23 @@ }; }; + adreno_smmu: iommu@59a0000 { + compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x059a0000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + ; + }; + sram@c11e000 { compatible = "qcom,shikra-imem", "syscon", "simple-mfd"; reg = <0x0 0x0c11e000 0x0 0x1000>; @@ -256,6 +273,80 @@ }; }; + apps_smmu: iommu@c600000 { + compatible = "qcom,shikra-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x0c600000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf200000 0x0 0x10000>, /* GICD */ From b872c3961e66c8e039650d654aa9d3de38893359 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Mon, 16 Mar 2026 21:08:23 +0530 Subject: [PATCH 0472/1330] dt-bindings: mailbox: qcom,apcs-kpss-global: Add Shikra compatible Add qcom,shikra-apcs-hmss-global for the APCS mailbox binding. This avoids undocumented-compatible warnings from checkpatch and keeps schema constraints aligned for this target. Signed-off-by: Vishnu Santhosh --- .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 ++ Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml | 1 + 2 files changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index f40dc90483272..bc1dc44fc2de8 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -65,6 +65,7 @@ properties: - qcom,msm8996-apcs-hmss-global - qcom,qcm2290-apcs-hmss-global - qcom,sdm845-apss-shared + - qcom,shikra-apcs-hmss-global reg: maxItems: 1 @@ -238,6 +239,7 @@ allOf: - qcom,msm8996-apcs-hmss-global - qcom,qcm2290-apcs-hmss-global - qcom,sdm845-apss-shared + - qcom,shikra-apcs-hmss-global then: properties: clocks: false diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml index 540bdfca53d97..823304afaa98f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml @@ -87,6 +87,7 @@ properties: - qcom,qcm2290-rpm-proc - qcom,qcs404-rpm-proc - qcom,sdm660-rpm-proc + - qcom,shikra-rpm-proc - qcom,sm6115-rpm-proc - qcom,sm6125-rpm-proc - qcom,sm6375-rpm-proc From 50c707b94b70b07a57aedcaa7d07b46ad0144495 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Mon, 16 Mar 2026 21:08:23 +0530 Subject: [PATCH 0473/1330] arm64: dts: qcom: Add RPM GLINK transport nodes Add the RPM message RAM SRAM region and APCS HMSS global mailbox controller, and wire them up to a new glink-edge node. The rpm_msg_ram node exposes the shared SRAM used for GLINK FIFOs and includes the apss_mpm sub-node for the MPM sleep counter. The `qcom,glink-rpm` transport uses: - `qcom,rpm-msg-ram` for shared GLINK FIFOs - APCS mailbox channel 0 for kick/notify This enables RPM GLINK-based inter-processor communication on Shikra. Signed-off-by: Vishnu Santhosh --- arch/arm64/boot/dts/qcom/shikra.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 9c20b1476d707..a7bb3ef8f24d9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -102,6 +102,17 @@ interrupts = ; }; + rpm: remoteproc { + compatible = "qcom,shikra-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -242,6 +253,19 @@ }; }; + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram", "mmio-sram"; + reg = <0x0 0x045f0000 0x0 0x7000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x045f0000 0x7000>; + + apss_mpm: sram@1b8 { + reg = <0x1b8 0x48>; + }; + }; + adreno_smmu: iommu@59a0000 { compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x059a0000 0x0 0x10000>; @@ -365,6 +389,12 @@ ranges; }; + apcs_glb: mailbox@f400000 { + compatible = "qcom,shikra-apcs-hmss-global"; + reg = <0x0 0x0f400000 0x0 0x1000>; + #mbox-cells = <1>; + }; + timer@f420000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0f420000 0x0 0x1000>; From 682e717bd8fcce49da9661570c2c4539bc60ece6 Mon Sep 17 00:00:00 2001 From: Shuai Zhang Date: Thu, 19 Mar 2026 11:20:03 +0800 Subject: [PATCH 0474/1330] FROMLIST: driver: bluetooth: hci_qca: disable power control for WCN7850 when bt_en is not defined For platforms where the bt_en GPIO is not defined, software-based power control should be disabled when power is managed by hardware. Add QCA_WCN7850 to the existing condition so that power_ctrl_enabled is cleared when bt_en is absent, aligning its behavior with WCN6750 and WCN6855. Links: https://lore.kernel.org/all/20260319031040.4096297-1-shuai.zhang@oss.qualcomm.com/ Signed-off-by: Shuai Zhang --- drivers/bluetooth/hci_qca.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c index e4c6b81c7c68b..121adf793369a 100644 --- a/drivers/bluetooth/hci_qca.c +++ b/drivers/bluetooth/hci_qca.c @@ -2470,7 +2470,8 @@ static int qca_serdev_probe(struct serdev_device *serdev) if (!qcadev->bt_en && (data->soc_type == QCA_WCN6750 || - data->soc_type == QCA_WCN6855)) + data->soc_type == QCA_WCN6855 || + data->soc_type == QCA_WCN7850)) power_ctrl_enabled = false; qcadev->sw_ctrl = devm_gpiod_get_optional(&serdev->dev, "swctrl", From 5f03c7f8924efe3a0d15d8ea9d32a7404994046c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 19:36:04 +0800 Subject: [PATCH 0475/1330] FROMLIST: drm/bridge: display-connector: don't autoenable HPD IRQ If HPD IRQ is enabled in the display_connector's probe, it can be triggered too early, before the DRM connector is completely setup. Use the enable_hpd / disable_hpd callbacks to control enablement of the HPD IRQ. Fixes: 0c275c30176b ("drm/bridge: Add bridge driver for display connectors") Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/all/20260314-dp-connector-hpd-v1-1-786044cedc17@oss.qualcomm.com/ --- drivers/gpu/drm/bridge/display-connector.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/bridge/display-connector.c b/drivers/gpu/drm/bridge/display-connector.c index 16c0631adeb18..6bb1134f75c3d 100644 --- a/drivers/gpu/drm/bridge/display-connector.c +++ b/drivers/gpu/drm/bridge/display-connector.c @@ -87,6 +87,20 @@ display_connector_bridge_detect(struct drm_bridge *bridge, struct drm_connector return display_connector_detect(bridge); } +static void display_connector_hpd_enable(struct drm_bridge *bridge) +{ + struct display_connector *conn = to_display_connector(bridge); + + enable_irq(conn->hpd_irq); +} + +static void display_connector_hpd_disable(struct drm_bridge *bridge) +{ + struct display_connector *conn = to_display_connector(bridge); + + disable_irq(conn->hpd_irq); +} + static const struct drm_edid *display_connector_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) { @@ -178,6 +192,8 @@ static u32 *display_connector_get_input_bus_fmts(struct drm_bridge *bridge, static const struct drm_bridge_funcs display_connector_bridge_funcs = { .attach = display_connector_attach, .detect = display_connector_bridge_detect, + .hpd_enable = display_connector_hpd_enable, + .hpd_disable = display_connector_hpd_disable, .edid_read = display_connector_edid_read, .atomic_get_output_bus_fmts = display_connector_get_output_bus_fmts, .atomic_get_input_bus_fmts = display_connector_get_input_bus_fmts, @@ -307,6 +323,7 @@ static int display_connector_probe(struct platform_device *pdev) NULL, display_connector_hpd_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_NO_AUTOEN | IRQF_ONESHOT, "HPD", conn); if (ret) { From 3a6466884d80d3d71157c94013f2c0effc0d38cf Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 19:37:45 +0800 Subject: [PATCH 0476/1330] FROMLIST: drm/bridge: display-connector: trigger initial HPD event for DP If the DisplayPort drivers use display-connector for the HPD detection, the internal HPD state machine might be not active and thus the hardware might be not able to handle cable detection correctly. Instead it will depend on the externall HPD notifications to set the cable state, bypassing the internal HPD state machine (for example this is the case for the msm DP driver). However if the cable has been plugged before the HPD IRQ has been enabled, there will be no HPD event coming. The drivers might fail detection in such a case. Trigger the HPD notification after enabling the HPD IRQ, propagating the cable insertion state. Fixes: 2e2bf3a5584d ("drm/bridge: display-connector: add DP support") Reported-by: Yongxing Mou Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/all/20260314-dp-connector-hpd-v1-2-786044cedc17@oss.qualcomm.com/ --- drivers/gpu/drm/bridge/display-connector.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/bridge/display-connector.c b/drivers/gpu/drm/bridge/display-connector.c index 6bb1134f75c3d..f7a5bfd9c0754 100644 --- a/drivers/gpu/drm/bridge/display-connector.c +++ b/drivers/gpu/drm/bridge/display-connector.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -25,6 +26,8 @@ struct display_connector { struct regulator *supply; struct gpio_desc *ddc_en; + + struct work_struct hpd_work; }; static inline struct display_connector * @@ -92,15 +95,29 @@ static void display_connector_hpd_enable(struct drm_bridge *bridge) struct display_connector *conn = to_display_connector(bridge); enable_irq(conn->hpd_irq); + + if (conn->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) + schedule_work(&conn->hpd_work); } static void display_connector_hpd_disable(struct drm_bridge *bridge) { struct display_connector *conn = to_display_connector(bridge); + if (conn->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) + cancel_work_sync(&conn->hpd_work); + disable_irq(conn->hpd_irq); } +static void display_connector_hpd_work(struct work_struct *work) +{ + struct display_connector *conn = container_of(work, struct display_connector, hpd_work); + struct drm_bridge *bridge = &conn->bridge; + + drm_bridge_hpd_notify(bridge, display_connector_detect(bridge)); +} + static const struct drm_edid *display_connector_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) { @@ -395,6 +412,8 @@ static int display_connector_probe(struct platform_device *pdev) conn->bridge.ops |= DRM_BRIDGE_OP_DETECT; if (conn->hpd_irq >= 0) conn->bridge.ops |= DRM_BRIDGE_OP_HPD; + if (conn->hpd_irq >= 0 && type == DRM_MODE_CONNECTOR_DisplayPort) + INIT_WORK(&conn->hpd_work, display_connector_hpd_work); dev_dbg(&pdev->dev, "Found %s display connector '%s' %s DDC bus and %s HPD GPIO (ops 0x%x)\n", From 336399a4778d0ffa96c70a0b9c9aded45225b945 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Sun, 22 Mar 2026 23:19:41 -0700 Subject: [PATCH 0477/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add PMIC devices Add a spmi-pmic-arb device for the SPMI PMIC arbiter found on Kaanapali. It has two subnodes corresponding to the SPMI0 bus controller and the SPMI1 bus controller. Also add dtsi files for PMH0104, PMH0110, PMD8028, PMIH0108, PMR735D and PM8010 along with temp-alarm and GPIO nodes under them, which are needed on Kaanapali. Signed-off-by: Jishnu Prakash Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260322-knp-pmic-dt-v1-1-70bc40ea4428@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 47 ++++ .../arm64/boot/dts/qcom/pm8010-kaanapali.dtsi | 93 ++++++++ .../boot/dts/qcom/pmd8028-kaanapali.dtsi | 62 +++++ .../boot/dts/qcom/pmh0104-kaanapali.dtsi | 63 ++++++ .../boot/dts/qcom/pmh0110-kaanapali.dtsi | 213 ++++++++++++++++++ .../boot/dts/qcom/pmih0108-kaanapali.dtsi | 68 ++++++ .../boot/dts/qcom/pmr735d-kaanapali.dtsi | 63 ++++++ 7 files changed, 609 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index c6786ab7afe15..454b3c29f5372 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3458,6 +3458,53 @@ #clock-cells = <0>; }; + arbiter@c400000 { + compatible = "qcom,kaanapali-spmi-pmic-arb", "qcom,glymur-spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c900000 0x0 0x400000>, + <0x0 0x0c4c0000 0x0 0x400000>, + <0x0 0x0c403000 0x0 0x8000>; + reg-names = "core", + "chnls", + "obsrvr", + "chnl_map"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + qcom,channel = <0>; + qcom,ee = <0>; + + spmi_bus0: spmi@c426000 { + reg = <0x0 0x0c426000 0x0 0x4000>, + <0x0 0x0c8c0000 0x0 0x10000>, + <0x0 0x0c42a000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c437000 { + reg = <0x0 0x0c437000 0x0 0x4000>, + <0x0 0x0c8d0000 0x0 0x10000>, + <0x0 0x0c43b000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,kaanapali-tlmm"; reg = <0x0 0x0f100000 0x0 0x300000>; diff --git a/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi new file mode 100644 index 0000000000000..bfc58a6589d3b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pm8010-m-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8010_m_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8010-n-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8010_n_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pm8010_m_e1: pmic@c { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_m_e1_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; + + pm8010_n_e1: pmic@d { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_n_e1_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi new file mode 100644 index 0000000000000..db4dc16a66e71 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmd8028-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmd8028_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmd8028_e1: pmic@4 { + compatible = "qcom,pmd8028", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmd8028_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmd8028_e1_gpios: gpio@8800 { + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmd8028_e1_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi new file mode 100644 index 0000000000000..d009c9a9f59e6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0104-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0104_j_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmh0104_j_e1: pmic@9 { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_j_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_j_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_j_e1_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi new file mode 100644 index 0000000000000..15d9cff246b37 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0110-d-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0110_d_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-f-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0110_f_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-g-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0110_g_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-i-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0110_i_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmh0110_d_e0: pmic@3 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_d_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_d_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_d_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_f_e0: pmic@5 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_f_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_g_e0: pmic@6 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_g_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_g_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_g_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_i_e0: pmic@8 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_i_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_i_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_i_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi new file mode 100644 index 0000000000000..b73b0e82c3d31 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmih0108-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmih0108_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmih0108_e1: pmic@7 { + compatible = "qcom,pmih0108", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmih0108_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmih0108_e1_gpios: gpio@8800 { + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmih0108_e1_gpios 0 0 18>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmih0108_e1_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi new file mode 100644 index 0000000000000..d0dd5e078cdc7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmr735d-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmr735d_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmr735d_e1: pmic@a { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_e1_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_e1_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From edd77222bed97aff8eb58da2e6488fab2829a19e Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Sun, 22 Mar 2026 23:19:42 -0700 Subject: [PATCH 0478/1330] FROMLIST: arm64: dts: qcom: kaanapali-mtp: Add PMIC support Include PMIC files used on Kaanapali MTP boards. Add configurations for keys (volume up and volume down), RGB LEDs and flash LEDs. Reviewed-by: Konrad Dybcio Reviewed-by: Shawn Guo Signed-off-by: Jishnu Prakash Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260322-knp-pmic-dt-v1-2-70bc40ea4428@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index bc57935c042c9..5054c59336878 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -5,9 +5,21 @@ /dts-v1/; +#include +#include +#include #include #include "kaanapali.dtsi" +#include "pm8010-kaanapali.dtsi" /* SPMI1: SID-12/13 */ +#include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0104-kaanapali.dtsi" /* SPMI1: SID-9 */ +#include "pmh0110-kaanapali.dtsi" /* SPMI0: SID-3/5/6/8 */ +#include "pmih0108-kaanapali.dtsi" /* SPMI1: SID-7 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "pmr735d-kaanapali.dtsi" /* SPMI1: SID-10 */ + / { model = "Qualcomm Technologies, Inc. Kaanapali MTP"; compatible = "qcom,kaanapali-mtp", "qcom,kaanapali"; @@ -53,6 +65,22 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + sound { compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard"; model = "Kaanapali-MTP"; @@ -801,6 +829,63 @@ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; }; +&pmh0101_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + function-enumerator = <0>; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + function-enumerator = <1>; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pmh0101_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/kaanapali/adsp.mbn", "qcom/kaanapali/adsp_dtb.mbn"; @@ -940,6 +1025,13 @@ bias-disable; }; + key_vol_up_default: key-vol-up-default-state { + pins = "gpio101"; + function = "gpio"; + output-disable; + bias-pull-up; + }; + pcie0_default_state: pcie0-default-state { perst-n-pins { pins = "gpio102"; From 4685cb789623690397f124c42fce60caceea52be Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Sun, 22 Mar 2026 23:19:43 -0700 Subject: [PATCH 0479/1330] FROMLIST: arm64: dts: qcom: kaanapali-qrd: Add PMIC support Include PMIC files used on Kaanapali QRD boards. Add configurations for keys (volume up and volume down), RGB LEDs and flash LEDs. Reviewed-by: Konrad Dybcio Reviewed-by: Shawn Guo Signed-off-by: Jishnu Prakash Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260322-knp-pmic-dt-v1-3-70bc40ea4428@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 32034eed03eb0..da0e8f9091c36 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -5,9 +5,21 @@ /dts-v1/; +#include +#include +#include #include #include "kaanapali.dtsi" +#include "pm8010-kaanapali.dtsi" /* SPMI1: SID-12/13 */ +#include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0104-kaanapali.dtsi" /* SPMI1: SID-9 */ +#include "pmh0110-kaanapali.dtsi" /* SPMI0: SID-3/5/6/8 */ +#include "pmih0108-kaanapali.dtsi" /* SPMI1: SID-7 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "pmr735d-kaanapali.dtsi" /* SPMI1: SID-10 */ + / { model = "Qualcomm Technologies, Inc. Kaanapali QRD"; compatible = "qcom,kaanapali-qrd", "qcom,kaanapali"; @@ -52,6 +64,22 @@ clock-div = <2>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; }; &apps_rsc { @@ -665,6 +693,63 @@ }; }; +&pmh0101_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + function-enumerator = <0>; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + function-enumerator = <1>; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pmh0101_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; @@ -701,6 +786,13 @@ <74 1>, /* eSE */ <119 2>, /* SoCCP */ <144 4>; /* CXM UART */ + + key_vol_up_default: key-vol-up-default-state { + pins = "gpio101"; + function = "gpio"; + output-disable; + bias-pull-up; + }; }; &uart7 { From 244dda4c14b430f2b0d13d005aa4d7a6f5f22c26 Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Sun, 22 Mar 2026 23:19:44 -0700 Subject: [PATCH 0480/1330] FROMLIST: arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi Enable bluetooth WCN785x and Wi-Fi on Kaanapali MTP board. Co-developed-by: Yijie Yang Signed-off-by: Zijun Hu Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260322-knp-pmic-dt-v1-4-70bc40ea4428@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 5054c59336878..d0f3909621c98 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -27,6 +27,7 @@ aliases { serial0 = &uart7; + serial1 = &uart18; }; chosen { @@ -189,6 +190,68 @@ #sound-dai-cells = <1>; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>; + pinctrl-names = "default"; + + bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_s2j_0p8>; + vddio-supply = <&vreg_l2g_1p8>; + vddio1p2-supply = <&vreg_l3g_1p2>; + vddaon-supply = <&vreg_s7g_0p9>; + vdddig-supply = <&vreg_s1j_0p8>; + vddrfa1p2-supply = <&vreg_s7f_1p2>; + vddrfa1p8-supply = <&vreg_s8f_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -827,6 +890,21 @@ &pcie_port0 { wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; }; &pmh0101_flash { @@ -880,6 +958,18 @@ }; }; +&pmh0104_j_e1_gpios { + bt_default: bt-default-state { + pins = "gpio5"; + function = "normal"; + input-disable; + output-enable; + output-low; + bias-disable; + power-source = <1>; + }; +}; + &pon_resin { linux,code = ; @@ -1011,6 +1101,19 @@ <119 2>, /* SoCCP */ <144 4>; /* CXM UART */ + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + spkr_0_sd_n_active: spkr-0-sd-n-active-state { pins = "gpio76"; function = "gpio"; @@ -1067,6 +1170,24 @@ status = "okay"; }; +&uart18 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + + max-speed = <3200000>; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>; From df00385a20a26670da8fab5927cffd6ee4a6eab7 Mon Sep 17 00:00:00 2001 From: Yuanjie Yang Date: Sun, 22 Mar 2026 23:19:45 -0700 Subject: [PATCH 0481/1330] FROMLIST: arm64: dts: qcom: kaanapali: add display hardware devices Add MDSS/MDP/DSI controllers and DSI PHYs for Kaanapali. DP controllers are not included. Signed-off-by: Yuanjie Yang Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260322-knp-pmic-dt-v1-5-70bc40ea4428@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 242 +++++++++++++++++++++++- 1 file changed, 240 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 454b3c29f5372..c129896f8daa7 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3,6 +3,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include #include #include #include @@ -3298,6 +3299,243 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@9800000 { + compatible = "qcom,kaanapali-mdss"; + reg = <0x0 0x09800000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_AHB_SWI_CLK>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@9801000 { + compatible = "qcom,kaanapali-dpu"; + reg = <0x0 0x09801000 0x0 0x1c8000>, + <0x0 0x09b16000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + }; + }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz = /bits/ 64 <207000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@9ac0000 { + compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x09ac0000 0x0 0x1000>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-312500000 { + opp-hz = /bits/ 64 <312500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@9ac1000 { + compatible = "qcom,kaanapali-dsi-phy-3nm"; + reg = <0x0 0x09ac1000 0x0 0x1cc>, + <0x0 0x09ac1200 0x0 0x280>, + <0x0 0x09ac1500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + dispcc: clock-controller@9ba2000 { compatible = "qcom,kaanapali-dispcc"; reg = <0x0 0x09ba2000 0x0 0x20000>; @@ -3313,8 +3551,8 @@ <0>, <0>, <0>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>; From daa6948c2d3323545e4b567e7e2f9697ac6d2a79 Mon Sep 17 00:00:00 2001 From: Yuanjie Yang Date: Sun, 22 Mar 2026 23:19:46 -0700 Subject: [PATCH 0482/1330] FROMLIST: arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices Enable MDSS/DPU/DSI0 and add Novatek NT37801 panel on Kaanapali MTP board. NT37801 Spec V1.0 chapter "5.7.1 Power On Sequence" states VDDI ranges 1.65V~1.95V, but ldo12 ranges 1.2V~1.8V, so change ldo12 range to 1.65V~1.8V. pmh0110_d_e0_gpios and pmh0110_f_e0_gpios are configured for level shifters. Kaanapali need configure these pinctrl for panel function. Signed-off-by: Yuanjie Yang Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260322-knp-pmic-dt-v1-6-70bc40ea4428@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 118 ++++++++++++++++++++- 1 file changed, 117 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index d0f3909621c98..07247dc98b701 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -375,7 +375,7 @@ vreg_l12b_1p8: ldo12 { regulator-name = "vreg_l12b_1p8"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; regulator-allow-set-load; @@ -873,6 +873,51 @@ qcom,dmic-sample-rate = <4800000>; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l1d_1p2>; + status = "okay"; + + panel@0 { + compatible = "novatek,nt37801"; + reg = <0>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend + &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active + &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend + &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active + &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>; + pinctrl-names = "default", "sleep"; + + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p0>; + vddio-supply = <&vreg_l12b_1p8>; + + reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l3d_0p8>; + + status = "okay"; +}; + &pcie0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -970,6 +1015,42 @@ }; }; +&pmh0110_d_e0_gpios { + sde_mdp_vsync_p_1p2_active: sde-mdp-vsync-p-1p2-active-state { + pins = "gpio9"; + function = "paired"; + input-disable; + output-enable; + power-source = <2>; /* 1.2v */ + }; + + sde_mdp_vsync_p_1p8_active: sde-mdp-vsync-p-1p8-active-state { + pins = "gpio10"; + function = "paired"; + input-enable; + output-disable; + power-source = <1>; /* 1.8v */ + }; +}; + +&pmh0110_f_e0_gpios { + sde_disp0_rst_1p2_active: sde-disp0-rst-1p2-active-state { + pins = "gpio9"; + function = "paired"; + input-enable; + output-disable; + power-source = <2>; /* 1.2v */ + }; + + sde_disp0_rst_1p8_active: sde-disp0-rst-1p8-active-state { + pins = "gpio10"; + function = "paired"; + input-disable; + output-enable; + power-source = <1>; /* 1.8v */ + }; +}; + &pon_resin { linux,code = ; @@ -1128,6 +1209,41 @@ bias-disable; }; + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_esync0_suspend: sde-esync0-suspend-state { + pins = "gpio88"; + function = "mdp_esync0_out"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + key_vol_up_default: key-vol-up-default-state { pins = "gpio101"; function = "gpio"; From 8421c8593ef28fca6bfb0cf8162ee1e8a147ebb0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 14 Feb 2026 01:02:59 +0200 Subject: [PATCH 0483/1330] BACKPORT: Revert "drm/msm/dpu: try reserving the DSPP-less LM first" This reverts commit 42f62cd79578 ("drm/msm/dpu: try reserving the DSPP-less LM first"). It seems on later DPUs using higher LMs require some additional setup or conflicts with the hardware defaults. Val (and other developers) reported blue screen on Hamoa (X1E80100) laptops. Revert the offending commit until we understand, what is the issue. Fixes: 42f62cd79578 ("drm/msm/dpu: try reserving the DSPP-less LM first") Reported-by: Val Packett Closes: https://lore.kernel.org/r/33424a9d-10a6-4479-bba6-12f8ce60da1a@packett.cool Signed-off-by: Dmitry Baryshkov Tested-by: Manivannan Sadhasivam # T14s Patchwork: https://patchwork.freedesktop.org/patch/704814/ Link: https://lore.kernel.org/r/20260214-revert-dspp-less-v1-1-be0d636a2a6e@oss.qualcomm.com From 8628ba8a7984086e9495841de8d147b4df4abfcc Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 27 Mar 2026 15:43:50 +0530 Subject: [PATCH 0484/1330] arm64: dts: qcom: Shikra: Add qfprom node Add qfprom node and its properties for Shikra SoC. Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a7bb3ef8f24d9..9e736ac101426 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -253,6 +253,18 @@ }; }; + qfprom: efuse@1b44000 { + compatible = "qcom,shikra-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b44000 0x0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@2006 { + reg = <0x2006 0x2>; + bits = <5 8>; + }; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x0 0x045f0000 0x0 0x7000>; From 603dd85972dc6735196126a2f3623b7e4e057020 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 27 Mar 2026 17:17:17 +0530 Subject: [PATCH 0485/1330] dt-bindings: nvmem: qfprom: Add Shikra compatible Document compatible string for the QFPROM on Shikra platform. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 839513d4b499d..74b369c796cf0 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -47,6 +47,7 @@ properties: - qcom,sdm630-qfprom - qcom,sdm670-qfprom - qcom,sdm845-qfprom + - qcom,shikra-qfprom - qcom,sm6115-qfprom - qcom,sm6350-qfprom - qcom,sm6375-qfprom From 8866f16daf13fcc46b5be9cbdff6ac7f8f7c2790 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 27 Mar 2026 18:01:13 +0530 Subject: [PATCH 0486/1330] dt-bindings: remoteproc: qcom: Add Shikra RPM processor compatible Add the qcom,shikra-rpm-proc compatible string to the Qualcomm RPM remote processor device tree binding. Signed-off-by: Sneh Mankad Signed-off-by: Komal Bajaj From 4d03d00c0a29225a174d310b0ada33f895c5b6de Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 27 Mar 2026 18:14:37 +0530 Subject: [PATCH 0487/1330] dt-bindings: mailbox: qcom: Add the Shikra APCS compatible Add compatible for the Qualcomm Shikra APCS block to the Qualcomm APCS binding. Signed-off-by: Sneh Mankad Signed-off-by: Komal Bajaj --- .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index bc1dc44fc2de8..a6d4fe840ea5d 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -64,6 +64,7 @@ properties: - qcom,ipq6018-apcs-apps-global - qcom,msm8996-apcs-hmss-global - qcom,qcm2290-apcs-hmss-global + - qcom,shikra-apcs-hmss-global - qcom,sdm845-apss-shared - qcom,shikra-apcs-hmss-global @@ -238,6 +239,7 @@ allOf: - qcom,msm8994-apcs-kpss-global - qcom,msm8996-apcs-hmss-global - qcom,qcm2290-apcs-hmss-global + - qcom,shikra-apcs-hmss-global - qcom,sdm845-apss-shared - qcom,shikra-apcs-hmss-global then: From fc14584d22e1a6c315630eed793a06fc99f6e2ab Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 27 Mar 2026 18:19:38 +0530 Subject: [PATCH 0488/1330] dt-bindings: soc: qcom: qcom,smd-rpm: Add compatible for Shikra Document the compatible for Shikra. Signed-off-by: Sneh Mankad Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 270bcd079f886..bd1d32898461c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -57,6 +57,7 @@ properties: - qcom,rpm-qcm2290 - qcom,rpm-qcs404 - qcom,rpm-sdm660 + - qcom,rpm-shikra - qcom,rpm-sm6115 - qcom,rpm-sm6125 - qcom,rpm-sm6375 From e69adab0e7b7fed955ec6e3705971800ebac9632 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 25 Mar 2026 12:07:43 +0530 Subject: [PATCH 0489/1330] arm64: dts: qcom: Add RPM SMD, LPM stats and MPM devices for shikra Add RPM SMD, subsystem LPM stats and MPM interrupt controller devices. Also add MPM as wakeup parent to TLMM device. Signed-off-by: Sneh Mankad Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 9e736ac101426..752258a512c6d 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -111,6 +111,30 @@ qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&apcs_glb 0>; }; + + mpm: interrupt-controller { + compatible = "qcom,mpm"; + qcom,rpm-msg-ram = <&apss_mpm>; + interrupts = ; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; + #power-domain-cells = <0>; + interrupt-parent = <&intc>; + qcom,mpm-pin-count = <95>; + qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ + <12 422>, /* DWC3 ss_phy_irq */ + <58 272>, /* QUSB2_PHY dmse_hv_vddmx */ + <59 273>, /* QUSB2_PHY dpse_hv_vddmx */ + <86 183>, /* MPM wake, SPMI */ + <90 157>, /* QUSB2_PHY DM */ + <91 158>; /* QUSB2_PHY DP */ + }; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm"; + qcom,glink-channels = "rpm_requests"; + }; }; reserved_memory: reserved-memory { @@ -244,6 +268,7 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 185>; + wakeup-parent = <&mpm>; qup_uart0_default: qup-uart0-default-state { pins = "gpio0", "gpio1"; @@ -278,6 +303,11 @@ }; }; + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0x0 0x04690000 0x0 0x14000>; + }; + adreno_smmu: iommu@59a0000 { compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x059a0000 0x0 0x10000>; From f0e5100d70b28eec303c08921bf134b889df1501 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 21 Jan 2026 12:15:45 +0200 Subject: [PATCH 0490/1330] dt-bindings: drm/bridge: anx7625: describe Type-C connector ANX7625 can be used to mux converted video stream with the USB signals on a Type-C connector. Describe the optional connector subnode, make it exclusive with the AUX bus and port@1 as it is impossible to have both eDP panel and USB-C connector. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260121-anx7625-typec-v2-1-d14f31256a17@oss.qualcomm.com --- .../display/bridge/analogix,anx7625.yaml | 98 ++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml index a1ed1004651b9..6ad466952c02d 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml @@ -85,6 +85,11 @@ properties: aux-bus: $ref: /schemas/display/dp-aux-bus.yaml# + connector: + type: object + $ref: /schemas/connector/usb-connector.yaml# + unevaluatedProperties: false + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -117,7 +122,6 @@ properties: required: - port@0 - - port@1 required: - compatible @@ -127,6 +131,28 @@ required: - vdd33-supply - ports +allOf: + - if: + required: + - aux-bus + - connector + then: + false + + - if: + required: + - connector + then: + properties: + ports: + properties: + port@1: false + else: + properties: + ports: + required: + - port@1 + additionalProperties: false examples: @@ -185,3 +211,73 @@ examples: }; }; }; + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + encoder@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1000_mipibrdg>; + vdd18-supply = <&pp1800_mipibrdg>; + vdd33-supply = <&pp3300_mipibrdg>; + analogix,audio-enable; + analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; + analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; + + connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + vbus-supply = <&vbus_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&usb_hs>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&usb_ss>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&usb_sbu>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&mipi_dsi>; + bus-type = <7>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; + }; From 06b27bdd1e0a5be1dac381ed9380083fb6a3da1b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 21 Jan 2026 12:15:46 +0200 Subject: [PATCH 0491/1330] drm: bridge: anx7625: implement minimal Type-C support ANX7625 can be used as a USB-C controller, handling USB and DP data streams. Provide minimal Type-C support necessary for ANX7625 to register the Type-C port device and properly respond to data / power role events from the Type-C partner. While ANX7625 provides TCPCI interface, using it would circumvent the on-chip running firmware. Analogix recommended using the higher-level interface instead of TCPCI. Reviewed-by: Xin Ji Reviewed-by: Heikki Krogerus Signed-off-by: Dmitry Baryshkov Link: https://patch.msgid.link/20260121-anx7625-typec-v2-2-d14f31256a17@oss.qualcomm.com --- drivers/gpu/drm/bridge/analogix/Kconfig | 1 + drivers/gpu/drm/bridge/analogix/anx7625.c | 155 ++++++++++++++++++++-- drivers/gpu/drm/bridge/analogix/anx7625.h | 22 ++- 3 files changed, 168 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig index 4846b2e9be7c2..f3448b0631fea 100644 --- a/drivers/gpu/drm/bridge/analogix/Kconfig +++ b/drivers/gpu/drm/bridge/analogix/Kconfig @@ -34,6 +34,7 @@ config DRM_ANALOGIX_ANX7625 tristate "Analogix Anx7625 MIPI to DP interface support" depends on DRM depends on OF + depends on TYPEC || !TYPEC select DRM_DISPLAY_DP_HELPER select DRM_DISPLAY_HDCP_HELPER select DRM_DISPLAY_HELPER diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 4e49e4f28d552..8dc6e3b169682 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -3,6 +3,7 @@ * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. * */ +#include #include #include #include @@ -15,6 +16,9 @@ #include #include #include +#include +#include +#include #include #include @@ -1325,7 +1329,7 @@ static int anx7625_read_hpd_gpio_config_status(struct anx7625_data *ctx) static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) { struct device *dev = ctx->dev; - int ret, val; + int ret; /* Reset main ocm */ ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); @@ -1339,6 +1343,11 @@ static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); else DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); +} + +static void anx7625_configure_hpd(struct anx7625_data *ctx) +{ + int val; /* * Make sure the HPD GPIO already be configured after OCM release before @@ -1369,7 +1378,9 @@ static int anx7625_ocm_loading_check(struct anx7625_data *ctx) if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) return -ENODEV; - anx7625_disable_pd_protocol(ctx); + if (!ctx->typec_port) + anx7625_disable_pd_protocol(ctx); + anx7625_configure_hpd(ctx); DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", anx7625_reg_read(ctx, @@ -1472,6 +1483,107 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx) DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); } +#if IS_REACHABLE(CONFIG_TYPEC) +static void anx7625_typec_set_orientation(struct anx7625_data *ctx) +{ + u32 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); + + if (val & (CC1_RP | CC1_RD)) + typec_set_orientation(ctx->typec_port, TYPEC_ORIENTATION_NORMAL); + else if (val & (CC2_RP | CC2_RD)) + typec_set_orientation(ctx->typec_port, TYPEC_ORIENTATION_REVERSE); + else + typec_set_orientation(ctx->typec_port, TYPEC_ORIENTATION_NONE); +} + +static void anx7625_typec_set_status(struct anx7625_data *ctx, + unsigned int intr_status, + unsigned int intr_vector) +{ + if (intr_vector & CC_STATUS) + anx7625_typec_set_orientation(ctx); + if (intr_vector & DATA_ROLE_STATUS) { + enum typec_data_role data_role = (intr_status & DATA_ROLE_STATUS) ? + TYPEC_HOST : TYPEC_DEVICE; + usb_role_switch_set_role(ctx->role_sw, + (intr_status & DATA_ROLE_STATUS) ? + USB_ROLE_HOST : USB_ROLE_DEVICE); + typec_set_data_role(ctx->typec_port, data_role); + ctx->typec_data_role = data_role; + } + if (intr_vector & VBUS_STATUS) + typec_set_pwr_role(ctx->typec_port, + (intr_status & VBUS_STATUS) ? + TYPEC_SOURCE : TYPEC_SINK); + if (intr_vector & VCONN_STATUS) + typec_set_vconn_role(ctx->typec_port, + (intr_status & VCONN_STATUS) ? + TYPEC_SOURCE : TYPEC_SINK); +} + +static int anx7625_typec_register(struct anx7625_data *ctx) +{ + struct typec_capability typec_cap = { }; + struct fwnode_handle *fwnode __free(fwnode_handle) = + device_get_named_child_node(ctx->dev, "connector"); + u32 val; + int ret; + + if (!fwnode) + return 0; + + ret = typec_get_fw_cap(&typec_cap, fwnode); + if (ret < 0) + return ret; + + typec_cap.revision = 0x0120; + typec_cap.pd_revision = 0x0300; + typec_cap.usb_capability = USB_CAPABILITY_USB2 | USB_CAPABILITY_USB3; + typec_cap.orientation_aware = true; + + typec_cap.driver_data = ctx; + + ctx->typec_port = typec_register_port(ctx->dev, &typec_cap); + if (IS_ERR(ctx->typec_port)) + return PTR_ERR(ctx->typec_port); + + ctx->role_sw = fwnode_usb_role_switch_get(fwnode); + if (IS_ERR(ctx->role_sw)) { + typec_unregister_port(ctx->typec_port); + return PTR_ERR(ctx->role_sw); + } + + val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); + + anx7625_typec_set_status(ctx, val, + CC_STATUS | DATA_ROLE_STATUS | + VBUS_STATUS | VCONN_STATUS); + + return 0; +} + +static void anx7625_typec_unregister(struct anx7625_data *ctx) +{ + usb_role_switch_put(ctx->role_sw); + typec_unregister_port(ctx->typec_port); +} +#else +static void anx7625_typec_set_status(struct anx7625_data *ctx, + unsigned int intr_status, + unsigned int intr_vector) +{ +} + +static int anx7625_typec_register(struct anx7625_data *ctx) +{ + return 0; +} + +static void anx7625_typec_unregister(struct anx7625_data *ctx) +{ +} +#endif + static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) { return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); @@ -1566,7 +1678,7 @@ static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) } } -static int anx7625_hpd_change_detect(struct anx7625_data *ctx) +static int anx7625_intr_status(struct anx7625_data *ctx) { int intr_vector, status; struct device *dev = ctx->dev; @@ -1593,9 +1705,6 @@ static int anx7625_hpd_change_detect(struct anx7625_data *ctx) return status; } - if (!(intr_vector & HPD_STATUS_CHANGE)) - return -ENOENT; - status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); if (status < 0) { @@ -1604,6 +1713,12 @@ static int anx7625_hpd_change_detect(struct anx7625_data *ctx) } DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); + + anx7625_typec_set_status(ctx, status, intr_vector); + + if (!(intr_vector & HPD_STATUS)) + return -ENOENT; + dp_hpd_change_handler(ctx, status & HPD_STATUS); return 0; @@ -1622,7 +1737,7 @@ static void anx7625_work_func(struct work_struct *work) return; } - event = anx7625_hpd_change_detect(ctx); + event = anx7625_intr_status(ctx); mutex_unlock(&ctx->lock); @@ -2741,11 +2856,29 @@ static int anx7625_i2c_probe(struct i2c_client *client) } if (!platform->pdata.low_power_mode) { - anx7625_disable_pd_protocol(platform); + struct fwnode_handle *fwnode; + + fwnode = device_get_named_child_node(dev, "connector"); + if (fwnode) + fwnode_handle_put(fwnode); + else + anx7625_disable_pd_protocol(platform); + + anx7625_configure_hpd(platform); + pm_runtime_get_sync(dev); _anx7625_hpd_polling(platform, 5000 * 100); } + if (platform->pdata.intp_irq) + anx7625_reg_write(platform, platform->i2c.rx_p0_client, + INTERFACE_CHANGE_INT_MASK, 0); + + /* After getting runtime handle */ + ret = anx7625_typec_register(platform); + if (ret) + goto pm_suspend; + /* Add work function */ if (platform->pdata.intp_irq) { enable_irq(platform->pdata.intp_irq); @@ -2759,6 +2892,10 @@ static int anx7625_i2c_probe(struct i2c_client *client) return 0; +pm_suspend: + if (!platform->pdata.low_power_mode) + pm_runtime_put_sync_suspend(&client->dev); + free_wq: if (platform->workqueue) destroy_workqueue(platform->workqueue); @@ -2774,6 +2911,8 @@ static void anx7625_i2c_remove(struct i2c_client *client) { struct anx7625_data *platform = i2c_get_clientdata(client); + anx7625_typec_unregister(platform); + drm_bridge_remove(&platform->bridge); if (platform->pdata.intp_irq) diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h index eb5580f1ab2f8..a18561c213af9 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.h +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h @@ -51,9 +51,21 @@ #define INTR_RECEIVED_MSG BIT(5) #define SYSTEM_STSTUS 0x45 +#define INTERFACE_CHANGE_INT_MASK 0x43 #define INTERFACE_CHANGE_INT 0x44 -#define HPD_STATUS_CHANGE 0x80 -#define HPD_STATUS 0x80 +#define VCONN_STATUS BIT(2) +#define VBUS_STATUS BIT(3) +#define CC_STATUS BIT(4) +#define DATA_ROLE_STATUS BIT(5) +#define HPD_STATUS BIT(7) + +#define NEW_CC_STATUS 0x46 +#define CC1_RD BIT(0) +#define CC1_RA BIT(1) +#define CC1_RP (BIT(2) | BIT(3)) +#define CC2_RD BIT(4) +#define CC2_RA BIT(5) +#define CC2_RP (BIT(6) | BIT(7)) /******** END of I2C Address 0x58 ********/ @@ -447,9 +459,15 @@ struct anx7625_i2c_client { struct i2c_client *tcpc_client; }; +struct typec_port; +struct usb_role_switch; + struct anx7625_data { struct anx7625_platform_data pdata; struct platform_device *audio_pdev; + struct typec_port *typec_port; + struct usb_role_switch *role_sw; + int typec_data_role; int hpd_status; int hpd_high_cnt; int dp_en; From 54836f02e4528901862801dd2abc365b7f4e6e7d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 21 Jan 2026 12:15:47 +0200 Subject: [PATCH 0492/1330] drm: bridge: anx7625: implement message sending Swapping the data role requires sending the message to the other USB-C side. Implement sending these messages through the OCM. The code is largely based on the anx7411.c USB-C driver. Signed-off-by: Dmitry Baryshkov Reviewed-by: Xin Ji Link: https://patch.msgid.link/20260121-anx7625-typec-v2-3-d14f31256a17@oss.qualcomm.com --- drivers/gpu/drm/bridge/analogix/anx7625.c | 68 +++++++++++++++++++++++ drivers/gpu/drm/bridge/analogix/anx7625.h | 12 ++++ 2 files changed, 80 insertions(+) diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 8dc6e3b169682..c43519097a457 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1484,6 +1484,73 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx) } #if IS_REACHABLE(CONFIG_TYPEC) +static u8 anx7625_checksum(u8 *buf, u8 len) +{ + u8 ret = 0; + u8 i; + + for (i = 0; i < len; i++) + ret += buf[i]; + + return ret; +} + +static int anx7625_read_msg_ctrl_status(struct anx7625_data *ctx) +{ + return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, CMD_SEND_BUF); +} + +static int anx7625_wait_msg_empty(struct anx7625_data *ctx) +{ + int val; + + return readx_poll_timeout(anx7625_read_msg_ctrl_status, ctx, + val, (val < 0) || (val == 0), + 2000, 2000 * 150); +} + +static int anx7625_send_msg(struct anx7625_data *ctx, u8 type, u8 *buf, u8 size) +{ + struct fw_msg *msg = &ctx->send_msg; + u8 crc; + int ret; + + size = min_t(u8, size, (u8)MAX_BUF_LEN); + memcpy(msg->buf, buf, size); + msg->msg_type = type; + + /* msg len equals buffer length + msg_type */ + msg->msg_len = size + 1; + + crc = anx7625_checksum((u8 *)msg, size + HEADER_LEN); + msg->buf[size] = 0 - crc; + + ret = anx7625_wait_msg_empty(ctx); + if (ret) + return ret; + + ret = anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, + CMD_SEND_BUF + 1, size + HEADER_LEN, + &msg->msg_type); + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, CMD_SEND_BUF, + msg->msg_len); + return ret; +} + +static int anx7625_typec_dr_set(struct typec_port *port, enum typec_data_role role) +{ + struct anx7625_data *ctx = typec_get_drvdata(port); + + if (role == ctx->typec_data_role) + return 0; + + return anx7625_send_msg(ctx, 0x11, NULL, 0); +} + +static const struct typec_operations anx7625_typec_ops = { + .dr_set = anx7625_typec_dr_set, +}; + static void anx7625_typec_set_orientation(struct anx7625_data *ctx) { u32 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); @@ -1542,6 +1609,7 @@ static int anx7625_typec_register(struct anx7625_data *ctx) typec_cap.orientation_aware = true; typec_cap.driver_data = ctx; + typec_cap.ops = &anx7625_typec_ops; ctx->typec_port = typec_register_port(ctx->dev, &typec_cap); if (IS_ERR(ctx->typec_port)) diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h index a18561c213af9..957d234ec07c8 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.h +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h @@ -67,6 +67,9 @@ #define CC2_RA BIT(5) #define CC2_RP (BIT(6) | BIT(7)) +#define CMD_SEND_BUF 0xC0 +#define CMD_RECV_BUF 0xE0 + /******** END of I2C Address 0x58 ********/ /***************************************************************/ @@ -462,6 +465,14 @@ struct anx7625_i2c_client { struct typec_port; struct usb_role_switch; +#define MAX_BUF_LEN 30 +struct fw_msg { + u8 msg_len; + u8 msg_type; + u8 buf[MAX_BUF_LEN]; +} __packed; +#define HEADER_LEN 2 + struct anx7625_data { struct anx7625_platform_data pdata; struct platform_device *audio_pdev; @@ -497,6 +508,7 @@ struct anx7625_data { struct drm_connector *connector; struct mipi_dsi_device *dsi; struct drm_dp_aux aux; + struct fw_msg send_msg; }; #endif /* __ANX7625_H__ */ From 282590690f9f25c8e9674a11c4aa1d602807a6b8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 11 Feb 2026 11:17:27 +0200 Subject: [PATCH 0493/1330] drm: bridge: anx7625: correctly detect if PD can be disabled During initial checks the ANX7625 bridge can be powered on before setting up the Type-C port. At this point, when anx7625_ocm_loading_check() checks if it can disable PD or not, it will notice that typec_port is not set and disable PD, breaking orientation and HPD handling. Unify the check between anx7625_ocm_loading_check() anx7625_i2c_probe() and anx7625_typec_register() and check for the presence of the "connector" node. Fixes: 8ad0f7d2e6fd ("drm: bridge: anx7625: implement message sending") Signed-off-by: Dmitry Baryshkov Reviewed-by: Xin Ji Tested-by: Loic Poulain Link: https://patch.msgid.link/20260211-anx7625-fix-pd-v1-1-1dd31451b06f@oss.qualcomm.com --- drivers/gpu/drm/bridge/analogix/anx7625.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index c43519097a457..1157a58cf1b19 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1363,6 +1363,18 @@ static void anx7625_configure_hpd(struct anx7625_data *ctx) anx7625_hpd_timer_config(ctx); } +static bool anx7625_need_pd(struct anx7625_data *ctx) +{ + struct fwnode_handle *fwnode; + + fwnode = device_get_named_child_node(ctx->dev, "connector"); + if (!fwnode) + return false; + + fwnode_handle_put(fwnode); + return true; +} + static int anx7625_ocm_loading_check(struct anx7625_data *ctx) { int ret; @@ -1378,7 +1390,7 @@ static int anx7625_ocm_loading_check(struct anx7625_data *ctx) if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) return -ENODEV; - if (!ctx->typec_port) + if (!anx7625_need_pd(ctx)) anx7625_disable_pd_protocol(ctx); anx7625_configure_hpd(ctx); @@ -2924,12 +2936,7 @@ static int anx7625_i2c_probe(struct i2c_client *client) } if (!platform->pdata.low_power_mode) { - struct fwnode_handle *fwnode; - - fwnode = device_get_named_child_node(dev, "connector"); - if (fwnode) - fwnode_handle_put(fwnode); - else + if (!anx7625_need_pd(platform)) anx7625_disable_pd_protocol(platform); anx7625_configure_hpd(platform); From c4493bf92d66936115018f5f5556f10459abad3a Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Thu, 22 Jan 2026 17:40:40 +0530 Subject: [PATCH 0494/1330] dt-bindings: display: msm: qcm2290-mdss: Fix iommus property Fix IOMMU DT propety for display via dropping SMMU stream IDs which relates to secure context bank. Assigning Linux kernel (HLOS) VMID to secure context bank stream IDs is incorrect. The maximum value for iommus property is updated accordingly. These DT bindings changes should be backwards compatible. Signed-off-by: Sumit Garg Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260122121042.579270-2-sumit.garg@kernel.org --- .../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml index bb09ecd1a5b4f..2772cdec7e42a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -108,7 +108,6 @@ examples: "cpu-cfg"; iommus = <&apps_smmu 0x420 0x2>; - ranges; display-controller@5e01000 { compatible = "qcom,qcm2290-dpu"; From b208a0c2023dac8aa96ba52ac92d9d07a33c7cf9 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Thu, 22 Jan 2026 17:40:41 +0530 Subject: [PATCH 0495/1330] dt-bindings: media: venus: Fix iommus property Fix IOMMU DT propety for venus via dropping SMMU stream IDs which relates to secure context bank. Assigning Linux kernel (HLOS) VMID to secure context bank stream IDs is incorrect. The maximum value for iommus property is updated accordingly. These DT bindings changes should be backwards compatible. Signed-off-by: Sumit Garg Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260122121042.579270-3-sumit.garg@kernel.org From 1c0d2b2d1499ada0e8eaac57d9489dcc39db054d Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Thu, 22 Jan 2026 17:40:42 +0530 Subject: [PATCH 0496/1330] arm64: dts: qcom: agatti: Fix IOMMU DT properties Fix IOMMU DT propeties for GPU, display and video peripherals via dropping SMMU stream IDs which relates to secure context bank. This problem only surfaced when the Gunyah based firmware stack is ported on Agatti replacing the legacy QHEE based firmware stack. Assigning Linux kernel (HLOS) VMID to secure context bank stream IDs is treated as a fault by Gunyah hypervisor which were previously ignored by QHEE hypervisor. The DT changes should be backwards compatible with legacy QHEE based firmware stack too. Suggested-by: Prakash Gupta Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov Signed-off-by: Sumit Garg Link: https://patch.msgid.link/20260122121042.579270-4-sumit.garg@kernel.org From d1ca4a4e86d08f35583f800fcbc0b0fa3a682870 Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Mon, 9 Feb 2026 14:24:25 +0000 Subject: [PATCH 0497/1330] dt-bindings: mfd: qcom,spmi-pmic: add compatibles for pm4124-codec Qualcomm Agatti SoC has PM4125 PMIC, which includes audio codec. Audio codec has TX and RX soundwire slave devices to connect to on-chip soundwire master. Add missing qcom,pm4125-codec compatible to pattern of audio-codec node properties in mfd qcom,spmi-pmic schema to complete the audio codec support. Signed-off-by: Alexey Klimov [Srini: reworked the patch] Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260209142428.214428-2-srinivas.kandagatla@oss.qualcomm.com --- Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 644c42b5e2e57..bdd304e9eac13 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -146,7 +146,11 @@ patternProperties: "^audio-codec@[0-9a-f]+$": type: object - $ref: /schemas/sound/qcom,pm8916-wcd-analog-codec.yaml# + oneOf: + - $ref: /schemas/sound/qcom,pm8916-wcd-analog-codec.yaml# + - properties: + compatible: + const: qcom,pm4125-codec "^battery@[0-9a-f]+$": type: object From 82f3941fe3ae86bfdc832bec04f1989d24c9f853 Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Mon, 9 Feb 2026 14:24:26 +0000 Subject: [PATCH 0498/1330] arm64: dts: qcom: agatti: add LPASS devices The rxmacro, txmacro, vamacro, soundwire nodes, lpass clock controllers are required to support audio playback and audio capture on sm6115 and its derivatives. Signed-off-by: Alexey Klimov Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260209142428.214428-3-srinivas.kandagatla@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/agatti.dtsi | 189 +++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 893cb06890130..00e961482a995 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -758,6 +758,42 @@ drive-strength = <8>; }; }; + + lpass_tx_swr_active: lpass-tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <10>; + slew-rate = <3>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; + + lpass_rx_swr_active: lpass-rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <10>; + slew-rate = <3>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <10>; + slew-rate = <3>; + bias-bus-hold; + }; + }; }; gcc: clock-controller@1400000 { @@ -2186,6 +2222,159 @@ }; }; + rxmacro: codec@a600000 { + compatible = "qcom,sm6115-lpass-rx-macro"; + reg = <0x0 0xa600000 0x0 0x1000>; + + clocks = <&q6afecc LPASS_CLK_ID_RX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_RX_CORE_NPL_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", + "npl", + "dcodec", + "fsgen"; + assigned-clocks = <&q6afecc LPASS_CLK_ID_RX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_RX_CORE_NPL_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <22579200>, + <22579200>; + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr1: soundwire@a610000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0x0 0x0a610000 0x0 0x2000>; + interrupts = ; + + clocks = <&rxmacro>; + clock-names = "iface"; + + resets = <&lpass_audiocc 0>; + reset-names = "swr_audio_cgcr"; + + label = "RX"; + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + + status = "disabled"; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + + txmacro: codec@a620000 { + compatible = "qcom,sm6115-lpass-tx-macro"; + reg = <0x0 0x0a620000 0x0 0x1000>; + + clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", + "npl", + "dcodec", + "fsgen"; + assigned-clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, + <19200000>; + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + lpass_audiocc: clock-controller@a6a9000 { + compatible = "qcom,sm6115-lpassaudiocc"; + reg = <0x0 0x0a6a9000 0x0 0x1000>; + #reset-cells = <1>; + }; + + vamacro: codec@a730000 { + compatible = "qcom,sm6115-lpass-va-macro"; + reg = <0x0 0x0a730000 0x0 0x1000>; + + clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "dcodec", + "npl"; + assigned-clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, + <19200000>; + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + swr0: soundwire@a740000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0x0 0x0a740000 0x0 0x2000>; + interrupts = , + ; + clocks = <&txmacro>; + clock-names = "iface"; + + resets = <&lpasscc 0>; + reset-names = "swr_audio_cgcr"; + + label = "VA_TX"; + qcom,din-ports = <3>; + qcom,dout-ports = <0>; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x00 0x00>; + + status = "disabled"; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + lpasscc: clock-controller@a7ec000 { + compatible = "qcom,sm6115-lpasscc"; + reg = <0x0 0x0a7ec000 0x0 0x1000>; + #reset-cells = <1>; + }; + remoteproc_adsp: remoteproc@ab00000 { compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; reg = <0x0 0x0ab00000 0x0 0x100>; From e5789359afbb3ced474961c5fac224406eb742b2 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 9 Feb 2026 14:24:27 +0000 Subject: [PATCH 0499/1330] arm64: dts: arduino-imola: add support for sound Add support for sound on Arduino UNO Q board, which includes - Headset playback and record. - Lineout Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260209142428.214428-4-srinivas.kandagatla@oss.qualcomm.com --- .../boot/dts/qcom/qrb2210-arduino-imola.dts | 137 ++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts index 5ab605cc56c80..d84e6c5625ea3 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts @@ -109,6 +109,98 @@ leds = <&ledr>, <&ledg>, <&ledb>; }; + sound { + compatible = "qcom,qrb2210-sndcard"; + model = "Arduino-Imola-HPH-LOUT"; + audio-routing = "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2"; + + mm1-dai-link { + link-name = "MultiMedia1"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + hph-playback-dai-link { + link-name = "HPH Playback"; + cpu { + sound-dai = <&q6afedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&pmic4125_codec 0>, <&swr1 0>, <&rxmacro 0>; + }; + }; + + lo-playback-dai-link { + link-name = "LO Playback"; + cpu { + sound-dai = <&q6afedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&pmic4125_codec 0>, <&swr1 0>, <&rxmacro 0>; + }; + }; + + ear-playback-dai-link { + link-name = "Ear Playback"; + cpu { + sound-dai = <&q6afedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&pmic4125_codec 0>, <&swr1 0>, <&rxmacro 0>; + }; + }; + + hph-capture-dai-link { + link-name = "HP Capture"; + cpu { + sound-dai = <&q6afedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&pmic4125_codec 1>, <&swr0 0>, <&txmacro 0>; + }; + }; + }; + /* PM4125 charger out, supplied by VBAT */ vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -331,6 +423,51 @@ }; }; +&spmi_bus { + pmic@0 { + pmic4125_codec: audio-codec@f000{ + compatible = "qcom,pm4125-codec"; + reg =<0xf000>; + vdd-io-supply = <&pm4125_l15>; + vdd-cp-supply = <&pm4125_s4>; + vdd-pa-vpos-supply = <&pm4125_s4>; + + vdd-mic-bias-supply = <&pm4125_l22>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + + qcom,rx-device = <&pm4125_rx>; + qcom,tx-device = <&pm4125_tx>; + #sound-dai-cells = <1>; + }; + }; +}; + +&swr0 { + pinctrl-0 = <&lpass_tx_swr_active>; + pinctrl-names = "default"; + status = "okay"; + + pm4125_tx: codec@0,3 { + compatible = "sdw20217010c00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + +&swr1 { + pinctrl-0 = <&lpass_rx_swr_active>; + pinctrl-names = "default"; + status = "okay"; + + pm4125_rx: codec@0,4 { + compatible = "sdw20217010c00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + &tlmm { jmisc_gpio18: jmisc-gpio18-state { pins = "gpio18"; From df3d08d2b09d41886b4fd01088f3ab4cff8f737a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 9 Feb 2026 14:24:28 +0000 Subject: [PATCH 0500/1330] arm64: defconfig: Enable Agatti audio drivers Enable reset controller and pm4125 audio codec driver that are required to enable audio support on Qualcomm Agatti SoC based platforms. Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260209142428.214428-5-srinivas.kandagatla@oss.qualcomm.com --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3537fd0e2eef6..0423ce79c2e25 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1150,6 +1150,7 @@ CONFIG_SND_SOC_ES8328_I2C=m CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_PM4125_SDW=m CONFIG_SND_SOC_PCM3168A_I2C=m CONFIG_SND_SOC_RK3308=m CONFIG_SND_SOC_RK817=m @@ -1568,6 +1569,7 @@ CONFIG_SM_GPUCC_8450=m CONFIG_SM_GPUCC_8550=m CONFIG_SM_GPUCC_8650=m CONFIG_SM_GPUCC_8750=m +CONFIG_SM_LPASSCC_6115=m CONFIG_SM_TCSRCC_8550=y CONFIG_SM_TCSRCC_8650=y CONFIG_SM_TCSRCC_8750=m From 0380f6c5c32c8e3aca92efaa9fa0ca4719355921 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 13 Feb 2026 19:25:25 +0200 Subject: [PATCH 0501/1330] arm64: dts: qcom: qrb2210-arduino-imola: describe DSI / DP bridge Aruino Uno-Q uses Analogix ANX7625 DSI-to-DP bridge to convert DSI signals to the connected USB-C DisplayPort dongles. Decribe the chip, USB-C connector and routing of USB and display signals. Co-developed-by: Martino Facchin Signed-off-by: Martino Facchin Tested-by: Loic Poulain Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260213-uno-q-anx7625-v2-1-c23359616528@oss.qualcomm.com --- .../boot/dts/qcom/qrb2210-arduino-imola.dts | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts index d84e6c5625ea3..5266f89feaaf2 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "agatti.dtsi" #include "pm4125.dtsi" @@ -201,6 +202,15 @@ }; }; + vreg_anx_30: regulator-anx-30 { + compatible = "regulator-fixed"; + regulator-name = "anx30"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + /* PM4125 charger out, supplied by VBAT */ vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -234,6 +244,86 @@ clock-frequency = <100000>; status = "okay"; + + anx7625: encoder@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupts-extended = <&tlmm 81 IRQ_TYPE_EDGE_FALLING>; + vdd10-supply = <&pm4125_l11>; + vdd18-supply = <&pm4125_l15>; + vdd33-supply = <&vreg_anx_30>; + analogix,audio-enable; + analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; + analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; + + pinctrl-0 = <&anx7625_int_pin>, <&anx7625_cable_det_pin>; + + connector { + compatible = "usb-c-connector"; + power-role = "sink"; + data-role = "dual"; + try-power-role = "sink"; + + pd-revision = /bits/ 8 <0x03 0x00 0x00 0x00>; + op-sink-microwatt = <15000000>; + sink-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + anx_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx_dsi0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm4125_l5>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&anx_dsi0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; }; &pm4125_vbus { @@ -490,6 +580,22 @@ output-disable; }; + anx7625_cable_det_pin: anx7625-cable-det-pins-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <16>; + output-disable; + bias-pull-up; + }; + + anx7625_int_pin: anx7625-int-pins-state { + pins = "gpio81"; + function = "gpio"; + drive-strength = <16>; + output-disable; + bias-pull-up; + }; + key_volp_n: key-volp-n-state { pins = "gpio96"; function = "gpio"; @@ -557,6 +663,10 @@ status = "okay"; }; +&usb_dwc3_hs { + remote-endpoint = <&anx_hs_in>; +}; + &usb_hsphy { vdd-supply = <&pm4125_l12>; vdda-pll-supply = <&pm4125_l13>; @@ -572,6 +682,10 @@ status = "okay"; }; +&usb_qmpphy_out { + remote-endpoint = <&anx_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; From b1e56e79b43e0f899483040c5bb79231c12f3a98 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Sun, 15 Feb 2026 03:30:02 +0200 Subject: [PATCH 0502/1330] drm: bridge: anx7625: don't crash if Type-C port is not used The typec_set_*() functions do not tolerate being passed the NULL typec_port instance. However, if CONFIG_TYPEC is enabled, but anx7625 DT node doesn't have the usb-c connector fwnode, then typec_port remains NULL, crashing the kernel. Prevent calling typec_set_foo() functions by checking that ctx->typec_port is not NULL in anx7625_typec_set_status(). Call trace: typec_set_orientation+0x18/0x68 (P) anx7625_typec_set_status+0x108/0x13c anx7625_work_func+0x124/0x438 process_one_work+0x214/0x648 worker_thread+0x1b4/0x358 kthread+0x14c/0x214 ret_from_fork+0x10/0x20 Code: 910003fd a90153f3 aa0003f3 2a0103f4 (f9431400) Fixes: f81455b2d332 ("drm: bridge: anx7625: implement minimal Type-C support") Reported-by: Salendarsingh Gaud Signed-off-by: Loic Poulain [db: dropped chunk anx7625_typec_unregister(), wrote commit message] Cc: Amit Kucheria Signed-off-by: Dmitry Baryshkov Link: https://patch.msgid.link/20260215-anx-fix-no-typec-v1-1-75172a5ca88b@oss.qualcomm.com --- drivers/gpu/drm/bridge/analogix/anx7625.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 1157a58cf1b19..763519ef0d38b 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1579,6 +1579,9 @@ static void anx7625_typec_set_status(struct anx7625_data *ctx, unsigned int intr_status, unsigned int intr_vector) { + if (!ctx->typec_port) + return; + if (intr_vector & CC_STATUS) anx7625_typec_set_orientation(ctx); if (intr_vector & DATA_ROLE_STATUS) { From ff9db608f388f61dd7b8f5c09fc7f8d65ac45a8e Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Mon, 30 Mar 2026 11:36:45 +0530 Subject: [PATCH 0503/1330] Revert "arm64: dts: qcom: agatti: enable FastRPC on the ADSP" This reverts commit 851d5ae6003b6517fb641675c33d4b529765fe14. RB1 board fails to boot with this change: [ 17.280102] qcom,fastrpc-cb ab00000.remoteproc:glink-edge:fastrpc:compute-cb@5: mem mmap error, fd 11, vaddr ffffb3670000, size 262144 Issue has been reported upstream here: https://lore.kernel.org/all/acoCFMdKRviiMZRp@sumit-xelite/ --- arch/arm64/boot/dts/qcom/agatti.dtsi | 41 ---------------------------- 1 file changed, 41 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 00e961482a995..298ef6388f04f 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -2478,47 +2478,6 @@ }; }; }; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - - qcom,non-secure-domain; - - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1c3 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1c4 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1c5 0x0>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x1c6 0x0>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x1c7 0x0>; - }; - }; }; }; From fdb388ec4e8b2c2146e053dfde00f50e672b89cb Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Sat, 28 Mar 2026 16:49:50 +0530 Subject: [PATCH 0504/1330] QCLINUX: qcom.config: Enable compressed firmware support Enable support for loading of compressed firmware. With compressed firmware binaries kernel is not able to load the firmware. Enable kernel configs to support compressed firmware. Signed-off-by: Salendarsingh Gaud --- arch/arm64/configs/qcom.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 5ab3c396bb670..344120e9c330f 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -27,6 +27,8 @@ CONFIG_DMABUF_HEAPS_CMA=y CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_EDAC_QCOM=m CONFIG_EXPERT=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y CONFIG_GUNYAH_WATCHDOG=y CONFIG_I2C_QCOM_GENI=y CONFIG_I6300ESB_WDT=y From 689d0f5755e5028477b9222628a34265af0db06c Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Wed, 25 Mar 2026 11:09:34 +0530 Subject: [PATCH 0505/1330] Revert "arm64: dts: qcom: qcs6490-rb3gen2: Adjust tsens thermal zone" This reverts commit 776fe08770380b70f8ec3d7a8878bf1846a106cb. Update trip threshold back to 95 degree as 105 is not applicable for all rb3gen2 boards. So reverting this change. Signed-off-by: Gaurav Kohli Signed-off-by: Dipa Ramesh Mantre --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 334 ------------------- 1 file changed, 334 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 85cc24079a24f..45526a5c8cbad 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1245,340 +1245,6 @@ }; }; -&thermal_zones { - cpu0-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu1-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu2-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu3-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu4-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu5-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu6-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu7-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu8-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu9-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu10-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - cpu11-thermal { - trips { - /delete-node/ trip-point0; - /delete-node/ trip-point1; - - cpu-crit { - temperature = <115000>; - }; - }; - - /delete-node/ cooling-maps; - }; - - aoss0-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - aoss0-crit { - temperature = <115000>; - }; - }; - }; - - aoss1-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - aoss1-crit { - temperature = <115000>; - }; - }; - }; - - cpuss0-thermal { - trips { - /delete-node/ trip-point0; - - cluster0-crit { - temperature = <115000>; - }; - }; - }; - - cpuss1-thermal { - trips { - /delete-node/ trip-point0; - - cluster0-crit { - temperature = <115000>; - }; - }; - }; - - gpuss0-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - gpuss0-crit { - temperature = <115000>; - }; - }; - }; - - gpuss1-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - gpuss1-crit { - temperature = <115000>; - }; - }; - }; - - nspss0-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - nspss0-crit { - temperature = <115000>; - }; - }; - }; - - nspss1-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - nspss1-crit { - temperature = <115000>; - }; - }; - }; - - video-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - video-crit { - temperature = <115000>; - }; - }; - }; - - ddr-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - ddr-crit { - temperature = <115000>; - }; - }; - }; - - mdmss0-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - mdmss0-crit { - temperature = <115000>; - }; - }; - }; - - mdmss1-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - mdmss1-crit { - temperature = <115000>; - }; - }; - }; - - mdmss2-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - mdmss2-crit { - temperature = <115000>; - }; - }; - }; - - mdmss3-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - mdmss3-crit { - temperature = <115000>; - }; - }; - }; - - camera0-thermal { - trips { - trip-point0 { - temperature = <105000>; - }; - - camera0-crit { - temperature = <115000>; - }; - }; - }; -}; - &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ From 709646c1e8d81174342df5eaf4d4b75e3b38c2e0 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 26 Mar 2026 00:42:59 +0530 Subject: [PATCH 0506/1330] FROMLIST: remoteproc: qcom: pas: Fix the dtb PAS context creation DTB PAS context creation should be done only for subsystems that support a DTB firmware binary; otherwise, memory is wasted. Move the context creation to the appropriate location and, while at it, fix the place where the DTB PAS context was being released unconditionally. Link: https://lore.kernel.org/lkml/20260325191301.164579-1-mukesh.ojha@oss.qualcomm.com/ Fixes: b13d8baf5601 ("remoteproc: pas: Replace metadata context with PAS context structure") Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 82d0fef763975..2ddd693a35c9e 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -262,7 +262,9 @@ static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw) return 0; release_dtb_metadata: - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + if (pas->dtb_pas_id) + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + release_firmware(pas->dtb_firmware); return ret; @@ -635,6 +637,7 @@ static void qcom_pas_pds_detach(struct qcom_pas *pas, struct device **pds, size_ static int qcom_pas_alloc_memory_region(struct qcom_pas *pas) { + struct rproc *rproc = pas->rproc; struct resource res; int ret; @@ -652,6 +655,12 @@ static int qcom_pas_alloc_memory_region(struct qcom_pas *pas) return PTR_ERR(pas->mem_region); } + pas->pas_ctx = devm_qcom_scm_pas_context_alloc(pas->dev, pas->pas_id, + pas->mem_phys, pas->mem_size); + if (IS_ERR(pas->pas_ctx)) + return PTR_ERR(pas->pas_ctx); + + pas->pas_ctx->use_tzmem = rproc->has_iommu; if (!pas->dtb_pas_id) return 0; @@ -669,6 +678,14 @@ static int qcom_pas_alloc_memory_region(struct qcom_pas *pas) return PTR_ERR(pas->dtb_mem_region); } + pas->dtb_pas_ctx = devm_qcom_scm_pas_context_alloc(pas->dev, pas->dtb_pas_id, + pas->dtb_mem_phys, + pas->dtb_mem_size); + if (IS_ERR(pas->dtb_pas_ctx)) + return PTR_ERR(pas->dtb_pas_ctx); + + pas->dtb_pas_ctx->use_tzmem = rproc->has_iommu; + return 0; } From 7d9eb80e0a2292cdb9bc85a26551d20476f465a9 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Tue, 10 Mar 2026 19:22:05 +0530 Subject: [PATCH 0507/1330] FROMLIST: remoteproc: qcom: pas: Map/unmap subsystem region before auth_and_reset Qualcomm remoteproc drivers such as qcom_q6v5_mss, which do not use the Peripheral Authentication Service (PAS), always map the MBA region before use and unmap it once the usage is complete. This behavior was introduced to avoid issues seen in the past where speculative accesses from the application processor to the MBA region after it was assigned to the remote Q6 led to an XPU violation. The issue was mitigated by unmapping the region before handing control to the remote Q6. Currently, most Qualcomm SoCs using the PAS driver run either with a standalone QHEE or the Gunyah hypervisor. In these environments, the hypervisor unmaps the Q6 memory from HLOS Stage-2 and remaps it into the Q6 Stage-2 page table. As a result, speculative accesses from HLOS cannot reach the region even if it remains mapped in HLOS Stage-1; therefore, XPU violations cannot occur. However, when the same SoC runs Linux at EL2, Linux itself must perform the unmapping to avoid such issues. It is still correct to apply this mapping/ unmapping sequence even for SoCs that run under Gunyah, so this behavior should not be conditional. Link: https://lore.kernel.org/lkml/20260325191301.164579-2-mukesh.ojha@oss.qualcomm.com/ Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 40 ++++++++++++++++++++--------- drivers/soc/qcom/mdt_loader.c | 18 ++++++++++--- include/linux/soc/qcom/mdt_loader.h | 4 +-- 3 files changed, 44 insertions(+), 18 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 2ddd693a35c9e..005a960bdeb1d 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -148,7 +148,16 @@ static void qcom_pas_minidump(struct rproc *rproc) if (rproc->dump_conf == RPROC_COREDUMP_DISABLED) return; + pas->mem_region = ioremap_wc(pas->mem_phys, pas->mem_size); + if (!pas->mem_region) { + dev_err(pas->dev, "unable to map memory region: %pa+%zx\n", + &pas->mem_phys, pas->mem_size); + return; + } + qcom_minidump(rproc, pas->minidump_id, qcom_pas_segment_dump); + iounmap(pas->mem_region); + pas->mem_region = NULL; } static int qcom_pas_pds_enable(struct qcom_pas *pas, struct device **pds, @@ -253,7 +262,7 @@ static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw) } ret = qcom_mdt_pas_load(pas->dtb_pas_ctx, pas->dtb_firmware, - pas->dtb_firmware_name, pas->dtb_mem_region, + pas->dtb_firmware_name, &pas->dtb_mem_reloc); if (ret) goto release_dtb_metadata; @@ -333,7 +342,7 @@ static int qcom_pas_start(struct rproc *rproc) } ret = qcom_mdt_pas_load(pas->pas_ctx, pas->firmware, rproc->firmware, - pas->mem_region, &pas->mem_reloc); + &pas->mem_reloc); if (ret) goto release_pas_metadata; @@ -524,6 +533,22 @@ static unsigned long qcom_pas_panic(struct rproc *rproc) return qcom_q6v5_panic(&pas->q6v5); } +static void qcom_pas_coredump(struct rproc *rproc) +{ + struct qcom_pas *pas = rproc->priv; + + pas->mem_region = ioremap_wc(pas->mem_phys, pas->mem_size); + if (!pas->mem_region) { + dev_err(pas->dev, "unable to map memory region: %pa+%zx\n", + &pas->mem_phys, pas->mem_size); + return; + } + + rproc_coredump(rproc); + iounmap(pas->mem_region); + pas->mem_region = NULL; +} + static const struct rproc_ops qcom_pas_ops = { .unprepare = qcom_pas_unprepare, .start = qcom_pas_start, @@ -532,6 +557,7 @@ static const struct rproc_ops qcom_pas_ops = { .parse_fw = qcom_pas_parse_firmware, .load = qcom_pas_load, .panic = qcom_pas_panic, + .coredump = qcom_pas_coredump, }; static const struct rproc_ops qcom_pas_minidump_ops = { @@ -649,11 +675,6 @@ static int qcom_pas_alloc_memory_region(struct qcom_pas *pas) pas->mem_phys = pas->mem_reloc = res.start; pas->mem_size = resource_size(&res); - pas->mem_region = devm_ioremap_resource_wc(pas->dev, &res); - if (IS_ERR(pas->mem_region)) { - dev_err(pas->dev, "unable to map memory region: %pR\n", &res); - return PTR_ERR(pas->mem_region); - } pas->pas_ctx = devm_qcom_scm_pas_context_alloc(pas->dev, pas->pas_id, pas->mem_phys, pas->mem_size); @@ -672,11 +693,6 @@ static int qcom_pas_alloc_memory_region(struct qcom_pas *pas) pas->dtb_mem_phys = pas->dtb_mem_reloc = res.start; pas->dtb_mem_size = resource_size(&res); - pas->dtb_mem_region = devm_ioremap_resource_wc(pas->dev, &res); - if (IS_ERR(pas->dtb_mem_region)) { - dev_err(pas->dev, "unable to map dtb memory region: %pR\n", &res); - return PTR_ERR(pas->dtb_mem_region); - } pas->dtb_pas_ctx = devm_qcom_scm_pas_context_alloc(pas->dev, pas->dtb_pas_id, pas->dtb_mem_phys, diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index c004d444d6985..33f3543f8e558 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -478,22 +479,31 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load); * @ctx: Pointer to the PAS (Peripheral Authentication Service) context * @fw: Firmware object representing the .mdt file * @firmware: Name of the firmware used to construct segment file names - * @mem_region: Memory region allocated for loading the firmware * @reloc_base: Physical address adjusted after relocation * * Return: 0 on success or a negative error code on failure. */ int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw, - const char *firmware, void *mem_region, phys_addr_t *reloc_base) + const char *firmware, phys_addr_t *reloc_base) { + void *mem_region; int ret; ret = __qcom_mdt_pas_init(ctx->dev, fw, firmware, ctx->pas_id, ctx->mem_phys, ctx); if (ret) return ret; - return qcom_mdt_load_no_init(ctx->dev, fw, firmware, mem_region, ctx->mem_phys, - ctx->mem_size, reloc_base); + mem_region = ioremap_wc(ctx->mem_phys, ctx->mem_size); + if (!mem_region) { + dev_err(ctx->dev, "unable to map memory region: %pa+%zx\n", &ctx->mem_phys, + ctx->mem_size); + return -EINVAL; + } + + ret = qcom_mdt_load_no_init(ctx->dev, fw, firmware, mem_region, ctx->mem_phys, + ctx->mem_size, reloc_base); + iounmap(mem_region); + return ret; } EXPORT_SYMBOL_GPL(qcom_mdt_pas_load); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/mdt_loader.h index 82372e0db0a18..7c551b98e1822 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -21,7 +21,7 @@ int qcom_mdt_load(struct device *dev, const struct firmware *fw, phys_addr_t *reloc_base); int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw, - const char *firmware, void *mem_region, phys_addr_t *reloc_base); + const char *firmware, phys_addr_t *reloc_base); int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, const char *fw_name, void *mem_region, @@ -47,7 +47,7 @@ static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw, static inline int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw, const char *firmware, - void *mem_region, phys_addr_t *reloc_base) + phys_addr_t *reloc_base) { return -ENODEV; } From e92ce45f52fc5eaa4f718ec1477a3ce160cfebe4 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 26 Mar 2026 00:43:01 +0530 Subject: [PATCH 0508/1330] FROMLIST: remoteproc: qcom: pas: Drop unused dtb_mem_region field dtb_mem_region is no longer referenced after the ioremap was moved to respective places where mapping is required. Remove it from struct qcom_pas. Link: https://lore.kernel.org/lkml/20260325191301.164579-3-mukesh.ojha@oss.qualcomm.com/ Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 005a960bdeb1d..40bc73f42b900 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -100,8 +100,9 @@ struct qcom_pas { phys_addr_t mem_reloc; phys_addr_t dtb_mem_reloc; phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT]; + void *mem_region; - void *dtb_mem_region; + size_t mem_size; size_t dtb_mem_size; size_t region_assign_size[MAX_ASSIGN_COUNT]; From 6aca716df93b5746181d190b46f61808eb44ce17 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Mon, 30 Mar 2026 15:48:02 +0530 Subject: [PATCH 0509/1330] arm64: dts: qcom: Move rpm_requests in glink-edge node Move rpm_requests node to under glink-edge node. Signed-off-by: Sneh Mankad --- arch/arm64/boot/dts/qcom/shikra.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 752258a512c6d..46534b9452adc 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -110,6 +110,11 @@ interrupts = ; qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm"; + qcom,glink-channels = "rpm_requests"; + }; }; mpm: interrupt-controller { @@ -130,11 +135,6 @@ <90 157>, /* QUSB2_PHY DM */ <91 158>; /* QUSB2_PHY DP */ }; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm"; - qcom,glink-channels = "rpm_requests"; - }; }; reserved_memory: reserved-memory { From 49bb0cc2a0597bfc6a008847411336b4f7b5f10d Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 13 Mar 2026 19:17:43 +0530 Subject: [PATCH 0510/1330] dt-bindings: clock: qcom,rpmcc: Add Shikra compatible Document the qcom,rpmcc-shikra compatible. Signed-off-by: Imran Shaik --- Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml index ab97d4b7dba8b..06f8439bb032a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -46,6 +46,7 @@ properties: - qcom,rpmcc-qcs404 - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 + - qcom,rpmcc-shikra - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 - qcom,rpmcc-sm6375 From 37e5bb407255afc13a2cba880b20590db0e6d36e Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 13 Mar 2026 18:38:09 +0530 Subject: [PATCH 0511/1330] dt-bindings: clock: qcom: Add GCC clocks for Shikra Add support for qcom global clock controller bindings for Shikra platform. Signed-off-by: Imran Shaik --- .../bindings/clock/qcom,shikra-gcc.yaml | 63 +++++ include/dt-bindings/clock/qcom,shikra-gcc.h | 258 ++++++++++++++++++ 2 files changed, 321 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,shikra-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml new file mode 100644 index 0000000000000..39cf7383df8bc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on Shikra + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on Shikra. + + See also: include/dt-bindings/clock/qcom,shikra-gcc.h + +properties: + compatible: + const: qcom,shikra-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: EMAC0 sgmiiphy mac rclk source + - description: EMAC0 sgmiiphy mac tclk source + - description: EMAC1 sgmiiphy mac rclk source + - description: EMAC1 sgmiiphy mac tclk source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@1400000 { + compatible = "qcom,shikra-gcc"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&emac0_sgmiiphy_rclk>, + <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, + <&pcie_pipe_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,shikra-gcc.h b/include/dt-bindings/clock/qcom,shikra-gcc.h new file mode 100644 index 0000000000000..77c6159755ce9 --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-gcc.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_AUX2 1 +#define GPLL1 2 +#define GPLL10 3 +#define GPLL11 4 +#define GPLL12 5 +#define GPLL12_OUT_AUX2 6 +#define GPLL3 7 +#define GPLL3_OUT_MAIN 8 +#define GPLL4 9 +#define GPLL5 10 +#define GPLL6 11 +#define GPLL6_OUT_MAIN 12 +#define GPLL7 13 +#define GPLL8 14 +#define GPLL8_OUT_MAIN 15 +#define GPLL9 16 +#define GPLL9_OUT_MAIN 17 +#define GCC_AHB2PHY_CSI_CLK 18 +#define GCC_AHB2PHY_USB_CLK 19 +#define GCC_BOOT_ROM_AHB_CLK 20 +#define GCC_CAM_THROTTLE_NRT_CLK 21 +#define GCC_CAM_THROTTLE_RT_CLK 22 +#define GCC_CAMERA_AHB_CLK 23 +#define GCC_CAMERA_XO_CLK 24 +#define GCC_CAMSS_AXI_CLK 25 +#define GCC_CAMSS_AXI_CLK_SRC 26 +#define GCC_CAMSS_CAMNOC_ATB_CLK 27 +#define GCC_CAMSS_CAMNOC_DRAGONLINK_ATB_CLK 28 +#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 29 +#define GCC_CAMSS_CCI_0_CLK 30 +#define GCC_CAMSS_CCI_CLK_SRC 31 +#define GCC_CAMSS_CPHY_0_CLK 32 +#define GCC_CAMSS_CPHY_1_CLK 33 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 34 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 35 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 36 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 37 +#define GCC_CAMSS_MCLK0_CLK 38 +#define GCC_CAMSS_MCLK0_CLK_SRC 39 +#define GCC_CAMSS_MCLK1_CLK 40 +#define GCC_CAMSS_MCLK1_CLK_SRC 41 +#define GCC_CAMSS_MCLK2_CLK 42 +#define GCC_CAMSS_MCLK2_CLK_SRC 43 +#define GCC_CAMSS_MCLK3_CLK 44 +#define GCC_CAMSS_MCLK3_CLK_SRC 45 +#define GCC_CAMSS_NRT_AXI_CLK 46 +#define GCC_CAMSS_OPE_AHB_CLK 47 +#define GCC_CAMSS_OPE_AHB_CLK_SRC 48 +#define GCC_CAMSS_OPE_CLK 49 +#define GCC_CAMSS_OPE_CLK_SRC 50 +#define GCC_CAMSS_RT_AXI_CLK 51 +#define GCC_CAMSS_TFE_0_CLK 52 +#define GCC_CAMSS_TFE_0_CLK_SRC 53 +#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 54 +#define GCC_CAMSS_TFE_0_CSID_CLK 55 +#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 56 +#define GCC_CAMSS_TFE_1_CLK 57 +#define GCC_CAMSS_TFE_1_CLK_SRC 58 +#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 59 +#define GCC_CAMSS_TFE_1_CSID_CLK 60 +#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 61 +#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 62 +#define GCC_CAMSS_TOP_AHB_CLK 63 +#define GCC_CAMSS_TOP_AHB_CLK_SRC 64 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 65 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 66 +#define GCC_DDRSS_GPU_AXI_CLK 67 +#define GCC_DDRSS_MEMNOC_PCIE_SF_CLK 68 +#define GCC_DISP_AHB_CLK 69 +#define GCC_DISP_GPLL0_CLK_SRC 70 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 71 +#define GCC_DISP_HF_AXI_CLK 72 +#define GCC_DISP_THROTTLE_CORE_CLK 73 +#define GCC_DISP_XO_CLK 74 +#define GCC_EMAC0_AHB_CLK 75 +#define GCC_EMAC0_AXI_CLK 76 +#define GCC_EMAC0_AXI_CLK_SRC 77 +#define GCC_EMAC0_AXI_SYS_NOC_CLK 78 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 79 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 80 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 81 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 82 +#define GCC_EMAC0_PHY_AUX_CLK 83 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 84 +#define GCC_EMAC0_PTP_CLK 85 +#define GCC_EMAC0_PTP_CLK_SRC 86 +#define GCC_EMAC0_RGMII_CLK 87 +#define GCC_EMAC0_RGMII_CLK_SRC 88 +#define GCC_EMAC1_AHB_CLK 89 +#define GCC_EMAC1_AXI_CLK 90 +#define GCC_EMAC1_AXI_CLK_SRC 91 +#define GCC_EMAC1_AXI_SYS_NOC_CLK 92 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 93 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 94 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 95 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 96 +#define GCC_EMAC1_PHY_AUX_CLK 97 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 98 +#define GCC_EMAC1_PTP_CLK 99 +#define GCC_EMAC1_PTP_CLK_SRC 100 +#define GCC_EMAC1_RGMII_CLK 101 +#define GCC_EMAC1_RGMII_CLK_SRC 102 +#define GCC_GP1_CLK 103 +#define GCC_GP1_CLK_SRC 104 +#define GCC_GP2_CLK 105 +#define GCC_GP2_CLK_SRC 106 +#define GCC_GP3_CLK 107 +#define GCC_GP3_CLK_SRC 108 +#define GCC_GPU_CFG_AHB_CLK 109 +#define GCC_GPU_GPLL0_CLK_SRC 110 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 111 +#define GCC_GPU_MEMNOC_GFX_CLK 112 +#define GCC_GPU_SMMU_VOTE_CLK 113 +#define GCC_GPU_SNOC_DVM_GFX_CLK 114 +#define GCC_GPU_THROTTLE_CORE_CLK 115 +#define GCC_MMU_TCU_VOTE_CLK 116 +#define GCC_PCIE_AUX_CLK 117 +#define GCC_PCIE_AUX_CLK_SRC 118 +#define GCC_PCIE_AUX_PHY_CLK_SRC 119 +#define GCC_PCIE_CFG_AHB_CLK 120 +#define GCC_PCIE_CLKREF_EN 121 +#define GCC_PCIE_MSTR_AXI_CLK 122 +#define GCC_PCIE_PIPE_CLK 123 +#define GCC_PCIE_PIPE_CLK_SRC 124 +#define GCC_PCIE_RCHNG_PHY_CLK 125 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 126 +#define GCC_PCIE_SLEEP_CLK 127 +#define GCC_PCIE_SLV_AXI_CLK 128 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 129 +#define GCC_PCIE_TBU_CLK 130 +#define GCC_PCIE_THROTTLE_CORE_CLK 131 +#define GCC_PCIE_THROTTLE_XO_CLK 132 +#define GCC_PCIE_TILE_AXI_SYS_NOC_CLK 133 +#define GCC_PDM2_CLK 134 +#define GCC_PDM2_CLK_SRC 135 +#define GCC_PDM_AHB_CLK 136 +#define GCC_PDM_XO4_CLK 137 +#define GCC_PWM0_XO512_CLK 138 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 139 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 140 +#define GCC_QMIP_DISP_AHB_CLK 141 +#define GCC_QMIP_GPU_CFG_AHB_CLK 142 +#define GCC_QMIP_PCIE_CFG_AHB_CLK 143 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 144 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 145 +#define GCC_QUPV3_WRAP0_CORE_CLK 146 +#define GCC_QUPV3_WRAP0_S0_CLK 147 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 148 +#define GCC_QUPV3_WRAP0_S1_CLK 149 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 150 +#define GCC_QUPV3_WRAP0_S2_CLK 151 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 152 +#define GCC_QUPV3_WRAP0_S3_CLK 153 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 154 +#define GCC_QUPV3_WRAP0_S4_CLK 155 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 156 +#define GCC_QUPV3_WRAP0_S5_CLK 157 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 158 +#define GCC_QUPV3_WRAP0_S6_CLK 159 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 160 +#define GCC_QUPV3_WRAP0_S7_CLK 161 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 162 +#define GCC_QUPV3_WRAP0_S8_CLK 163 +#define GCC_QUPV3_WRAP0_S8_CLK_SRC 164 +#define GCC_QUPV3_WRAP0_S9_CLK 165 +#define GCC_QUPV3_WRAP0_S9_CLK_SRC 166 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 167 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 168 +#define GCC_SDCC1_AHB_CLK 169 +#define GCC_SDCC1_APPS_CLK 170 +#define GCC_SDCC1_APPS_CLK_SRC 171 +#define GCC_SDCC1_ICE_CORE_CLK 172 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 +#define GCC_SDCC2_AHB_CLK 174 +#define GCC_SDCC2_APPS_CLK 175 +#define GCC_SDCC2_APPS_CLK_SRC 176 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 177 +#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 178 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 179 +#define GCC_TSCSS_AHB_CLK 180 +#define GCC_TSCSS_CLK_SRC 181 +#define GCC_TSCSS_CNTR_CLK 182 +#define GCC_TSCSS_ETU_CLK 183 +#define GCC_UFS_CLKREF_EN 184 +#define GCC_USB20_MASTER_CLK 185 +#define GCC_USB20_MASTER_CLK_SRC 186 +#define GCC_USB20_MOCK_UTMI_CLK 187 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 188 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 189 +#define GCC_USB20_SLEEP_CLK 190 +#define GCC_USB30_PRIM_MASTER_CLK 191 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 192 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 193 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 194 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 195 +#define GCC_USB30_PRIM_SLEEP_CLK 196 +#define GCC_USB3_PRIM_CLKREF_EN 197 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 198 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 199 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 200 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 201 +#define GCC_VCODEC0_AXI_CLK 202 +#define GCC_VENUS_AHB_CLK 203 +#define GCC_VENUS_CTL_AXI_CLK 204 +#define GCC_VIDEO_AHB_CLK 205 +#define GCC_VIDEO_AXI0_CLK 206 +#define GCC_VIDEO_THROTTLE_CORE_CLK 207 +#define GCC_VIDEO_VCODEC0_SYS_CLK 208 +#define GCC_VIDEO_VENUS_CLK_SRC 209 +#define GCC_VIDEO_VENUS_CTL_CLK 210 +#define GCC_VIDEO_XO_CLK 211 + +/* GCC power domains */ +#define GCC_CAMSS_TOP_GDSC 0 +#define GCC_EMAC0_GDSC 1 +#define GCC_EMAC1_GDSC 2 +#define GCC_PCIE_GDSC 3 +#define GCC_USB20_GDSC 4 +#define GCC_USB30_PRIM_GDSC 5 +#define GCC_VCODEC0_GDSC 6 +#define GCC_VENUS_GDSC 7 + +/* GCC resets */ +#define GCC_CAMSS_OPE_BCR 0 +#define GCC_CAMSS_TFE_BCR 1 +#define GCC_CAMSS_TOP_BCR 2 +#define GCC_EMAC0_BCR 3 +#define GCC_EMAC1_BCR 4 +#define GCC_GPU_BCR 5 +#define GCC_MMSS_BCR 6 +#define GCC_PCIE_BCR 7 +#define GCC_PCIE_PHY_BCR 8 +#define GCC_PDM_BCR 9 +#define GCC_QUPV3_WRAPPER_0_BCR 10 +#define GCC_QUSB2PHY_PRIM_BCR 11 +#define GCC_SDCC1_BCR 12 +#define GCC_SDCC2_BCR 13 +#define GCC_TSCSS_BCR 14 +#define GCC_USB20_BCR 15 +#define GCC_USB30_PRIM_BCR 16 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 17 +#define GCC_USB3_PHY_PRIM_SP0_BCR 18 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 19 +#define GCC_VCODEC0_BCR 20 +#define GCC_VENUS_BCR 21 +#define GCC_VIDEO_INTERFACE_BCR 22 + +#endif From 75616ec82da91244c58dcc480b262c3231a32f7e Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 13 Mar 2026 19:20:30 +0530 Subject: [PATCH 0512/1330] clk: qcom: smd-rpm: Add clocks for Shikra Add support for RPM-managed clocks on the Shikra platform. Signed-off-by: Imran Shaik --- drivers/clk/qcom/clk-smd-rpm.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 103db984a40b9..50daa2b0b8235 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1289,6 +1289,44 @@ static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { .num_icc_clks = ARRAY_SIZE(qcm2290_icc_clks) }; +static struct clk_smd_rpm *shikra_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, + [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A]= &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, + [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, + [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, + [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, + [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, + [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, +}; + +static const struct rpm_smd_clk_desc rpm_clk_shikra = { + .clks = shikra_clks, + .num_clks = ARRAY_SIZE(shikra_clks), + .icc_clks = qcm2290_icc_clks, + .num_icc_clks = ARRAY_SIZE(qcm2290_icc_clks) +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 }, { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, @@ -1309,6 +1347,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, { .compatible = "qcom,rpmcc-sdm429", .data = &rpm_clk_sdm429 }, { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, + { .compatible = "qcom,rpmcc-shikra", .data = &rpm_clk_shikra }, { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 }, { .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 }, From 1afff93422bf907d668f8a3f8e7344a791233f00 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 13 Mar 2026 17:37:50 +0530 Subject: [PATCH 0513/1330] clk: qcom: Add support for Global clock controller on Shikra Add support for Global clock controller for Shikra Qualcomm SoC. Signed-off-by: Imran Shaik --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-shikra.c | 4484 +++++++++++++++++++++++++++++++++ 3 files changed, 4494 insertions(+) create mode 100644 drivers/clk/qcom/gcc-shikra.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 99ef623a3c936..d45f0166ee04d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -119,6 +119,15 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. +config CLK_SHIKRA_GCC + tristate "Shikra Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on Shikra devices. + Say Y if you want to use multimedia devices or peripheral + devices such as Camera, Video, UART, SPI, I2C, USB, SD/eMMC etc. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4eb79dec0ddc8..9daa97f5ecf99 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o +obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o diff --git a/drivers/clk/qcom/gcc-shikra.c b/drivers/clk/qcom/gcc-shikra.c new file mode 100644 index 0000000000000..3ca5ed7cd48a1 --- /dev/null +++ b/drivers/clk/qcom/gcc-shikra.c @@ -0,0 +1,4484 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_EMAC0_SGMIIPHY_RCLK, + DT_EMAC0_SGMIIPHY_TCLK, + DT_EMAC1_SGMIIPHY_RCLK, + DT_EMAC1_SGMIIPHY_TCLK, + DT_PCIE_PIPE_CLK, + DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_EMAC0_SGMIIPHY_RCLK, + P_EMAC0_SGMIIPHY_TCLK, + P_EMAC1_SGMIIPHY_RCLK, + P_EMAC1_SGMIIPHY_TCLK, + P_GPLL0_OUT_AUX2, + P_GPLL0_OUT_EARLY, + P_GPLL10_OUT_MAIN, + P_GPLL11_OUT_AUX, + P_GPLL11_OUT_AUX2, + P_GPLL11_OUT_MAIN, + P_GPLL12_OUT_AUX2, + P_GPLL12_OUT_EARLY, + P_GPLL3_OUT_EARLY, + P_GPLL3_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_GPLL5_OUT_MAIN, + P_GPLL6_OUT_EARLY, + P_GPLL6_OUT_MAIN, + P_GPLL7_OUT_MAIN, + P_GPLL8_OUT_EARLY, + P_GPLL8_OUT_MAIN, + P_GPLL9_OUT_EARLY, + P_GPLL9_OUT_MAIN, + P_PCIE_PIPE_CLK, + P_SLEEP_CLK, + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +static const struct pll_vco brammo_vco[] = { + { 500000000, 1250000000, 0 }, +}; + +static const struct pll_vco spark_vco[] = { + { 750000000, 1500000000, 1 }, + { 500000000, 1000000000, 2 }, +}; + +static struct clk_alpha_pll gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll0_out_aux2, + .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll0_out_aux2", + .parent_hws = (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll1 = { + .offset = 0x1000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(1), + .hw.init = &(const struct clk_init_data) { + .name = "gpll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +/* 1152.0 MHz Configuration */ +static const struct alpha_pll_config gpll10_config = { + .l = 0x3c, + .alpha = 0x0, + .vco_val = BIT(20), + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +static struct clk_alpha_pll gpll10 = { + .offset = 0xa000, + .config = &gpll10_config, + .vco_table = spark_vco, + .num_vco = ARRAY_SIZE(spark_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(10), + .hw.init = &(const struct clk_init_data) { + .name = "gpll10", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +/* 600.0 MHz Configuration */ +static const struct alpha_pll_config gpll11_config = { + .l = 0x1f, + .alpha = 0x0, + .alpha_hi = 0x40, + .alpha_en_mask = BIT(24), + .vco_val = BIT(21), + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +static struct clk_alpha_pll gpll11 = { + .offset = 0xb000, + .config = &gpll11_config, + .vco_table = spark_vco, + .num_vco = ARRAY_SIZE(spark_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(11), + .hw.init = &(const struct clk_init_data) { + .name = "gpll11", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll12 = { + .offset = 0xc000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(12), + .hw.init = &(const struct clk_init_data) { + .name = "gpll12", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll12_out_aux2[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll12_out_aux2 = { + .offset = 0xc000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll12_out_aux2, + .num_post_div = ARRAY_SIZE(post_div_table_gpll12_out_aux2), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll12_out_aux2", + .parent_hws = (const struct clk_hw*[]) { + &gpll12.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll3 = { + .offset = 0x3000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(3), + .hw.init = &(const struct clk_init_data) { + .name = "gpll3", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll3_out_main[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll3_out_main = { + .offset = 0x3000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll3_out_main, + .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll3_out_main", + .parent_hws = (const struct clk_hw*[]) { + &gpll3.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll4 = { + .offset = 0x4000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(4), + .hw.init = &(const struct clk_init_data) { + .name = "gpll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll5 = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(5), + .hw.init = &(const struct clk_init_data) { + .name = "gpll5", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll6 = { + .offset = 0x6000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data) { + .name = "gpll6", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll6_out_main[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll6_out_main = { + .offset = 0x6000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll6_out_main, + .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll6_out_main", + .parent_hws = (const struct clk_hw*[]) { + &gpll6.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll7 = { + .offset = 0x7000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(7), + .hw.init = &(const struct clk_init_data) { + .name = "gpll7", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +/* 533.2 MHz Configuration */ +static const struct alpha_pll_config gpll8_config = { + .l = 0x1b, + .alpha = 0x55555555, + .alpha_hi = 0xc5, + .alpha_en_mask = BIT(24), + .vco_val = BIT(21), + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .early_output_mask = BIT(3), + .post_div_val = BIT(8), + .post_div_mask = GENMASK(11, 8), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +static struct clk_alpha_pll gpll8 = { + .offset = 0x8000, + .config = &gpll8_config, + .vco_table = spark_vco, + .num_vco = ARRAY_SIZE(spark_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data) { + .name = "gpll8", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll8_out_main[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll8_out_main = { + .offset = 0x8000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll8_out_main, + .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll8_out_main", + .parent_hws = (const struct clk_hw*[]) { + &gpll8.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +/* 1152.0 MHz Configuration */ +static const struct alpha_pll_config gpll9_config = { + .l = 0x3c, + .alpha = 0x0, + .post_div_val = BIT(8), + .post_div_mask = GENMASK(9, 8), + .main_output_mask = BIT(0), + .early_output_mask = BIT(3), + .config_ctl_val = 0x00004289, + .test_ctl_val = 0x08000000, +}; + +static struct clk_alpha_pll gpll9 = { + .offset = 0x9000, + .config = &gpll9_config, + .vco_table = brammo_vco, + .num_vco = ARRAY_SIZE(brammo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(9), + .hw.init = &(const struct clk_init_data) { + .name = "gpll9", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll9_out_main[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll9_out_main = { + .offset = 0x9000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll9_out_main, + .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), + .width = 2, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpll9_out_main", + .parent_hws = (const struct clk_hw*[]){ + &gpll9.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_aux2.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL6_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_aux2.clkr.hw }, + { .hw = &gpll6_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_aux2.clkr.hw }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL9_OUT_EARLY, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll9.clkr.hw }, + { .hw = &gpll10.clkr.hw }, + { .hw = &gpll9.clkr.hw }, + { .hw = &gpll3_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EARLY, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_aux2.clkr.hw }, + { .hw = &gpll10.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll3.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_GPLL3_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_aux2.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll3_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL8_OUT_EARLY, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL8_OUT_MAIN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EARLY, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll8.clkr.hw }, + { .hw = &gpll10.clkr.hw }, + { .hw = &gpll8_out_main.clkr.hw }, + { .hw = &gpll9.clkr.hw }, + { .hw = &gpll3.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_8[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL8_OUT_EARLY, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL8_OUT_MAIN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll8.clkr.hw }, + { .hw = &gpll10.clkr.hw }, + { .hw = &gpll8_out_main.clkr.hw }, + { .hw = &gpll9.clkr.hw }, + { .hw = &gpll3_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_9[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL8_OUT_EARLY, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL6_OUT_MAIN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EARLY, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll8.clkr.hw }, + { .hw = &gpll10.clkr.hw }, + { .hw = &gpll6_out_main.clkr.hw }, + { .hw = &gpll9.clkr.hw }, + { .hw = &gpll3.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_10[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_11[] = { + { P_BI_TCXO, 0 }, + { P_GPLL12_OUT_EARLY, 1 }, + { P_GPLL12_OUT_AUX2, 4 }, + { P_GPLL3_OUT_EARLY, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll12.clkr.hw }, + { .hw = &gpll12_out_aux2.clkr.hw }, + { .hw = &gpll3.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_12[] = { + { P_BI_TCXO, 0 }, + { P_GPLL12_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL12_OUT_AUX2, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll12.clkr.hw }, + { .hw = &gpll0_out_aux2.clkr.hw }, + { .hw = &gpll12_out_aux2.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_13[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_13[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_14[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL8_OUT_MAIN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EARLY, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_14[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_aux2.clkr.hw }, + { .hw = &gpll10.clkr.hw }, + { .hw = &gpll8_out_main.clkr.hw }, + { .hw = &gpll9.clkr.hw }, + { .hw = &gpll3.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_15[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL8_OUT_EARLY, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL6_OUT_EARLY, 5 }, + { P_GPLL3_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_15[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll8.clkr.hw }, + { .hw = &gpll10.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll3_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_21[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL7_OUT_MAIN, 3 }, + { P_GPLL4_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_21[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_aux2.clkr.hw }, + { .hw = &gpll7.clkr.hw }, + { .hw = &gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_22[] = { + { P_BI_TCXO, 0 }, + { P_GPLL12_OUT_EARLY, 1 }, + { P_GPLL5_OUT_MAIN, 3 }, + { P_GPLL12_OUT_AUX2, 4 }, + { P_GPLL3_OUT_EARLY, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_22[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll12.clkr.hw }, + { .hw = &gpll5.clkr.hw }, + { .hw = &gpll12_out_aux2.clkr.hw }, + { .hw = &gpll3.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_24[] = { + { P_BI_TCXO, 0 }, + { P_GPLL11_OUT_MAIN, 1 }, + { P_GPLL11_OUT_AUX, 2 }, + { P_GPLL11_OUT_AUX2, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_24[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll11.clkr.hw }, + { .hw = &gpll11.clkr.hw }, + { .hw = &gpll11.clkr.hw }, +}; + +static struct clk_regmap_phy_mux gcc_emac0_cc_sgmiiphy_rx_clk_src = { + .reg = 0xad048, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_cc_sgmiiphy_rx_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_EMAC0_SGMIIPHY_RCLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_emac0_cc_sgmiiphy_tx_clk_src = { + .reg = 0xad040, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_cc_sgmiiphy_tx_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_EMAC0_SGMIIPHY_TCLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_emac1_cc_sgmiiphy_rx_clk_src = { + .reg = 0xae048, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_cc_sgmiiphy_rx_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_EMAC1_SGMIIPHY_RCLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_emac1_cc_sgmiiphy_tx_clk_src = { + .reg = 0xae040, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_cc_sgmiiphy_tx_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_EMAC1_SGMIIPHY_TCLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src = { + .reg = 0xaf058, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_pipe_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_PCIE_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb3_prim_phy_pipe_clk_src = { + .reg = 0x1a05c, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_prim_phy_pipe_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), + F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), + F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_axi_clk_src = { + .cmd_rcgr = 0x5802c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_camss_axi_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_axi_clk_src", + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_cci_clk_src = { + .cmd_rcgr = 0x56000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_14, + .freq_tbl = ftbl_gcc_camss_cci_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_cci_clk_src", + .parent_data = gcc_parent_data_14, + .num_parents = ARRAY_SIZE(gcc_parent_data_14), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), + F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { + .cmd_rcgr = 0x45000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_csi0phytimer_clk_src", + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { + .cmd_rcgr = 0x4501c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_csi1phytimer_clk_src", + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { + F(19200000, P_GPLL9_OUT_EARLY, 1, 1, 60), + F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), + F(64000000, P_GPLL9_OUT_EARLY, 9, 1, 2), + { } +}; + +static struct clk_rcg2 gcc_camss_mclk0_clk_src = { + .cmd_rcgr = 0x51000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_mclk0_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk1_clk_src = { + .cmd_rcgr = 0x5101c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_mclk1_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk2_clk_src = { + .cmd_rcgr = 0x51038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_mclk2_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk3_clk_src = { + .cmd_rcgr = 0x51054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_mclk3_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { + .cmd_rcgr = 0x55024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_ope_ahb_clk_src", + .parent_data = gcc_parent_data_7, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), + F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), + F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), + F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_ope_clk_src = { + .cmd_rcgr = 0x55004, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_gcc_camss_ope_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_ope_clk_src", + .parent_data = gcc_parent_data_7, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), + F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), + F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), + F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), + F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), + F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), + F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), + F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), + F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), + F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), + F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), + F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), + F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), + F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), + F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { + .cmd_rcgr = 0x52004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_0_clk_src", + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { + .cmd_rcgr = 0x52094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_9, + .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_0_csid_clk_src", + .parent_data = gcc_parent_data_9, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { + .cmd_rcgr = 0x52024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_1_clk_src", + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { + .cmd_rcgr = 0x520b4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_9, + .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_1_csid_clk_src", + .parent_data = gcc_parent_data_9, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), + F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { + .cmd_rcgr = 0x52064, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_15, + .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_cphy_rx_clk_src", + .parent_data = gcc_parent_data_15, + .num_parents = ARRAY_SIZE(gcc_parent_data_15), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), + F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { + .cmd_rcgr = 0x58010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_top_ahb_clk_src", + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_axi_clk_src[] = { + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), + F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), + F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_axi_clk_src = { + .cmd_rcgr = 0x109dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_emac0_axi_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_axi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = { + .cmd_rcgr = 0xad01c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_10, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_phy_aux_clk_src", + .parent_data = gcc_parent_data_10, + .num_parents = ARRAY_SIZE(gcc_parent_data_10), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = { + F(250000000, P_GPLL12_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_ptp_clk_src = { + .cmd_rcgr = 0xad064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_11, + .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_ptp_clk_src", + .parent_data = gcc_parent_data_11, + .num_parents = ARRAY_SIZE(gcc_parent_data_11), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = { + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(125000000, P_GPLL12_OUT_AUX2, 4, 0, 0), + F(250000000, P_GPLL12_OUT_EARLY, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_rgmii_clk_src = { + .cmd_rcgr = 0xad04c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_12, + .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_rgmii_clk_src", + .parent_data = gcc_parent_data_12, + .num_parents = ARRAY_SIZE(gcc_parent_data_12), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_axi_clk_src = { + .cmd_rcgr = 0x109fc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_emac0_axi_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_axi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = { + .cmd_rcgr = 0xae01c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_10, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_phy_aux_clk_src", + .parent_data = gcc_parent_data_10, + .num_parents = ARRAY_SIZE(gcc_parent_data_10), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_ptp_clk_src = { + .cmd_rcgr = 0xae064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_11, + .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_ptp_clk_src", + .parent_data = gcc_parent_data_11, + .num_parents = ARRAY_SIZE(gcc_parent_data_11), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_rgmii_clk_src = { + .cmd_rcgr = 0xae04c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_12, + .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_rgmii_clk_src", + .parent_data = gcc_parent_data_12, + .num_parents = ARRAY_SIZE(gcc_parent_data_12), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x4d004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gp1_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x4e004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gp2_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src = { + .cmd_rcgr = 0x4f004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gp3_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_aux_clk_src = { + .cmd_rcgr = 0xaf074, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_aux_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { + .cmd_rcgr = 0xaf05c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_aux_phy_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = { + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = { + .cmd_rcgr = 0xaf028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_rchng_phy_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x20010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), + F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), + F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), + F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), + F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), + F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), + F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), + F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { + .name = "gcc_qupv3_wrap0_s0_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { + .cmd_rcgr = 0x1f148, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { + .name = "gcc_qupv3_wrap0_s1_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { + .cmd_rcgr = 0x1f278, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { + .name = "gcc_qupv3_wrap0_s2_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { + .cmd_rcgr = 0x1f3a8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { + .name = "gcc_qupv3_wrap0_s3_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { + .cmd_rcgr = 0x1f4d8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { + .name = "gcc_qupv3_wrap0_s4_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { + .cmd_rcgr = 0x1f608, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { + .name = "gcc_qupv3_wrap0_s5_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { + .cmd_rcgr = 0x1f738, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { + .name = "gcc_qupv3_wrap0_s6_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { + .cmd_rcgr = 0x1f868, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { + .name = "gcc_qupv3_wrap0_s7_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { + .cmd_rcgr = 0x1f998, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s8_clk_src_init = { + .name = "gcc_qupv3_wrap0_s8_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s8_clk_src = { + .cmd_rcgr = 0x1fac8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s8_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s9_clk_src_init = { + .name = "gcc_qupv3_wrap0_s9_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s9_clk_src = { + .cmd_rcgr = 0x1fbf8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap0_s9_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), + F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { + .cmd_rcgr = 0x38028, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc1_apps_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x38010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc1_ice_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .cmd_rcgr = 0x1e00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_21, + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc2_apps_clk_src", + .parent_data = gcc_parent_data_21, + .num_parents = ARRAY_SIZE(gcc_parent_data_21), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_floor_ops, + }, +}; + +static struct clk_rcg2 gcc_tscss_clk_src = { + .cmd_rcgr = 0xac004, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_22, + .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_tscss_clk_src", + .parent_data = gcc_parent_data_22, + .num_parents = ARRAY_SIZE(gcc_parent_data_22), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { + F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), + F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb20_master_clk_src = { + .cmd_rcgr = 0xb003c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb20_master_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb20_master_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { + .cmd_rcgr = 0xb0020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_13, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb20_mock_utmi_clk_src", + .parent_data = gcc_parent_data_13, + .num_parents = ARRAY_SIZE(gcc_parent_data_13), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { + .cmd_rcgr = 0x1a01c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_prim_master_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { + .cmd_rcgr = 0x1a034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { + .cmd_rcgr = 0x1a060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_prim_phy_aux_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { + F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), + F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_video_venus_clk_src = { + .cmd_rcgr = 0x6d000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_24, + .freq_tbl = ftbl_gcc_video_venus_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_video_venus_clk_src", + .parent_data = gcc_parent_data_24, + .num_parents = ARRAY_SIZE(gcc_parent_data_24), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { + .reg = 0xb0038, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb20_mock_utmi_postdiv_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb20_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { + .reg = 0x1a04c, + .shift = 0, + .width = 2, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_ahb2phy_csi_clk = { + .halt_reg = 0x1d004, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x1d004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1d004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ahb2phy_csi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ahb2phy_usb_clk = { + .halt_reg = 0x1d008, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1d008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1d008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ahb2phy_usb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x23004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x23004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(1), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cam_throttle_nrt_clk = { + .halt_reg = 0x17070, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17070, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(16), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_cam_throttle_nrt_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cam_throttle_rt_clk = { + .halt_reg = 0x1706c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1706c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(15), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_cam_throttle_rt_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_axi_clk = { + .halt_reg = 0x58044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x58044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_camnoc_atb_clk = { + .halt_reg = 0x5804c, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x5804c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x5804c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_camnoc_atb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_camnoc_dragonlink_atb_clk = { + .halt_reg = 0x58060, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x58060, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x58060, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_camnoc_dragonlink_atb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { + .halt_reg = 0x58050, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x58050, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x58050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_camnoc_nts_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_0_clk = { + .halt_reg = 0x56018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x56018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_cci_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_cci_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_0_clk = { + .halt_reg = 0x52088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_cphy_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_1_clk = { + .halt_reg = 0x5208c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5208c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_cphy_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0phytimer_clk = { + .halt_reg = 0x45018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x45018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1phytimer_clk = { + .halt_reg = 0x45034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x45034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk0_clk = { + .halt_reg = 0x51018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_mclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk1_clk = { + .halt_reg = 0x51034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_mclk1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk2_clk = { + .halt_reg = 0x51050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_mclk2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk3_clk = { + .halt_reg = 0x5106c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5106c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_mclk3_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_nrt_axi_clk = { + .halt_reg = 0x58054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x58054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_nrt_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ope_ahb_clk = { + .halt_reg = 0x5503c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5503c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_ope_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_ope_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ope_clk = { + .halt_reg = 0x5501c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5501c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_ope_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_ope_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_rt_axi_clk = { + .halt_reg = 0x5805c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5805c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_rt_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_0_clk = { + .halt_reg = 0x5201c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5201c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { + .halt_reg = 0x5207c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5207c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_0_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_0_csid_clk = { + .halt_reg = 0x520ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x520ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_0_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_0_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_1_clk = { + .halt_reg = 0x5203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5203c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { + .halt_reg = 0x52080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_1_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_1_csid_clk = { + .halt_reg = 0x520cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x520cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_tfe_1_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_1_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_top_ahb_clk = { + .halt_reg = 0x58028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x58028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_camss_top_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { + .halt_reg = 0x111c4, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x111c4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x111c4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_cfg_noc_usb2_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { + .halt_reg = 0x1a07c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1a07c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a07c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk = { + .halt_reg = 0x71000, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x71000, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x71000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ddrss_gpu_axi_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_memnoc_pcie_sf_clk = { + .halt_reg = 0x29044, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x29044, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x29044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ddrss_memnoc_pcie_sf_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_div gcc_disp_gpll0_clk_src = { + .reg = 0x17058, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gcc_disp_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_branch gcc_disp_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(11), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_disp_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gcc_disp_gpll0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk = { + .halt_reg = 0x17020, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17020, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_disp_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_throttle_core_clk = { + .halt_reg = 0x17064, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17064, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(13), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_disp_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_ahb_clk = { + .halt_reg = 0xad010, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xad010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xad010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_axi_clk = { + .halt_reg = 0xad014, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xad014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xad014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_axi_sys_noc_clk = { + .halt_reg = 0x109d4, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x109d4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x109d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_axi_sys_noc_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_cc_sgmiiphy_rx_clk = { + .halt_reg = 0xad044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xad044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_cc_sgmiiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_cc_sgmiiphy_tx_clk = { + .halt_reg = 0xad03c, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0xad03c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xad03c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_cc_sgmiiphy_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_phy_aux_clk = { + .halt_reg = 0xad018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xad018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_ptp_clk = { + .halt_reg = 0xad034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xad034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_ptp_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_ptp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rgmii_clk = { + .halt_reg = 0xad038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xad038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_rgmii_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_rgmii_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_ahb_clk = { + .halt_reg = 0xae010, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xae010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xae010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_axi_clk = { + .halt_reg = 0xae014, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xae014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xae014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_axi_sys_noc_clk = { + .halt_reg = 0x109f4, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x109f4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x109f4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_axi_sys_noc_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_cc_sgmiiphy_rx_clk = { + .halt_reg = 0xae044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xae044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_cc_sgmiiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_cc_sgmiiphy_tx_clk = { + .halt_reg = 0xae03c, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0xae03c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xae03c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_cc_sgmiiphy_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_phy_aux_clk = { + .halt_reg = 0xae018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xae018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_ptp_clk = { + .halt_reg = 0xae034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xae034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_ptp_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_ptp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_rgmii_clk = { + .halt_reg = 0xae038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xae038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_rgmii_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_rgmii_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x4d000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x4e000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4e000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x4f000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4f000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gp3_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gpu_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gpll0_out_aux2.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk = { + .halt_reg = 0x3600c, + .halt_check = BRANCH_VOTED, + .hwcg_reg = 0x3600c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x3600c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gpu_memnoc_gfx_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_smmu_vote_clk = { + .halt_reg = 0x7d000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gpu_smmu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x36018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_throttle_core_clk = { + .halt_reg = 0x36048, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x36048, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(21), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gpu_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmu_tcu_vote_clk = { + .halt_reg = 0x7d06c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d06c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_mmu_tcu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_aux_clk = { + .halt_reg = 0xaf044, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf044, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_cfg_ahb_clk = { + .halt_reg = 0xaf010, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(27), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_clkref_en = { + .halt_reg = 0xb8000, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xb8000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_mstr_axi_clk = { + .halt_reg = 0xaf020, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf020, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(30), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_pipe_clk = { + .halt_reg = 0xaf050, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0xaf050, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79018, + .enable_mask = BIT(2), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_rchng_phy_clk = { + .halt_reg = 0xaf040, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(31), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_rchng_phy_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_rchng_phy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_sleep_clk = { + .halt_reg = 0xaf04c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf04c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79018, + .enable_mask = BIT(1), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_sleep_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_aux_phy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_axi_clk = { + .halt_reg = 0xaf018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(29), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_q2a_axi_clk = { + .halt_reg = 0xaf014, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(28), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_tbu_clk = { + .halt_reg = 0xaf098, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf098, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79018, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_tbu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_throttle_core_clk = { + .halt_reg = 0xaf094, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf094, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79018, + .enable_mask = BIT(5), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_throttle_xo_clk = { + .halt_reg = 0xaf090, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79018, + .enable_mask = BIT(4), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_throttle_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_tile_axi_sys_noc_clk = { + .halt_reg = 0x10f2c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x10f2c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x10f2c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_tile_axi_sys_noc_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x2000c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2000c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x20004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x20004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x20004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x20008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x20008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pwm0_xo512_clk = { + .halt_reg = 0x2002c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2002c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pwm0_xo512_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { + .halt_reg = 0x17014, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(9), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qmip_camera_nrt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { + .halt_reg = 0x17060, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17060, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(12), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qmip_camera_rt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk = { + .halt_reg = 0x17018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(10), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qmip_disp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { + .halt_reg = 0x36040, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x36040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qmip_gpu_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_pcie_cfg_ahb_clk = { + .halt_reg = 0xaf08c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xaf08c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79018, + .enable_mask = BIT(3), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qmip_pcie_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { + .halt_reg = 0x17010, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qmip_video_vcodec_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { + .halt_reg = 0x1f014, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(21), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk = { + .halt_reg = 0x1f00c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk = { + .halt_reg = 0x1f144, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(22), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s0_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk = { + .halt_reg = 0x1f274, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(23), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk = { + .halt_reg = 0x1f3a4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(24), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk = { + .halt_reg = 0x1f4d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(25), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s3_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk = { + .halt_reg = 0x1f604, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(26), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s4_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk = { + .halt_reg = 0x1f734, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(27), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s5_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s6_clk = { + .halt_reg = 0x1f864, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(28), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s6_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s7_clk = { + .halt_reg = 0x1f994, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(29), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s7_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s8_clk = { + .halt_reg = 0x1fac4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(30), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s8_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s8_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s9_clk = { + .halt_reg = 0x1fbf4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(31), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s9_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s9_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { + .halt_reg = 0x1f004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1f004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap_0_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { + .halt_reg = 0x1f008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1f008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap_0_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x38008, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x38008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x38008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x38004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc1_apps_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x3800c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x3800c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x3800c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc1_ice_core_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x1e008, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1e008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1e008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x1e004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc2_apps_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb2_prim_axi_clk = { + .halt_reg = 0x10a14, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x10a14, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x10a14, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sys_noc_usb2_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { + .halt_reg = 0x1a078, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1a078, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a078, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sys_noc_usb3_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tscss_ahb_clk = { + .halt_reg = 0xac024, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xac024, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xac024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_tscss_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tscss_cntr_clk = { + .halt_reg = 0xac020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xac020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_tscss_cntr_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_tscss_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tscss_etu_clk = { + .halt_reg = 0xac01c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xac01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_tscss_etu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_tscss_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_clkref_en = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ufs_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_master_clk = { + .halt_reg = 0xb0010, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xb0010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb0010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb20_master_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_mock_utmi_clk = { + .halt_reg = 0xb001c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xb001c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb20_mock_utmi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_sleep_clk = { + .halt_reg = 0xb0018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xb0018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb20_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk = { + .halt_reg = 0x1a010, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1a010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_prim_master_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { + .halt_reg = 0x1a018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_prim_mock_utmi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk = { + .halt_reg = 0x1a014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_prim_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_en = { + .halt_reg = 0x9f000, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x9f000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_prim_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { + .halt_reg = 0x1a054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { + .halt_reg = 0x1a058, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x1a058, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_prim_phy_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vcodec0_axi_clk = { + .halt_reg = 0x6e008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6e008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_vcodec0_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus_ahb_clk = { + .halt_reg = 0x6e010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6e010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_venus_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus_ctl_axi_clk = { + .halt_reg = 0x6e004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6e004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_venus_ctl_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi0_clk = { + .halt_reg = 0x1701c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1701c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1701c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_video_axi0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_throttle_core_clk = { + .halt_reg = 0x17068, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17068, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_video_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_vcodec0_sys_clk = { + .halt_reg = 0x6d044, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x6d044, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x6d044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_video_vcodec0_sys_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_video_venus_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_venus_ctl_clk = { + .halt_reg = 0x6d02c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6d02c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_video_venus_ctl_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_video_venus_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gcc_camss_top_gdsc = { + .gdscr = 0x58004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_camss_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_emac0_gdsc = { + .gdscr = 0xad004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_emac0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_emac1_gdsc = { + .gdscr = 0xae004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_emac1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_gdsc = { + .gdscr = 0xaf004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_pcie_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb20_gdsc = { + .gdscr = 0xb0004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_usb20_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb30_prim_gdsc = { + .gdscr = 0x1a004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_venus_gdsc = { + .gdscr = 0x6d01c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_venus_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_vcodec0_gdsc = { + .gdscr = 0x6d038, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_vcodec0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &gcc_venus_gdsc.pd, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gcc_shikra_clocks[] = { + [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, + [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, + [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, + [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, + [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, + [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, + [GCC_CAMSS_CAMNOC_DRAGONLINK_ATB_CLK] = &gcc_camss_camnoc_dragonlink_atb_clk.clkr, + [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, + [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, + [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, + [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, + [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, + [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, + [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, + [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, + [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, + [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, + [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, + [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, + [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, + [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, + [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, + [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, + [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, + [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, + [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, + [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, + [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, + [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, + [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, + [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, + [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, + [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, + [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, + [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, + [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, + [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, + [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, + [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, + [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, + [GCC_DDRSS_MEMNOC_PCIE_SF_CLK] = &gcc_ddrss_memnoc_pcie_sf_clk.clkr, + [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, + [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, + [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, + [GCC_EMAC0_AHB_CLK] = &gcc_emac0_ahb_clk.clkr, + [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr, + [GCC_EMAC0_AXI_CLK_SRC] = &gcc_emac0_axi_clk_src.clkr, + [GCC_EMAC0_AXI_SYS_NOC_CLK] = &gcc_emac0_axi_sys_noc_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &gcc_emac0_cc_sgmiiphy_rx_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr, + [GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &gcc_emac0_cc_sgmiiphy_tx_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr, + [GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr, + [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr, + [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr, + [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr, + [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr, + [GCC_EMAC1_AHB_CLK] = &gcc_emac1_ahb_clk.clkr, + [GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr, + [GCC_EMAC1_AXI_CLK_SRC] = &gcc_emac1_axi_clk_src.clkr, + [GCC_EMAC1_AXI_SYS_NOC_CLK] = &gcc_emac1_axi_sys_noc_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &gcc_emac1_cc_sgmiiphy_rx_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr, + [GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &gcc_emac1_cc_sgmiiphy_tx_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr, + [GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr, + [GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr, + [GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr, + [GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr, + [GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr, + [GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SMMU_VOTE_CLK] = &gcc_gpu_smmu_vote_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, + [GCC_MMU_TCU_VOTE_CLK] = &gcc_mmu_tcu_vote_clk.clkr, + [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr, + [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr, + [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr, + [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr, + [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr, + [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr, + [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr, + [GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr, + [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr, + [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr, + [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr, + [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr, + [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr, + [GCC_PCIE_TBU_CLK] = &gcc_pcie_tbu_clk.clkr, + [GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr, + [GCC_PCIE_THROTTLE_XO_CLK] = &gcc_pcie_throttle_xo_clk.clkr, + [GCC_PCIE_TILE_AXI_SYS_NOC_CLK] = &gcc_pcie_tile_axi_sys_noc_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, + [GCC_QMIP_PCIE_CFG_AHB_CLK] = &gcc_qmip_pcie_cfg_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, + [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, + [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, + [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, + [GCC_QUPV3_WRAP0_S8_CLK] = &gcc_qupv3_wrap0_s8_clk.clkr, + [GCC_QUPV3_WRAP0_S8_CLK_SRC] = &gcc_qupv3_wrap0_s8_clk_src.clkr, + [GCC_QUPV3_WRAP0_S9_CLK] = &gcc_qupv3_wrap0_s9_clk.clkr, + [GCC_QUPV3_WRAP0_S9_CLK_SRC] = &gcc_qupv3_wrap0_s9_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SYS_NOC_USB2_PRIM_AXI_CLK] = &gcc_sys_noc_usb2_prim_axi_clk.clkr, + [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, + [GCC_TSCSS_AHB_CLK] = &gcc_tscss_ahb_clk.clkr, + [GCC_TSCSS_CLK_SRC] = &gcc_tscss_clk_src.clkr, + [GCC_TSCSS_CNTR_CLK] = &gcc_tscss_cntr_clk.clkr, + [GCC_TSCSS_ETU_CLK] = &gcc_tscss_etu_clk.clkr, + [GCC_UFS_CLKREF_EN] = &gcc_ufs_clkref_en.clkr, + [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, + [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, + [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, + [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, + [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, + [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, + [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, + [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, + [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, + [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, + [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, + [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, + [GPLL0] = &gpll0.clkr, + [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, + [GPLL1] = &gpll1.clkr, + [GPLL10] = &gpll10.clkr, + [GPLL11] = &gpll11.clkr, + [GPLL12] = &gpll12.clkr, + [GPLL12_OUT_AUX2] = &gpll12_out_aux2.clkr, + [GPLL3] = &gpll3.clkr, + [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, + [GPLL4] = &gpll4.clkr, + [GPLL5] = &gpll5.clkr, + [GPLL6] = &gpll6.clkr, + [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, + [GPLL7] = &gpll7.clkr, + [GPLL8] = &gpll8.clkr, + [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, + [GPLL9] = &gpll9.clkr, + [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, +}; + +static struct gdsc *gcc_shikra_gdscs[] = { + [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, + [GCC_EMAC0_GDSC] = &gcc_emac0_gdsc, + [GCC_EMAC1_GDSC] = &gcc_emac1_gdsc, + [GCC_PCIE_GDSC] = &gcc_pcie_gdsc, + [GCC_USB20_GDSC] = &gcc_usb20_gdsc, + [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, + [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, + [GCC_VENUS_GDSC] = &gcc_venus_gdsc, +}; + +static const struct qcom_reset_map gcc_shikra_resets[] = { + [GCC_CAMSS_OPE_BCR] = { 0x55000 }, + [GCC_CAMSS_TFE_BCR] = { 0x52000 }, + [GCC_CAMSS_TOP_BCR] = { 0x58000 }, + [GCC_EMAC0_BCR] = { 0xad000 }, + [GCC_EMAC1_BCR] = { 0xae000 }, + [GCC_GPU_BCR] = { 0x36000 }, + [GCC_MMSS_BCR] = { 0x17000 }, + [GCC_PCIE_BCR] = { 0xaf000 }, + [GCC_PCIE_PHY_BCR] = { 0xb1000 }, + [GCC_PDM_BCR] = { 0x20000 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_SDCC1_BCR] = { 0x38000 }, + [GCC_SDCC2_BCR] = { 0x1e000 }, + [GCC_TSCSS_BCR] = { 0xac000 }, + [GCC_USB20_BCR] = { 0xb0000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_VCODEC0_BCR] = { 0x6d034 }, + [GCC_VENUS_BCR] = { 0x6d018 }, + [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, +}; + +static struct clk_alpha_pll *gcc_shikra_plls[] = { + &gpll10, + &gpll11, + &gpll8, + &gpll9, +}; + +static u32 gcc_shikra_critical_cbcrs[] = { + 0x17008, /* GCC_CAMERA_AHB_CLK */ + 0x17028, /* GCC_CAMERA_XO_CLK */ + 0x1700c, /* GCC_DISP_AHB_CLK */ + 0x1702c, /* GCC_DISP_XO_CLK */ + 0x36004, /* GCC_GPU_CFG_AHB_CLK */ + 0x36100, /* GCC_GPU_IREF_CLK */ + 0x79004, /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + 0x17004, /* GCC_VIDEO_AHB_CLK */ + 0x17024, /* GCC_VIDEO_XO_CLK */ +}; + +static const struct clk_rcg_dfs_data gcc_shikra_dfs_clocks[] = { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s8_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s9_clk_src), +}; + +static const struct regmap_config gcc_shikra_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xc7000, + .fast_io = true, +}; + +static struct qcom_cc_driver_data gcc_shikra_driver_data = { + .alpha_plls = gcc_shikra_plls, + .num_alpha_plls = ARRAY_SIZE(gcc_shikra_plls), + .clk_cbcrs = gcc_shikra_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(gcc_shikra_critical_cbcrs), + .dfs_rcgs = gcc_shikra_dfs_clocks, + .num_dfs_rcgs = ARRAY_SIZE(gcc_shikra_dfs_clocks), +}; + +static const struct qcom_cc_desc gcc_shikra_desc = { + .config = &gcc_shikra_regmap_config, + .clks = gcc_shikra_clocks, + .num_clks = ARRAY_SIZE(gcc_shikra_clocks), + .resets = gcc_shikra_resets, + .num_resets = ARRAY_SIZE(gcc_shikra_resets), + .gdscs = gcc_shikra_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_shikra_gdscs), + .driver_data = &gcc_shikra_driver_data, +}; + +static const struct of_device_id gcc_shikra_match_table[] = { + { .compatible = "qcom,shikra-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_shikra_match_table); + +static int gcc_shikra_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_shikra_desc); +} + +static struct platform_driver gcc_shikra_driver = { + .probe = gcc_shikra_probe, + .driver = { + .name = "gcc-shikra", + .of_match_table = gcc_shikra_match_table, + }, +}; + +static int __init gcc_shikra_init(void) +{ + return platform_driver_register(&gcc_shikra_driver); +} +subsys_initcall(gcc_shikra_init); + +static void __exit gcc_shikra_exit(void) +{ + platform_driver_unregister(&gcc_shikra_driver); +} +module_exit(gcc_shikra_exit); + +MODULE_DESCRIPTION("QTI GCC SHIKRA Driver"); +MODULE_LICENSE("GPL"); From 462428e0df297b36122d827eff1c115432a1ee72 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 13 Mar 2026 18:16:03 +0530 Subject: [PATCH 0514/1330] arm64: defconfig: Enable GCC on Shikra EVK boards Enable the GCC driver on the Qualcomm Shikra EVK boards. Signed-off-by: Imran Shaik --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0423ce79c2e25..7134d0f8e8540 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1446,6 +1446,7 @@ CONFIG_CLK_IMX8QXP=y CONFIG_CLK_IMX8ULP=y CONFIG_CLK_IMX93=y CONFIG_CLK_IMX95_BLK_CTL=y +CONFIG_CLK_SHIKRA_GCC=y CONFIG_TI_SCI_CLK=y CONFIG_COMMON_CLK_MT8192_AUDSYS=y CONFIG_COMMON_CLK_MT8192_CAMSYS=y From aed7c0a65d085d3d1552da4f25216a5dd118c140 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 13 Mar 2026 18:02:14 +0530 Subject: [PATCH 0515/1330] arm64: dts: qcom: Add GCC and RPMCC node support Add support for RPMCC and GCC nodes on Shikra platforms. Signed-off-by: Imran Shaik --- arch/arm64/boot/dts/qcom/shikra.dtsi | 39 ++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 46534b9452adc..d5869aaaf5133 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -3,6 +3,8 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include #include / { @@ -91,6 +93,20 @@ }; }; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -114,6 +130,13 @@ rpm_requests: rpm-requests { compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm"; qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-shikra", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; }; }; @@ -278,6 +301,22 @@ }; }; + gcc: clock-controller@1400000 { + compatible = "qcom,shikra-gcc"; + reg = <0x0 0x01400000 0x0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + qfprom: efuse@1b44000 { compatible = "qcom,shikra-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; From ae5db676b6194f986a9036908b1b53e1ad90c1f7 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 9 Mar 2026 16:42:57 +0530 Subject: [PATCH 0516/1330] FROMLIST: ASoC: dt-bindings: qcom,q6apm-lpass-dais: Document DAI subnode Extend the qcom,q6apm-lpass-dais device tree binding to explicitly describe Digital Audio Interface (DAI) child nodes. Add #address-cells and #size-cells to allow representation of multiple DAI instances as child nodes, and define a dai@ pattern to document per-DAI properties such as the interface ID and associated clocks. Qualcomm platforms like talos integrate third-party audio codecs or use different external audio paths. These designs often require additional configuration such as explicit MI2S MCLK settings for audio to work. Link: https://lore.kernel.org/all/20260309111300.2484262-2-mohammad.rafi.shaik@oss.qualcomm.com/ Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Signed-off-by: Mohammad Rafi Shaik --- .../bindings/sound/qcom,q6apm-lpass-dais.yaml | 41 ++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml b/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml index 2fb95544db8b5..1d770cbcb058a 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml @@ -21,6 +21,34 @@ properties: '#sound-dai-cells': const: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +# Digital Audio Interfaces +patternProperties: + '^dai@[0-9]+$': + type: object + description: + Q6DSP Digital Audio Interfaces. + + properties: + reg: + description: + Digital Audio Interface ID + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + + additionalProperties: false + required: - compatible - '#sound-dai-cells' @@ -29,7 +57,18 @@ unevaluatedProperties: false examples: - | - dais { + #include + + bedais { compatible = "qcom,q6apm-lpass-dais"; #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dai@16 { + reg = ; + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_1 + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + }; }; From d31174d5b61bd34293d5c1b70f47e43a85ce5d48 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 9 Mar 2026 16:42:58 +0530 Subject: [PATCH 0517/1330] FROMLIST: ASoC: qcom: qdsp6: q6prm: add the missing LPASS MCLK clock IDs Add the missing LPASS MCLK ids for the q6prm ADSP. Link: https://lore.kernel.org/all/20260309111300.2484262-3-mohammad.rafi.shaik@oss.qualcomm.com/ Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Signed-off-by: Mohammad Rafi Shaik --- sound/soc/qcom/qdsp6/q6prm-clocks.c | 5 +++++ sound/soc/qcom/qdsp6/q6prm.h | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6prm-clocks.c index 4c574b48ab004..51b131fa95316 100644 --- a/sound/soc/qcom/qdsp6/q6prm-clocks.c +++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c @@ -42,6 +42,11 @@ static const struct q6dsp_clk_init q6prm_clks[] = { Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT), Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT), Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR), + Q6PRM_CLK(LPASS_CLK_ID_MCLK_1), + Q6PRM_CLK(LPASS_CLK_ID_MCLK_2), + Q6PRM_CLK(LPASS_CLK_ID_MCLK_3), + Q6PRM_CLK(LPASS_CLK_ID_MCLK_4), + Q6PRM_CLK(LPASS_CLK_ID_MCLK_5), Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK), Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK), Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK), diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h index a988a32086fe1..8296370e3cbf7 100644 --- a/sound/soc/qcom/qdsp6/q6prm.h +++ b/sound/soc/qcom/qdsp6/q6prm.h @@ -52,6 +52,17 @@ /* Clock ID for QUINARY MI2S OSR CLK */ #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116 +/* Clock ID for MCLK1 */ +#define Q6PRM_LPASS_CLK_ID_MCLK_1 0x300 +/* Clock ID for MCLK2 */ +#define Q6PRM_LPASS_CLK_ID_MCLK_2 0x301 +/* Clock ID for MCLK3 */ +#define Q6PRM_LPASS_CLK_ID_MCLK_3 0x302 +/* Clock ID for MCLK4 */ +#define Q6PRM_LPASS_CLK_ID_MCLK_4 0x303 +/* Clock ID for MCLK5 */ +#define Q6PRM_LPASS_CLK_ID_MCLK_5 0x304 + #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306 From be0d4ee6be146ed79e5ea1fa88a6b8bc9ad06535 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 9 Mar 2026 16:42:59 +0530 Subject: [PATCH 0518/1330] FROMLIST: ASoC: qcom: q6apm-lpass-dais: Add MI2S clock control Add support for MI2S clock control within q6apm-lpass DAIs, including handling of MCLK, BCLK, and ECLK via the DAI .set_sysclk callback. Each MI2S port now retrieves its clock handles from the device tree, allowing per-port clock configuration and proper enable/disable during startup and shutdown. Link: https://lore.kernel.org/all/20260309111300.2484262-4-mohammad.rafi.shaik@oss.qualcomm.com/ Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Signed-off-by: Mohammad Rafi Shaik --- sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 137 +++++++++++++++++++++++- sound/soc/qcom/qdsp6/q6prm.h | 4 + 2 files changed, 139 insertions(+), 2 deletions(-) diff --git a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c index ba64117b8cfe1..d7541b5c7085d 100644 --- a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c +++ b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c @@ -2,10 +2,12 @@ // Copyright (c) 2021, Linaro Limited #include +#include #include #include #include #include +#include #include #include #include @@ -15,13 +17,22 @@ #include "q6dsp-common.h" #include "audioreach.h" #include "q6apm.h" +#include "q6prm.h" #define AUDIOREACH_BE_PCM_BASE 16 +struct q6apm_dai_priv_data { + struct clk *mclk; + struct clk *bclk; + struct clk *eclk; + bool mclk_enabled, bclk_enabled, eclk_enabled; +}; + struct q6apm_lpass_dai_data { struct q6apm_graph *graph[APM_PORT_MAX]; bool is_port_started[APM_PORT_MAX]; struct audioreach_module_config module_config[APM_PORT_MAX]; + struct q6apm_dai_priv_data priv[APM_PORT_MAX]; }; static int q6dma_set_channel_map(struct snd_soc_dai *dai, @@ -238,6 +249,70 @@ static int q6apm_lpass_dai_startup(struct snd_pcm_substream *substream, struct s return 0; } +static int q6i2s_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) +{ + return q6apm_lpass_dai_startup(substream, dai); +} + +static void q6i2s_lpass_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) +{ + struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); + + if (dai_data->priv[dai->id].mclk_enabled) { + clk_disable_unprepare(dai_data->priv[dai->id].mclk); + dai_data->priv[dai->id].mclk_enabled = false; + } + + if (dai_data->priv[dai->id].bclk_enabled) { + clk_disable_unprepare(dai_data->priv[dai->id].bclk); + dai_data->priv[dai->id].bclk_enabled = false; + } + + if (dai_data->priv[dai->id].eclk_enabled) { + clk_disable_unprepare(dai_data->priv[dai->id].eclk); + dai_data->priv[dai->id].eclk_enabled = false; + } + q6apm_lpass_dai_shutdown(substream, dai); +} + +static int q6i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir) +{ + struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); + struct clk *sysclk; + bool *enabled; + int ret = 0; + + switch (clk_id) { + case LPAIF_MI2S_MCLK: + sysclk = dai_data->priv[dai->id].mclk; + enabled = &dai_data->priv[dai->id].mclk_enabled; + break; + case LPAIF_MI2S_BCLK: + sysclk = dai_data->priv[dai->id].bclk; + enabled = &dai_data->priv[dai->id].bclk_enabled; + break; + case LPAIF_MI2S_ECLK: + sysclk = dai_data->priv[dai->id].eclk; + enabled = &dai_data->priv[dai->id].eclk_enabled; + break; + default: + break; + } + + if (sysclk) { + clk_set_rate(sysclk, freq); + ret = clk_prepare_enable(sysclk); + if (ret) { + dev_err(dai->dev, "Error, Unable to prepare (%d) sysclk\n", clk_id); + return ret; + } + + *enabled = true; + } + + return ret; +} + static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); @@ -258,11 +333,12 @@ static const struct snd_soc_dai_ops q6dma_ops = { static const struct snd_soc_dai_ops q6i2s_ops = { .prepare = q6apm_lpass_dai_prepare, - .startup = q6apm_lpass_dai_startup, - .shutdown = q6apm_lpass_dai_shutdown, + .startup = q6i2s_dai_startup, + .shutdown = q6i2s_lpass_dai_shutdown, .set_channel_map = q6dma_set_channel_map, .hw_params = q6dma_hw_params, .set_fmt = q6i2s_set_fmt, + .set_sysclk = q6i2s_set_sysclk, }; static const struct snd_soc_dai_ops q6hdmi_ops = { @@ -281,6 +357,59 @@ static const struct snd_soc_component_driver q6apm_lpass_dai_component = { .remove_order = SND_SOC_COMP_ORDER_FIRST, }; +static int of_q6apm_parse_dai_data(struct device *dev, + struct q6apm_lpass_dai_data *data) +{ + struct device_node *node; + int ret; + + for_each_child_of_node(dev->of_node, node) { + struct q6apm_dai_priv_data *priv; + int id; + + ret = of_property_read_u32(node, "reg", &id); + if (ret || id < 0 || id >= APM_PORT_MAX) { + dev_err(dev, "valid dai id not found:%d\n", ret); + continue; + } + + switch (id) { + /* MI2S specific properties */ + case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: + priv = &data->priv[id]; + priv->mclk = of_clk_get_by_name(node, "mclk"); + if (IS_ERR(priv->mclk)) { + if (PTR_ERR(priv->mclk) == -EPROBE_DEFER) + return dev_err_probe(dev, PTR_ERR(priv->mclk), + "unable to get mi2s mclk\n"); + priv->mclk = NULL; + } + + priv->bclk = of_clk_get_by_name(node, "bclk"); + if (IS_ERR(priv->bclk)) { + if (PTR_ERR(priv->bclk) == -EPROBE_DEFER) + return dev_err_probe(dev, PTR_ERR(priv->bclk), + "unable to get mi2s bclk\n"); + priv->bclk = NULL; + } + + priv->eclk = of_clk_get_by_name(node, "eclk"); + if (IS_ERR(priv->eclk)) { + if (PTR_ERR(priv->eclk) == -EPROBE_DEFER) + return dev_err_probe(dev, PTR_ERR(priv->eclk), + "unable to get mi2s eclk\n"); + priv->eclk = NULL; + } + break; + default: + break; + } + } + + return 0; +} + static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev) { struct q6dsp_audio_port_dai_driver_config cfg; @@ -288,12 +417,16 @@ static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev) struct snd_soc_dai_driver *dais; struct device *dev = &pdev->dev; int num_dais; + int ret; dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL); if (!dai_data) return -ENOMEM; dev_set_drvdata(dev, dai_data); + ret = of_q6apm_parse_dai_data(dev, dai_data); + if (ret) + return ret; memset(&cfg, 0, sizeof(cfg)); cfg.q6i2s_ops = &q6i2s_ops; diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h index 8296370e3cbf7..a00d1eda1e708 100644 --- a/sound/soc/qcom/qdsp6/q6prm.h +++ b/sound/soc/qcom/qdsp6/q6prm.h @@ -3,6 +3,10 @@ #ifndef __Q6PRM_H__ #define __Q6PRM_H__ +#define LPAIF_MI2S_MCLK 1 +#define LPAIF_MI2S_BCLK 2 +#define LPAIF_MI2S_ECLK 3 + /* Clock ID for Primary I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100 /* Clock ID for Primary I2S EBIT */ From 758665dc0f5fabaef3d74a4305a4b238bdcfb7d2 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 9 Mar 2026 16:43:00 +0530 Subject: [PATCH 0519/1330] FROMLIST: ASoC: qcom: sc8280xp: ASoC: qcom: sc8280xp: enhance machine driver for board-specific config The sc8280xp machine driver is currently written with a largely SoC-centric view and assumes a uniform audio topology across all boards. In practice, multiple products based on the same SoC use different board designs and external audio components, which require board-specific configuration to function correctly. Several Qualcomm platforms like talos integrate third-party audio codecs or use different external audio paths. These designs often require additional configuration such as explicit MI2S MCLK settings for audio to work. This change enhances the sc8280xp machine driver to support board-specific configuration such as allowing each board variant to provide its own DAPM widgets and routes, reflecting the actual audio components and connectors present and enabling MI2S MCLK programming for boards that use external codecs requiring a stable master clock. Link: https://lore.kernel.org/all/20260309111300.2484262-5-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik --- sound/soc/qcom/sc8280xp.c | 180 ++++++++++++++++++++++++++++++++++---- 1 file changed, 162 insertions(+), 18 deletions(-) diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c index 7925aa3f63ba0..c2e9323dff90c 100644 --- a/sound/soc/qcom/sc8280xp.c +++ b/sound/soc/qcom/sc8280xp.c @@ -12,17 +12,62 @@ #include #include #include "qdsp6/q6afe.h" +#include "qdsp6/q6apm.h" +#include "qdsp6/q6prm.h" #include "common.h" #include "sdw.h" +#define MCLK_FREQ 12288000 +#define MCLK_NATIVE_FREQ 11289600 + +static struct snd_soc_dapm_widget sc8280xp_dapm_widgets[] = { + SND_SOC_DAPM_HP("Headphone Jack", NULL), + SND_SOC_DAPM_MIC("Mic Jack", NULL), + SND_SOC_DAPM_SPK("DP0 Jack", NULL), + SND_SOC_DAPM_SPK("DP1 Jack", NULL), + SND_SOC_DAPM_SPK("DP2 Jack", NULL), + SND_SOC_DAPM_SPK("DP3 Jack", NULL), + SND_SOC_DAPM_SPK("DP4 Jack", NULL), + SND_SOC_DAPM_SPK("DP5 Jack", NULL), + SND_SOC_DAPM_SPK("DP6 Jack", NULL), + SND_SOC_DAPM_SPK("DP7 Jack", NULL), +}; + +struct snd_soc_common { + char *driver_name; + const struct snd_soc_dapm_widget *dapm_widgets; + int num_dapm_widgets; + const struct snd_soc_dapm_route *dapm_routes; + int num_dapm_routes; + bool mi2s_mclk_enable; +}; + struct sc8280xp_snd_data { bool stream_prepared[AFE_PORT_MAX]; struct snd_soc_card *card; struct snd_soc_jack jack; struct snd_soc_jack dp_jack[8]; + struct snd_soc_common *snd_soc_common_priv; bool jack_setup; }; +static inline int sc8280xp_get_mclk_feq(unsigned int rate) +{ + int freq = MCLK_FREQ; + + switch (rate) { + case SNDRV_PCM_RATE_11025: + case SNDRV_PCM_RATE_44100: + case SNDRV_PCM_RATE_88200: + freq = MCLK_NATIVE_FREQ; + break; + default: + break; + } + + return freq; +} + static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd) { struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card); @@ -32,10 +77,6 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd) int dp_pcm_id = 0; switch (cpu_dai->id) { - case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX: - case QUINARY_MI2S_RX...QUINARY_MI2S_TX: - snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP); - break; case WSA_CODEC_DMA_RX_0: case WSA_CODEC_DMA_RX_1: /* @@ -96,6 +137,31 @@ static int sc8280xp_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, return 0; } +static int sc8280xp_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); + struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card); + int mclk_freq = sc8280xp_get_mclk_feq(params_rate(params)); + + switch (cpu_dai->id) { + case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX: + case QUINARY_MI2S_RX...QUINARY_MI2S_TX: + snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP); + + if (data->snd_soc_common_priv->mi2s_mclk_enable) + snd_soc_dai_set_sysclk(cpu_dai, + LPAIF_MI2S_MCLK, mclk_freq, + SND_SOC_CLOCK_IN); + break; + default: + break; + }; + + return 0; +} + static int sc8280xp_snd_prepare(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); @@ -117,6 +183,7 @@ static int sc8280xp_snd_hw_free(struct snd_pcm_substream *substream) static const struct snd_soc_ops sc8280xp_be_ops = { .startup = qcom_snd_sdw_startup, .shutdown = qcom_snd_sdw_shutdown, + .hw_params = sc8280xp_snd_hw_params, .hw_free = sc8280xp_snd_hw_free, .prepare = sc8280xp_snd_prepare, }; @@ -145,37 +212,114 @@ static int sc8280xp_platform_probe(struct platform_device *pdev) card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); if (!card) return -ENOMEM; - card->owner = THIS_MODULE; + /* Allocate the private data */ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; + data->snd_soc_common_priv = (struct snd_soc_common *)of_device_get_match_data(dev); + if (!data->snd_soc_common_priv) + return -ENOMEM; + + card->owner = THIS_MODULE; card->dev = dev; dev_set_drvdata(dev, card); snd_soc_card_set_drvdata(card, data); + card->dapm_widgets = data->snd_soc_common_priv->dapm_widgets; + card->num_dapm_widgets = data->snd_soc_common_priv->num_dapm_widgets; + card->dapm_routes = data->snd_soc_common_priv->dapm_routes; + card->num_dapm_routes = data->snd_soc_common_priv->num_dapm_routes; + ret = qcom_snd_parse_of(card); if (ret) return ret; - card->driver_name = of_device_get_match_data(dev); + card->driver_name = data->snd_soc_common_priv->driver_name; sc8280xp_add_be_ops(card); return devm_snd_soc_register_card(dev, card); } +static struct snd_soc_common kaanapali_priv_data = { + .driver_name = "kaanapali", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common qcs9100_priv_data = { + .driver_name = "sa8775p", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common qcs615_priv_data = { + .driver_name = "qcs615", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), + .mi2s_mclk_enable = true, +}; + +static struct snd_soc_common qcm6490_priv_data = { + .driver_name = "qcm6490", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common qcs6490_priv_data = { + .driver_name = "qcs6490", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common qcs8275_priv_data = { + .driver_name = "qcs8300", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common sc8280xp_priv_data = { + .driver_name = "sc8280xp", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common sm8450_priv_data = { + .driver_name = "sm8450", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common sm8550_priv_data = { + .driver_name = "sm8550", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common sm8650_priv_data = { + .driver_name = "sm8650", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static struct snd_soc_common sm8750_priv_data = { + .driver_name = "sm8750", + .dapm_widgets = sc8280xp_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + static const struct of_device_id snd_sc8280xp_dt_match[] = { - {.compatible = "qcom,kaanapali-sndcard", "kaanapali"}, - {.compatible = "qcom,qcm6490-idp-sndcard", "qcm6490"}, - {.compatible = "qcom,qcs615-sndcard", "qcs615"}, - {.compatible = "qcom,qcs6490-rb3gen2-sndcard", "qcs6490"}, - {.compatible = "qcom,qcs8275-sndcard", "qcs8300"}, - {.compatible = "qcom,qcs9075-sndcard", "sa8775p"}, - {.compatible = "qcom,qcs9100-sndcard", "sa8775p"}, - {.compatible = "qcom,sc8280xp-sndcard", "sc8280xp"}, - {.compatible = "qcom,sm8450-sndcard", "sm8450"}, - {.compatible = "qcom,sm8550-sndcard", "sm8550"}, - {.compatible = "qcom,sm8650-sndcard", "sm8650"}, - {.compatible = "qcom,sm8750-sndcard", "sm8750"}, + {.compatible = "qcom,kaanapali-sndcard", .data = &kaanapali_priv_data}, + {.compatible = "qcom,qcm6490-idp-sndcard", .data = &qcm6490_priv_data}, + {.compatible = "qcom,qcs615-sndcard", .data = &qcs615_priv_data}, + {.compatible = "qcom,qcs6490-rb3gen2-sndcard", .data = &qcs6490_priv_data}, + {.compatible = "qcom,qcs8275-sndcard", .data = &qcs8275_priv_data}, + {.compatible = "qcom,qcs9075-sndcard", .data = &qcs9100_priv_data}, + {.compatible = "qcom,qcs9100-sndcard", .data = &qcs9100_priv_data}, + {.compatible = "qcom,sc8280xp-sndcard", .data = &sc8280xp_priv_data}, + {.compatible = "qcom,sm8450-sndcard", .data = &sm8450_priv_data}, + {.compatible = "qcom,sm8550-sndcard", .data = &sm8550_priv_data}, + {.compatible = "qcom,sm8650-sndcard", .data = &sm8650_priv_data}, + {.compatible = "qcom,sm8750-sndcard", .data = &sm8750_priv_data}, {} }; From ee21a66680c16a67ab3348558608fbd08acbe512 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 30 Mar 2026 16:31:38 +0530 Subject: [PATCH 0520/1330] arm64: dts: qcom: Add SPMI bus controller for Shikra Add spmi-pmic-arb device for the SPMI PMIC arbiter found on shikra. Signed-off-by: Rakesh Kota --- arch/arm64/boot/dts/qcom/shikra.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index d5869aaaf5133..e9a4c7b63eb3b 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -329,6 +329,28 @@ }; }; + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x0 0x045f0000 0x0 0x7000>; From 0f0334acdffe27a511c61de614eb04bab79540ae Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 30 Mar 2026 18:13:38 +0530 Subject: [PATCH 0521/1330] arm64: dts: qcom: Add RPM power domain controller for shikra Add the RPM SMD power domain controller node for Shikra with a complete OPP table covering all 8 voltage corners from MIN_SVS to TURBO_NO_CPR. Signed-off-by: Rakesh Kota --- arch/arm64/boot/dts/qcom/shikra.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index e9a4c7b63eb3b..202c21096d5ee 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include @@ -137,6 +138,48 @@ clock-names = "xo"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,shikra-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; }; }; From 6ad7796c95dc4f350977f0452ec7e54397a901d0 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 30 Mar 2026 16:32:39 +0530 Subject: [PATCH 0522/1330] arm64: dts: qcom: Add regulator for Retail and Industrial SOM variants Add RPM regulator for the Shikra Retail (CQM/CQS) SOM variants using pm4125-regulators with S1-S4 buck switchers and L1-L22 LDOs, and for the Industrial (IQS) SOM variant using pm8150-regulators with S4-S9 buck switchers and L1-L18 LDOs. Signed-off-by: Rakesh Kota --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 131 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi | 131 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 120 +++++++++++++++++ 3 files changed, 382 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 75ae79daf3b45..79ea476c7c4a6 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -6,3 +6,134 @@ #include "shikra.dtsi" /* Modem, Cocos + Kunlun PMIC */ + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; + + pm4125_s1: s1 { + regulator-min-microvolt = <1396000>; + regulator-max-microvolt = <1950000>; + }; + + pm4125_s2: s2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm4125_s4: s4 { + regulator-min-microvolt = <640000>; + regulator-max-microvolt = <1414000>; + }; + + pm4125_l1: l1 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l2: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm4125_l3: l3 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pm4125_l4: l4 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + pm4125_l5: l5 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l6: l6 { + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + }; + + pm4125_l7: l7 { + regulator-min-microvolt = <664000>; + regulator-max-microvolt = <664000>; + }; + + pm4125_l8: l8 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm4125_l9: l9 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm4125_l10: l10 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l11: l11 { + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1150000>; + }; + + pm4125_l12: l12 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + }; + + pm4125_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + }; + + pm4125_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + }; + + pm4125_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + pm4125_l16: l16 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm4125_l17: l17 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3544000>; + }; + + pm4125_l18: l18 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3300000>; + }; + + pm4125_l19: l19 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3300000>; + }; + + pm4125_l20: l20 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + pm4125_l21: l21 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + pm4125_l22: l22 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi index be745fe517e88..2434c997173e2 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi @@ -6,3 +6,134 @@ #include "shikra.dtsi" /* APQ (No Modem), Cocos + Kunlun PMIC */ + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; + + pm4125_s1: s1 { + regulator-min-microvolt = <1396000>; + regulator-max-microvolt = <1950000>; + }; + + pm4125_s2: s2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm4125_s4: s4 { + regulator-min-microvolt = <640000>; + regulator-max-microvolt = <1414000>; + }; + + pm4125_l1: l1 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l2: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm4125_l3: l3 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pm4125_l4: l4 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + pm4125_l5: l5 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l6: l6 { + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + }; + + pm4125_l7: l7 { + regulator-min-microvolt = <664000>; + regulator-max-microvolt = <664000>; + }; + + pm4125_l8: l8 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm4125_l9: l9 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm4125_l10: l10 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l11: l11 { + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1150000>; + }; + + pm4125_l12: l12 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + }; + + pm4125_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + }; + + pm4125_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + }; + + pm4125_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + pm4125_l16: l16 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm4125_l17: l17 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3544000>; + }; + + pm4125_l18: l18 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3300000>; + }; + + pm4125_l19: l19 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3300000>; + }; + + pm4125_l20: l20 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + pm4125_l21: l21 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + pm4125_l22: l22 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi index a916caa73d823..9581f98b7d08e 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -6,3 +6,123 @@ #include "shikra.dtsi" /* APQ (No Modem), Wailua PMIC */ +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8150-regulators"; + + pm8150_s4: s4 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <2040000>; + }; + + pm8150_s5: s5 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + pm8150_s6: s6 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1352000>; + }; + + pm8150_s7: s7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm8150_s8: s8 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pm8150_l1: l1 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + }; + + pm8150_l2: l2 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + pm8150_l3: l3 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + }; + + pm8150_l4: l4 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + }; + + pm8150_l5: l5 { + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + }; + + pm8150_l6: l6 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm8150_l7: l7 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm8150_l8: l8 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1304000>; + }; + + pm8150_l9: l9 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm8150_l10:l10{ + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + pm8150_l11:l11{ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm8150_l12:l12{ + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + pm8150_l13:l13{ + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3230000>; + }; + + pm8150_l14:l14{ + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1910000>; + }; + + pm8150_l15:l15{ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8150_l16:l16{ + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + pm8150_l17:l17{ + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + pm8150_l18:l18{ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + }; +}; From 12770added450a7ddc88437569b59943341448e1 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Tue, 24 Mar 2026 14:04:04 +0800 Subject: [PATCH 0523/1330] FROMLIST: arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM pins This patch adds the Generic Pack Router (GPR) node together with Audio Process Manager (APM) and Proxy Resource Manager (PRM) audio service nodes to the Talos device tree description. It also introduces MI2S1 pinctrl states for data0, data1, sck, and ws lines, grouped into a single entry at the SoC-level DTSI for better reuse and clarity. Link: https://lore.kernel.org/all/20260324060405.3098891-1-le.qi@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Le Qi --- arch/arm64/boot/dts/qcom/talos.dtsi | 54 +++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index faa472b216b53..6323aa0e117d8 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include #include / { @@ -1616,6 +1617,20 @@ bias-pull-up; }; + mi2s1_pins: mi2s1-state { + pins = "gpio108", "gpio109", "gpio110", "gpio111"; + function = "mi2s_1"; + drive-strength = <8>; + bias-disable; + }; + + mi2s_mclk: mi2s-mclk-state { + pins = "gpio122"; + function = "mclk2"; + drive-strength = <8>; + bias-disable; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -5159,6 +5174,45 @@ dma-coherent; }; }; + + gpr: gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1721 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; From a6a151e8f9bdc2fae50bab50db4e4ff355c29870 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Tue, 24 Mar 2026 14:04:05 +0800 Subject: [PATCH 0524/1330] FROMLIST: arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codec Add the sound card node for QCS615 Talos EVK with DA7212 codec connected over the Primary MI2S interface. The configuration enables headphone playback and headset microphone capture, both of which have been tested to work. Link: https://lore.kernel.org/all/20260324060405.3098891-1-le.qi@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Le Qi --- arch/arm64/boot/dts/qcom/talos-evk.dts | 65 ++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/qcom/talos-evk.dts index af100e22beeec..6352d614e288c 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "talos-evk-som.dtsi" +#include / { model = "Qualcomm QCS615 IQ 615 EVK"; @@ -40,6 +41,46 @@ }; }; + sound { + compatible = "qcom,qcs615-sndcard"; + model = "TALOS-EVK"; + + pinctrl-0 = <&mi2s1_pins>, <&mi2s_mclk>; + pinctrl-names = "default"; + + pri-mi2s-capture-dai-link { + link-name = "Primary MI2S Capture"; + + codec { + sound-dai = <&codec_da7212>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + pri-mi2s-playback-dai-link { + link-name = "Primary MI2S Playback"; + + codec { + sound-dai = <&codec_da7212>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vreg_v1p8_out: regulator-v1p8-out { compatible = "regulator-fixed"; regulator-name = "vreg-v1p8-out"; @@ -109,6 +150,19 @@ }; }; +&i2c5 { + status = "okay"; + + codec_da7212: codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + #sound-dai-cells = <0>; + VDDA-supply = <&vreg_v1p8_out>; + VDDIO-supply = <&vreg_v1p8_out>; + VDDMIC-supply = <&vreg_v3p3_out>; + }; +}; + &mdss_dsi0_out { remote-endpoint = <&adv7535_in>; data-lanes = <0 1 2 3>; @@ -124,6 +178,17 @@ status = "okay"; }; +&q6apmbedai { + #address-cells = <1>; + #size-cells = <0>; + + dai@17 { + reg = ; + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_2 LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + }; +}; + &sdhc_2 { pinctrl-0 = <&sdc2_state_on>; pinctrl-1 = <&sdc2_state_off>; From 16d25a350ecc121f881b0cab69bf28a8e6818a41 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 19 Jan 2026 14:24:54 +0530 Subject: [PATCH 0525/1330] FROMLIST: arm64: dts: qcom: talos: Add EL2 overlay All the existing variants Talos boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Talos IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Link: https://lore.kernel.org/lkml/20260127-talos-el2-overlay-v2-3-b6a2266532c4@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ arch/arm64/boot/dts/qcom/talos-el2.dtso | 25 +++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 29a569a54a218..61fb9d55add0e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -161,6 +161,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb + +qcs615-ride-el2-dtbs := qcs615-ride.dtb talos-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb diff --git a/arch/arm64/boot/dts/qcom/talos-el2.dtso b/arch/arm64/boot/dts/qcom/talos-el2.dtso new file mode 100644 index 0000000000000..f6818c058d724 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-el2.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + + * Talos specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +&gpu_zap_shader { + status = "disabled"; +}; + +&remoteproc_adsp { + iommus = <&apps_smmu 0x1720 0x0>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x1080 0x0>; +}; + +&venus { + status = "disabled"; +}; From e42c60287ac81196b20c85a80a8c95f4818662d5 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Tue, 3 Feb 2026 17:32:31 +0800 Subject: [PATCH 0526/1330] PENDING: arm64: dts: qcom: talos-evk-som: Enable Adreno 612 GPU Enable GPU for talos-evk-som platform and provide path for zap shader. Signed-off-by: Jie Zhang --- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index f877a3e5d0b00..de16916e98f5b 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -317,6 +317,14 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs615/a612_zap.mbn"; +}; + &i2c5 { clock-frequency = <400000>; status = "okay"; From fe6d55b64aae67a4d1ae7542e308bbba5fec4a26 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 13 Feb 2026 19:20:25 +0530 Subject: [PATCH 0527/1330] FROMLIST: arm64: dts: qcom: talos: Flatten usb controller nodes Flatten usb controller nodes and update to using latest bindings and flattened driver approach. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260128062720.437712-2-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 +-- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 12 +-- arch/arm64/boot/dts/qcom/talos.dtsi | 87 +++++++++------------ 3 files changed, 46 insertions(+), 65 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index e5ce9a4faa9cb..164e1a6ad6ac2 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -670,11 +670,9 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "peripheral"; + + status = "okay"; }; &usb_2_hsphy { @@ -686,11 +684,9 @@ }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index de16916e98f5b..7f0e91a3d67a7 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -555,11 +555,9 @@ */ &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_hsphy { @@ -571,11 +569,9 @@ }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 6323aa0e117d8..c8ed9e61f8e98 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -4964,9 +4964,9 @@ status = "disabled"; }; - usb_1: usb@a6f8800 { - compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4985,52 +4985,47 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; + iommus = <&apps_smmu 0x140 0x0>; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; + phys = <&usb_hsphy_1>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&gcc GCC_USB30_PRIM_BCR>; #address-cells = <2>; #size-cells = <2>; ranges; - status = "disabled"; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xcd00>; - - iommus = <&apps_smmu 0x140 0x0>; - interrupts = ; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; - phys = <&usb_1_hsphy>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - }; + status = "disabled"; }; - usb_2: usb@a8f8800 { - compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a8f8800 0x0 0x400>; + usb_2: usb@a800000 { + compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a800000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, <&gcc GCC_USB20_SEC_MASTER_CLK>, @@ -5049,18 +5044,24 @@ <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; + iommus = <&apps_smmu 0xe0 0x0>; power-domains = <&gcc USB20_SEC_GDSC>; required-opps = <&rpmhpd_opp_nom>; + phys = <&usb_hsphy_2>; + phy-names = "usb2-phy"; + resets = <&gcc GCC_USB20_SEC_BCR>; qcom,select-utmi-as-pipe-clk; @@ -5069,26 +5070,14 @@ #size-cells = <2>; ranges; - status = "disabled"; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a800000 0x0 0xcd00>; - - iommus = <&apps_smmu 0xe0 0x0>; - interrupts = ; - - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - - maximum-speed = "high-speed"; - }; + status = "disabled"; }; tsens0: thermal-sensor@c263000 { From 9a97f258daf4afe79a1d4de3a57c9486e761ce4f Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 13 Feb 2026 19:22:50 +0530 Subject: [PATCH 0528/1330] FROMLIST: arm64: dts: qcom: talos: Mark usb controllers are wakeup capable devices USB controllers on talos are wakeup capable. Hence add wakeup-source property to both controller nodes. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/all/20260128062720.437712-3-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index c8ed9e61f8e98..e5ad7f6f68bbd 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -5020,6 +5020,8 @@ snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + wakeup-source; + status = "disabled"; }; @@ -5077,6 +5079,8 @@ snps,hird-threshold = /bits/ 8 <0x10>; maximum-speed = "high-speed"; + wakeup-source; + status = "disabled"; }; From ec30eec8b7faa5117caf7c22d2cad671fbc9dfe5 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 13 Mar 2026 14:56:11 +0530 Subject: [PATCH 0529/1330] Revert "FROMLIST: arm64: dts: qcom: talos: Mark usb controllers are wakeup capable devices" This reverts commit 6f583fcc990caa11dcbe54ffd51908f9b6e42a26. Reason for revert: compilation issue due to commit 6f583fcc990caa11dcbe54ffd51908f9b6e42a26. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index e5ad7f6f68bbd..c8ed9e61f8e98 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -5020,8 +5020,6 @@ snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; - wakeup-source; - status = "disabled"; }; @@ -5079,8 +5077,6 @@ snps,hird-threshold = /bits/ 8 <0x10>; maximum-speed = "high-speed"; - wakeup-source; - status = "disabled"; }; From 4f71c5a5c4309de5fd9e39cb9a81985bb7a88c44 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 13 Mar 2026 14:56:11 +0530 Subject: [PATCH 0530/1330] Revert "FROMLIST: arm64: dts: qcom: talos: Flatten usb controller nodes" This reverts commit 94c450310e8905d3767414f75c312c42408d9f53. Reason for revert: compilation issue due to mismatch of USB phy node. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 ++- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 12 ++- arch/arm64/boot/dts/qcom/talos.dtsi | 87 ++++++++++++--------- 3 files changed, 65 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 164e1a6ad6ac2..e5ce9a4faa9cb 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -670,11 +670,13 @@ }; &usb_1 { - dr_mode = "peripheral"; - status = "okay"; }; +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + &usb_2_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; @@ -684,11 +686,13 @@ }; &usb_2 { - dr_mode = "host"; - status = "okay"; }; +&usb_2_dwc3 { + dr_mode = "host"; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l17a>; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 7f0e91a3d67a7..de16916e98f5b 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -555,11 +555,13 @@ */ &usb_1 { - dr_mode = "host"; - status = "okay"; }; +&usb_1_dwc3 { + dr_mode = "host"; +}; + &usb_1_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; @@ -569,11 +571,13 @@ }; &usb_2 { - dr_mode = "host"; - status = "okay"; }; +&usb_2_dwc3 { + dr_mode = "host"; +}; + &usb_2_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index c8ed9e61f8e98..6323aa0e117d8 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -4964,9 +4964,9 @@ status = "disabled"; }; - usb_1: usb@a600000 { - compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; - reg = <0x0 0x0a600000 0x0 0xfc100>; + usb_1: usb@a6f8800 { + compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4985,47 +4985,52 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dwc_usb3", - "pwr_event", + interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; - iommus = <&apps_smmu 0x140 0x0>; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&usb_hsphy_1>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - resets = <&gcc GCC_USB30_PRIM_BCR>; #address-cells = <2>; #size-cells = <2>; ranges; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xcd00>; + + iommus = <&apps_smmu 0x140 0x0>; + interrupts = ; + + phys = <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + }; }; - usb_2: usb@a800000 { - compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; - reg = <0x0 0x0a800000 0x0 0xfc100>; + usb_2: usb@a8f8800 { + compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a8f8800 0x0 0x400>; clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, <&gcc GCC_USB20_SEC_MASTER_CLK>, @@ -5044,24 +5049,18 @@ <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "dwc_usb3", - "pwr_event", + interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; - iommus = <&apps_smmu 0xe0 0x0>; power-domains = <&gcc USB20_SEC_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&usb_hsphy_2>; - phy-names = "usb2-phy"; - resets = <&gcc GCC_USB20_SEC_BCR>; qcom,select-utmi-as-pipe-clk; @@ -5070,14 +5069,26 @@ #size-cells = <2>; ranges; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - maximum-speed = "high-speed"; - status = "disabled"; + + usb_2_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a800000 0x0 0xcd00>; + + iommus = <&apps_smmu 0xe0 0x0>; + interrupts = ; + + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + + maximum-speed = "high-speed"; + }; }; tsens0: thermal-sensor@c263000 { From 52a0226f1299c06d97862fd02f9cb3cd3cc5c357 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 16 Mar 2026 12:32:42 +0800 Subject: [PATCH 0531/1330] FROMLIST: arm64: dts: qcom: remove the disabled replicator Remove the disabled device that blocks probing of the connected replicator, as the replicator driver validates all connected devices during probe. kernel log: [ 18.540971] platform 6046000.replicator: deferred probe pending: (reason unknown) Link: https://lore.kernel.org/all/20260316-clean-up-failed-devices-v1-1-f22fc9b072ab@oss.qualcomm.com/ Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/talos.dtsi | 41 ----------------------------- 1 file changed, 41 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 6323aa0e117d8..4db5ecd641b28 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -2468,14 +2468,6 @@ remote-endpoint = <&tmc_etr_in>; }; }; - - port@1 { - reg = <1>; - - replicator0_out1: endpoint { - remote-endpoint = <&replicator1_in>; - }; - }; }; }; @@ -2522,31 +2514,6 @@ }; }; - replicator@604a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x0 0x0604a000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - status = "disabled"; - - in-ports { - port { - replicator1_in: endpoint { - remote-endpoint = <&replicator0_out1>; - }; - }; - }; - - out-ports { - port { - replicator1_out: endpoint { - remote-endpoint = <&funnel_swao_in6>; - }; - }; - }; - }; - cti@683b000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x0683b000 0x0 0x1000>; @@ -2968,14 +2935,6 @@ #address-cells = <1>; #size-cells = <0>; - port@6 { - reg = <6>; - - funnel_swao_in6: endpoint { - remote-endpoint = <&replicator1_out>; - }; - }; - port@7 { reg = <7>; From 72e39ea9da2f552ba5ef92497198b10431d8c12d Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 24 Mar 2026 18:43:20 +0530 Subject: [PATCH 0532/1330] FROMLIST: arm64: dts: qcom: talos: Add QSPI support The Talos (QCS615) platform includes a QSPI controller used for accessing external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and the QSPI controller node to enable support for this hardware. Link: https://patch.msgid.link/20260324-spi-nor-v1-3-3efe59c1c119@oss.qualcomm.com Signed-off-by: Viken Dadhaniya --- arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 4db5ecd641b28..0592ea8dff9b6 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -532,6 +532,25 @@ }; + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-60000000 { + opp-hz = /bits/ 64 <60000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-133250000 { + opp-hz = /bits/ 64 <133250000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-266500000 { + opp-hz = /bits/ 64 <266500000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; @@ -1631,6 +1650,34 @@ bias-disable; }; + qspi_cs0: qspi-cs0-state { + pins = "gpio44"; + function = "qspi"; + bias-disable; + drive-strength = <6>; + }; + + qspi_data0123: qspi-data0123-state { + pins = "gpio45", "gpio46", "gpio47", "gpio49"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + + qspi_clk: qspi-clk-state { + pins = "gpio48"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + + qspi_cs1: qspi-cs1-state { + pins = "gpio50"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -3884,6 +3931,39 @@ }; }; + qspi: spi@88df000 { + compatible = "qcom,qcs615-qspi", + "qcom,qspi-v1"; + reg = <0x0 0x088df000 0x0 0x1000>; + + interrupts = ; + + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", + "core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QSPI QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qspi-config", + "qspi-memory"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qspi_opp_table>; + + iommus = <&apps_smmu 0x160 0x0>; + + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + dc_noc: interconnect@9160000 { reg = <0x0 0x09160000 0x0 0x3200>; compatible = "qcom,qcs615-dc-noc"; From 2310a24dcc7489379366802227f13a3b8337b926 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 24 Mar 2026 20:45:34 +0530 Subject: [PATCH 0533/1330] FROMLIST: arm64: dts: qcom: qcs615-ride: enable QSPI and NOR flash The QCS615 Ride board has a SPI-NOR flash connected to the QSPI controller on CS0. Enable the QSPI controller and add the corresponding SPI-NOR flash node to allow the system to access it. Link: https://patch.msgid.link/20260324-spi-nor-v1-4-3efe59c1c119@oss.qualcomm.com Signed-off-by: Viken Dadhaniya --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index e5ce9a4faa9cb..addb6e6e66ee4 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -531,6 +531,18 @@ }; }; +&qspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From e8bc4f7dd8317bf6d6589beedc79ae1aa73abc32 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 13 Mar 2026 16:04:18 +0530 Subject: [PATCH 0534/1330] FROMLIST: arm64: dts: qcom: sm8750: Enable TSENS and thermal zones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sm8750 includes four TSENS instances, with a total of 47 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 130°C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 120°C and critical trip at 125°C. Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20260313-sm8750_tsens-v1-2-250fcc3794a2@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 897 +++++++++++++++++++++++++++ 1 file changed, 897 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 64199a0cc8d9d..74e0f88a0f9c0 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -24,6 +24,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -6111,6 +6112,902 @@ }; }; }; + + tsens0: thermal-sensor@c228000 { + compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c228000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <15>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <7>; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22a000 { + compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22a000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22b000 { + compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22b000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <9>; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-2-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-2-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-3-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-3-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-4-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-4-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-5-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-5-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss-0-0-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss-0-1-thermal { + thermal-sensors = <&tsens0 14>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss-1-0-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss-1-1-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss2-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss3-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss4-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss4-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss5-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss5-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss6-thermal { + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss6-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss7-thermal { + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss7-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem0-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + modem0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem1-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + modem1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem2-thermal { + thermal-sensors = <&tsens2 11>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + modem2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem3-thermal { + thermal-sensors = <&tsens2 12>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + modem3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors = <&tsens2 13>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera1-thermal { + thermal-sensors = <&tsens2 14>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens2 15>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + video-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx0-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx2-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx0-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx1-thermal { + thermal-sensors = <&tsens3 5>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx2-thermal { + thermal-sensors = <&tsens3 6>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx3-thermal { + thermal-sensors = <&tsens3 7>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + thermal-sensors = <&tsens3 8>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + ddr-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; timer { From dc7b179672876ac56b522d93fe91daa743d999d0 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 23 Dec 2025 18:02:20 +0530 Subject: [PATCH 0535/1330] FROMLIST: thermal: Add Remote Proc cooling driver Add a new generic driver for thermal cooling devices that control remote processors (modem, DSP, etc.) through various communication channels. This driver provides an abstraction layer between the thermal subsystem and vendor-specific remote processor communication mechanisms. Suggested-by: Amit Kucheria Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20251223123227.1317244-2-gaurav.kohli@oss.qualcomm.com --- MAINTAINERS | 8 ++ drivers/thermal/Kconfig | 11 ++ drivers/thermal/Makefile | 2 + drivers/thermal/remoteproc_cooling.c | 154 +++++++++++++++++++++++++++ include/linux/remoteproc_cooling.h | 52 +++++++++ 5 files changed, 227 insertions(+) create mode 100644 drivers/thermal/remoteproc_cooling.c create mode 100644 include/linux/remoteproc_cooling.h diff --git a/MAINTAINERS b/MAINTAINERS index 05b1f90fa79a6..844dbf5a7cebb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26317,6 +26317,14 @@ F: drivers/thermal/cpufreq_cooling.c F: drivers/thermal/cpuidle_cooling.c F: include/linux/cpu_cooling.h +THERMAL/REMOTEPROC_COOLING +M: Gaurav Kohli +L: linux-pm@vger.kernel.org +S: Supported +F: drivers/thermal/remoteproc_cooling.c +F: include/linux/remoteproc_cooling.h + + THERMAL/POWER_ALLOCATOR M: Lukasz Luba L: linux-pm@vger.kernel.org diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index b10080d618604..31e92be343871 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -229,6 +229,17 @@ config PCIE_THERMAL If you want this support, you should say Y here. + +config REMOTEPROC_THERMAL + bool "Remote processor cooling support" + help + This implements a generic cooling mechanism for remote processors + (modem, DSP, etc.) that allows vendor-specific implementations to + register thermal cooling devices and provide callbacks for thermal + mitigation. + + If you want this support, you should say Y here. + config THERMAL_EMULATION bool "Thermal emulation mode support" help diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index bb21e7ea7fc6b..ae747dde54feb 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -34,6 +34,8 @@ thermal_sys-$(CONFIG_DEVFREQ_THERMAL) += devfreq_cooling.o thermal_sys-$(CONFIG_PCIE_THERMAL) += pcie_cooling.o +thermal_sys-$(CONFIG_REMOTEPROC_THERMAL) += remoteproc_cooling.o + obj-$(CONFIG_K3_THERMAL) += k3_bandgap.o k3_j72xx_bandgap.o # platform thermal drivers obj-y += broadcom/ diff --git a/drivers/thermal/remoteproc_cooling.c b/drivers/thermal/remoteproc_cooling.c new file mode 100644 index 0000000000000..a1f948cbde0fe --- /dev/null +++ b/drivers/thermal/remoteproc_cooling.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Remote Processor Cooling Device + * + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define REMOTEPROC_PREFIX "rproc_" + +struct remoteproc_cooling_ops { + int (*get_max_level)(void *devdata, unsigned long *level); + int (*get_cur_level)(void *devdata, unsigned long *level); + int (*set_cur_level)(void *devdata, unsigned long level); +}; + +/** + * struct remoteproc_cdev - Remote processor cooling device + * @cdev: Thermal cooling device handle + * @ops: Vendor-specific operation callbacks + * @devdata: Private data for vendor implementation + * @np: Device tree node associated with this cooling device + * @lock: Mutex to protect cooling device operations + */ +struct remoteproc_cdev { + struct thermal_cooling_device *cdev; + const struct remoteproc_cooling_ops *ops; + void *devdata; + struct device_node *np; + struct mutex lock; +}; + + +/* Thermal cooling device callbacks */ + +static int remoteproc_get_max_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + struct remoteproc_cdev *rproc_cdev = cdev->devdata; + int ret; + + if (!rproc_cdev || !rproc_cdev->ops) + return -EINVAL; + + mutex_lock(&rproc_cdev->lock); + ret = rproc_cdev->ops->get_max_level(rproc_cdev->devdata, state); + mutex_unlock(&rproc_cdev->lock); + + return ret; +} + +static int remoteproc_get_cur_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + struct remoteproc_cdev *rproc_cdev = cdev->devdata; + int ret; + + if (!rproc_cdev || !rproc_cdev->ops) + return -EINVAL; + + mutex_lock(&rproc_cdev->lock); + ret = rproc_cdev->ops->get_cur_level(rproc_cdev->devdata, state); + mutex_unlock(&rproc_cdev->lock); + + return ret; +} + +static int remoteproc_set_cur_state(struct thermal_cooling_device *cdev, + unsigned long state) +{ + struct remoteproc_cdev *rproc_cdev = cdev->devdata; + int ret; + + if (!rproc_cdev || !rproc_cdev->ops) + return -EINVAL; + + mutex_lock(&rproc_cdev->lock); + ret = rproc_cdev->ops->set_cur_level(rproc_cdev->devdata, state); + mutex_unlock(&rproc_cdev->lock); + + return ret; +} + +static const struct thermal_cooling_device_ops remoteproc_cooling_ops = { + .get_max_state = remoteproc_get_max_state, + .get_cur_state = remoteproc_get_cur_state, + .set_cur_state = remoteproc_set_cur_state, +}; + +struct remoteproc_cdev * +remoteproc_cooling_register(struct device_node *np, + const char *name, const struct remoteproc_cooling_ops *ops, + void *devdata) +{ + struct remoteproc_cdev *rproc_cdev; + struct thermal_cooling_device *cdev; + int ret; + + if (!name || !ops) { + return ERR_PTR(-EINVAL); + } + + rproc_cdev = kzalloc(sizeof(*rproc_cdev), GFP_KERNEL); + if (!rproc_cdev) + return ERR_PTR(-ENOMEM); + + rproc_cdev->ops = ops; + rproc_cdev->devdata = devdata; + rproc_cdev->np = np; + mutex_init(&rproc_cdev->lock); + + char *rproc_name __free(kfree) = + kasprintf(GFP_KERNEL, REMOTEPROC_PREFIX "%s", name); + /* Register with thermal framework */ + if (np) { + cdev = thermal_of_cooling_device_register(np, rproc_name, rproc_cdev, + &remoteproc_cooling_ops); + } + + if (IS_ERR(cdev)) { + ret = PTR_ERR(cdev); + goto free_rproc_cdev; + } + + rproc_cdev->cdev = cdev; + + return rproc_cdev; + +free_rproc_cdev: + kfree(rproc_cdev); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(remoteproc_cooling_register); + +void remoteproc_cooling_unregister(struct remoteproc_cdev *rproc_cdev) +{ + if (!rproc_cdev) + return; + + thermal_cooling_device_unregister(rproc_cdev->cdev); + mutex_destroy(&rproc_cdev->lock); + kfree(rproc_cdev); +} +EXPORT_SYMBOL_GPL(remoteproc_cooling_unregister); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Remote Processor Cooling Device"); diff --git a/include/linux/remoteproc_cooling.h b/include/linux/remoteproc_cooling.h new file mode 100644 index 0000000000000..ef94019d220de --- /dev/null +++ b/include/linux/remoteproc_cooling.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Remote Processor Cooling Device + * + * Copyright (c) 2025, Qualcomm Innovation Center + */ + +#ifndef __REMOTEPROC_COOLING_H__ +#define __REMOTEPROC_COOLING_H__ + +#include + +struct device; +struct device_node; + +struct remoteproc_cooling_ops { + int (*get_max_level)(void *devdata, unsigned long *level); + int (*get_cur_level)(void *devdata, unsigned long *level); + int (*set_cur_level)(void *devdata, unsigned long level); +}; + +struct remoteproc_cdev; + +#ifdef CONFIG_REMOTEPROC_THERMAL + +struct remoteproc_cdev * +remoteproc_cooling_register(struct device_node *np, + const char *name, + const struct remoteproc_cooling_ops *ops, + void *devdata); + +void remoteproc_cooling_unregister(struct remoteproc_cdev *rproc_cdev); + +#else /* !CONFIG_REMOTEPROC_THERMAL */ + +static inline struct remoteproc_cdev * +remoteproc_cooling_register(struct device_node *np, + const char *name, + const struct remoteproc_cooling_ops *ops, + void *devdata) +{ + return ERR_PTR(-EINVAL); +} + +static inline void +remoteproc_cooling_unregister(struct remoteproc_cdev *rproc_cdev) +{ +} + +#endif /* CONFIG_REMOTEPROC_THERMAL */ + +#endif /* __REMOTEPROC_COOLING_H__ */ From 32731e67bf59a7dd01f7051e3676980334bab087 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 23 Dec 2025 18:02:22 +0530 Subject: [PATCH 0536/1330] FROMLIST: dt-bindings: thermal: Add qcom,qmi-cooling yaml bindings The cooling subnode of a remoteproc represents a client of the Thermal Mitigation Device QMI service running on it. Each subnode of the cooling node represents a single control exposed by the service. Add maintainer name also and update this binding for cdsp substem. Co-developed-by: Casey Connolly Signed-off-by: Gaurav Kohli Signed-off-by: Casey Connolly Link: https://lore.kernel.org/r/20251223123227.1317244-4-gaurav.kohli@oss.qualcomm.com --- .../bindings/remoteproc/qcom,pas-common.yaml | 6 ++ .../bindings/thermal/qcom,qmi-cooling.yaml | 99 +++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom,qmi-cooling.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index 68c17bf18987c..6a736161d5aed 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -80,6 +80,12 @@ properties: and devices related to the ADSP. unevaluatedProperties: false + cooling: + $ref: /schemas/thermal/qcom,qmi-cooling.yaml# + description: + Cooling subnode which represents the cooling devices exposed by the Modem. + unevaluatedProperties: false + required: - clocks - clock-names diff --git a/Documentation/devicetree/bindings/thermal/qcom,qmi-cooling.yaml b/Documentation/devicetree/bindings/thermal/qcom,qmi-cooling.yaml new file mode 100644 index 0000000000000..90b46712d2412 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom,qmi-cooling.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 (c), Linaro Limited + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom,qmi-cooling.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMI based thermal mitigation (TMD) cooling devices. + +maintainers: + - Caleb Connolly + - Gaurav Kohli + +description: + Qualcomm QMI-based TMD cooling devices are used to mitigate thermal conditions + across multiple remote subsystems. These devices operate based on junction temperature + sensors (TSENS) associated with thermal zones for each subsystem. + + Each subnode corresponds to a control interface for a single instance of the TMD + service running on a remote subsystem. + +definitions: + tmd: + type: object + description: | + A single Thermal Mitigation Device exposed by a remote subsystem. + properties: + label: + maxItems: 1 + "#cooling-cells": + $ref: /schemas/thermal/thermal-cooling-devices.yaml#/properties/#cooling-cells + phandle: true + + required: + - label + - "#cooling-cells" + + additionalProperties: false + +properties: + compatible: + enum: + - qcom,qmi-cooling-modem + - qcom,qmi-cooling-cdsp + + vdd: + $ref: "#/definitions/tmd" + description: + Modem processor temperature TMD + properties: + label: + const: modem + +required: + - compatible + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,qmi-cooling-cdsp + then: + properties: + cdsp_sw: + $ref: "#/definitions/tmd" + description: + CDSP software TMD + properties: + label: + const: cdsp_sw + +unevaluatedProperties: false + +examples: + - | + remoteproc-cdsp { + cooling { + compatible = "qcom,qmi-cooling-cdsp"; + + cdsp_sw0: cdsp_sw { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; + }; + + remoteproc-cdsp1 { + cooling { + compatible = "qcom,qmi-cooling-cdsp1"; + + cdsp_sw1: cdsp_sw { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; + }; +... From 3cbe64ce997d568d699e9e1e4aa481839e85ed2a Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Tue, 23 Dec 2025 18:02:23 +0530 Subject: [PATCH 0537/1330] FROMLIST: thermal: qcom: add qmi-cooling driver The Thermal Mitigation Device (TMD) service exposes various platform specific thermal mitigations available on remote subsystems (ie the modem and cdsp). The service is exposed via the QMI messaging interface, usually over the QRTR transport. Qualcomm QMI-based TMD cooling devices are used to mitigate thermal conditions across multiple remote subsystems. These devices operate based on junction temperature sensors (TSENS) associated with thermal zones for each subsystem. Co-developed-by: Gaurav Kohli Signed-off-by: Casey Connolly Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20251223123227.1317244-5-gaurav.kohli@oss.qualcomm.com --- drivers/soc/qcom/Kconfig | 13 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qmi-cooling.c | 498 +++++++++++++++++++++++++++++++++ drivers/soc/qcom/qmi-cooling.h | 428 ++++++++++++++++++++++++++++ 4 files changed, 940 insertions(+) create mode 100644 drivers/soc/qcom/qmi-cooling.c create mode 100644 drivers/soc/qcom/qmi-cooling.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 2caadbbcf8307..905a24b42fe69 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -124,6 +124,19 @@ config QCOM_PMIC_GLINK Say yes here to support USB-C and battery status on modern Qualcomm platforms. +config QCOM_QMI_COOLING + tristate "Qualcomm QMI cooling drivers" + depends on QCOM_RPROC_COMMON + depends on ARCH_QCOM || COMPILE_TEST + select QCOM_QMI_HELPERS + help + This enables the remote subsystem cooling devices. These cooling + devices will be used by Qualcomm chipset to place various remote + subsystem mitigations like remote processor passive mitigation, + remote subsystem voltage restriction at low temperatures etc. + The QMI cooling device will interface with remote subsystem + using Qualcomm remoteproc interface. + config QCOM_QMI_HELPERS tristate depends on NET diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 798643be3590c..a3fa2b8eebfc7 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink_altmode.o obj-$(CONFIG_QCOM_PMIC_PDCHARGER_ULOG) += pmic_pdcharger_ulog.o CFLAGS_pmic_pdcharger_ulog.o := -I$(src) +obj-$(CONFIG_QCOM_QMI_COOLING) += qmi-cooling.o obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o qmi_helpers-y += qmi_encdec.o qmi_interface.o obj-$(CONFIG_QCOM_RAMP_CTRL) += ramp_controller.o diff --git a/drivers/soc/qcom/qmi-cooling.c b/drivers/soc/qcom/qmi-cooling.c new file mode 100644 index 0000000000000..1a6afcb96bf69 --- /dev/null +++ b/drivers/soc/qcom/qmi-cooling.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017, The Linux Foundation + * Copyright (c) 2025, Linaro Limited + * + * QMI Thermal Mitigation Device (TMD) client driver. + * This driver provides an in-kernel client to handle hot and cold thermal + * mitigations for remote subsystems (modem and DSPs) running the TMD service. + * It doesn't implement any handling of reports from remote subsystems. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qmi-cooling.h" + +#define MODEM0_INSTANCE_ID 0x0 +#define ADSP_INSTANCE_ID 0x1 +#define CDSP_INSTANCE_ID 0x43 +#define SLPI_INSTANCE_ID 0x53 + +#define QMI_TMD_RESP_TIMEOUT msecs_to_jiffies(100) + +/** + * struct qmi_tmd_client - TMD client state + * @dev: Device associated with this client + * @name: Friendly name for the remote TMD service + * @handle: QMI connection handle + * @mutex: Lock to synchronise QMI communication + * @id: The QMI TMD service instance ID + * @cdev_list: The list of cooling devices (controls) enabled for this instance + * @svc_arrive_work: Work item for initialising the client when the TMD service + * starts. + * @connection_active: Whether or not we're connected to the QMI TMD service + */ +struct qmi_tmd_client { + struct device *dev; + const char *name; + struct qmi_handle handle; + struct mutex mutex; + u32 id; + struct list_head cdev_list; + struct work_struct svc_arrive_work; + bool connection_active; +}; + +/** + * struct qmi_tmd - A TMD cooling device + * @np: OF node associated with this control + * @type: The control type (exposed via sysfs) + * @qmi_name: The common name of this control shared by the remote subsystem + * @rproc_cdev: Remote processor cooling device handle + * @cur_state: The current cooling/warming/mitigation state + * @max_state: The maximum state + * @client: The TMD client instance this control is associated with + */ +struct qmi_tmd { + struct device_node *np; + const char *type; + char qmi_name[QMI_TMD_MITIGATION_DEV_ID_LENGTH_MAX_V01 + 1]; + struct list_head node; + struct remoteproc_cdev *rproc_cdev; + unsigned int cur_state; + unsigned int max_state; + struct qmi_tmd_client *client; +}; + +/** + * struct qmi_instance_id - QMI instance match data + * @id: The QMI instance ID + * @name: Friendly name for this instance + */ +struct qmi_instance_data { + u32 id; + const char *name; +}; + +/* Notify the remote subsystem of the requested cooling state */ +static int qmi_tmd_send_state_request(struct qmi_tmd *tmd) +{ + struct tmd_set_mitigation_level_resp_msg_v01 tmd_resp = { 0 }; + struct tmd_set_mitigation_level_req_msg_v01 req = { 0 }; + struct qmi_tmd_client *client; + struct qmi_txn txn; + int ret = 0; + + client = tmd->client; + + guard(mutex)(&client->mutex); + + /* + * This function is called by qmi_set_cur_state() which does not know if + * the QMI service is actually online. If it isn't then we noop here. + * The state is cached in tmd->cur_state and will be broadcast via + * qmi_tmd_init_control() when the service comes up. + */ + if (!client->connection_active) + return 0; + + strscpy(req.mitigation_dev_id.mitigation_dev_id, tmd->qmi_name, + QMI_TMD_MITIGATION_DEV_ID_LENGTH_MAX_V01 + 1); + req.mitigation_level = tmd->cur_state; + + ret = qmi_txn_init(&client->handle, &txn, + tmd_set_mitigation_level_resp_msg_v01_ei, &tmd_resp); + if (ret < 0) { + dev_err(client->dev, "qmi set state %d txn init failed for %s ret %d\n", + tmd->cur_state, tmd->type, ret); + return ret; + } + + ret = qmi_send_request(&client->handle, NULL, &txn, + QMI_TMD_SET_MITIGATION_LEVEL_REQ_V01, + TMD_SET_MITIGATION_LEVEL_REQ_MSG_V01_MAX_MSG_LEN, + tmd_set_mitigation_level_req_msg_v01_ei, &req); + if (ret < 0) { + dev_err(client->dev, "qmi set state %d txn send failed for %s ret %d\n", + tmd->cur_state, tmd->type, ret); + qmi_txn_cancel(&txn); + return ret; + } + + ret = qmi_txn_wait(&txn, QMI_TMD_RESP_TIMEOUT); + if (ret < 0) { + dev_err(client->dev, "qmi set state %d txn wait failed for %s ret %d\n", + tmd->cur_state, tmd->type, ret); + return ret; + } + + if (tmd_resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ret = -tmd_resp.resp.result; + dev_err(client->dev, "qmi set state %d NOT success for %s ret %d\n", + tmd->cur_state, tmd->type, ret); + return ret; + } + + dev_dbg(client->dev, "Requested state %d/%d for %s\n", tmd->cur_state, + tmd->max_state, tmd->type); + + return 0; +} + +static int qmi_get_max_level(void *devdata, unsigned long *level) +{ + struct qmi_tmd *tmd = devdata; + + if (!tmd) + return -EINVAL; + + *level = tmd->max_state; + + return 0; +} + +static int qmi_get_cur_level(void *devdata, unsigned long *level) +{ + struct qmi_tmd *tmd = devdata; + + if (!tmd) + return -EINVAL; + + *level = tmd->cur_state; + + return 0; +} + +static int qmi_set_cur_level(void *devdata, unsigned long level) +{ + struct qmi_tmd *tmd = devdata; + + if (!tmd) + return -EINVAL; + + if (level > tmd->max_state) + return -EINVAL; + + if (tmd->cur_state == level) + return 0; + + tmd->cur_state = level; + + return qmi_tmd_send_state_request(tmd); +} + +static const struct remoteproc_cooling_ops qmi_rproc_ops = { + .get_max_level = qmi_get_max_level, + .get_cur_level = qmi_get_cur_level, + .set_cur_level = qmi_set_cur_level, +}; + +static int qmi_register_cooling_device(struct qmi_tmd *tmd) +{ + struct remoteproc_cdev *rproc_cdev; + + rproc_cdev = remoteproc_cooling_register(tmd->np, + tmd->type, + &qmi_rproc_ops, + tmd); + + if (IS_ERR(rproc_cdev)) + return dev_err_probe(tmd->client->dev, PTR_ERR(rproc_cdev), + "Failed to register cooling device %s\n", + tmd->qmi_name); + + tmd->rproc_cdev = rproc_cdev; + return 0; +} + +/* + * Init a single TMD control by registering a cooling device for it, or + * synchronising state with the remote subsystem if recovering from a service + * restart. This is called when the TMD service starts up. + */ +static int qmi_tmd_init_control(struct qmi_tmd_client *client, const char *label, + u8 max_state) +{ + struct qmi_tmd *tmd = NULL; + + list_for_each_entry(tmd, &client->cdev_list, node) + if (!strncasecmp(tmd->qmi_name, label, + QMI_TMD_MITIGATION_DEV_ID_LENGTH_MAX_V01 + 1)) + goto found; + + dev_dbg(client->dev, + "TMD '%s' available in firmware but not specified in DT\n", + label); + return 0; + +found: + tmd->max_state = max_state; + /* + * If the cooling device already exists then the QMI service went away and + * came back. So just make sure the current cooling device state is + * reflected on the remote side and then return. + */ + if (tmd->rproc_cdev) + return qmi_tmd_send_state_request(tmd); + + return qmi_register_cooling_device(tmd); +} + +/* + * When the QMI service starts up on a remote subsystem this function will fetch + * the list of TMDs on the subsystem, match it to the TMDs specified in devicetree + * and call qmi_tmd_init_control() for each + */ +static void qmi_tmd_svc_arrive(struct work_struct *work) +{ + struct qmi_tmd_client *client = + container_of(work, struct qmi_tmd_client, svc_arrive_work); + + struct tmd_get_mitigation_device_list_req_msg_v01 req = { 0 }; + struct tmd_get_mitigation_device_list_resp_msg_v01 *resp __free(kfree); + int ret = 0, i; + struct qmi_txn txn; + + /* resp struct is 1.1kB, allocate it on the heap. */ + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) + return; + + /* Get a list of TMDs supported by the remoteproc */ + scoped_guard(mutex, &client->mutex) { + ret = qmi_txn_init(&client->handle, &txn, + tmd_get_mitigation_device_list_resp_msg_v01_ei, resp); + if (ret < 0) { + dev_err(client->dev, + "Transaction init error for instance_id: %#x ret %d\n", + client->id, ret); + return; + } + + ret = qmi_send_request(&client->handle, NULL, &txn, + QMI_TMD_GET_MITIGATION_DEVICE_LIST_REQ_V01, + TMD_GET_MITIGATION_DEVICE_LIST_REQ_MSG_V01_MAX_MSG_LEN, + tmd_get_mitigation_device_list_req_msg_v01_ei, &req); + if (ret < 0) { + qmi_txn_cancel(&txn); + return; + } + + ret = qmi_txn_wait(&txn, QMI_TMD_RESP_TIMEOUT); + if (ret < 0) { + dev_err(client->dev, "Transaction wait error for client %#x ret:%d\n", + client->id, ret); + return; + } + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + ret = resp->resp.result; + dev_err(client->dev, "Failed to get device list for client %#x ret:%d\n", + client->id, ret); + return; + } + + client->connection_active = true; + } + + for (i = 0; i < resp->mitigation_device_list_len; i++) { + struct tmd_mitigation_dev_list_type_v01 *device = + &resp->mitigation_device_list[i]; + + ret = qmi_tmd_init_control(client, + device->mitigation_dev_id.mitigation_dev_id, + device->max_mitigation_level); + if (ret) + break; + } +} + +static void thermal_qmi_net_reset(struct qmi_handle *qmi) +{ + struct qmi_tmd_client *client = container_of(qmi, struct qmi_tmd_client, handle); + struct qmi_tmd *tmd = NULL; + + list_for_each_entry(tmd, &client->cdev_list, node) { + qmi_tmd_send_state_request(tmd); + } +} + +static void thermal_qmi_del_server(struct qmi_handle *qmi, struct qmi_service *service) +{ + struct qmi_tmd_client *client = container_of(qmi, struct qmi_tmd_client, handle); + + scoped_guard(mutex, &client->mutex) + client->connection_active = false; +} + +static int thermal_qmi_new_server(struct qmi_handle *qmi, struct qmi_service *service) +{ + struct qmi_tmd_client *client = container_of(qmi, struct qmi_tmd_client, handle); + struct sockaddr_qrtr sq = { AF_QIPCRTR, service->node, service->port }; + + scoped_guard(mutex, &client->mutex) + kernel_connect(qmi->sock, (struct sockaddr_unsized *)&sq, sizeof(sq), 0); + + queue_work(system_highpri_wq, &client->svc_arrive_work); + + return 0; +} + +static struct qmi_ops thermal_qmi_event_ops = { + .new_server = thermal_qmi_new_server, + .del_server = thermal_qmi_del_server, + .net_reset = thermal_qmi_net_reset, +}; + +static void qmi_tmd_cleanup(struct qmi_tmd_client *client) +{ + struct qmi_tmd *tmd, *c_next; + + guard(mutex)(&client->mutex); + + client->connection_active = false; + + qmi_handle_release(&client->handle); + cancel_work(&client->svc_arrive_work); + list_for_each_entry_safe(tmd, c_next, &client->cdev_list, node) { + if (tmd->rproc_cdev) + remoteproc_cooling_unregister(tmd->rproc_cdev); + + list_del(&tmd->node); + } +} + +/* Parse the controls and allocate a qmi_tmd for each of them */ +static int qmi_tmd_alloc_cdevs(struct qmi_tmd_client *client) +{ + struct device *dev = client->dev; + struct qmi_tmd *tmd; + struct device_node *subnode, *node = dev->of_node; + int ret; + + for_each_available_child_of_node(node, subnode) { + const char *name; + + tmd = devm_kzalloc(dev, sizeof(*tmd), GFP_KERNEL); + if (!tmd) + return dev_err_probe(client->dev, -ENOMEM, + "Couldn't allocate tmd\n"); + + tmd->type = devm_kasprintf(client->dev, GFP_KERNEL, "%s:%s", + client->name, subnode->name); + if (!tmd->type) + return dev_err_probe(dev, -ENOMEM, + "Couldn't allocate cooling device name\n"); + + if (of_property_read_string(subnode, "label", &name)) { + return dev_err_probe(client->dev, -EINVAL, + "Failed to parse dev name for %s\n", + subnode->name); + } + + ret = strscpy(tmd->qmi_name, name, + QMI_TMD_MITIGATION_DEV_ID_LENGTH_MAX_V01 + 1); + if (ret == -E2BIG) { + return dev_err_probe(dev, -EINVAL, "TMD label %s is too long\n", + name); + } + + tmd->client = client; + tmd->np = subnode; + tmd->cur_state = 0; + list_add(&tmd->node, &client->cdev_list); + } + + if (list_empty(&client->cdev_list)) + return dev_err_probe(client->dev, -EINVAL, + "No cooling devices specified for client %s (%#x)\n", + client->name, client->id); + + return 0; +} + +static int qmi_tmd_client_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct qmi_tmd_client *client; + const struct qmi_instance_data *match; + int ret; + client = devm_kzalloc(dev, sizeof(*client), GFP_KERNEL); + if (!client) + return -ENOMEM; + + client->dev = dev; + + match = of_device_get_match_data(dev); + if (!match) + return dev_err_probe(dev, -EINVAL, "No match data\n"); + + client->id = match->id; + client->name = match->name; + + mutex_init(&client->mutex); + INIT_LIST_HEAD(&client->cdev_list); + INIT_WORK(&client->svc_arrive_work, qmi_tmd_svc_arrive); + + ret = qmi_tmd_alloc_cdevs(client); + if (ret) + return ret; + + platform_set_drvdata(pdev, client); + + ret = qmi_handle_init(&client->handle, + TMD_GET_MITIGATION_DEVICE_LIST_RESP_MSG_V01_MAX_MSG_LEN, + &thermal_qmi_event_ops, NULL); + if (ret < 0) + return dev_err_probe(client->dev, ret, "QMI handle init failed for client %#x\n", + client->id); + + ret = qmi_add_lookup(&client->handle, TMD_SERVICE_ID_V01, TMD_SERVICE_VERS_V01, + client->id); + if (ret < 0) { + qmi_handle_release(&client->handle); + return dev_err_probe(client->dev, ret, "QMI register failed for client 0x%x\n", + client->id); + } + + return 0; +} + +static void qmi_tmd_client_remove(struct platform_device *pdev) +{ + struct qmi_tmd_client *client = platform_get_drvdata(pdev); + + qmi_tmd_cleanup(client); +} + +static const struct of_device_id qmi_tmd_device_table[] = { + { + .compatible = "qcom,qmi-cooling-cdsp", + .data = &((struct qmi_instance_data) { CDSP_INSTANCE_ID, "cdsp" }), + }, + {} +}; +MODULE_DEVICE_TABLE(of, qmi_tmd_device_table); + +static struct platform_driver qmi_tmd_device_driver = { + .probe = qmi_tmd_client_probe, + .remove = qmi_tmd_client_remove, + .driver = { + .name = "qcom-qmi-cooling", + .of_match_table = qmi_tmd_device_table, + }, +}; + +module_platform_driver(qmi_tmd_device_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm QMI Thermal Mitigation Device driver"); diff --git a/drivers/soc/qcom/qmi-cooling.h b/drivers/soc/qcom/qmi-cooling.h new file mode 100644 index 0000000000000..f46b827b4ce64 --- /dev/null +++ b/drivers/soc/qcom/qmi-cooling.h @@ -0,0 +1,428 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017, The Linux Foundation + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef __QCOM_COOLING_H__ +#define __QCOM_COOLING_H__ + +#include + +#define TMD_SERVICE_ID_V01 0x18 +#define TMD_SERVICE_VERS_V01 0x01 + +#define QMI_TMD_GET_MITIGATION_DEVICE_LIST_RESP_V01 0x0020 +#define QMI_TMD_GET_MITIGATION_LEVEL_REQ_V01 0x0022 +#define QMI_TMD_GET_SUPPORTED_MSGS_REQ_V01 0x001E +#define QMI_TMD_SET_MITIGATION_LEVEL_REQ_V01 0x0021 +#define QMI_TMD_REGISTER_NOTIFICATION_MITIGATION_LEVEL_RESP_V01 0x0023 +#define QMI_TMD_GET_SUPPORTED_MSGS_RESP_V01 0x001E +#define QMI_TMD_SET_MITIGATION_LEVEL_RESP_V01 0x0021 +#define QMI_TMD_DEREGISTER_NOTIFICATION_MITIGATION_LEVEL_RESP_V01 0x0024 +#define QMI_TMD_MITIGATION_LEVEL_REPORT_IND_V01 0x0025 +#define QMI_TMD_GET_MITIGATION_LEVEL_RESP_V01 0x0022 +#define QMI_TMD_GET_SUPPORTED_FIELDS_REQ_V01 0x001F +#define QMI_TMD_GET_MITIGATION_DEVICE_LIST_REQ_V01 0x0020 +#define QMI_TMD_REGISTER_NOTIFICATION_MITIGATION_LEVEL_REQ_V01 0x0023 +#define QMI_TMD_DEREGISTER_NOTIFICATION_MITIGATION_LEVEL_REQ_V01 0x0024 +#define QMI_TMD_GET_SUPPORTED_FIELDS_RESP_V01 0x001F + +#define QMI_TMD_MITIGATION_DEV_ID_LENGTH_MAX_V01 32 +#define QMI_TMD_MITIGATION_DEV_LIST_MAX_V01 32 + +struct tmd_mitigation_dev_id_type_v01 { + char mitigation_dev_id[QMI_TMD_MITIGATION_DEV_ID_LENGTH_MAX_V01 + 1]; +}; + +static const struct qmi_elem_info tmd_mitigation_dev_id_type_v01_ei[] = { + { + .data_type = QMI_STRING, + .elem_len = QMI_TMD_MITIGATION_DEV_ID_LENGTH_MAX_V01 + 1, + .elem_size = sizeof(char), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct tmd_mitigation_dev_id_type_v01, + mitigation_dev_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct tmd_mitigation_dev_list_type_v01 { + struct tmd_mitigation_dev_id_type_v01 mitigation_dev_id; + uint8_t max_mitigation_level; +}; + +static const struct qmi_elem_info tmd_mitigation_dev_list_type_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct tmd_mitigation_dev_id_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct tmd_mitigation_dev_list_type_v01, + mitigation_dev_id), + .ei_array = tmd_mitigation_dev_id_type_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct tmd_mitigation_dev_list_type_v01, + max_mitigation_level), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct tmd_get_mitigation_device_list_req_msg_v01 { + char placeholder; +}; + +#define TMD_GET_MITIGATION_DEVICE_LIST_REQ_MSG_V01_MAX_MSG_LEN 0 +const struct qmi_elem_info tmd_get_mitigation_device_list_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct tmd_get_mitigation_device_list_resp_msg_v01 { + struct qmi_response_type_v01 resp; + uint8_t mitigation_device_list_valid; + uint32_t mitigation_device_list_len; + struct tmd_mitigation_dev_list_type_v01 + mitigation_device_list[QMI_TMD_MITIGATION_DEV_LIST_MAX_V01]; +}; + +#define TMD_GET_MITIGATION_DEVICE_LIST_RESP_MSG_V01_MAX_MSG_LEN 1099 +static const struct qmi_elem_info tmd_get_mitigation_device_list_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct tmd_get_mitigation_device_list_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct tmd_get_mitigation_device_list_resp_msg_v01, + mitigation_device_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct tmd_get_mitigation_device_list_resp_msg_v01, + mitigation_device_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_TMD_MITIGATION_DEV_LIST_MAX_V01, + .elem_size = sizeof(struct tmd_mitigation_dev_list_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct tmd_get_mitigation_device_list_resp_msg_v01, + mitigation_device_list), + .ei_array = tmd_mitigation_dev_list_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct tmd_set_mitigation_level_req_msg_v01 { + struct tmd_mitigation_dev_id_type_v01 mitigation_dev_id; + uint8_t mitigation_level; +}; + +#define TMD_SET_MITIGATION_LEVEL_REQ_MSG_V01_MAX_MSG_LEN 40 +static const struct qmi_elem_info tmd_set_mitigation_level_req_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct tmd_mitigation_dev_id_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct tmd_set_mitigation_level_req_msg_v01, + mitigation_dev_id), + .ei_array = tmd_mitigation_dev_id_type_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct tmd_set_mitigation_level_req_msg_v01, + mitigation_level), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct tmd_set_mitigation_level_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define TMD_SET_MITIGATION_LEVEL_RESP_MSG_V01_MAX_MSG_LEN 7 +static const struct qmi_elem_info tmd_set_mitigation_level_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct tmd_set_mitigation_level_resp_msg_v01, resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct tmd_get_mitigation_level_req_msg_v01 { + struct tmd_mitigation_dev_id_type_v01 mitigation_device; +}; +#define TMD_GET_MITIGATION_LEVEL_REQ_MSG_V01_MAX_MSG_LEN 36 + +static const struct qmi_elem_info tmd_get_mitigation_level_req_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct tmd_mitigation_dev_id_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct tmd_get_mitigation_level_req_msg_v01, + mitigation_device), + .ei_array = tmd_mitigation_dev_id_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct tmd_get_mitigation_level_resp_msg_v01 { + struct qmi_response_type_v01 resp; + uint8_t current_mitigation_level_valid; + uint8_t current_mitigation_level; + uint8_t requested_mitigation_level_valid; + uint8_t requested_mitigation_level; +}; + +#define TMD_GET_MITIGATION_LEVEL_RESP_MSG_V01_MAX_MSG_LEN 15 +static const struct qmi_elem_info tmd_get_mitigation_level_resp_msg_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct tmd_get_mitigation_level_resp_msg_v01, resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct tmd_get_mitigation_level_resp_msg_v01, + current_mitigation_level_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct tmd_get_mitigation_level_resp_msg_v01, + current_mitigation_level), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct tmd_get_mitigation_level_resp_msg_v01, + requested_mitigation_level_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct tmd_get_mitigation_level_resp_msg_v01, + requested_mitigation_level), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct tmd_register_notification_mitigation_level_req_msg_v01 { + struct tmd_mitigation_dev_id_type_v01 mitigation_device; +}; + +#define TMD_REGISTER_NOTIFICATION_MITIGATION_LEVEL_REQ_MSG_V01_MAX_MSG_LEN 36 +static const struct qmi_elem_info + tmd_register_notification_mitigation_level_req_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct tmd_mitigation_dev_id_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct tmd_register_notification_mitigation_level_req_msg_v01, + mitigation_device), + .ei_array = tmd_mitigation_dev_id_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, + }; + +struct tmd_register_notification_mitigation_level_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define TMD_REGISTER_NOTIFICATION_MITIGATION_LEVEL_RESP_MSG_V01_MAX_MSG_LEN 7 +static const struct qmi_elem_info + tmd_register_notification_mitigation_level_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct tmd_register_notification_mitigation_level_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, + }; + +struct tmd_deregister_notification_mitigation_level_req_msg_v01 { + struct tmd_mitigation_dev_id_type_v01 mitigation_device; +}; + +#define TMD_DEREGISTER_NOTIFICATION_MITIGATION_LEVEL_REQ_MSG_V01_MAX_MSG_LEN 36 +static const struct qmi_elem_info + tmd_deregister_notification_mitigation_level_req_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct tmd_mitigation_dev_id_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct tmd_deregister_notification_mitigation_level_req_msg_v01, + mitigation_device), + .ei_array = tmd_mitigation_dev_id_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, + }; + +struct tmd_deregister_notification_mitigation_level_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define TMD_DEREGISTER_NOTIFICATION_MITIGATION_LEVEL_RESP_MSG_V01_MAX_MSG_LEN 7 +static const struct qmi_elem_info + tmd_deregister_notification_mitigation_level_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct tmd_deregister_notification_mitigation_level_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, + }; + +struct tmd_mitigation_level_report_ind_msg_v01 { + struct tmd_mitigation_dev_id_type_v01 mitigation_device; + uint8_t current_mitigation_level; +}; + +#define TMD_MITIGATION_LEVEL_REPORT_IND_MSG_V01_MAX_MSG_LEN 40 +static const struct qmi_elem_info tmd_mitigation_level_report_ind_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct tmd_mitigation_dev_id_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct tmd_mitigation_level_report_ind_msg_v01, + mitigation_device), + .ei_array = tmd_mitigation_dev_id_type_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct tmd_mitigation_level_report_ind_msg_v01, + current_mitigation_level), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +#endif /* __QMI_COOLING_INTERNAL_H__ */ From b5669df500874ef0927ced21c6c158f589ff2b2d Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 13 Mar 2026 16:04:17 +0530 Subject: [PATCH 0538/1330] FROMLIST: dt-bindings: thermal: qcom-tsens: Document the SM8750 Temperature Sensor Document the Temperature Sensor (TSENS) on the SM8750 SoC. Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Gaurav Kohli Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260313-sm8750_tsens-v1-1-250fcc3794a2@oss.qualcomm.com --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 3c5256b0cd9f2..57f1cbb4c188e 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -81,6 +81,7 @@ properties: - qcom,sm8450-tsens - qcom,sm8550-tsens - qcom,sm8650-tsens + - qcom,sm8750-tsens - qcom,x1e80100-tsens - const: qcom,tsens-v2 From ed4fe7a80ab7db48bc007abe4f431c34532e0003 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 6 Feb 2026 02:44:05 +0530 Subject: [PATCH 0539/1330] FROMLIST: dt-bindings: hwmon: Add qcom,bcl-hwmon yaml bindings Add devicetree binding documentation for Qualcomm PMIC Battery Current Limiting (BCL) hardware monitor. The BCL hardware provides monitoring and alarm functionality for battery overcurrent and battery/system under voltage conditions. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20260206-qcom-bcl-hwmon-v1-1-7b426f0b77a1@oss.qualcomm.com --- .../bindings/hwmon/qcom,bcl-hwmon.yaml | 128 ++++++++++++++++++ .../bindings/mfd/qcom,spmi-pmic.yaml | 4 + 2 files changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml diff --git a/Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml new file mode 100644 index 0000000000000..6ffadc4d28bcf --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/qcom,bcl-hwmon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMIC Battery Current Limiting (BCL) Hardware Monitor + +maintainers: + - Manaf Meethalavalappu Pallikunhi + +description: | + SPMI PMIC Battery Current Limiting (BCL) hardware provides monitoring and + alarm functionality for battery overcurrent and battery or system under + voltage conditions. It monitors battery voltage and current, and + can trigger interrupts when configurable thresholds are exceeded. + +properties: + compatible: + oneOf: + - description: v1 based BCL + items: + - enum: + - qcom,pm7250b-bcl + - qcom,pm8250b-bcl + - const: qcom,bcl-v1 + + - description: v2 based BCL + items: + - enum: + - qcom,pm8350b-bcl + - qcom,pm8350c-bcl + - const: qcom,bcl-v2 + + - description: v3 bmx based BCL + items: + - enum: + - qcom,pm8550b-bcl + - qcom,pm7550ba-bcl + - const: qcom,bcl-v3-bmx + + - description: v3 core based BCL + items: + - enum: + - qcom,pm8550-bc0l + - qcom,pm7550-bcl + - const: qcom,bcl-v3-core + + - description: v3 wb based BCL + items: + - enum: + - qcom,pmw5100-bcl + - const: qcom,bcl-v3-wb + + - description: v4 bmx based BCL + items: + - enum: + - qcom,pmih010-bcl + - const: qcom,bcl-v4-bmx + + - description: v4 bmx with different scale based BCL + items: + - enum: + - qcom,pmv010-bcl + - const: qcom,bcl-v4-pmv010 + + - description: v4 core based BCL + items: + - enum: + - qcom,pmh010-bcl + - const: qcom,bcl-v4-core + + - description: v4 wb based BCL + items: + - enum: + - qcom,pmw6100-bcl + - const: qcom,bcl-v4-wb + + reg: + maxItems: 1 + description: BCL base address in the SPMI PMIC register map + + interrupts: + minItems: 2 + maxItems: 2 + description: + BCL alarm interrupts for different threshold levels + + interrupt-names: + items: + - const: bcl-max-min + - const: bcl-critical + + overcurrent-thresholds-milliamp: + description: + Current thresholds in milliamperes for the two configurable current + alarm levels (max and critical). These values are used to override + default thresholds if a platform has different battery ocp specification. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1d00 { + compatible = "qcom,pm7250b-bcl", "qcom,bcl-v1"; + reg = <0x1d00>; + interrupts = <0x2 0x1d 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x1d 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "bcl-max-min", + "bcl-critical"; + overcurrent-thresholds-milliamp = <5500 6000>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index bdd304e9eac13..71cbf1c1058ad 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -193,6 +193,10 @@ patternProperties: type: object $ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml# + "^sensor@[0-9a-f]+$": + type: object + $ref: /schemas/hwmon/qcom,bcl-hwmon.yaml# + "^temp-alarm@[0-9a-f]+$": type: object $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml# From 7ee6efc26ac857c8acbba7096410d24600280e1a Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 6 Feb 2026 02:44:06 +0530 Subject: [PATCH 0540/1330] FROMLIST: hwmon: Add Qualcomm PMIC BCL hardware monitor driver Add support for Qualcomm PMIC Battery Current Limiting (BCL) hardware monitor driver. The BCL peripheral is present in Qualcomm PMICs and provides real-time monitoring and protection against battery overcurrent and under voltage conditions. The driver monitors: - Battery voltage with configurable low voltage thresholds - Battery current with configurable high current thresholds - Two limit alarm interrupts (max/min, critical) The driver integrates with the Linux hwmon subsystem and provides standard hwmon attributes for monitoring battery conditions. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20260206-qcom-bcl-hwmon-v1-2-7b426f0b77a1@oss.qualcomm.com --- MAINTAINERS | 9 + drivers/hwmon/Kconfig | 9 + drivers/hwmon/Makefile | 1 + drivers/hwmon/qcom-bcl-hwmon.c | 982 +++++++++++++++++++++++++++++++++ drivers/hwmon/qcom-bcl-hwmon.h | 311 +++++++++++ 5 files changed, 1312 insertions(+) create mode 100644 drivers/hwmon/qcom-bcl-hwmon.c create mode 100644 drivers/hwmon/qcom-bcl-hwmon.h diff --git a/MAINTAINERS b/MAINTAINERS index 844dbf5a7cebb..dcf36cbd90243 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21652,6 +21652,15 @@ S: Maintained F: Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml F: drivers/net/wwan/qcom_bam_dmux.c +QUALCOMM BCL HARDWARE MONITOR DRIVER +M: Manaf Meethalavalappu Pallikunhi +L: linux-hwmon@vger.kernel.org +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml +F: drivers/hwmon/qcom-bcl-hwmon.c +F: drivers/hwmon/qcom-bcl-hwmon.h + QUALCOMM BLUETOOTH DRIVER M: Bartosz Golaszewski L: linux-arm-msm@vger.kernel.org diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 4f203fc74512b..ebb74b9f9e09e 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1916,6 +1916,15 @@ config SENSORS_PWM_FAN This driver can also be built as a module. If so, the module will be called pwm-fan. +config SENSORS_QCOM_BCL + tristate "Qualcomm BCL hardware monitoring" + help + Say yes here to enable support for Qualcomm battery over current + and under voltage alarms monitor. + + This driver can also be built as a module. If so, the module + will be called qcom-bcl-hwmon. + config SENSORS_QNAP_MCU_HWMON tristate "QNAP MCU hardware monitoring" depends on MFD_QNAP_MCU diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index bfbcc5d8b72a0..deb9e52c5a0b4 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -198,6 +198,7 @@ obj-$(CONFIG_SENSORS_POWERZ) += powerz.o obj-$(CONFIG_SENSORS_POWR1220) += powr1220.o obj-$(CONFIG_SENSORS_PT5161L) += pt5161l.o obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o +obj-$(CONFIG_SENSORS_QCOM_BCL) += qcom-bcl-hwmon.o obj-$(CONFIG_SENSORS_QNAP_MCU_HWMON) += qnap-mcu-hwmon.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o obj-$(CONFIG_SENSORS_SBTSI) += sbtsi_temp.o diff --git a/drivers/hwmon/qcom-bcl-hwmon.c b/drivers/hwmon/qcom-bcl-hwmon.c new file mode 100644 index 0000000000000..9894b1d14d124 --- /dev/null +++ b/drivers/hwmon/qcom-bcl-hwmon.c @@ -0,0 +1,982 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm pmic BCL hardware driver for battery overcurrent and + * battery or system under voltage monitor + * + * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qcom-bcl-hwmon.h" + +ADD_BCL_HWMON_ALARM_MAPS(in, min, lcrit); +ADD_BCL_HWMON_ALARM_MAPS(curr, max, crit); + +/* Interrupt names for each alarm level */ +static const char * const bcl_int_names[ALARM_MAX] = { + [LVL0] = "bcl-max-min", + [LVL1] = "bcl-critical", +}; + +static const char * const bcl_channel_label[CHANNEL_MAX] = { + "BCL Voltage", + "BCL Current", +}; + +/* Common Reg Fields */ +static const struct reg_field common_reg_fields[COMMON_FIELD_MAX] = { + [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), +}; + +/* BCL Version/Modes specific fields */ +static const struct reg_field bcl_v1_reg_fields[] = { + [F_IN_MON_EN] = REG_FIELD(MODE_CTL1, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(VADC_CONV_REQ, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(IADC_CONV_REQ, 0, 0), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_v2_reg_fields[] = { + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 1), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(VADC_CONV_REQ, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(IADC_CONV_REQ, 0, 0), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_v3_bmx_reg_fields[] = { + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR_GEN3, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_v3_wb_reg_fields[] = { + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 3), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_v3_core_reg_fields[] = { + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VCMP_L0_THR, 0, 5), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), +}; + +static const struct reg_field bcl_v4_bmx_reg_fields[] = { + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 15), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR_GEN3, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 15), +}; + +static const struct reg_field bcl_v4_wb_reg_fields[] = { + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 6), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 15), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 4), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 15), +}; + +static const struct reg_field bcl_v4_core_reg_fields[] = { + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VCMP_L0_THR, 0, 6), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 6), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 15), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), +}; + +/* V1 BMX and core */ +static const struct bcl_desc pm7250b_data = { + .reg_fields = bcl_v1_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 8, + .thresh_field_bits_size = 7, + .channel[IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {ADC, INDEX}, + }, + .channel[CURR] = { + .max = 10000, + .default_scale_nu = 305180, + .thresh_type = {ADC, ADC}, + }, +}; + +/* V2 BMX and core */ +static const struct bcl_desc pm8350_data = { + .reg_fields = bcl_v2_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 8, + .thresh_field_bits_size = 8, + .channel[IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {ADC, INDEX}, + }, + .channel[CURR] = { + .max = 10000, + .default_scale_nu = 305180, + .thresh_type = {ADC, ADC}, + }, +}; + +/* V3 BMX */ +static const struct bcl_desc pm8550b_data = { + .reg_fields = bcl_v3_bmx_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 8, + .thresh_field_bits_size = 8, + .channel[IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {ADC, INDEX}, + }, + .channel[CURR] = { + .max = 12000, + .default_scale_nu = 366220, + .thresh_type = {ADC, ADC}, + }, +}; + +/* V3 WB */ +static const struct bcl_desc pmw5100_data = { + .reg_fields = bcl_v3_wb_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 8, + .thresh_field_bits_size = 8, + .channel[IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {ADC, INDEX}, + }, + .channel[CURR] = { + .base = 800, + .max = 2000, + .step = 100, + .default_scale_nu = 61035, + .thresh_type = {ADC, INDEX}, + }, +}; + +/* V3 CORE */ +static const struct bcl_desc pm8550_data = { + .reg_fields = bcl_v3_core_reg_fields, + .num_reg_fields = F_CURR_MON_EN + 1, + .data_field_bits_size = 8, + .thresh_field_bits_size = 8, + .channel[IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .thresh_type = {INDEX, INDEX}, + }, +}; + +/* V4 BMX */ +static const struct bcl_desc pmih010_data = { + .reg_fields = bcl_v4_bmx_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 16, + .thresh_field_bits_size = 8, + .channel[IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {ADC, INDEX}, + }, + .channel[CURR] = { + .max = 20000, + .default_scale_nu = 610370, + .thresh_type = {ADC, ADC}, + }, +}; + +/* V4 WB */ +static const struct bcl_desc pmw6100_data = { + .reg_fields = bcl_v4_wb_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 16, + .thresh_field_bits_size = 8, + .channel[IN] = { + .base = 1500, + .max = 4000, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {ADC, INDEX}, + }, + .channel[CURR] = { + .base = 900, + .max = 3300, + .step = 150, + .default_scale_nu = 152586, + .thresh_type = {ADC, INDEX}, + }, +}; + +/* V4 CORE */ +static const struct bcl_desc pmh010_data = { + .reg_fields = bcl_v4_core_reg_fields, + .num_reg_fields = F_CURR_MON_EN + 1, + .thresh_field_bits_size = 8, + .channel[IN] = { + .base = 1500, + .max = 4000, + .step = 25, + .thresh_type = {INDEX, INDEX}, + }, +}; + +/* V4 BMX with different scale */ +static const struct bcl_desc pmv010_data = { + .reg_fields = bcl_v4_bmx_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 16, + .thresh_field_bits_size = 8, + .channel[IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {ADC, INDEX}, + }, + .channel[CURR] = { + .max = 12000, + .default_scale_nu = 366220, + .thresh_type = {ADC, ADC}, + }, +}; + +/** + * bcl_convert_raw_to_milliunit - Convert raw value to milli unit + * @desc: BCL device descriptor + * @raw_val: Raw ADC value from hardware + * @type: type of the channel, in or curr + * @field_width: bits size for data or threshold field + * + * Return: value in milli unit + */ +static unsigned int bcl_convert_raw_to_milliunit(const struct bcl_desc *desc, int raw_val, + enum bcl_channel_type type, u8 field_width) +{ + u32 def_scale = desc->channel[type].default_scale_nu; + u32 lsb_weight = field_width > 8 ? 1 : 1 << field_width; + u32 scaling_factor = def_scale * lsb_weight; + + return div_s64((s64)raw_val * scaling_factor, 1000000); +} + +/** + * bcl_convert_milliunit_to_raw - Convert milli unit to raw value + * @desc: BCL device descriptor + * @ma_val: threshold value in milli unit + * @type: type of the channel, in or curr + * @field_width: bits size for data or threshold field + * + * Return: Raw ADC value for hardware + */ +static unsigned int bcl_convert_milliunit_to_raw(const struct bcl_desc *desc, int mval, + enum bcl_channel_type type, u8 field_width) +{ + u32 def_scale = desc->channel[type].default_scale_nu; + u32 lsb_weight = field_width > 8 ? 1 : 1 << field_width; + u32 scaling_factor = def_scale * lsb_weight; + + return div_s64((s64)mval * 1000000, scaling_factor); +} + +/** + * bcl_convert_milliunit_to_index - Convert milliunit to in or curr index + * @desc: BCL device descriptor + * @val: in or curr value in milli unit + * @type: type of the channel, in or curr + * + * Converts a value in milli unit to an index for BCL that use indexed thresholds. + * + * Return: Voltage index value + */ +static unsigned int bcl_convert_milliunit_to_index(const struct bcl_desc *desc, int val, + enum bcl_channel_type type) +{ + return div_s64((s64)val - desc->channel[type].base, desc->channel[type].step); +} + +/** + * bcl_convert_index_to_milliunit - Convert in or curr index to milli unit + * @desc: BCL device descriptor + * @val: index value + * @type: type of the channel, in or curr + * + * Converts an index value to milli unit for BCL that use indexed thresholds. + * + * Return: Voltage value in millivolts + */ +static unsigned int bcl_convert_index_to_milliunit(const struct bcl_desc *desc, int val, + enum bcl_channel_type type) +{ + return desc->channel[type].base + val * desc->channel[type].step; +} + +static int bcl_in_thresh_write(struct bcl_device *bcl, long value, enum bcl_limit_alarm lvl) +{ + const struct bcl_desc *desc = bcl->desc; + u32 raw_val; + + int thresh = clamp_val(value, desc->channel[IN].base, desc->channel[IN].max); + + if (desc->channel[IN].thresh_type[lvl] == ADC) + raw_val = bcl_convert_milliunit_to_raw(desc, thresh, IN, + desc->thresh_field_bits_size); + else + raw_val = bcl_convert_milliunit_to_index(desc, thresh, IN); + + return regmap_field_write(bcl->fields[F_IN_L0_THR + lvl], raw_val); +} + +static int bcl_curr_thresh_write(struct bcl_device *bcl, long value, enum bcl_limit_alarm lvl) +{ + const struct bcl_desc *desc = bcl->desc; + u32 raw_val; + + /* Clamp only to curr max */ + int thresh = clamp_val(value, value, desc->channel[CURR].max); + + if (desc->channel[CURR].thresh_type[lvl] == ADC) + raw_val = bcl_convert_milliunit_to_raw(desc, thresh, CURR, + desc->thresh_field_bits_size); + else + raw_val = bcl_convert_milliunit_to_index(desc, thresh, CURR); + + return regmap_field_write(bcl->fields[F_CURR_H0_THR + lvl], raw_val); +} + +static int bcl_in_thresh_read(struct bcl_device *bcl, enum bcl_limit_alarm lvl, long *out) +{ + int ret, thresh; + u32 raw_val = 0; + const struct bcl_desc *desc = bcl->desc; + + ret = bcl_read_field_value(bcl, F_IN_L0_THR + lvl, &raw_val); + if (ret) + return ret; + + if (desc->channel[IN].thresh_type[lvl] == ADC) + thresh = bcl_convert_raw_to_milliunit(desc, raw_val, IN, + desc->thresh_field_bits_size); + else + thresh = bcl_convert_index_to_milliunit(desc, raw_val, IN); + + *out = thresh; + + return 0; +} + +static int bcl_curr_thresh_read(struct bcl_device *bcl, enum bcl_limit_alarm lvl, long *out) +{ + int ret, thresh; + u32 raw_val = 0; + const struct bcl_desc *desc = bcl->desc; + + ret = bcl_read_field_value(bcl, F_CURR_H0_THR + lvl, &raw_val); + if (ret) + return ret; + + if (desc->channel[CURR].thresh_type[lvl] == ADC) + thresh = bcl_convert_raw_to_milliunit(desc, raw_val, CURR, + desc->thresh_field_bits_size); + else + thresh = bcl_convert_index_to_milliunit(desc, raw_val, CURR); + + *out = thresh; + + return 0; +} + +static int bcl_curr_input_read(struct bcl_device *bcl, long *out) +{ + int ret; + u32 raw_val = 0; + const struct bcl_desc *desc = bcl->desc; + + ret = bcl_read_field_value(bcl, F_CURR_INPUT, &raw_val); + if (ret) + return ret; + + /* + * The sensor sometime can read a value 0 if there are + * consecutive reads + */ + if (raw_val != 0) + bcl->last_curr_input = + bcl_convert_raw_to_milliunit(desc, raw_val, CURR, + desc->data_field_bits_size); + + *out = bcl->last_curr_input; + + return 0; +} + +static int bcl_in_input_read(struct bcl_device *bcl, long *out) +{ + int ret; + u32 raw_val = 0; + const struct bcl_desc *desc = bcl->desc; + + ret = bcl_read_field_value(bcl, F_IN_INPUT, &raw_val); + if (ret) + return ret; + + if (raw_val < GENMASK(desc->data_field_bits_size - 1, 0)) + bcl->last_in_input = + bcl_convert_raw_to_milliunit(desc, raw_val, IN, + desc->data_field_bits_size); + + *out = bcl->last_in_input; + + return 0; +} + +static int bcl_read_alarm_status(struct bcl_device *bcl, + enum bcl_limit_alarm lvl, long *status) +{ + int ret; + u32 raw_val = 0; + + ret = bcl_read_field_value(bcl, F_LVL0_ALARM + lvl, &raw_val); + if (ret) + return ret; + + *status = raw_val; + + return 0; +} + +static unsigned int bcl_get_version_major(const struct bcl_device *bcl) +{ + u32 raw_val = 0; + + bcl_read_field_value(bcl, F_V_MAJOR, &raw_val); + + return raw_val; +} + +static unsigned int bcl_get_version_minor(const struct bcl_device *bcl) +{ + u32 raw_val = 0; + + bcl_read_field_value(bcl, F_V_MINOR, &raw_val); + + return raw_val; +} + +static void bcl_hwmon_notify_event(struct bcl_device *bcl, enum bcl_limit_alarm alarm) +{ + if (bcl->in_mon_enabled) + hwmon_notify_event(bcl->hwmon_dev, hwmon_in, + in_lvl_to_attr_map[alarm], 0); + if (bcl->curr_mon_enabled) + hwmon_notify_event(bcl->hwmon_dev, hwmon_curr, + curr_lvl_to_attr_map[alarm], 0); +} + +static void bcl_alarm_enable_poll(struct work_struct *work) +{ + struct bcl_alarm_data *alarm = container_of(work, struct bcl_alarm_data, + alarm_poll_work.work); + struct bcl_device *bcl = alarm->device; + long status; + + guard(mutex)(&bcl->lock); + + if (bcl_read_alarm_status(bcl, alarm->type, &status)) + goto re_schedule; + + if (!status & !alarm->irq_enabled) { + bcl_enable_irq(alarm); + bcl_hwmon_notify_event(bcl, alarm->type); + return; + } + +re_schedule: + schedule_delayed_work(&alarm->alarm_poll_work, + msecs_to_jiffies(BCL_ALARM_POLLING_MS)); +} + +static irqreturn_t bcl_handle_alarm(int irq, void *data) +{ + struct bcl_alarm_data *alarm = data; + struct bcl_device *bcl = alarm->device; + long status; + + guard(mutex)(&bcl->lock); + + if (bcl_read_alarm_status(bcl, alarm->type, &status) || !status) + return IRQ_HANDLED; + + if (!bcl->hwmon_dev) + return IRQ_HANDLED; + + bcl_hwmon_notify_event(bcl, alarm->type); + + bcl_disable_irq(alarm); + schedule_delayed_work(&alarm->alarm_poll_work, + msecs_to_jiffies(BCL_ALARM_POLLING_MS)); + + dev_dbg(bcl->dev, "Irq:%d triggered for bcl type:%d\n", + irq, alarm->type); + + return IRQ_HANDLED; +} + +static umode_t bcl_hwmon_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct bcl_device *bcl = data; + + switch (type) { + case hwmon_in: + if (!bcl->in_mon_enabled) + return 0; + switch (attr) { + case hwmon_in_input: + return bcl->in_input_enabled ? 0444 : 0; + case hwmon_in_label: + case hwmon_in_min_alarm: + case hwmon_in_lcrit_alarm: + return 0444; + case hwmon_in_min: + case hwmon_in_lcrit: + return 0644; + default: + return 0; + } + case hwmon_curr: + if (!bcl->curr_mon_enabled) + return 0; + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_label: + case hwmon_curr_max_alarm: + case hwmon_curr_crit_alarm: + return 0444; + case hwmon_curr_max: + case hwmon_curr_crit: + return 0644; + default: + return 0; + } + default: + return 0; + } +} + +static int bcl_hwmon_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct bcl_device *bcl = dev_get_drvdata(dev); + int ret = -EOPNOTSUPP; + + guard(mutex)(&bcl->lock); + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_min: + case hwmon_in_lcrit: + ret = bcl_in_thresh_write(bcl, val, in_attr_to_lvl_map[attr]); + break; + default: + ret = -EOPNOTSUPP; + } + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_max: + case hwmon_curr_crit: + ret = bcl_curr_thresh_write(bcl, val, curr_attr_to_lvl_map[attr]); + break; + default: + ret = -EOPNOTSUPP; + } + break; + default: + break; + } + + return ret; +} + +static int bcl_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *value) +{ + struct bcl_device *bcl = dev_get_drvdata(dev); + int ret; + + guard(mutex)(&bcl->lock); + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_input: + ret = bcl_in_input_read(bcl, value); + break; + case hwmon_in_min: + case hwmon_in_lcrit: + ret = bcl_in_thresh_read(bcl, in_attr_to_lvl_map[attr], value); + break; + case hwmon_in_min_alarm: + case hwmon_in_lcrit_alarm: + ret = bcl_read_alarm_status(bcl, in_attr_to_lvl_map[attr], value); + break; + default: + ret = -EOPNOTSUPP; + } + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + ret = bcl_curr_input_read(bcl, value); + break; + case hwmon_curr_max: + case hwmon_curr_crit: + ret = bcl_curr_thresh_read(bcl, curr_attr_to_lvl_map[attr], value); + break; + case hwmon_curr_max_alarm: + case hwmon_curr_crit_alarm: + ret = bcl_read_alarm_status(bcl, curr_attr_to_lvl_map[attr], value); + break; + default: + ret = -EOPNOTSUPP; + } + break; + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +static int bcl_hwmon_read_string(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + switch (type) { + case hwmon_in: + if (attr != hwmon_in_label) + break; + *str = bcl_channel_label[IN]; + return 0; + case hwmon_curr: + if (attr != hwmon_curr_label) + break; + *str = bcl_channel_label[CURR]; + return 0; + default: + break; + } + + return -EOPNOTSUPP; +} + +static const struct hwmon_ops bcl_hwmon_ops = { + .is_visible = bcl_hwmon_is_visible, + .read = bcl_hwmon_read, + .read_string = bcl_hwmon_read_string, + .write = bcl_hwmon_write, +}; + +static const struct hwmon_channel_info *bcl_hwmon_info[] = { + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL | HWMON_I_MIN | + HWMON_I_LCRIT | HWMON_I_MIN_ALARM | + HWMON_I_LCRIT_ALARM), + HWMON_CHANNEL_INFO(curr, + HWMON_C_INPUT | HWMON_C_LABEL | HWMON_C_MAX | + HWMON_C_CRIT | HWMON_C_MAX_ALARM | + HWMON_C_CRIT_ALARM), + NULL, +}; + +static const struct hwmon_chip_info bcl_hwmon_chip_info = { + .ops = &bcl_hwmon_ops, + .info = bcl_hwmon_info, +}; + +static int bcl_curr_thresh_update(struct bcl_device *bcl) +{ + int ret, i; + + if (!bcl->curr_thresholds[0]) + return 0; + + for (i = 0; i < ALARM_MAX; i++) { + ret = bcl_curr_thresh_write(bcl, bcl->curr_thresholds[i], i); + if (ret < 0) + return ret; + } + + return 0; +} + +static void bcl_hw_channel_mon_init(struct bcl_device *bcl) +{ + bcl->in_mon_enabled = bcl_in_monitor_enabled(bcl); + bcl->in_input_enabled = bcl_in_input_enabled(bcl); + bcl->curr_mon_enabled = bcl_curr_monitor_enabled(bcl); +} + +static int bcl_alarm_irq_init(struct platform_device *pdev, + struct bcl_device *bcl) +{ + int ret = 0, irq_num = 0, i = 0; + struct bcl_alarm_data *alarm; + + for (i = LVL0; i < ALARM_MAX; i++) { + alarm = &bcl->bcl_alarms[i]; + alarm->type = i; + alarm->device = bcl; + + ret = devm_delayed_work_autocancel(bcl->dev, &alarm->alarm_poll_work, + bcl_alarm_enable_poll); + if (ret) + return ret; + + irq_num = platform_get_irq_byname(pdev, bcl_int_names[i]); + if (irq_num <= 0) + continue; + + ret = devm_request_threaded_irq(&pdev->dev, irq_num, NULL, + bcl_handle_alarm, IRQF_ONESHOT, + bcl_int_names[i], alarm); + if (ret) { + dev_err(&pdev->dev, "Error requesting irq(%s).err:%d\n", + bcl_int_names[i], ret); + return ret; + } + alarm->irq = irq_num; + enable_irq_wake(alarm->irq); + alarm->irq_enabled = true; + } + + return 0; +} + +static int bcl_regmap_field_init(struct device *dev, struct bcl_device *bcl, + const struct bcl_desc *data) +{ + int i; + struct reg_field fields[F_MAX_FIELDS]; + + BUILD_BUG_ON(ARRAY_SIZE(common_reg_fields) != COMMON_FIELD_MAX); + + for (i = 0; i < data->num_reg_fields; i++) { + if (i < COMMON_FIELD_MAX) + fields[i] = common_reg_fields[i]; + else + fields[i] = data->reg_fields[i]; + + /* Need to adjust BCL base from regmap dynamically */ + fields[i].reg += bcl->base; + } + + return devm_regmap_field_bulk_alloc(dev, bcl->regmap, bcl->fields, + fields, data->num_reg_fields); +} + +static int bcl_get_device_property_data(struct platform_device *pdev, + struct bcl_device *bcl) +{ + struct device *dev = &pdev->dev; + int ret; + u32 reg; + + ret = device_property_read_u32(dev, "reg", ®); + if (ret < 0) + return ret; + + bcl->base = reg; + + device_property_read_u32_array(dev, "overcurrent-thresholds-milliamp", + bcl->curr_thresholds, 2); + return 0; +} + +static int bcl_probe(struct platform_device *pdev) +{ + struct bcl_device *bcl; + int ret; + + bcl = devm_kzalloc(&pdev->dev, sizeof(*bcl), GFP_KERNEL); + if (!bcl) + return -ENOMEM; + + bcl->dev = &pdev->dev; + bcl->desc = device_get_match_data(&pdev->dev); + if (!bcl->desc) + return -EINVAL; + + ret = devm_mutex_init(bcl->dev, &bcl->lock); + if (ret) + return ret; + + bcl->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!bcl->regmap) { + dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + ret = bcl_get_device_property_data(pdev, bcl); + if (ret < 0) + return ret; + + ret = bcl_regmap_field_init(bcl->dev, bcl, bcl->desc); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to allocate regmap fields, err:%d\n", ret); + return ret; + } + + if (!bcl_hw_is_enabled(bcl)) + return -ENODEV; + + ret = bcl_curr_thresh_update(bcl); + if (ret < 0) + return ret; + + ret = bcl_alarm_irq_init(pdev, bcl); + if (ret < 0) + return ret; + + bcl_hw_channel_mon_init(bcl); + + dev_set_drvdata(&pdev->dev, bcl); + + bcl->hwmon_name = devm_hwmon_sanitize_name(&pdev->dev, + dev_name(bcl->dev)); + if (IS_ERR(bcl->hwmon_name)) { + dev_err(&pdev->dev, "Failed to sanitize hwmon name\n"); + return PTR_ERR(bcl->hwmon_name); + } + + bcl->hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, + bcl->hwmon_name, + bcl, + &bcl_hwmon_chip_info, + NULL); + if (IS_ERR(bcl->hwmon_dev)) { + dev_err(&pdev->dev, "Failed to register hwmon device: %ld\n", + PTR_ERR(bcl->hwmon_dev)); + return PTR_ERR(bcl->hwmon_dev); + } + + dev_dbg(&pdev->dev, "BCL hwmon device with version: %u.%u registered\n", + bcl_get_version_major(bcl), bcl_get_version_minor(bcl)); + + return 0; +} + +static const struct of_device_id bcl_match[] = { + { + .compatible = "qcom,bcl-v1", + .data = &pm7250b_data, + }, { + .compatible = "qcom,bcl-v2", + .data = &pm8350_data, + }, { + .compatible = "qcom,bcl-v3-bmx", + .data = &pm8550b_data, + }, { + .compatible = "qcom,bcl-v3-wb", + .data = &pmw5100_data, + }, { + .compatible = "qcom,bcl-v3-core", + .data = &pm8550_data, + }, { + .compatible = "qcom,bcl-v4-bmx", + .data = &pmih010_data, + }, { + .compatible = "qcom,bcl-v4-wb", + .data = &pmw6100_data, + }, { + .compatible = "qcom,bcl-v4-core", + .data = &pmh010_data, + }, { + .compatible = "qcom,bcl-v4-pmv010", + .data = &pmv010_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, bcl_match); + +static struct platform_driver bcl_driver = { + .probe = bcl_probe, + .driver = { + .name = BCL_DRIVER_NAME, + .of_match_table = bcl_match, + }, +}; + +MODULE_AUTHOR("Manaf Meethalavalappu Pallikunhi "); +MODULE_DESCRIPTION("QCOM BCL HWMON driver"); +module_platform_driver(bcl_driver); +MODULE_LICENSE("GPL"); diff --git a/drivers/hwmon/qcom-bcl-hwmon.h b/drivers/hwmon/qcom-bcl-hwmon.h new file mode 100644 index 0000000000000..28a7154d9486a --- /dev/null +++ b/drivers/hwmon/qcom-bcl-hwmon.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __QCOM_BCL_HWMON_H__ +#define __QCOM_BCL_HWMON_H__ + +#define BCL_DRIVER_NAME "qcom-bcl-hwmon" + +/* BCL common regmap offset */ +#define REVISION1 0x0 +#define REVISION2 0x1 +#define STATUS 0x8 +#define INT_RT_STS 0x10 +#define EN_CTL1 0x46 + +/* BCL GEN1 regmap offsets */ +#define MODE_CTL1 0x41 +#define VADC_L0_THR 0x48 +#define VCMP_L1_THR 0x49 +#define IADC_H0_THR 0x4b +#define IADC_H1_THR 0x4c +#define VADC_CONV_REQ 0x72 +#define IADC_CONV_REQ 0x82 +#define VADC_DATA1 0x76 +#define IADC_DATA1 0x86 + +/* BCL GEN3 regmap offsets */ +#define VCMP_CTL 0x44 +#define VCMP_L0_THR 0x47 +#define PARAM_1 0x0e +#define IADC_H1_THR_GEN3 0x4d + +#define BCL_IN_INC_MV 25 +#define BCL_ALARM_POLLING_MS 50 + +/** + * enum bcl_limit_alarm - BCL alarm threshold levels + * @LVL0: Level 0 alarm threshold (mapped to in_min_alarm or curr_max_alarm) + * @LVL1: Level 1 alarm threshold (mapped to in_lcrit_alarm or curr_crit_alarm) + * @ALARM_MAX: sentinel value + * + * Defines the three threshold levels for BCL monitoring. Each level corresponds + * to different severity of in or curr conditions. + */ +enum bcl_limit_alarm { + LVL0, + LVL1, + + ALARM_MAX, +}; + +/** + * enum bcl_channel_type - BCL supported sensor channel type + * @IN: in (voltage) channel + * @CURR: curr (current) channel + * @CHANNEL_MAX: sentinel value + * + * Defines the supported channel types for bcl. + */ +enum bcl_channel_type { + IN, + CURR, + + CHANNEL_MAX, +}; + +/** + * enum bcl_thresh_type - voltage or current threshold representation type + * @ADC: Raw ADC value representation + * @INDEX: Index-based voltage or current representation + * + * Specifies how voltage or current thresholds are stored and interpreted in + * registers. Some PMICs use raw ADC values while others use indexed values. + */ +enum bcl_thresh_type { + ADC, + INDEX, +}; + +/** + * enum bcl_fields - BCL register field identifiers + * @F_V_MAJOR: Major revision info field + * @F_V_MINOR: Minor revision info field + * @F_CTL_EN: Monitor enable control field + * @F_LVL0_ALARM: Level 0 alarm status field + * @F_LVL1_ALARM: Level 1 alarm status field + * @COMMON_FIELD_MAX: sentinel value for common fields + * @F_IN_MON_EN: voltage monitor enable control field + * @F_IN_L0_THR: voltage level 0 threshold field + * @F_IN_L1_THR: voltage level 1 threshold field + * @F_IN_INPUT_EN: voltage input enable control field + * @F_IN_INPUT: voltage input data field + * @F_CURR_MON_EN: current monitor enable control field + * @F_CURR_H0_THR: current level 0 threshold field + * @F_CURR_H1_THR: current level 1 threshold field + * @F_CURR_INPUT: current input data field + * @F_MAX_FIELDS: sentinel value + * + * Enumeration of all register fields used by the BCL driver for accessing + * registers through regmap fields. + */ +enum bcl_fields { + F_V_MAJOR, + F_V_MINOR, + + F_CTL_EN, + + /* common alarm for in and curr channel */ + F_LVL0_ALARM, + F_LVL1_ALARM, + + COMMON_FIELD_MAX, + + F_IN_MON_EN = COMMON_FIELD_MAX, + F_IN_L0_THR, + F_IN_L1_THR, + + F_IN_INPUT_EN, + F_IN_INPUT, + + F_CURR_MON_EN, + F_CURR_H0_THR, + F_CURR_H1_THR, + + F_CURR_INPUT, + + F_MAX_FIELDS +}; + +#define ADD_BCL_HWMON_ALARM_MAPS(_type, lvl0_attr, lvl1_attr) \ + \ +static const u8 _type##_attr_to_lvl_map[] = { \ + [hwmon_##_type##_##lvl0_attr] = LVL0, \ + [hwmon_##_type##_##lvl1_attr] = LVL1, \ + [hwmon_##_type##_##lvl0_attr##_alarm] = LVL0, \ + [hwmon_##_type##_##lvl1_attr##_alarm] = LVL1, \ +}; \ + \ +static const u8 _type##_lvl_to_attr_map[ALARM_MAX] = { \ + [LVL0] = hwmon_##_type##_##lvl0_attr##_alarm, \ + [LVL1] = hwmon_##_type##_##lvl1_attr##_alarm, \ +} + +/** + * struct bcl_channel_cfg - BCL channel related configuration + * @default_scale_nu: Default scaling factor in nano unit + * @base: Base threshold value in milli unit + * @max: Maximum threshold value in milli unit + * @step: step increment value between two indexed threshold value + * @thresh_type: Array specifying threshold representation type for each alarm level + * + * Contains hardware-specific configuration and scaling parameters for different + * channel(voltage and current).. + */ + +struct bcl_channel_cfg { + u32 default_scale_nu; + u32 base; + u32 max; + u32 step; + u8 thresh_type[ALARM_MAX]; +}; + +/** + * struct bcl_desc - BCL device descriptor + * @reg_fields: Array of register field definitions for this device variant + * @channel: Each channel specific(voltage or current) configuration + * @num_reg_fields: Number of register field definitions for this device variant + * @data_field_bits_size: data read register bit size + * @thresh_field_bits_size: lsb bit size those are not included in threshold register + * + * Contains hardware-specific configuration and scaling parameters for different + * BCL variants. Each PMIC model may have different register layouts and + * conversion factors. + */ + +struct bcl_desc { + const struct reg_field *reg_fields; + struct bcl_channel_cfg channel[CHANNEL_MAX]; + u8 num_reg_fields; + u8 data_field_bits_size; + u8 thresh_field_bits_size; +}; + +struct bcl_device; + +/** + * struct bcl_alarm_data - BCL alarm interrupt data + * @irq: IRQ number assigned to this alarm + * @irq_enabled: Flag indicating if IRQ is enabled + * @type: Alarm level type (LVL0, or LVL1) + * @device: Pointer to parent BCL device structure + * @alarm_poll_work: delayed_work to poll alarm status + * + * Stores interrupt-related information for each alarm threshold level. + * Used by the IRQ handler to identify which alarm triggered. + */ +struct bcl_alarm_data { + int irq; + bool irq_enabled; + enum bcl_limit_alarm type; + struct bcl_device *device; + struct delayed_work alarm_poll_work; +}; + +/** + * struct bcl_device - Main BCL device structure + * @dev: Pointer to device structure + * @regmap: Regmap for accessing PMIC registers + * @fields: Array of regmap fields for register access + * @bcl_alarms: Array of alarm data structures for each threshold level + * @lock: Mutex for protecting concurrent hardware access + * @in_mon_enabled: Flag indicating if voltage monitoring is enabled + * @curr_mon_enabled: Flag indicating if current monitoring is enabled + * @curr_thresholds: Current threshold values in milliamps from dt-binding(LVL0 and LVL1) + * @base: the BCL regbase offset from regmap + * @in_input_enabled: Flag indicating if voltage input reading is enabled + * @last_in_input: Last valid voltage input reading in millivolts + * @last_curr_input: Last valid current input reading in milliamps + * @desc: Pointer to device descriptor with hardware-specific parameters + * @hwmon_dev: Pointer to registered hwmon device + * @hwmon_name: Sanitized name for hwmon device + * + * Main driver structure containing all state and configuration for a BCL + * monitoring instance. Manages voltage and current monitoring, thresholds, + * and alarm handling. + */ +struct bcl_device { + struct device *dev; + struct regmap *regmap; + u16 base; + struct regmap_field *fields[F_MAX_FIELDS]; + struct bcl_alarm_data bcl_alarms[ALARM_MAX]; + struct mutex lock; + u32 curr_thresholds[ALARM_MAX]; + u32 last_in_input; + u32 last_curr_input; + bool in_mon_enabled; + bool curr_mon_enabled; + bool in_input_enabled; + const struct bcl_desc *desc; + struct device *hwmon_dev; + char *hwmon_name; +}; + +/** + * bcl_read_field_value - Read alarm status for a given level + * @bcl: BCL device structure + * @id: Index in bcl->fields[] + * @val: Pointer to store val + * + * Return: 0 on success or regmap error code + */ +static inline int bcl_read_field_value(const struct bcl_device *bcl, enum bcl_fields id, u32 *val) +{ + return regmap_field_read(bcl->fields[id], val); +} + +/** + * bcl_field_enabled - Generic helper to check if a regmap field is enabled + * @bcl: BCL device structure + * @field: Index in bcl->fields[] + * + * Return: true if field is non-zero, false otherwise + */ +static inline bool bcl_field_enabled(const struct bcl_device *bcl, enum bcl_fields id) +{ + int ret; + u32 val = 0; + + ret = regmap_field_read(bcl->fields[id], &val); + if (ret) + return false; + + return !!val; +} + +#define bcl_in_input_enabled(bcl) bcl_field_enabled(bcl, F_IN_INPUT_EN) +#define bcl_curr_monitor_enabled(bcl) bcl_field_enabled(bcl, F_CURR_MON_EN) +#define bcl_in_monitor_enabled(bcl) bcl_field_enabled(bcl, F_IN_MON_EN) +#define bcl_hw_is_enabled(bcl) bcl_field_enabled(bcl, F_CTL_EN) + +/** + * bcl_enable_irq - Generic helper to enable alarm irq + * @alarm: BCL level alarm data + */ +static inline void bcl_enable_irq(struct bcl_alarm_data *alarm) +{ + if (alarm->irq_enabled) + return; + alarm->irq_enabled = true; + enable_irq(alarm->irq); + enable_irq_wake(alarm->irq); +} + +/** + * bcl_disable_irq - Generic helper to disable alarm irq + * @alarm: BCL level alarm data + */ +static inline void bcl_disable_irq(struct bcl_alarm_data *alarm) +{ + if (!alarm->irq_enabled) + return; + alarm->irq_enabled = false; + disable_irq_nosync(alarm->irq); + disable_irq_wake(alarm->irq); +} + +#endif /* __QCOM_BCL_HWMON_H__ */ From 1e1a9e6c40b64bd35905feaa8be577dee191b74c Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 12 Mar 2026 21:26:35 +0530 Subject: [PATCH 0541/1330] FROMLIST: arm64: dts: qcom: x1e80100: Remove interconnect from SCM device Interconnect from SCM device are optional and were added to get additional performance benefit. These nodes however delays the SCM firmware device probe due to dependency on interconnect and results in NULL pointer dereference for the users of SCM device driver APIs, such as PDC driver. Remove them from the scm device to unblock the user. Link: https://lore.kernel.org/r/20260312-hamoa_pdc-v1-1-760c8593ce50@oss.qualcomm.com Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index eddfba5f8492b..f885d7b7a06c4 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -526,8 +526,7 @@ firmware { scm: scm { compatible = "qcom,scm-x1e80100", "qcom,scm"; - interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + /* TODO: add interconnects */ qcom,dload-mode = <&tcsr 0x19000>; }; From 779cab15edc3d821884d76d2d0b8706dd569c629 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 12 Mar 2026 21:26:38 +0530 Subject: [PATCH 0542/1330] FROMLIST: arm64: dts: qcom: x1e80100: Add deepest idle state Add deepest idle state along with pdc config reg to make GPIO IRQs work as wakeup capable interrupts in deepest idle state. Add QMP handle to allow PDC device to place a SoC level low power mode restriction. Link: https://lore.kernel.org/r/20260312-hamoa_pdc-v1-4-760c8593ce50@oss.qualcomm.com Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index f885d7b7a06c4..d2a54b1215a07 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -304,6 +304,14 @@ exit-latency-us = <4000>; min-residency-us = <7000>; }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x0200c354>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <9000>; + }; }; }; @@ -665,7 +673,7 @@ system_pd: power-domain-system { #power-domain-cells = <0>; - /* TODO: system-wide idle states */ + domain-idle-states = <&domain_ss3>; }; reboot-mode { @@ -6763,8 +6771,10 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,x1e80100-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; - + reg = <0 0x0b220000 0 0x30000>, + <0 0x174000f0 0 0x64>, + <0 0x0b2045e8 0 0x4>; + qcom,qmp = <&aoss_qmp>; qcom,pdc-ranges = <0 480 42>, <42 251 5>, <47 522 52>, <99 609 32>, <131 717 12>, <143 816 19>; From 6094334adb0f34a18f1857dcb8db2f7cd9713a97 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 31 Dec 2025 15:48:46 +0530 Subject: [PATCH 0543/1330] FROMLIST: arm64: dts: qcom: purwa: Drop the Hamoa workaround for PDC Purwa shares the Hamoa (X1E80100) PDC device, but the hardware register bug addressed in commit e9a48ea4d90b ("irqchip/qcom-pdc: Workaround hardware register bug on X1E80100") is already fixed in Purwa silicon. Hamoa compatible forces the software workaround. Use the Purwa specific compatible string for the PDC node to remove the workaround from Purwa. Fixes: f08edb529916 ("arm64: dts: qcom: Add X1P42100 SoC and CRD") Link: https://lore.kernel.org/r/20251231-purwa_pdc-v1-2-2b4979dd88ad@oss.qualcomm.com Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad --- arch/arm64/boot/dts/qcom/purwa.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 4f9357787fee7..743eb12569f41 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -174,6 +174,10 @@ compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; }; +&pdc { + compatible = "qcom,x1p42100-pdc", "qcom,pdc"; +}; + &qfprom { gpu_speed_bin: gpu-speed-bin@119 { reg = <0x119 0x2>; From e8420d96d22336cc2c6c3f61257dc847612eb73f Mon Sep 17 00:00:00 2001 From: Shuai Zhang Date: Tue, 24 Mar 2026 14:59:48 +0800 Subject: [PATCH 0544/1330] WORKAROUND: arm64: dts: qcom: hamoa-iot-evk: support Bluetooth over both USB and UART On Hamoa boards, a single M.2 slot may host either a UART-based or a USB-based Bluetooth device. As a result, the UART controller node is always present in DT, while the USB path is hot-pluggable. When Bluetooth operates over USB, the presence of the UART DT node still causes the hci_qca UART driver to probe. During probe or power sequencing, the driver may deassert BT_EN, cutting power to the shared Bluetooth device and disconnecting the USB interface. Model BT_EN as an always-on fixed regulator so it cannot be toggled by the UART probe. This prevents the UART driver from interfering with Bluetooth operation when the device is connected over USB. Workaround will be reverted once the M.2 solutionis available upstream. Signed-off-by: Shuai Zhang --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 34 ++++++++++++++++------ 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 79be3d347f471..e24858d5fadcc 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -514,6 +514,23 @@ regulator-boot-on; }; + vreg_wcn_bt_en: regulator-wcn-bt-en { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_BT_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 116 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_bt_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -679,10 +696,9 @@ vddrfa1p2-supply = <&vreg_wcn_1p9>; vddrfa1p8-supply = <&vreg_wcn_1p9>; - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-0 = <&wcn_wlan_en>; pinctrl-names = "default"; regulators { @@ -1518,13 +1534,13 @@ compatible = "qcom,wcn7850-bt"; max-speed = <3200000>; - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddrfacmn-supply = <&vreg_wcn_3p3>; + vddaon-supply = <&vreg_wcn_3p3>; + vddwlcx-supply = <&vreg_wcn_3p3>; + vddwlmx-supply = <&vreg_wcn_3p3>; + vddrfa0p8-supply = <&vreg_wcn_3p3>; + vddrfa1p2-supply = <&vreg_wcn_3p3>; + vddrfa1p8-supply = <&vreg_wcn_3p3>; }; }; From 48669446fa3a3c345c723686216dbb19e839903b Mon Sep 17 00:00:00 2001 From: Shuai Zhang Date: Thu, 19 Mar 2026 11:56:41 +0800 Subject: [PATCH 0545/1330] WORKAROUND: power: sequencing: qcom-wcn: skip BT devices without bt-enable GPIO If a Bluetooth consumer device does not have a bt-enable GPIO configured in the power sequencer (for example, when BT_EN is tied high via a hardware pull-up and therefore absent from the DT), the power sequencer should not match the device. In this case, the Bluetooth consumer driver will fall back to its legacy power control path and correctly set power_ctrl_enabled to false. Bluetooth device nodes are conventionally named "bluetooth" in the device tree, so use of_node_name_eq() as a generic check instead of enumerating specific compatible strings. Workaround will be reverted once the M.2 solution is available upstream. Signed-off-by: Shuai Zhang --- drivers/power/sequencing/pwrseq-qcom-wcn.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/power/sequencing/pwrseq-qcom-wcn.c b/drivers/power/sequencing/pwrseq-qcom-wcn.c index b55b4317e21b6..dc83d32415a2d 100644 --- a/drivers/power/sequencing/pwrseq-qcom-wcn.c +++ b/drivers/power/sequencing/pwrseq-qcom-wcn.c @@ -432,6 +432,20 @@ static int pwrseq_qcom_wcn_match_regulator(struct pwrseq_device *pwrseq, reg_node->parent->parent != ctx->of_node) return PWRSEQ_NO_MATCH; + /* + * If this is a Bluetooth consumer device but the bt-enable GPIO is not + * configured in the power sequencer (e.g. BT_EN is tied high via a + * hardware pull-up and therefore absent from the DT), don't match. + * The consumer driver will fall back to its legacy power control path + * and correctly set power_ctrl_enabled to false. + * + * BT device nodes are conventionally named "bluetooth" in the DT, + * so use of_node_name_eq() as a generic check rather than enumerating + * specific compatible strings. + */ + if (!ctx->bt_gpio && of_node_name_eq(dev_node, "bluetooth")) + return PWRSEQ_NO_MATCH; + return PWRSEQ_MATCH_OK; } From 49db42fb9b93e32b076b6fd8d268b7149a5b23f0 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 1 Apr 2026 19:22:14 +0530 Subject: [PATCH 0546/1330] dt-bindings: watchdog: qcom-wdt: Document Shikra watchdog Add devicetree binding for watchdog present on Qualcomm's Shikra SoC. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 9f861045b71e8..69ab3bf5db903 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -40,6 +40,7 @@ properties: - qcom,apss-wdt-sdm845 - qcom,apss-wdt-sdx55 - qcom,apss-wdt-sdx65 + - qcom,apss-wdt-shikra - qcom,apss-wdt-sm6115 - qcom,apss-wdt-sm6350 - qcom,apss-wdt-sm8150 From c7112e150b7ec1b607f1c99a50f22923161744a8 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 1 Apr 2026 19:02:52 +0530 Subject: [PATCH 0547/1330] arm64: dts: qcom: shikra: Add watchdog node Add the watchdog node for Shikra SoC. Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 202c21096d5ee..0cdf3f0c9f6dd 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -541,6 +541,14 @@ #mbox-cells = <1>; }; + watchdog@f410000 { + compatible = "qcom,apss-wdt-shikra", "qcom,kpss-wdt"; + reg = <0x0 0x0f410000 0x0 0x1000>; + interrupts = , + ; + clocks = <&sleep_clk>; + }; + timer@f420000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0f420000 0x0 0x1000>; From d8aa2f393294cbfd997db4c47da6479b340050f4 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 12 Mar 2026 21:26:36 +0530 Subject: [PATCH 0548/1330] FROMLIST: dt-bindings: interrupt-controller: qcom,pdc: Document reg and QMP Document PDC reg to configure pass through or secondary controller mode for GPIO IRQs. Document QMP handle for action concerning global resources. Link: https://lore.kernel.org/r/20260312-hamoa_pdc-v1-2-760c8593ce50@oss.qualcomm.com Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index f9321366cae45..9e07a9b5f456d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -61,6 +61,7 @@ properties: items: - description: PDC base register region - description: Edge or Level config register for SPI interrupts + - description: PDC config for pass through or secondary IRQ mode for GPIOs '#interrupt-cells': const: 2 @@ -81,6 +82,10 @@ properties: The tuples indicates the valid mapping of valid PDC ports and their hwirq mapping. + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + required: - compatible - reg From 33ce9393a9ec89f497c1208b3889e19c48ce10fe Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 12 Mar 2026 21:26:37 +0530 Subject: [PATCH 0549/1330] FROMLIST: irqchip/qcom-pdc: Configure PDC to pass through mode There are two modes PDC irqchip supports pass through mode and secondary controller mode. All PDC irqchip supports pass through mode in which both Direct SPIs and GPIO IRQs (as SPIs) are sent to GIC without latching at PDC. Newer PDCs (v3.0 onwards) also support additional secondary controller mode where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs still works same as pass through mode without latching at PDC even in secondary controller mode. All the SoCs so far default uses pass through mode with the exception of x1e. x1e PDC may be set to secondary controller mode for builds on CRD boards whereas it may be set to pass through mode for IoT-EVK. There is no way to read which current mode it is set to and make PDC work in respective mode as the read access is not opened up for non secure world. There is though write access opened up via SCM write API to set the mode. Configure PDC mode to pass through mode for all x1e based boards via SCM write. Link: https://lore.kernel.org/r/20260312-hamoa_pdc-v1-3-760c8593ce50@oss.qualcomm.com Co-developed-by: Sneh Mankad Signed-off-by: Sneh Mankad Signed-off-by: Maulik Shah --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/qcom-pdc.c | 119 ++++++++++++++++++++++++++++++++++--- 2 files changed, 111 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f07b00d7fef90..1d4ed503b2625 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -508,6 +508,7 @@ config GOLDFISH_PIC config QCOM_PDC tristate "QCOM PDC" depends on ARCH_QCOM + depends on QCOM_AOSS_QMP select IRQ_DOMAIN_HIERARCHY help Power Domain Controller driver to manage and configure wakeup diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 32b77fa93f730..051700d672471 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #define PDC_MAX_GPIO_IRQS 256 #define PDC_DRV_OFFSET 0x10000 @@ -26,9 +28,11 @@ /* Valid only on HW version < 3.2 */ #define IRQ_ENABLE_BANK 0x10 #define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_IRQS)) +#define IRQ_i_CFG_IRQ_MASK_3_0 3 #define IRQ_i_CFG 0x110 /* Valid only on HW version >= 3.2 */ +#define IRQ_i_CFG_IRQ_MASK_3_2 4 #define IRQ_i_CFG_IRQ_ENABLE 3 #define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0) @@ -36,8 +40,11 @@ #define PDC_VERSION_REG 0x1000 /* Notable PDC versions */ +#define PDC_VERSION_3_0 0x30000 #define PDC_VERSION_3_2 0x30200 +#define PDC_PASS_THROUGH_MODE 0 + struct pdc_pin_region { u32 pin_base; u32 parent_base; @@ -97,6 +104,33 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 enable) pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable); } +/* + * The new mask bit controls whether the interrupt is to be forwarded to the + * parent GIC in secondary controller mode. Writing the mask is do not care + * when the PDC is set to pass through mode. + * + * As linux only makes so far make use of pass through mode set all IRQs + * masked during probe. + */ +static void __pdc_mask_intr(int pin_out, bool mask) +{ + unsigned long irq_cfg; + int mask_bit; + + /* Mask bit available from v3.0 */ + if (pdc_version < PDC_VERSION_3_0) + return; + + if (pdc_version < PDC_VERSION_3_2) + mask_bit = IRQ_i_CFG_IRQ_MASK_3_0; + else + mask_bit = IRQ_i_CFG_IRQ_MASK_3_2; + + irq_cfg = pdc_reg_read(IRQ_i_CFG, pin_out); + __assign_bit(mask_bit, &irq_cfg, mask); + pdc_reg_write(IRQ_i_CFG, pin_out, irq_cfg); +} + static void __pdc_enable_intr(int pin_out, bool on) { unsigned long enable; @@ -312,7 +346,6 @@ static const struct irq_domain_ops qcom_pdc_ops = { static int pdc_setup_pin_mapping(struct device_node *np) { int ret, n, i; - n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); if (n <= 0 || n % 3) return -EINVAL; @@ -341,8 +374,10 @@ static int pdc_setup_pin_mapping(struct device_node *np) if (ret) return ret; - for (i = 0; i < pdc_region[n].cnt; i++) + for (i = 0; i < pdc_region[n].cnt; i++) { __pdc_enable_intr(i + pdc_region[n].pin_base, 0); + __pdc_mask_intr(i + pdc_region[n].pin_base, true); + } } return 0; @@ -352,10 +387,13 @@ static int pdc_setup_pin_mapping(struct device_node *np) static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *parent) { + static const char buf[64] = "{class: cx_mol, res: cx, val: mol}"; + unsigned int domain_flag = IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP; struct irq_domain *parent_domain, *pdc_domain; struct device_node *node = pdev->dev.of_node; resource_size_t res_size; struct resource res; + struct qmp *pdc_qmp; int ret; /* compat with old sm8150 DT which had very small region for PDC */ @@ -366,6 +404,13 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare if (res_size > resource_size(&res)) pr_warn("%pOF: invalid reg size, please fix DT\n", node); + pdc_base = ioremap(res.start, res_size); + if (!pdc_base) { + pr_err("%pOF: unable to map PDC registers\n", node); + ret = -ENXIO; + goto fail; + } + /* * PDC has multiple DRV regions, each one provides the same set of * registers for a particular client in the system. Due to a hardware @@ -382,15 +427,71 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare } pdc_x1e_quirk = true; - } - pdc_base = ioremap(res.start, res_size); - if (!pdc_base) { - pr_err("%pOF: unable to map PDC registers\n", node); - ret = -ENXIO; - goto fail; + /* + * There are two modes PDC irqchip can work in + * - pass through mode + * - secondary controller mode + * + * All PDC irqchip supports pass through mode in which both + * Direct SPIs and GPIO IRQs (as SPIs) are sent to GIC + * without latching at PDC. + * + * Newer PDCs (v3.0 onwards) also support additional + * secondary controller mode where PDC latches GPIO IRQs + * and sends to GIC as level type IRQ. Direct SPIs still + * works same as pass through mode without latching at PDC + * even in secondary controller mode. + * + * All the SoCs so far default uses pass through mode with + * the exception of x1e. + * + * x1e modes: + * + * x1e PDC may be set to secondary controller mode for + * builds on CRD boards whereas it may be set to pass + * through mode for IoT-EVK boards. + * + * There is no way to read which current mode it is set to + * and make PDC work in respective mode as the read access + * is not opened up for non secure world. There is though + * write access opened up via SCM write API to set the mode. + * + * Configure PDC mode to pass through mode for all x1e based + * boards. + * + * For successful write: + * - Nothing more to be done + * + * For unsuccessful write: + * - Inform TLMM to monitor GPIO IRQs (same as MPM) + * - Prevent SoC low power mode (CxPC) as PDC is not + * monitoring GPIO IRQs which may be needed to wake + * the SoC from low power mode. + */ + ret = of_address_to_resource(node, 2, &res); + if (ret) { + domain_flag = IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP; + goto skip_scm_write; + } + + ret = qcom_scm_io_writel(res.start, PDC_PASS_THROUGH_MODE); + if (ret) { + pdc_qmp = qmp_get(&pdev->dev); + if (IS_ERR(pdc_qmp)) { + ret = PTR_ERR(pdc_qmp); + goto fail; + } else { + ret = qmp_send(pdc_qmp, buf, sizeof(buf)); + qmp_put(pdc_qmp); + if (ret) + goto fail; + } + domain_flag = IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP; + } } +skip_scm_write: pdc_version = pdc_reg_read(PDC_VERSION_REG, 0); parent_domain = irq_find_host(parent); @@ -407,7 +508,7 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare } pdc_domain = irq_domain_create_hierarchy(parent_domain, - IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, + domain_flag, PDC_MAX_GPIO_IRQS, of_fwnode_handle(node), &qcom_pdc_ops, NULL); From 048ce542081f2df4e202927db3400dc503f01883 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 31 Dec 2025 15:48:45 +0530 Subject: [PATCH 0550/1330] FROMLIST: dt-bindings: interrupt-controller: qcom,pdc: Document x1p42100 PDC Purwa shares the Hamoa (X1E80100) PDC device, but the hardware register bug addressed in commit e9a48ea4d90b ("irqchip/qcom-pdc: Workaround hardware register bug on X1E80100") is already fixed in Purwa silicon. Hamoa compatible forces the software workaround. Add PDC compatible for purwa as "qcom,x1p42100-pdc" to remove the workaround from Purwa. Fixes: f08edb529916 ("arm64: dts: qcom: Add X1P42100 SoC and CRD") Link: https://lore.kernel.org/r/20251231-purwa_pdc-v1-1-2b4979dd88ad@oss.qualcomm.com Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 9e07a9b5f456d..5d1cdd322c9a8 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -54,6 +54,7 @@ properties: - qcom,sm8650-pdc - qcom,sm8750-pdc - qcom,x1e80100-pdc + - qcom,x1p42100-pdc - const: qcom,pdc reg: From 119fc4345f31ba548018e9d9645e36d0f9b048e3 Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Sun, 29 Mar 2026 23:22:47 +0530 Subject: [PATCH 0551/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC Add the base USB devicetree definitions for Kaanapali platform. The overall chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY (rev. v8) and M31 eUSB2 PHY. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/all/20260329175249.2946508-2-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 154 ++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index c129896f8daa7..9e335b615110f 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -6096,6 +6096,160 @@ reg = <0x100 0x80>; }; }; + + usb_hsphy: phy@88e3000 { + compatible = "qcom,kaanapali-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x88e3000 0x0 0x29c>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,kaanapali-qmp-usb3-dp-phy", + "qcom,sm8750-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb: usb@a600000 { + compatible = "qcom,kaanapali-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + iommus = <&apps_smmu 0x40 0x0>; + + phys = <&usb_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + dma-coherent; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; }; thermal-zones { From 5f47df246b1c932da144e40a974d0eb180f311c3 Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Sun, 29 Mar 2026 23:22:48 +0530 Subject: [PATCH 0552/1330] FROMLIST: arm64: dts: qcom: kaanpaali: Add USB support for MTP platform Enable USB support on Kaanapali MTP variant. Enable USB controller in device mode till glink node is added. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/all/20260329175249.2946508-3-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 07247dc98b701..c0e2f2be6a0df 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -82,6 +82,11 @@ }; }; + pmih0108_e1_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; + }; + sound { compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard"; model = "Kaanapali-MTP"; @@ -1321,3 +1326,25 @@ status = "okay"; }; + +&usb { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l4f_0p8>; + vdda12-supply = <&vreg_l1d_1p2>; + + phys = <&pmih0108_e1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l1d_1p2>; + vdda-pll-supply = <&vreg_l4f_0p8>; + + status = "okay"; +}; From 4697e02e5288fcafad12cffa4aa950fa1453015c Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Sun, 29 Mar 2026 23:22:49 +0530 Subject: [PATCH 0553/1330] FROMLIST: arm64: dts: qcom: kaanpaali: Add USB support for QRD platform Enable USB support on Kaanapali QRD variant. Enable USB controller in device mode till glink node is added. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/all/20260329175249.2946508-4-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index da0e8f9091c36..4916d2f3be3ed 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -80,6 +80,11 @@ wakeup-source; }; }; + + pmih0108_e1_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; + }; }; &apps_rsc { @@ -816,3 +821,25 @@ status = "okay"; }; + +&usb { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l4f_0p8>; + vdda12-supply = <&vreg_l1d_1p2>; + + phys = <&pmih0108_e1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l1d_1p2>; + vdda-pll-supply = <&vreg_l4f_0p8>; + + status = "okay"; +}; From 8a76a96a91aa070bb4e66096ab6d77d426fa9e79 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 24 Mar 2026 18:43:18 +0530 Subject: [PATCH 0554/1330] FROMLIST: spi: dt-bindings: qcom-qspi: Add QCS615 compatible Add the "qcom,qcs615-qspi" compatible string to the Qualcomm QSPI device- tree binding to enable QCS615-based platforms to use the existing QSPI controller binding. Link: https://patch.msgid.link/20260324-spi-nor-v1-1-3efe59c1c119@oss.qualcomm.com Signed-off-by: Viken Dadhaniya --- Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml index 1696ac46a660e..d9aac33b695bf 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml @@ -20,6 +20,7 @@ properties: compatible: items: - enum: + - qcom,qcs615-qspi - qcom,sc7180-qspi - qcom,sc7280-qspi - qcom,sdm845-qspi From e837c7870682b913dd969cfd6608b15086757e59 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 24 Mar 2026 18:43:19 +0530 Subject: [PATCH 0555/1330] FROMLIST: spi: spi-qcom-qspi: Add interconnect support for memory path The QSPI controller has two interconnect paths: 1. qspi-config: CPU to QSPI controller for register access 2. qspi-memory: QSPI controller to memory for DMA operations Currently, the driver only manages the qspi-config path. Add support for the qspi-memory path to ensure proper bandwidth allocation for QSPI data transfers to/from memory. Enable and disable both paths during runtime PM transitions. Link: https://patch.msgid.link/20260324-spi-nor-v1-2-3efe59c1c119@oss.qualcomm.com Signed-off-by: Viken Dadhaniya --- drivers/spi/spi-qcom-qspi.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index 7e39038160e00..624b3a7b62914 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -174,6 +174,7 @@ struct qcom_qspi { void *virt_cmd_desc[QSPI_MAX_SG]; unsigned int n_cmd_desc; struct icc_path *icc_path_cpu_to_qspi; + struct icc_path *icc_path_mem; unsigned long last_speed; /* Lock to protect data accessed by IRQs */ spinlock_t lock; @@ -272,7 +273,7 @@ static void qcom_qspi_handle_err(struct spi_controller *host, static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz) { int ret; - unsigned int avg_bw_cpu; + unsigned int avg_bw_cpu, avg_bw_mem; if (speed_hz == ctrl->last_speed) return 0; @@ -285,7 +286,7 @@ static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz) } /* - * Set BW quota for CPU. + * Set BW quota for CPU and memory paths. * We don't have explicit peak requirement so keep it equal to avg_bw. */ avg_bw_cpu = Bps_to_icc(speed_hz); @@ -296,6 +297,13 @@ static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz) return ret; } + avg_bw_mem = Bps_to_icc(speed_hz); + ret = icc_set_bw(ctrl->icc_path_mem, avg_bw_mem, avg_bw_mem); + if (ret) { + dev_err(ctrl->dev, "ICC BW voting failed for memory: %d\n", ret); + return ret; + } + ctrl->last_speed = speed_hz; return 0; @@ -729,6 +737,11 @@ static int qcom_qspi_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(ctrl->icc_path_cpu_to_qspi), "Failed to get cpu path\n"); + ctrl->icc_path_mem = devm_of_icc_get(dev, "qspi-memory"); + if (IS_ERR(ctrl->icc_path_mem)) + return dev_err_probe(dev, PTR_ERR(ctrl->icc_path_mem), + "Failed to get memory path\n"); + /* Set BW vote for register access */ ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, Bps_to_icc(1000), Bps_to_icc(1000)); @@ -829,6 +842,13 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev) return ret; } + ret = icc_disable(ctrl->icc_path_mem); + if (ret) { + dev_err_ratelimited(ctrl->dev, "ICC disable failed for memory: %d\n", ret); + icc_enable(ctrl->icc_path_cpu_to_qspi); + return ret; + } + pinctrl_pm_select_sleep_state(dev); return 0; @@ -849,9 +869,19 @@ static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev) return ret; } + ret = icc_enable(ctrl->icc_path_mem); + if (ret) { + dev_err_ratelimited(ctrl->dev, "ICC enable failed for memory: %d\n", ret); + icc_disable(ctrl->icc_path_cpu_to_qspi); + return ret; + } + ret = clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks); - if (ret) + if (ret) { + icc_disable(ctrl->icc_path_cpu_to_qspi); + icc_disable(ctrl->icc_path_mem); return ret; + } return dev_pm_opp_set_rate(dev, ctrl->last_speed * 4); } From f042bdea0687e11b7c13d9f1ac7b2babe650ac5a Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 12 Mar 2026 21:26:39 +0530 Subject: [PATCH 0556/1330] FROMLIST: Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now" This reverts commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"). PDC interrupts no more break GPIOs. PDC is now set to pass through mode which allows GPIO interrupts to setup as wakeup capable at PDC and pass them to GIC as SPIs. Update nwakeirq_map to reflect the GPIO to PDC irq map size. Link: https://lore.kernel.org/r/20260312-hamoa_pdc-v1-5-760c8593ce50@oss.qualcomm.com Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad --- drivers/pinctrl/qcom/pinctrl-x1e80100.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index bb36f40b19fa5..04e08680f996b 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1839,9 +1839,7 @@ static const struct msm_pinctrl_soc_data x1e80100_pinctrl = { .ngroups = ARRAY_SIZE(x1e80100_groups), .ngpios = 239, .wakeirq_map = x1e80100_pdc_map, - /* TODO: Enabling PDC currently breaks GPIO interrupts */ - .nwakeirq_map = 0, - /* .nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map), */ + .nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map), .egpio_func = 9, }; From 739e2ed27030540959837c8eaec24037337ae015 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Thu, 2 Apr 2026 11:44:12 +0530 Subject: [PATCH 0557/1330] PENDING: media: iris: update MDT PAS load call for new API The Qualcomm MDT loader changed qcom_mdt_pas_load() to take only four arguments and use the PAS context for relocation and memory handling. Update the iris firmware loading path to match that interface by dropping the temporary memremap/memunmap flow, removing the extra mem_virt argument from qcom_mdt_pas_load(), and simplifying the error path accordingly. This keeps the iris driver aligned with the SCM/PAS loader changes and fixes the build failure caused by the old five-argument call. Signed-off-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_firmware.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index d74a5aed291d7..e19daf0c41262 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -29,7 +29,6 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) phys_addr_t mem_phys; size_t res_size; ssize_t fw_size; - void *mem_virt; int ret; if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4) @@ -60,22 +59,16 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) goto err_release_fw; } - mem_virt = memremap(mem_phys, res_size, MEMREMAP_WC); - if (!mem_virt) { - ret = -ENOMEM; - goto err_release_fw; - } - - ret = qcom_mdt_pas_load(ctx, firmware, fw_name, mem_virt, NULL); + ret = qcom_mdt_pas_load(ctx, firmware, fw_name, NULL); qcom_scm_pas_metadata_release(ctx); if (ret) - goto err_mem_unmap; + goto err_release_fw; if (core->fw.iommu_domain) { ret = iommu_map(core->fw.iommu_domain, 0, mem_phys, res_size, IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); if (ret) - goto err_mem_unmap; + goto err_release_fw; } ret = qcom_scm_pas_prepare_and_auth_reset(ctx); @@ -88,8 +81,6 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) err_iommu_unmap: iommu_unmap(core->fw.iommu_domain, 0, res_size); -err_mem_unmap: - memunmap(mem_virt); err_release_fw: release_firmware(firmware); From 18bf2d1a8c9b1e48ec89e334462c1ba543c9a920 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Fri, 3 Apr 2026 11:39:57 +0530 Subject: [PATCH 0558/1330] Add qcom-next log files for 20260403 Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud --- qcom-next/merge.log | 459 +++++++++++++++++++++++++++++++++++++++++++ qcom-next/topic_SHA1 | 51 +++++ 2 files changed, 510 insertions(+) create mode 100644 qcom-next/merge.log create mode 100644 qcom-next/topic_SHA1 diff --git a/qcom-next/merge.log b/qcom-next/merge.log new file mode 100644 index 0000000000000..16473635eb8f1 --- /dev/null +++ b/qcom-next/merge.log @@ -0,0 +1,459 @@ +Verified existence of local and remote repos: Success +/local/mnt/workspace/automerge/actions-runner/_work/kernel-automation/kernel-automation/kernel-topics /local/mnt/workspace/automerge/actions-runner/_work/kernel-automation/kernel-automation/kernel-topics +Reuse-Recorded-Resolution: Enabled +Downloaded shared rerere cache +Local tree is clean +Removing old remotes ... +The remote kernel https://github.com/qualcomm-linux/kernel.git is no longer tracked. +Delete it [Y/n]? The remote origin https://github.com/qualcomm-linux/kernel-topics.git is no longer tracked. +Delete it [Y/n]? The remote trovalds https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git is no longer tracked. +Delete it [Y/n]? Done, removed 3 old remote(s). +Adding new remotes... +Adding remote baseline https://github.com/qualcomm-linux/kernel.git qcom-next-staging +Updating baseline +Adding remote tech/bsp/clk https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/clk +Updating tech/bsp/clk +Adding remote tech/bsp/interconnect https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/interconnect +Updating tech/bsp/interconnect +Adding remote tech/mem/secure-buffer https://github.com/qualcomm-linux/kernel-topics.git tech/mem/secure-buffer +Updating tech/mem/secure-buffer +Adding remote tech/security/firmware-smc https://github.com/qualcomm-linux/kernel-topics.git tech/security/firmware-smc +Updating tech/security/firmware-smc +Adding remote tech/bsp/soc-infra https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/soc-infra +Updating tech/bsp/soc-infra +Adding remote tech/debug/soc https://github.com/qualcomm-linux/kernel-topics.git tech/debug/soc +Updating tech/debug/soc +Adding remote tech/bsp/pinctrl https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/pinctrl +Updating tech/bsp/pinctrl +Adding remote tech/bsp/remoteproc https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/remoteproc +Updating tech/bsp/remoteproc +Adding remote tech/bus/peripherals https://github.com/qualcomm-linux/kernel-topics.git tech/bus/peripherals +Updating tech/bus/peripherals +Adding remote tech/bus/pci/all https://github.com/qualcomm-linux/kernel-topics.git tech/bus/pci/all +Updating tech/bus/pci/all +Adding remote tech/bus/pci/mhi https://github.com/qualcomm-linux/kernel-topics.git tech/bus/pci/mhi +Updating tech/bus/pci/mhi +Adding remote tech/bus/pci/phy https://github.com/qualcomm-linux/kernel-topics.git tech/bus/pci/phy +Updating tech/bus/pci/phy +Adding remote tech/bus/pci/pwrctl https://github.com/qualcomm-linux/kernel-topics.git tech/bus/pci/pwrctl +Updating tech/bus/pci/pwrctl +Adding remote tech/bus/usb/dwc https://github.com/qualcomm-linux/kernel-topics.git tech/bus/usb/dwc +Updating tech/bus/usb/dwc +Adding remote tech/bus/usb/gadget https://github.com/qualcomm-linux/kernel-topics.git tech/bus/usb/gadget +Updating tech/bus/usb/gadget +Adding remote tech/bus/usb/phy https://github.com/qualcomm-linux/kernel-topics.git tech/bus/usb/phy +Updating tech/bus/usb/phy +Adding remote tech/debug/eud https://github.com/qualcomm-linux/kernel-topics.git tech/debug/eud +Updating tech/debug/eud +Adding remote tech/debug/hwtracing https://github.com/qualcomm-linux/kernel-topics.git tech/debug/hwtracing +Updating tech/debug/hwtracing +Adding remote tech/debug/rdbg https://github.com/qualcomm-linux/kernel-topics.git tech/debug/rdbg +Updating tech/debug/rdbg +Adding remote tech/pmic/backlight https://github.com/qualcomm-linux/kernel-topics.git tech/pmic/backlight +Updating tech/pmic/backlight +Adding remote tech/pmic/mfd https://github.com/qualcomm-linux/kernel-topics.git tech/pmic/mfd +Updating tech/pmic/mfd +Adding remote tech/pmic/misc https://github.com/qualcomm-linux/kernel-topics.git tech/pmic/misc +Updating tech/pmic/misc +Adding remote tech/pmic/regulator https://github.com/qualcomm-linux/kernel-topics.git tech/pmic/regulator +Updating tech/pmic/regulator +Adding remote tech/pmic/supply https://github.com/qualcomm-linux/kernel-topics.git tech/pmic/supply +Updating tech/pmic/supply +Adding remote tech/mem/dma-buf https://github.com/qualcomm-linux/kernel-topics.git tech/mem/dma-buf +Updating tech/mem/dma-buf +Adding remote tech/mem/iommu https://github.com/qualcomm-linux/kernel-topics.git tech/mem/iommu +Updating tech/mem/iommu +Adding remote tech/mm/audio/all https://github.com/qualcomm-linux/kernel-topics.git tech/mm/audio/all +Updating tech/mm/audio/all +Adding remote tech/mm/audio/soundwire https://github.com/qualcomm-linux/kernel-topics.git tech/mm/audio/soundwire +Updating tech/mm/audio/soundwire +Adding remote tech/mm/camss https://github.com/qualcomm-linux/kernel-topics.git tech/mm/camss +Updating tech/mm/camss +Adding remote tech/mm/drm https://github.com/qualcomm-linux/kernel-topics.git tech/mm/drm +Updating tech/mm/drm +Adding remote tech/mm/fastrpc https://github.com/qualcomm-linux/kernel-topics.git tech/mm/fastrpc +Updating tech/mm/fastrpc +Adding remote tech/mm/phy https://github.com/qualcomm-linux/kernel-topics.git tech/mm/phy +Updating tech/mm/phy +Adding remote tech/mm/video https://github.com/qualcomm-linux/kernel-topics.git tech/mm/video +Updating tech/mm/video +Adding remote tech/mm/gpu https://github.com/qualcomm-linux/kernel-topics.git tech/mm/gpu +Updating tech/mm/gpu +Adding remote tech/mproc/rpmsg https://github.com/qualcomm-linux/kernel-topics.git tech/mproc/rpmsg +Updating tech/mproc/rpmsg +Adding remote tech/mproc/qmi https://github.com/qualcomm-linux/kernel-topics.git tech/mproc/qmi +Updating tech/mproc/qmi +Adding remote tech/net/ath https://github.com/qualcomm-linux/kernel-topics.git tech/net/ath +Updating tech/net/ath +Adding remote tech/net/eth https://github.com/qualcomm-linux/kernel-topics.git tech/net/eth +Updating tech/net/eth +Adding remote tech/net/rmnet https://github.com/qualcomm-linux/kernel-topics.git tech/net/rmnet +Updating tech/net/rmnet +Adding remote tech/net/qrtr https://github.com/qualcomm-linux/kernel-topics.git tech/net/qrtr +Updating tech/net/qrtr +Adding remote tech/net/phy https://github.com/qualcomm-linux/kernel-topics.git tech/net/phy +Updating tech/net/phy +Adding remote tech/net/bluetooth https://github.com/qualcomm-linux/kernel-topics.git tech/net/bluetooth +Updating tech/net/bluetooth +Adding remote tech/pm/opp https://github.com/qualcomm-linux/kernel-topics.git tech/pm/opp +Updating tech/pm/opp +Adding remote tech/pm/pmdomain https://github.com/qualcomm-linux/kernel-topics.git tech/pm/pmdomain +Updating tech/pm/pmdomain +Adding remote tech/pm/power https://github.com/qualcomm-linux/kernel-topics.git tech/pm/power +Updating tech/pm/power +Adding remote tech/pm/thermal https://github.com/qualcomm-linux/kernel-topics.git tech/pm/thermal +Updating tech/pm/thermal +Adding remote tech/security/crypto https://github.com/qualcomm-linux/kernel-topics.git tech/security/crypto +Updating tech/security/crypto +Adding remote tech/security/fscrypt https://github.com/qualcomm-linux/kernel-topics.git tech/security/fscrypt +Updating tech/security/fscrypt +Adding remote tech/security/ice https://github.com/qualcomm-linux/kernel-topics.git tech/security/ice +Updating tech/security/ice +Adding remote tech/storage/nvmem https://github.com/qualcomm-linux/kernel-topics.git tech/storage/nvmem +Updating tech/storage/nvmem +Adding remote tech/storage/phy https://github.com/qualcomm-linux/kernel-topics.git tech/storage/phy +Updating tech/storage/phy +Adding remote tech/storage/all https://github.com/qualcomm-linux/kernel-topics.git tech/storage/all +Updating tech/storage/all +Adding remote tech/virt/gunyah https://github.com/qualcomm-linux/kernel-topics.git tech/virt/gunyah +Updating tech/virt/gunyah +Adding remote tech/all/dt/qcs6490 https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/qcs6490 +Updating tech/all/dt/qcs6490 +Adding remote tech/all/dt/qcs9100 https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/qcs9100 +Updating tech/all/dt/qcs9100 +Adding remote tech/all/dt/qcs8300 https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/qcs8300 +Updating tech/all/dt/qcs8300 +Adding remote tech/all/dt/qcs615 https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/qcs615 +Updating tech/all/dt/qcs615 +Adding remote tech/all/dt/agatti https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/agatti +Updating tech/all/dt/agatti +Adding remote tech/all/dt/hamoa https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/hamoa +Updating tech/all/dt/hamoa +Adding remote tech/all/dt/glymur https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/glymur +Updating tech/all/dt/glymur +Adding remote tech/all/dt/kaanapali https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/kaanapali +Updating tech/all/dt/kaanapali +Adding remote tech/all/dt/pakala https://github.com/qualcomm-linux/kernel-topics.git tech/all/dt/pakala +Updating tech/all/dt/pakala +Adding remote tech/all/config https://github.com/qualcomm-linux/kernel-topics.git tech/all/config +Updating tech/all/config +Adding remote tech/overlay/dt https://github.com/qualcomm-linux/kernel-topics.git tech/overlay/dt +Updating tech/overlay/dt +Adding remote tech/all/workaround https://github.com/qualcomm-linux/kernel-topics.git tech/all/workaround +Updating tech/all/workaround +Adding remote tech/mproc/all https://github.com/qualcomm-linux/kernel-topics.git tech/mproc/all +Updating tech/mproc/all +Adding remote tech/noup/debug/all https://github.com/qualcomm-linux/kernel-topics.git tech/noup/debug/all +Updating tech/noup/debug/all +Adding remote tech/hwe/unoq https://github.com/qualcomm-linux/kernel-topics.git tech/hwe/unoq +Updating tech/hwe/unoq +Adding remote early/hwe/shikra/drivers https://github.com/qualcomm-linux/kernel-topics.git early/hwe/shikra/drivers +Updating early/hwe/shikra/drivers +Adding remote early/hwe/shikra/dt https://github.com/qualcomm-linux/kernel-topics.git early/hwe/shikra/dt +Updating early/hwe/shikra/dt +Done, added 71 new remote(s). +Updating the remotes ... +Updating tech/bsp/clk +Updating tech/bsp/interconnect +Updating tech/mem/secure-buffer +Updating tech/security/firmware-smc +Updating tech/bsp/soc-infra +Updating tech/debug/soc +Updating tech/bsp/pinctrl +Updating tech/bsp/remoteproc +Updating tech/bus/peripherals +Updating tech/bus/pci/all +Updating tech/bus/pci/mhi +Updating tech/bus/pci/phy +Updating tech/bus/pci/pwrctl +Updating tech/bus/usb/dwc +Updating tech/bus/usb/gadget +Updating tech/bus/usb/phy +Updating tech/debug/eud +Updating tech/debug/hwtracing +Updating tech/debug/rdbg +Updating tech/pmic/backlight +Updating tech/pmic/mfd +Updating tech/pmic/misc +Updating tech/pmic/regulator +Updating tech/pmic/supply +Updating tech/mem/dma-buf +Updating tech/mem/iommu +Updating tech/mm/audio/all +Updating tech/mm/audio/soundwire +Updating tech/mm/camss +Updating tech/mm/drm +Updating tech/mm/fastrpc +Updating tech/mm/phy +Updating tech/mm/video +Updating tech/mm/gpu +Updating tech/mproc/rpmsg +Updating tech/mproc/qmi +Updating tech/net/ath +Updating tech/net/eth +Updating tech/net/rmnet +Updating tech/net/qrtr +Updating tech/net/phy +Updating tech/net/bluetooth +Updating tech/pm/opp +Updating tech/pm/pmdomain +Updating tech/pm/power +Updating tech/pm/thermal +Updating tech/security/crypto +Updating tech/security/fscrypt +Updating tech/security/ice +Updating tech/storage/nvmem +Updating tech/storage/phy +Updating tech/storage/all +Updating tech/virt/gunyah +Updating tech/all/dt/qcs6490 +Updating tech/all/dt/qcs9100 +Updating tech/all/dt/qcs8300 +Updating tech/all/dt/qcs615 +Updating tech/all/dt/agatti +Updating tech/all/dt/hamoa +Updating tech/all/dt/glymur +Updating tech/all/dt/kaanapali +Updating tech/all/dt/pakala +Updating tech/all/config +Updating tech/overlay/dt +Updating tech/all/workaround +Updating tech/mproc/all +Updating tech/noup/debug/all +Updating tech/hwe/unoq +Updating early/hwe/shikra/drivers +Updating early/hwe/shikra/dt +Done, updated 0 remote(s). +Updating baseline ... +Fetching baseline +latest tag/id is 7aaa8047eafd0bd628065b15757d9b48c5f9c07d +Done, updated baseline. +Latest tag is 7aaa8047eafd0bd628065b15757d9b48c5f9c07d +Create a new integration branch based on 7aaa8047eafd0bd628065b15757d9b48c5f9c07d +Merging topic branches... +------------------------------------------ + ** Merging topic branch: tech/bsp/clk/tech/bsp/clk +Merge successful : tech/bsp/clk : 90af1d3e6dede77b7c2eb4aa2ee56677023aedb3 : 12 +------------------------------------------ + ** Merging topic branch: tech/bsp/interconnect/tech/bsp/interconnect +Merge successful : tech/bsp/interconnect : 7d3a72c70998b3a0c25928ab7e61b4231467700d : 5 +------------------------------------------ + ** Merging topic branch: tech/mem/secure-buffer/tech/mem/secure-buffer +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/security/firmware-smc/tech/security/firmware-smc +Merge successful : tech/security/firmware-smc : a50984a91bb9d551ee48136ee2db90eca0929979 : 2 +------------------------------------------ + ** Merging topic branch: tech/bsp/soc-infra/tech/bsp/soc-infra +Merge successful : tech/bsp/soc-infra : c793ce5e280bffeca61ab6cdf9ef058c3ad92a99 : 5 +------------------------------------------ + ** Merging topic branch: tech/debug/soc/tech/debug/soc +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/bsp/pinctrl/tech/bsp/pinctrl +Merge successful : tech/bsp/pinctrl : 28c2b80824ce68f269fd85b0308df499bca9181d : 1 +------------------------------------------ + ** Merging topic branch: tech/bsp/remoteproc/tech/bsp/remoteproc +Merge successful : tech/bsp/remoteproc : abb91aeb56bf212aa9f8a0929bc728237e685d56 : 5 +------------------------------------------ + ** Merging topic branch: tech/bus/peripherals/tech/bus/peripherals +Merge successful : tech/bus/peripherals : 8c19ed7289a5e75d811af1ab68c79a971b18a554 : 2 +------------------------------------------ + ** Merging topic branch: tech/bus/pci/all/tech/bus/pci/all +Merge successful : tech/bus/pci/all : 6a697f861422a7e8a1e0e189455baffdad08a9c1 : 6 +------------------------------------------ + ** Merging topic branch: tech/bus/pci/mhi/tech/bus/pci/mhi +Merge successful : tech/bus/pci/mhi : fb9c1632f424ecdcd7fef1205499a1b64d477cdc : 1 +------------------------------------------ + ** Merging topic branch: tech/bus/pci/phy/tech/bus/pci/phy +Merge failed, manual merge +No files need merging +[qcom-next 98edf480f0e9] Merge remote-tracking branch tech/bus/pci/phy into qcom-next +Merge successful : tech/bus/pci/phy : aaf8ef1234f456bd05343c235d7ad0b921a97220 : 4 +------------------------------------------ + ** Merging topic branch: tech/bus/pci/pwrctl/tech/bus/pci/pwrctl +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/bus/usb/dwc/tech/bus/usb/dwc +Merge successful : tech/bus/usb/dwc : 49ac8e0eb9656bdaa63dfa8431879f8fe6798742 : 2 +------------------------------------------ + ** Merging topic branch: tech/bus/usb/gadget/tech/bus/usb/gadget +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/bus/usb/phy/tech/bus/usb/phy +Merge successful : tech/bus/usb/phy : 8c7f91d8f5390117341ccedf03dbca8620e1fede : 35 +------------------------------------------ + ** Merging topic branch: tech/debug/eud/tech/debug/eud +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/debug/hwtracing/tech/debug/hwtracing +Merge successful : tech/debug/hwtracing : 87ae82d339bfcb4af6216f36d831240b42fe8d73 : 31 +------------------------------------------ + ** Merging topic branch: tech/debug/rdbg/tech/debug/rdbg +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/pmic/backlight/tech/pmic/backlight +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/pmic/mfd/tech/pmic/mfd +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/pmic/misc/tech/pmic/misc +Merge successful : tech/pmic/misc : e6525e383cf7a4fe2a6f0b5713045620ef6a9b91 : 9 +------------------------------------------ + ** Merging topic branch: tech/pmic/regulator/tech/pmic/regulator +Merge successful : tech/pmic/regulator : 81fc8fbf0f0a02a7b2d855aee574b88bd7d59107 : 6 +------------------------------------------ + ** Merging topic branch: tech/pmic/supply/tech/pmic/supply +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/mem/dma-buf/tech/mem/dma-buf +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/mem/iommu/tech/mem/iommu +Merge successful : tech/mem/iommu : 43dfdd1471b043f0b8240f9bc79b03f9fe63e598 : 4 +------------------------------------------ + ** Merging topic branch: tech/mm/audio/all/tech/mm/audio/all +Merge successful : tech/mm/audio/all : d38b67b0aa386ae60c62d75dd3a5d2ea06ddeb62 : 14 +------------------------------------------ + ** Merging topic branch: tech/mm/audio/soundwire/tech/mm/audio/soundwire +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/mm/camss/tech/mm/camss +Merge successful : tech/mm/camss : ef80fadce4f21a59dc47963b82dd837fbaf27566 : 20 +------------------------------------------ + ** Merging topic branch: tech/mm/drm/tech/mm/drm +Merge successful : tech/mm/drm : b17e72357fffb70eaa2577edada34e30557208ee : 12 +------------------------------------------ + ** Merging topic branch: tech/mm/fastrpc/tech/mm/fastrpc +Merge successful : tech/mm/fastrpc : c29b2a8795e0f64836ca9314837d167013d0699e : 5 +------------------------------------------ + ** Merging topic branch: tech/mm/phy/tech/mm/phy +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/mm/video/tech/mm/video +Merge successful : tech/mm/video : fa0e48250f91c77370e01fec89db5539ee3401ca : 4 +------------------------------------------ + ** Merging topic branch: tech/mm/gpu/tech/mm/gpu +Merge successful : tech/mm/gpu : 9c8e55ded527bf43ab608810515b6c74e251b99f : 2 +------------------------------------------ + ** Merging topic branch: tech/mproc/rpmsg/tech/mproc/rpmsg +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/mproc/qmi/tech/mproc/qmi +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/net/ath/tech/net/ath +Merge successful : tech/net/ath : f8562ba7c0e1a81bdf56a29fe0caf2fee6c301fe : 2 +------------------------------------------ + ** Merging topic branch: tech/net/eth/tech/net/eth +Merge successful : tech/net/eth : 49b156fb09e0950aab5d3b4d6f1a92a3a78766d1 : 1 +------------------------------------------ + ** Merging topic branch: tech/net/rmnet/tech/net/rmnet +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/net/qrtr/tech/net/qrtr +Merge successful : tech/net/qrtr : 64d75f7e2a793b65d86fd9b35f8d4c40595ba799 : 1 +------------------------------------------ + ** Merging topic branch: tech/net/phy/tech/net/phy +Merge successful : tech/net/phy : a3602e9cbd3dd4519ddc446ddba1261fe4e156bd : 1 +------------------------------------------ + ** Merging topic branch: tech/net/bluetooth/tech/net/bluetooth +Merge successful : tech/net/bluetooth : 229e73eda5f991c40b55c97150f2547433b083f2 : 3 +------------------------------------------ + ** Merging topic branch: tech/pm/opp/tech/pm/opp +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/pm/pmdomain/tech/pm/pmdomain +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/pm/power/tech/pm/power +Merge successful : tech/pm/power : 25fc1b70fb8b9e86cabdb3f633590a5469e72756 : 9 +------------------------------------------ + ** Merging topic branch: tech/pm/thermal/tech/pm/thermal +Merge successful : tech/pm/thermal : d174ed3bbac5d6ab7ba02a96b0356ea6e57935f8 : 6 +------------------------------------------ + ** Merging topic branch: tech/security/crypto/tech/security/crypto +Merge successful : tech/security/crypto : a6ce790e0668cc6f98549c390017c5d1be5d983d : 12 +------------------------------------------ + ** Merging topic branch: tech/security/fscrypt/tech/security/fscrypt +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/security/ice/tech/security/ice +Merge successful : tech/security/ice : 5184a0ec45bba44504d3f09f49cb25142f988403 : 15 +------------------------------------------ + ** Merging topic branch: tech/storage/nvmem/tech/storage/nvmem +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/storage/phy/tech/storage/phy +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/storage/all/tech/storage/all +Merge successful : tech/storage/all : e254daed78f7b24bf852df097b78455ca142666a : 1 +------------------------------------------ + ** Merging topic branch: tech/virt/gunyah/tech/virt/gunyah +Nothing to merge: Already up to date. +------------------------------------------ + ** Merging topic branch: tech/all/dt/qcs6490/tech/all/dt/qcs6490 +Merge successful : tech/all/dt/qcs6490 : 5fb16ec0d2e8ab7658e147729274e6ea6f29494b : 16 +------------------------------------------ + ** Merging topic branch: tech/all/dt/qcs9100/tech/all/dt/qcs9100 +Merge successful : tech/all/dt/qcs9100 : 5586aacbb055f02fa9989c1c3b587ec7e13d3b82 : 19 +------------------------------------------ + ** Merging topic branch: tech/all/dt/qcs8300/tech/all/dt/qcs8300 +Merge successful : tech/all/dt/qcs8300 : 37ae3467288572b7c48fe9e4f1761c8669f68639 : 21 +------------------------------------------ + ** Merging topic branch: tech/all/dt/qcs615/tech/all/dt/qcs615 +Merge successful : tech/all/dt/qcs615 : 367314f4728d5949e932dad7ca5dbc27d66844a0 : 27 +------------------------------------------ + ** Merging topic branch: tech/all/dt/agatti/tech/all/dt/agatti +Merge successful : tech/all/dt/agatti : c828f10cd2c53b7ff2cc061e73b239973ee17bc6 : 1 +------------------------------------------ + ** Merging topic branch: tech/all/dt/hamoa/tech/all/dt/hamoa +Merge successful : tech/all/dt/hamoa : 49fad942ea2e8cb32ae046842a58fdec0577b714 : 32 +------------------------------------------ + ** Merging topic branch: tech/all/dt/glymur/tech/all/dt/glymur +Merge successful : tech/all/dt/glymur : 3aa6f058d95da70702d42a820eba09bbc6b95050 : 23 +------------------------------------------ + ** Merging topic branch: tech/all/dt/kaanapali/tech/all/dt/kaanapali +Merge successful : tech/all/dt/kaanapali : 70486f23c076015ff1cee6616beb776b564cf529 : 23 +------------------------------------------ + ** Merging topic branch: tech/all/dt/pakala/tech/all/dt/pakala +Merge successful : tech/all/dt/pakala : 86103bc08e13ed2feea53df030b7410456d0f69b : 6 +------------------------------------------ + ** Merging topic branch: tech/all/config/tech/all/config +Merge successful : tech/all/config : 9050b95eabc118e790acfe2f77dfece9beef819a : 53 +------------------------------------------ + ** Merging topic branch: tech/overlay/dt/tech/overlay/dt +Merge failed, manual merge +No files need merging +[qcom-next 2003a1c586be] Merge remote-tracking branch tech/overlay/dt into qcom-next +Merge successful : tech/overlay/dt : bbed7cfb3264aadc265375d97a95316c703ecb0f : 24 +------------------------------------------ + ** Merging topic branch: tech/all/workaround/tech/all/workaround +Merge failed, manual merge +No files need merging +[qcom-next 10f0a2f6dae8] Merge remote-tracking branch tech/all/workaround into qcom-next +Merge successful : tech/all/workaround : c3f9d3b06c59cdca5219c05d5d313fb780541114 : 13 +------------------------------------------ + ** Merging topic branch: tech/mproc/all/tech/mproc/all +Merge successful : tech/mproc/all : eabd91e71290eab8529edcb342f0bccd7d94c08f : 4 +------------------------------------------ + ** Merging topic branch: tech/noup/debug/all/tech/noup/debug/all +Merge successful : tech/noup/debug/all : 342aeb8c5a4125bff7f8431acf4b6f8b73920dd9 : 15 +------------------------------------------ + ** Merging topic branch: tech/hwe/unoq/tech/hwe/unoq +Merge failed, manual merge +No files need merging +[qcom-next b0da29906863] Merge remote-tracking branch tech/hwe/unoq into qcom-next +Merge successful : tech/hwe/unoq : 7d981feccfaaddb1057ff650e656dcac4e76371b : 16 +------------------------------------------ + ** Merging topic branch: early/hwe/shikra/drivers/early/hwe/shikra/drivers +Merge successful : early/hwe/shikra/drivers : 347ed4487fd0ee0230e49b8d918481335843ba6c : 25 +------------------------------------------ + ** Merging topic branch: early/hwe/shikra/dt/early/hwe/shikra/dt +Merge successful : early/hwe/shikra/dt : 6ae20adae0cce5d240772fc24a45d01a4d6b7935 : 15 +Done, merged 49 topic(s). +[main c650a68] New rr-cache entries from ci-merge + 2 files changed, 5759 insertions(+), 8 deletions(-) + create mode 100644 rr-cache/99839c91a45bfcee801607737b8189856f3cb12e/thisimage.1 diff --git a/qcom-next/topic_SHA1 b/qcom-next/topic_SHA1 new file mode 100644 index 0000000000000..095e6e7adc297 --- /dev/null +++ b/qcom-next/topic_SHA1 @@ -0,0 +1,51 @@ +Name SHA Commits +------------------------------------------------------------------------------------ +tech/bsp/clk 90af1d3e6dede77b7c2eb4aa2ee56677023aedb3 12 +tech/bsp/interconnect 7d3a72c70998b3a0c25928ab7e61b4231467700d 5 +tech/security/firmware-smc a50984a91bb9d551ee48136ee2db90eca0929979 2 +tech/bsp/soc-infra c793ce5e280bffeca61ab6cdf9ef058c3ad92a99 5 +tech/bsp/pinctrl 28c2b80824ce68f269fd85b0308df499bca9181d 1 +tech/bsp/remoteproc abb91aeb56bf212aa9f8a0929bc728237e685d56 5 +tech/bus/peripherals 8c19ed7289a5e75d811af1ab68c79a971b18a554 2 +tech/bus/pci/all 6a697f861422a7e8a1e0e189455baffdad08a9c1 6 +tech/bus/pci/mhi fb9c1632f424ecdcd7fef1205499a1b64d477cdc 1 +tech/bus/pci/phy aaf8ef1234f456bd05343c235d7ad0b921a97220 4 +tech/bus/usb/dwc 49ac8e0eb9656bdaa63dfa8431879f8fe6798742 2 +tech/bus/usb/phy 8c7f91d8f5390117341ccedf03dbca8620e1fede 35 +tech/debug/hwtracing 87ae82d339bfcb4af6216f36d831240b42fe8d73 31 +tech/pmic/misc e6525e383cf7a4fe2a6f0b5713045620ef6a9b91 9 +tech/pmic/regulator 81fc8fbf0f0a02a7b2d855aee574b88bd7d59107 6 +tech/mem/iommu 43dfdd1471b043f0b8240f9bc79b03f9fe63e598 4 +tech/mm/audio/all d38b67b0aa386ae60c62d75dd3a5d2ea06ddeb62 14 +tech/mm/camss ef80fadce4f21a59dc47963b82dd837fbaf27566 20 +tech/mm/drm b17e72357fffb70eaa2577edada34e30557208ee 12 +tech/mm/fastrpc c29b2a8795e0f64836ca9314837d167013d0699e 5 +tech/mm/video fa0e48250f91c77370e01fec89db5539ee3401ca 4 +tech/mm/gpu 9c8e55ded527bf43ab608810515b6c74e251b99f 2 +tech/net/ath f8562ba7c0e1a81bdf56a29fe0caf2fee6c301fe 2 +tech/net/eth 49b156fb09e0950aab5d3b4d6f1a92a3a78766d1 1 +tech/net/qrtr 64d75f7e2a793b65d86fd9b35f8d4c40595ba799 1 +tech/net/phy a3602e9cbd3dd4519ddc446ddba1261fe4e156bd 1 +tech/net/bluetooth 229e73eda5f991c40b55c97150f2547433b083f2 3 +tech/pm/power 25fc1b70fb8b9e86cabdb3f633590a5469e72756 9 +tech/pm/thermal d174ed3bbac5d6ab7ba02a96b0356ea6e57935f8 6 +tech/security/crypto a6ce790e0668cc6f98549c390017c5d1be5d983d 12 +tech/security/ice 5184a0ec45bba44504d3f09f49cb25142f988403 15 +tech/storage/all e254daed78f7b24bf852df097b78455ca142666a 1 +tech/all/dt/qcs6490 5fb16ec0d2e8ab7658e147729274e6ea6f29494b 16 +tech/all/dt/qcs9100 5586aacbb055f02fa9989c1c3b587ec7e13d3b82 19 +tech/all/dt/qcs8300 37ae3467288572b7c48fe9e4f1761c8669f68639 21 +tech/all/dt/qcs615 367314f4728d5949e932dad7ca5dbc27d66844a0 27 +tech/all/dt/agatti c828f10cd2c53b7ff2cc061e73b239973ee17bc6 1 +tech/all/dt/hamoa 49fad942ea2e8cb32ae046842a58fdec0577b714 32 +tech/all/dt/glymur 3aa6f058d95da70702d42a820eba09bbc6b95050 23 +tech/all/dt/kaanapali 70486f23c076015ff1cee6616beb776b564cf529 23 +tech/all/dt/pakala 86103bc08e13ed2feea53df030b7410456d0f69b 6 +tech/all/config 9050b95eabc118e790acfe2f77dfece9beef819a 53 +tech/overlay/dt bbed7cfb3264aadc265375d97a95316c703ecb0f 24 +tech/all/workaround c3f9d3b06c59cdca5219c05d5d313fb780541114 13 +tech/mproc/all eabd91e71290eab8529edcb342f0bccd7d94c08f 4 +tech/noup/debug/all 342aeb8c5a4125bff7f8431acf4b6f8b73920dd9 15 +tech/hwe/unoq 7d981feccfaaddb1057ff650e656dcac4e76371b 16 +early/hwe/shikra/drivers 347ed4487fd0ee0230e49b8d918481335843ba6c 25 +early/hwe/shikra/dt 6ae20adae0cce5d240772fc24a45d01a4d6b7935 15 From 375d20b5eec987cae02d09c2e9beefcd20daad95 Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Wed, 8 Apr 2026 15:00:45 +0530 Subject: [PATCH 0559/1330] wifi: ath12k: fix context switch in panic notifier issue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Call Stack: Voluntary context switch within RCU read-side critical section! WARNING: kernel/rcu/tree_plugin.h:332 at rcu_note_context_switch+0x4c4/0x508, CPU#1: bash/817 CPU: 1 UID: 0 PID: 817 Comm: bash Tainted: G W 7.0.0-rc3 #1 PREEMPT Tainted: [W]=WARN Hardware name: Qualcomm Technologies, Inc. Hamoa IoT EVK (DT) pstate: 614000c5 (nZCv daIF +PAN -UAO -TCO +DIT -SSBS BTYPE=--) pc : rcu_note_context_switch+0x4c4/0x508 lr : rcu_note_context_switch+0x4c4/0x508 sp : ffff800085eeb7f0 x29: ffff800085eeb7f0 x28: ffff0008044fd640 x27: 0000000000000000 x26: 0000000000000000 x25: ffffd83dbc89c100 x24: ffff00081e668000 x23: 0000000000000000 x22: ffff0008044fd640 x21: ffffd83dbd9a6760 x20: 0000000000000000 x19: ffff008f386a2040 x18: 0000000000003fb8 x17: 2020202020202020 x16: ffffd83dbb6147b0 x15: 00000000000006a7 x14: 0000000000000001 x13: 00000000000006a6 x12: 00000000fffff6a5 x11: ffffd83dbd3b2a90 x10: ffffd83dbd414a88 x9 : ffffd83dbd3b2b10 x8 : ffffd83dbd40ab10 x7 : 0000000000003f70 x6 : 00000000000006a5 x5 : ffff008f3868d448 x4 : 80000000fffff6a5 x3 : ffff28517be05000 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0008044fd640 Call trace: rcu_note_context_switch+0x4c4/0x508 (P) __schedule+0xbc/0x1204 schedule+0x34/0x110 schedule_timeout+0x84/0x11c __mhi_device_get_sync+0x164/0x228 [mhi] mhi_device_get_sync+0x1c/0x3c [mhi] ath12k_wifi7_pci_bus_wake_up+0x20/0x2c [ath12k_wifi7] ath12k_pci_read32+0x58/0x350 [ath12k] ath12k_pci_clear_dbg_registers+0x28/0xb8 [ath12k] ath12k_pci_panic_handler+0x20/0x44 [ath12k] ath12k_core_panic_handler+0x28/0x3c [ath12k] notifier_call_chain+0x78/0x1c0 atomic_notifier_call_chain+0x3c/0x5c In ath12k_pci_panic_handler() many reset related registers need to be read/written. Since Q6 can be in a power‑saving mode (M1/M2), the common PCI read/write APIs in ath12k explicitly wake up Q6 and wait until it reaches the M0 state before issuing the read/write. The wait may result in a context switch. Panic handler is in a atomic RCU read process, we need to avoid context switch in this process. Add a flag to avoid waking up Q6 in panic handler process. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Yingying Tang Signed-off-by: Kuba Pawlak --- drivers/net/wireless/ath/ath12k/core.c | 2 ++ drivers/net/wireless/ath/ath12k/core.h | 1 + drivers/net/wireless/ath/ath12k/pci.c | 6 ++++-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/ath/ath12k/core.c index 4ed608ba3c304..e86dcc6ddbb86 100644 --- a/drivers/net/wireless/ath/ath12k/core.c +++ b/drivers/net/wireless/ath/ath12k/core.c @@ -1770,6 +1770,8 @@ static int ath12k_core_panic_handler(struct notifier_block *nb, struct ath12k_base *ab = container_of(nb, struct ath12k_base, panic_nb); + set_bit(ATH12K_FLAG_PANIC_PROCESSING, &ab->dev_flags); + return ath12k_hif_panic_handler(ab); } diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h index 990934ec92fca..490c8a20028fa 100644 --- a/drivers/net/wireless/ath/ath12k/core.h +++ b/drivers/net/wireless/ath/ath12k/core.h @@ -279,6 +279,7 @@ enum ath12k_dev_flags { ATH12K_FLAG_QMI_FW_READY_COMPLETE, ATH12K_FLAG_FTM_SEGMENTED, ATH12K_FLAG_FIXED_MEM_REGION, + ATH12K_FLAG_PANIC_PROCESSING, }; struct ath12k_tx_conf { diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c index 375277ca2b892..9efc9396c90b7 100644 --- a/drivers/net/wireless/ath/ath12k/pci.c +++ b/drivers/net/wireless/ath/ath12k/pci.c @@ -1157,7 +1157,8 @@ u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset) * need to wakeup MHI to access. */ if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && - offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) + offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup && + !test_bit(ATH12K_FLAG_PANIC_PROCESSING, &ab->dev_flags)) ret = ab_pci->pci_ops->wakeup(ab); if (offset < WINDOW_START) { @@ -1205,7 +1206,8 @@ void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value) * need to wakeup MHI to access. */ if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && - offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) + offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup && + !test_bit(ATH12K_FLAG_PANIC_PROCESSING, &ab->dev_flags)) ret = ab_pci->pci_ops->wakeup(ab); if (offset < WINDOW_START) { From 93b8fb7b0273dcfafe9da4482d195dfa19de6664 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Thu, 15 Jan 2026 10:30:10 +0800 Subject: [PATCH 0560/1330] QCLINUX: arm64: dts: qcom: workaround for TPM pins Purwa will crash if HLOS attempts to access or configure the TPM pins, as these operations require higher privilege levels. Therefore, the TPM pins should be reserved in the DTS until NHLOS provides proper support. Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index fb90beb1096f6..9ce86d3ff8cb5 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -472,7 +472,8 @@ }; &tlmm { - gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ + gpio-reserved-ranges = <34 2>, /* TPM LP & INT */ + <44 4>; /* SPI (TPM) */ pcie3_default: pcie3-default-state { clkreq-n-pins { From 92d6856a47909155661a92f1790f553132735080 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 20 Apr 2026 16:31:09 +0200 Subject: [PATCH 0561/1330] initial derivative Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 5 + debian.qcom/config/README.rst | 185 ++ debian.qcom/config/annotations | 2452 +++++++++++++++++ debian.qcom/control.d/flavour-control.stub | 87 + .../control.d/flavour-signed-control.stub | 38 + debian.qcom/control.d/vars.qcom | 6 + debian.qcom/control.stub.in | 98 + debian.qcom/dkms-versions | 1 + debian.qcom/etc/update.conf | 7 + debian.qcom/modprobe.d/common.conf | 3 + debian.qcom/reconstruct | 39 + debian.qcom/rules.d/arm64.mk | 18 + debian.qcom/tracking-bug | 1 + debian.qcom/upstream-stable | 3 + debian.qcom/variants | 1 + debian/debian.env | 2 +- 16 files changed, 2945 insertions(+), 1 deletion(-) create mode 100644 debian.qcom/changelog create mode 100644 debian.qcom/config/README.rst create mode 100644 debian.qcom/config/annotations create mode 100644 debian.qcom/control.d/flavour-control.stub create mode 100644 debian.qcom/control.d/flavour-signed-control.stub create mode 100644 debian.qcom/control.d/vars.qcom create mode 100644 debian.qcom/control.stub.in create mode 100644 debian.qcom/dkms-versions create mode 100644 debian.qcom/etc/update.conf create mode 100644 debian.qcom/modprobe.d/common.conf create mode 100644 debian.qcom/reconstruct create mode 100644 debian.qcom/rules.d/arm64.mk create mode 100644 debian.qcom/tracking-bug create mode 100644 debian.qcom/upstream-stable create mode 100644 debian.qcom/variants diff --git a/debian.qcom/changelog b/debian.qcom/changelog new file mode 100644 index 0000000000000..177a595752d4b --- /dev/null +++ b/debian.qcom/changelog @@ -0,0 +1,5 @@ +linux-qcom (7.0.0-1003.3) resolute; urgency=medium + + Initial variant of Qualcomm + + -- Kuba Pawlak Mon, 20 Apr 2026 16:44:39 +0200 diff --git a/debian.qcom/config/README.rst b/debian.qcom/config/README.rst new file mode 100644 index 0000000000000..751ce7f3b284d --- /dev/null +++ b/debian.qcom/config/README.rst @@ -0,0 +1,185 @@ +================== +Config Annotations +================== + +:Author: Andrea Righi + +Overview +======== + +Each Ubuntu kernel needs to maintain its own .config for each supported +architecture and each flavour. + +Every time a new patch is applied or a kernel is rebased on top of a new +one, we need to update the .config's accordingly (config options can be +added, removed and also renamed). + +So, we need to make sure that some critical config options are always +matching the desired value in order to have a functional kernel. + +State of the art +================ + +At the moment configs are maintained as a set of Kconfig chunks (inside +`debian./config/`): a global one, plus per-arch / per-flavour +chunks. + +In addition to that, we need to maintain also a file called +'annotations'; the purpose of this file is to make sure that some +critical config options are not silently removed or changed when the +real .config is re-generated (for example after a rebase or after +applying a new set of patches). + +The main problem with this approach is that, often, we have duplicate +information that is stored both in the Kconfig chunks *and* in the +annotations files and, at the same time, the whole .config's information +is distributed between Kconfig chunks and annotations, making it hard to +maintain, review and manage in general. + +Proposed solution +================= + +The proposed solution is to store all the config information into the +"annotations" format and get rid of the config chunks (basically the +real .config's can be produced "compiling" annotations). + +Implementation +============== + +To help the management of the annotations an helper script is provided +(`debian/scripts/misc/annotations`): + +``` +usage: annotations [-h] [--version] [--file FILE] [--arch ARCH] [--flavour FLAVOUR] [--config CONFIG] + (--query | --export | --import FILE | --update FILE | --check FILE) + +Manage Ubuntu kernel .config and annotations + +options: + -h, --help show this help message and exit + --version, -v show program's version number and exit + --file FILE, -f FILE Pass annotations or .config file to be parsed + --arch ARCH, -a ARCH Select architecture + --flavour FLAVOUR, -l FLAVOUR + Select flavour (default is "generic") + --config CONFIG, -c CONFIG + Select a specific config option + +Action: + --query, -q Query annotations + --export, -e Convert annotations to .config format + --import FILE, -i FILE + Import a full .config for a specific arch and flavour into annotations + --update FILE, -u FILE + Import a partial .config into annotations (only resync configs specified in FILE) + --check FILE, -k FILE + Validate kernel .config with annotations +``` + +This script allows to query config settings (per arch/flavour/config), +export them into the Kconfig format (generating the real .config files) +and check if the final .config matches the rules defined in the +annotations. + +Examples (annotations is defined as an alias to `debian/scripts/annotations`): + + - Show settings for `CONFIG_DEBUG_INFO_BTF` for master kernel across all the + supported architectures and flavours: + +``` +$ annotations --query --config CONFIG_DEBUG_INFO_BTF +{ + "policy": { + "amd64": "y", + "arm64": "y", + "armhf": "n", + "ppc64el": "y", + "riscv64": "y", + "s390x": "y" + }, + "note": "'Needs newer pahole for armhf'" +} +``` + + - Dump kernel .config for arm64 and flavour generic-64k: + +``` +$ annotations --arch arm64 --flavour generic-64k --export +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_COMPAT=y +... +``` + + - Update annotations file with a new kernel .config for amd64 flavour + generic: + +``` +$ annotations --arch amd64 --flavour generic --import build/.config +``` + +Moreover, an additional kernelconfig commands are provided +(via debian/rules targets): + - `migrateconfigs`: automatically merge all the previous configs into + annotations (local changes still need to be committed) + +Annotations headers +=================== + +The main annotations file should contain a header to define the architectures +and flavours that are supported. + +Here is the format of the header for the generic kernel: +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 armhf ppc64el riscv64 s390x +# FLAVOUR: amd64-generic arm64-generic arm64-generic-64k armhf-generic armhf-generic-lpae ppc64el-generic riscv64-generic s390x-generic + +``` + +Example header of a derivative (linux-aws): +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 +# FLAVOUR: amd64-aws arm64-aws +# FLAVOUR_DEP: {'amd64-aws': 'amd64-generic', 'arm64-aws': 'arm64-generic'} + +include "../../debian.master/config/annotations" + +# Below you can define only the specific linux-aws configs that differ from linux generic + +``` + +Pros and Cons +============= + + Pros: + - avoid duplicate information in .config's and annotations + - allow to easily define groups of config settings (for a specific + environment or feature, such as annotations.clouds, annotations.ubuntu, + annotations.snapd, etc.) + - config options are more accessible, easy to change and review + - we can easily document how config options are managed (and external + contributors won't be discouraged anymore when they need to to change a + config option) + + Cons: + - potential regressions: the new tool/scripts can have potential bugs, + so we could experience regressions due to some missed config changes + - kernel team need to understand the new process (even if everything + is transparent, kernel cranking process is the same, there might be + corner cases that need to be addressed and resolved manually) + +TODO +==== + + - Migrate all flavour and arch definitions into annotations (rather + than having this information defined in multiple places inside + debian/scripts); right now this information is "partially" migrated, + meaning that we need to define arches and flavours in the headers + section of annotations (so that the annotations tool can figure out + the list of supported arches and flavours), but arches and flavours + are still defined elsewhere, ideally we would like to have arches and + flavours defined only in one place: annotations. diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations new file mode 100644 index 0000000000000..49d5e8694bdb5 --- /dev/null +++ b/debian.qcom/config/annotations @@ -0,0 +1,2452 @@ +# Menu: HEADER +# FORMAT: 4 +# ARCH: arm64 +# FLAVOUR: arm64-qcom +# FLAVOUR_DEP: {'arm64-qcom': 'arm64-generic'} + +include "../../debian.master/config/annotations" + +CONFIG_ARCH_MMAP_RND_BITS policy<{'arm64': '18'}> +CONFIG_ARCH_MMAP_RND_BITS note<'LP: #1983357'> + +CONFIG_ARCH_MMAP_RND_COMPAT_BITS policy<{'arm64': '11'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS note<'LP: #1983357'> + +CONFIG_ARCH_ROCKCHIP policy<{'arm64': 'n'}> +CONFIG_ARCH_ROCKCHIP note<'LP: #1825222'> + +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT note<'LP: #2102032'> + +CONFIG_DRM_AMDGPU_CIK policy<{'arm64': '-'}> +CONFIG_DRM_AMDGPU_CIK note<'for zesty'> + +CONFIG_DRM_MGAG200 policy<{'arm64': 'n'}> +CONFIG_DRM_MGAG200 note<'LP: #1693337'> + +CONFIG_EFI_ZBOOT policy<{'arm64': 'n'}> +CONFIG_EFI_ZBOOT note<'we use arch/arm64/boot/Image.gz'> + +CONFIG_HSA_AMD_P2P policy<{'arm64': '-'}> +CONFIG_HSA_AMD_P2P note<'LP: #1987394'> + +CONFIG_IPMMU_VMSA policy<{'arm64': '-'}> +CONFIG_IPMMU_VMSA note<'LP: #1718734'> + +CONFIG_KERNEL_ZSTD policy<{'arm64': '-'}> +CONFIG_KERNEL_ZSTD note<'we use arch/arm64/boot/Image.gz'> + +CONFIG_MMC_SDHCI policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI note<'installation essential on omap/highbank'> + +CONFIG_MMC_SDHCI_PLTFM policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_PLTFM note<'boot essential on highbank'> + +CONFIG_NR_CPUS policy<{'arm64': '256'}> +CONFIG_NR_CPUS note<'LP: #2042897 (arm64), LP: #1967889 (riscv64), LP: #1864198 (s390x)'> + +CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'arm64': 'y'}> +CONFIG_REGULATOR_FIXED_VOLTAGE note<'boot essential on arm'> + +CONFIG_SERIAL_SH_SCI policy<{'arm64': '-'}> +CONFIG_SERIAL_SH_SCI note<'LP: #2022361'> + +CONFIG_SERIAL_SH_SCI_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_SH_SCI_CONSOLE note<'LP: #2022361'> + +CONFIG_SERIAL_SH_SCI_EARLYCON policy<{'arm64': '-'}> +CONFIG_SERIAL_SH_SCI_EARLYCON note<'LP: #2022361'> + +CONFIG_SND policy<{'arm64': 'y'}> +CONFIG_SND note<'LP: #2126816'> + +CONFIG_SND_SOC policy<{'arm64': 'y'}> +CONFIG_SND_SOC note<'LP: #2126816'> + +CONFIG_SOUND policy<{'arm64': 'y'}> +CONFIG_SOUND note<'LP: #2126816'> + +CONFIG_SUN6I_RTC_CCU policy<{'arm64': '-'}> +CONFIG_SUN6I_RTC_CCU note<'needed by Allwinner D1 pinctrl/gpio'> + +CONFIG_SYSFB_SIMPLEFB policy<{'arm64': 'n'}> +CONFIG_SYSFB_SIMPLEFB note<'LP: #1965303'> + +CONFIG_TOUCHSCREEN_APPLE_Z2 policy<{'arm64': '-'}> +CONFIG_TOUCHSCREEN_APPLE_Z2 note<'TODO: update note'> + + +# ---- Annotations without notes ---- + +CONFIG_AC97_BUS policy<{'arm64': 'y'}> +CONFIG_ADI_AXI_ADC policy<{'arm64': '-'}> +CONFIG_ADI_AXI_DAC policy<{'arm64': '-'}> +CONFIG_AHCI_IMX policy<{'arm64': '-'}> +CONFIG_AHCI_MTK policy<{'arm64': '-'}> +CONFIG_AHCI_MVEBU policy<{'arm64': '-'}> +CONFIG_AHCI_QORIQ policy<{'arm64': '-'}> +CONFIG_AHCI_SUNXI policy<{'arm64': '-'}> +CONFIG_AHCI_TEGRA policy<{'arm64': '-'}> +CONFIG_AHCI_XGENE policy<{'arm64': '-'}> +CONFIG_AIROHA_CPU_PM_DOMAIN policy<{'arm64': '-'}> +CONFIG_AIROHA_THERMAL policy<{'arm64': '-'}> +CONFIG_AIROHA_WATCHDOG policy<{'arm64': '-'}> +CONFIG_AMD_ISP4 policy<{'arm64': '-'}> +CONFIG_AMLOGIC_THERMAL policy<{'arm64': '-'}> +CONFIG_APPLE_ADMAC policy<{'arm64': '-'}> +CONFIG_APPLE_AIC policy<{'arm64': '-'}> +CONFIG_APPLE_DART policy<{'arm64': '-'}> +CONFIG_APPLE_M1_CPU_PMU policy<{'arm64': '-'}> +CONFIG_APPLE_MAILBOX policy<{'arm64': '-'}> +CONFIG_APPLE_PMGR_PWRSTATE policy<{'arm64': '-'}> +CONFIG_APPLE_RTKIT policy<{'arm64': '-'}> +CONFIG_APPLE_SART policy<{'arm64': '-'}> +CONFIG_APPLE_TUNABLE policy<{'arm64': '-'}> +CONFIG_APPLE_WATCHDOG policy<{'arm64': '-'}> +CONFIG_ARCH_ACTIONS policy<{'arm64': 'n'}> +CONFIG_ARCH_AIROHA policy<{'arm64': 'n'}> +CONFIG_ARCH_APPLE policy<{'arm64': 'n'}> +CONFIG_ARCH_AXIADO policy<{'arm64': 'n'}> +CONFIG_ARCH_BERLIN policy<{'arm64': 'n'}> +CONFIG_ARCH_BITMAIN policy<{'arm64': 'n'}> +CONFIG_ARCH_BLAIZE policy<{'arm64': 'n'}> +CONFIG_ARCH_CIX policy<{'arm64': 'n'}> +CONFIG_ARCH_FORCE_MAX_ORDER policy<{'arm64': '10'}> +CONFIG_ARCH_HAS_RESET_CONTROLLER policy<{'arm64': '-'}> +CONFIG_ARCH_HISI policy<{'arm64': 'n'}> +CONFIG_ARCH_INTEL_SOCFPGA policy<{'arm64': 'n'}> +CONFIG_ARCH_K3 policy<{'arm64': 'n'}> +CONFIG_ARCH_KEEMBAY policy<{'arm64': 'n'}> +CONFIG_ARCH_LAYERSCAPE policy<{'arm64': '-'}> +CONFIG_ARCH_LG1K policy<{'arm64': 'n'}> +CONFIG_ARCH_MA35 policy<{'arm64': 'n'}> +CONFIG_ARCH_MEDIATEK policy<{'arm64': 'n'}> +CONFIG_ARCH_MESON policy<{'arm64': 'n'}> +CONFIG_ARCH_MMP policy<{'arm64': 'n'}> +CONFIG_ARCH_MVEBU policy<{'arm64': 'n'}> +CONFIG_ARCH_MXC policy<{'arm64': '-'}> +CONFIG_ARCH_NPCM policy<{'arm64': 'n'}> +CONFIG_ARCH_NXP policy<{'arm64': 'n'}> +CONFIG_ARCH_PENSANDO policy<{'arm64': 'n'}> +CONFIG_ARCH_R8A774A1 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A774B1 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A774C0 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A774E1 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A77951 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A77960 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A77961 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A77965 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A77970 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A77980 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A77990 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A77995 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A779A0 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A779F0 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A779G0 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A779H0 policy<{'arm64': '-'}> +CONFIG_ARCH_R8A78000 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A07G043 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A07G044 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A07G054 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A08G045 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A09G011 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A09G047 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A09G056 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A09G057 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A09G077 policy<{'arm64': '-'}> +CONFIG_ARCH_R9A09G087 policy<{'arm64': '-'}> +CONFIG_ARCH_RCAR_GEN3 policy<{'arm64': '-'}> +CONFIG_ARCH_RCAR_GEN4 policy<{'arm64': '-'}> +CONFIG_ARCH_RCAR_GEN5 policy<{'arm64': '-'}> +CONFIG_ARCH_REALTEK policy<{'arm64': 'n'}> +CONFIG_ARCH_RENESAS policy<{'arm64': 'n'}> +CONFIG_ARCH_RZG2L policy<{'arm64': '-'}> +CONFIG_ARCH_S32 policy<{'arm64': '-'}> +CONFIG_ARCH_SEATTLE policy<{'arm64': 'n'}> +CONFIG_ARCH_SOPHGO policy<{'arm64': 'n'}> +CONFIG_ARCH_SPARX5 policy<{'arm64': 'n'}> +CONFIG_ARCH_SPRD policy<{'arm64': 'n'}> +CONFIG_ARCH_STM32 policy<{'arm64': 'n'}> +CONFIG_ARCH_SUNXI policy<{'arm64': 'n'}> +CONFIG_ARCH_SYNQUACER policy<{'arm64': 'n'}> +CONFIG_ARCH_TEGRA policy<{'arm64': 'n'}> +CONFIG_ARCH_TEGRA_132_SOC policy<{'arm64': '-'}> +CONFIG_ARCH_TEGRA_186_SOC policy<{'arm64': '-'}> +CONFIG_ARCH_TEGRA_194_SOC policy<{'arm64': '-'}> +CONFIG_ARCH_TEGRA_210_SOC policy<{'arm64': '-'}> +CONFIG_ARCH_TEGRA_234_SOC policy<{'arm64': '-'}> +CONFIG_ARCH_TEGRA_241_SOC policy<{'arm64': '-'}> +CONFIG_ARCH_TEGRA_264_SOC policy<{'arm64': '-'}> +CONFIG_ARCH_THUNDER policy<{'arm64': 'n'}> +CONFIG_ARCH_THUNDER2 policy<{'arm64': 'n'}> +CONFIG_ARCH_VEXPRESS policy<{'arm64': 'n'}> +CONFIG_ARCH_VISCONTI policy<{'arm64': 'n'}> +CONFIG_ARCH_XGENE policy<{'arm64': 'n'}> +CONFIG_ARCH_ZYNQMP policy<{'arm64': 'n'}> +CONFIG_ARC_EMAC_CORE policy<{'arm64': '-'}> +CONFIG_ARMADA_37XX_CLK policy<{'arm64': '-'}> +CONFIG_ARMADA_37XX_RWTM_MBOX policy<{'arm64': '-'}> +CONFIG_ARMADA_37XX_WATCHDOG policy<{'arm64': '-'}> +CONFIG_ARMADA_AP806_SYSCON policy<{'arm64': '-'}> +CONFIG_ARMADA_AP_CPU_CLK policy<{'arm64': '-'}> +CONFIG_ARMADA_AP_CP_HELPER policy<{'arm64': '-'}> +CONFIG_ARMADA_CP110_SYSCON policy<{'arm64': '-'}> +CONFIG_ARMADA_THERMAL policy<{'arm64': '-'}> +CONFIG_ARM_AIROHA_SOC_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM policy<{'arm64': '-'}> +CONFIG_ARM_APPLE_SOC_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_ARMADA_37XX_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_ARMADA_8K_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_GIC_PM policy<{'arm64': '-'}> +CONFIG_ARM_GIC_V3_ITS_FSL_MC policy<{'arm64': '-'}> +CONFIG_ARM_IMX6Q_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_IMX8M_DDRC_DEVFREQ policy<{'arm64': '-'}> +CONFIG_ARM_IMX_BUS_DEVFREQ policy<{'arm64': '-'}> +CONFIG_ARM_IMX_CPUFREQ_DT policy<{'arm64': '-'}> +CONFIG_ARM_MEDIATEK_CCI_DEVFREQ policy<{'arm64': '-'}> +CONFIG_ARM_MEDIATEK_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_MEDIATEK_CPUFREQ_HW policy<{'arm64': '-'}> +CONFIG_ARM_MHU policy<{'arm64': 'y'}> +CONFIG_ARM_QCOM_CPUFREQ_HW policy<{'arm64': 'y'}> +CONFIG_ARM_RK3399_DMC_DEVFREQ policy<{'arm64': '-'}> +CONFIG_ARM_SBSA_WATCHDOG policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_CPUFREQ policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_PERF_DOMAIN policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_POWER_DOMAIN policy<{'arm64': 'y'}> +CONFIG_ARM_SCPI_POWER_DOMAIN policy<{'arm64': 'y'}> +CONFIG_ARM_SCPI_PROTOCOL policy<{'arm64': 'y'}> +CONFIG_ARM_SMC_WATCHDOG policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_QCOM_TBU policy<{'arm64': '-'}> +CONFIG_ARM_SP805_WATCHDOG policy<{'arm64': 'y'}> +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ policy<{'arm64': '-'}> +CONFIG_ARM_TEGRA124_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_TEGRA186_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_TEGRA194_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_TEGRA20_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ARM_TEGRA_DEVFREQ policy<{'arm64': '-'}> +CONFIG_ARM_TI_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ATH11K_COREDUMP policy<{'arm64': '-'}> +CONFIG_AX88179B policy<{'arm64': '-'}> +CONFIG_AXI_DMAC policy<{'arm64': '-'}> +CONFIG_BACKLIGHT_APPLE_DWI policy<{'arm64': '-'}> +CONFIG_BACKLIGHT_QCOM_WLED policy<{'arm64': 'y'}> +CONFIG_BATTERY_OLPC policy<{'arm64': '-'}> +CONFIG_BCMDHD policy<{'arm64': '-'}> +CONFIG_BCMDHD_FW_PATH policy<{'arm64': '-'}> +CONFIG_BCMDHD_NVRAM_PATH policy<{'arm64': '-'}> +CONFIG_BCMDHD_OOB policy<{'arm64': '-'}> +CONFIG_BCMDHD_PCIE policy<{'arm64': '-'}> +CONFIG_BCMDHD_SDIO policy<{'arm64': '-'}> +CONFIG_BCMDHD_SDIO_IRQ policy<{'arm64': '-'}> +CONFIG_BCMDHD_USB policy<{'arm64': '-'}> +CONFIG_BERLIN2_ADC policy<{'arm64': '-'}> +CONFIG_CAN_BXCAN policy<{'arm64': '-'}> +CONFIG_CAN_RCAR policy<{'arm64': '-'}> +CONFIG_CAN_RCAR_CANFD policy<{'arm64': '-'}> +CONFIG_CAN_ROCKCHIP_CANFD policy<{'arm64': '-'}> +CONFIG_CAVIUM_CPT policy<{'arm64': '-'}> +CONFIG_CEC_MESON_AO policy<{'arm64': '-'}> +CONFIG_CEC_MESON_G12A_AO policy<{'arm64': '-'}> +CONFIG_CEC_STM32 policy<{'arm64': '-'}> +CONFIG_CEC_TEGRA policy<{'arm64': '-'}> +CONFIG_CHARGER_CPCAP policy<{'arm64': '-'}> +CONFIG_CHARGER_SC2731 policy<{'arm64': '-'}> +CONFIG_CIX_MBOX policy<{'arm64': '-'}> +CONFIG_CLKSRC_STM32_LP policy<{'arm64': '-'}> +CONFIG_CLK_ACTIONS policy<{'arm64': '-'}> +CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'y'}> +CONFIG_CLK_GLYMUR_GPUCC policy<{'arm64': 'y'}> +CONFIG_CLK_GLYMUR_VIDEOCC policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8MM policy<{'arm64': '-'}> +CONFIG_CLK_IMX8MN policy<{'arm64': '-'}> +CONFIG_CLK_IMX8MP policy<{'arm64': '-'}> +CONFIG_CLK_IMX8MQ policy<{'arm64': '-'}> +CONFIG_CLK_IMX8QXP policy<{'arm64': '-'}> +CONFIG_CLK_IMX8ULP policy<{'arm64': '-'}> +CONFIG_CLK_IMX93 policy<{'arm64': '-'}> +CONFIG_CLK_IMX95_BLK_CTL policy<{'arm64': '-'}> +CONFIG_CLK_INTEL_SOCFPGA policy<{'arm64': '-'}> +CONFIG_CLK_INTEL_SOCFPGA64 policy<{'arm64': '-'}> +CONFIG_CLK_KAANAPALI_TCSRCC policy<{'arm64': 'n'}> +CONFIG_CLK_LS1028A_PLLDIG policy<{'arm64': '-'}> +CONFIG_CLK_MA35D1 policy<{'arm64': '-'}> +CONFIG_CLK_OWL_S500 policy<{'arm64': '-'}> +CONFIG_CLK_OWL_S700 policy<{'arm64': '-'}> +CONFIG_CLK_OWL_S900 policy<{'arm64': '-'}> +CONFIG_CLK_PX30 policy<{'arm64': '-'}> +CONFIG_CLK_QORIQ policy<{'arm64': '-'}> +CONFIG_CLK_R8A774A1 policy<{'arm64': '-'}> +CONFIG_CLK_R8A774B1 policy<{'arm64': '-'}> +CONFIG_CLK_R8A774C0 policy<{'arm64': '-'}> +CONFIG_CLK_R8A774E1 policy<{'arm64': '-'}> +CONFIG_CLK_R8A7795 policy<{'arm64': '-'}> +CONFIG_CLK_R8A77960 policy<{'arm64': '-'}> +CONFIG_CLK_R8A77961 policy<{'arm64': '-'}> +CONFIG_CLK_R8A77965 policy<{'arm64': '-'}> +CONFIG_CLK_R8A77970 policy<{'arm64': '-'}> +CONFIG_CLK_R8A77980 policy<{'arm64': '-'}> +CONFIG_CLK_R8A77990 policy<{'arm64': '-'}> +CONFIG_CLK_R8A77995 policy<{'arm64': '-'}> +CONFIG_CLK_R8A779A0 policy<{'arm64': '-'}> +CONFIG_CLK_R8A779F0 policy<{'arm64': '-'}> +CONFIG_CLK_R8A779G0 policy<{'arm64': '-'}> +CONFIG_CLK_R8A779H0 policy<{'arm64': '-'}> +CONFIG_CLK_R9A07G043 policy<{'arm64': '-'}> +CONFIG_CLK_R9A07G044 policy<{'arm64': '-'}> +CONFIG_CLK_R9A07G054 policy<{'arm64': '-'}> +CONFIG_CLK_R9A08G045 policy<{'arm64': '-'}> +CONFIG_CLK_R9A09G011 policy<{'arm64': '-'}> +CONFIG_CLK_R9A09G047 policy<{'arm64': '-'}> +CONFIG_CLK_R9A09G056 policy<{'arm64': '-'}> +CONFIG_CLK_R9A09G057 policy<{'arm64': '-'}> +CONFIG_CLK_R9A09G077 policy<{'arm64': '-'}> +CONFIG_CLK_R9A09G087 policy<{'arm64': '-'}> +CONFIG_CLK_RCAR_CPG_LIB policy<{'arm64': '-'}> +CONFIG_CLK_RCAR_GEN3_CPG policy<{'arm64': '-'}> +CONFIG_CLK_RCAR_GEN4_CPG policy<{'arm64': '-'}> +CONFIG_CLK_RCAR_USB2_CLOCK_SEL policy<{'arm64': '-'}> +CONFIG_CLK_RENESAS policy<{'arm64': '-'}> +CONFIG_CLK_RENESAS_CPG_MSSR policy<{'arm64': '-'}> +CONFIG_CLK_RENESAS_DIV6 policy<{'arm64': '-'}> +CONFIG_CLK_RENESAS_VBATTB policy<{'arm64': '-'}> +CONFIG_CLK_RK3308 policy<{'arm64': '-'}> +CONFIG_CLK_RK3328 policy<{'arm64': '-'}> +CONFIG_CLK_RK3368 policy<{'arm64': '-'}> +CONFIG_CLK_RK3399 policy<{'arm64': '-'}> +CONFIG_CLK_RK3528 policy<{'arm64': '-'}> +CONFIG_CLK_RK3562 policy<{'arm64': '-'}> +CONFIG_CLK_RK3568 policy<{'arm64': '-'}> +CONFIG_CLK_RK3576 policy<{'arm64': '-'}> +CONFIG_CLK_RK3588 policy<{'arm64': '-'}> +CONFIG_CLK_RV1126B policy<{'arm64': '-'}> +CONFIG_CLK_RZG2L policy<{'arm64': '-'}> +CONFIG_CLK_RZV2H policy<{'arm64': '-'}> +CONFIG_CLK_SHIKRA_GCC policy<{'arm64': 'y'}> +CONFIG_CLK_SOPHGO_CV1800 policy<{'arm64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_CLKGEN policy<{'arm64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_PLL policy<{'arm64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_RPGATE policy<{'arm64': '-'}> +CONFIG_CLK_SOPHGO_SG2044 policy<{'arm64': '-'}> +CONFIG_CLK_SOPHGO_SG2044_PLL policy<{'arm64': '-'}> +CONFIG_CLK_TEGRA_BPMP policy<{'arm64': '-'}> +CONFIG_CLK_X1E80100_GCC policy<{'arm64': 'y'}> +CONFIG_CLK_X1P42100_CAMCC policy<{'arm64': 'y'}> +CONFIG_CLK_X1P42100_VIDEOCC policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_A1_PERIPHERALS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_A1_PLL policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_APPLE_NCO policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_AXG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_AXG_AUDIO policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_BM1880 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_C3_PERIPHERALS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_C3_PLL policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_CS2000_CP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_EN7523 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_FSL_FLEXSPI policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_FSL_SAI policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_G12A policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_GXBB policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_HI3516CV300 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_HI3519 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_HI3559A policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_HI3660 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_HI3670 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_HI3798CV200 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_HI6220 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_HI655X policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MEDIATEK policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MEDIATEK_FHCTL policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_AO_CLKC policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_CLKC_UTILS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_CPU_DYNDIV policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_DUALDIV policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_EE_CLKC policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_MPLL policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_PHASE policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_PLL policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_REGMAP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_SCLK_DIV policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_VCLK policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MESON_VID_PLL_DIV policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT2712 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT2712_BDPSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT2712_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT2712_JPGDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT2712_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT2712_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT2712_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT2712_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6735 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6735_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6735_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6735_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6735_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_AUDIOSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_CAMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_GCESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_MFGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_MIPI0ASYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_MIPI0BSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_MIPI1ASYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_MIPI1BSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_MIPI2ASYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_MIPI2BSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6765_VCODECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779_AUDSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779_CAMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779_IPESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6779_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6795 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6795_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6795_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6795_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6795_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6797 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6797_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6797_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6797_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT6797_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7622 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7622_AUDSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7622_ETHSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7622_HIFSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7981 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7981_ETHSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7986 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7986_ETHSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT7988 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8167 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8167_AUDSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8167_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8167_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8167_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8167_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8173 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8173_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8173_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8173_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8173_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_AUDIOSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_CAMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_IPU_ADL policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_IPU_CONN policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_IPU_CORE0 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_IPU_CORE1 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8183_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_CAMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_IPESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_MCUSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_MDPSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8186_WPESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_ADSP_AUDIO26M policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_CAMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_IMP_IIC_WRAP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_IPESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_VDOSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_VPPSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8188_WPESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_AUDSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_CAMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_IPESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_MDPSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_MSDC policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_SCP_ADSP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8192_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_APUSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_AUDSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_CAMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_IMGSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_IPESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_MSDC policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_SCP_ADSP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_VDOSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_VPPSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8195_WPESYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_MCUSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_MDPSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_MFGCFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_PEXTPSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_UFSSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_VDECSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8196_VENCSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8365 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8365_APU policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8365_CAM policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8365_MFG policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8365_MMSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8365_VDEC policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8365_VENC policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8516 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_MT8516_AUDSYS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_NPCM8XX policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_NUVOTON policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_PWM policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_PXA1908 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_S4_PERIPHERALS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_S4_PLL policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_STM32MP policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_STM32MP215 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_STM32MP257 policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_T7_PERIPHERALS policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_T7_PLL policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_VISCONTI policy<{'arm64': '-'}> +CONFIG_COMMON_CLK_ZYNQMP policy<{'arm64': '-'}> +CONFIG_COMMON_RESET_HI3660 policy<{'arm64': '-'}> +CONFIG_COMMON_RESET_HI6220 policy<{'arm64': '-'}> +CONFIG_CPUMASK_OFFSTACK policy<{'arm64': '-'}> +CONFIG_CRC7 policy<{'arm64': 'y'}> +CONFIG_CRC_ITU_T policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_ALLWINNER policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_CPT policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_EIP93 policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_JR policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_MARVELL policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_MARVELL_CESA policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_MXS_DCP policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_OCTEONTX2_CPT policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_OCTEONTX_CPT policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SA2UL policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SAHARA policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_STM32_CRC policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_STM32_CRYP policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_STM32_HASH policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN4I_SS policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_TEGRA policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_TI_DTHEV2 policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_XILINX_TRNG policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_ZYNQMP_AES policy<{'arm64': '-'}> +CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 policy<{'arm64': '-'}> +CONFIG_CV1800_MBOX policy<{'arm64': '-'}> +CONFIG_CZNIC_PLATFORMS policy<{'arm64': '-'}> +CONFIG_DEBUG_KERNEL_DC policy<{'arm64': '-'}> +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI policy<{'arm64': '-'}> +CONFIG_DMA_SUN6I policy<{'arm64': '-'}> +CONFIG_DPAA2_CONSOLE policy<{'arm64': '-'}> +CONFIG_DPAA_ERRATUM_A050385 policy<{'arm64': '-'}> +CONFIG_DRM_ACCEL_ROCKET policy<{'arm64': '-'}> +CONFIG_DRM_ADP policy<{'arm64': '-'}> +CONFIG_DRM_AMDGPU policy<{'arm64': 'n'}> +CONFIG_DRM_AMDGPU_SI policy<{'arm64': '-'}> +CONFIG_DRM_AMDGPU_USERPTR policy<{'arm64': '-'}> +CONFIG_DRM_AMDGPU_WERROR policy<{'arm64': '-'}> +CONFIG_DRM_AMD_ACP policy<{'arm64': '-'}> +CONFIG_DRM_AMD_DC policy<{'arm64': '-'}> +CONFIG_DRM_AMD_DC_FP policy<{'arm64': '-'}> +CONFIG_DRM_AMD_DC_SI policy<{'arm64': '-'}> +CONFIG_DRM_AMD_ISP policy<{'arm64': '-'}> +CONFIG_DRM_AMD_SECURE_DISPLAY policy<{'arm64': '-'}> +CONFIG_DRM_BUDDY policy<{'arm64': '-'}> +CONFIG_DRM_CDNS_MHDP8546_J721E policy<{'arm64': '-'}> +CONFIG_DRM_DISPLAY_DP_TUNNEL policy<{'arm64': '-'}> +CONFIG_DRM_DW_DP policy<{'arm64': '-'}> +CONFIG_DRM_DW_HDMI policy<{'arm64': '-'}> +CONFIG_DRM_DW_HDMI_AHB_AUDIO policy<{'arm64': '-'}> +CONFIG_DRM_DW_HDMI_CEC policy<{'arm64': '-'}> +CONFIG_DRM_DW_HDMI_GP_AUDIO policy<{'arm64': '-'}> +CONFIG_DRM_DW_HDMI_I2S_AUDIO policy<{'arm64': '-'}> +CONFIG_DRM_DW_HDMI_QP policy<{'arm64': '-'}> +CONFIG_DRM_DW_HDMI_QP_CEC policy<{'arm64': '-'}> +CONFIG_DRM_DW_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_DRM_DW_MIPI_DSI2 policy<{'arm64': '-'}> +CONFIG_DRM_EFIDRM policy<{'arm64': 'n'}> +CONFIG_DRM_ETNAVIV policy<{'arm64': 'n'}> +CONFIG_DRM_ETNAVIV_THERMAL policy<{'arm64': '-'}> +CONFIG_DRM_FSL_LDB policy<{'arm64': '-'}> +CONFIG_DRM_GPUSVM policy<{'arm64': '-'}> +CONFIG_DRM_HISI_KIRIN policy<{'arm64': 'n'}> +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE policy<{'arm64': '-'}> +CONFIG_DRM_IMX8MP_HDMI_PAI policy<{'arm64': '-'}> +CONFIG_DRM_IMX8MP_HDMI_PVI policy<{'arm64': '-'}> +CONFIG_DRM_IMX8QM_LDB policy<{'arm64': '-'}> +CONFIG_DRM_IMX8QXP_LDB policy<{'arm64': '-'}> +CONFIG_DRM_IMX8QXP_PIXEL_COMBINER policy<{'arm64': '-'}> +CONFIG_DRM_IMX8QXP_PIXEL_LINK policy<{'arm64': '-'}> +CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI policy<{'arm64': '-'}> +CONFIG_DRM_IMX8_DC policy<{'arm64': '-'}> +CONFIG_DRM_IMX93_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_DRM_IMX_DCSS policy<{'arm64': '-'}> +CONFIG_DRM_IMX_LCDC policy<{'arm64': '-'}> +CONFIG_DRM_IMX_LCDIF policy<{'arm64': '-'}> +CONFIG_DRM_IMX_LDB_HELPER policy<{'arm64': '-'}> +CONFIG_DRM_INNO_HDMI policy<{'arm64': '-'}> +CONFIG_DRM_KMB_DISPLAY policy<{'arm64': '-'}> +CONFIG_DRM_LOGICVC policy<{'arm64': 'n'}> +CONFIG_DRM_LONTIUM_LT8713SX policy<{'arm64': 'm'}> +CONFIG_DRM_MEDIATEK policy<{'arm64': '-'}> +CONFIG_DRM_MEDIATEK_DP policy<{'arm64': '-'}> +CONFIG_DRM_MEDIATEK_HDMI policy<{'arm64': '-'}> +CONFIG_DRM_MEDIATEK_HDMI_COMMON policy<{'arm64': '-'}> +CONFIG_DRM_MEDIATEK_HDMI_V2 policy<{'arm64': '-'}> +CONFIG_DRM_MESON policy<{'arm64': '-'}> +CONFIG_DRM_MESON_DW_HDMI policy<{'arm64': '-'}> +CONFIG_DRM_MESON_DW_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_DRM_MSM_VALIDATE_XML policy<{'arm64': '-'}> +CONFIG_DRM_MXS policy<{'arm64': '-'}> +CONFIG_DRM_MXSFB policy<{'arm64': '-'}> +CONFIG_DRM_NOUVEAU policy<{'arm64': 'n'}> +CONFIG_DRM_NOUVEAU_BACKLIGHT policy<{'arm64': '-'}> +CONFIG_DRM_NOUVEAU_CH7006 policy<{'arm64': '-'}> +CONFIG_DRM_NOUVEAU_GSP_DEFAULT policy<{'arm64': '-'}> +CONFIG_DRM_NOUVEAU_SIL164 policy<{'arm64': '-'}> +CONFIG_DRM_NOUVEAU_SVM policy<{'arm64': '-'}> +CONFIG_DRM_NOVA policy<{'arm64': 'n'}> +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS policy<{'arm64': '-'}> +CONFIG_DRM_PL111 policy<{'arm64': 'n'}> +CONFIG_DRM_RADEON policy<{'arm64': 'n'}> +CONFIG_DRM_RADEON_USERPTR policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_CMM policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_DU policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_DW_HDMI policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_LVDS policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_USE_CMM policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_USE_LVDS policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_USE_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_VSP policy<{'arm64': '-'}> +CONFIG_DRM_RCAR_WRITEBACK policy<{'arm64': '-'}> +CONFIG_DRM_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_DRM_RZG2L_DU policy<{'arm64': '-'}> +CONFIG_DRM_RZG2L_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_DRM_RZG2L_USE_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_DRM_SHMOBILE policy<{'arm64': '-'}> +CONFIG_DRM_SPRD policy<{'arm64': '-'}> +CONFIG_DRM_SSD130X policy<{'arm64': 'n'}> +CONFIG_DRM_SSD130X_I2C policy<{'arm64': '-'}> +CONFIG_DRM_SSD130X_SPI policy<{'arm64': '-'}> +CONFIG_DRM_STM policy<{'arm64': '-'}> +CONFIG_DRM_STM_DSI policy<{'arm64': '-'}> +CONFIG_DRM_STM_LVDS policy<{'arm64': '-'}> +CONFIG_DRM_SUBALLOC_HELPER policy<{'arm64': '-'}> +CONFIG_DRM_SUN4I policy<{'arm64': '-'}> +CONFIG_DRM_SUN6I_DSI policy<{'arm64': '-'}> +CONFIG_DRM_SUN8I_DW_HDMI policy<{'arm64': '-'}> +CONFIG_DRM_SUN8I_MIXER policy<{'arm64': '-'}> +CONFIG_DRM_SUN8I_TCON_TOP policy<{'arm64': '-'}> +CONFIG_DRM_TEGRA policy<{'arm64': '-'}> +CONFIG_DRM_TEGRA_DEBUG policy<{'arm64': '-'}> +CONFIG_DRM_TEGRA_STAGING policy<{'arm64': '-'}> +CONFIG_DRM_TIDSS policy<{'arm64': 'n'}> +CONFIG_DRM_XE policy<{'arm64': 'n'}> +CONFIG_DRM_XE_DEBUG policy<{'arm64': '-'}> +CONFIG_DRM_XE_DEBUG_MEM policy<{'arm64': '-'}> +CONFIG_DRM_XE_DEBUG_MEMIRQ policy<{'arm64': '-'}> +CONFIG_DRM_XE_DEBUG_SRIOV policy<{'arm64': '-'}> +CONFIG_DRM_XE_DEBUG_VM policy<{'arm64': '-'}> +CONFIG_DRM_XE_DISPLAY policy<{'arm64': '-'}> +CONFIG_DRM_XE_DP_TUNNEL policy<{'arm64': '-'}> +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT policy<{'arm64': '-'}> +CONFIG_DRM_XE_FORCE_PROBE policy<{'arm64': '-'}> +CONFIG_DRM_XE_GPUSVM policy<{'arm64': '-'}> +CONFIG_DRM_XE_JOB_TIMEOUT_MAX policy<{'arm64': '-'}> +CONFIG_DRM_XE_JOB_TIMEOUT_MIN policy<{'arm64': '-'}> +CONFIG_DRM_XE_PAGEMAP policy<{'arm64': '-'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT policy<{'arm64': '-'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX policy<{'arm64': '-'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN policy<{'arm64': '-'}> +CONFIG_DRM_XE_TIMESLICE_MAX policy<{'arm64': '-'}> +CONFIG_DRM_XE_TIMESLICE_MIN policy<{'arm64': '-'}> +CONFIG_DRM_XE_USERPTR_INVAL_INJECT policy<{'arm64': '-'}> +CONFIG_DRM_XE_WERROR policy<{'arm64': '-'}> +CONFIG_DRM_ZYNQMP_DPSUB policy<{'arm64': '-'}> +CONFIG_DRM_ZYNQMP_DPSUB_AUDIO policy<{'arm64': '-'}> +CONFIG_DVB_MAX_ADAPTERS policy<{'arm64': '16'}> +CONFIG_DWMAC_IMX8 policy<{'arm64': '-'}> +CONFIG_DWMAC_MEDIATEK policy<{'arm64': '-'}> +CONFIG_DWMAC_MESON policy<{'arm64': '-'}> +CONFIG_DWMAC_RENESAS_GBETH policy<{'arm64': '-'}> +CONFIG_DWMAC_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_DWMAC_S32 policy<{'arm64': '-'}> +CONFIG_DWMAC_SOCFPGA policy<{'arm64': '-'}> +CONFIG_DWMAC_SOPHGO policy<{'arm64': '-'}> +CONFIG_DWMAC_STM32 policy<{'arm64': '-'}> +CONFIG_DWMAC_SUN55I policy<{'arm64': '-'}> +CONFIG_DWMAC_SUN8I policy<{'arm64': '-'}> +CONFIG_DWMAC_SUNXI policy<{'arm64': '-'}> +CONFIG_DWMAC_TEGRA policy<{'arm64': '-'}> +CONFIG_DWMAC_VISCONTI policy<{'arm64': '-'}> +CONFIG_DW_APB_ICTL policy<{'arm64': '-'}> +CONFIG_EDAC_ALTERA policy<{'arm64': '-'}> +CONFIG_EDAC_ALTERA_ETHERNET policy<{'arm64': '-'}> +CONFIG_EDAC_ALTERA_NAND policy<{'arm64': '-'}> +CONFIG_EDAC_ALTERA_OCRAM policy<{'arm64': '-'}> +CONFIG_EDAC_ALTERA_QSPI policy<{'arm64': '-'}> +CONFIG_EDAC_ALTERA_SDMMC policy<{'arm64': '-'}> +CONFIG_EDAC_ALTERA_SDRAM policy<{'arm64': '-'}> +CONFIG_EDAC_ALTERA_USB policy<{'arm64': '-'}> +CONFIG_EDAC_LAYERSCAPE policy<{'arm64': '-'}> +CONFIG_EDAC_NPCM policy<{'arm64': '-'}> +CONFIG_EDAC_SYNOPSYS policy<{'arm64': '-'}> +CONFIG_EDAC_VERSAL policy<{'arm64': '-'}> +CONFIG_EDAC_VERSALNET policy<{'arm64': '-'}> +CONFIG_EDAC_ZYNQMP policy<{'arm64': '-'}> +CONFIG_EEPROM_93CX6 policy<{'arm64': 'y'}> +CONFIG_EFI_SBAT_FILE policy<{'arm64': '-'}> +CONFIG_EINT_MTK policy<{'arm64': '-'}> +CONFIG_EMAC_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_EXTCON_RTK_TYPE_C policy<{'arm64': '-'}> +CONFIG_FB_IMX policy<{'arm64': '-'}> +CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA policy<{'arm64': '-'}> +CONFIG_FB_SH_MOBILE_LCDC policy<{'arm64': '-'}> +CONFIG_FB_XILINX policy<{'arm64': '-'}> +CONFIG_FEC policy<{'arm64': '-'}> +CONFIG_FPGA_MGR_SOCFPGA policy<{'arm64': '-'}> +CONFIG_FPGA_MGR_SOCFPGA_A10 policy<{'arm64': '-'}> +CONFIG_FPGA_MGR_STRATIX10_SOC policy<{'arm64': '-'}> +CONFIG_FPGA_MGR_VERSAL_FPGA policy<{'arm64': '-'}> +CONFIG_FPGA_MGR_ZYNQMP_FPGA policy<{'arm64': '-'}> +CONFIG_FRAME_WARN policy<{'arm64': '2048'}> +CONFIG_FSL_BMAN_TEST policy<{'arm64': '-'}> +CONFIG_FSL_BMAN_TEST_API policy<{'arm64': '-'}> +CONFIG_FSL_DPAA policy<{'arm64': '-'}> +CONFIG_FSL_DPAA2_ETH policy<{'arm64': '-'}> +CONFIG_FSL_DPAA2_ETH_DCB policy<{'arm64': '-'}> +CONFIG_FSL_DPAA2_PTP_CLOCK policy<{'arm64': '-'}> +CONFIG_FSL_DPAA2_QDMA policy<{'arm64': '-'}> +CONFIG_FSL_DPAA_CHECKING policy<{'arm64': '-'}> +CONFIG_FSL_DPAA_ETH policy<{'arm64': '-'}> +CONFIG_FSL_FMAN policy<{'arm64': '-'}> +CONFIG_FSL_GUTS policy<{'arm64': '-'}> +CONFIG_FSL_IFC policy<{'arm64': '-'}> +CONFIG_FSL_IMX8_DDR_PMU policy<{'arm64': '-'}> +CONFIG_FSL_IMX9_DDR_PMU policy<{'arm64': '-'}> +CONFIG_FSL_MC_BUS policy<{'arm64': '-'}> +CONFIG_FSL_MC_DPIO policy<{'arm64': '-'}> +CONFIG_FSL_MC_UAPI_SUPPORT policy<{'arm64': '-'}> +CONFIG_FSL_QMAN_TEST policy<{'arm64': '-'}> +CONFIG_FUEL_GAUGE_SC27XX policy<{'arm64': '-'}> +CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT policy<{'arm64': 'y'}> +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND policy<{'arm64': '-'}> +CONFIG_GENERIC_IRQ_IPI_MUX policy<{'arm64': '-'}> +CONFIG_GH_VIRT_WATCHDOG policy<{'arm64': '-'}> +CONFIG_GPIO_ALTERA_A10SR policy<{'arm64': '-'}> +CONFIG_GPIO_BLZP1600 policy<{'arm64': '-'}> +CONFIG_GPIO_DAVINCI policy<{'arm64': '-'}> +CONFIG_GPIO_EIC_SPRD policy<{'arm64': '-'}> +CONFIG_GPIO_EN7523 policy<{'arm64': '-'}> +CONFIG_GPIO_IMX_SCU policy<{'arm64': '-'}> +CONFIG_GPIO_MACSMC policy<{'arm64': '-'}> +CONFIG_GPIO_MPC8XXX policy<{'arm64': '-'}> +CONFIG_GPIO_MVEBU policy<{'arm64': '-'}> +CONFIG_GPIO_MXC policy<{'arm64': '-'}> +CONFIG_GPIO_NPCM_SGPIO policy<{'arm64': '-'}> +CONFIG_GPIO_PCA953X policy<{'arm64': 'y'}> +CONFIG_GPIO_PMIC_EIC_SPRD policy<{'arm64': '-'}> +CONFIG_GPIO_PXA policy<{'arm64': '-'}> +CONFIG_GPIO_RCAR policy<{'arm64': '-'}> +CONFIG_GPIO_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_GPIO_RTD policy<{'arm64': '-'}> +CONFIG_GPIO_SL28CPLD policy<{'arm64': '-'}> +CONFIG_GPIO_SPRD policy<{'arm64': '-'}> +CONFIG_GPIO_TEGRA policy<{'arm64': '-'}> +CONFIG_GPIO_TEGRA186 policy<{'arm64': '-'}> +CONFIG_GPIO_THUNDERX policy<{'arm64': '-'}> +CONFIG_GPIO_TN48M_CPLD policy<{'arm64': '-'}> +CONFIG_GPIO_VF610 policy<{'arm64': '-'}> +CONFIG_GPIO_VISCONTI policy<{'arm64': '-'}> +CONFIG_GPIO_XGENE_SB policy<{'arm64': '-'}> +CONFIG_GPIO_XLP policy<{'arm64': '-'}> +CONFIG_GPIO_ZYNQ policy<{'arm64': '-'}> +CONFIG_GPIO_ZYNQMP_MODEPIN policy<{'arm64': '-'}> +CONFIG_GUNYAH policy<{'arm64': '-'}> +CONFIG_GUNYAH_DRIVERS policy<{'arm64': '-'}> +CONFIG_GUNYAH_IOEVENTFD policy<{'arm64': '-'}> +CONFIG_GUNYAH_IRQFD policy<{'arm64': '-'}> +CONFIG_GUNYAH_PLATFORM_HOOKS policy<{'arm64': '-'}> +CONFIG_GUNYAH_QCOM_PLATFORM policy<{'arm64': '-'}> +CONFIG_GUNYAH_VCPU policy<{'arm64': '-'}> +CONFIG_GUNYAH_WATCHDOG policy<{'arm64': 'y'}> +CONFIG_HAVE_KERNEL_GZIP policy<{'arm64': '-'}> +CONFIG_HAVE_KERNEL_ZSTD policy<{'arm64': '-'}> +CONFIG_HBMC_AM654 policy<{'arm64': '-'}> +CONFIG_HI3660_MBOX policy<{'arm64': '-'}> +CONFIG_HI6220_MBOX policy<{'arm64': '-'}> +CONFIG_HISILICON_IRQ_MBIGEN policy<{'arm64': '-'}> +CONFIG_HISILICON_LPC policy<{'arm64': '-'}> +CONFIG_HISI_DMA policy<{'arm64': '-'}> +CONFIG_HISI_THERMAL policy<{'arm64': '-'}> +CONFIG_HSA_AMD policy<{'arm64': '-'}> +CONFIG_HSA_AMD_SVM policy<{'arm64': '-'}> +CONFIG_HTE_TEGRA194 policy<{'arm64': '-'}> +CONFIG_HTE_TEGRA194_TEST policy<{'arm64': '-'}> +CONFIG_HWSPINLOCK_OMAP policy<{'arm64': '-'}> +CONFIG_HWSPINLOCK_QCOM policy<{'arm64': 'y'}> +CONFIG_HWSPINLOCK_SPRD policy<{'arm64': '-'}> +CONFIG_HWSPINLOCK_SUN6I policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_AIROHA policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_CAVIUM policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_HISI policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_HISTB policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_MESON policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_MTK policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_NPCM policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_OMAP policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_STM32 policy<{'arm64': '-'}> +CONFIG_HW_RANDOM_XGENE policy<{'arm64': '-'}> +CONFIG_I2C_ALTERA policy<{'arm64': '-'}> +CONFIG_I2C_APPLE policy<{'arm64': '-'}> +CONFIG_I2C_DEMUX_PINCTRL policy<{'arm64': 'n'}> +CONFIG_I2C_DESIGNWARE_AMDISP policy<{'arm64': '-'}> +CONFIG_I2C_HIX5HD2 policy<{'arm64': '-'}> +CONFIG_I2C_IMX policy<{'arm64': '-'}> +CONFIG_I2C_IMX_LPI2C policy<{'arm64': '-'}> +CONFIG_I2C_MESON policy<{'arm64': '-'}> +CONFIG_I2C_MT65XX policy<{'arm64': '-'}> +CONFIG_I2C_MT7621 policy<{'arm64': '-'}> +CONFIG_I2C_MUX policy<{'arm64': 'y'}> +CONFIG_I2C_MUX_PCA954x policy<{'arm64': 'y'}> +CONFIG_I2C_MV64XXX policy<{'arm64': '-'}> +CONFIG_I2C_NPCM policy<{'arm64': '-'}> +CONFIG_I2C_OMAP policy<{'arm64': '-'}> +CONFIG_I2C_OWL policy<{'arm64': '-'}> +CONFIG_I2C_PXA policy<{'arm64': '-'}> +CONFIG_I2C_PXA_SLAVE policy<{'arm64': '-'}> +CONFIG_I2C_QUP policy<{'arm64': 'y'}> +CONFIG_I2C_RCAR policy<{'arm64': '-'}> +CONFIG_I2C_RIIC policy<{'arm64': '-'}> +CONFIG_I2C_RZV2M policy<{'arm64': '-'}> +CONFIG_I2C_SH_MOBILE policy<{'arm64': '-'}> +CONFIG_I2C_SPRD policy<{'arm64': '-'}> +CONFIG_I2C_STM32F4 policy<{'arm64': '-'}> +CONFIG_I2C_STM32F7 policy<{'arm64': '-'}> +CONFIG_I2C_SYNQUACER policy<{'arm64': '-'}> +CONFIG_I2C_TEGRA policy<{'arm64': '-'}> +CONFIG_I2C_TEGRA_BPMP policy<{'arm64': '-'}> +CONFIG_I2C_VERSATILE policy<{'arm64': '-'}> +CONFIG_I2C_XGENE_SLIMPRO policy<{'arm64': '-'}> +CONFIG_I2C_XLP9XX policy<{'arm64': '-'}> +CONFIG_IIO_STM32_LPTIMER_TRIGGER policy<{'arm64': '-'}> +CONFIG_IIO_STM32_TIMER_TRIGGER policy<{'arm64': '-'}> +CONFIG_IMX2_WDT policy<{'arm64': '-'}> +CONFIG_IMX7D_ADC policy<{'arm64': '-'}> +CONFIG_IMX7ULP_WDT policy<{'arm64': '-'}> +CONFIG_IMX8MM_THERMAL policy<{'arm64': '-'}> +CONFIG_IMX8M_BLK_CTRL policy<{'arm64': '-'}> +CONFIG_IMX8QXP_ADC policy<{'arm64': '-'}> +CONFIG_IMX91_THERMAL policy<{'arm64': '-'}> +CONFIG_IMX93_ADC policy<{'arm64': '-'}> +CONFIG_IMX9_BLK_CTRL policy<{'arm64': '-'}> +CONFIG_IMX_AIPSTZ policy<{'arm64': '-'}> +CONFIG_IMX_DMA policy<{'arm64': '-'}> +CONFIG_IMX_DSP policy<{'arm64': '-'}> +CONFIG_IMX_DSP_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_IMX_GPCV2 policy<{'arm64': '-'}> +CONFIG_IMX_GPCV2_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_IMX_INTMUX policy<{'arm64': '-'}> +CONFIG_IMX_IRQSTEER policy<{'arm64': '-'}> +CONFIG_IMX_MBOX policy<{'arm64': '-'}> +CONFIG_IMX_MU_MSI policy<{'arm64': '-'}> +CONFIG_IMX_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_IMX_SCMI_CPU_DRV policy<{'arm64': '-'}> +CONFIG_IMX_SCMI_CPU_EXT policy<{'arm64': '-'}> +CONFIG_IMX_SCMI_LMM_DRV policy<{'arm64': '-'}> +CONFIG_IMX_SCMI_LMM_EXT policy<{'arm64': '-'}> +CONFIG_IMX_SCMI_MISC_DRV policy<{'arm64': '-'}> +CONFIG_IMX_SCMI_MISC_EXT policy<{'arm64': '-'}> +CONFIG_IMX_SCU policy<{'arm64': '-'}> +CONFIG_IMX_SCU_PD policy<{'arm64': '-'}> +CONFIG_IMX_SC_THERMAL policy<{'arm64': '-'}> +CONFIG_IMX_SC_WDT policy<{'arm64': '-'}> +CONFIG_IMX_SDMA policy<{'arm64': '-'}> +CONFIG_IMX_THERMAL policy<{'arm64': '-'}> +CONFIG_IMX_WEIM policy<{'arm64': '-'}> +CONFIG_INPUT_BBNSM_PWRKEY policy<{'arm64': '-'}> +CONFIG_INPUT_HISI_POWERKEY policy<{'arm64': '-'}> +CONFIG_INPUT_SC27XX_VIBRA policy<{'arm64': '-'}> +CONFIG_INTEL_MEI policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_GSC policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_GSC_PROXY policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_HDCP policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_LB policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_ME policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_PXP policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_TXE policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_VSC policy<{'arm64': '-'}> +CONFIG_INTEL_MEI_VSC_HW policy<{'arm64': '-'}> +CONFIG_INTEL_STRATIX10_RSU policy<{'arm64': '-'}> +CONFIG_INTEL_STRATIX10_SERVICE policy<{'arm64': '-'}> +CONFIG_INTEL_VSC policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_IMX policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_IMX8MM policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_IMX8MN policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_IMX8MP policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_IMX8MQ policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_MTK policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_MTK_DVFSRC_EMI policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_MTK_MT8183 policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_MTK_MT8195 policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_MTK_MT8196 policy<{'arm64': '-'}> +CONFIG_INTERCONNECT_QCOM_KAANAPALI policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_QCS615 policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_QCS8300 policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_SDM845 policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_SM8450 policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_SM8550 policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_SM8650 policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_X1E80100 policy<{'arm64': 'y'}> +CONFIG_IPMI_KCS_BMC policy<{'arm64': '-'}> +CONFIG_IPMI_KCS_BMC_CDEV_IPMI policy<{'arm64': '-'}> +CONFIG_IPMI_KCS_BMC_SERIO policy<{'arm64': '-'}> +CONFIG_IPQ_APSS_6018 policy<{'arm64': 'y'}> +CONFIG_IPQ_APSS_PLL policy<{'arm64': 'y'}> +CONFIG_IPQ_GCC_5332 policy<{'arm64': 'y'}> +CONFIG_IPQ_GCC_6018 policy<{'arm64': 'y'}> +CONFIG_IPQ_GCC_8074 policy<{'arm64': 'y'}> +CONFIG_IPQ_GCC_9574 policy<{'arm64': 'y'}> +CONFIG_IR_MESON policy<{'arm64': '-'}> +CONFIG_IR_MESON_TX policy<{'arm64': '-'}> +CONFIG_IR_MTK policy<{'arm64': '-'}> +CONFIG_IR_SUNXI policy<{'arm64': '-'}> +CONFIG_K3_DMA policy<{'arm64': '-'}> +CONFIG_K3_RTI_WATCHDOG policy<{'arm64': '-'}> +CONFIG_K3_THERMAL policy<{'arm64': '-'}> +CONFIG_KASAN policy<{'arm64': 'y'}> +CONFIG_KASAN_EXTRA_INFO policy<{'arm64': 'n'}> +CONFIG_KASAN_GENERIC policy<{'arm64': 'n'}> +CONFIG_KASAN_HW_TAGS policy<{'arm64': 'y'}> +CONFIG_KASAN_SW_TAGS policy<{'arm64': 'n'}> +CONFIG_KASAN_VMALLOC policy<{'arm64': 'y'}> +CONFIG_KCSAN policy<{'arm64': '-'}> +CONFIG_KEEMBAY_WATCHDOG policy<{'arm64': '-'}> +CONFIG_KERNEL_GZIP policy<{'arm64': '-'}> +CONFIG_KEYBOARD_IMX policy<{'arm64': '-'}> +CONFIG_KEYBOARD_IMX_SC_KEY policy<{'arm64': '-'}> +CONFIG_KEYBOARD_MT6779 policy<{'arm64': '-'}> +CONFIG_KEYBOARD_NVEC policy<{'arm64': '-'}> +CONFIG_KEYBOARD_PXA27x policy<{'arm64': '-'}> +CONFIG_KEYBOARD_SNVS_PWRKEY policy<{'arm64': '-'}> +CONFIG_KEYBOARD_SUN4I_LRADC policy<{'arm64': '-'}> +CONFIG_KEYBOARD_TEGRA policy<{'arm64': '-'}> +CONFIG_KHADAS_MCU_FAN_THERMAL policy<{'arm64': '-'}> +CONFIG_KUNPENG_HCCS policy<{'arm64': '-'}> +CONFIG_LAN966X_OIC policy<{'arm64': '-'}> +CONFIG_LAN969X_SWITCH policy<{'arm64': '-'}> +CONFIG_LEDS_SC27XX_BLTC policy<{'arm64': '-'}> +CONFIG_LEDS_SUN50I_A100 policy<{'arm64': '-'}> +CONFIG_LEGACY_PTY_COUNT policy<{'arm64': '-'}> +CONFIG_LOG_BUF_SHIFT policy<{'arm64': '17'}> +CONFIG_LSM_MMAP_MIN_ADDR policy<{'arm64': '32768'}> +CONFIG_LS_EXTIRQ policy<{'arm64': '-'}> +CONFIG_LS_SCFG_MSI policy<{'arm64': '-'}> +CONFIG_MARVELL_CN10K_DDR_PMU policy<{'arm64': '-'}> +CONFIG_MARVELL_CN10K_DPI policy<{'arm64': '-'}> +CONFIG_MARVELL_CN10K_TAD_PMU policy<{'arm64': '-'}> +CONFIG_MARVELL_GTI_WDT policy<{'arm64': '-'}> +CONFIG_MARVELL_PEM_PMU policy<{'arm64': '-'}> +CONFIG_MCHP_LAN966X_PCI policy<{'arm64': 'n'}> +CONFIG_MDIO_AIROHA policy<{'arm64': '-'}> +CONFIG_MDIO_BUS_MUX_MESON_G12A policy<{'arm64': '-'}> +CONFIG_MDIO_BUS_MUX_MESON_GXL policy<{'arm64': '-'}> +CONFIG_MDIO_SUN4I policy<{'arm64': '-'}> +CONFIG_MDIO_XGENE policy<{'arm64': '-'}> +CONFIG_MEDIATEK_2P5GE_PHY policy<{'arm64': '-'}> +CONFIG_MEDIATEK_GE_SOC_PHY policy<{'arm64': 'n'}> +CONFIG_MEDIATEK_MT6577_AUXADC policy<{'arm64': '-'}> +CONFIG_MEDIATEK_WATCHDOG policy<{'arm64': '-'}> +CONFIG_MESON_CANVAS policy<{'arm64': '-'}> +CONFIG_MESON_CLK_MEASURE policy<{'arm64': '-'}> +CONFIG_MESON_DDR_PMU policy<{'arm64': '-'}> +CONFIG_MESON_EE_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_MESON_GXBB_WATCHDOG policy<{'arm64': '-'}> +CONFIG_MESON_GXL_PHY policy<{'arm64': '-'}> +CONFIG_MESON_GX_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_MESON_GX_SOCINFO policy<{'arm64': '-'}> +CONFIG_MESON_IRQ_GPIO policy<{'arm64': '-'}> +CONFIG_MESON_SARADC policy<{'arm64': '-'}> +CONFIG_MESON_SECURE_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_MESON_SM policy<{'arm64': '-'}> +CONFIG_MESON_WATCHDOG policy<{'arm64': '-'}> +CONFIG_MFD_AC100 policy<{'arm64': '-'}> +CONFIG_MFD_ALTERA_A10SR policy<{'arm64': '-'}> +CONFIG_MFD_ALTERA_SYSMGR policy<{'arm64': '-'}> +CONFIG_MFD_AXP20X_RSB policy<{'arm64': '-'}> +CONFIG_MFD_HI655X_PMIC policy<{'arm64': '-'}> +CONFIG_MFD_I2C_PMIC policy<{'arm64': '-'}> +CONFIG_MFD_KHADAS_MCU policy<{'arm64': '-'}> +CONFIG_MFD_MACSMC policy<{'arm64': '-'}> +CONFIG_MFD_NVEC policy<{'arm64': '-'}> +CONFIG_MFD_SC27XX_PMIC policy<{'arm64': '-'}> +CONFIG_MFD_SL28CPLD policy<{'arm64': '-'}> +CONFIG_MFD_SPMI_PMIC policy<{'arm64': 'y'}> +CONFIG_MFD_STM32_LPTIMER policy<{'arm64': '-'}> +CONFIG_MFD_STM32_TIMERS policy<{'arm64': '-'}> +CONFIG_MFD_SUN4I_GPADC policy<{'arm64': '-'}> +CONFIG_MFD_SUN6I_PRCM policy<{'arm64': '-'}> +CONFIG_MFD_TI_AM335X_TSCADC policy<{'arm64': '-'}> +CONFIG_MFD_TN48M_CPLD policy<{'arm64': '-'}> +CONFIG_MHI_EP_NET policy<{'arm64': '-'}> +CONFIG_MMC_BLOCK_MINORS policy<{'arm64': '32'}> +CONFIG_MMC_CAVIUM_THUNDERX policy<{'arm64': '-'}> +CONFIG_MMC_CQHCI policy<{'arm64': 'y'}> +CONFIG_MMC_DW policy<{'arm64': 'y'}> +CONFIG_MMC_DW_EXYNOS policy<{'arm64': 'y'}> +CONFIG_MMC_DW_HI3798CV200 policy<{'arm64': 'y'}> +CONFIG_MMC_DW_K3 policy<{'arm64': 'y'}> +CONFIG_MMC_DW_PLTFM policy<{'arm64': 'y'}> +CONFIG_MMC_DW_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_MMC_HSQ policy<{'arm64': 'y'}> +CONFIG_MMC_MESON_GX policy<{'arm64': '-'}> +CONFIG_MMC_MESON_MX_SDIO policy<{'arm64': '-'}> +CONFIG_MMC_MTK policy<{'arm64': 'y'}> +CONFIG_MMC_MXC policy<{'arm64': '-'}> +CONFIG_MMC_OWL policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_ACPI policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_AM654 policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_CADENCE policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_ESDHC_IMX policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_F_SDH30 policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_MSM policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_NPCM policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_OF_ARASAN policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_OF_DWCMSHC policy<{'arm64': 'y'}> +CONFIG_MMC_SDHCI_OF_ESDHC policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_OF_MA35D1 policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_OF_SPARX5 policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_PXAV2 policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_PXAV3 policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_SPRD policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_TEGRA policy<{'arm64': '-'}> +CONFIG_MMC_SDHCI_XENON policy<{'arm64': 'y'}> +CONFIG_MMC_SDHI policy<{'arm64': '-'}> +CONFIG_MMC_SDHI_INTERNAL_DMAC policy<{'arm64': '-'}> +CONFIG_MMC_SDHI_SYS_DMAC policy<{'arm64': '-'}> +CONFIG_MMC_SH_MMCIF policy<{'arm64': '-'}> +CONFIG_MMC_SPI policy<{'arm64': 'y'}> +CONFIG_MMC_SUNXI policy<{'arm64': '-'}> +CONFIG_MMC_TMIO_CORE policy<{'arm64': '-'}> +CONFIG_MMP_PDMA policy<{'arm64': '-'}> +CONFIG_MMP_TDMA policy<{'arm64': '-'}> +CONFIG_MSM_GCC_8916 policy<{'arm64': 'y'}> +CONFIG_MSM_GCC_8994 policy<{'arm64': 'y'}> +CONFIG_MSM_GCC_8998 policy<{'arm64': 'y'}> +CONFIG_MSM_RDBG policy<{'arm64': '-'}> +CONFIG_MST_IRQ policy<{'arm64': '-'}> +CONFIG_MT7622_WMAC policy<{'arm64': '-'}> +CONFIG_MT76_NPU policy<{'arm64': '-'}> +CONFIG_MT798X_WMAC policy<{'arm64': '-'}> +CONFIG_MT7996_NPU policy<{'arm64': '-'}> +CONFIG_MTD_INTEL_DG policy<{'arm64': '-'}> +CONFIG_MTD_NAND_ECC_MEDIATEK policy<{'arm64': '-'}> +CONFIG_MTD_NAND_FSL_IFC policy<{'arm64': '-'}> +CONFIG_MTD_NAND_GPMI_NAND policy<{'arm64': '-'}> +CONFIG_MTD_NAND_HISI504 policy<{'arm64': '-'}> +CONFIG_MTD_NAND_MARVELL policy<{'arm64': '-'}> +CONFIG_MTD_NAND_MESON policy<{'arm64': '-'}> +CONFIG_MTD_NAND_MTK policy<{'arm64': '-'}> +CONFIG_MTD_NAND_MXC policy<{'arm64': '-'}> +CONFIG_MTD_NAND_NUVOTON_MA35 policy<{'arm64': '-'}> +CONFIG_MTD_NAND_OMAP2 policy<{'arm64': '-'}> +CONFIG_MTD_NAND_OMAP_BCH policy<{'arm64': '-'}> +CONFIG_MTD_NAND_OMAP_BCH_BUILD policy<{'arm64': '-'}> +CONFIG_MTD_NAND_RENESAS policy<{'arm64': '-'}> +CONFIG_MTD_NAND_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_MTD_NAND_STM32_FMC2 policy<{'arm64': '-'}> +CONFIG_MTD_NAND_SUNXI policy<{'arm64': '-'}> +CONFIG_MTD_NAND_TEGRA policy<{'arm64': '-'}> +CONFIG_MTD_PARSER_TRX policy<{'arm64': '-'}> +CONFIG_MTK_ADSP_IPC policy<{'arm64': '-'}> +CONFIG_MTK_ADSP_MBOX policy<{'arm64': '-'}> +CONFIG_MTK_CMDQ policy<{'arm64': '-'}> +CONFIG_MTK_CMDQ_MBOX policy<{'arm64': '-'}> +CONFIG_MTK_CPUX_TIMER policy<{'arm64': '-'}> +CONFIG_MTK_CQDMA policy<{'arm64': '-'}> +CONFIG_MTK_DEVAPC policy<{'arm64': '-'}> +CONFIG_MTK_DVFSRC policy<{'arm64': '-'}> +CONFIG_MTK_GPUEB_MBOX policy<{'arm64': '-'}> +CONFIG_MTK_HSDMA policy<{'arm64': '-'}> +CONFIG_MTK_INFRACFG policy<{'arm64': '-'}> +CONFIG_MTK_IOMMU policy<{'arm64': '-'}> +CONFIG_MTK_LVTS_THERMAL policy<{'arm64': '-'}> +CONFIG_MTK_LVTS_THERMAL_DEBUGFS policy<{'arm64': '-'}> +CONFIG_MTK_MFG_PM_DOMAIN policy<{'arm64': '-'}> +CONFIG_MTK_MMSYS policy<{'arm64': '-'}> +CONFIG_MTK_PMIC_WRAP policy<{'arm64': '-'}> +CONFIG_MTK_REGULATOR_COUPLER policy<{'arm64': '-'}> +CONFIG_MTK_SCP policy<{'arm64': '-'}> +CONFIG_MTK_SCPSYS policy<{'arm64': '-'}> +CONFIG_MTK_SCPSYS_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_MTK_SMI policy<{'arm64': '-'}> +CONFIG_MTK_SOCINFO policy<{'arm64': '-'}> +CONFIG_MTK_SOC_THERMAL policy<{'arm64': '-'}> +CONFIG_MTK_SVS policy<{'arm64': '-'}> +CONFIG_MTK_THERMAL policy<{'arm64': '-'}> +CONFIG_MTK_TIMER policy<{'arm64': '-'}> +CONFIG_MTK_UART_APDMA policy<{'arm64': '-'}> +CONFIG_MTK_VCP_MBOX policy<{'arm64': '-'}> +CONFIG_MULTIPLEXER policy<{'arm64': 'm'}> +CONFIG_MVEBU_GICP policy<{'arm64': '-'}> +CONFIG_MVEBU_ICU policy<{'arm64': '-'}> +CONFIG_MVEBU_ODMI policy<{'arm64': '-'}> +CONFIG_MVEBU_PIC policy<{'arm64': '-'}> +CONFIG_MVEBU_SEI policy<{'arm64': '-'}> +CONFIG_MVNETA policy<{'arm64': '-'}> +CONFIG_MVPP2 policy<{'arm64': '-'}> +CONFIG_MVPP2_PTP policy<{'arm64': '-'}> +CONFIG_MV_XOR policy<{'arm64': '-'}> +CONFIG_MXC_CLK policy<{'arm64': '-'}> +CONFIG_MXC_CLK_SCU policy<{'arm64': '-'}> +CONFIG_MXS_DMA policy<{'arm64': '-'}> +CONFIG_NET_AIROHA policy<{'arm64': '-'}> +CONFIG_NET_AIROHA_FLOW_STATS policy<{'arm64': '-'}> +CONFIG_NET_AIROHA_NPU policy<{'arm64': '-'}> +CONFIG_NET_VENDOR_ACTIONS policy<{'arm64': '-'}> +CONFIG_NET_VENDOR_AIROHA policy<{'arm64': '-'}> +CONFIG_NET_VENDOR_ALLWINNER policy<{'arm64': '-'}> +CONFIG_NET_VENDOR_MEDIATEK policy<{'arm64': '-'}> +CONFIG_NET_XGENE policy<{'arm64': '-'}> +CONFIG_NET_XGENE_V2 policy<{'arm64': '-'}> +CONFIG_NFC_MEI_PHY policy<{'arm64': '-'}> +CONFIG_NFC_MICROREAD_MEI policy<{'arm64': '-'}> +CONFIG_NFC_PN544_MEI policy<{'arm64': '-'}> +CONFIG_NL80211_TESTMODE policy<{'arm64': 'y'}> +CONFIG_NLS_DEFAULT policy<{'arm64': '"iso8859-1"'}> +CONFIG_NODES_SHIFT policy<{'arm64': '4'}> +CONFIG_NOUVEAU_DEBUG policy<{'arm64': '-'}> +CONFIG_NOUVEAU_DEBUG_DEFAULT policy<{'arm64': '-'}> +CONFIG_NOUVEAU_DEBUG_MMU policy<{'arm64': '-'}> +CONFIG_NOUVEAU_DEBUG_PUSH policy<{'arm64': '-'}> +CONFIG_NOUVEAU_PLATFORM_DRIVER policy<{'arm64': '-'}> +CONFIG_NPCM7XX_KCS_IPMI_BMC policy<{'arm64': '-'}> +CONFIG_NPCM7XX_TIMER policy<{'arm64': '-'}> +CONFIG_NPCM7XX_WATCHDOG policy<{'arm64': '-'}> +CONFIG_NPCM_ADC policy<{'arm64': '-'}> +CONFIG_NVEC_PAZ00 policy<{'arm64': '-'}> +CONFIG_NVEC_POWER policy<{'arm64': '-'}> +CONFIG_NVMEM_APPLE_EFUSES policy<{'arm64': '-'}> +CONFIG_NVMEM_APPLE_SPMI policy<{'arm64': '-'}> +CONFIG_NVMEM_IMX_IIM policy<{'arm64': '-'}> +CONFIG_NVMEM_IMX_OCOTP policy<{'arm64': '-'}> +CONFIG_NVMEM_IMX_OCOTP_ELE policy<{'arm64': '-'}> +CONFIG_NVMEM_IMX_OCOTP_SCU policy<{'arm64': '-'}> +CONFIG_NVMEM_LAYERSCAPE_SFP policy<{'arm64': '-'}> +CONFIG_NVMEM_MESON_EFUSE policy<{'arm64': '-'}> +CONFIG_NVMEM_MESON_MX_EFUSE policy<{'arm64': '-'}> +CONFIG_NVMEM_MTK_EFUSE policy<{'arm64': '-'}> +CONFIG_NVMEM_QCOM_QFPROM policy<{'arm64': 'y'}> +CONFIG_NVMEM_RCAR_EFUSE policy<{'arm64': '-'}> +CONFIG_NVMEM_ROCKCHIP_EFUSE policy<{'arm64': '-'}> +CONFIG_NVMEM_ROCKCHIP_OTP policy<{'arm64': '-'}> +CONFIG_NVMEM_S32G_OCOTP policy<{'arm64': '-'}> +CONFIG_NVMEM_SC27XX_EFUSE policy<{'arm64': '-'}> +CONFIG_NVMEM_SNVS_LPGPR policy<{'arm64': '-'}> +CONFIG_NVMEM_SPRD_EFUSE policy<{'arm64': '-'}> +CONFIG_NVMEM_STM32_BSEC_OPTEE_TA policy<{'arm64': '-'}> +CONFIG_NVMEM_STM32_ROMEM policy<{'arm64': '-'}> +CONFIG_NVMEM_SUNXI_SID policy<{'arm64': '-'}> +CONFIG_NVMEM_ZYNQMP policy<{'arm64': '-'}> +CONFIG_NVME_APPLE policy<{'arm64': '-'}> +CONFIG_NXP_SAR_ADC policy<{'arm64': '-'}> +CONFIG_NXP_STM_TIMER policy<{'arm64': '-'}> +CONFIG_OLPC_EC policy<{'arm64': '-'}> +CONFIG_OLPC_XO175 policy<{'arm64': '-'}> +CONFIG_OLPC_XO175_EC policy<{'arm64': '-'}> +CONFIG_OMAP2PLUS_MBOX policy<{'arm64': '-'}> +CONFIG_OMAP_DM_TIMER policy<{'arm64': '-'}> +CONFIG_OMAP_GPMC policy<{'arm64': '-'}> +CONFIG_OMAP_GPMC_DEBUG policy<{'arm64': '-'}> +CONFIG_OMAP_MBOX_KFIFO_SIZE policy<{'arm64': '-'}> +CONFIG_OMAP_USB2 policy<{'arm64': '-'}> +CONFIG_OWL_DMA policy<{'arm64': '-'}> +CONFIG_OWL_EMAC policy<{'arm64': '-'}> +CONFIG_OWL_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_OWL_PM_DOMAINS_HELPER policy<{'arm64': '-'}> +CONFIG_OWL_TIMER policy<{'arm64': '-'}> +CONFIG_PAGE_BLOCK_MAX_ORDER policy<{'arm64': '10'}> +CONFIG_PANIC_TIMEOUT policy<{'arm64': '-1'}> +CONFIG_PATA_IMX policy<{'arm64': '-'}> +CONFIG_PCIE_APPLE policy<{'arm64': '-'}> +CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR policy<{'arm64': '-'}> +CONFIG_PCIE_ARMADA_8K policy<{'arm64': '-'}> +CONFIG_PCIE_HISI_STB policy<{'arm64': '-'}> +CONFIG_PCIE_KEEMBAY policy<{'arm64': '-'}> +CONFIG_PCIE_KEEMBAY_EP policy<{'arm64': '-'}> +CONFIG_PCIE_KEEMBAY_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_LAYERSCAPE_GEN4 policy<{'arm64': '-'}> +CONFIG_PCIE_MEDIATEK policy<{'arm64': '-'}> +CONFIG_PCIE_MEDIATEK_GEN3 policy<{'arm64': '-'}> +CONFIG_PCIE_MOBIVEIL_PLAT policy<{'arm64': '-'}> +CONFIG_PCIE_NXP_S32G policy<{'arm64': '-'}> +CONFIG_PCIE_QCOM_EP policy<{'arm64': 'n'}> +CONFIG_PCIE_RCAR_EP policy<{'arm64': '-'}> +CONFIG_PCIE_RCAR_GEN4 policy<{'arm64': '-'}> +CONFIG_PCIE_RCAR_GEN4_EP policy<{'arm64': '-'}> +CONFIG_PCIE_RCAR_GEN4_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_RCAR_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_RENESAS_RZG3S_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_PCIE_ROCKCHIP_DW policy<{'arm64': '-'}> +CONFIG_PCIE_ROCKCHIP_DW_EP policy<{'arm64': '-'}> +CONFIG_PCIE_ROCKCHIP_DW_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_ROCKCHIP_EP policy<{'arm64': '-'}> +CONFIG_PCIE_ROCKCHIP_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_SG2042_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_SOPHGO_DW policy<{'arm64': '-'}> +CONFIG_PCIE_STM32_EP policy<{'arm64': '-'}> +CONFIG_PCIE_STM32_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_TEGRA194 policy<{'arm64': '-'}> +CONFIG_PCIE_TEGRA194_EP policy<{'arm64': '-'}> +CONFIG_PCIE_TEGRA194_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_VISCONTI_HOST policy<{'arm64': '-'}> +CONFIG_PCIE_XILINX_CPM policy<{'arm64': '-'}> +CONFIG_PCIE_XILINX_DMA_PL policy<{'arm64': '-'}> +CONFIG_PCIE_XILINX_NWL policy<{'arm64': '-'}> +CONFIG_PCI_AARDVARK policy<{'arm64': '-'}> +CONFIG_PCI_BRIDGE_EMUL policy<{'arm64': '-'}> +CONFIG_PCI_IMX6 policy<{'arm64': '-'}> +CONFIG_PCI_IMX6_EP policy<{'arm64': '-'}> +CONFIG_PCI_IMX6_HOST policy<{'arm64': '-'}> +CONFIG_PCI_J721E policy<{'arm64': '-'}> +CONFIG_PCI_J721E_EP policy<{'arm64': '-'}> +CONFIG_PCI_J721E_HOST policy<{'arm64': '-'}> +CONFIG_PCI_KEYSTONE policy<{'arm64': '-'}> +CONFIG_PCI_KEYSTONE_EP policy<{'arm64': '-'}> +CONFIG_PCI_KEYSTONE_HOST policy<{'arm64': '-'}> +CONFIG_PCI_KEYSTONE_TRISTATE policy<{'arm64': '-'}> +CONFIG_PCI_LAYERSCAPE policy<{'arm64': '-'}> +CONFIG_PCI_LAYERSCAPE_EP policy<{'arm64': '-'}> +CONFIG_PCI_PWRCTL policy<{'arm64': '-'}> +CONFIG_PCI_PWRCTL_PWRSEQ policy<{'arm64': '-'}> +CONFIG_PCI_PWRCTRL_TC9563 policy<{'arm64': 'y'}> +CONFIG_PCI_SKY1_HOST policy<{'arm64': '-'}> +CONFIG_PCI_TEGRA policy<{'arm64': '-'}> +CONFIG_PCS_LYNX policy<{'arm64': 'm'}> +CONFIG_PCS_RZN1_MIIC policy<{'arm64': '-'}> +CONFIG_PECI_NPCM policy<{'arm64': '-'}> +CONFIG_PHYLINK policy<{'arm64': 'm'}> +CONFIG_PHY_AIROHA_PCIE policy<{'arm64': '-'}> +CONFIG_PHY_AM654_SERDES policy<{'arm64': '-'}> +CONFIG_PHY_APPLE_ATC policy<{'arm64': '-'}> +CONFIG_PHY_BERLIN_SATA policy<{'arm64': '-'}> +CONFIG_PHY_BERLIN_USB policy<{'arm64': '-'}> +CONFIG_PHY_FSL_IMX8MQ_USB policy<{'arm64': '-'}> +CONFIG_PHY_FSL_IMX8M_PCIE policy<{'arm64': '-'}> +CONFIG_PHY_FSL_IMX8QM_HSIO policy<{'arm64': '-'}> +CONFIG_PHY_FSL_LYNX_28G policy<{'arm64': '-'}> +CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY policy<{'arm64': '-'}> +CONFIG_PHY_HI3660_USB policy<{'arm64': '-'}> +CONFIG_PHY_HI3670_PCIE policy<{'arm64': '-'}> +CONFIG_PHY_HI3670_USB policy<{'arm64': '-'}> +CONFIG_PHY_HI6220_USB policy<{'arm64': '-'}> +CONFIG_PHY_HISI_INNO_USB2 policy<{'arm64': '-'}> +CONFIG_PHY_HISTB_COMBPHY policy<{'arm64': '-'}> +CONFIG_PHY_INTEL_KEEMBAY_EMMC policy<{'arm64': '-'}> +CONFIG_PHY_INTEL_KEEMBAY_USB policy<{'arm64': '-'}> +CONFIG_PHY_J721E_WIZ policy<{'arm64': '-'}> +CONFIG_PHY_LAN966X_SERDES policy<{'arm64': '-'}> +CONFIG_PHY_MA35_USB policy<{'arm64': '-'}> +CONFIG_PHY_MESON8B_USB2 policy<{'arm64': '-'}> +CONFIG_PHY_MESON_AXG_MIPI_DPHY policy<{'arm64': '-'}> +CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG policy<{'arm64': '-'}> +CONFIG_PHY_MESON_AXG_PCIE policy<{'arm64': '-'}> +CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG policy<{'arm64': '-'}> +CONFIG_PHY_MESON_G12A_USB2 policy<{'arm64': '-'}> +CONFIG_PHY_MESON_G12A_USB3_PCIE policy<{'arm64': '-'}> +CONFIG_PHY_MESON_GXL_USB2 policy<{'arm64': '-'}> +CONFIG_PHY_MIXEL_LVDS_PHY policy<{'arm64': '-'}> +CONFIG_PHY_MIXEL_MIPI_DPHY policy<{'arm64': '-'}> +CONFIG_PHY_MTK_DP policy<{'arm64': '-'}> +CONFIG_PHY_MTK_HDMI policy<{'arm64': '-'}> +CONFIG_PHY_MTK_MIPI_CSI_0_5 policy<{'arm64': '-'}> +CONFIG_PHY_MTK_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_PHY_MTK_PCIE policy<{'arm64': '-'}> +CONFIG_PHY_MTK_TPHY policy<{'arm64': '-'}> +CONFIG_PHY_MTK_UFS policy<{'arm64': '-'}> +CONFIG_PHY_MTK_XFI_TPHY policy<{'arm64': '-'}> +CONFIG_PHY_MTK_XSPHY policy<{'arm64': '-'}> +CONFIG_PHY_MVEBU_A3700_COMPHY policy<{'arm64': '-'}> +CONFIG_PHY_MVEBU_A3700_UTMI policy<{'arm64': '-'}> +CONFIG_PHY_MVEBU_A38X_COMPHY policy<{'arm64': '-'}> +CONFIG_PHY_MVEBU_CP110_COMPHY policy<{'arm64': '-'}> +CONFIG_PHY_MVEBU_CP110_UTMI policy<{'arm64': '-'}> +CONFIG_PHY_PXA_USB policy<{'arm64': '-'}> +CONFIG_PHY_QCOM_QMP policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_PCIE policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_PCIE_8996 policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_UFS policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_QMP_USB policy<{'arm64': 'y'}> +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 policy<{'arm64': 'y'}> +CONFIG_PHY_R8A779F0_ETHERNET_SERDES policy<{'arm64': '-'}> +CONFIG_PHY_RCAR_GEN2 policy<{'arm64': '-'}> +CONFIG_PHY_RCAR_GEN3_PCIE policy<{'arm64': '-'}> +CONFIG_PHY_RCAR_GEN3_USB2 policy<{'arm64': '-'}> +CONFIG_PHY_RCAR_GEN3_USB3 policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_DP policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_DPHY_RX0 policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_EMMC policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_INNO_HDMI policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_INNO_USB2 policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_PCIE policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_TYPEC policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_USB policy<{'arm64': '-'}> +CONFIG_PHY_ROCKCHIP_USBDP policy<{'arm64': '-'}> +CONFIG_PHY_RTK_RTD_USB2PHY policy<{'arm64': '-'}> +CONFIG_PHY_RTK_RTD_USB3PHY policy<{'arm64': '-'}> +CONFIG_PHY_RZ_G3E_USB3 policy<{'arm64': '-'}> +CONFIG_PHY_SOPHGO_CV1800_USB2 policy<{'arm64': '-'}> +CONFIG_PHY_STM32_COMBOPHY policy<{'arm64': '-'}> +CONFIG_PHY_STM32_USBPHYC policy<{'arm64': '-'}> +CONFIG_PHY_SUN4I_USB policy<{'arm64': '-'}> +CONFIG_PHY_SUN50I_USB3 policy<{'arm64': '-'}> +CONFIG_PHY_SUN6I_MIPI_DPHY policy<{'arm64': '-'}> +CONFIG_PHY_SUN9I_USB policy<{'arm64': '-'}> +CONFIG_PHY_TEGRA194_P2U policy<{'arm64': '-'}> +CONFIG_PHY_TEGRA_XUSB policy<{'arm64': '-'}> +CONFIG_PHY_TI_GMII_SEL policy<{'arm64': '-'}> +CONFIG_PHY_XGENE policy<{'arm64': '-'}> +CONFIG_PHY_XILINX_ZYNQMP policy<{'arm64': '-'}> +CONFIG_PINCTRL_AC5 policy<{'arm64': '-'}> +CONFIG_PINCTRL_AIROHA policy<{'arm64': '-'}> +CONFIG_PINCTRL_AMDISP policy<{'arm64': '-'}> +CONFIG_PINCTRL_AMLOGIC_A4 policy<{'arm64': '-'}> +CONFIG_PINCTRL_AMLOGIC_C3 policy<{'arm64': '-'}> +CONFIG_PINCTRL_AMLOGIC_T7 policy<{'arm64': '-'}> +CONFIG_PINCTRL_APPLE_GPIO policy<{'arm64': '-'}> +CONFIG_PINCTRL_ARMADA_37XX policy<{'arm64': '-'}> +CONFIG_PINCTRL_ARMADA_AP806 policy<{'arm64': '-'}> +CONFIG_PINCTRL_ARMADA_CP110 policy<{'arm64': '-'}> +CONFIG_PINCTRL_AS370 policy<{'arm64': '-'}> +CONFIG_PINCTRL_BERLIN policy<{'arm64': '-'}> +CONFIG_PINCTRL_BERLIN_BG4CT policy<{'arm64': '-'}> +CONFIG_PINCTRL_BM1880 policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX8DXL policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX8MM policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX8MN policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX8MP policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX8MQ policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX8QM policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX8QXP policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX8ULP policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX91 policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX93 policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMXRT1050 policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMXRT1170 policy<{'arm64': '-'}> +CONFIG_PINCTRL_IMX_SCU policy<{'arm64': '-'}> +CONFIG_PINCTRL_IPQ5332 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IPQ6018 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IPQ8074 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IPQ9574 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_KAANAPALI policy<{'arm64': 'n'}> +CONFIG_PINCTRL_KEEMBAY policy<{'arm64': '-'}> +CONFIG_PINCTRL_MA35 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MA35D1 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON8_PMX policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON_A1 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON_AXG policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON_AXG_PMX policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON_G12A policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON_GXBB policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON_GXL policy<{'arm64': '-'}> +CONFIG_PINCTRL_MESON_S4 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MSM8916 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MSM8953 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MSM8976 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MSM8994 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MSM8996 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MSM8998 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT2712 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT6397 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT6765 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT6779 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT6795 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT6797 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT6878 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT6893 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT7622 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT7981 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT7986 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT7988 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8167 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8173 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8183 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8186 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8188 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8189 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8192 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8195 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8196 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8365 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MT8516 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MTK policy<{'arm64': '-'}> +CONFIG_PINCTRL_MTK_MOORE policy<{'arm64': '-'}> +CONFIG_PINCTRL_MTK_PARIS policy<{'arm64': '-'}> +CONFIG_PINCTRL_MTK_V2 policy<{'arm64': '-'}> +CONFIG_PINCTRL_MVEBU policy<{'arm64': '-'}> +CONFIG_PINCTRL_NPCM8XX policy<{'arm64': '-'}> +CONFIG_PINCTRL_OWL policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A774A1 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A774B1 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A774C0 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A774E1 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A77951 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A77960 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A77961 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A77965 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A77970 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A77980 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A77990 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A77995 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A779A0 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A779F0 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A779G0 policy<{'arm64': '-'}> +CONFIG_PINCTRL_PFC_R8A779H0 policy<{'arm64': '-'}> +CONFIG_PINCTRL_QCM2290 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QCOM_SPMI_PMIC policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QCS404 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QCS615 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QCS8300 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QCS8300_LPASS_LPI policy<{'arm64': '-'}> +CONFIG_PINCTRL_QDF2XXX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QDU1000 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RENESAS policy<{'arm64': '-'}> +CONFIG_PINCTRL_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_PINCTRL_RTD policy<{'arm64': '-'}> +CONFIG_PINCTRL_RTD1315E policy<{'arm64': '-'}> +CONFIG_PINCTRL_RTD1319D policy<{'arm64': '-'}> +CONFIG_PINCTRL_RTD1619B policy<{'arm64': '-'}> +CONFIG_PINCTRL_RZG2L policy<{'arm64': '-'}> +CONFIG_PINCTRL_RZT2H policy<{'arm64': '-'}> +CONFIG_PINCTRL_RZV2M policy<{'arm64': '-'}> +CONFIG_PINCTRL_S32CC policy<{'arm64': '-'}> +CONFIG_PINCTRL_S32G2 policy<{'arm64': '-'}> +CONFIG_PINCTRL_S700 policy<{'arm64': '-'}> +CONFIG_PINCTRL_S900 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SA7255P policy<{'arm64': '-'}> +CONFIG_PINCTRL_SA8775P_LPASS_LPI policy<{'arm64': '-'}> +CONFIG_PINCTRL_SA8797P policy<{'arm64': '-'}> +CONFIG_PINCTRL_SDM660 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SDM670 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SDM845 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SHIKRA policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SH_PFC policy<{'arm64': '-'}> +CONFIG_PINCTRL_SKY1 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SKY1_BASE policy<{'arm64': '-'}> +CONFIG_PINCTRL_SM6115 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM6125 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM6350 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM6375 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM8150 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM8250 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM8350 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM8450 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM8550 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SM8650 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SOPHGO_COMMON policy<{'arm64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV1800B policy<{'arm64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV1812H policy<{'arm64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV18XX_OPS policy<{'arm64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2000 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2002 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2042 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2042_OPS policy<{'arm64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2044 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SPRD policy<{'arm64': '-'}> +CONFIG_PINCTRL_SPRD_SC9860 policy<{'arm64': '-'}> +CONFIG_PINCTRL_STM32 policy<{'arm64': '-'}> +CONFIG_PINCTRL_STM32MP257 policy<{'arm64': '-'}> +CONFIG_PINCTRL_STM32_HDP policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN20I_D1 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN4I_A10 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_A100 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_A100_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_A64 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_A64_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_H5 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_H6 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_H616 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_H616_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN50I_H6_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN55I_A523 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN55I_A523_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN5I policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN6I_A31 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN6I_A31_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN8I_A23 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN8I_A23_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN8I_A33 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN8I_A83T policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN8I_A83T_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN8I_H3 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN8I_H3_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN8I_V3S policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN9I_A80 policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUN9I_A80_R policy<{'arm64': '-'}> +CONFIG_PINCTRL_SUNXI policy<{'arm64': '-'}> +CONFIG_PINCTRL_TEGRA policy<{'arm64': '-'}> +CONFIG_PINCTRL_TEGRA124 policy<{'arm64': '-'}> +CONFIG_PINCTRL_TEGRA186 policy<{'arm64': '-'}> +CONFIG_PINCTRL_TEGRA194 policy<{'arm64': '-'}> +CONFIG_PINCTRL_TEGRA210 policy<{'arm64': '-'}> +CONFIG_PINCTRL_TEGRA234 policy<{'arm64': '-'}> +CONFIG_PINCTRL_TEGRA_XUSB policy<{'arm64': '-'}> +CONFIG_PINCTRL_TMPV7700 policy<{'arm64': '-'}> +CONFIG_PINCTRL_VISCONTI policy<{'arm64': '-'}> +CONFIG_PINCTRL_X1E80100 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ZYNQMP policy<{'arm64': '-'}> +CONFIG_PM_AUTOSLEEP policy<{'arm64': 'y'}> +CONFIG_PM_WAKELOCKS_LIMIT policy<{'arm64': '0'}> +CONFIG_POWER_RESET_HISI policy<{'arm64': '-'}> +CONFIG_POWER_RESET_LINKSTATION policy<{'arm64': '-'}> +CONFIG_POWER_RESET_MACSMC policy<{'arm64': '-'}> +CONFIG_POWER_RESET_OCELOT_RESET policy<{'arm64': '-'}> +CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF policy<{'arm64': '-'}> +CONFIG_POWER_RESET_SC27XX policy<{'arm64': '-'}> +CONFIG_POWER_RESET_TORADEX_EC policy<{'arm64': '-'}> +CONFIG_PRU_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_PTP_QCOM_CLOCK_TSC policy<{'arm64': '-'}> +CONFIG_PWC_RZV2M policy<{'arm64': '-'}> +CONFIG_PWM_AIROHA policy<{'arm64': '-'}> +CONFIG_PWM_APPLE policy<{'arm64': '-'}> +CONFIG_PWM_AXI_PWMGEN policy<{'arm64': '-'}> +CONFIG_PWM_BERLIN policy<{'arm64': '-'}> +CONFIG_PWM_HIBVT policy<{'arm64': '-'}> +CONFIG_PWM_IMX1 policy<{'arm64': '-'}> +CONFIG_PWM_IMX27 policy<{'arm64': '-'}> +CONFIG_PWM_IMX_TPM policy<{'arm64': '-'}> +CONFIG_PWM_KEEMBAY policy<{'arm64': '-'}> +CONFIG_PWM_MEDIATEK policy<{'arm64': '-'}> +CONFIG_PWM_MESON policy<{'arm64': '-'}> +CONFIG_PWM_MTK_DISP policy<{'arm64': '-'}> +CONFIG_PWM_OMAP_DMTIMER policy<{'arm64': '-'}> +CONFIG_PWM_PXA policy<{'arm64': '-'}> +CONFIG_PWM_RCAR policy<{'arm64': '-'}> +CONFIG_PWM_RENESAS_RCAR policy<{'arm64': '-'}> +CONFIG_PWM_RENESAS_RZG2L_GPT policy<{'arm64': '-'}> +CONFIG_PWM_RENESAS_RZ_MTU3 policy<{'arm64': '-'}> +CONFIG_PWM_RENESAS_TPU policy<{'arm64': '-'}> +CONFIG_PWM_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_PWM_RZ_MTU3 policy<{'arm64': '-'}> +CONFIG_PWM_SL28CPLD policy<{'arm64': '-'}> +CONFIG_PWM_SOPHGO_SG2042 policy<{'arm64': '-'}> +CONFIG_PWM_SPRD policy<{'arm64': '-'}> +CONFIG_PWM_STM32 policy<{'arm64': '-'}> +CONFIG_PWM_STM32_LP policy<{'arm64': '-'}> +CONFIG_PWM_SUN4I policy<{'arm64': '-'}> +CONFIG_PWM_TEGRA policy<{'arm64': '-'}> +CONFIG_PWM_TIECAP policy<{'arm64': '-'}> +CONFIG_PWM_TIEHRPWM policy<{'arm64': '-'}> +CONFIG_PWM_VISCONTI policy<{'arm64': '-'}> +CONFIG_PXA168_ETH policy<{'arm64': '-'}> +CONFIG_PXA1908_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_PXA_DMA policy<{'arm64': '-'}> +CONFIG_PXA_SSP policy<{'arm64': '-'}> +CONFIG_QCM_GCC_2290 policy<{'arm64': 'y'}> +CONFIG_QCOM_A53PLL policy<{'arm64': 'y'}> +CONFIG_QCOM_AOSS_QMP policy<{'arm64': 'y'}> +CONFIG_QCOM_APCS_IPC policy<{'arm64': 'y'}> +CONFIG_QCOM_APR policy<{'arm64': 'y'}> +CONFIG_QCOM_BAM_DMA policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_APCC_MSM8996 policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_APCS_MSM8916 policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_SMD_RPM policy<{'arm64': 'y'}> +CONFIG_QCOM_CPR policy<{'arm64': 'y'}> +CONFIG_QCOM_CPUCP_MBOX policy<{'arm64': 'y'}> +CONFIG_QCOM_DCC policy<{'arm64': 'y'}> +CONFIG_QCOM_DCC_DEV policy<{'arm64': 'y'}> +CONFIG_QCOM_DMABUF_HEAPS policy<{'arm64': '-'}> +CONFIG_QCOM_DMABUF_HEAPS_CARVEOUT policy<{'arm64': '-'}> +CONFIG_QCOM_DMABUF_HEAPS_CMA policy<{'arm64': '-'}> +CONFIG_QCOM_DMABUF_HEAPS_PAGE_POOL_REFILL policy<{'arm64': '-'}> +CONFIG_QCOM_DMABUF_HEAPS_SYSTEM policy<{'arm64': '-'}> +CONFIG_QCOM_DMABUF_HEAPS_SYSTEM_SECURE policy<{'arm64': '-'}> +CONFIG_QCOM_DMABUF_HEAPS_SYSTEM_UNCACHED policy<{'arm64': '-'}> +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC policy<{'arm64': '-'}> +CONFIG_QCOM_HFPLL policy<{'arm64': 'y'}> +CONFIG_QCOM_HIDMA policy<{'arm64': 'y'}> +CONFIG_QCOM_HIDMA_MGMT policy<{'arm64': 'y'}> +CONFIG_QCOM_INLINE_CRYPTO_ENGINE policy<{'arm64': 'y'}> +CONFIG_QCOM_KVM_ENABLED policy<{'arm64': '-'}> +CONFIG_QCOM_MEMORY_DUMP_DEV policy<{'arm64': 'y'}> +CONFIG_QCOM_MEMORY_DUMP_V2 policy<{'arm64': 'y'}> +CONFIG_QCOM_MEM_BUF policy<{'arm64': '-'}> +CONFIG_QCOM_MEM_BUF_DEV policy<{'arm64': '-'}> +CONFIG_QCOM_MINIDUMP policy<{'arm64': '-'}> +CONFIG_QCOM_MPM policy<{'arm64': 'y'}> +CONFIG_QCOM_PANEL_EVENT_NOTIFIER policy<{'arm64': '-'}> +CONFIG_QCOM_PDR_HELPERS policy<{'arm64': 'y'}> +CONFIG_QCOM_PDR_MSG policy<{'arm64': 'y'}> +CONFIG_QCOM_QMI_COOLING policy<{'arm64': 'm'}> +CONFIG_QCOM_QMI_HELPERS policy<{'arm64': 'y'}> +CONFIG_QCOM_QPS615_PCIE_SWITCH policy<{'arm64': '-'}> +CONFIG_QCOM_RPMPD policy<{'arm64': 'y'}> +CONFIG_QCOM_RPROC_MINIDUMP policy<{'arm64': '-'}> +CONFIG_QCOM_SCM_ADDON policy<{'arm64': '-'}> +CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT policy<{'arm64': '-'}> +CONFIG_QCOM_SECURE_BUFFER policy<{'arm64': '-'}> +CONFIG_QCOM_SI_CORE policy<{'arm64': '-'}> +CONFIG_QCOM_SI_CORE_ADCI policy<{'arm64': '-'}> +CONFIG_QCOM_SI_CORE_MEM_OBJECT policy<{'arm64': '-'}> +CONFIG_QCOM_SI_CORE_WQ policy<{'arm64': '-'}> +CONFIG_QCOM_SI_CORE_XTS policy<{'arm64': '-'}> +CONFIG_QCOM_SMCINVOKE policy<{'arm64': '-'}> +CONFIG_QCOM_SMD_RPM policy<{'arm64': 'y'}> +CONFIG_QCOM_SMEM policy<{'arm64': 'y'}> +CONFIG_QCOM_SMP2P policy<{'arm64': 'y'}> +CONFIG_QCOM_SMP2P_SLEEPSTATE policy<{'arm64': '-'}> +CONFIG_QCOM_SMSM policy<{'arm64': 'y'}> +CONFIG_QCOM_SOC_DEBUG policy<{'arm64': '-'}> +CONFIG_QCOM_SPMI_ADC5_GEN3 policy<{'arm64': 'm'}> +CONFIG_QCOM_SPMI_ADC_TM5_GEN3 policy<{'arm64': 'm'}> +CONFIG_QCOM_SPMI_MBG_TM policy<{'arm64': '-'}> +CONFIG_QCOM_TGU policy<{'arm64': 'y'}> +CONFIG_QCOM_WATCHDOG_BARK_TIME policy<{'arm64': '-'}> +CONFIG_QCOM_WATCHDOG_IPI_PING policy<{'arm64': '-'}> +CONFIG_QCOM_WATCHDOG_PET_TIME policy<{'arm64': '-'}> +CONFIG_QCOM_WCNSS_PIL policy<{'arm64': 'm'}> +CONFIG_QCOM_WDOG_BITE_EARLY_PANIC policy<{'arm64': '-'}> +CONFIG_QCOM_WDT_CORE policy<{'arm64': '-'}> +CONFIG_QCS_GCC_404 policy<{'arm64': 'y'}> +CONFIG_QCS_GCC_615 policy<{'arm64': 'y'}> +CONFIG_QCS_GCC_8300 policy<{'arm64': 'y'}> +CONFIG_QORIQ_CPUFREQ policy<{'arm64': '-'}> +CONFIG_QORIQ_THERMAL policy<{'arm64': '-'}> +CONFIG_QTI_BCL_PMIC5 policy<{'arm64': '-'}> +CONFIG_QTI_DEVFREQ_CDEV policy<{'arm64': '-'}> +CONFIG_QTI_TZ_LOG policy<{'arm64': '-'}> +CONFIG_RAVB policy<{'arm64': '-'}> +CONFIG_RCAR_DMAC policy<{'arm64': '-'}> +CONFIG_RCAR_GEN3_THERMAL policy<{'arm64': '-'}> +CONFIG_RCAR_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_RCAR_THERMAL policy<{'arm64': '-'}> +CONFIG_RCU_CPU_STALL_TIMEOUT policy<{'arm64': '21'}> +CONFIG_REBOOT_MODE policy<{'arm64': 'y'}> +CONFIG_REGMAP_AC97 policy<{'arm64': '-'}> +CONFIG_REGMAP_SPMI policy<{'arm64': 'y'}> +CONFIG_REGULATOR_ANATOP policy<{'arm64': '-'}> +CONFIG_REGULATOR_DEBUG_CONTROL policy<{'arm64': '-'}> +CONFIG_REGULATOR_GPIO policy<{'arm64': 'y'}> +CONFIG_REGULATOR_HI655X policy<{'arm64': '-'}> +CONFIG_REGULATOR_MT6380 policy<{'arm64': '-'}> +CONFIG_REGULATOR_MTK_DVFSRC policy<{'arm64': '-'}> +CONFIG_REGULATOR_PROXY_CONSUMER policy<{'arm64': '-'}> +CONFIG_REGULATOR_PWM policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_REFGEN policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_RPMH policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_SMD_RPM policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QCOM_SPMI policy<{'arm64': 'y'}> +CONFIG_REGULATOR_QPNP_LCDB policy<{'arm64': '-'}> +CONFIG_REGULATOR_RZG2L_VBCTRL policy<{'arm64': '-'}> +CONFIG_REGULATOR_SC2731 policy<{'arm64': '-'}> +CONFIG_REGULATOR_STM32_BOOSTER policy<{'arm64': '-'}> +CONFIG_REGULATOR_STM32_PWR policy<{'arm64': '-'}> +CONFIG_REGULATOR_STM32_VREFBUF policy<{'arm64': '-'}> +CONFIG_REGULATOR_SUN20I policy<{'arm64': '-'}> +CONFIG_REMOTEPROC_THERMAL policy<{'arm64': 'y'}> +CONFIG_RENESAS_DMA policy<{'arm64': '-'}> +CONFIG_RENESAS_ETHER_SWITCH policy<{'arm64': '-'}> +CONFIG_RENESAS_GEN4_PTP policy<{'arm64': '-'}> +CONFIG_RENESAS_I3C policy<{'arm64': '-'}> +CONFIG_RENESAS_IRQC policy<{'arm64': '-'}> +CONFIG_RENESAS_OSTM policy<{'arm64': '-'}> +CONFIG_RENESAS_RPCIF policy<{'arm64': '-'}> +CONFIG_RENESAS_RZAWDT policy<{'arm64': '-'}> +CONFIG_RENESAS_RZG2LWDT policy<{'arm64': '-'}> +CONFIG_RENESAS_RZG2L_IRQC policy<{'arm64': '-'}> +CONFIG_RENESAS_RZN1WDT policy<{'arm64': '-'}> +CONFIG_RENESAS_RZT2H_ICU policy<{'arm64': '-'}> +CONFIG_RENESAS_RZV2HWDT policy<{'arm64': '-'}> +CONFIG_RENESAS_RZV2H_ICU policy<{'arm64': '-'}> +CONFIG_RENESAS_USB_DMAC policy<{'arm64': '-'}> +CONFIG_RENESAS_WDT policy<{'arm64': '-'}> +CONFIG_RENESAS_WWDT policy<{'arm64': '-'}> +CONFIG_RESET_A10SR policy<{'arm64': '-'}> +CONFIG_RESET_BERLIN policy<{'arm64': '-'}> +CONFIG_RESET_HISI policy<{'arm64': '-'}> +CONFIG_RESET_IMX7 policy<{'arm64': '-'}> +CONFIG_RESET_IMX8MP_AUDIOMIX policy<{'arm64': '-'}> +CONFIG_RESET_IMX_SCU policy<{'arm64': '-'}> +CONFIG_RESET_MCHP_SPARX5 policy<{'arm64': 'm'}> +CONFIG_RESET_MESON policy<{'arm64': '-'}> +CONFIG_RESET_MESON_AUDIO_ARB policy<{'arm64': '-'}> +CONFIG_RESET_MESON_AUX policy<{'arm64': '-'}> +CONFIG_RESET_MESON_COMMON policy<{'arm64': '-'}> +CONFIG_RESET_NPCM policy<{'arm64': '-'}> +CONFIG_RESET_NUVOTON_MA35D1 policy<{'arm64': '-'}> +CONFIG_RESET_RZG2L_USBPHY_CTRL policy<{'arm64': '-'}> +CONFIG_RESET_RZV2H_USB2PHY policy<{'arm64': '-'}> +CONFIG_RESET_SUNXI policy<{'arm64': '-'}> +CONFIG_RESET_TEGRA_BPMP policy<{'arm64': '-'}> +CONFIG_RESET_TI_SCI policy<{'arm64': '-'}> +CONFIG_RESET_TN48M_CPLD policy<{'arm64': '-'}> +CONFIG_RESET_ZYNQMP policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_ANALOGIX_DP policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_CDN_DP policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_DTPM policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_DW_DP policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_DW_HDMI policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_DW_HDMI_QP policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_DW_MIPI_DSI policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_DW_MIPI_DSI2 policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_GRF policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_INNO_HDMI policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_IODOMAIN policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_IOMMU policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_LVDS policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_MBOX policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_RGB policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_RK3066_HDMI policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_SARADC policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_THERMAL policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_TIMER policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_VOP policy<{'arm64': '-'}> +CONFIG_ROCKCHIP_VOP2 policy<{'arm64': '-'}> +CONFIG_RPMSG policy<{'arm64': 'y'}> +CONFIG_RPMSG_MTK_SCP policy<{'arm64': '-'}> +CONFIG_RPMSG_QCOM_GLINK policy<{'arm64': 'y'}> +CONFIG_RPMSG_QCOM_GLINK_RPM policy<{'arm64': 'y'}> +CONFIG_RPMSG_QCOM_SMD policy<{'arm64': 'y'}> +CONFIG_RST_RCAR policy<{'arm64': '-'}> +CONFIG_RTC_DRV_AMLOGIC_A4 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_ARMADA38X policy<{'arm64': '-'}> +CONFIG_RTC_DRV_BBNSM policy<{'arm64': '-'}> +CONFIG_RTC_DRV_CV1800 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_FSL_FTM_ALARM policy<{'arm64': '-'}> +CONFIG_RTC_DRV_IMXDI policy<{'arm64': '-'}> +CONFIG_RTC_DRV_IMX_SC policy<{'arm64': '-'}> +CONFIG_RTC_DRV_MA35D1 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_MACSMC policy<{'arm64': '-'}> +CONFIG_RTC_DRV_MESON_VRTC policy<{'arm64': '-'}> +CONFIG_RTC_DRV_MT2712 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_MT7622 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_MV policy<{'arm64': '-'}> +CONFIG_RTC_DRV_MXC policy<{'arm64': '-'}> +CONFIG_RTC_DRV_MXC_V2 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_NVIDIA_VRS10 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_RENESAS_RTCA3 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_RTD119X policy<{'arm64': '-'}> +CONFIG_RTC_DRV_S32G policy<{'arm64': '-'}> +CONFIG_RTC_DRV_SA1100 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_SC27XX policy<{'arm64': '-'}> +CONFIG_RTC_DRV_SH policy<{'arm64': '-'}> +CONFIG_RTC_DRV_SNVS policy<{'arm64': '-'}> +CONFIG_RTC_DRV_STM32 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_SUN6I policy<{'arm64': '-'}> +CONFIG_RTC_DRV_TEGRA policy<{'arm64': '-'}> +CONFIG_RTC_DRV_TI_K3 policy<{'arm64': '-'}> +CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> +CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> +CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> +CONFIG_RTSN policy<{'arm64': '-'}> +CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.92.0 (ded5c06cf 2025-12-08)"'}> +CONFIG_RZG2L_ADC policy<{'arm64': '-'}> +CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> +CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> +CONFIG_RZG3S_THERMAL policy<{'arm64': '-'}> +CONFIG_RZT2H_ADC policy<{'arm64': '-'}> +CONFIG_RZ_DMAC policy<{'arm64': '-'}> +CONFIG_RZ_MTU3 policy<{'arm64': '-'}> +CONFIG_RZ_MTU3_CNT policy<{'arm64': '-'}> +CONFIG_S32G_WDT policy<{'arm64': '-'}> +CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': '-'}> +CONFIG_SATA_RCAR policy<{'arm64': '-'}> +CONFIG_SC27XX_ADC policy<{'arm64': '-'}> +CONFIG_SCSI_UFS_AMD_VERSAL2 policy<{'arm64': '-'}> +CONFIG_SCSI_UFS_HISI policy<{'arm64': '-'}> +CONFIG_SCSI_UFS_MEDIATEK policy<{'arm64': '-'}> +CONFIG_SCSI_UFS_RENESAS policy<{'arm64': '-'}> +CONFIG_SCSI_UFS_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_SCSI_UFS_SPRD policy<{'arm64': '-'}> +CONFIG_SCSI_UFS_TI_J721E policy<{'arm64': '-'}> +CONFIG_SC_CAMCC_7280 policy<{'arm64': 'y'}> +CONFIG_SC_DISPCC_7280 policy<{'arm64': 'y'}> +CONFIG_SC_GPUCC_7280 policy<{'arm64': 'y'}> +CONFIG_SC_LPASS_CORECC_7280 policy<{'arm64': 'y'}> +CONFIG_SC_VIDEOCC_7280 policy<{'arm64': 'y'}> +CONFIG_SDM_DISPCC_845 policy<{'arm64': 'y'}> +CONFIG_SDM_GCC_845 policy<{'arm64': 'y'}> +CONFIG_SDM_GPUCC_845 policy<{'arm64': 'y'}> +CONFIG_SDM_VIDEOCC_845 policy<{'arm64': 'y'}> +CONFIG_SENSORS_EMC2305 policy<{'arm64': 'y'}> +CONFIG_SENSORS_MACSMC_HWMON policy<{'arm64': '-'}> +CONFIG_SENSORS_QCOM_BCL policy<{'arm64': 'y'}> +CONFIG_SENSORS_SA67MCU policy<{'arm64': '-'}> +CONFIG_SENSORS_SG2042_MCU policy<{'arm64': '-'}> +CONFIG_SENSORS_SL28CPLD policy<{'arm64': '-'}> +CONFIG_SENSORS_SPARX5 policy<{'arm64': '-'}> +CONFIG_SERIAL_8250_EM policy<{'arm64': '-'}> +CONFIG_SERIAL_8250_EXAR policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_MT6577 policy<{'arm64': '-'}> +CONFIG_SERIAL_8250_OMAP policy<{'arm64': '-'}> +CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP policy<{'arm64': '-'}> +CONFIG_SERIAL_8250_PERICOM policy<{'arm64': 'y'}> +CONFIG_SERIAL_8250_PXA policy<{'arm64': '-'}> +CONFIG_SERIAL_8250_TEGRA policy<{'arm64': '-'}> +CONFIG_SERIAL_FSL_LINFLEXUART policy<{'arm64': 'y'}> +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_FSL_LPUART policy<{'arm64': 'y'}> +CONFIG_SERIAL_FSL_LPUART_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_IMX policy<{'arm64': '-'}> +CONFIG_SERIAL_IMX_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_IMX_EARLYCON policy<{'arm64': '-'}> +CONFIG_SERIAL_MESON policy<{'arm64': '-'}> +CONFIG_SERIAL_MESON_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_MVEBU_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_MVEBU_UART policy<{'arm64': '-'}> +CONFIG_SERIAL_NUVOTON_MA35D1 policy<{'arm64': '-'}> +CONFIG_SERIAL_OWL policy<{'arm64': '-'}> +CONFIG_SERIAL_OWL_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_PXA policy<{'arm64': '-'}> +CONFIG_SERIAL_PXA_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_RSCI policy<{'arm64': '-'}> +CONFIG_SERIAL_SAMSUNG policy<{'arm64': '-'}> +CONFIG_SERIAL_SAMSUNG_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_SAMSUNG_UARTS policy<{'arm64': '-'}> +CONFIG_SERIAL_SH_SCI_DMA policy<{'arm64': '-'}> +CONFIG_SERIAL_SH_SCI_NR_UARTS policy<{'arm64': '-'}> +CONFIG_SERIAL_STM32 policy<{'arm64': '-'}> +CONFIG_SERIAL_STM32_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_TEGRA policy<{'arm64': '-'}> +CONFIG_SERIAL_TEGRA_TCU policy<{'arm64': '-'}> +CONFIG_SERIAL_TEGRA_TCU_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIAL_TEGRA_UTC policy<{'arm64': '-'}> +CONFIG_SERIAL_TEGRA_UTC_CONSOLE policy<{'arm64': '-'}> +CONFIG_SERIO_AMBAKMI policy<{'arm64': 'y'}> +CONFIG_SERIO_NVEC_PS2 policy<{'arm64': '-'}> +CONFIG_SERIO_OLPC_APSP policy<{'arm64': '-'}> +CONFIG_SERIO_SUN4I_PS2 policy<{'arm64': '-'}> +CONFIG_SH_ETH policy<{'arm64': '-'}> +CONFIG_SH_TIMER_CMT policy<{'arm64': '-'}> +CONFIG_SH_TIMER_TMU policy<{'arm64': '-'}> +CONFIG_SL28CPLD_WATCHDOG policy<{'arm64': '-'}> +CONFIG_SLIC_DS26522 policy<{'arm64': '-'}> +CONFIG_SLUB_RCU_DEBUG policy<{'arm64': 'n'}> +CONFIG_SM_CAMCC_7150 policy<{'arm64': 'n'}> +CONFIG_SM_DISPCC_7150 policy<{'arm64': 'n'}> +CONFIG_SM_DISPCC_8250 policy<{'arm64': 'y'}> +CONFIG_SM_DISPCC_8650 policy<{'arm64': '-'}> +CONFIG_SM_GCC_6115 policy<{'arm64': 'y'}> +CONFIG_SM_GCC_8150 policy<{'arm64': 'y'}> +CONFIG_SM_GCC_8250 policy<{'arm64': 'y'}> +CONFIG_SM_GCC_8350 policy<{'arm64': 'y'}> +CONFIG_SM_GCC_8450 policy<{'arm64': 'y'}> +CONFIG_SM_GCC_8550 policy<{'arm64': 'y'}> +CONFIG_SM_GCC_8650 policy<{'arm64': 'y'}> +CONFIG_SM_GCC_8750 policy<{'arm64': 'y'}> +CONFIG_SM_GPUCC_8150 policy<{'arm64': 'y'}> +CONFIG_SM_GPUCC_8250 policy<{'arm64': 'y'}> +CONFIG_SM_GPUCC_8650 policy<{'arm64': 'y'}> +CONFIG_SM_GPUCC_8750 policy<{'arm64': 'y'}> +CONFIG_SM_TCSRCC_8550 policy<{'arm64': 'y'}> +CONFIG_SM_TCSRCC_8650 policy<{'arm64': 'y'}> +CONFIG_SM_VIDEOCC_7150 policy<{'arm64': 'n'}> +CONFIG_SM_VIDEOCC_8250 policy<{'arm64': 'y'}> +CONFIG_SND_COMPRESS_OFFLOAD policy<{'arm64': 'y'}> +CONFIG_SND_DMAENGINE_PCM policy<{'arm64': 'y'}> +CONFIG_SND_HDA_ALIGNED_MMIO policy<{'arm64': '-'}> +CONFIG_SND_HDA_CIX_IPBLOQ policy<{'arm64': '-'}> +CONFIG_SND_HDA_COMPONENT policy<{'arm64': '-'}> +CONFIG_SND_HDA_I915 policy<{'arm64': '-'}> +CONFIG_SND_HDA_TEGRA policy<{'arm64': '-'}> +CONFIG_SND_IMX_SOC policy<{'arm64': '-'}> +CONFIG_SND_KIRKWOOD_SOC policy<{'arm64': '-'}> +CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB policy<{'arm64': '-'}> +CONFIG_SND_MESON_AIU policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_FIFO policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_FRDDR policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_PDM policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_SOUND_CARD policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_SPDIFIN policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_SPDIFOUT policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_TDMIN policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_TDMOUT policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_TDM_FORMATTER policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_TDM_INTERFACE policy<{'arm64': '-'}> +CONFIG_SND_MESON_AXG_TODDR policy<{'arm64': '-'}> +CONFIG_SND_MESON_CARD_UTILS policy<{'arm64': '-'}> +CONFIG_SND_MESON_CODEC_GLUE policy<{'arm64': '-'}> +CONFIG_SND_MESON_G12A_TOACODEC policy<{'arm64': '-'}> +CONFIG_SND_MESON_G12A_TOHDMITX policy<{'arm64': '-'}> +CONFIG_SND_MESON_GX_SOUND_CARD policy<{'arm64': '-'}> +CONFIG_SND_MMP_SOC_SSPA policy<{'arm64': '-'}> +CONFIG_SND_PCM policy<{'arm64': 'y'}> +CONFIG_SND_PXA910_SOC policy<{'arm64': '-'}> +CONFIG_SND_SOC_ALC5632 policy<{'arm64': '-'}> +CONFIG_SND_SOC_APPLE_MCA policy<{'arm64': '-'}> +CONFIG_SND_SOC_AUDIO_PKT policy<{'arm64': '-'}> +CONFIG_SND_SOC_CV1800B_ADC_CODEC policy<{'arm64': '-'}> +CONFIG_SND_SOC_CV1800B_DAC_CODEC policy<{'arm64': '-'}> +CONFIG_SND_SOC_CV1800B_TDM policy<{'arm64': '-'}> +CONFIG_SND_SOC_DAVINCI_MCASP policy<{'arm64': '-'}> +CONFIG_SND_SOC_FSL_ASOC_CARD policy<{'arm64': '-'}> +CONFIG_SND_SOC_FSL_AUD2HTX policy<{'arm64': '-'}> +CONFIG_SND_SOC_I2C_AND_SPI policy<{'arm64': 'y'}> +CONFIG_SND_SOC_IMX_AUDIO_RPMSG policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_AUDMIX policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_CARD policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_ES8328 policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_HDMI policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_PCM_DMA policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_PCM_RPMSG policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_RPMSG policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_SGTL5000 policy<{'arm64': '-'}> +CONFIG_SND_SOC_IMX_SPDIF policy<{'arm64': '-'}> +CONFIG_SND_SOC_INNO_RK3036 policy<{'arm64': '-'}> +CONFIG_SND_SOC_INTEL_KEEMBAY policy<{'arm64': '-'}> +CONFIG_SND_SOC_J721E_EVM policy<{'arm64': '-'}> +CONFIG_SND_SOC_MEDIATEK policy<{'arm64': '-'}> +CONFIG_SND_SOC_MESON_T9015 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MSIOF policy<{'arm64': '-'}> +CONFIG_SND_SOC_MSM_AUDIO_MEM policy<{'arm64': '-'}> +CONFIG_SND_SOC_MSM_STUB policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT2701 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT6359 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT6359_ACCDET policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT6797 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT6797_MT6351 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT7986 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT7986_WM8960 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8173 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8183 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8183_DA7219_MAX98357A policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8186 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8186_MT6366 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8186_MT6366_DA7219_MAX98357 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8186_MT6366_RT1019_RT5682S policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8188 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8188_MT6359 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8189 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8189_NAU8825 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8192 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8195 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8195_MT6359 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8365 policy<{'arm64': '-'}> +CONFIG_SND_SOC_MT8365_MT6357 policy<{'arm64': '-'}> +CONFIG_SND_SOC_NAU8825 policy<{'arm64': '-'}> +CONFIG_SND_SOC_QCM6490 policy<{'arm64': '-'}> +CONFIG_SND_SOC_QCS9100 policy<{'arm64': '-'}> +CONFIG_SND_SOC_RCAR policy<{'arm64': '-'}> +CONFIG_SND_SOC_RK3288_HDMI_ANALOG policy<{'arm64': '-'}> +CONFIG_SND_SOC_RK3308 policy<{'arm64': '-'}> +CONFIG_SND_SOC_RK3328 policy<{'arm64': '-'}> +CONFIG_SND_SOC_RK3399_GRU_SOUND policy<{'arm64': '-'}> +CONFIG_SND_SOC_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_SND_SOC_ROCKCHIP_I2S policy<{'arm64': '-'}> +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM policy<{'arm64': '-'}> +CONFIG_SND_SOC_ROCKCHIP_MAX98090 policy<{'arm64': '-'}> +CONFIG_SND_SOC_ROCKCHIP_PDM policy<{'arm64': '-'}> +CONFIG_SND_SOC_ROCKCHIP_RT5645 policy<{'arm64': '-'}> +CONFIG_SND_SOC_ROCKCHIP_SAI policy<{'arm64': '-'}> +CONFIG_SND_SOC_ROCKCHIP_SPDIF policy<{'arm64': '-'}> +CONFIG_SND_SOC_RT1011 policy<{'arm64': '-'}> +CONFIG_SND_SOC_RT1015 policy<{'arm64': '-'}> +CONFIG_SND_SOC_RT1015P policy<{'arm64': '-'}> +CONFIG_SND_SOC_RT5514 policy<{'arm64': '-'}> +CONFIG_SND_SOC_RT5514_SPI policy<{'arm64': '-'}> +CONFIG_SND_SOC_RT5677 policy<{'arm64': '-'}> +CONFIG_SND_SOC_RT5677_SPI policy<{'arm64': '-'}> +CONFIG_SND_SOC_RZ policy<{'arm64': '-'}> +CONFIG_SND_SOC_SDCA_OPTIONAL policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SH4_FSI policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_COMPRESS policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_IMX8 policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_IMX8M policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_IMX8ULP policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_IMX9 policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_IMX_COMMON policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_IPC3 policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_MT8186 policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_MT8195 policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_MTK_COMMON policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_OF_DEV policy<{'arm64': '-'}> +CONFIG_SND_SOC_SOF_XTENSA policy<{'arm64': '-'}> +CONFIG_SND_SOC_SPF_CORE policy<{'arm64': '-'}> +CONFIG_SND_SOC_SPRD policy<{'arm64': '-'}> +CONFIG_SND_SOC_SPRD_MCDT policy<{'arm64': '-'}> +CONFIG_SND_SOC_STM32_DFSDM policy<{'arm64': '-'}> +CONFIG_SND_SOC_STM32_I2S policy<{'arm64': '-'}> +CONFIG_SND_SOC_STM32_SAI policy<{'arm64': '-'}> +CONFIG_SND_SOC_STM32_SPDIFRX policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA186_ASRC policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA186_DSPK policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA20_AC97 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA20_DAS policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA20_I2S policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA20_SPDIF policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_ADMAIF policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_ADX policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_AHUB policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_AMX policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_DMIC policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_I2S policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_MIXER policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_MVC policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_OPE policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA210_SFC policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA30_AHUB policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA30_I2S policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_ALC5632 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_MACHINE_DRV policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_MAX98088 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_MAX98090 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_RT5631 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_RT5640 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_RT5677 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_SGTL5000 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_TRIMSLICE policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_WM8753 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_WM8903 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TEGRA_WM9712 policy<{'arm64': '-'}> +CONFIG_SND_SOC_TI_EDMA_PCM policy<{'arm64': '-'}> +CONFIG_SND_SOC_TI_SDMA_PCM policy<{'arm64': '-'}> +CONFIG_SND_SOC_TI_UDMA_PCM policy<{'arm64': '-'}> +CONFIG_SND_SOC_WM8994 policy<{'arm64': '-'}> +CONFIG_SND_SOC_WM9712 policy<{'arm64': '-'}> +CONFIG_SND_SOC_WM_HUBS policy<{'arm64': '-'}> +CONFIG_SND_SUN4I_CODEC policy<{'arm64': '-'}> +CONFIG_SND_SUN4I_I2S policy<{'arm64': '-'}> +CONFIG_SND_SUN4I_SPDIF policy<{'arm64': '-'}> +CONFIG_SND_SUN50I_CODEC_ANALOG policy<{'arm64': '-'}> +CONFIG_SND_SUN50I_DMIC policy<{'arm64': '-'}> +CONFIG_SND_SUN8I_ADDA_PR_REGMAP policy<{'arm64': '-'}> +CONFIG_SND_SUN8I_CODEC policy<{'arm64': '-'}> +CONFIG_SND_SUN8I_CODEC_ANALOG policy<{'arm64': '-'}> +CONFIG_SND_TIMER policy<{'arm64': 'y'}> +CONFIG_SNI_NETSEC policy<{'arm64': '-'}> +CONFIG_SOCFPGA_FPGA_BRIDGE policy<{'arm64': '-'}> +CONFIG_SOC_IMX8M policy<{'arm64': '-'}> +CONFIG_SOC_IMX9 policy<{'arm64': '-'}> +CONFIG_SOC_RENESAS policy<{'arm64': '-'}> +CONFIG_SOC_TEGRA_CBB policy<{'arm64': '-'}> +CONFIG_SOC_TEGRA_FLOWCTRL policy<{'arm64': '-'}> +CONFIG_SOC_TEGRA_FUSE policy<{'arm64': '-'}> +CONFIG_SOC_TEGRA_PMC policy<{'arm64': '-'}> +CONFIG_SOC_TEGRA_POWERGATE_BPMP policy<{'arm64': '-'}> +CONFIG_SOPHGO_CV1800B_ADC policy<{'arm64': '-'}> +CONFIG_SOPHGO_CV1800B_DMAMUX policy<{'arm64': '-'}> +CONFIG_SOPHGO_CV1800_RTCSYS policy<{'arm64': '-'}> +CONFIG_SOPHGO_SG2042_MSI policy<{'arm64': '-'}> +CONFIG_SOPHGO_SG2044_TOPSYS policy<{'arm64': '-'}> +CONFIG_SPARX5_DCB policy<{'arm64': '-'}> +CONFIG_SPARX5_SWITCH policy<{'arm64': 'n'}> +CONFIG_SPI_AIROHA_SNFI policy<{'arm64': '-'}> +CONFIG_SPI_AMLOGIC_SPIFC_A1 policy<{'arm64': '-'}> +CONFIG_SPI_AMLOGIC_SPIFC_A4 policy<{'arm64': '-'}> +CONFIG_SPI_AMLOGIC_SPISG policy<{'arm64': '-'}> +CONFIG_SPI_APPLE policy<{'arm64': '-'}> +CONFIG_SPI_ARMADA_3700 policy<{'arm64': '-'}> +CONFIG_SPI_AXIADO policy<{'arm64': '-'}> +CONFIG_SPI_FSL_DSPI policy<{'arm64': '-'}> +CONFIG_SPI_FSL_LPSPI policy<{'arm64': '-'}> +CONFIG_SPI_FSL_QUADSPI policy<{'arm64': '-'}> +CONFIG_SPI_HISI_SFC policy<{'arm64': '-'}> +CONFIG_SPI_IMX policy<{'arm64': '-'}> +CONFIG_SPI_MESON_SPICC policy<{'arm64': '-'}> +CONFIG_SPI_MESON_SPIFC policy<{'arm64': '-'}> +CONFIG_SPI_MT65XX policy<{'arm64': '-'}> +CONFIG_SPI_MTK_NOR policy<{'arm64': '-'}> +CONFIG_SPI_MTK_SNFI policy<{'arm64': '-'}> +CONFIG_SPI_NPCM_FIU policy<{'arm64': '-'}> +CONFIG_SPI_NPCM_PSPI policy<{'arm64': '-'}> +CONFIG_SPI_NXP_FLEXSPI policy<{'arm64': '-'}> +CONFIG_SPI_NXP_XSPI policy<{'arm64': '-'}> +CONFIG_SPI_OMAP24XX policy<{'arm64': '-'}> +CONFIG_SPI_ORION policy<{'arm64': '-'}> +CONFIG_SPI_PXA2XX policy<{'arm64': '-'}> +CONFIG_SPI_PXA2XX_PCI policy<{'arm64': '-'}> +CONFIG_SPI_QUP policy<{'arm64': 'y'}> +CONFIG_SPI_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_SPI_ROCKCHIP_SFC policy<{'arm64': '-'}> +CONFIG_SPI_RPCIF policy<{'arm64': '-'}> +CONFIG_SPI_RSPI policy<{'arm64': '-'}> +CONFIG_SPI_RZV2H_RSPI policy<{'arm64': '-'}> +CONFIG_SPI_RZV2M_CSI policy<{'arm64': '-'}> +CONFIG_SPI_SG2044_NOR policy<{'arm64': '-'}> +CONFIG_SPI_SH_HSPI policy<{'arm64': '-'}> +CONFIG_SPI_SH_MSIOF policy<{'arm64': '-'}> +CONFIG_SPI_SLAVE_MT27XX policy<{'arm64': '-'}> +CONFIG_SPI_SPRD policy<{'arm64': '-'}> +CONFIG_SPI_SPRD_ADI policy<{'arm64': '-'}> +CONFIG_SPI_STM32 policy<{'arm64': '-'}> +CONFIG_SPI_STM32_OSPI policy<{'arm64': '-'}> +CONFIG_SPI_STM32_QSPI policy<{'arm64': '-'}> +CONFIG_SPI_SUN4I policy<{'arm64': '-'}> +CONFIG_SPI_SUN6I policy<{'arm64': '-'}> +CONFIG_SPI_SYNQUACER policy<{'arm64': '-'}> +CONFIG_SPI_TEGRA114 policy<{'arm64': '-'}> +CONFIG_SPI_TEGRA20_SFLASH policy<{'arm64': '-'}> +CONFIG_SPI_TEGRA20_SLINK policy<{'arm64': '-'}> +CONFIG_SPI_TEGRA210_QUAD policy<{'arm64': '-'}> +CONFIG_SPI_WPCM_FIU policy<{'arm64': '-'}> +CONFIG_SPI_XLP policy<{'arm64': '-'}> +CONFIG_SPMI policy<{'arm64': 'y'}> +CONFIG_SPMI_APPLE policy<{'arm64': '-'}> +CONFIG_SPMI_MSM_PMIC_ARB policy<{'arm64': 'y'}> +CONFIG_SPMI_MTK_PMIF policy<{'arm64': '-'}> +CONFIG_SPRD_COMMON_CLK policy<{'arm64': '-'}> +CONFIG_SPRD_DMA policy<{'arm64': '-'}> +CONFIG_SPRD_IOMMU policy<{'arm64': '-'}> +CONFIG_SPRD_MBOX policy<{'arm64': '-'}> +CONFIG_SPRD_SC9860_CLK policy<{'arm64': '-'}> +CONFIG_SPRD_SC9863A_CLK policy<{'arm64': '-'}> +CONFIG_SPRD_THERMAL policy<{'arm64': '-'}> +CONFIG_SPRD_TIMER policy<{'arm64': '-'}> +CONFIG_SPRD_UMS512_CLK policy<{'arm64': '-'}> +CONFIG_SPRD_WATCHDOG policy<{'arm64': '-'}> +CONFIG_STACKDEPOT_ALWAYS_INIT policy<{'arm64': 'y'}> +CONFIG_STM32MP_EXTI policy<{'arm64': '-'}> +CONFIG_STM32_ADC policy<{'arm64': '-'}> +CONFIG_STM32_ADC_CORE policy<{'arm64': '-'}> +CONFIG_STM32_DAC policy<{'arm64': '-'}> +CONFIG_STM32_DAC_CORE policy<{'arm64': '-'}> +CONFIG_STM32_DFSDM_ADC policy<{'arm64': '-'}> +CONFIG_STM32_DFSDM_CORE policy<{'arm64': '-'}> +CONFIG_STM32_DMA policy<{'arm64': '-'}> +CONFIG_STM32_DMA3 policy<{'arm64': '-'}> +CONFIG_STM32_DMAMUX policy<{'arm64': '-'}> +CONFIG_STM32_FIREWALL policy<{'arm64': '-'}> +CONFIG_STM32_FMC2_EBI policy<{'arm64': '-'}> +CONFIG_STM32_LPTIMER_CNT policy<{'arm64': '-'}> +CONFIG_STM32_MDMA policy<{'arm64': '-'}> +CONFIG_STM32_OMM policy<{'arm64': '-'}> +CONFIG_STM32_RPROC policy<{'arm64': '-'}> +CONFIG_STM32_TIMER_CNT policy<{'arm64': '-'}> +CONFIG_STM32_WATCHDOG policy<{'arm64': '-'}> +CONFIG_STMP_DEVICE policy<{'arm64': '-'}> +CONFIG_STM_PROTO_OST policy<{'arm64': 'n'}> +CONFIG_STUB_CLK_HI3660 policy<{'arm64': '-'}> +CONFIG_STUB_CLK_HI6220 policy<{'arm64': '-'}> +CONFIG_ST_THERMAL policy<{'arm64': '-'}> +CONFIG_ST_THERMAL_MEMMAP policy<{'arm64': '-'}> +CONFIG_SUN20I_GPADC policy<{'arm64': '-'}> +CONFIG_SUN20I_PPU policy<{'arm64': '-'}> +CONFIG_SUN4I_EMAC policy<{'arm64': '-'}> +CONFIG_SUN4I_GPADC policy<{'arm64': '-'}> +CONFIG_SUN4I_TIMER policy<{'arm64': '-'}> +CONFIG_SUN50I_A100_CCU policy<{'arm64': '-'}> +CONFIG_SUN50I_A100_R_CCU policy<{'arm64': '-'}> +CONFIG_SUN50I_A64_CCU policy<{'arm64': '-'}> +CONFIG_SUN50I_DE2_BUS policy<{'arm64': '-'}> +CONFIG_SUN50I_ERRATUM_UNKNOWN1 policy<{'arm64': '-'}> +CONFIG_SUN50I_H616_CCU policy<{'arm64': '-'}> +CONFIG_SUN50I_H6_CCU policy<{'arm64': '-'}> +CONFIG_SUN50I_H6_PRCM_PPU policy<{'arm64': '-'}> +CONFIG_SUN50I_H6_R_CCU policy<{'arm64': '-'}> +CONFIG_SUN50I_IOMMU policy<{'arm64': '-'}> +CONFIG_SUN55I_A523_CCU policy<{'arm64': '-'}> +CONFIG_SUN55I_A523_MCU_CCU policy<{'arm64': '-'}> +CONFIG_SUN55I_A523_R_CCU policy<{'arm64': '-'}> +CONFIG_SUN55I_PCK600 policy<{'arm64': '-'}> +CONFIG_SUN6I_MSGBOX policy<{'arm64': '-'}> +CONFIG_SUN6I_R_INTC policy<{'arm64': '-'}> +CONFIG_SUN8I_DE2_CCU policy<{'arm64': '-'}> +CONFIG_SUN8I_H3_CCU policy<{'arm64': '-'}> +CONFIG_SUN8I_R_CCU policy<{'arm64': '-'}> +CONFIG_SUN8I_THERMAL policy<{'arm64': '-'}> +CONFIG_SUNXI_CCU policy<{'arm64': '-'}> +CONFIG_SUNXI_MBUS policy<{'arm64': '-'}> +CONFIG_SUNXI_NMI_INTC policy<{'arm64': '-'}> +CONFIG_SUNXI_RSB policy<{'arm64': '-'}> +CONFIG_SUNXI_SRAM policy<{'arm64': '-'}> +CONFIG_SUNXI_WATCHDOG policy<{'arm64': '-'}> +CONFIG_SYSC_R8A774A1 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A774B1 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A774C0 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A774E1 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A7795 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A77960 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A77961 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A77965 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A77970 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A77980 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A77990 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A77995 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A779A0 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A779F0 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A779G0 policy<{'arm64': '-'}> +CONFIG_SYSC_R8A779H0 policy<{'arm64': '-'}> +CONFIG_SYSC_R9A08G045 policy<{'arm64': '-'}> +CONFIG_SYSC_RCAR policy<{'arm64': '-'}> +CONFIG_SYSC_RCAR_GEN4 policy<{'arm64': '-'}> +CONFIG_SYSC_RZ policy<{'arm64': '-'}> +CONFIG_SYS_R9A09G047 policy<{'arm64': '-'}> +CONFIG_SYS_R9A09G056 policy<{'arm64': '-'}> +CONFIG_SYS_R9A09G057 policy<{'arm64': '-'}> +CONFIG_SYS_SUPPORTS_SH_CMT policy<{'arm64': '-'}> +CONFIG_SYS_SUPPORTS_SH_TMU policy<{'arm64': '-'}> +CONFIG_TCG_TIS_SYNQUACER policy<{'arm64': '-'}> +CONFIG_TEE_STMM_EFI policy<{'arm64': 'n'}> +CONFIG_TEGRA186_GPC_DMA policy<{'arm64': '-'}> +CONFIG_TEGRA186_TIMER policy<{'arm64': '-'}> +CONFIG_TEGRA20_APB_DMA policy<{'arm64': '-'}> +CONFIG_TEGRA210_ADMA policy<{'arm64': '-'}> +CONFIG_TEGRA210_EMC policy<{'arm64': '-'}> +CONFIG_TEGRA210_EMC_TABLE policy<{'arm64': '-'}> +CONFIG_TEGRA_ACONNECT policy<{'arm64': '-'}> +CONFIG_TEGRA_AHB policy<{'arm64': '-'}> +CONFIG_TEGRA_BPMP policy<{'arm64': '-'}> +CONFIG_TEGRA_BPMP_THERMAL policy<{'arm64': '-'}> +CONFIG_TEGRA_CLK_DFLL policy<{'arm64': '-'}> +CONFIG_TEGRA_GMI policy<{'arm64': '-'}> +CONFIG_TEGRA_HOST1X policy<{'arm64': '-'}> +CONFIG_TEGRA_HOST1X_CONTEXT_BUS policy<{'arm64': '-'}> +CONFIG_TEGRA_HOST1X_FIREWALL policy<{'arm64': '-'}> +CONFIG_TEGRA_HSP_MBOX policy<{'arm64': '-'}> +CONFIG_TEGRA_IOMMU_SMMU policy<{'arm64': '-'}> +CONFIG_TEGRA_IVC policy<{'arm64': '-'}> +CONFIG_TEGRA_MC policy<{'arm64': '-'}> +CONFIG_TEGRA_SOCTHERM policy<{'arm64': '-'}> +CONFIG_TEGRA_TIMER policy<{'arm64': '-'}> +CONFIG_TEGRA_WATCHDOG policy<{'arm64': '-'}> +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS policy<{'arm64': '10000'}> +CONFIG_THUNDERX2_PMU policy<{'arm64': '-'}> +CONFIG_TIMER_IMX_SYS_CTR policy<{'arm64': '-'}> +CONFIG_TI_AM335X_ADC policy<{'arm64': '-'}> +CONFIG_TI_AM65_CPSW_QOS policy<{'arm64': '-'}> +CONFIG_TI_AM65_CPSW_TAS policy<{'arm64': '-'}> +CONFIG_TI_DAVINCI_MDIO policy<{'arm64': '-'}> +CONFIG_TI_ECAP_CAPTURE policy<{'arm64': '-'}> +CONFIG_TI_EQEP policy<{'arm64': '-'}> +CONFIG_TI_ICSSG_PRUETH policy<{'arm64': '-'}> +CONFIG_TI_ICSSG_PRUETH_SR1 policy<{'arm64': '-'}> +CONFIG_TI_ICSS_IEP policy<{'arm64': '-'}> +CONFIG_TI_K3_AM65_CPSW_NUSS policy<{'arm64': '-'}> +CONFIG_TI_K3_AM65_CPSW_SWITCHDEV policy<{'arm64': '-'}> +CONFIG_TI_K3_AM65_CPTS policy<{'arm64': '-'}> +CONFIG_TI_K3_CPPI_DESC_POOL policy<{'arm64': '-'}> +CONFIG_TI_K3_DSP_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_TI_K3_M4_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_TI_K3_PSIL policy<{'arm64': '-'}> +CONFIG_TI_K3_R5_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_TI_K3_RINGACC policy<{'arm64': '-'}> +CONFIG_TI_K3_SOCINFO policy<{'arm64': '-'}> +CONFIG_TI_K3_UDMA policy<{'arm64': '-'}> +CONFIG_TI_K3_UDMA_GLUE_LAYER policy<{'arm64': '-'}> +CONFIG_TI_MESSAGE_MANAGER policy<{'arm64': '-'}> +CONFIG_TI_PRUETH policy<{'arm64': '-'}> +CONFIG_TI_PRUSS policy<{'arm64': '-'}> +CONFIG_TI_PRUSS_INTC policy<{'arm64': '-'}> +CONFIG_TI_SCI_CLK policy<{'arm64': '-'}> +CONFIG_TI_SCI_CLK_PROBE_FROM_FW policy<{'arm64': '-'}> +CONFIG_TI_SCI_INTA_IRQCHIP policy<{'arm64': '-'}> +CONFIG_TI_SCI_INTA_MSI_DOMAIN policy<{'arm64': '-'}> +CONFIG_TI_SCI_INTR_IRQCHIP policy<{'arm64': '-'}> +CONFIG_TI_SCI_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_TI_SCI_PROTOCOL policy<{'arm64': '-'}> +CONFIG_TI_SYSC policy<{'arm64': '-'}> +CONFIG_TI_SYSCON_CLK policy<{'arm64': '-'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C policy<{'arm64': 'n'}> +CONFIG_TOUCHSCREEN_SUN4I policy<{'arm64': '-'}> +CONFIG_TOUCHSCREEN_TI_AM335X_TSC policy<{'arm64': '-'}> +CONFIG_TURRIS_MOX_RWTM policy<{'arm64': '-'}> +CONFIG_TURRIS_MOX_RWTM_KEYCTL policy<{'arm64': '-'}> +CONFIG_TURRIS_SIGNING_KEY policy<{'arm64': '-'}> +CONFIG_USB_CDNS3_IMX policy<{'arm64': '-'}> +CONFIG_USB_CDNS3_TI policy<{'arm64': '-'}> +CONFIG_USB_DWC3_AM62 policy<{'arm64': '-'}> +CONFIG_USB_DWC3_APPLE policy<{'arm64': '-'}> +CONFIG_USB_DWC3_IMX8MP policy<{'arm64': '-'}> +CONFIG_USB_DWC3_KEYSTONE policy<{'arm64': '-'}> +CONFIG_USB_DWC3_MESON_G12A policy<{'arm64': '-'}> +CONFIG_USB_DWC3_RTK policy<{'arm64': '-'}> +CONFIG_USB_DWC3_XILINX policy<{'arm64': '-'}> +CONFIG_USB_EHCI_HCD_NPCM7XX policy<{'arm64': '-'}> +CONFIG_USB_EHCI_HCD_ORION policy<{'arm64': '-'}> +CONFIG_USB_EHCI_MV policy<{'arm64': '-'}> +CONFIG_USB_EHCI_TEGRA policy<{'arm64': '-'}> +CONFIG_USB_EMXX policy<{'arm64': '-'}> +CONFIG_USB_F_QDSS policy<{'arm64': '-'}> +CONFIG_USB_HUB_USB5807 policy<{'arm64': '-'}> +CONFIG_USB_MTU3 policy<{'arm64': '-'}> +CONFIG_USB_MTU3_DEBUG policy<{'arm64': '-'}> +CONFIG_USB_MTU3_DUAL_ROLE policy<{'arm64': '-'}> +CONFIG_USB_MTU3_GADGET policy<{'arm64': '-'}> +CONFIG_USB_MTU3_HOST policy<{'arm64': '-'}> +CONFIG_USB_MUSB_MEDIATEK policy<{'arm64': '-'}> +CONFIG_USB_MUSB_SUNXI policy<{'arm64': '-'}> +CONFIG_USB_MXS_PHY policy<{'arm64': '-'}> +CONFIG_USB_RENESAS_USB3 policy<{'arm64': '-'}> +CONFIG_USB_RENESAS_USBF policy<{'arm64': '-'}> +CONFIG_USB_RENESAS_USBHS policy<{'arm64': '-'}> +CONFIG_USB_RENESAS_USBHS_HCD policy<{'arm64': '-'}> +CONFIG_USB_RENESAS_USBHS_UDC policy<{'arm64': '-'}> +CONFIG_USB_RZV2M_USB3DRD policy<{'arm64': '-'}> +CONFIG_USB_TEGRA_PHY policy<{'arm64': '-'}> +CONFIG_USB_TEGRA_XUDC policy<{'arm64': '-'}> +CONFIG_USB_XHCI_HISTB policy<{'arm64': '-'}> +CONFIG_USB_XHCI_MTK policy<{'arm64': '-'}> +CONFIG_USB_XHCI_MVEBU policy<{'arm64': '-'}> +CONFIG_USB_XHCI_RCAR policy<{'arm64': '-'}> +CONFIG_USB_XHCI_RZV2M policy<{'arm64': '-'}> +CONFIG_USB_XHCI_TEGRA policy<{'arm64': '-'}> +CONFIG_V4L2_H264 policy<{'arm64': '-'}> +CONFIG_V4L2_ISP policy<{'arm64': '-'}> +CONFIG_V4L2_JPEG_HELPER policy<{'arm64': '-'}> +CONFIG_V4L2_VP9 policy<{'arm64': '-'}> +CONFIG_VFIO_FSL_MC policy<{'arm64': '-'}> +CONFIG_VIDEO_ALLEGRO_DVT policy<{'arm64': '-'}> +CONFIG_VIDEO_AMD_ISP4_CAPTURE policy<{'arm64': '-'}> +CONFIG_VIDEO_AMPHION_VPU policy<{'arm64': '-'}> +CONFIG_VIDEO_C3_ISP policy<{'arm64': '-'}> +CONFIG_VIDEO_C3_MIPI_ADAPTER policy<{'arm64': '-'}> +CONFIG_VIDEO_C3_MIPI_CSI2 policy<{'arm64': '-'}> +CONFIG_VIDEO_CODA policy<{'arm64': '-'}> +CONFIG_VIDEO_DW100 policy<{'arm64': '-'}> +CONFIG_VIDEO_E5010_JPEG_ENC policy<{'arm64': '-'}> +CONFIG_VIDEO_HANTRO policy<{'arm64': '-'}> +CONFIG_VIDEO_HANTRO_HEVC_RFC policy<{'arm64': '-'}> +CONFIG_VIDEO_HANTRO_IMX8M policy<{'arm64': '-'}> +CONFIG_VIDEO_HANTRO_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_VIDEO_HANTRO_STM32MP25 policy<{'arm64': '-'}> +CONFIG_VIDEO_HANTRO_SUNXI policy<{'arm64': '-'}> +CONFIG_VIDEO_IMX7_CSI policy<{'arm64': '-'}> +CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 policy<{'arm64': '-'}> +CONFIG_VIDEO_IMX8_ISI policy<{'arm64': '-'}> +CONFIG_VIDEO_IMX8_ISI_M2M policy<{'arm64': '-'}> +CONFIG_VIDEO_IMX8_JPEG policy<{'arm64': '-'}> +CONFIG_VIDEO_IMX_MIPI_CSIS policy<{'arm64': '-'}> +CONFIG_VIDEO_IMX_PXP policy<{'arm64': '-'}> +CONFIG_VIDEO_MALI_C55 policy<{'arm64': '-'}> +CONFIG_VIDEO_MEDIATEK_JPEG policy<{'arm64': '-'}> +CONFIG_VIDEO_MEDIATEK_MDP policy<{'arm64': '-'}> +CONFIG_VIDEO_MEDIATEK_MDP3 policy<{'arm64': '-'}> +CONFIG_VIDEO_MEDIATEK_VCODEC policy<{'arm64': '-'}> +CONFIG_VIDEO_MEDIATEK_VCODEC_SCP policy<{'arm64': '-'}> +CONFIG_VIDEO_MEDIATEK_VCODEC_VPU policy<{'arm64': '-'}> +CONFIG_VIDEO_MEDIATEK_VPU policy<{'arm64': '-'}> +CONFIG_VIDEO_MESON_GE2D policy<{'arm64': '-'}> +CONFIG_VIDEO_MESON_VDEC policy<{'arm64': '-'}> +CONFIG_VIDEO_MMP_CAMERA policy<{'arm64': '-'}> +CONFIG_VIDEO_NPCM_VCD_ECE policy<{'arm64': '-'}> +CONFIG_VIDEO_RCAR_CSI2 policy<{'arm64': '-'}> +CONFIG_VIDEO_RCAR_DRIF policy<{'arm64': '-'}> +CONFIG_VIDEO_RCAR_ISP policy<{'arm64': '-'}> +CONFIG_VIDEO_RCAR_VIN policy<{'arm64': '-'}> +CONFIG_VIDEO_RENESAS_FCP policy<{'arm64': '-'}> +CONFIG_VIDEO_RENESAS_FDP1 policy<{'arm64': '-'}> +CONFIG_VIDEO_RENESAS_JPU policy<{'arm64': '-'}> +CONFIG_VIDEO_RENESAS_VSP1 policy<{'arm64': '-'}> +CONFIG_VIDEO_ROCKCHIP_CIF policy<{'arm64': '-'}> +CONFIG_VIDEO_ROCKCHIP_ISP1 policy<{'arm64': '-'}> +CONFIG_VIDEO_ROCKCHIP_RGA policy<{'arm64': '-'}> +CONFIG_VIDEO_ROCKCHIP_VDEC policy<{'arm64': '-'}> +CONFIG_VIDEO_RZG2L_CRU policy<{'arm64': '-'}> +CONFIG_VIDEO_RZG2L_CSI2 policy<{'arm64': '-'}> +CONFIG_VIDEO_RZV2H_IVC policy<{'arm64': '-'}> +CONFIG_VIDEO_STM32_CSI policy<{'arm64': '-'}> +CONFIG_VIDEO_STM32_DCMI policy<{'arm64': '-'}> +CONFIG_VIDEO_STM32_DCMIPP policy<{'arm64': '-'}> +CONFIG_VIDEO_STM32_DMA2D policy<{'arm64': '-'}> +CONFIG_VIDEO_SUN4I_CSI policy<{'arm64': '-'}> +CONFIG_VIDEO_SUN6I_CSI policy<{'arm64': '-'}> +CONFIG_VIDEO_SUN6I_ISP policy<{'arm64': '-'}> +CONFIG_VIDEO_SUN6I_MIPI_CSI2 policy<{'arm64': '-'}> +CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 policy<{'arm64': '-'}> +CONFIG_VIDEO_SUN8I_DEINTERLACE policy<{'arm64': '-'}> +CONFIG_VIDEO_SUN8I_ROTATE policy<{'arm64': '-'}> +CONFIG_VIDEO_SUNXI policy<{'arm64': '-'}> +CONFIG_VIDEO_SUNXI_CEDRUS policy<{'arm64': '-'}> +CONFIG_VIDEO_SYNOPSYS_HDMIRX policy<{'arm64': '-'}> +CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID policy<{'arm64': '-'}> +CONFIG_VIDEO_TEGRA policy<{'arm64': '-'}> +CONFIG_VIDEO_TEGRA_TPG policy<{'arm64': '-'}> +CONFIG_VIDEO_TEGRA_VDE policy<{'arm64': '-'}> +CONFIG_VIDEO_TI_CAL policy<{'arm64': '-'}> +CONFIG_VIDEO_TI_CAL_MC policy<{'arm64': '-'}> +CONFIG_VIDEO_TI_J721E_CSI2RX policy<{'arm64': '-'}> +CONFIG_VIDEO_WAVE_VPU policy<{'arm64': '-'}> +CONFIG_VISCONTI_WATCHDOG policy<{'arm64': '-'}> +CONFIG_VMAP_PFN policy<{'arm64': '-'}> +CONFIG_W1_MASTER_MXC policy<{'arm64': '-'}> +CONFIG_WLAN_VENDOR_BCMDHD policy<{'arm64': '-'}> +CONFIG_XE_VFIO_PCI policy<{'arm64': '-'}> +CONFIG_XGENE_DMA policy<{'arm64': '-'}> +CONFIG_XGENE_PMU policy<{'arm64': '-'}> +CONFIG_XGENE_SLIMPRO_MBOX policy<{'arm64': '-'}> +CONFIG_XILINX_AMS policy<{'arm64': '-'}> +CONFIG_XLNX_EVENT_MANAGER policy<{'arm64': '-'}> +CONFIG_XLNX_R5_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_ZYNQMP_FIRMWARE policy<{'arm64': '-'}> +CONFIG_ZYNQMP_FIRMWARE_DEBUG policy<{'arm64': '-'}> +CONFIG_ZYNQMP_IPI_MBOX policy<{'arm64': '-'}> +CONFIG_ZYNQMP_PM_DOMAINS policy<{'arm64': '-'}> +CONFIG_ZYNQMP_POWER policy<{'arm64': '-'}> diff --git a/debian.qcom/control.d/flavour-control.stub b/debian.qcom/control.d/flavour-control.stub new file mode 100644 index 0000000000000..4055c769adb64 --- /dev/null +++ b/debian.qcom/control.d/flavour-control.stub @@ -0,0 +1,87 @@ +# Items that get replaced: +# FLAVOUR +# ARCH +# SUPPORTED +# TARGET +# BOOTLOADER +# =PROVIDES= +# +# Items marked with =FOO= are optional +# +# This file describes the template for packages that are created for each flavour +# in debian/control.d/vars.* +# +# This file gets edited in a couple of places. See the debian/control.stub rule in +# debian/rules. PGGVER, ABINUM, and SRCPKGNAME are all converted in the +# process of creating debian/control. +# +# The flavour specific strings (ARCH, etc) are converted using values from the various +# flavour files in debian/control.d/vars.* +# +# XXX: Leave the blank line before the first package!! + +Package: linux-modules-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, wireless-regdb +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel modules for version PKGVER + Contains the corresponding System.map file, the modules built by the + packager, and scripts that try to ensure that the system is not left in an + unbootable state after an update. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-headers-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-headers-PKGVER-ABINUM, ${shlibs:Depends} +Provides: linux-headers, linux-headers-3.0 +Description: Linux kernel headers for version PKGVER + This package provides kernel header files for version PKGVER. + . + This is for sites that want the latest kernel headers. Please read + /usr/share/doc/linux-headers-PKGVER-ABINUM/debian.README.gz for details. + +Package: linux-lib-rust-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: amd64 +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Rust library files related to Linux kernel version PKGVER + This package provides kernel library files for version PKGVER, that allow to + compile out-of-tree kernel modules written in Rust. + +Package: linux-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-tools-PKGVER-ABINUM +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as x86_energy_perf_policy) for + version PKGVER-ABINUM. + +Package: linux-cloud-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud for version PKGVER-ABINUM. + diff --git a/debian.qcom/control.d/flavour-signed-control.stub b/debian.qcom/control.d/flavour-signed-control.stub new file mode 100644 index 0000000000000..b8551a52e743f --- /dev/null +++ b/debian.qcom/control.d/flavour-signed-control.stub @@ -0,0 +1,38 @@ +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Provides: linux-image, fuse-module, =PROVIDES=${linux:rprovides} +Depends: ${misc:Depends}, ${shlibs:Depends}, kmod, linux-base (>= 4.5ubuntu1~16.04.1), linux-modules-PKGVER-ABINUM-FLAVOUR +Recommends: BOOTLOADER, initramfs-tools | linux-initramfs-tool +Breaks: flash-kernel (<< 3.90ubuntu2) [arm64 armhf], s390-tools (<< 2.3.0-0ubuntu3) [s390x] +Conflicts: linux-image=SIGN-PEER-PKG=-PKGVER-ABINUM-FLAVOUR +Suggests: bpftool, linux-perf, SRCPKGNAME-tools, linux-headers-PKGVER-ABINUM-FLAVOUR +Description: Linux kernel image for version PKGVER + This package contains the=SIGN-ME-TXT= Linux kernel image for version PKGVER. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR-dbgsym +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends} +Provides: linux-debug +Description: Linux kernel debug image for version PKGVER + This package provides the=SIGN-ME-TXT= kernel debug image for version PKGVER. + . + This is for sites that wish to debug the kernel. + . + The kernel image contained in this package is NOT meant to boot from. It + is uncompressed, and unstripped. This package also includes the + unstripped modules. + diff --git a/debian.qcom/control.d/vars.qcom b/debian.qcom/control.d/vars.qcom new file mode 100644 index 0000000000000..05645c172e0dd --- /dev/null +++ b/debian.qcom/control.d/vars.qcom @@ -0,0 +1,6 @@ +arch="arm64" +supported="Qualcomm SoC" +target="Geared toward desktop and server systems." +desc="=HUMAN= SMP" +bootloader="grub-pc [amd64] | grub-efi-amd64 [amd64] | grub-efi-ia32 [amd64] | grub [amd64] | lilo [amd64] | flash-kernel [armhf arm64] | grub-efi-arm64 [arm64] | grub-efi-arm [armhf] | grub-ieee1275 [ppc64el]" +provides="kvm-api-4, redhat-cluster-modules, ivtv-modules, virtualbox-guest-modules [amd64]" diff --git a/debian.qcom/control.stub.in b/debian.qcom/control.stub.in new file mode 100644 index 0000000000000..9bf2ad3269dce --- /dev/null +++ b/debian.qcom/control.stub.in @@ -0,0 +1,98 @@ +Source: SRCPKGNAME +Section: devel +Priority: optional +Maintainer: Ubuntu Kernel Team +Rules-Requires-Root: no +Standards-Version: 3.9.4.0 +Build-Depends: + autoconf , + automake , + bc , + bindgen:native [amd64 arm64 armhf ppc64el riscv64 s390x], + bison , + clang-19:native [amd64 arm64 armhf ppc64el riscv64 s390x], + cpio, + curl , + debhelper-compat (= 10), + default-jdk-headless:native , + dkms , + flex , + gawk , + java-common , + kmod , + libaudit-dev , + libcap-dev , + libdebuginfod-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libdw-dev , + libelf-dev , + libiberty-dev , + liblzma-dev , + libnewt-dev , + libnuma-dev [amd64 arm64 ppc64el s390x] , + libpci-dev , + libssl-dev , + libstdc++-dev, + libtool , + libtraceevent-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libtracefs-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libudev-dev , + libunwind8-dev [amd64 arm64 armhf ppc64el] , + makedumpfile:native [amd64] , + openssl , + pahole (>= 1.29-2ubuntu2) [amd64 arm64 armhf ppc64el s390x riscv64] | dwarves (>= 1.21) [amd64 arm64 armhf ppc64el s390x riscv64] , + pkg-config , + python3:native , + python3-dev:native , + libpython3-dev , + python3-setuptools, + rsync [!i386] , + rust-src:native [amd64 arm64 armhf ppc64el riscv64 s390x], + rustc:native (>= 1.82) [amd64 arm64 armhf ppc64el riscv64 s390x], + rustfmt:native [amd64 arm64 armhf ppc64el riscv64 s390x], + uuid-dev , + zstd , + bpftool:native [amd64 arm64 armhf ppc64el riscv64 s390x] , +Build-Depends-Indep: + asciidoc , + bzip2 , + python3-docutils , + sharutils , + xmlto , +Vcs-Git: git://git.launchpad.net/~ubuntu-kernel/ubuntu/+source/linux/+git/=SERIES= +XS-Testsuite: autopkgtest +#XS-Testsuite-Depends: gcc-4.7 binutils + +Package: SRCPKGNAME-headers-PKGVER-ABINUM +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Header files related to Linux kernel version PKGVER + This package provides kernel header files for version PKGVER, for sites + that want the latest kernel headers. Please read + /usr/share/doc/SRCPKGNAME-headers-PKGVER-ABINUM/debian.README.gz for details + +Package: SRCPKGNAME-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 armhf arm64 ppc64el s390x +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-tools-common +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as perf and x86_energy_perf_policy) for + version PKGVER-ABINUM. + You probably want to install linux-tools-PKGVER-ABINUM-. + +Package: SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 armhf +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-cloud-tools-common +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud tools for version PKGVER-ABINUM. + You probably want to install linux-cloud-tools-PKGVER-ABINUM-. diff --git a/debian.qcom/dkms-versions b/debian.qcom/dkms-versions new file mode 100644 index 0000000000000..0e93a2219d97c --- /dev/null +++ b/debian.qcom/dkms-versions @@ -0,0 +1 @@ +v4l2loopback 0.15.0-0ubuntu2 modulename=v4l2loopback debpath=pool/universe/v/%package%/v4l2loopback-dkms_%version%_all.deb arch=amd64 rprovides=v4l2loopback-modules rprovides=v4l2loopback-dkms diff --git a/debian.qcom/etc/update.conf b/debian.qcom/etc/update.conf new file mode 100644 index 0000000000000..3917a390a39f5 --- /dev/null +++ b/debian.qcom/etc/update.conf @@ -0,0 +1,7 @@ +# WARNING: we do not create update.conf when we are not a +# derivative. Various cranky components make use of this. +# If we start unconditionally creating update.conf we need +# to fix at least cranky close and cranky rebase. +RELEASE_REPO=git://git.launchpad.net/~ubuntu-kernel/ubuntu/+source/linux/+git/resolute +SOURCE_RELEASE_BRANCH=master-next +DEBIAN_MASTER=debian.master diff --git a/debian.qcom/modprobe.d/common.conf b/debian.qcom/modprobe.d/common.conf new file mode 100644 index 0000000000000..e0fbbd6e060d4 --- /dev/null +++ b/debian.qcom/modprobe.d/common.conf @@ -0,0 +1,3 @@ +# LP:1434842 -- disable OSS drivers by default to allow pulseaudio to emulate +blacklist snd-mixer-oss +blacklist snd-pcm-oss diff --git a/debian.qcom/reconstruct b/debian.qcom/reconstruct new file mode 100644 index 0000000000000..007db83ee5931 --- /dev/null +++ b/debian.qcom/reconstruct @@ -0,0 +1,39 @@ +# Recreate any symlinks created since the orig. +chmod +x 'debian/cloud-tools/hv_get_dhcp_info' +chmod +x 'debian/cloud-tools/hv_get_dns_info' +chmod +x 'debian/cloud-tools/hv_set_ifconfig' +chmod +x 'debian/rules' +chmod +x 'debian/scripts/checks/final-checks' +chmod +x 'debian/scripts/checks/module-signature-check' +chmod +x 'debian/scripts/control-create' +chmod +x 'debian/scripts/dkms-build' +chmod +x 'debian/scripts/dkms-build--nvidia-N' +chmod +x 'debian/scripts/dkms-build-configure--zfs' +chmod +x 'debian/scripts/file-downloader' +chmod +x 'debian/scripts/link-headers' +chmod +x 'debian/scripts/link-lib-rust' +chmod +x 'debian/scripts/misc/annotations' +chmod +x 'debian/scripts/misc/find-missing-sauce.sh' +chmod +x 'debian/scripts/misc/gen-auto-reconstruct' +chmod +x 'debian/scripts/misc/git-ubuntu-log' +chmod +x 'debian/scripts/misc/insert-changes' +chmod +x 'debian/scripts/misc/insert-ubuntu-changes' +chmod +x 'debian/scripts/misc/kernelconfig' +chmod +x 'debian/scripts/sign-module' +chmod +x 'debian/templates/extra.postinst.in' +chmod +x 'debian/templates/extra.postrm.in' +chmod +x 'debian/templates/headers.postinst.in' +chmod +x 'debian/templates/image.postinst.in' +chmod +x 'debian/templates/image.postrm.in' +chmod +x 'debian/templates/image.preinst.in' +chmod +x 'debian/templates/image.prerm.in' +chmod +x 'debian/tests/rebuild' +chmod +x 'debian/tests/ubuntu-regression-suite' +# Remove any files deleted from the orig. +rm -f 'arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi' +rm -f 'arch/arm64/boot/dts/qcom/qcs8300.dtsi' +rm -f 'arch/arm64/boot/dts/qcom/sm6150.dtsi' +rm -f 'arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi' +rm -f 'arch/arm64/boot/dts/qcom/x1e80100.dtsi' +rm -f 'drivers/media/platform/qcom/iris/iris_platform_sm8250.c' +exit 0 diff --git a/debian.qcom/rules.d/arm64.mk b/debian.qcom/rules.d/arm64.mk new file mode 100644 index 0000000000000..ccbbf22620230 --- /dev/null +++ b/debian.qcom/rules.d/arm64.mk @@ -0,0 +1,18 @@ +build_arch = arm64 +defconfig = defconfig +flavours = qcom +build_image = Image.gz +kernel_file = arch/$(build_arch)/boot/Image.gz +install_file = vmlinuz +no_dumpfile = true + +vdso = vdso_install + +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true + +do_dtbs = true diff --git a/debian.qcom/tracking-bug b/debian.qcom/tracking-bug new file mode 100644 index 0000000000000..d3b4c49558578 --- /dev/null +++ b/debian.qcom/tracking-bug @@ -0,0 +1 @@ +2133502 d2025.10.20-6 diff --git a/debian.qcom/upstream-stable b/debian.qcom/upstream-stable new file mode 100644 index 0000000000000..30e10948e88f9 --- /dev/null +++ b/debian.qcom/upstream-stable @@ -0,0 +1,3 @@ +# The following upstream stable releases have been ported: +[upstream-stable] + linux-6.17.y = v6.17.1 diff --git a/debian.qcom/variants b/debian.qcom/variants new file mode 100644 index 0000000000000..4ba280517af59 --- /dev/null +++ b/debian.qcom/variants @@ -0,0 +1 @@ +-- diff --git a/debian/debian.env b/debian/debian.env index be31a0c270197..d75a9cb98131f 100644 --- a/debian/debian.env +++ b/debian/debian.env @@ -1 +1 @@ -DEBIAN=debian.master +DEBIAN=debian.qcom From 1fd2d6e8a1c7234b7ef855fa081196bb77cf20fe Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 27 Apr 2026 17:58:47 +0200 Subject: [PATCH 0562/1330] add RT flavor Signed-off-by: Kuba Pawlak --- debian.qcom/config/annotations | 120 ++++++++++++++++++++- debian.qcom/control.d/flavour-control.stub | 19 +--- debian.qcom/control.d/vars.qcom-rt | 6 ++ debian.qcom/control.stub.in | 19 ++-- debian.qcom/rules.d/arm64.mk | 4 +- debian.qcom/variants | 1 + 6 files changed, 137 insertions(+), 32 deletions(-) create mode 100644 debian.qcom/control.d/vars.qcom-rt diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 49d5e8694bdb5..9521c3fb9f7ef 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -1,8 +1,8 @@ # Menu: HEADER # FORMAT: 4 # ARCH: arm64 -# FLAVOUR: arm64-qcom -# FLAVOUR_DEP: {'arm64-qcom': 'arm64-generic'} +# FLAVOUR: arm64-qcom arm64-qcom-rt +# FLAVOUR_DEP: {'arm64-qcom': 'arm64-generic', 'arm64-qcom-rt': 'arm64-generic'} include "../../debian.master/config/annotations" @@ -36,6 +36,9 @@ CONFIG_IPMMU_VMSA note<'LP: #1718734'> CONFIG_KERNEL_ZSTD policy<{'arm64': '-'}> CONFIG_KERNEL_ZSTD note<'we use arch/arm64/boot/Image.gz'> +CONFIG_KVM policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> +CONFIG_KVM note<'TODO: update note'> + CONFIG_MMC_SDHCI policy<{'arm64': 'y'}> CONFIG_MMC_SDHCI note<'installation essential on omap/highbank'> @@ -45,6 +48,18 @@ CONFIG_MMC_SDHCI_PLTFM note<'boot essential on highbank CONFIG_NR_CPUS policy<{'arm64': '256'}> CONFIG_NR_CPUS note<'LP: #2042897 (arm64), LP: #1967889 (riscv64), LP: #1864198 (s390x)'> +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED note<'TODO: update note'> + +CONFIG_PREEMPT_DYNAMIC policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> +CONFIG_PREEMPT_DYNAMIC note<'TODO: update note'> + +CONFIG_RCU_LAZY policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> +CONFIG_RCU_LAZY note<'TODO: update note'> + +CONFIG_RCU_LAZY_DEFAULT_OFF policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_RCU_LAZY_DEFAULT_OFF note<'TODO: update note'> + CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'arm64': 'y'}> CONFIG_REGULATOR_FIXED_VOLTAGE note<'boot essential on arm'> @@ -111,6 +126,7 @@ CONFIG_ARCH_BERLIN policy<{'arm64': 'n'}> CONFIG_ARCH_BITMAIN policy<{'arm64': 'n'}> CONFIG_ARCH_BLAIZE policy<{'arm64': 'n'}> CONFIG_ARCH_CIX policy<{'arm64': 'n'}> +CONFIG_ARCH_ENABLE_THP_MIGRATION policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_ARCH_FORCE_MAX_ORDER policy<{'arm64': '10'}> CONFIG_ARCH_HAS_RESET_CONTROLLER policy<{'arm64': '-'}> CONFIG_ARCH_HISI policy<{'arm64': 'n'}> @@ -168,6 +184,8 @@ CONFIG_ARCH_SPARX5 policy<{'arm64': 'n'}> CONFIG_ARCH_SPRD policy<{'arm64': 'n'}> CONFIG_ARCH_STM32 policy<{'arm64': 'n'}> CONFIG_ARCH_SUNXI policy<{'arm64': 'n'}> +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_ARCH_SYNQUACER policy<{'arm64': 'n'}> CONFIG_ARCH_TEGRA policy<{'arm64': 'n'}> CONFIG_ARCH_TEGRA_132_SOC policy<{'arm64': '-'}> @@ -181,9 +199,12 @@ CONFIG_ARCH_THUNDER policy<{'arm64': 'n'}> CONFIG_ARCH_THUNDER2 policy<{'arm64': 'n'}> CONFIG_ARCH_VEXPRESS policy<{'arm64': 'n'}> CONFIG_ARCH_VISCONTI policy<{'arm64': 'n'}> +CONFIG_ARCH_WANT_PMD_MKWRITE policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_ARCH_XGENE policy<{'arm64': 'n'}> CONFIG_ARCH_ZYNQMP policy<{'arm64': 'n'}> CONFIG_ARC_EMAC_CORE policy<{'arm64': '-'}> +CONFIG_ARM64_CONTPTE policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_ARM64_ERRATUM_834220 policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_ARMADA_37XX_CLK policy<{'arm64': '-'}> CONFIG_ARMADA_37XX_RWTM_MBOX policy<{'arm64': '-'}> CONFIG_ARMADA_37XX_WATCHDOG policy<{'arm64': '-'}> @@ -240,13 +261,21 @@ CONFIG_BCMDHD_SDIO policy<{'arm64': '-'}> CONFIG_BCMDHD_SDIO_IRQ policy<{'arm64': '-'}> CONFIG_BCMDHD_USB policy<{'arm64': '-'}> CONFIG_BERLIN2_ADC policy<{'arm64': '-'}> +CONFIG_BLK_CGROUP_IOLATENCY policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> +CONFIG_BRIDGE_EBT_BROUTE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_BRIDGE_EBT_T_FILTER policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_BRIDGE_EBT_T_NAT policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_BRIDGE_NF_EBTABLES_LEGACY policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_CAN_BXCAN policy<{'arm64': '-'}> CONFIG_CAN_RCAR policy<{'arm64': '-'}> CONFIG_CAN_RCAR_CANFD policy<{'arm64': '-'}> CONFIG_CAN_ROCKCHIP_CANFD policy<{'arm64': '-'}> CONFIG_CAVIUM_CPT policy<{'arm64': '-'}> +CONFIG_CEC_GPIO policy<{'arm64': 'm', 'arm64-qcom-rt': 'n'}> CONFIG_CEC_MESON_AO policy<{'arm64': '-'}> CONFIG_CEC_MESON_G12A_AO policy<{'arm64': '-'}> +CONFIG_CEC_PIN policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_CEC_PIN_ERROR_INJ policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_CEC_STM32 policy<{'arm64': '-'}> CONFIG_CEC_TEGRA policy<{'arm64': '-'}> CONFIG_CHARGER_CPCAP policy<{'arm64': '-'}> @@ -533,6 +562,7 @@ CONFIG_COMMON_CLK_VISCONTI policy<{'arm64': '-'}> CONFIG_COMMON_CLK_ZYNQMP policy<{'arm64': '-'}> CONFIG_COMMON_RESET_HI3660 policy<{'arm64': '-'}> CONFIG_COMMON_RESET_HI6220 policy<{'arm64': '-'}> +CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'arm64': '1', 'arm64-qcom-rt': '0'}> CONFIG_CPUMASK_OFFSTACK policy<{'arm64': '-'}> CONFIG_CRC7 policy<{'arm64': 'y'}> CONFIG_CRC_ITU_T policy<{'arm64': 'y'}> @@ -595,8 +625,16 @@ CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 policy<{'arm64': '-'}> CONFIG_CV1800_MBOX policy<{'arm64': '-'}> CONFIG_CZNIC_PLATFORMS policy<{'arm64': '-'}> CONFIG_DEBUG_KERNEL_DC policy<{'arm64': '-'}> +CONFIG_DEBUG_MUTEXES policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_DEBUG_RWSEMS policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_DETECT_HUNG_TASK_BLOCKER policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI policy<{'arm64': '-'}> +CONFIG_DEV_DAX policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_DEV_DAX_CXL policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_DEV_DAX_KMEM policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_DEV_DAX_PMEM policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_DMA_SUN6I policy<{'arm64': '-'}> +CONFIG_DM_PCACHE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_DPAA2_CONSOLE policy<{'arm64': '-'}> CONFIG_DPAA_ERRATUM_A050385 policy<{'arm64': '-'}> CONFIG_DRM_ACCEL_ROCKET policy<{'arm64': '-'}> @@ -789,6 +827,7 @@ CONFIG_FSL_MC_BUS policy<{'arm64': '-'}> CONFIG_FSL_MC_DPIO policy<{'arm64': '-'}> CONFIG_FSL_MC_UAPI_SUPPORT policy<{'arm64': '-'}> CONFIG_FSL_QMAN_TEST policy<{'arm64': '-'}> +CONFIG_FS_DAX_PMD policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_FUEL_GAUGE_SC27XX policy<{'arm64': '-'}> CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT policy<{'arm64': 'y'}> CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND policy<{'arm64': '-'}> @@ -823,6 +862,7 @@ CONFIG_GPIO_XGENE_SB policy<{'arm64': '-'}> CONFIG_GPIO_XLP policy<{'arm64': '-'}> CONFIG_GPIO_ZYNQ policy<{'arm64': '-'}> CONFIG_GPIO_ZYNQMP_MODEPIN policy<{'arm64': '-'}> +CONFIG_GUEST_PERF_EVENTS policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_GUNYAH policy<{'arm64': '-'}> CONFIG_GUNYAH_DRIVERS policy<{'arm64': '-'}> CONFIG_GUNYAH_IOEVENTFD policy<{'arm64': '-'}> @@ -833,6 +873,16 @@ CONFIG_GUNYAH_VCPU policy<{'arm64': '-'}> CONFIG_GUNYAH_WATCHDOG policy<{'arm64': 'y'}> CONFIG_HAVE_KERNEL_GZIP policy<{'arm64': '-'}> CONFIG_HAVE_KERNEL_ZSTD policy<{'arm64': '-'}> +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_KVM_DIRTY_RING policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_KVM_IRQCHIP policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_KVM_IRQ_BYPASS policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_KVM_IRQ_ROUTING policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_KVM_MSI policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_KVM_READONLY_MEM policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_SCHED_AVG_IRQ policy<{'arm64-qcom-rt': 'y'}> CONFIG_HBMC_AM654 policy<{'arm64': '-'}> CONFIG_HI3660_MBOX policy<{'arm64': '-'}> CONFIG_HI6220_MBOX policy<{'arm64': '-'}> @@ -960,6 +1010,14 @@ CONFIG_INTERCONNECT_QCOM_SM8450 policy<{'arm64': 'y'}> CONFIG_INTERCONNECT_QCOM_SM8550 policy<{'arm64': 'y'}> CONFIG_INTERCONNECT_QCOM_SM8650 policy<{'arm64': 'y'}> CONFIG_INTERCONNECT_QCOM_X1E80100 policy<{'arm64': 'y'}> +CONFIG_IP6_NF_FILTER policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP6_NF_IPTABLES_LEGACY policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP6_NF_MANGLE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP6_NF_NAT policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP6_NF_RAW policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP6_NF_SECURITY policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP6_NF_TARGET_HL policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP6_NF_TARGET_MASQUERADE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_IPMI_KCS_BMC policy<{'arm64': '-'}> CONFIG_IPMI_KCS_BMC_CDEV_IPMI policy<{'arm64': '-'}> CONFIG_IPMI_KCS_BMC_SERIO policy<{'arm64': '-'}> @@ -969,6 +1027,21 @@ CONFIG_IPQ_GCC_5332 policy<{'arm64': 'y'}> CONFIG_IPQ_GCC_6018 policy<{'arm64': 'y'}> CONFIG_IPQ_GCC_8074 policy<{'arm64': 'y'}> CONFIG_IPQ_GCC_9574 policy<{'arm64': 'y'}> +CONFIG_IP_NF_ARPFILTER policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_ARPTABLES policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_FILTER policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_IPTABLES_LEGACY policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_MANGLE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_NAT policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_RAW policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_SECURITY policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_TARGET_MASQUERADE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_TARGET_NETMAP policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_TARGET_REDIRECT policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IP_NF_TARGET_TTL policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_IRQ_BYPASS_MANAGER policy<{'arm64': 'y', 'arm64-qcom-rt': 'm'}> +CONFIG_IRQ_TIME_ACCOUNTING policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> +CONFIG_IR_GPIO_TX policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_IR_MESON policy<{'arm64': '-'}> CONFIG_IR_MESON_TX policy<{'arm64': '-'}> CONFIG_IR_MTK policy<{'arm64': '-'}> @@ -995,10 +1068,17 @@ CONFIG_KEYBOARD_SUN4I_LRADC policy<{'arm64': '-'}> CONFIG_KEYBOARD_TEGRA policy<{'arm64': '-'}> CONFIG_KHADAS_MCU_FAN_THERMAL policy<{'arm64': '-'}> CONFIG_KUNPENG_HCCS policy<{'arm64': '-'}> +CONFIG_KVM_COMMON policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_KVM_GENERIC_HARDWARE_ENABLING policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_KVM_GUEST_MEMFD policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_KVM_MMIO policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_KVM_VFIO policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_LAN966X_OIC policy<{'arm64': '-'}> CONFIG_LAN969X_SWITCH policy<{'arm64': '-'}> CONFIG_LEDS_SC27XX_BLTC policy<{'arm64': '-'}> CONFIG_LEDS_SUN50I_A100 policy<{'arm64': '-'}> +CONFIG_LEDS_TRIGGER_CPU policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_LEGACY_PTY_COUNT policy<{'arm64': '-'}> CONFIG_LOG_BUF_SHIFT policy<{'arm64': '17'}> CONFIG_LSM_MMAP_MIN_ADDR policy<{'arm64': '32768'}> @@ -1092,6 +1172,7 @@ CONFIG_MMC_SUNXI policy<{'arm64': '-'}> CONFIG_MMC_TMIO_CORE policy<{'arm64': '-'}> CONFIG_MMP_PDMA policy<{'arm64': '-'}> CONFIG_MMP_TDMA policy<{'arm64': '-'}> +CONFIG_MM_ID policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_MSM_GCC_8916 policy<{'arm64': 'y'}> CONFIG_MSM_GCC_8994 policy<{'arm64': 'y'}> CONFIG_MSM_GCC_8998 policy<{'arm64': 'y'}> @@ -1162,6 +1243,10 @@ CONFIG_MV_XOR policy<{'arm64': '-'}> CONFIG_MXC_CLK policy<{'arm64': '-'}> CONFIG_MXC_CLK_SCU policy<{'arm64': '-'}> CONFIG_MXS_DMA policy<{'arm64': '-'}> +CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_NETFILTER_XTABLES_LEGACY policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_NETFILTER_XT_TARGET_NOTRACK policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> +CONFIG_NETFILTER_XT_TARGET_TRACE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_NET_AIROHA policy<{'arm64': '-'}> CONFIG_NET_AIROHA_FLOW_STATS policy<{'arm64': '-'}> CONFIG_NET_AIROHA_NPU policy<{'arm64': '-'}> @@ -1182,12 +1267,15 @@ CONFIG_NOUVEAU_DEBUG_DEFAULT policy<{'arm64': '-'}> CONFIG_NOUVEAU_DEBUG_MMU policy<{'arm64': '-'}> CONFIG_NOUVEAU_DEBUG_PUSH policy<{'arm64': '-'}> CONFIG_NOUVEAU_PLATFORM_DRIVER policy<{'arm64': '-'}> +CONFIG_NO_PAGE_MAPCOUNT policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_NPCM7XX_KCS_IPMI_BMC policy<{'arm64': '-'}> CONFIG_NPCM7XX_TIMER policy<{'arm64': '-'}> CONFIG_NPCM7XX_WATCHDOG policy<{'arm64': '-'}> CONFIG_NPCM_ADC policy<{'arm64': '-'}> +CONFIG_NUMA_BALANCING policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_NVEC_PAZ00 policy<{'arm64': '-'}> CONFIG_NVEC_POWER policy<{'arm64': '-'}> +CONFIG_NVHE_EL2_DEBUG policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_NVMEM_APPLE_EFUSES policy<{'arm64': '-'}> CONFIG_NVMEM_APPLE_SPMI policy<{'arm64': '-'}> CONFIG_NVMEM_IMX_IIM policy<{'arm64': '-'}> @@ -1288,6 +1376,7 @@ CONFIG_PCI_TEGRA policy<{'arm64': '-'}> CONFIG_PCS_LYNX policy<{'arm64': 'm'}> CONFIG_PCS_RZN1_MIIC policy<{'arm64': '-'}> CONFIG_PECI_NPCM policy<{'arm64': '-'}> +CONFIG_PERSISTENT_HUGE_ZERO_FOLIO policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_PHYLINK policy<{'arm64': 'm'}> CONFIG_PHY_AIROHA_PCIE policy<{'arm64': '-'}> CONFIG_PHY_AM654_SERDES policy<{'arm64': '-'}> @@ -1575,7 +1664,11 @@ CONFIG_POWER_RESET_OCELOT_RESET policy<{'arm64': '-'}> CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF policy<{'arm64': '-'}> CONFIG_POWER_RESET_SC27XX policy<{'arm64': '-'}> CONFIG_POWER_RESET_TORADEX_EC policy<{'arm64': '-'}> +CONFIG_PREEMPT_NOTIFIERS policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_PREEMPT_RT policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> +CONFIG_PREEMPT_RT_NEEDS_BH_LOCK policy<{'arm64-qcom-rt': 'n'}> CONFIG_PRU_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_PTDUMP_STAGE2_DEBUGFS policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_PTP_QCOM_CLOCK_TSC policy<{'arm64': '-'}> CONFIG_PWC_RZV2M policy<{'arm64': '-'}> CONFIG_PWM_AIROHA policy<{'arm64': '-'}> @@ -1686,12 +1779,17 @@ CONFIG_QORIQ_THERMAL policy<{'arm64': '-'}> CONFIG_QTI_BCL_PMIC5 policy<{'arm64': '-'}> CONFIG_QTI_DEVFREQ_CDEV policy<{'arm64': '-'}> CONFIG_QTI_TZ_LOG policy<{'arm64': '-'}> +CONFIG_QUEUED_RWLOCKS policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_RAVB policy<{'arm64': '-'}> CONFIG_RCAR_DMAC policy<{'arm64': '-'}> CONFIG_RCAR_GEN3_THERMAL policy<{'arm64': '-'}> CONFIG_RCAR_REMOTEPROC policy<{'arm64': '-'}> CONFIG_RCAR_THERMAL policy<{'arm64': '-'}> +CONFIG_RCU_BOOST policy<{'arm64-qcom-rt': 'y'}> +CONFIG_RCU_BOOST_DELAY policy<{'arm64-qcom-rt': '500'}> CONFIG_RCU_CPU_STALL_TIMEOUT policy<{'arm64': '21'}> +CONFIG_RCU_NOCB_CPU_CB_BOOST policy<{'arm64-qcom-rt': 'y'}> +CONFIG_READ_ONLY_THP_FOR_FS policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_REBOOT_MODE policy<{'arm64': 'y'}> CONFIG_REGMAP_AC97 policy<{'arm64': '-'}> CONFIG_REGMAP_SPMI policy<{'arm64': 'y'}> @@ -1811,7 +1909,6 @@ CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> CONFIG_RTSN policy<{'arm64': '-'}> -CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.92.0 (ded5c06cf 2025-12-08)"'}> CONFIG_RZG2L_ADC policy<{'arm64': '-'}> CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> @@ -2101,6 +2198,8 @@ CONFIG_SOC_TEGRA_FLOWCTRL policy<{'arm64': '-'}> CONFIG_SOC_TEGRA_FUSE policy<{'arm64': '-'}> CONFIG_SOC_TEGRA_PMC policy<{'arm64': '-'}> CONFIG_SOC_TEGRA_POWERGATE_BPMP policy<{'arm64': '-'}> +CONFIG_SOFTIRQ_ON_OWN_STACK policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_SOFTLOCKUP_DETECTOR_INTR_STORM policy<{'arm64-qcom-rt': 'n'}> CONFIG_SOPHGO_CV1800B_ADC policy<{'arm64': '-'}> CONFIG_SOPHGO_CV1800B_DMAMUX policy<{'arm64': '-'}> CONFIG_SOPHGO_CV1800_RTCSYS policy<{'arm64': '-'}> @@ -2277,7 +2376,9 @@ CONFIG_TEGRA_MC policy<{'arm64': '-'}> CONFIG_TEGRA_SOCTHERM policy<{'arm64': '-'}> CONFIG_TEGRA_TIMER policy<{'arm64': '-'}> CONFIG_TEGRA_WATCHDOG policy<{'arm64': '-'}> +CONFIG_TEST_HMM policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS policy<{'arm64': '10000'}> +CONFIG_THP_SWAP policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_THUNDERX2_PMU policy<{'arm64': '-'}> CONFIG_TIMER_IMX_SYS_CTR policy<{'arm64': '-'}> CONFIG_TI_AM335X_ADC policy<{'arm64': '-'}> @@ -2317,6 +2418,18 @@ CONFIG_TI_SYSCON_CLK policy<{'arm64': '-'}> CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C policy<{'arm64': 'n'}> CONFIG_TOUCHSCREEN_SUN4I policy<{'arm64': '-'}> CONFIG_TOUCHSCREEN_TI_AM335X_TSC policy<{'arm64': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_NEVER policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_ADVISE policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_ALWAYS policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_NEVER policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_WITHIN_SIZE policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_ADVISE policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_ALWAYS policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_NEVER policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_WITHIN_SIZE policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_TURRIS_MOX_RWTM policy<{'arm64': '-'}> CONFIG_TURRIS_MOX_RWTM_KEYCTL policy<{'arm64': '-'}> CONFIG_TURRIS_SIGNING_KEY policy<{'arm64': '-'}> @@ -2438,6 +2551,7 @@ CONFIG_VISCONTI_WATCHDOG policy<{'arm64': '-'}> CONFIG_VMAP_PFN policy<{'arm64': '-'}> CONFIG_W1_MASTER_MXC policy<{'arm64': '-'}> CONFIG_WLAN_VENDOR_BCMDHD policy<{'arm64': '-'}> +CONFIG_WQ_POWER_EFFICIENT_DEFAULT policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> CONFIG_XE_VFIO_PCI policy<{'arm64': '-'}> CONFIG_XGENE_DMA policy<{'arm64': '-'}> CONFIG_XGENE_PMU policy<{'arm64': '-'}> diff --git a/debian.qcom/control.d/flavour-control.stub b/debian.qcom/control.d/flavour-control.stub index 4055c769adb64..d206299a721fe 100644 --- a/debian.qcom/control.d/flavour-control.stub +++ b/debian.qcom/control.d/flavour-control.stub @@ -1,10 +1,12 @@ # Items that get replaced: # FLAVOUR +# DESC # ARCH # SUPPORTED # TARGET # BOOTLOADER # =PROVIDES= +# =DEPENDS= # # Items marked with =FOO= are optional # @@ -25,7 +27,7 @@ Build-Profiles: Architecture: ARCH Section: kernel Priority: optional -Depends: ${misc:Depends}, ${shlibs:Depends}, wireless-regdb +Depends: ${misc:Depends}, ${shlibs:Depends}, =DEPENDS=wireless-regdb Built-Using: ${linux:BuiltUsing} Description: Linux kernel modules for version PKGVER Contains the corresponding System.map file, the modules built by the @@ -53,9 +55,9 @@ Description: Linux kernel headers for version PKGVER This is for sites that want the latest kernel headers. Please read /usr/share/doc/linux-headers-PKGVER-ABINUM/debian.README.gz for details. -Package: linux-lib-rust-PKGVER-ABINUM-FLAVOUR +Package: SRCPKGNAME-lib-rust-PKGVER-ABINUM-FLAVOUR Build-Profiles: -Architecture: amd64 +Architecture: arm64 Multi-Arch: foreign Section: devel Priority: optional @@ -74,14 +76,3 @@ Description: Linux kernel version specific tools for version PKGVER-ABINUM This package provides the architecture dependant parts for kernel version locked tools (such as x86_energy_perf_policy) for version PKGVER-ABINUM. - -Package: linux-cloud-tools-PKGVER-ABINUM-FLAVOUR -Build-Profiles: -Architecture: ARCH -Section: devel -Priority: optional -Depends: ${misc:Depends}, SRCPKGNAME-cloud-tools-PKGVER-ABINUM -Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM - This package provides the architecture dependant parts for kernel - version locked tools for cloud for version PKGVER-ABINUM. - diff --git a/debian.qcom/control.d/vars.qcom-rt b/debian.qcom/control.d/vars.qcom-rt new file mode 100644 index 0000000000000..13d4794fc74ed --- /dev/null +++ b/debian.qcom/control.d/vars.qcom-rt @@ -0,0 +1,6 @@ +arch="arm64" +supported="Qualcomm SoC" +target="Geared toward realtime systems." +desc="=HUMAN= SMP" +bootloader="grub-pc [amd64] | grub-efi-amd64 [amd64] | grub-efi-ia32 [amd64] | grub [amd64] | lilo [amd64] | flash-kernel [armhf arm64] | grub-efi-arm64 [arm64] | grub-efi-arm [armhf] | grub-ieee1275 [ppc64el]" +provides="kvm-api-4, redhat-cluster-modules, ivtv-modules, virtualbox-guest-modules [amd64]" diff --git a/debian.qcom/control.stub.in b/debian.qcom/control.stub.in index 9bf2ad3269dce..11d4b108898c7 100644 --- a/debian.qcom/control.stub.in +++ b/debian.qcom/control.stub.in @@ -10,7 +10,7 @@ Build-Depends: bc , bindgen:native [amd64 arm64 armhf ppc64el riscv64 s390x], bison , - clang-19:native [amd64 arm64 armhf ppc64el riscv64 s390x], + clang-21:native [amd64 arm64 armhf ppc64el riscv64 s390x], cpio, curl , debhelper-compat (= 10), @@ -21,6 +21,7 @@ Build-Depends: java-common , kmod , libaudit-dev , + libbpf-dev , libcap-dev , libdebuginfod-dev [amd64 arm64 armhf ppc64el s390x riscv64] , libdw-dev , @@ -28,6 +29,8 @@ Build-Depends: libiberty-dev , liblzma-dev , libnewt-dev , + libnl-3-dev, + libnl-genl-3-dev, libnuma-dev [amd64 arm64 ppc64el s390x] , libpci-dev , libssl-dev , @@ -37,6 +40,7 @@ Build-Depends: libtracefs-dev [amd64 arm64 armhf ppc64el s390x riscv64] , libudev-dev , libunwind8-dev [amd64 arm64 armhf ppc64el] , + llvm-21-dev, makedumpfile:native [amd64] , openssl , pahole (>= 1.29-2ubuntu2) [amd64 arm64 armhf ppc64el s390x riscv64] | dwarves (>= 1.21) [amd64 arm64 armhf ppc64el s390x riscv64] , @@ -76,7 +80,7 @@ Description: Header files related to Linux kernel version PKGVER Package: SRCPKGNAME-tools-PKGVER-ABINUM Build-Profiles: -Architecture: amd64 armhf arm64 ppc64el s390x +Architecture: arm64 Section: devel Priority: optional Depends: ${misc:Depends}, ${shlibs:Depends}, linux-tools-common @@ -85,14 +89,3 @@ Description: Linux kernel version specific tools for version PKGVER-ABINUM version locked tools (such as perf and x86_energy_perf_policy) for version PKGVER-ABINUM. You probably want to install linux-tools-PKGVER-ABINUM-. - -Package: SRCPKGNAME-cloud-tools-PKGVER-ABINUM -Build-Profiles: -Architecture: amd64 armhf -Section: devel -Priority: optional -Depends: ${misc:Depends}, ${shlibs:Depends}, linux-cloud-tools-common -Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM - This package provides the architecture dependant parts for kernel - version locked tools for cloud tools for version PKGVER-ABINUM. - You probably want to install linux-cloud-tools-PKGVER-ABINUM-. diff --git a/debian.qcom/rules.d/arm64.mk b/debian.qcom/rules.d/arm64.mk index ccbbf22620230..d6fb228237969 100644 --- a/debian.qcom/rules.d/arm64.mk +++ b/debian.qcom/rules.d/arm64.mk @@ -1,10 +1,10 @@ build_arch = arm64 defconfig = defconfig -flavours = qcom +flavours = qcom qcom-rt build_image = Image.gz kernel_file = arch/$(build_arch)/boot/Image.gz install_file = vmlinuz -no_dumpfile = true +no_dumpfile = true vdso = vdso_install diff --git a/debian.qcom/variants b/debian.qcom/variants index 4ba280517af59..cab2f62a9df90 100644 --- a/debian.qcom/variants +++ b/debian.qcom/variants @@ -1 +1,2 @@ +-7.0 -- From cccbd348ba704949d0a9cb27067e2dff038cbea4 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 27 Apr 2026 18:07:58 +0200 Subject: [PATCH 0563/1330] UBUNTU: Start new release Ignore: yes Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 177a595752d4b..20f375082ab54 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,3 +1,11 @@ +linux-qcom (7.0.0-1004.4) UNRELEASED; urgency=medium + + CHANGELOG: Do not edit directly. Autogenerated at release. + CHANGELOG: Use the printchanges target to see the current changes. + CHANGELOG: Use the insertchanges target to create the final log. + + -- Kuba Pawlak Mon, 27 Apr 2026 18:07:58 +0200 + linux-qcom (7.0.0-1003.3) resolute; urgency=medium Initial variant of Qualcomm From 41b2284f4336471859096c5c61c125ac277c4698 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 27 Apr 2026 18:11:38 +0200 Subject: [PATCH 0564/1330] UBUNTU: Ubuntu-qcom-7.0.0-1004.5 Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 730 +++++++++++++++++++++++++++++++++++++++- debian.qcom/reconstruct | 7 +- 2 files changed, 726 insertions(+), 11 deletions(-) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 20f375082ab54..7b2ed6134e45b 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,10 +1,730 @@ -linux-qcom (7.0.0-1004.4) UNRELEASED; urgency=medium +linux-qcom (7.0.0-1004.5) resolute; urgency=medium - CHANGELOG: Do not edit directly. Autogenerated at release. - CHANGELOG: Use the printchanges target to see the current changes. - CHANGELOG: Use the insertchanges target to create the final log. + * Miscellaneous upstream changes + - UPSTREAM: dt-bindings: usb: qcom,snps-dwc3: Add the SM8750 compatible + - FROMLIST: dt-bindings: arm-smmu: Add compatible for Kaanapali and Glymur + SoCs + - FROMLIST: dt-bindings: firmware: qcom,scm: Document SCM on Kaanapali SOC + - FROMGIT: dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & + PMCX0102 + - FROMGIT: dt-bindings: rpmh-regulator: Update pmic-id DT prop info for + new CMD-DB + - FROMGIT: regulator: rpmh-regulator: Add RPMH regulator support for + Glymur + - FROMGIT: regulator: rpmh-regulator: Add RPMH regulator support for + PMR735D + - FROMGIT: regulator: dt-bindings: qcom,rpmh: Add support for PMR735D + - FROMLIST: dt-bindings: firmware: qcom,scm: Document Glymur scm + - FROMLIST: dt-bindings: usb: qcom,dwc3: Correct the SM8750 compatible + - FROMLIST: dmaengine: Add DMA_PREP_LOCK/DMA_PREP_UNLOCK flags + - FROMLIST: dmaengine: qcom: bam_dma: Extend the driver's device match + data + - FROMLIST: dmaengine: qcom: bam_dma: Add bam_pipe_lock flag support + - FROMLIST: crypto: qce - Include algapi.h in the core.h header + - FROMLIST: crypto: qce - Remove unused ignore_buf + - FROMLIST: crypto: qce - Simplify arguments of devm_qce_dma_request() + - FROMLIST: crypto: qce - Use existing devres APIs in + devm_qce_dma_request() + - FROMLIST: crypto: qce - Map crypto memory for DMA + - FROMLIST: crypto: qce - Add BAM DMA support for crypto register I/O + - FROMLIST: crypto: qce - Add support for BAM locking + - FROMLIST: crypto: qce - Switch to using BAM DMA for crypto I/O + - FROMLIST: iommu/arm-smmu-qcom: Restore ACTLR settings for MDSS on + sa8775p + - arm64: dts: qcom: agatti: enable FastRPC on the ADSP + - FROMLIST: crypto: qce - Add runtime PM and interconnect bandwidth + scaling support + - FROMLIST: ufs: ufs-qcom: Fix sequential read variance + - FROMLIST: bus: mhi: host: pci_generic: Add Qualcomm SDX35 modem + - FROMLIST: dt-bindings: soc: qcom: qcom,pmic-glink: Add Glymur and + Kaanapali compatibles + - FROMLIST: soc: qcom: pmic_glink: Add charger PDR service information to + client data + - FROMLIST: soc: qcom: pmic_glink: Add support for Glymur and Kaanapali + - FROMLIST: usb: typec: ucsi: ucsi_glink: Add support for Glymur and + Kaanapali + - FROMLIST: power: supply: qcom_battmgr: Add support for Glymur and + Kaanapali + - FROMLIST: dt-bindings: iio: adc: Split out QCOM VADC channel properties + - FROMLIST: dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC + - FROMLIST: iio: adc: Add support for QCOM PMIC5 Gen3 ADC + - FROMLIST: thermal: qcom: add support for PMIC5 Gen3 ADC thermal + monitoring + - FROMLIST: media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video + codec binding + - FROMLIST: media: iris: Add platform data for kaanapali + - FROMLIST: media: iris: Enable Secure PAS support with IOMMU managed by + Linux + - FROMLIST: dt-bindings: i2c: qcom-cci: Document sm6150 compatible + - FROMLIST: media: i2c: imx412: Assert reset GPIO during probe + - FROMLIST: media: i2c: imx412: Extend the power-on waiting time + - FROMLIST: arm64: dts: qcom: qcs615-ride: Add PSCI SYSTEM_RESET2 types + - FROMLIST: arm64: dts: qcom: talos: add the GPU SMMU node + - FROMLIST: arm64: dts: qcom: talos: Add gpu and rgmu nodes + - FROMLIST: arm64: dts: qcom: talos: Add GPU cooling + - FROMLIST: arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU + - FROMLIST: arm64: dts: qcom: Enable cdsp qmi tmd devices for talos + - FROMLIST: arm64: dts: qcom: talos: Add psci reboot-modes + - FROMLIST: dt-bindings: arm: qcom: talos-evk: Add QCS615 Talos EVK SMARC + platform + - FROMLOST: arm64: dts: qcom: talos/qcs615-ride: Fix inconsistent USB PHY + node naming + - FROMLIST: arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk + board + - FROMLIST: arm64: dts: qcom: talos: add ETR device + - FROMLIST: arm64: dts: qcom: talos: Add camss node + - FROMLIST: arm64: dts: qcom: talos: Add CCI definitions + - FROMLIST: arm64: dts: qcom: talos: Add camera MCLK pinctrl + - FROMLIST: dt-bindings: i2c: qcom-cci: Document sm6150 compatible + - FROMLIST: arm64: dts: qcom: talos-evk-camera: Add DT overlay + - FROMLIST: coresight: core: Refactoring ctcu_get_active_port and make it + generic + - FROMLIST: coresight: tmc: add create/clean functions for etr_buf_list + - FROMLIST: coresight: tmc: Introduce tmc_sysfs_ops to wrap sysfs read + operations + - FROMLIST: coresight: etr: add a new function to retrieve the CTCU device + - FROMLIST: dt-bindings: arm: add an interrupt property for Coresight CTCU + - FROMLIST: coresight: ctcu: enable byte-cntr for TMC ETR devices + - FROMLIST: coresight: tmc: integrate byte-cntr's sysfs_ops with tmc sysfs + file_ops + - FROMLIST: coresight: ctcu: fix the spin_bug + - FROMLIST: dt-bindings: arm: Add support for Qualcomm TGU trace + - FROMLIST: qcom-tgu: Add TGU driver + - FROMLIST: qcom-tgu: Add signal priority support + - FROMLIST: qcom-tgu: Add TGU decode support + - FROMLIST: qcom-tgu: Add support to configure next action + - FROMLIST: qcom-tgu: Add timer/counter functionality for TGU + - FROMLIST: qcom-tgu: Add reset node to initialize + - FROMLIST: coresight: cti: Convert trigger usage fields to dynamic + bitmaps and arrays + - FROMLIST: coresight: cti: Add Qualcomm extended CTI support + - FROMLIST: stm: class: Add MIPI OST protocol support + - FROMLIST: dt-bindings: arm: coresight: Add 'qcom,cpu-bound-components' + property + - FROMLIST: coresight-funnel: Support CPU cluster funnel initialization + - FROMLIST: coresight-funnel: Defer probe when associated CPUs are offline + - FROMLIST: coresight-replicator: Support CPU cluster replicator + initialization + - FROMLIST: coresight-replicator: Defer probe when associated CPUs are + offline + - FROMLIST: coresight-replicator: Update management interface for CPU- + bound devices + - FROMLIST: coresight-tmc: Support probe and initialization for CPU + cluster TMCs + - FROMLIST: coresight-tmc-etf: Refactor enable function for CPU cluster + ETF support + - FROMLIST: coresight-tmc: Update management interface for CPU-bound TMCs + - FROMLIST: coresight-tmc: Defer probe when associated CPUs are offline + - FROMLIST: coresight: Pass trace mode to link enable callback + - FROMLIST: dt-binding: document QCOM platforms for CTCU device + - FROMLIST: phy: qcom: sgmii-eth: add second regulator support + - FROMLIST: net: phy: qcom: qca808x: Add .get_rate_matching support + - FROMLIST: dt-bindings: remoteproc: qcom,sm8550-pas: Add Kaanapali ADSP + - FROMLIST: dt-bindings: remoteproc: qcom,sm8550-pas: Add Kaanapali CDSP + - FROMLIST: arm64: dts: qcom: kaanapali: add coresight nodes + - FROMLIST: arm64: dts: qcom: kaanapali: Add QUPv3 configuration for + serial engines + - FROMLIST: arm64: dts: qcom: kaanapali: Add TSENS and thermal zones + - FROMLIST: arm64: dts: qcom: kaanapali: Add ADSP and CDSP for Kaanapali + SoC + - FROMLIST: arm64: dts: qcom: kaanapali: Add support for audio + - FROMLIST: arm64: dts: qcom: kaanapali-mtp: Enable ADSP and CDSP + - FROMLIST: arm64: dts: qcom: kaanapali-qrd: Enable ADSP and CDSP + - FROMLIST: arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, + WCD9395, DMIC) + - FROMLIST: arm64: dts: qcom: kaanapali: Add support for MM clock + controllers for Kaanapali + - FROMLIST: arm64: dts: qcom: kaanapali: Add iris video node + - FROMLIST: arm64: dts: qcom: kaanpali: Add power-domain and iface clk for + ice node + - FROMLIST: misc: fastrpc: Move fdlist to invoke context structure + - FROMLIST: misc: fastrpc: Replace hardcoded ctxid mask with GENMASK + - FROMLIST: misc: fastrpc: Expand context ID mask for DSP polling mode + support + - FROMLIST: misc: fastrpc: Add polling mode support for fastRPC driver + - FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Kaanapali + compatible + - FROMLIST: PCI: dwc: Use common D3cold eligibility helper in suspend path + - FROMLIST: PCI: host-common: Add shared D3cold eligibility helper for + host bridges + - FROMLIST: PCI: qcom: Add D3cold support + - FROMLIST: PCI: qcom: Prevent GDSC power down on suspend + - QCLINUX: defconfig: Introduce prune.config fragment + - QCLINUX: defconfig: Define qcom.config and enable DMABUF heaps + - QCLINUX: arch: arm64: configs: Enable coresight components in + qcom.config + - QCLINUX: defconfig: enable zram defconfig on qcom.config + - QCLINUX: defconfig: Enable scheduler and thermal related configs + - QCLINUX: debug: Enable additional Qualcomm-specific debug configs + - QCLINUX: arch: arm64: configs: Enable stm components in qcom.config + - QCLINUX: defconfig: enable Crypto and ICE related configs + - QCLINUX: defconfig: enable amc6821 defconfig on qcom.config + - QCLINUX: defconfig: Enable QCA808X ethernet phy config + - QCLINUX: defconfig: Enable EDAC_QCOM on qcom.config + - QCLINUX: debug: Enable WLAN related debug configs + - QCLINUX: defconfig: Enable ATH reg setting + - QCLINUX: defconfig: Enable BT_RFCOMM, BT_BNEP and UHID + - QCLINUX: defconfig: Enable various power management configs + - QCLINUX: debug: Enable power management debug configs + - FROMLIST: defconfig: qcom: Enable lt8713sx bridge driver + - QCLINUX: Revert "QCLINUX: defconfig: enable Crypto and ICE related + configs" + - QCLINUX: defconfig: Enable watchdog drivers for VM usecases + - QCLINUX: debug.config: Drop heavy debug configs + - QCLINUX: defconfig: Enable Trusted Execution Environment (TEE) driver + for Qualcomm TEE (QTEE) + - QCLINUX: defconfig: Enable support for vhost-net, vsock + - FROMLIST: arm64: defconfig: Enable Sound DMIC driver + - QCLINUX: arm64: configs: qcom.config: Enable GUNYAH_WATCHDOG + - FROMLIST: arm64: defconfig: Enable Glymur configs for boot to shell + - QCLINUX: arm64: configs: qcom.config: Enable UINPUT + - QCLINUX: defconfig: enable EMC2305 defconfig on qcom.config + - QCLINUX: arm64: configs: Added new rt.config for RT kernel + - QCLINUX: arm64: configs: qcom.config: Enable I2C_QCOM_GENI as built-in + - QCLINUX: arm64: configs: Added Kubernetes support in qcom.config + - QCLINUX: qcom.comfig: disable ICE/UFS crypto + - QCLINUX: defconfig: enable Remoteproc cooling feature + - QCLINUX: arm64: configs: qcom.config: Enable CONNECTOR, PROC_EVENTS + - QCLINUX: qcom.config: add crypto corresponding config + - FROMLIST: arm64: defconfig: Enable camcc, videocc clock controllers on + SM8750 + - QCLINUX: prune.config: Enable backlight config for Hamoa/Purwa + - QCLINUX: qcom.config: Enable 39-bit VA space for 4K-page builds + - QCLINUX: qcom.config: enable the ICE related config + - FROMLIST: arm64: configs: Update defconfig for DSI-LVDS bridge support + - FROMLIST: arm64: defconfig: Enable Kaanapali clock controllers + - QCLINUX: qcom.config: Enable FTRACE option for performance profiling + - FROMLIST: arm64: defconfig: Enable VIDEOCC and CAMCC drivers on Qualcomm + X1P42100 + - Revert "QCLINUX: qcom.config: Enable 39-bit VA space for 4K-page builds" + - QCLINUX: qcom.config: Enable CPUidle Teo and Menu governors + - FROMLIST: arm64: defconfig: Enable SM8750 clock controllers + - FROMLIST: arm64: defconfig: Enable Glymur clock controllers + - FROMLIST: drm/msm/adreno: Add GPU to MODULE_DEVICE_TABLE + - QCLINUX: arm64: dts: qcom: Add camera DT binding + - QCLINUX: arm64: dts: qcom: Add lemans camx overlay dts + - QCLINUX: arm64: dts: qcom: Add rb3gen2 camx overlay dts + - QCLINUX: arm64: dts: qcom: Add monaco camx overlay dts + - PENDING: arm64: dts: qcom: qcs8300: Update camera PIL region to 7MB + - QCLINUX: arm64: dts: qcom: Update rbgen2 camx overlay dts + - QCLINUX: arm64: dts: qcom: Update Monaco camx overlay dts + - QCLINUX: arm64: dts: qcom: Update Lemans camx overlay dts + - PENDING: arm64: dts: qcom: change pil camera memory map + - QCLINUX: arm64: dts: qcom: Add Talos camx overlay dts + - QCLINUX: arm64: dts: qcom: Change rb3gen2 camera firmware path + - QCLINUX: arm64: dts: qcom: Change monaco camera firmware path + - QCLINUX: arm64: dts: qcom: Change lemans camera firmware path + - QCLINUX: arm64: dts: qcom: Change talos camera firmware path + - QCLINUX: arm64: dts: qcom: talos: add camnoc bandwidth levels + - QCLINUX: arm64: dts: qcom: disabled vreg_cam1_2p8 regulator + - QCLINUX: arm64: dts: qcom: Enable IMX577 sensor on lemans + - QCLINUX: arm64: dts: qcom: Add camx overlay for talos evk + - QCLINUX: arm64: dts: qcom: add node labels and explicit QoS flag in + lemans + - QCLINUX: arm64: dts: qcom: add node labels and explicit QoS flag in + monaco + - QCLINUX: arm64: dts: qcom: lemans: Add CamX EL2 overlay + - QCLINUX: firmware: qcom_scm: Add new scm to update Camera QoS + - FROMLIST: dt-bindings: arm: Document reboot mode magic + - FROMLIST: arm64: dts: qcom: qcm6490-idp: Add PSCI SYSTEM_RESET2 types + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Add PSCI SYSTEM_RESET2 + types + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Adjust tsens thermal zone + configuration + - FROMLIST: arm64: dts: qcom: Enable cdsp qmi tmd devices for kodiak + - FROMLIST: arm64: dts: qcom: Enable lvds panel-DV215FHM-R01 for rb3gen2 + industrial mezzanine + - FROMLIST: arm64: dts: qcom: qcm6490-idp: add and enable BT node + - FROMLIST: arm64: dts: qcom: qcm6490-idp: Enable PCIe1 + - FROMLIST: arm64: dts: qcom: kodiak: Fix PCIe1 PHY ref clock voting + - FROMLIST: arm64: dts: qcom: lemans: Add PSCI SYSTEM_RESET2 types + - FROMLIST: arm64: dts: qcom: lemans: Add eDP ref clock for eDP PHYs + - FROMLIST: arm64: dts: qcom: lemans-evk: Enable Bluetooth support + - FROMLIST: dt-bindings: phy: describe additional regulator for Qualcomm + SGMII PHY + - FROMLIST: arm64: dts: qcom: lemans-evk: add additional SerDes PHY + regulator + - FROMLIST: arm64: dts: qcom: lemans-ride-common: add additional SerDes + PHY regulators + - FROMLIST: arm64: dts: qcom: Enable cdsp qmi tmd devices for lemans + - FROMLIST: arm64: dts: qcom: lemans-evk: Rename hd3ss3220_ instance for + primary port controller + - FROMLIST: arm64: dts: qcom: lemans-evk: Enable secondary USB controller + in host mode + - WORKAROUND: arm64: dts: qcom: lemans-evk: Remove WCN6855 PMU node to + bypass pwrseq flow + - FROMLIST: arm64: dts: qcom: lemans: disable zap-shader for EL2 + configuration + - FROMLIST: arm64: dts: qcom: monaco: Add PSCI SYSTEM_RESET2 types + - FROMLIST: arm64: dts: qcom: qcs8300: Add CCI definitions + - FROMLIST: arm64: dts: qcom: monaco-evk-camera: Add DT overlay + - FROMLIST: arm64: dts: qcom: qcs8300-ride: enable WLAN on qcs8300-ride + - FROMLIST: arm64: dts: qcom: monaco-evk: Enable Bluetooth support + - FROMLIST: arm64: dts: qcom: qcs8300-ride: Enable Bluetooth support + - FROMLIST: arm64: dts: qcom: qcs8300: add Display Serial Interface device + nodes + - FROMLIST: arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge + node + - FROMLIST: arm64: dts: qcom: monaco: add lt8713sx bridge with displayport + - FROMLIST: arm64: dts: qcom: monaco-evk: fix the SerDes PHY regulators + - FROMLIST: arm64: dts: qcom: qcs8300-ride: add additional SerDes PHY + regulator + - QCLINUX: arch: arm64: qcom: qcs8300-ride: Enable PCIe Qref regulator + - FROMLIST: arm64: dts: qcom: Enable cdsp qmi tmd devices for monaco + - WORKAROUND: arm64: dts: qcom: monaco-evk: Remove WCN6855 PMU node to + bypass pwrseq flow + - FROMLIST: arm64: dts: qcom: monaco: Add EL2 overlay + - WORKAROUND: arm64: dts: qcom: monaco: Disable global IRQ for pcie1 + - QCLINUX: drivers: increase deferred probe timeout + - QCLINUX: PCI: Disable L1ss through quirk for Qualcomm SA8775P + - WORKAROUND: arm64: dts: qcom: lemans: Disable global IRQ for pcie1 + - WORKAROUND: scsi: ufs: core: Set uic_cmd_timeout to max + - FROMLIST: misc: fastrpc: Add reference counting for fastrpc_user + structure + - soc: qcom: smp2p: Add irqchip state support + - soc: qcom: smp2p: Add support for smp2p v2 + - soc: qcom: smem: Expose DDR data from SMEM + - FROMLIST: net: qrtr: Expand control port access to root + - FROMLIST: soc: qcom: icc-bwmon: Update zone1_thres_count to 3 + - FROMLIST: firmware: qcom: scm: Register gunyah watchdog device + - FROMLIST: watchdog: Add driver for Gunyah Watchdog + - FROMLIST: soc: qcom: pd-mapper: Fix element length in + servreg_loc_pfr_req_ei + - FROMLIST: soc: qcom: qmi: Print error codes in failure paths + - FROMLIST: dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema + - FROMLIST: phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver + - FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Add optional PHY + handle definitions + - FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Add support for + combo-mode endpoints + - FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Add iommus minItems: + 5 + - FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Allow CSIPHY supplies + to be optional + - FROMLIST: media: qcom: camss: Add legacy_phy flag to SoC definition + structures + - FROMLIST: media: qcom: camss: Add support for PHY API devices + - FROMLIST: media: qcom: camss: Drop legacy PHY descriptions from x1e + - mmc: host: sdhci-msm: Add support for wrapped keys + - FROMLIST: dt-bindings: crypto: qcom,ice: Require power-domain and iface + clk + - FROMLIST: arm64: dts: qcom: lemans: Add power-domain and iface clk for + ice node + - FROMLIST: arm64: dts: qcom: monaco: Add power-domain and iface clk for + ice node + - FROMLIST: arm64: dts: qcom: sc7180: Add power-domain and iface clk for + ice node + - FROMLIST: arm64: dts: qcom: kodiak: Add power-domain and iface clk for + ice node + - FROMLIST: arm64: dts: qcom: sm8450: Add power-domain and iface clk for + ice node + - FROMLIST: arm64: dts: qcom: sm8550: Add power-domain and iface clk for + ice node + - FROMLIST: arm64: dts: qcom: sm8650: Add power-domain and iface clk for + ice node + - FROMLIST: arm64: dts: qcom: sm8750: Add power-domain and iface clk for + ice node + - FROMLIST: soc: qcom: ice: Add explicit power-domain and clock voting + calls for ICE + - mmc: Avoid reprogram all keys to Inline Crypto Engine for MMC runtime + suspend resume + - FROMLIST: arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC + - FROMLIST: arm64: dts: qcom: sm8750-mtp: Enable display + - FROMLIST: arm64: dts: qcom: sm8750: enable ETR and CTCU devices + - FROMLIST: arm64: dts: qcom: sm8750: Add camera clock controller + - FROMLIST: arm64: dts: qcom: qcm6490-idp: Fix WCD9370 reset GPIO polarity + - dt-bindings: arm: qcom,ids: Add SoC ID for Shikra IoT variants + - soc: qcom: socinfo: Add SoC ID for Shikra IoT variants + - dt-bindings: arm-smmu: Add compatible for Shikra SoC + - dt-bindings: firmware: qcom,scm: Document SCM on Shikra SoC + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: use DP controller native + HPD + - dt-bindings: arm: qcom: Document Shikra and its evk boards + - QCLINUX: qcom-dcc: Add driver support for Data Capture and Compare + unit(DCC) + - QCLINUX: add qcom_debug.config for debug features + - QCLINUX: qcom-dcc: add qcom-dcc dev driver + - QCLINUX: memory-dump: add QCOM memory dump driver + - QCLINUX: mem-dump: add memory dump device driver + - QCLINUX: memory-dump: add logic for reserving CMA memory + - QCLINUX: qcom-dcc: add device configuration for Pakala + - QCLINUX: memory-dump: add memory dump table for Pakala + - QCLINUX: qcom-dcc: add device configuration for Kaanapali + - QCLINUX: memory-dump: add memory dump table for Kaanapali + - QCLINUX: qcom-dcc: add device configuration for Hamoa + - QCLINUX: memory-dump: add memory dump table for Hamoa + - QCLINUX: memory-dump: fix array size issue for Talos + - dt-bindings: sram: qcom,imem: Add the Shikra compatible + - FROMLIST: driver: bluetooth:btusb: Allow firmwarea re-download when + version matches + - FROMLIST: driver: bluetooth: hci_qca: Cleanup on all setup failures + - WORKAROUND: Revert "PCI: dwc: Remove MSI/MSIX capability for Root Port + if iMSI-RX is used as MSI controller" + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add + TC9563 PCIe switch node for PCIe0 + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add + second TC9563 PCIe switch node for PCIe1 + - FROMLIST: PCI: qcom: Add .get_ltssm() helper + - FROMLIST: remoteproc: qcom: Fix NULL pointer issue + - FROMLIST: remoteproc: qcom: probe all child devices + - FROMLIST: arm64: dts: qcom: lemans-evk: Add IFP Mezzanine + - PENDING: arm64: dts: qcom: Add EL2 support for Iris for lemans + - FROMLIST: arm64: dts: qcom: lemans-evk: Enable GPIO expander interrupt + for Lemans EVK + - FROMLIST: arm64: dts: qcom: lemans: Add role-switch support and HS + endpoint for tertiary USB controller + - FROMLIST: arm64: dts: qcom: lemans-evk: Enable the tertiary USB + controller + - FROMLIST: arm64: dts: qcom: lemans-evk: Enable wakeup for primary USB + controller + - FROMLIST: arm64: dts: qcom: lemans: add mdss1 display device nodes + - FROMLIST: arm64: dts: qcom: lemans-ride: Enable mdss1 display Port + - FROMLIST: arm64: dts: qcom: monaco-evk: Add IFP Mezzanine + - FROMLIST: arm64: dts: qcom: monaco-evk: Enable GPIO expander interrupt + for Monaco EVK + - FROMLIST: arm64: dts: qcom: monaco-evk: Enable the tertiary USB + controller + - BACKPORT: arm64: dts: qcom: monaco-evk: Enable primary USB controller in + host mode + - WORKAROUND: soc: qcom: smem_dramc: Fix v3 DDR freq table out-of-bounds + - FROMLIST: dt-bindings: can: microchip,mcp251xfd: allow gpio-hog child + nodes + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller + - FROMLIST: drm/msm/a6xx: Fix the bogus protect error on X2-85 + - dt-bindings: interconnect: document the RPMh Network-On-Chip + interconnect in Mahua SoC + - interconnect: qcom: glymur: Add Mahua SoC support + - FROMLIST: dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks + property to enable QoS + - FROMLIST: interconnect: qcom: qcs8300: enable QoS configuration + - FROMLIST: arm64: dts: qcom: qcs8300: Add clocks for QoS configuration + - power: reset: reboot-mode: Remove devres based allocations + - power: reset: reboot-mode: Add firmware node based registration + - power: reset: reboot-mode: Add support for 64 bit magic + - Documentation: ABI: Add sysfs-class-reboot-mode-reboot_modes + - power: reset: reboot-mode: Expose sysfs for registered reboot_modes + - firmware: psci: Implement vendor-specific resets as reboot-mode + - FROMLIST: dt-bindings: arm: qcom: Document Glymur SoC and board + - FROMLIST: arm64: dts: qcom: Introduce Glymur base dtsi + - FROMLIST: arm64: dts: qcom: glymur: Enable Glymur CRD board support + - FROMLIST: arm64: dts: qcom: glymur: Add USB related nodes + - FROMLIST: arm64: dts: qcom: glymur-crd: Enable USB support + - FROMLIST: arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC + - FROMLIST: arm64: dts: qcom: glymur-crd: Enable ADSP and CDSP + - PENDING: arm64: dts: qcom: glymur: Describe display related nodes + - PENDING: arm64: dts: qcom: glymur-crd: Enable eDP display support + - PENDING: arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and + touchscreen + - FROMLIST: arm64: dts: qcom: Add support for MM clock controllers for + Glymur + - PENDING: arm64: dts: qcom: Add Glymur GPU support + - PENDING: arm64: dts: qcom: glymur: Add GPU smmu nodes + - PENDING: arm64: dts: glymur: Add LPASS macro codecs and pinctrl + - PENDING: arm64: dts: qcom: glymur-crd: add Audio sound card node + - WORKAROUND: arm64: dts: qcom: glymur: Add refgen and qref supplies for + PCIe PHY on Glymur + - FROMLIST: arm64: dts: qcom: glymur: Add remoteproc for SoCCP + - FROMLIST: arm64: dts: qcom: glymur: Add glymur BWMONs + - PENDING: arm64: dts: qcom: glymur: Upgrade dispcc opp entry to turbo + - FROMLIST: arch: arm64: dts: qcom: Add support for PCIe3a + - FROMLIST: arm64: defconfig: Enable Qualcomm WCD937x headphone codec as + module + - QCLINUX: qcom.config: enable CONFIG_CMA for qcom chipsets + - QCLINUX: arm64: dts: qcom: add labels to sensor DTSI + - FROMLIST: arm64: dts: qcom: qcs8300: Add clocks for QoS configuration + - FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for + glymur Gen5 x8 bifurcation mode + - FROMLIST: phy: qcom: qmp-pcie: Add multiple power-domains support + - FROMLIST: phy: qcom: qmp-pcie: Support multiple nocsr resets + - FROMLIST: phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur + - FROMLIST: dt-bindings: mmc: sdhci-msm: Add ICE phandle + - FROMLIST: arm64: dts: qcom: kodiak: enable the inline crypto engine for + SDHC + - FROMLIST: arm64: dts: qcom: monaco: enable the inline crypto engine for + SDHC + - FROMLIST: media: dt-bindings: Add CAMSS device for Kaanapali + - FROMLIST: media: qcom: camss: Add Kaanapali compatible camss driver + - FROMLIST: media: qcom: camss: csiphy: Add support for v2.4.0 two-phase + CSIPHY + - FROMLIST: media: qcom: camss: csid: Add support for CSID gen4 + - FROMLIST: media: qcom: camss: vfe: Add support for VFE gen4 + - FROMLIST: phy: qcom: qmp-pcie: Add multiple power-domains support + - FROMLIST: phy: qcom: qmp-pcie: Support multiple nocsr resets + - FROMLIST: phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur + - WORKAROUND: phy: qcom: qmp-pcie: Add vdda-refgen and vdda-qref supplies + for Glymur + - WORKAROUND: remoteproc: qcom: Fix RB8 device hung issue + - FROMLIST: arm64: dts: qcom: glymur-crd: Add Embedded controller node + - dt-bindings: pinctrl: Document the Shikra Top Level Mode Multiplexer + - pinctrl: qcom: Add Shikra pinctrl driver + - FROMLIST: media: qcom: camss: Fix csid IRQ offset for sa8775p + - FROMLIST: media: qcom: camss: Fix csid clock configuration for sa8775p + - FROMLIST: media: qcom: camss: Add missing clocks for VFE lite on sa8775p + - arm64: dts: qcom: Introduce Shikra Soc base dtsi + - arm64: dts: qcom: Add Shikra IoT SoM platforms + - arm64: dts: qcom: Add Shikra EVK boards + - FROMLIST: wifi: ath12k: fix incorrect channel survey index + - FROMLIST: wifi: ath12k: prepare REO update element only for primary link + - QCLINUX: arm64: dts: qcom: lemans: Fix comment typo in camx EL2 dtso. + - QCLINUX: arm64: dts: qcom: monaco: Add CamX EL2 overlay + - FROMLIST: coresight: platform: check the availability of the endpoint + before parse + - FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Glymur + compatible + - FROMLIST: dt-bindings: phy: qcom-m31-eusb2: Add Glymur compatible + - usb: misc: onboard_usb_hub: Add Genesys Logic GL3590 hub support + - dt-bindings: usb: Add binding for Genesys Logic GL3590 hub + - FROMLIST: dt-bindings: soc: qcom: eud: Restructure to model multi-path + hardware + - FROMLIST: usb: misc: qcom_eud: add sysfs attribute for port selection + - FROMLIST: usb: misc: qcom_eud: add per-path High-Speed PHY control + - FROMLIST: usb: misc: qcom_eud: add per-path role switch support + - FROMLIST: usb: misc: qcom_eud: improve enable_store API + - FROMLIST: usb: misc: qcom_eud: add host mode coordination + - FROMLIST: usb: misc: qcom_eud: fix virtual attach/detach event handling + - FROMLIST: arm64: dts: qcom: kodiak: Align EUD node with binding + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable EUD debug + functionality + - FROMLIST: usb: typec: hd3ss3220: Enable VBUS based on role state + - FROMLIST: usb: typec: hd3ss3220: Add wakeup support from system suspend + - Revert "FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable EUD debug + functionality" + - Revert "FROMLIST: arm64: dts: qcom: kodiak: Align EUD node with binding" + - FROMLIST: arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug + block + - FROMLIST: arm64: dts: qcom: hamoa: enable ETR and CTCU devices + - FROMLIST: dt-bindings: arm: qcom: Document PURWA-IOT-EVK board + - FROMLIST: firmware: qcom: scm: Allow QSEECOM on PURWA-IOT-EVK + - FROMLIST: arm64: dts: qcom: Add PURWA-IOT-SOM platform + - FROMLIST: arm64: dts: qcom: Add base PURWA-IOT-EVK board + - FROMLIST: arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC + - FROMLIST: arm64: dts: qcom: hamoa-iot-evk: Enable UFS + - FROMLIST: arm64: dts: qcom: hamoa-iot-evk: Add SDC2 node for hamoa iot + evk board + - FROMLIST: arm64: dts: qcom: hamoa-evk: Add DP0/DP1 audio DAI links + - FROMLIST: arm64: dts: qcom: x1e80100: Add CAMCC block definition + - FROMLIST: arm64: dts: qcom: Update compatible for videocc and camcc + nodes on purwa + - FROMLIST: arm64: dts: qcom: x1e80100: Add '#cooling-cells' for CPU nodes + - FROMLIST: arm64: dts: qcom: hamoa: Add PSCI SYSTEM_RESET2 types + - FROMLIST: arm64: dts: qcom: hamoa: Add EL2 overlay for hamoa-evk + - FROMLIST: arm64: dts: qcom: hamoa: Add remoteproc IOMMUS in EL2 device + trees + - FROMLIST: arm64: dts: qcom: x1e80100: Add MIPI CSI PHY nodes + - FROMLIST: arm64: dts: qcom: x1e80100: Add CAMSS block definition + - FROMLIST: arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m + regulators + - FROMLIST: arm64: dts: qcom: x1e80100-crd: Add ov08x40 RGB sensor on + CSIPHY4 + - FROMLIST: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add pm8010 + camera PMIC with voltage levels for IR and RGB camera + - FROMLIST: arm64: dts: qcom: hamoa-iot-som: Add pm8010 L4M regulator + - FROMLIST: arm64: dts: qcom: hamoa-iot-evk-camera-imx577: Add DT overlay + - FROMLIST: arm64: dts: qcom: hamoa-iot-evk: Update TSENS thermal zone + configuration + - FROMLIST: arm64: dts: qcom: glymur: add coresight nodes + - QCLINUX: qcom-dcc: add device configuration for Glymur + - QCLINUX: memory-dump: add support for Glymur + - FROMLIST: dt-bindings: phy: qcom-edp: Add reference clock for sa8775p + eDP PHY + - FROMLIST: drm/bridge: lt9611uxc: Increase EDID wait time from 500ms to + 1000ms + - FROMLIST: drm/bridge: lt9611uxc: extend mode valid checks + - FROMLIST: drm/bridge: lt9611uxc: add support for 4K@30 resolution + - FROMLIST: dt-bindings: bridge: lt8713sx: Add bindings + - FROMLIST: drm/bridge: add support for lontium lt8713sx bridge driver + - FROMLIST: dt-bindings: bridge: lt9211: Add bindings + - FROMLIST: drm/bridge: add support for lontium lt9211c bridge + - FROMLIST: drm/bridge: lt9611uxc: reset edid_read on disconnect + - FROMLIST: clk: qcom: clk-alpha-pll: Add support for controlling Rivian + PLL + - FROMLIST: dt-bindings: clock: qcom: Add video clock controller on Glymur + SoC + - FROMLIST: clk: qcom: videocc-glymur: Add video clock controller driver + for Glymur + - FROMLIST: dt-bindings: clock: qcom: document the Glymur GPU Clock + Controller + - FROMLIST: clk: qcom: Add support for GPUCC and GXCLK for Glymur + - FROMLIST: dt-bindings: clock: qcom: Add X1P42100 video clock controller + - FROMLIST: dt-bindings: clock: qcom: Add X1P42100 camera clock controller + - FROMLIST: clk: qcom: videocc-x1p42100: Add support for video clock + controller + - FROMLIST: clk: qcom: camcc-x1e80100: Add support for camera QDSS debug + clocks + - FROMLIST: clk: qcom: camcc-x1p42100: Add support for camera clock + controller + - FROMLIST: dt-bindings: clock: qcom: Add SM8750 GPU clocks + - FROMLIST: clk: qcom: Add a driver for SM8750 GPU clocks + - dt-bindings: power: qcom,rpmpd: document the Shikra RPM Power Domains + - soc: qcom: rpmpd: Add Shikra RPM support + - dt-bindings: regulator: qcom,smd-rpm-regulator: Document PM8150 IC + - regulator: qcom_smd: Add PM8150 regulators + - FROMLIST: ASoC: qcom: q6dsp-lpass-ports: Extend q6dsp-lpass-ports driver + to support additional sampling rates + - FROMLIST: ASoC: qcom: q6dsp-lpass-ports: Update constraints to support + 32-bit PCM format + - FROMLIST: soc: qcom: pd-mapper: Add support for SA8775P + - FROMLIST: soc: qcom: pd-mapper: Add support for QCS8300 + - FROMLIST: arm64: qcom: pd-mapper: Add QCS615 power domain mappings + - FROMLIST: ASoC: qcom: qdsp6: Fix q6apm remove ordering during ADSP stop + and start + - FROMLIST: ASoC: qcom: q6apm: move component registration to unmanaged + version + - FROMLIST: ASoC: qcom: q6apm: remove child devices when apm is removed + - FROMLIST: ASoC: qcom: qdsp6: topology: check widget type before + accessing data + - QCLINUX: defconfig: Enable Qualcomm BCL driver + - QCLINUX: qcom.config: Enable testmode config + - FROMLIST: iommu/arm-smmu: Use pm_runtime in fault handlers + - FROMLIST: soc: qcom: pd-mapper: Add support for Glymur + - soc: qcom: rpmpd: Add Shikra RPM compatiable + - QCLINUX: qcom.config: update TGU config + - QCLINUX: qcom.config: fix the TNOC config + - FROMLIST: arm64: dts: qcom: glymur-crd: USB mode change to Host + - Revert "FROMLIST: usb: misc: qcom_eud: fix virtual attach/detach event + handling" + - Revert "FROMLIST: usb: misc: qcom_eud: add host mode coordination" + - Revert "FROMLIST: usb: misc: qcom_eud: improve enable_store API" + - Revert "FROMLIST: usb: misc: qcom_eud: add per-path role switch support" + - Revert "FROMLIST: usb: misc: qcom_eud: add per-path High-Speed PHY + control" + - Revert "FROMLIST: usb: misc: qcom_eud: add sysfs attribute for port + selection" + - Revert "FROMLIST: dt-bindings: soc: qcom: eud: Restructure to model + multi-path hardware" + - FROMLIST: dt-bindings: connector: Add role‑switch provider phandle + - FROMLIST: dt-bindings: soc: qcom: eud: Add support for dual-port + configuration + - FROMLIST: usb: misc: qcom_eud: add sysfs attribute for port selection + - FROMLIST: usb: misc: qcom_eud: add per-port High-Speed PHY control + - FROMLIST: usb: misc: qcom_eud: add per-port role switch support + - FROMLIST: usb: misc: qcom_eud: improve enable_store API + - FROMLIST: usb: misc: qcom_eud: fix virtual attach/detach event handling + - FROMLIST: usb: misc: qcom_eud: add host mode coordination + - FROMLIST: usb: dwc3: qcom: notify EUD driver of role changes + - FROMLIST: arm64: dts: qcom: kodiak: Fix EUD USB controller connection + - FROMLIST: arm64: dts: qcom: Map USB connector to EUD for kodiak boards + - FROMLIST: arm64: dts: qcom: purwa-iot-evk: Enable UFS + - FROMLIST: arm64: dts: qcom: purwa-iot-evk: Add SDC2 node for purwa iot + evk board + - arm64: dts: qcom: Shikra: Add reserved memory nodes + - FROMLIST: arm64: dts: qcom: sm8750-mtp: Set sufficient voltage for panel + nt37801 + - dt-bindings: arm-smmu: Add adreno-smmu compatible for Shikra SoC + - mailbox: qcom-apcs-ipc-mailbox: Add compatible string + - arm64: dts: qcom: Shikra: add smmu nodes + - dt-bindings: mailbox: qcom,apcs-kpss-global: Add Shikra compatible + - arm64: dts: qcom: Add RPM GLINK transport nodes + - FROMLIST: driver: bluetooth: hci_qca: disable power control for WCN7850 + when bt_en is not defined + - FROMLIST: drm/bridge: display-connector: don't autoenable HPD IRQ + - FROMLIST: drm/bridge: display-connector: trigger initial HPD event for + DP + - FROMLIST: arm64: dts: qcom: kaanapali: Add PMIC devices + - FROMLIST: arm64: dts: qcom: kaanapali-mtp: Add PMIC support + - FROMLIST: arm64: dts: qcom: kaanapali-qrd: Add PMIC support + - FROMLIST: arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi + - FROMLIST: arm64: dts: qcom: kaanapali: add display hardware devices + - FROMLIST: arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices + - FROMLIST: drm/msm/dpu: fix mismatch between power and frequency + - BACKPORT: Revert "drm/msm/dpu: try reserving the DSPP-less LM first" + - arm64: dts: qcom: Shikra: Add qfprom node + - dt-bindings: nvmem: qfprom: Add Shikra compatible + - dt-bindings: remoteproc: qcom: Add Shikra RPM processor compatible + - dt-bindings: mailbox: qcom: Add the Shikra APCS compatible + - dt-bindings: soc: qcom: qcom,smd-rpm: Add compatible for Shikra + - arm64: dts: qcom: Add RPM SMD, LPM stats and MPM devices for shikra + - dt-bindings: drm/bridge: anx7625: describe Type-C connector + - drm: bridge: anx7625: implement minimal Type-C support + - drm: bridge: anx7625: implement message sending + - drm: bridge: anx7625: correctly detect if PD can be disabled + - dt-bindings: display: msm: qcm2290-mdss: Fix iommus property + - dt-bindings: media: venus: Fix iommus property + - arm64: dts: qcom: agatti: Fix IOMMU DT properties + - dt-bindings: mfd: qcom,spmi-pmic: add compatibles for pm4124-codec + - arm64: dts: qcom: agatti: add LPASS devices + - arm64: dts: arduino-imola: add support for sound + - arm64: defconfig: Enable Agatti audio drivers + - arm64: dts: qcom: qrb2210-arduino-imola: describe DSI / DP bridge + - drm: bridge: anx7625: don't crash if Type-C port is not used + - arm64: dts: qcom: arduino-imola: fix faulty spidev node + - drm/msm: add missing MODULE_DEVICE_ID definitions + - Revert "arm64: dts: qcom: agatti: enable FastRPC on the ADSP" + - QCLINUX: qcom.config: Enable compressed firmware support + - Revert "arm64: dts: qcom: qcs6490-rb3gen2: Adjust tsens thermal zone" + - FROMLIST: remoteproc: qcom: pas: Fix the dtb PAS context creation + - FROMLIST: remoteproc: qcom: pas: Map/unmap subsystem region before + auth_and_reset + - FROMLIST: remoteproc: qcom: pas: Drop unused dtb_mem_region field + - arm64: dts: qcom: Move rpm_requests in glink-edge node + - dt-bindings: clock: qcom,rpmcc: Add Shikra compatible + - dt-bindings: clock: qcom: Add GCC clocks for Shikra + - clk: qcom: smd-rpm: Add clocks for Shikra + - clk: qcom: Add support for Global clock controller on Shikra + - arm64: defconfig: Enable GCC on Shikra EVK boards + - arm64: dts: qcom: Add GCC and RPMCC node support + - FROMLIST: ASoC: dt-bindings: qcom,q6apm-lpass-dais: Document DAI subnode + - FROMLIST: ASoC: qcom: qdsp6: q6prm: add the missing LPASS MCLK clock IDs + - FROMLIST: ASoC: qcom: q6apm-lpass-dais: Add MI2S clock control + - FROMLIST: ASoC: qcom: sc8280xp: ASoC: qcom: sc8280xp: enhance machine + driver for board-specific config + - arm64: dts: qcom: Add SPMI bus controller for Shikra + - arm64: dts: qcom: Add RPM power domain controller for shikra + - arm64: dts: qcom: Add regulator for Retail and Industrial SOM variants + - FROMLIST: arm64: dts: qcom: talos: Add GPR node, audio services, and + MI2S1 TLMM pins + - FROMLIST: arm64: dts: qcom: talos-evk: Add sound card support with + DA7212 codec + - FROMLIST: arm64: dts: qcom: talos: Add EL2 overlay + - PENDING: arm64: dts: qcom: talos-evk-som: Enable Adreno 612 GPU + - FROMLIST: arm64: dts: qcom: talos: Flatten usb controller nodes + - FROMLIST: arm64: dts: qcom: talos: Mark usb controllers are wakeup + capable devices + - Revert "FROMLIST: arm64: dts: qcom: talos: Mark usb controllers are + wakeup capable devices" + - Revert "FROMLIST: arm64: dts: qcom: talos: Flatten usb controller nodes" + - FROMLIST: arm64: dts: qcom: remove the disabled replicator + - FROMLIST: arm64: dts: qcom: talos: Add QSPI support + - FROMLIST: arm64: dts: qcom: qcs615-ride: enable QSPI and NOR flash + - FROMLIST: arm64: dts: qcom: sm8750: Enable TSENS and thermal zones + - FROMLIST: thermal: Add Remote Proc cooling driver + - FROMLIST: dt-bindings: thermal: Add qcom,qmi-cooling yaml bindings + - FROMLIST: thermal: qcom: add qmi-cooling driver + - FROMLIST: dt-bindings: thermal: qcom-tsens: Document the SM8750 + Temperature Sensor + - FROMLIST: dt-bindings: hwmon: Add qcom,bcl-hwmon yaml bindings + - FROMLIST: hwmon: Add Qualcomm PMIC BCL hardware monitor driver + - FROMLIST: arm64: dts: qcom: x1e80100: Remove interconnect from SCM + device + - FROMLIST: arm64: dts: qcom: x1e80100: Add deepest idle state + - FROMLIST: arm64: dts: qcom: purwa: Drop the Hamoa workaround for PDC + - WORKAROUND: arm64: dts: qcom: hamoa-iot-evk: support Bluetooth over both + USB and UART + - WORKAROUND: power: sequencing: qcom-wcn: skip BT devices without bt- + enable GPIO + - dt-bindings: watchdog: qcom-wdt: Document Shikra watchdog + - arm64: dts: qcom: shikra: Add watchdog node + - FROMLIST: dt-bindings: interrupt-controller: qcom,pdc: Document reg and + QMP + - FROMLIST: irqchip/qcom-pdc: Configure PDC to pass through mode + - FROMLIST: dt-bindings: interrupt-controller: qcom,pdc: Document x1p42100 + PDC + - FROMLIST: arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC + - FROMLIST: arm64: dts: qcom: kaanpaali: Add USB support for MTP platform + - FROMLIST: arm64: dts: qcom: kaanpaali: Add USB support for QRD platform + - FROMLIST: spi: dt-bindings: qcom-qspi: Add QCS615 compatible + - FROMLIST: spi: spi-qcom-qspi: Add interconnect support for memory path + - FROMLIST: Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for + now" + - PENDING: media: iris: update MDT PAS load call for new API + - Add qcom-next log files for 20260403 + - wifi: ath12k: fix context switch in panic notifier issue + - QCLINUX: arm64: dts: qcom: workaround for TPM pins + - initial derivative + - add RT flavor + - formatting - -- Kuba Pawlak Mon, 27 Apr 2026 18:07:58 +0200 + -- Kuba Pawlak Mon, 27 Apr 2026 18:11:38 +0200 linux-qcom (7.0.0-1003.3) resolute; urgency=medium diff --git a/debian.qcom/reconstruct b/debian.qcom/reconstruct index 007db83ee5931..16e52ee71b8a0 100644 --- a/debian.qcom/reconstruct +++ b/debian.qcom/reconstruct @@ -1,4 +1,5 @@ # Recreate any symlinks created since the orig. +[ ! -L 'ubuntu/igh-ecat/master/rtdm-ioctl.c' ] && ln -sf 'ioctl.c' 'ubuntu/igh-ecat/master/rtdm-ioctl.c' chmod +x 'debian/cloud-tools/hv_get_dhcp_info' chmod +x 'debian/cloud-tools/hv_get_dns_info' chmod +x 'debian/cloud-tools/hv_set_ifconfig' @@ -30,10 +31,4 @@ chmod +x 'debian/templates/image.prerm.in' chmod +x 'debian/tests/rebuild' chmod +x 'debian/tests/ubuntu-regression-suite' # Remove any files deleted from the orig. -rm -f 'arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi' -rm -f 'arch/arm64/boot/dts/qcom/qcs8300.dtsi' -rm -f 'arch/arm64/boot/dts/qcom/sm6150.dtsi' -rm -f 'arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi' -rm -f 'arch/arm64/boot/dts/qcom/x1e80100.dtsi' -rm -f 'drivers/media/platform/qcom/iris/iris_platform_sm8250.c' exit 0 From 9c69977ee2a052ba0caf2ac8c4500c467f5eba6a Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Thu, 30 Apr 2026 14:06:19 +0200 Subject: [PATCH 0565/1330] [Config] change CONFIG options for -rt BugLink: https://bugs.launchpad.net/bugs/2142303 Signed-off-by: Kuba Pawlak --- debian.qcom/config/annotations | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 9521c3fb9f7ef..8cbc867670bd8 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -30,6 +30,12 @@ CONFIG_EFI_ZBOOT note<'we use arch/arm64/boot/Ima CONFIG_HSA_AMD_P2P policy<{'arm64': '-'}> CONFIG_HSA_AMD_P2P note<'LP: #1987394'> +CONFIG_HZ_1000 policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> +CONFIG_HZ_1000 note + +CONFIG_HZ_250 policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> +CONFIG_HZ_250 note + CONFIG_IPMMU_VMSA policy<{'arm64': '-'}> CONFIG_IPMMU_VMSA note<'LP: #1718734'> @@ -45,6 +51,12 @@ CONFIG_MMC_SDHCI note<'installation essential on CONFIG_MMC_SDHCI_PLTFM policy<{'arm64': 'y'}> CONFIG_MMC_SDHCI_PLTFM note<'boot essential on highbank'> +CONFIG_NO_HZ_FULL policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> +CONFIG_NO_HZ_FULL note + +CONFIG_NO_HZ_IDLE policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> +CONFIG_NO_HZ_IDLE note + CONFIG_NR_CPUS policy<{'arm64': '256'}> CONFIG_NR_CPUS note<'LP: #2042897 (arm64), LP: #1967889 (riscv64), LP: #1864198 (s390x)'> @@ -54,12 +66,18 @@ CONFIG_NUMA_BALANCING_DEFAULT_ENABLED note<'TODO: update note'> CONFIG_PREEMPT_DYNAMIC policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> CONFIG_PREEMPT_DYNAMIC note<'TODO: update note'> -CONFIG_RCU_LAZY policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> -CONFIG_RCU_LAZY note<'TODO: update note'> +CONFIG_RCU_LAZY policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_RCU_LAZY note CONFIG_RCU_LAZY_DEFAULT_OFF policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_RCU_LAZY_DEFAULT_OFF note<'TODO: update note'> +CONFIG_RCU_NOCB_CPU policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_RCU_NOCB_CPU note + +CONFIG_RCU_NOCB_CPU_DEFAULT_ALL policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> +CONFIG_RCU_NOCB_CPU_DEFAULT_ALL note + CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'arm64': 'y'}> CONFIG_REGULATOR_FIXED_VOLTAGE note<'boot essential on arm'> @@ -909,6 +927,7 @@ CONFIG_HW_RANDOM_OMAP policy<{'arm64': '-'}> CONFIG_HW_RANDOM_ROCKCHIP policy<{'arm64': '-'}> CONFIG_HW_RANDOM_STM32 policy<{'arm64': '-'}> CONFIG_HW_RANDOM_XGENE policy<{'arm64': '-'}> +CONFIG_HZ policy<{'arm64': '1000', 'arm64-qcom-rt': '250'}> CONFIG_I2C_ALTERA policy<{'arm64': '-'}> CONFIG_I2C_APPLE policy<{'arm64': '-'}> CONFIG_I2C_DEMUX_PINCTRL policy<{'arm64': 'n'}> @@ -1788,7 +1807,7 @@ CONFIG_RCAR_THERMAL policy<{'arm64': '-'}> CONFIG_RCU_BOOST policy<{'arm64-qcom-rt': 'y'}> CONFIG_RCU_BOOST_DELAY policy<{'arm64-qcom-rt': '500'}> CONFIG_RCU_CPU_STALL_TIMEOUT policy<{'arm64': '21'}> -CONFIG_RCU_NOCB_CPU_CB_BOOST policy<{'arm64-qcom-rt': 'y'}> +CONFIG_RCU_NOCB_CPU_CB_BOOST policy<{'arm64-qcom-rt': '-'}> CONFIG_READ_ONLY_THP_FOR_FS policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_REBOOT_MODE policy<{'arm64': 'y'}> CONFIG_REGMAP_AC97 policy<{'arm64': '-'}> @@ -2380,6 +2399,7 @@ CONFIG_TEST_HMM policy<{'arm64': 'n', 'arm64-qco CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS policy<{'arm64': '10000'}> CONFIG_THP_SWAP policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_THUNDERX2_PMU policy<{'arm64': '-'}> +CONFIG_TICK_CPU_ACCOUNTING policy<{'arm64-qcom-rt': 'n'}> CONFIG_TIMER_IMX_SYS_CTR policy<{'arm64': '-'}> CONFIG_TI_AM335X_ADC policy<{'arm64': '-'}> CONFIG_TI_AM65_CPSW_QOS policy<{'arm64': '-'}> From a7f1db6b984842f06878d81efeee2fe8dd505a30 Mon Sep 17 00:00:00 2001 From: Jianping Li Date: Tue, 24 Mar 2026 15:25:55 +0800 Subject: [PATCH 0566/1330] misc: fastrpc: fix race between buffer mapping and device removal fastrpc buffer mapping and unmapping paths can race with session teardown during device remove. Introduce a per-session map_mutex to serialize buffer map/unmap and DMA operations with session teardown. This ensures proper synchronization between buffer lifecycle and device removal and avoids crashes caused by concurrent map/unmap operations. Buglink: https://bugs.launchpad.net/bugs/2147001 [kuba-t-pawlak: context adjusted to account for missing functions] Signed-off-by: Jianping Li Signed-off-by: Kuba Pawlak --- drivers/misc/fastrpc.c | 51 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 46 insertions(+), 5 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 21b9bb63691ff..5e596ed65e09d 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -271,6 +271,7 @@ struct fastrpc_session_ctx { int sid; bool used; bool valid; + struct mutex mutex; }; struct fastrpc_soc_data { @@ -353,9 +354,14 @@ static inline u64 fastrpc_sid_offset(struct fastrpc_channel_ctx *cctx, static void fastrpc_free_map(struct kref *ref) { struct fastrpc_map *map; + struct fastrpc_user *fl; map = container_of(ref, struct fastrpc_map, refcount); + fl = map->fl; + if (!fl) + return; + if (map->table) { if (map->attr & FASTRPC_ATTR_SECUREMAP) { struct qcom_scm_vmperm perm; @@ -374,10 +380,16 @@ static void fastrpc_free_map(struct kref *ref) return; } } + mutex_lock(&fl->sctx->mutex); + if (!fl->sctx->dev) { + mutex_unlock(&fl->sctx->mutex); + return; + } dma_buf_unmap_attachment_unlocked(map->attach, map->table, DMA_BIDIRECTIONAL); dma_buf_detach(map->buf, map->attach); dma_buf_put(map->buf); + mutex_unlock(&fl->sctx->mutex); } if (map->fl) { @@ -434,9 +446,17 @@ static int fastrpc_map_lookup(struct fastrpc_user *fl, int fd, static void fastrpc_buf_free(struct fastrpc_buf *buf) { - dma_free_coherent(buf->dev, buf->size, buf->virt, - fastrpc_ipa_to_dma_addr(buf->fl->cctx, buf->dma_addr)); - kfree(buf); + struct fastrpc_user *fl = buf->fl; + + if (!fl) + return; + mutex_lock(&fl->sctx->mutex); + if (fl->sctx->dev) { + dma_free_coherent(buf->dev, buf->size, buf->virt, + fastrpc_ipa_to_dma_addr(buf->fl->cctx, buf->dma_addr)); + kfree(buf); + } + mutex_unlock(&fl->sctx->mutex); } static int __fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, @@ -459,8 +479,10 @@ static int __fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, buf->dev = dev; buf->raddr = 0; - buf->virt = dma_alloc_coherent(dev, buf->size, &buf->dma_addr, - GFP_KERNEL); + mutex_lock(&fl->sctx->mutex); + if (fl->sctx->dev) + buf->virt = dma_alloc_coherent(dev, buf->size, &buf->dma_addr, GFP_KERNEL); + mutex_unlock(&fl->sctx->mutex); if (!buf->virt) { mutex_destroy(&buf->lock); kfree(buf); @@ -503,6 +525,8 @@ static void fastrpc_channel_ctx_free(struct kref *ref) struct fastrpc_channel_ctx *cctx; cctx = container_of(ref, struct fastrpc_channel_ctx, refcount); + for (int i = 0; i < FASTRPC_MAX_SESSIONS; i++) + mutex_destroy(&cctx->session[i].mutex); kfree(cctx); } @@ -846,19 +870,29 @@ static int fastrpc_map_attach(struct fastrpc_user *fl, int fd, goto get_err; } + mutex_lock(&fl->sctx->mutex); + if (!fl->sctx->dev) { + err = -ENODEV; + mutex_unlock(&fl->sctx->mutex); + goto attach_err; + } + map->attach = dma_buf_attach(map->buf, sess->dev); if (IS_ERR(map->attach)) { dev_err(sess->dev, "Failed to attach dmabuf\n"); err = PTR_ERR(map->attach); + mutex_unlock(&fl->sctx->mutex); goto attach_err; } table = dma_buf_map_attachment_unlocked(map->attach, DMA_BIDIRECTIONAL); if (IS_ERR(table)) { err = PTR_ERR(table); + mutex_unlock(&fl->sctx->mutex); goto map_err; } map->table = table; + mutex_unlock(&fl->sctx->mutex); if (attr & FASTRPC_ATTR_SECUREMAP) map->dma_addr = sg_phys(map->table->sgl); @@ -2365,6 +2399,7 @@ static int fastrpc_cb_probe(struct platform_device *pdev) sess->used = false; sess->valid = true; sess->dev = dev; + mutex_init(&sess->mutex); dev_set_drvdata(dev, sess); if (cctx->domain_id == CDSP_DOMAIN_ID) @@ -2381,6 +2416,7 @@ static int fastrpc_cb_probe(struct platform_device *pdev) break; dup_sess = &cctx->session[cctx->sesscount++]; memcpy(dup_sess, sess, sizeof(*dup_sess)); + mutex_init(&dup_sess->mutex); } } spin_unlock_irqrestore(&cctx->lock, flags); @@ -2403,6 +2439,11 @@ static void fastrpc_cb_remove(struct platform_device *pdev) spin_lock_irqsave(&cctx->lock, flags); for (i = 0; i < FASTRPC_MAX_SESSIONS; i++) { if (cctx->session[i].sid == sess->sid) { + spin_unlock_irqrestore(&cctx->lock, flags); + mutex_lock(&cctx->session[i].mutex); + cctx->session[i].dev = NULL; + mutex_unlock(&cctx->session[i].mutex); + spin_lock_irqsave(&cctx->lock, flags); cctx->session[i].valid = false; cctx->sesscount--; } From 2ad3f84a3f5ca081c37af6ef7a80a3ab9e00b1b3 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 4 May 2026 10:42:25 +0200 Subject: [PATCH 0567/1330] UBUNTU: Start new release Ignore: yes Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 7b2ed6134e45b..6761320486c7b 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,5 +1,15 @@ +linux-qcom (7.0.0-1005.6) UNRELEASED; urgency=medium + + CHANGELOG: Do not edit directly. Autogenerated at release. + CHANGELOG: Use the printchanges target to see the current changes. + CHANGELOG: Use the insertchanges target to create the final log. + + -- Kuba Pawlak Mon, 04 May 2026 10:42:25 +0200 + linux-qcom (7.0.0-1004.5) resolute; urgency=medium + * resolute/linux: 7.0.0-15.15 -proposed tracker (LP: #2148866) + * Miscellaneous upstream changes - UPSTREAM: dt-bindings: usb: qcom,snps-dwc3: Add the SM8750 compatible - FROMLIST: dt-bindings: arm-smmu: Add compatible for Kaanapali and Glymur @@ -724,6 +734,8 @@ linux-qcom (7.0.0-1004.5) resolute; urgency=medium - add RT flavor - formatting + [ Ubuntu: 7.0.0-15.15 ] + -- Kuba Pawlak Mon, 27 Apr 2026 18:11:38 +0200 linux-qcom (7.0.0-1003.3) resolute; urgency=medium From 120ed481ca5152399f780272430984005d7471cd Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 4 May 2026 10:50:04 +0200 Subject: [PATCH 0568/1330] UBUNTU: Ubuntu-qcom-7.0.0-1005.7 Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 12 +++++++----- debian.qcom/config/annotations | 14 +++++++------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 6761320486c7b..3c14c1c89cff4 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,10 +1,12 @@ -linux-qcom (7.0.0-1005.6) UNRELEASED; urgency=medium +linux-qcom (7.0.0-1005.7) resolute; urgency=medium - CHANGELOG: Do not edit directly. Autogenerated at release. - CHANGELOG: Use the printchanges target to see the current changes. - CHANGELOG: Use the insertchanges target to create the final log. + * INVALID or PRIVATE BUG (LP: #2142303) + - [Config] change CONFIG options for -rt - -- Kuba Pawlak Mon, 04 May 2026 10:42:25 +0200 + * Miscellaneous upstream changes + - misc: fastrpc: fix race between buffer mapping and device removal + + -- Kuba Pawlak Mon, 04 May 2026 10:50:04 +0200 linux-qcom (7.0.0-1004.5) resolute; urgency=medium diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 8cbc867670bd8..d4fd3b082ddd5 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -31,10 +31,10 @@ CONFIG_HSA_AMD_P2P policy<{'arm64': '-'}> CONFIG_HSA_AMD_P2P note<'LP: #1987394'> CONFIG_HZ_1000 policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> -CONFIG_HZ_1000 note +CONFIG_HZ_1000 note<'TODO: update note'> CONFIG_HZ_250 policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> -CONFIG_HZ_250 note +CONFIG_HZ_250 note<'TODO: update note'> CONFIG_IPMMU_VMSA policy<{'arm64': '-'}> CONFIG_IPMMU_VMSA note<'LP: #1718734'> @@ -52,10 +52,10 @@ CONFIG_MMC_SDHCI_PLTFM policy<{'arm64': 'y'}> CONFIG_MMC_SDHCI_PLTFM note<'boot essential on highbank'> CONFIG_NO_HZ_FULL policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> -CONFIG_NO_HZ_FULL note +CONFIG_NO_HZ_FULL note<'TODO: update note'> CONFIG_NO_HZ_IDLE policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> -CONFIG_NO_HZ_IDLE note +CONFIG_NO_HZ_IDLE note<'TODO: update note'> CONFIG_NR_CPUS policy<{'arm64': '256'}> CONFIG_NR_CPUS note<'LP: #2042897 (arm64), LP: #1967889 (riscv64), LP: #1864198 (s390x)'> @@ -67,16 +67,16 @@ CONFIG_PREEMPT_DYNAMIC policy<{'arm64': 'y', 'arm64-qco CONFIG_PREEMPT_DYNAMIC note<'TODO: update note'> CONFIG_RCU_LAZY policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> -CONFIG_RCU_LAZY note +CONFIG_RCU_LAZY note<'TODO: update note'> CONFIG_RCU_LAZY_DEFAULT_OFF policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_RCU_LAZY_DEFAULT_OFF note<'TODO: update note'> CONFIG_RCU_NOCB_CPU policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> -CONFIG_RCU_NOCB_CPU note +CONFIG_RCU_NOCB_CPU note<'TODO: update note'> CONFIG_RCU_NOCB_CPU_DEFAULT_ALL policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> -CONFIG_RCU_NOCB_CPU_DEFAULT_ALL note +CONFIG_RCU_NOCB_CPU_DEFAULT_ALL note<'TODO: update note'> CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'arm64': 'y'}> CONFIG_REGULATOR_FIXED_VOLTAGE note<'boot essential on arm'> From ee3f4412438e444f600ca4895eec1597e73409c2 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Fri, 29 May 2026 11:23:17 +0200 Subject: [PATCH 0569/1330] UBUNTU: [Packaging] update Ubuntu.md BugLink: https://bugs.launchpad.net/bugs/1786013 Signed-off-by: Kuba Pawlak --- Ubuntu.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubuntu.md b/Ubuntu.md index a49309c1d8c9d..5408e7dbc87bf 100644 --- a/Ubuntu.md +++ b/Ubuntu.md @@ -1,8 +1,8 @@ -Name: linux +Name: linux-qcom Version: 7.0.0 Series: 26.04 (resolute) Description: This is the source code for the Ubuntu linux kernel for the 26.04 series. This - source tree is used to produce the flavours: generic, generic-64k. + source tree is used to produce the flavours: qcom, qcom-rt. This kernel is configured to support the widest range of desktop, laptop and server configurations. From 506b2d9a8cc822b865b8f6c77c384625aa9f5f41 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Fri, 29 May 2026 11:23:21 +0200 Subject: [PATCH 0570/1330] UBUNTU: Start new release Ignore: yes Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 3c14c1c89cff4..b626b97896758 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,3 +1,11 @@ +linux-qcom (7.0.0-1006.8) UNRELEASED; urgency=medium + + CHANGELOG: Do not edit directly. Autogenerated at release. + CHANGELOG: Use the printchanges target to see the current changes. + CHANGELOG: Use the insertchanges target to create the final log. + + -- Kuba Pawlak Fri, 29 May 2026 11:23:21 +0200 + linux-qcom (7.0.0-1005.7) resolute; urgency=medium * INVALID or PRIVATE BUG (LP: #2142303) From 86eecc986e889fa54dd763878e09c42718c4f452 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Fri, 29 May 2026 11:23:37 +0200 Subject: [PATCH 0571/1330] UBUNTU: link-to-tracker: update tracking bug BugLink: https://bugs.launchpad.net/bugs/2154429 Properties: no-test-build Signed-off-by: Kuba Pawlak --- debian.qcom/tracking-bug | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian.qcom/tracking-bug b/debian.qcom/tracking-bug index d3b4c49558578..86fd99fae49ed 100644 --- a/debian.qcom/tracking-bug +++ b/debian.qcom/tracking-bug @@ -1 +1 @@ -2133502 d2025.10.20-6 +2154429 d2026.05.20-1 From 4ba9e0cb2a85da0a5df7a15e4fcf8b92dd3f2e95 Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Thu, 18 Sep 2025 14:57:03 +0530 Subject: [PATCH 0572/1330] FROMGIT: regulator: rpmh-regulator: Add support for new resource name format Currently rpmh-regulator resource name inside CMD-DB follows this format: `^(ldo|smp|bob|vs)[a-n][1-9][0-9]?$` (eg - ldob11, smpa2, bobc1 etc) Here `[a-n]` in the resource name signifies the `pmic-id`. However, newer firmware follows a different format that also includes the `bus_id` as well in the resource name. New format: `^(L|S|B)[1-9][0-9]?[A-N]_E[0-3]$` (eg - L11B_E1, S2A_E0, B1C_E0 etc) Here `_E[0-3]` at the end is the `bus_id`, and upper case `[A-N]` is used to denote `pmic-id`, while the regulator `(ldo|smp|bob)` is replaced with their initials in upper case `(L|S|B|VA)`. To handle this properly, do the following: - Remove the `resource_name` member from vreg init data - Add `index` and `regulator_hw_type` new members, which will contain the index number and the regulator hardware type (SMPS/LDO/BOB/VS) which can be combined with the pmic-id read from the devicetree to generate the resource_name. - Choose new resource name format if `pmic-id` contains `_E` in it, else fallback to old format. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Kamal Wadhwa Link: https://patch.msgid.link/20250918-glymur-rpmh-regulator-driver-v3-3-184c09678be3@oss.qualcomm.com Signed-off-by: Mark Brown Signed-off-by: Yijie Yang (cherry picked from commit 71f424fb76e46df5b2a53dd18f54efeb6a6b267e) --- drivers/regulator/qcom-rpmh-regulator.c | 1146 ----------------------- 1 file changed, 1146 deletions(-) diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qcom-rpmh-regulator.c index 6e4cb2871fca8..2809036034322 100644 --- a/drivers/regulator/qcom-rpmh-regulator.c +++ b/drivers/regulator/qcom-rpmh-regulator.c @@ -97,953 +97,6 @@ static const struct resource_name_formats vreg_rsc_name_lookup[NUM_REGULATOR_TYP #define PMIC530_LDO_MODE_OPM 5 #define PMIC530_LDO_MODE_HPM 7 -#define PMIC_ID_LEN 4 -/** - * struct rpmh_vreg_hw_data - RPMh regulator hardware configurations - * @regulator_type: RPMh accelerator type used to manage this - * regulator - * @ops: Pointer to regulator ops callback structure - * @voltage_ranges: The possible ranges of voltages supported by this - * PMIC regulator type - * @n_linear_ranges: Number of entries in voltage_ranges - * @n_voltages: The number of unique voltage set points defined - * by voltage_ranges - * @hpm_min_load_uA: Minimum load current in microamps that requires - * high power mode (HPM) operation. This is used - * for LDO hardware type regulators only. - * @pmic_mode_map: Array indexed by regulator framework mode - * containing PMIC hardware modes. Must be large - * enough to index all framework modes supported - * by this regulator hardware type. - * @of_map_mode: Maps an RPMH_REGULATOR_MODE_* mode value defined - * in device tree to a regulator framework mode - */ -struct rpmh_vreg_hw_data { - enum rpmh_regulator_type regulator_type; - const struct regulator_ops *ops; - const struct linear_range *voltage_ranges; - int n_linear_ranges; - int n_voltages; - int hpm_min_load_uA; - const int *pmic_mode_map; - unsigned int (*of_map_mode)(unsigned int mode); -}; - -/** - * struct rpmh_vreg - individual RPMh regulator data structure encapsulating a - * single regulator device - * @dev: Device pointer for the top-level PMIC RPMh - * regulator parent device. This is used as a - * handle in RPMh write requests. - * @addr: Base address of the regulator resource within - * an RPMh accelerator - * @rdesc: Regulator descriptor - * @hw_data: PMIC regulator configuration data for this RPMh - * regulator - * @always_wait_for_ack: Boolean flag indicating if a request must always - * wait for an ACK from RPMh before continuing even - * if it corresponds to a strictly lower power - * state (e.g. enabled --> disabled). - * @enabled: Flag indicating if the regulator is enabled or - * not - * @bypassed: Boolean indicating if the regulator is in - * bypass (pass-through) mode or not. This is - * only used by BOB rpmh-regulator resources. - * @voltage_selector: Selector used for get_voltage_sel() and - * set_voltage_sel() callbacks - * @mode: RPMh VRM regulator current framework mode - */ -struct rpmh_vreg { - struct device *dev; - u32 addr; - struct regulator_desc rdesc; - const struct rpmh_vreg_hw_data *hw_data; - bool always_wait_for_ack; - - int enabled; - bool bypassed; - int voltage_selector; - unsigned int mode; -}; - -/** - * struct rpmh_vreg_init_data - initialization data for an RPMh regulator - * @name: Name for the regulator which also corresponds - * to the device tree subnode name of the regulator - * @index: This is the index number of the regulator present - * on the PMIC. - * @vreg_hw_type: Regulator HW type enum, this must be BOB, SMPS, - * LDO, VS, based on the regulator HW type. - * @supply_name: Parent supply regulator name - * @hw_data: Configuration data for this PMIC regulator type - */ -struct rpmh_vreg_init_data { - const char *name; - enum regulator_hw_type vreg_hw_type; - int index; - const char *supply_name; - const struct rpmh_vreg_hw_data *hw_data; -}; - -/** - * rpmh_regulator_send_request() - send the request to RPMh - * @vreg: Pointer to the RPMh regulator - * @cmd: Pointer to the RPMh command to send - * @wait_for_ack: Boolean indicating if execution must wait until the - * request has been acknowledged as complete - * - * Return: 0 on success, or a negative error number on failure - */ -static int rpmh_regulator_send_request(struct rpmh_vreg *vreg, - struct tcs_cmd *cmd, bool wait_for_ack) -{ - int ret; - - if (wait_for_ack || vreg->always_wait_for_ack) - ret = rpmh_write(vreg->dev, RPMH_ACTIVE_ONLY_STATE, cmd, 1); - else - ret = rpmh_write_async(vreg->dev, RPMH_ACTIVE_ONLY_STATE, cmd, - 1); - - return ret; -} - -static int _rpmh_regulator_vrm_set_voltage_sel(struct regulator_dev *rdev, - unsigned int selector, bool wait_for_ack) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - struct tcs_cmd cmd = { - .addr = vreg->addr + RPMH_REGULATOR_REG_VRM_VOLTAGE, - }; - int ret; - - /* VRM voltage control register is set with voltage in millivolts. */ - cmd.data = DIV_ROUND_UP(regulator_list_voltage_linear_range(rdev, - selector), 1000); - - ret = rpmh_regulator_send_request(vreg, &cmd, wait_for_ack); - if (!ret) - vreg->voltage_selector = selector; - - return ret; -} - -static int rpmh_regulator_vrm_set_voltage_sel(struct regulator_dev *rdev, - unsigned int selector) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - - if (vreg->enabled == -EINVAL) { - /* - * Cache the voltage and send it later when the regulator is - * enabled or disabled. - */ - vreg->voltage_selector = selector; - return 0; - } - - return _rpmh_regulator_vrm_set_voltage_sel(rdev, selector, - selector > vreg->voltage_selector); -} - -static int rpmh_regulator_vrm_get_voltage_sel(struct regulator_dev *rdev) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - - return vreg->voltage_selector; -} - -static int rpmh_regulator_is_enabled(struct regulator_dev *rdev) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - - return vreg->enabled; -} - -static int rpmh_regulator_set_enable_state(struct regulator_dev *rdev, - bool enable) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - struct tcs_cmd cmd = { - .addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE, - .data = enable, - }; - int ret; - - if (vreg->enabled == -EINVAL && - vreg->voltage_selector != -ENOTRECOVERABLE) { - ret = _rpmh_regulator_vrm_set_voltage_sel(rdev, - vreg->voltage_selector, true); - if (ret < 0) - return ret; - } - - ret = rpmh_regulator_send_request(vreg, &cmd, enable); - if (!ret) - vreg->enabled = enable; - - return ret; -} - -static int rpmh_regulator_enable(struct regulator_dev *rdev) -{ - return rpmh_regulator_set_enable_state(rdev, true); -} - -static int rpmh_regulator_disable(struct regulator_dev *rdev) -{ - return rpmh_regulator_set_enable_state(rdev, false); -} - -static int rpmh_regulator_vrm_set_mode_bypass(struct rpmh_vreg *vreg, - unsigned int mode, bool bypassed) -{ - struct tcs_cmd cmd = { - .addr = vreg->addr + RPMH_REGULATOR_REG_VRM_MODE, - }; - int pmic_mode; - - if (mode > REGULATOR_MODE_STANDBY) - return -EINVAL; - - pmic_mode = vreg->hw_data->pmic_mode_map[mode]; - if (pmic_mode < 0) - return pmic_mode; - - if (bypassed) - cmd.data = PMIC4_BOB_MODE_PASS; - else - cmd.data = pmic_mode; - - return rpmh_regulator_send_request(vreg, &cmd, true); -} - -static int rpmh_regulator_vrm_set_mode(struct regulator_dev *rdev, - unsigned int mode) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - int ret; - - if (mode == vreg->mode) - return 0; - - ret = rpmh_regulator_vrm_set_mode_bypass(vreg, mode, vreg->bypassed); - if (!ret) - vreg->mode = mode; - - return ret; -} - -static unsigned int rpmh_regulator_vrm_get_mode(struct regulator_dev *rdev) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - - return vreg->mode; -} - -/** - * rpmh_regulator_vrm_get_optimum_mode() - get the mode based on the load - * @rdev: Regulator device pointer for the rpmh-regulator - * @input_uV: Input voltage - * @output_uV: Output voltage - * @load_uA: Aggregated load current in microamps - * - * This function is used in the regulator_ops for VRM type RPMh regulator - * devices. - * - * Return: 0 on success, or a negative error number on failure - */ -static unsigned int rpmh_regulator_vrm_get_optimum_mode( - struct regulator_dev *rdev, int input_uV, int output_uV, int load_uA) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - - if (load_uA >= vreg->hw_data->hpm_min_load_uA) - return REGULATOR_MODE_NORMAL; - else - return REGULATOR_MODE_IDLE; -} - -static int rpmh_regulator_vrm_set_bypass(struct regulator_dev *rdev, - bool enable) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - int ret; - - if (vreg->bypassed == enable) - return 0; - - ret = rpmh_regulator_vrm_set_mode_bypass(vreg, vreg->mode, enable); - if (!ret) - vreg->bypassed = enable; - - return ret; -} - -static int rpmh_regulator_vrm_get_bypass(struct regulator_dev *rdev, - bool *enable) -{ - struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); - - *enable = vreg->bypassed; - - return 0; -} - -static const struct regulator_ops rpmh_regulator_vrm_ops = { - .enable = rpmh_regulator_enable, - .disable = rpmh_regulator_disable, - .is_enabled = rpmh_regulator_is_enabled, - .set_voltage_sel = rpmh_regulator_vrm_set_voltage_sel, - .get_voltage_sel = rpmh_regulator_vrm_get_voltage_sel, - .list_voltage = regulator_list_voltage_linear_range, - .set_mode = rpmh_regulator_vrm_set_mode, - .get_mode = rpmh_regulator_vrm_get_mode, -}; - -static const struct regulator_ops rpmh_regulator_vrm_drms_ops = { - .enable = rpmh_regulator_enable, - .disable = rpmh_regulator_disable, - .is_enabled = rpmh_regulator_is_enabled, - .set_voltage_sel = rpmh_regulator_vrm_set_voltage_sel, - .get_voltage_sel = rpmh_regulator_vrm_get_voltage_sel, - .list_voltage = regulator_list_voltage_linear_range, - .set_mode = rpmh_regulator_vrm_set_mode, - .get_mode = rpmh_regulator_vrm_get_mode, - .get_optimum_mode = rpmh_regulator_vrm_get_optimum_mode, -}; - -static const struct regulator_ops rpmh_regulator_vrm_bypass_ops = { - .enable = rpmh_regulator_enable, - .disable = rpmh_regulator_disable, - .is_enabled = rpmh_regulator_is_enabled, - .set_voltage_sel = rpmh_regulator_vrm_set_voltage_sel, - .get_voltage_sel = rpmh_regulator_vrm_get_voltage_sel, - .list_voltage = regulator_list_voltage_linear_range, - .set_mode = rpmh_regulator_vrm_set_mode, - .get_mode = rpmh_regulator_vrm_get_mode, - .set_bypass = rpmh_regulator_vrm_set_bypass, - .get_bypass = rpmh_regulator_vrm_get_bypass, -}; - -static const struct regulator_ops rpmh_regulator_xob_ops = { - .enable = rpmh_regulator_enable, - .disable = rpmh_regulator_disable, - .is_enabled = rpmh_regulator_is_enabled, -}; - -/** - * rpmh_regulator_init_vreg() - initialize all attributes of an rpmh-regulator - * @vreg: Pointer to the individual rpmh-regulator resource - * @dev: Pointer to the top level rpmh-regulator PMIC device - * @node: Pointer to the individual rpmh-regulator resource - * device node - * @pmic_id: String used to identify the top level rpmh-regulator - * PMIC device on the board - * @pmic_rpmh_data: Pointer to a null-terminated array of rpmh-regulator - * resources defined for the top level PMIC device - * - * Return: 0 on success, or a negative error number on failure - */ -static int rpmh_regulator_init_vreg(struct rpmh_vreg *vreg, struct device *dev, - struct device_node *node, const char *pmic_id, - const struct rpmh_vreg_init_data *pmic_rpmh_data) -{ - struct regulator_config reg_config = {}; - char rpmh_resource_name[20] = ""; - const char *rsc_name; - const struct rpmh_vreg_init_data *rpmh_data; - struct regulator_init_data *init_data; - struct regulator_dev *rdev; - int ret; - - vreg->dev = dev; - - for (rpmh_data = pmic_rpmh_data; rpmh_data->name; rpmh_data++) - if (of_node_name_eq(node, rpmh_data->name)) - break; - - if (!rpmh_data->name) { - dev_err(dev, "Unknown regulator %pOFn\n", node); - return -EINVAL; - } - - if (strnlen(pmic_id, PMIC_ID_LEN) > 1 && strnstr(pmic_id, "_E", PMIC_ID_LEN)) { - rsc_name = vreg_rsc_name_lookup[rpmh_data->vreg_hw_type].rsc_name_fmt; - scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name), - rsc_name, rpmh_data->index, pmic_id); - - } else { - rsc_name = vreg_rsc_name_lookup[rpmh_data->vreg_hw_type].rsc_name_fmt1; - scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name), - rsc_name, pmic_id, rpmh_data->index); - } - - vreg->addr = cmd_db_read_addr(rpmh_resource_name); - if (!vreg->addr) { - dev_err(dev, "%pOFn: could not find RPMh address for resource %s\n", - node, rpmh_resource_name); - return -ENODEV; - } - - vreg->rdesc.name = rpmh_data->name; - vreg->rdesc.supply_name = rpmh_data->supply_name; - vreg->hw_data = rpmh_data->hw_data; - - vreg->enabled = -EINVAL; - vreg->voltage_selector = -ENOTRECOVERABLE; - vreg->mode = REGULATOR_MODE_INVALID; - - if (rpmh_data->hw_data->n_voltages) { - vreg->rdesc.linear_ranges = rpmh_data->hw_data->voltage_ranges; - vreg->rdesc.n_linear_ranges = rpmh_data->hw_data->n_linear_ranges; - vreg->rdesc.n_voltages = rpmh_data->hw_data->n_voltages; - } - - vreg->always_wait_for_ack = of_property_read_bool(node, - "qcom,always-wait-for-ack"); - - vreg->rdesc.owner = THIS_MODULE; - vreg->rdesc.type = REGULATOR_VOLTAGE; - vreg->rdesc.ops = vreg->hw_data->ops; - vreg->rdesc.of_map_mode = vreg->hw_data->of_map_mode; - - init_data = of_get_regulator_init_data(dev, node, &vreg->rdesc); - if (!init_data) - return -ENOMEM; - - if (rpmh_data->hw_data->regulator_type == XOB && - init_data->constraints.min_uV && - init_data->constraints.min_uV == init_data->constraints.max_uV) { - vreg->rdesc.fixed_uV = init_data->constraints.min_uV; - vreg->rdesc.n_voltages = 1; - } - - reg_config.dev = dev; - reg_config.init_data = init_data; - reg_config.of_node = node; - reg_config.driver_data = vreg; - - rdev = devm_regulator_register(dev, &vreg->rdesc, ®_config); - if (IS_ERR(rdev)) { - ret = PTR_ERR(rdev); - dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", - node, ret); - return ret; - } - - dev_dbg(dev, "%pOFn regulator registered for RPMh resource %s @ 0x%05X\n", - node, rpmh_resource_name, vreg->addr); - - return 0; -} - -static const int pmic_mode_map_pmic4_ldo[REGULATOR_MODE_STANDBY + 1] = { - [REGULATOR_MODE_INVALID] = -EINVAL, - [REGULATOR_MODE_STANDBY] = PMIC4_LDO_MODE_RETENTION, - [REGULATOR_MODE_IDLE] = PMIC4_LDO_MODE_LPM, - [REGULATOR_MODE_NORMAL] = PMIC4_LDO_MODE_HPM, - [REGULATOR_MODE_FAST] = -EINVAL, -}; - -static const int pmic_mode_map_pmic5_ldo[REGULATOR_MODE_STANDBY + 1] = { - [REGULATOR_MODE_INVALID] = -EINVAL, - [REGULATOR_MODE_STANDBY] = PMIC5_LDO_MODE_RETENTION, - [REGULATOR_MODE_IDLE] = PMIC5_LDO_MODE_LPM, - [REGULATOR_MODE_NORMAL] = PMIC5_LDO_MODE_HPM, - [REGULATOR_MODE_FAST] = -EINVAL, -}; - -static const int pmic_mode_map_pmic5_ldo_hpm[REGULATOR_MODE_STANDBY + 1] = { - [REGULATOR_MODE_INVALID] = -EINVAL, - [REGULATOR_MODE_STANDBY] = -EINVAL, - [REGULATOR_MODE_IDLE] = -EINVAL, - [REGULATOR_MODE_NORMAL] = PMIC5_LDO_MODE_HPM, - [REGULATOR_MODE_FAST] = -EINVAL, -}; - -static const int pmic_mode_map_pmic530_ldo[REGULATOR_MODE_STANDBY + 1] = { - [REGULATOR_MODE_INVALID] = -EINVAL, - [REGULATOR_MODE_STANDBY] = PMIC530_LDO_MODE_RETENTION, - [REGULATOR_MODE_IDLE] = PMIC530_LDO_MODE_LPM, - [REGULATOR_MODE_NORMAL] = PMIC530_LDO_MODE_OPM, - [REGULATOR_MODE_FAST] = PMIC530_LDO_MODE_HPM, -}; - -static unsigned int rpmh_regulator_pmic4_ldo_of_map_mode(unsigned int rpmh_mode) -{ - unsigned int mode; - - switch (rpmh_mode) { - case RPMH_REGULATOR_MODE_HPM: - mode = REGULATOR_MODE_NORMAL; - break; - case RPMH_REGULATOR_MODE_LPM: - mode = REGULATOR_MODE_IDLE; - break; - case RPMH_REGULATOR_MODE_RET: - mode = REGULATOR_MODE_STANDBY; - break; - default: - mode = REGULATOR_MODE_INVALID; - break; - } - - return mode; -} - -static unsigned int rpmh_regulator_pmic530_ldo_of_map_mode(unsigned int rpmh_mode) -{ - unsigned int mode; - - switch (rpmh_mode) { - case RPMH_REGULATOR_MODE_HPM: - mode = REGULATOR_MODE_FAST; - break; - case RPMH_REGULATOR_MODE_AUTO: - mode = REGULATOR_MODE_NORMAL; - break; - case RPMH_REGULATOR_MODE_LPM: - mode = REGULATOR_MODE_IDLE; - break; - case RPMH_REGULATOR_MODE_RET: - mode = REGULATOR_MODE_STANDBY; - break; - default: - mode = REGULATOR_MODE_INVALID; - break; - } - return mode; -} - -static const int pmic_mode_map_pmic4_smps[REGULATOR_MODE_STANDBY + 1] = { - [REGULATOR_MODE_INVALID] = -EINVAL, - [REGULATOR_MODE_STANDBY] = PMIC4_SMPS_MODE_RETENTION, - [REGULATOR_MODE_IDLE] = PMIC4_SMPS_MODE_PFM, - [REGULATOR_MODE_NORMAL] = PMIC4_SMPS_MODE_AUTO, - [REGULATOR_MODE_FAST] = PMIC4_SMPS_MODE_PWM, -}; - -static const int pmic_mode_map_pmic5_smps[REGULATOR_MODE_STANDBY + 1] = { - [REGULATOR_MODE_INVALID] = -EINVAL, - [REGULATOR_MODE_STANDBY] = PMIC5_SMPS_MODE_RETENTION, - [REGULATOR_MODE_IDLE] = PMIC5_SMPS_MODE_PFM, - [REGULATOR_MODE_NORMAL] = PMIC5_SMPS_MODE_AUTO, - [REGULATOR_MODE_FAST] = PMIC5_SMPS_MODE_PWM, -}; - -static unsigned int -rpmh_regulator_pmic4_smps_of_map_mode(unsigned int rpmh_mode) -{ - unsigned int mode; - - switch (rpmh_mode) { - case RPMH_REGULATOR_MODE_HPM: - mode = REGULATOR_MODE_FAST; - break; - case RPMH_REGULATOR_MODE_AUTO: - mode = REGULATOR_MODE_NORMAL; - break; - case RPMH_REGULATOR_MODE_LPM: - mode = REGULATOR_MODE_IDLE; - break; - case RPMH_REGULATOR_MODE_RET: - mode = REGULATOR_MODE_STANDBY; - break; - default: - mode = REGULATOR_MODE_INVALID; - break; - } - - return mode; -} - -static const int pmic_mode_map_pmic4_bob[REGULATOR_MODE_STANDBY + 1] = { - [REGULATOR_MODE_INVALID] = -EINVAL, - [REGULATOR_MODE_STANDBY] = -EINVAL, - [REGULATOR_MODE_IDLE] = PMIC4_BOB_MODE_PFM, - [REGULATOR_MODE_NORMAL] = PMIC4_BOB_MODE_AUTO, - [REGULATOR_MODE_FAST] = PMIC4_BOB_MODE_PWM, -}; - -static const int pmic_mode_map_pmic5_bob[REGULATOR_MODE_STANDBY + 1] = { - [REGULATOR_MODE_INVALID] = -EINVAL, - [REGULATOR_MODE_STANDBY] = -EINVAL, - [REGULATOR_MODE_IDLE] = PMIC5_BOB_MODE_PFM, - [REGULATOR_MODE_NORMAL] = PMIC5_BOB_MODE_AUTO, - [REGULATOR_MODE_FAST] = PMIC5_BOB_MODE_PWM, -}; - -static unsigned int rpmh_regulator_pmic4_bob_of_map_mode(unsigned int rpmh_mode) -{ - unsigned int mode; - - switch (rpmh_mode) { - case RPMH_REGULATOR_MODE_HPM: - mode = REGULATOR_MODE_FAST; - break; - case RPMH_REGULATOR_MODE_AUTO: - mode = REGULATOR_MODE_NORMAL; - break; - case RPMH_REGULATOR_MODE_LPM: - mode = REGULATOR_MODE_IDLE; - break; - default: - mode = REGULATOR_MODE_INVALID; - break; - } - - return mode; -} - -static const struct rpmh_vreg_hw_data pmic4_pldo = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 256, - .hpm_min_load_uA = 10000, - .pmic_mode_map = pmic_mode_map_pmic4_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic4_pldo_lv = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 128, - .hpm_min_load_uA = 10000, - .pmic_mode_map = pmic_mode_map_pmic4_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic4_nldo = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 128, - .hpm_min_load_uA = 30000, - .pmic_mode_map = pmic_mode_map_pmic4_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic4_hfsmps3 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 216, - .pmic_mode_map = pmic_mode_map_pmic4_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic4_ftsmps426 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000), - }, - .n_linear_ranges = 1, - .n_voltages = 259, - .pmic_mode_map = pmic_mode_map_pmic4_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic4_bob = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_bypass_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000), - }, - .n_linear_ranges = 1, - .n_voltages = 84, - .pmic_mode_map = pmic_mode_map_pmic4_bob, - .of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic4_lvs = { - .regulator_type = XOB, - .ops = &rpmh_regulator_xob_ops, - /* LVS hardware does not support voltage or mode configuration. */ -}; - -static const struct rpmh_vreg_hw_data pmic5_pldo = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 256, - .hpm_min_load_uA = 10000, - .pmic_mode_map = pmic_mode_map_pmic5_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_pldo_lv = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 63, - .hpm_min_load_uA = 10000, - .pmic_mode_map = pmic_mode_map_pmic5_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_pldo515_mv = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1800000, 0, 187, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 188, - .hpm_min_load_uA = 10000, - .pmic_mode_map = pmic_mode_map_pmic5_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_pldo502 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 256, - .pmic_mode_map = pmic_mode_map_pmic5_ldo_hpm, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_pldo502ln = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1800000, 0, 2, 200000), - REGULATOR_LINEAR_RANGE(2608000, 3, 28, 16000), - REGULATOR_LINEAR_RANGE(3104000, 29, 30, 96000), - REGULATOR_LINEAR_RANGE(3312000, 31, 31, 0), - }, - .n_linear_ranges = 4, - .n_voltages = 32, - .pmic_mode_map = pmic_mode_map_pmic5_ldo_hpm, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_nldo = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 124, - .hpm_min_load_uA = 30000, - .pmic_mode_map = pmic_mode_map_pmic5_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_nldo515 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 211, - .hpm_min_load_uA = 30000, - .pmic_mode_map = pmic_mode_map_pmic5_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_nldo502 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(528000, 0, 127, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 128, - .hpm_min_load_uA = 30000, - .pmic_mode_map = pmic_mode_map_pmic5_ldo, - .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_hfsmps510 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 216, - .pmic_mode_map = pmic_mode_map_pmic5_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_ftsmps510 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(300000, 0, 263, 4000), - }, - .n_linear_ranges = 1, - .n_voltages = 264, - .pmic_mode_map = pmic_mode_map_pmic5_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_ftsmps520 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(300000, 0, 263, 4000), - }, - .n_linear_ranges = 1, - .n_voltages = 264, - .pmic_mode_map = pmic_mode_map_pmic5_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_ftsmps525 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(300000, 0, 267, 4000), - REGULATOR_LINEAR_RANGE(1376000, 268, 438, 8000), - }, - .n_linear_ranges = 2, - .n_voltages = 439, - .pmic_mode_map = pmic_mode_map_pmic5_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_ftsmps527 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 215, - .pmic_mode_map = pmic_mode_map_pmic5_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_hfsmps515 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(320000, 0, 235, 16000), - }, - .n_linear_ranges = 1, - .n_voltages = 236, - .pmic_mode_map = pmic_mode_map_pmic5_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_hfsmps515_1 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(900000, 0, 4, 16000), - }, - .n_linear_ranges = 1, - .n_voltages = 5, - .pmic_mode_map = pmic_mode_map_pmic5_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_bob = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_bypass_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(3000000, 0, 31, 32000), - }, - .n_linear_ranges = 1, - .n_voltages = 32, - .pmic_mode_map = pmic_mode_map_pmic5_bob, - .of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_nldo530 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 211, - .hpm_min_load_uA = 30000, - .pmic_mode_map = pmic_mode_map_pmic530_ldo, - .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp150 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 256, - .hpm_min_load_uA = 10000, - .pmic_mode_map = pmic_mode_map_pmic530_ldo, - .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp300 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 256, - .hpm_min_load_uA = 20000, - .pmic_mode_map = pmic_mode_map_pmic530_ldo, - .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp600 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_drms_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), - }, - .n_linear_ranges = 1, - .n_voltages = 256, - .hpm_min_load_uA = 40000, - .pmic_mode_map = pmic_mode_map_pmic530_ldo, - .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode, -}; - -static const struct rpmh_vreg_hw_data pmic5_ftsmps530 = { - .regulator_type = VRM, - .ops = &rpmh_regulator_vrm_ops, - .voltage_ranges = (struct linear_range[]) { - REGULATOR_LINEAR_RANGE(252000, 0, 305, 4000), - REGULATOR_LINEAR_RANGE(1480000, 306, 464, 8000), - }, - .n_linear_ranges = 2, - .n_voltages = 465, - .pmic_mode_map = pmic_mode_map_pmic5_smps, - .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, -}; - #define RPMH_VREG(_name, _vreg_hw_type, _index, _hw_data, _supply_name) \ { \ .name = _name, \ @@ -1544,205 +597,6 @@ static const struct rpmh_vreg_init_data pmh0110_vreg_data[] = { RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3"), RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l4"), {} -}; - -static const struct rpmh_vreg_init_data pmx55_vreg_data[] = { - RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"), - RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"), - RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps510, "vdd-s3"), - RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"), - RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"), - RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"), - RPMH_VREG("smps7", SMPS, 7, &pmic5_hfsmps510, "vdd-s7"), - RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"), - RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"), - RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l9"), - RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4-l12"), - RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6"), - RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6"), - RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7-l8"), - RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l7-l8"), - RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l3-l9"), - RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10-l11-l13"), - RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l10-l11-l13"), - RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l4-l12"), - RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l10-l11-l13"), - RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14"), - RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l15"), - RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l16"), - {} -}; - -static const struct rpmh_vreg_init_data pmx65_vreg_data[] = { - RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"), - RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"), - RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps510, "vdd-s3"), - RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"), - RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"), - RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"), - RPMH_VREG("smps7", SMPS, 7, &pmic5_hfsmps510, "vdd-s7"), - RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"), - RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"), - RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l18"), - RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"), - RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4"), - RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6-l16"), - RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6-l16"), - RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7"), - RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8-l9"), - RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l8-l9"), - RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10"), - RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l11-l13"), - RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l12"), - RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l11-l13"), - RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14"), - RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l15"), - RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l5-l6-l16"), - RPMH_VREG("ldo17", LDO, 17, &pmic5_nldo, "vdd-l17"), - /* ldo18 not configured */ - RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo, "vdd-l19"), - RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo, "vdd-l20"), - RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo, "vdd-l21"), - {} -}; - -static const struct rpmh_vreg_init_data pmx75_vreg_data[] = { - RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"), - RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"), - RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"), - RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"), - RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"), - RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"), - RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps525, "vdd-s7"), - RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps525, "vdd-s8"), - RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps525, "vdd-s9"), - RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps525, "vdd-s10"), - RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"), - RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-18"), - RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"), - RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l4-l16"), - RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo_lv, "vdd-l5-l6"), - RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo_lv, "vdd-l5-l6"), - RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"), - RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo515, "vdd-l8-l9"), - RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo515, "vdd-l8-l9"), - RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10"), - RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l11-l13"), - RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo515, "vdd-l12"), - RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l11-l13"), - RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo515, "vdd-l14"), - RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo515, "vdd-l15"), - RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo515, "vdd-l4-l16"), - RPMH_VREG("ldo17", LDO, 17, &pmic5_nldo515, "vdd-l17"), - /* ldo18 not configured */ - RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo515, "vdd-l19"), - RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo515, "vdd-l20-l21"), - RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo515, "vdd-l20-l21"), -}; - -static const struct rpmh_vreg_init_data pm7325_vreg_data[] = { - RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps510, "vdd-s1"), - RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"), - RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps520, "vdd-s3"), - RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps520, "vdd-s4"), - RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps520, "vdd-s5"), - RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps520, "vdd-s6"), - RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps520, "vdd-s7"), - RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"), - RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l4-l12-l15"), - RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l7"), - RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"), - RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l1-l4-l12-l15"), - RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5"), - RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9-l10"), - RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l2-l7"), - RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8"), - RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9-l10"), - RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo, "vdd-l6-l9-l10"), - RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"), - RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l1-l4-l12-l15"), - RPMH_VREG("ldo13", LDO, 13, &pmic5_nldo, "vdd-l13"), - RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14-l16"), - RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l1-l4-l12-l15"), - RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo, "vdd-l14-l16"), - RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"), - RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"), - RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"), - {} -}; - -static const struct rpmh_vreg_init_data pm7550_vreg_data[] = { - RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"), - RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"), - RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"), - RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"), - RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"), - RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"), - RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"), - RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-l3"), - RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l2-l3"), - RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l4-l5"), - RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-l4-l5"), - RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6"), - RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"), - RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo515, "vdd-l8"), - RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo515, "vdd-l9-l10"), - RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo515, "vdd-l9-l10"), - RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo515, "vdd-l11"), - RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo515_mv, "vdd-l12-l14"), - RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo515_mv, "vdd-l13-l16"), - RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo, "vdd-l12-l14"), - RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), - RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l13-l16"), - RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), - RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), - RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), - RPMH_VREG("ldo20", LDO, 20, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), - RPMH_VREG("ldo21", LDO, 21, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), - RPMH_VREG("ldo22", LDO, 22, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), - RPMH_VREG("ldo23", LDO, 23, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), - RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"), - {} -}; - -static const struct rpmh_vreg_init_data pmr735a_vreg_data[] = { - RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps520, "vdd-s1"), - RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"), - RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps515, "vdd-s3"), - RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"), - RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"), - RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"), - RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"), - RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5-l6"), - RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l5-l6"), - RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-bob"), - {} -}; - -static const struct rpmh_vreg_init_data pmr735b_vreg_data[] = { - RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"), - RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"), - RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"), - RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"), - RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5"), - RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6"), - RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7-l8"), - RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l7-l8"), - RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l9"), - RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo_lv, "vdd-l10"), - RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo, "vdd-l11"), - RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l12"), - {} -}; - -static const struct rpmh_vreg_init_data pmr735d_vreg_data[] = { - RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1-l2-l5"), - RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l1-l2-l5"), - RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3-l4"), - RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l3-l4"), - RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-l1-l2-l5"), - RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6"), - RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"), {} }; From fd1bb0474997ed29d9e35dc047f60549dfdd82c9 Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Thu, 19 Mar 2026 09:54:05 +0530 Subject: [PATCH 0573/1330] FROMLIST: media: qcom: venus: drop extra padding in NV12 raw size calculation get_framesize_raw_nv12() currently adds SZ_4K to the UV plane size and an additional SZ_8K to the total buffer size. This inflates the calculated sizeimage and leads userspace to over-allocate buffers without a clear requirement. Remove the extra SZ_4K/SZ_8K padding and compute the NV12 size as the sum of Y and UV planes, keeping the final ALIGN(size, SZ_4K) intact. Link: https://lore.kernel.org/linux-arm-msm/20260331-fix_venus_bug_issue-v1-1-e4ae7a1d8db2@oss.qualcomm.com Fixes: e1cb72de702ad ("media: venus: helpers: move frame size calculations on common place") Signed-off-by: Renjiang Han (cherry picked from commit f970b24ef09185712135e88611b239fcf917885c) --- drivers/media/platform/qcom/venus/helpers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/venus/helpers.c b/drivers/media/platform/qcom/venus/helpers.c index 747c388fe25fa..59eee3dd9e06c 100644 --- a/drivers/media/platform/qcom/venus/helpers.c +++ b/drivers/media/platform/qcom/venus/helpers.c @@ -954,8 +954,8 @@ static u32 get_framesize_raw_nv12(u32 width, u32 height) uv_sclines = ALIGN(((height + 1) >> 1), 16); y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + SZ_4K; - size = y_plane + uv_plane + SZ_8K; + uv_plane = uv_stride * uv_sclines; + size = y_plane + uv_plane; return ALIGN(size, SZ_4K); } From 481f5a725c2888ef5f74bee8020af8d85072b458 Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Mon, 30 Mar 2026 16:47:59 +0530 Subject: [PATCH 0574/1330] FROMLIST: media: qcom: venus: relax encoder frame/blur dimension steps on v4 Encoder HFI capabilities on v4 advertise a 16-pixel step for frame and blur dimensions. This is overly restrictive and can cause userspace caps negotiation to fail even for valid resolutions. Relax the advertised step size to 1 and keep alignment enforcement in buffer layout and size calculations. Link: https://lore.kernel.org/linux-arm-msm/20260331-fix_venus_bug_issue-v1-2-e4ae7a1d8db2@oss.qualcomm.com Fixes: 8b88cabef404e ("media: venus: hfi_plat_v4: Populate codecs and capabilities for v4") Signed-off-by: Renjiang Han (cherry picked from commit af55d5ff55e4b184b42e382a2642f46a8f702d47) --- .../platform/qcom/venus/hfi_platform_v4.c | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/qcom/venus/hfi_platform_v4.c b/drivers/media/platform/qcom/venus/hfi_platform_v4.c index cda888b56b5d4..e0b3652bb4409 100644 --- a/drivers/media/platform/qcom/venus/hfi_platform_v4.c +++ b/drivers/media/platform/qcom/venus/hfi_platform_v4.c @@ -136,8 +136,8 @@ static const struct hfi_plat_caps caps[] = { .codec = HFI_VIDEO_CODEC_H264, .domain = VIDC_SESSION_TYPE_ENC, .cap_bufs_mode_dynamic = true, - .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, - .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, @@ -173,8 +173,8 @@ static const struct hfi_plat_caps caps[] = { .codec = HFI_VIDEO_CODEC_HEVC, .domain = VIDC_SESSION_TYPE_ENC, .cap_bufs_mode_dynamic = true, - .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, - .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, @@ -195,8 +195,8 @@ static const struct hfi_plat_caps caps[] = { .caps[19] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, .caps[20] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, .caps[21] = {HFI_CAPABILITY_ROTATION, 1, 4, 90}, - .caps[22] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 16}, - .caps[23] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 16}, + .caps[22] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 1}, + .caps[23] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 1}, .num_caps = 24, .pl[0] = {HFI_HEVC_PROFILE_MAIN, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, .pl[1] = {HFI_HEVC_PROFILE_MAIN10, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, @@ -210,8 +210,8 @@ static const struct hfi_plat_caps caps[] = { .codec = HFI_VIDEO_CODEC_VP8, .domain = VIDC_SESSION_TYPE_ENC, .cap_bufs_mode_dynamic = true, - .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, - .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, @@ -229,8 +229,8 @@ static const struct hfi_plat_caps caps[] = { .caps[16] = {HFI_CAPABILITY_P_FRAME_QP, 0, 127, 1}, .caps[17] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 2, 1}, .caps[18] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, - .caps[19] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 16}, - .caps[20] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 16}, + .caps[19] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 1}, + .caps[20] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 1}, .caps[21] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, .caps[22] = {HFI_CAPABILITY_ROTATION, 1, 4, 90}, .num_caps = 23, From dbaf2366dc64e25069264e208ea31d4649978bdb Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Mon, 30 Mar 2026 16:51:33 +0530 Subject: [PATCH 0575/1330] FROMLIST: media: qcom: venus: relax encoder frame/blur step size on v6 Encoder HFI capabilities on v6 enforce a 16-pixel step for frame and blur dimensions, which does not reflect actual hardware requirements and can reject valid userspace configurations. Relax the step size to 1 while leaving min/max limits unchanged. Link: https://lore.kernel.org/linux-arm-msm/20260331-fix_venus_bug_issue-v1-3-e4ae7a1d8db2@oss.qualcomm.com Fixes: 869d77e706290 ("media: venus: hfi_plat_v6: Populate capabilities for v6") Signed-off-by: Renjiang Han (cherry picked from commit bb5c223409459dff68e14606a508e9d5b4eb4871) --- .../media/platform/qcom/venus/hfi_platform_v6.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/venus/hfi_platform_v6.c b/drivers/media/platform/qcom/venus/hfi_platform_v6.c index d8568c08cc361..fb8d10ab34043 100644 --- a/drivers/media/platform/qcom/venus/hfi_platform_v6.c +++ b/drivers/media/platform/qcom/venus/hfi_platform_v6.c @@ -173,8 +173,8 @@ static const struct hfi_plat_caps caps[] = { .codec = HFI_VIDEO_CODEC_HEVC, .domain = VIDC_SESSION_TYPE_ENC, .cap_bufs_mode_dynamic = true, - .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 128, 8192, 16}, - .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 128, 8192, 16}, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 128, 8192, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 128, 8192, 1}, .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 64, 138240, 1}, .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 160000000, 1}, .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, @@ -195,8 +195,8 @@ static const struct hfi_plat_caps caps[] = { .caps[19] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, .caps[20] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, .caps[21] = {HFI_CAPABILITY_ROTATION, 1, 4, 90}, - .caps[22] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 16}, - .caps[23] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 16}, + .caps[22] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 1}, + .caps[23] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 1}, .num_caps = 24, .pl[0] = {HFI_HEVC_PROFILE_MAIN, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, .pl[1] = {HFI_HEVC_PROFILE_MAIN10, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, @@ -210,8 +210,8 @@ static const struct hfi_plat_caps caps[] = { .codec = HFI_VIDEO_CODEC_VP8, .domain = VIDC_SESSION_TYPE_ENC, .cap_bufs_mode_dynamic = true, - .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 128, 4096, 16}, - .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 128, 4096, 16}, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 128, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 128, 4096, 1}, .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 64, 36864, 1}, .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 74000000, 1}, .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, @@ -229,8 +229,8 @@ static const struct hfi_plat_caps caps[] = { .caps[16] = {HFI_CAPABILITY_P_FRAME_QP, 0, 127, 1}, .caps[17] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 2, 1}, .caps[18] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, - .caps[19] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 16}, - .caps[20] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 16}, + .caps[19] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 1}, + .caps[20] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 1}, .caps[21] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, .caps[22] = {HFI_CAPABILITY_ROTATION, 1, 4, 90}, .num_caps = 23, From 12a337f624ea17e4f068ff57ea1abb19f71db8fb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 Apr 2026 12:40:43 +0000 Subject: [PATCH 0576/1330] FROMLIST: media: qcom: venus: flip the venus/iris switch With the Iris and Venus driver having more or less feature parity for HFI 6xx platforms and with Iris gaining support for SC7280, flip the switch. Use Iris by default for SM8250 and SC7280, the platforms which are supported by both drivers, and use Venus only if Iris is not compiled at all. Use IS_ENABLED to strip out the code and data structures which are used by the disabled platforms. Link: https://lore.kernel.org/all/20260327-venus-iris-flip-switch-v5-4-2f4b6c636927@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Reviewed-by: Dikshita Agarwal (cherry picked from commit b74d927e14f99e6d1ab67fcecdd9fb687e26ac7b) --- drivers/media/platform/qcom/iris/Makefile | 5 +--- drivers/media/platform/qcom/iris/iris_probe.c | 2 -- drivers/media/platform/qcom/venus/core.c | 28 +++++++++++-------- drivers/media/platform/qcom/venus/core.h | 11 ++++++++ 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 2abbd3aeb4af0..2fde45f817276 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -10,6 +10,7 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ + iris_platform_gen1.o \ iris_platform_gen2.o \ iris_power.o \ iris_probe.o \ @@ -26,8 +27,4 @@ qcom-iris-objs += iris_buffer.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ -ifeq ($(CONFIG_VIDEO_QCOM_VENUS),) -qcom-iris-objs += iris_platform_gen1.o -endif - obj-$(CONFIG_VIDEO_QCOM_IRIS) += qcom-iris.o diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index a27a23b960bdf..fb5b31270c56a 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -356,7 +356,6 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, }, -#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_VENUS)) { .compatible = "qcom,sc7280-venus", .data = &sc7280_data, @@ -365,7 +364,6 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,sm8250-venus", .data = &sm8250_data, }, -#endif { .compatible = "qcom,sm8550-iris", .data = &sm8550_data, diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c index 25523c5a56915..64e6f87dbbe23 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -968,6 +968,7 @@ static const struct venus_resources sc7180_res = { .enc_nodename = "video-encoder", }; +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) static const struct freq_tbl sm8250_freq_table[] = { { 0, 444000000 }, { 0, 366000000 }, @@ -1126,6 +1127,7 @@ static const struct venus_resources sc7280_res = { .dec_nodename = "video-decoder", .enc_nodename = "video-encoder", }; +#endif static const struct bw_tbl qcm2290_bw_table_dec[] = { { 352800, 597000, 0, 746000, 0 }, /* 1080p@30 + 720p@30 */ @@ -1221,18 +1223,20 @@ static const struct venus_resources sc8280xp_res = { static const struct of_device_id venus_dt_match[] = { - { .compatible = "qcom,msm8916-venus", .data = &msm8916_res }, - { .compatible = "qcom,msm8996-venus", .data = &msm8996_res }, - { .compatible = "qcom,msm8998-venus", .data = &msm8998_res }, - { .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res }, - { .compatible = "qcom,sc7180-venus", .data = &sc7180_res }, - { .compatible = "qcom,sc7280-venus", .data = &sc7280_res }, - { .compatible = "qcom,sc8280xp-venus", .data = &sc8280xp_res }, - { .compatible = "qcom,sdm660-venus", .data = &sdm660_res }, - { .compatible = "qcom,sdm845-venus", .data = &sdm845_res }, - { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2 }, - { .compatible = "qcom,sm8250-venus", .data = &sm8250_res }, - { .compatible = "qcom,sm8350-venus", .data = &sm8350_res }, + { .compatible = "qcom,msm8916-venus", .data = &msm8916_res, }, + { .compatible = "qcom,msm8996-venus", .data = &msm8996_res, }, + { .compatible = "qcom,msm8998-venus", .data = &msm8998_res, }, + { .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res, }, + { .compatible = "qcom,sc7180-venus", .data = &sc7180_res, }, +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) + { .compatible = "qcom,sc7280-venus", .data = &sc7280_res, }, +#endif + { .compatible = "qcom,sdm660-venus", .data = &sdm660_res, }, + { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, }, + { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2, }, +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) + { .compatible = "qcom,sm8250-venus", .data = &sm8250_res, }, +#endif { } }; MODULE_DEVICE_TABLE(of, venus_dt_match); diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index bd89a5d58baf8..a3a6cb4cc37bf 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -55,8 +55,10 @@ enum vpu_version { VPU_VERSION_AR50, VPU_VERSION_AR50_LITE, VPU_VERSION_IRIS1, +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) VPU_VERSION_IRIS2, VPU_VERSION_IRIS2_1, +#endif }; struct firmware_version { @@ -529,13 +531,22 @@ struct venus_inst { #define IS_V1(core) ((core)->res->hfi_version == HFI_VERSION_1XX) #define IS_V3(core) ((core)->res->hfi_version == HFI_VERSION_3XX) #define IS_V4(core) ((core)->res->hfi_version == HFI_VERSION_4XX) +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) #define IS_V6(core) ((core)->res->hfi_version == HFI_VERSION_6XX) +#else +#define IS_V6(core) (0) +#endif #define IS_AR50(core) ((core)->res->vpu_version == VPU_VERSION_AR50) #define IS_AR50_LITE(core) ((core)->res->vpu_version == VPU_VERSION_AR50_LITE) #define IS_IRIS1(core) ((core)->res->vpu_version == VPU_VERSION_IRIS1) +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) #define IS_IRIS2(core) ((core)->res->vpu_version == VPU_VERSION_IRIS2) #define IS_IRIS2_1(core) ((core)->res->vpu_version == VPU_VERSION_IRIS2_1) +#else +#define IS_IRIS2(core) (0) +#define IS_IRIS2_1(core) (0) +#endif static inline bool is_lite(struct venus_core *core) { From f885aea3f3860bd0cda996681542d0e971d18c80 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Fri, 3 Apr 2026 16:03:42 +0530 Subject: [PATCH 0577/1330] FROMLIST: media: iris: add FPS calculation and VPP FW overhead in frequency formula The driver was using a fixed default FPS value when calculating the VPU frequency. This caused wrong frequency requests for high-frame-rate streams, for example 4K at 240 FPS. Because of this, the hardware was running at a lower frequency than needed. Add the FPS measurement based on the decoder input buffer arrival rate. The measured FPS is stored per instance and used in frequency calculation instead of the fixed default FPS. The value is clamped so that it does not exceed platform limits. Add a VPP firmware overhead when running in STAGE_2. Link: https://lore.kernel.org/all/20260401-update_fps_calculation-v6-1-f44f8154ca39@oss.qualcomm.com/ Reviewed-by: Vikash Garodia Signed-off-by: Vishnu Reddy (cherry picked from commit f323616c9d818e6149da5a46a8dfe80383fba2f0) --- .../media/platform/qcom/iris/iris_instance.h | 4 ++++ drivers/media/platform/qcom/iris/iris_vdec.c | 20 +++++++++++++++++++ drivers/media/platform/qcom/iris/iris_vpu2.c | 2 +- .../platform/qcom/iris/iris_vpu_common.c | 6 +++++- 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h index 16965150f427b..63dd889c9992a 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -67,6 +67,8 @@ struct iris_fmt { * @metadata_idx: index for metadata buffer * @codec: codec type * @last_buffer_dequeued: a flag to indicate that last buffer is sent by driver + * @last_buf_ns: start time of received input buffer for current one second FPS window + * @frame_counter: input buffer counter for current one second FPS window * @frame_rate: frame rate of current instance * @operating_rate: operating rate of current instance * @hfi_rc_type: rate control type @@ -109,6 +111,8 @@ struct iris_inst { u32 metadata_idx; u32 codec; bool last_buffer_dequeued; + u64 last_buf_ns; + u32 frame_counter; u32 frame_rate; u32 operating_rate; u32 hfi_rc_type; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index 99d544e2af4f9..fa4dc09ba26ee 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -54,6 +54,7 @@ int iris_vdec_inst_init(struct iris_inst *inst) f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT); inst->buffers[BUF_OUTPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage; + inst->frame_rate = MAXIMUM_FPS; memcpy(&inst->fw_caps[0], &core->inst_fw_caps_dec[0], INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap)); @@ -363,6 +364,8 @@ int iris_vdec_streamon_input(struct iris_inst *inst) if (ret) return ret; + inst->frame_counter = 0; + return iris_process_streamon_input(inst); } @@ -405,6 +408,7 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) { struct iris_buffer *buf = to_iris_buffer(vbuf); struct vb2_buffer *vb2 = &vbuf->vb2_buf; + u64 cur_buf_ns, delta_ns; struct vb2_queue *q; int ret; @@ -421,6 +425,22 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) return 0; } + if (buf->type == BUF_INPUT) { + cur_buf_ns = ktime_get_ns(); + + if (!inst->frame_counter) + inst->last_buf_ns = cur_buf_ns; + + inst->frame_counter++; + delta_ns = cur_buf_ns - inst->last_buf_ns; + + if (delta_ns >= NSEC_PER_SEC) { + inst->frame_rate = clamp_t(u32, inst->frame_counter, DEFAULT_FPS, + MAXIMUM_FPS); + inst->frame_counter = 0; + } + } + iris_scale_power(inst); return iris_queue_buffer(inst, buf); diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c index 01ef40f389574..b8714dcbad10a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -18,7 +18,7 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) struct v4l2_format *inp_f = inst->fmt_src; u32 mbs_per_second, mbpf, height, width; unsigned long vpp_freq, vsp_freq; - u32 fps = DEFAULT_FPS; + u32 fps = inst->frame_rate; width = max(inp_f->fmt.pix_mp.width, inst->crop.width); height = max(inp_f->fmt.pix_mp.height, inst->crop.height); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 69e6126dc4d95..3e3482d1841d2 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -420,7 +420,7 @@ u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_siz u32 height, width, mbs_per_second, mbpf; u64 fw_cycles, fw_vpp_cycles; u64 vsp_cycles, vpp_cycles; - u32 fps = DEFAULT_FPS; + u32 fps = inst->frame_rate; width = max(inp_f->fmt.pix_mp.width, inst->crop.width); height = max(inp_f->fmt.pix_mp.height, inst->crop.height); @@ -439,6 +439,10 @@ u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_siz if (inst->fw_caps[PIPE].value > 1) vpp_cycles += div_u64(vpp_cycles * 59, 1000); + /* 1.05 is VPP FW overhead */ + if (inst->fw_caps[STAGE].value == STAGE_2) + vpp_cycles += mult_frac(vpp_cycles, 5, 100); + vsp_cycles = fps * data_size * 8; vsp_cycles = div_u64(vsp_cycles, 2); /* VSP FW overhead 1.05 */ From e7fdcf42ea961a11b5258f8d8cc3fe7f3a84f07e Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 10 Apr 2026 14:15:20 +0800 Subject: [PATCH 0578/1330] QCLINUX: qcom-dcc: add logic to configure linked list in probe Configure the linked list with defined register entries in dcc_probe. Signed-off-by: Jie Gan (cherry picked from commit b443c9635c8c61d7a660dbd69c8e81eeeb3b6362) --- drivers/misc/qcom-dcc-dev.c | 38 +++++++++++++++++++++ drivers/misc/qcom-dcc.c | 67 +++++++++++++++++++++++++++++++++++++ drivers/misc/qcom-dcc.h | 16 +++++++++ 3 files changed, 121 insertions(+) diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index 5da18b4d221dd..52571a2a6228e 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -12,6 +12,24 @@ static struct platform_device *dcc_pdev; +static const struct dcc_register_entry talos_dcc_entries[] = { + { "R 0x3d96000" }, + { "R 0x3d96004" }, +}; + +static const struct dcc_link_config talos_link_configs[] = { + { + .link_list = 3, + .entries = talos_dcc_entries, + .num_entries = ARRAY_SIZE(talos_dcc_entries), + }, +}; + +static const struct dcc_config talos_config = { + .lists = talos_link_configs, + .num_lists = ARRAY_SIZE(talos_link_configs), +}; + static const struct dcc_pdata talos_pdata = { .base = 0x010a2000, .size = 0x00001000, @@ -19,6 +37,25 @@ static const struct dcc_pdata talos_pdata = { .ram_size = 0x00002000, .dcc_offset = 0x6000, .map_ver = 0x1, + .config = &talos_config, +}; + +static const struct dcc_register_entry lemans_dcc_entries[] = { + { "R 0x610110 1" }, + { "R 0x9050008 1" }, +}; + +static const struct dcc_link_config lemans_link_configs[] = { + { + .link_list = 6, + .entries = lemans_dcc_entries, + .num_entries = ARRAY_SIZE(lemans_dcc_entries), + }, +}; + +static const struct dcc_config lemans_config = { + .lists = lemans_link_configs, + .num_lists = ARRAY_SIZE(lemans_link_configs), }; static const struct dcc_pdata lemans_pdata = { @@ -28,6 +65,7 @@ static const struct dcc_pdata lemans_pdata = { .ram_size = 0x00006000, .dcc_offset = 0x38800, .map_ver = 0x3, + .config = &lemans_config, }; static const struct dcc_pdata kodiak_pdata = { diff --git a/drivers/misc/qcom-dcc.c b/drivers/misc/qcom-dcc.c index e75f98b90d8f7..d38c5f4a680b6 100644 --- a/drivers/misc/qcom-dcc.c +++ b/drivers/misc/qcom-dcc.c @@ -1425,6 +1425,72 @@ static ssize_t dcc_sram_read(struct file *file, char __user *data, return len; } +static void dcc_configure_list(struct dcc_drvdata *drvdata, + const struct dcc_config *config) +{ + const struct dcc_link_config *link; + const struct dcc_register_entry *entry; + char *token, *bufp, *buf_orig; + char *delim = " "; + int ret, i, j, configured; + size_t len; + + if (!config || !config->num_lists) + return; + + for (i = 0; i < config->num_lists; i++) { + link = &config->lists[i]; + + if (link->link_list >= drvdata->max_link_list) { + dev_err(drvdata->dev, "Invalid link list index %d\n", link->link_list); + continue; + } + + configured = 0; + + for (j = 0; j < link->num_entries; j++) { + entry = &link->entries[j]; + + len = strlen(entry->config); + buf_orig = kzalloc(len + 1, GFP_KERNEL); + if (!buf_orig) + return; + + strscpy(buf_orig, entry->config, len + 1); + bufp = buf_orig; + + token = strsep(&bufp, delim); + if (!bufp) { + dev_err(drvdata->dev, "Malformed entry: \"%s\"\n", + entry->config); + kfree(buf_orig); + continue; + } + + if (!strcmp("R", token)) { + ret = dcc_config_add_read(drvdata, bufp, link->link_list); + } else if (!strcmp("W", token)) { + ret = dcc_config_add_write(drvdata, bufp, link->link_list); + } else if (!strcmp("RW", token)) { + ret = dcc_config_add_read_write(drvdata, bufp, link->link_list); + } else if (!strcmp("L", token)) { + ret = dcc_config_add_loop(drvdata, bufp, link->link_list); + } else { + dev_err(drvdata->dev, "%s is not a correct input\n", token); + ret = -EINVAL; + } + + if (ret >= 0) + configured++; + + kfree(buf_orig); + } + + if (configured) + dcc_enable(drvdata, link->link_list); + } +} + static const struct file_operations dcc_sram_fops = { .owner = THIS_MODULE, .read = dcc_sram_read, @@ -1520,6 +1586,7 @@ static int dcc_probe(struct platform_device *pdev) } dcc_create_debug_dir(drvdata); + dcc_configure_list(drvdata, pdata->config); return 0; } diff --git a/drivers/misc/qcom-dcc.h b/drivers/misc/qcom-dcc.h index 513c95dc742b5..ce8551141062d 100644 --- a/drivers/misc/qcom-dcc.h +++ b/drivers/misc/qcom-dcc.h @@ -8,6 +8,21 @@ #include +struct dcc_register_entry { + const char *config; +}; + +struct dcc_link_config { + int link_list; + const struct dcc_register_entry *entries; + int num_entries; +}; + +struct dcc_config { + const struct dcc_link_config *lists; + int num_lists; +}; + struct dcc_pdata { phys_addr_t base; resource_size_t size; @@ -15,6 +30,7 @@ struct dcc_pdata { resource_size_t ram_size; u32 dcc_offset; u8 map_ver; + const struct dcc_config *config; }; #endif From 0d9e62d69b24ffd256bf845d1aae37606cfa043b Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 10 Apr 2026 14:15:33 +0800 Subject: [PATCH 0579/1330] QCLINUX: qcom-dcc: add register list for the Talos Add the registers for configuring the linked_list of the DCC driver for debugging purpose. Signed-off-by: Jie Gan (cherry picked from commit 3a4648d380fc3d5f2a0396cce16714235705fb85) --- drivers/misc/qcom-dcc-dev.c | 753 ++++++++++++++++++++++++++++++++++++ 1 file changed, 753 insertions(+) diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index 52571a2a6228e..7656e8e90aa1c 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -13,6 +13,759 @@ static struct platform_device *dcc_pdev; static const struct dcc_register_entry talos_dcc_entries[] = { + { "R 0x9680000" }, + { "R 0x9680004" }, + { "R 0x9681000" }, + { "R 0x9681004" }, + { "R 0x9681008" }, + { "R 0x968100c" }, + { "R 0x9681010" }, + { "R 0x9681014" }, + { "R 0x968101c" }, + { "R 0x9681020" }, + { "R 0x9681024" }, + { "R 0x9681028" }, + { "R 0x968102c" }, + { "R 0x9681030" }, + { "R 0x9681034" }, + { "R 0x968103c" }, + { "R 0x9698100" }, + { "R 0x9698104" }, + { "R 0x9698108" }, + { "R 0x9698110" }, + { "R 0x9698120" }, + { "R 0x9698124" }, + { "R 0x9698128" }, + { "R 0x969812c" }, + { "R 0x9698130" }, + { "R 0x9698134" }, + { "R 0x9698138" }, + { "R 0x969813c" }, + { "R 0x9698500" }, + { "R 0x9698504" }, + { "R 0x9698508" }, + { "R 0x969850c" }, + { "R 0x9698510" }, + { "R 0x9698514" }, + { "R 0x9698518" }, + { "R 0x969851c" }, + { "R 0x9698700" }, + { "R 0x9698704" }, + { "R 0x9698708" }, + { "R 0x969870c" }, + { "R 0x9698714" }, + { "R 0x9698718" }, + { "R 0x969871c" }, + { "R 0x1620204" }, + { "R 0x1620240" }, + { "R 0x1620248" }, + { "R 0x1620288" }, + { "R 0x162028C" }, + { "R 0x1620290" }, + { "R 0x1620294" }, + { "R 0x16202A8" }, + { "R 0x16202AC" }, + { "R 0x16202B0" }, + { "R 0x16202B4" }, + { "R 0x1620300" }, + { "R 0x1700204" }, + { "R 0x1700240" }, + { "R 0x1700248" }, + { "R 0x1700288" }, + { "R 0x1700290" }, + { "R 0x1700300" }, + { "R 0x1700304" }, + { "R 0x1700308" }, + { "R 0x170030C" }, + { "R 0x1700310" }, + { "R 0x1700314" }, + { "R 0x1700C08" }, + { "R 0x1700C10" }, + { "R 0x1700C20" }, + { "R 0x1700C24" }, + { "R 0x1700C28" }, + { "R 0x1700C2C" }, + { "R 0x1700C30" }, + { "R 0x1700C34" }, + { "R 0x1700C38" }, + { "R 0x1700C3C" }, + { "R 0x1740240" }, + { "R 0x1740248" }, + { "R 0x1740288" }, + { "R 0x1740290" }, + { "R 0x1740300" }, + { "R 0x1740304" }, + { "R 0x1740308" }, + { "R 0x174030C" }, + { "R 0x1740310" }, + { "R 0x1740314" }, + { "R 0x1740004" }, + { "R 0x1740008" }, + { "R 0x1740010" }, + { "R 0x1740020" }, + { "R 0x1740024" }, + { "R 0x1740028" }, + { "R 0x174002C" }, + { "R 0x1740030" }, + { "R 0x1740034" }, + { "R 0x1740038" }, + { "R 0x174003C" }, + { "R 0x9698204" }, + { "R 0x9698240" }, + { "R 0x9698244" }, + { "R 0x9698248" }, + { "R 0x969824C" }, + { "R 0x9681010" }, + { "R 0x9681014" }, + { "R 0x9681018" }, + { "R 0x968101C" }, + { "R 0x9681020" }, + { "R 0x9681024" }, + { "R 0x9681028" }, + { "R 0x968102C" }, + { "R 0x9681030" }, + { "R 0x9681034" }, + { "R 0x968103C" }, + { "R 0x9698100" }, + { "R 0x9698104" }, + { "R 0x9698108" }, + { "R 0x9698110" }, + { "R 0x9698120" }, + { "R 0x9698124" }, + { "R 0x9698128" }, + { "R 0x969812C" }, + { "R 0x9698130" }, + { "R 0x9698134" }, + { "R 0x9698138" }, + { "R 0x969813C" }, + { "R 0x62BE2004" }, + { "R 0x62BE2040" }, + { "R 0x62BE2048" }, + { "R 0x62BE2088" }, + { "R 0x62BE2090" }, + { "R 0x62BE2100" }, + { "R 0x62BE2104" }, + { "R 0x62BE2108" }, + { "R 0x62BE210C" }, + { "R 0x62BE2110" }, + { "R 0x62BE2114" }, + { "R 0x62BE2118" }, + { "R 0x62BE0010" }, + { "R 0x62BE0020" }, + { "R 0x62BE0024" }, + { "R 0x62BE0028" }, + { "R 0x62BE002C" }, + { "R 0x62BE0030" }, + { "R 0x62BE0034" }, + { "R 0x62BE0038" }, + { "R 0x62BE003C" }, + { "R 0x9160204" }, + { "R 0x9160240" }, + { "R 0x9160248" }, + { "R 0x9160288" }, + { "R 0x9160290" }, + { "R 0x9160300" }, + { "R 0x9160304" }, + { "R 0x9160308" }, + { "R 0x916030C" }, + { "R 0x9160310" }, + { "R 0x9160314" }, + { "R 0x9160318" }, + { "R 0x9160008" }, + { "R 0x9160010" }, + { "R 0x9160020" }, + { "R 0x9160024" }, + { "R 0x9160028" }, + { "R 0x916002C" }, + { "R 0x9160030" }, + { "R 0x9160034" }, + { "R 0x9160038" }, + { "R 0x916003C" }, + { "R 0x1620500 4" }, + { "R 0x1620700 4" }, + { "R 0x1620300" }, + { "R 0x1620F00 2" }, + { "R 0x1620B00 2" }, + { "R 0x1700B00 2" }, + { "R 0x1700700 3" }, + { "R 0x9163100" }, + { "R 0x96AA100" }, + { "R 0x9050008" }, + { "R 0x9050068" }, + { "R 0x9050078" }, + { "R 0x18200400" }, + { "R 0x18200404" }, + { "R 0x18200408" }, + { "R 0x18200038" }, + { "R 0x18200040" }, + { "R 0x18200048" }, + { "R 0x18220038" }, + { "R 0x18220040" }, + { "R 0x182200D0" }, + { "R 0x18200030" }, + { "R 0x18200010" }, + { "R 0x1822000c" }, + { "R 0x18220d14" }, + { "R 0x18220fb4" }, + { "R 0x18221254" }, + { "R 0x182214f4" }, + { "R 0x18221794" }, + { "R 0x18221a34" }, + { "R 0x18221cd4" }, + { "R 0x18221f74" }, + { "R 0x18220d18" }, + { "R 0x18220fb8" }, + { "R 0x18221258" }, + { "R 0x182214f8" }, + { "R 0x18221798" }, + { "R 0x18221a38" }, + { "R 0x18221cd8" }, + { "R 0x18221f78" }, + { "R 0x18220d00" }, + { "R 0x18220d04" }, + { "R 0x18220d1c" }, + { "R 0x18220fbc" }, + { "R 0x1822125c" }, + { "R 0x182214fc" }, + { "R 0x1822179c" }, + { "R 0x18221a3c" }, + { "R 0x18221cdc" }, + { "R 0x18221f7c" }, + { "R 0x18221274" }, + { "R 0x18221288" }, + { "R 0x1822129c" }, + { "R 0x182212b0" }, + { "R 0x182212c4" }, + { "R 0x182212d8" }, + { "R 0x182212ec" }, + { "R 0x18221300" }, + { "R 0x18221314" }, + { "R 0x18221328" }, + { "R 0x1822133c" }, + { "R 0x18221350" }, + { "R 0x18221364" }, + { "R 0x18221378" }, + { "R 0x1822138c" }, + { "R 0x182213a0" }, + { "R 0x18221514" }, + { "R 0x18221528" }, + { "R 0x1822153c" }, + { "R 0x18221550" }, + { "R 0x18221564" }, + { "R 0x18221578" }, + { "R 0x1822158c" }, + { "R 0x182215a0" }, + { "R 0x182215b4" }, + { "R 0x182215c8" }, + { "R 0x182215dc" }, + { "R 0x182215f0" }, + { "R 0x18221604" }, + { "R 0x18221618" }, + { "R 0x1822162c" }, + { "R 0x18221640" }, + { "R 0x182217b4" }, + { "R 0x182217c8" }, + { "R 0x182217dc" }, + { "R 0x182217f0" }, + { "R 0x18221804" }, + { "R 0x18221818" }, + { "R 0x1822182c" }, + { "R 0x18221840" }, + { "R 0x18221854" }, + { "R 0x18221868" }, + { "R 0x1822187c" }, + { "R 0x18221890" }, + { "R 0x182218a4" }, + { "R 0x182218b8" }, + { "R 0x182218cc" }, + { "R 0x182218e0" }, + { "R 0x18221a54" }, + { "R 0x18221a68" }, + { "R 0x18221a7c" }, + { "R 0x18221a90" }, + { "R 0x18221aa4" }, + { "R 0x18221ab8" }, + { "R 0x18221acc" }, + { "R 0x18221ae0" }, + { "R 0x18221af4" }, + { "R 0x18221b08" }, + { "R 0x18221b1c" }, + { "R 0x18221b30" }, + { "R 0x18221b44" }, + { "R 0x18221b58" }, + { "R 0x18221b6c" }, + { "R 0x18221b80" }, + { "R 0x18221cf4" }, + { "R 0x18221d08" }, + { "R 0x18221d1c" }, + { "R 0x18221d30" }, + { "R 0x18221d44" }, + { "R 0x18221d58" }, + { "R 0x18221d6c" }, + { "R 0x18221d80" }, + { "R 0x18221d94" }, + { "R 0x18221da8" }, + { "R 0x18221dbc" }, + { "R 0x18221dd0" }, + { "R 0x18221de4" }, + { "R 0x18221df8" }, + { "R 0x18221e0c" }, + { "R 0x18221e20" }, + { "R 0x18221f94" }, + { "R 0x18221fa8" }, + { "R 0x18221fbc" }, + { "R 0x18221fd0" }, + { "R 0x18221fe4" }, + { "R 0x18221ff8" }, + { "R 0x1822200c" }, + { "R 0x18222020" }, + { "R 0x18222034" }, + { "R 0x18222048" }, + { "R 0x1822205c" }, + { "R 0x18222070" }, + { "R 0x18222084" }, + { "R 0x18222098" }, + { "R 0x182220ac" }, + { "R 0x182220c0" }, + { "R 0x18221278" }, + { "R 0x1822128c" }, + { "R 0x182212a0" }, + { "R 0x182212b4" }, + { "R 0x182212c8" }, + { "R 0x182212dc" }, + { "R 0x182212f0" }, + { "R 0x18221304" }, + { "R 0x18221318" }, + { "R 0x1822132c" }, + { "R 0x18221340" }, + { "R 0x18221354" }, + { "R 0x18221368" }, + { "R 0x1822137c" }, + { "R 0x18221390" }, + { "R 0x182213a4" }, + { "R 0x18221518" }, + { "R 0x1822152c" }, + { "R 0x18221540" }, + { "R 0x18221554" }, + { "R 0x18221568" }, + { "R 0x1822157c" }, + { "R 0x18221590" }, + { "R 0x182215a4" }, + { "R 0x182215b8" }, + { "R 0x182215cc" }, + { "R 0x182215e0" }, + { "R 0x182215f4" }, + { "R 0x18221608" }, + { "R 0x1822161c" }, + { "R 0x18221630" }, + { "R 0x18221644" }, + { "R 0x182217b8" }, + { "R 0x182217cc" }, + { "R 0x182217e0" }, + { "R 0x182217f4" }, + { "R 0x18221808" }, + { "R 0x1822181c" }, + { "R 0x18221830" }, + { "R 0x18221844" }, + { "R 0x18221858" }, + { "R 0x1822186c" }, + { "R 0x18221880" }, + { "R 0x18221894" }, + { "R 0x182218a8" }, + { "R 0x182218bc" }, + { "R 0x182218d0" }, + { "R 0x182218e4" }, + { "R 0x18221a58" }, + { "R 0x18221a6c" }, + { "R 0x18221a80" }, + { "R 0x18221a94" }, + { "R 0x18221aa8" }, + { "R 0x18221abc" }, + { "R 0x18221ad0" }, + { "R 0x18221ae4" }, + { "R 0x18221af8" }, + { "R 0x18221b0c" }, + { "R 0x18221b20" }, + { "R 0x18221b34" }, + { "R 0x18221b48" }, + { "R 0x18221b5c" }, + { "R 0x18221b70" }, + { "R 0x18221b84" }, + { "R 0x18221cf8" }, + { "R 0x18221d0c" }, + { "R 0x18221d20" }, + { "R 0x18221d34" }, + { "R 0x18221d48" }, + { "R 0x18221d5c" }, + { "R 0x18221d70" }, + { "R 0x18221d84" }, + { "R 0x18221d98" }, + { "R 0x18221dac" }, + { "R 0x18221dc0" }, + { "R 0x18221dd4" }, + { "R 0x18221de8" }, + { "R 0x18221dfc" }, + { "R 0x18221e10" }, + { "R 0x18221e24" }, + { "R 0x18221f98" }, + { "R 0x18221fac" }, + { "R 0x18221fc0" }, + { "R 0x18221fd4" }, + { "R 0x18221fe8" }, + { "R 0x18221ffc" }, + { "R 0x18222010" }, + { "R 0x18222024" }, + { "R 0x18222038" }, + { "R 0x1822204c" }, + { "R 0x18222060" }, + { "R 0x18222074" }, + { "R 0x18222088" }, + { "R 0x1822209c" }, + { "R 0x182220b0" }, + { "R 0x182220c4" }, + { "R 0x18000024" }, + { "R 0x18000040" }, + { "R 0x18010024" }, + { "R 0x18010040" }, + { "R 0x18020024" }, + { "R 0x18020040" }, + { "R 0x18030024" }, + { "R 0x18030040" }, + { "R 0x18040024" }, + { "R 0x18040040" }, + { "R 0x18050024" }, + { "R 0x18050040" }, + { "R 0x18060024" }, + { "R 0x18060040" }, + { "R 0x18070024" }, + { "R 0x18070040" }, + { "R 0x18080024" }, + { "R 0x18080040" }, + { "R 0x180800F8" }, + { "R 0x18080104" }, + { "R 0x1808011C" }, + { "R 0x18080128" }, + { "R 0x90b0280" }, + { "R 0x90b0288" }, + { "R 0x90b028c" }, + { "R 0x90b0290" }, + { "R 0x90b0294" }, + { "R 0x90b0298" }, + { "R 0x90b029c" }, + { "R 0x90b02a0" }, + { "R 0x18321700" }, + { "R 0x18322C18" }, + { "R 0x18323700" }, + { "R 0x18324C18" }, + { "R 0x18325F00" }, + { "R 0x18327418" }, + { "R 0x9236028" }, + { "R 0x923602C" }, + { "R 0x9236030" }, + { "R 0x9236034" }, + { "R 0x9236038" }, + { "R 0x9232100" }, + { "R 0x92360b0" }, + { "R 0x9236044" }, + { "R 0x9236048" }, + { "R 0x923604c" }, + { "R 0x9236050" }, + { "R 0x923e030" }, + { "R 0x923e034" }, + { "R 0x9241000" }, + { "R 0x9248058" }, + { "R 0x924805c" }, + { "R 0x9248060" }, + { "R 0x9248064" }, + { "R 0x9260410" }, + { "R 0x92e0410" }, + { "R 0x9260414" }, + { "R 0x92e0414" }, + { "R 0x9260418" }, + { "R 0x92e0418" }, + { "R 0x9260420" }, + { "R 0x9260424" }, + { "R 0x9260430" }, + { "R 0x9260440" }, + { "R 0x9260448" }, + { "R 0x92604a0" }, + { "R 0x92e0420" }, + { "R 0x92e0424" }, + { "R 0x92e0430" }, + { "R 0x92e0440" }, + { "R 0x92e0448" }, + { "R 0x92e04a0" }, + { "R 0x9600000" }, + { "R 0x9601000" }, + { "R 0x9602000" }, + { "R 0x9603000" }, + { "R 0x9604000" }, + { "R 0x9605000" }, + { "R 0x9606000" }, + { "R 0x9607000" }, + { "R 0x9608000" }, + { "R 0x9609000" }, + { "R 0x960a000" }, + { "R 0x960b000" }, + { "R 0x960c000" }, + { "R 0x960d000" }, + { "R 0x960e000" }, + { "R 0x960f000" }, + { "R 0x9610000" }, + { "R 0x9611000" }, + { "R 0x9612000" }, + { "R 0x9613000" }, + { "R 0x9614000" }, + { "R 0x9615000" }, + { "R 0x9616000" }, + { "R 0x9617000" }, + { "R 0x9618000" }, + { "R 0x9619000" }, + { "R 0x961a000" }, + { "R 0x961b000" }, + { "R 0x961c000" }, + { "R 0x961d000" }, + { "R 0x961e000" }, + { "R 0x961f000" }, + { "R 0x9600004" }, + { "R 0x9601004" }, + { "R 0x9602004" }, + { "R 0x9603004" }, + { "R 0x9604004" }, + { "R 0x9605004" }, + { "R 0x9606004" }, + { "R 0x9607004" }, + { "R 0x9608004" }, + { "R 0x9609004" }, + { "R 0x960a004" }, + { "R 0x960b004" }, + { "R 0x960c004" }, + { "R 0x960d004" }, + { "R 0x960e004" }, + { "R 0x960f004" }, + { "R 0x9610004" }, + { "R 0x9611004" }, + { "R 0x9612004" }, + { "R 0x9613004" }, + { "R 0x9614004" }, + { "R 0x9615004" }, + { "R 0x9616004" }, + { "R 0x9617004" }, + { "R 0x9618004" }, + { "R 0x9619004" }, + { "R 0x961a004" }, + { "R 0x961b004" }, + { "R 0x961c004" }, + { "R 0x961d004" }, + { "R 0x961e004" }, + { "R 0x961f004" }, + { "R 0x9266418" }, + { "R 0x92e6418" }, + { "R 0x9265804" }, + { "R 0x92e5804" }, + { "R 0x92604b8" }, + { "R 0x92e04b8" }, + { "R 0x0C201244 1" }, + { "R 0x0C202244 1" }, + { "R 0x18100C18 1" }, + { "R 0x18101C18 1" }, + { "R 0x18300000 1" }, + { "R 0x183A3A84 2" }, + { "R 0x18393A84 2" }, + { "R 0x00100000" }, + { "R 0x00100004" }, + { "R 0x00100008" }, + { "R 0x0010000C" }, + { "R 0x00100010" }, + { "R 0x00100014" }, + { "R 0x00100018" }, + { "R 0x0010001C" }, + { "R 0x00100020" }, + { "R 0x00100024" }, + { "R 0x00100028" }, + { "R 0x0010002C" }, + { "R 0x00100030" }, + { "R 0x00100034" }, + { "R 0x00100100" }, + { "R 0x00100104" }, + { "R 0x00100108" }, + { "R 0x0010010C" }, + { "R 0x00101000" }, + { "R 0x00101004" }, + { "R 0x00101008" }, + { "R 0x0010100C" }, + { "R 0x00101010" }, + { "R 0x00101014" }, + { "R 0x00101018" }, + { "R 0x0010101C" }, + { "R 0x00101020" }, + { "R 0x00101024" }, + { "R 0x00101028" }, + { "R 0x0010102C" }, + { "R 0x00101030" }, + { "R 0x00101034" }, + { "R 0x00102000" }, + { "R 0x00102004" }, + { "R 0x00102008" }, + { "R 0x0010200C" }, + { "R 0x00102010" }, + { "R 0x00102014" }, + { "R 0x00102018" }, + { "R 0x0010201C" }, + { "R 0x00102020" }, + { "R 0x00102024" }, + { "R 0x00102028" }, + { "R 0x0010202C" }, + { "R 0x00102030" }, + { "R 0x00102034" }, + { "R 0x00103000" }, + { "R 0x00103004" }, + { "R 0x00103008" }, + { "R 0x0010300C" }, + { "R 0x00103010" }, + { "R 0x00103014" }, + { "R 0x00103018" }, + { "R 0x0010301C" }, + { "R 0x00103020" }, + { "R 0x00103024" }, + { "R 0x00103028" }, + { "R 0x0010302C" }, + { "R 0x00103030" }, + { "R 0x00103034" }, + { "R 0x00113000" }, + { "R 0x00113004" }, + { "R 0x00113008" }, + { "R 0x0011300C" }, + { "R 0x00113010" }, + { "R 0x00113014" }, + { "R 0x00113018" }, + { "R 0x0011301C" }, + { "R 0x00113020" }, + { "R 0x00113024" }, + { "R 0x00113028" }, + { "R 0x0011302C" }, + { "R 0x00113030" }, + { "R 0x00113034" }, + { "R 0x0011A000" }, + { "R 0x0011A004" }, + { "R 0x0011A008" }, + { "R 0x0011A00C" }, + { "R 0x0011A010" }, + { "R 0x0011A014" }, + { "R 0x0011A018" }, + { "R 0x0011A01C" }, + { "R 0x0011A020" }, + { "R 0x0011A024" }, + { "R 0x0011A028" }, + { "R 0x0011A02C" }, + { "R 0x0011A030" }, + { "R 0x0011A034" }, + { "R 0x0011B000" }, + { "R 0x0011B004" }, + { "R 0x0011B008" }, + { "R 0x0011B00C" }, + { "R 0x0011B010" }, + { "R 0x0011B014" }, + { "R 0x0011B018" }, + { "R 0x0011B01C" }, + { "R 0x0011B020" }, + { "R 0x0011B024" }, + { "R 0x0011B028" }, + { "R 0x0011B02C" }, + { "R 0x0011B030" }, + { "R 0x0011B034" }, + { "R 0x00174000" }, + { "R 0x00174004" }, + { "R 0x00174008" }, + { "R 0x0017400C" }, + { "R 0x00174010" }, + { "R 0x00174014" }, + { "R 0x00174018" }, + { "R 0x0017401C" }, + { "R 0x00174020" }, + { "R 0x00174024" }, + { "R 0x00174028" }, + { "R 0x0017402C" }, + { "R 0x00174030" }, + { "R 0x00174034" }, + { "R 0x00176000" }, + { "R 0x00176004" }, + { "R 0x00176008" }, + { "R 0x0017600C" }, + { "R 0x00176010" }, + { "R 0x00176014" }, + { "R 0x00176018" }, + { "R 0x0017601C" }, + { "R 0x00176020" }, + { "R 0x00176024" }, + { "R 0x00176028" }, + { "R 0x0017602C" }, + { "R 0x00176030" }, + { "R 0x00176034" }, + { "R 0x0010401C" }, + { "R 0x00183024" }, + { "R 0x00144168" }, + { "R 0x0011702C" }, + { "R 0x0010904C" }, + { "R 0x00189038" }, + { "R 0x001443E8" }, + { "R 0x001442B8" }, + { "R 0x00105060" }, + { "R 0x00141024" }, + { "R 0x00145038" }, + { "R 0x00109004" }, + { "R 0x00189004" }, + { "R 0x00190004" }, + { "R 0x0C2A0000" }, + { "R 0x0C2A0004" }, + { "R 0x0C2A0008" }, + { "R 0x0C2A000C" }, + { "R 0x0C2A0010" }, + { "R 0x0C2A0014" }, + { "R 0x0C2A0018" }, + { "R 0x0C2A001C" }, + { "R 0x0C2A0020" }, + { "R 0x0C2A0024" }, + { "R 0x0C2A0028" }, + { "R 0x0C2A002C" }, + { "R 0x0C2A0030" }, + { "R 0x0C2A0034" }, + { "R 0x0C2A1000" }, + { "R 0x0C2A1004" }, + { "R 0x0C2A1008" }, + { "R 0x0C2A100C" }, + { "R 0x0C2A1010" }, + { "R 0x0C2A1014" }, + { "R 0x0C2A1018" }, + { "R 0x0C2A101C" }, + { "R 0x0C2A1020" }, + { "R 0x0C2A1024" }, + { "R 0x0C2A1028" }, + { "R 0x0C2A102C" }, + { "R 0x0C2A1030" }, + { "R 0x0C2A2260" }, + { "R 0x0C2A2264" }, + { "R 0x0C2A3008" }, + { "R 0x0C2A300C" }, + { "R 0x0C2A3010" }, + { "R 0x0C2A3014" }, + { "R 0x0C2A3024" }, + { "R 0x0C2A2034" }, + { "R 0x0C2A214C" }, + { "R 0x0C2A2150" }, + { "R 0x0C2A2154" }, + { "R 0x0C2630A0 4" }, + { "R 0x0C2630B0 4" }, + { "R 0x0C2630C0 4" }, + { "R 0x0C2630D0 4" }, + { "R 0x1800005C 1" }, + { "R 0x1801005C 1" }, + { "R 0x1802005C 1" }, + { "R 0x1803005C 1" }, + { "R 0x1804005C 1" }, + { "R 0x1805005C 1" }, + { "R 0x1806005C 1" }, + { "R 0x1807005C 1" }, { "R 0x3d96000" }, { "R 0x3d96004" }, }; From 4bbe631c08e381fd21efa69e3899e1b775a5d065 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 10 Apr 2026 21:26:53 +0800 Subject: [PATCH 0580/1330] QCLINUX: qcom-dcc: use late_initcall and build as built-in for boot debug The DCC device stub driver was registered with module_init(), which runs during the initcall sequence before late_initcall(). The DCC hardware depends on resources that are not yet available at that point, causing the driver to fail silently during early boot. Switch to late_initcall() so the driver initialises after all subsystem dependencies are ready. Remove the module_exit() registration since the driver is now built-in only. Update qcom_debug.config to build CONFIG_QCOM_DCC and CONFIG_QCOM_DCC_DEV as built-in (=y) instead of loadable modules (=m) to match the late_initcall() requirement and allow early boot debugging. Signed-off-by: Jie Gan (cherry picked from commit 7c9ef49d17b14e38b6c4889bf5714abb670d19ff) --- arch/arm64/configs/qcom_debug.config | 4 ++-- drivers/misc/qcom-dcc-dev.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/configs/qcom_debug.config b/arch/arm64/configs/qcom_debug.config index 48ae2fb9737ac..0419414d6c51b 100644 --- a/arch/arm64/configs/qcom_debug.config +++ b/arch/arm64/configs/qcom_debug.config @@ -1,4 +1,4 @@ -CONFIG_QCOM_DCC=m -CONFIG_QCOM_DCC_DEV=m +CONFIG_QCOM_DCC=y +CONFIG_QCOM_DCC_DEV=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_MEMORY_DUMP_DEV=m diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index 7656e8e90aa1c..4d0c9c9526da3 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -978,7 +978,6 @@ static void __exit dcc_dev_exit(void) platform_device_unregister(dcc_pdev); } -module_init(dcc_dev_init); -module_exit(dcc_dev_exit); +late_initcall(dcc_dev_init); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver, device stub"); From 570d15023824251120f08e393af22a23e81bfe49 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 10 Apr 2026 21:27:10 +0800 Subject: [PATCH 0581/1330] QCLINUX: memory-dump: use late_initcall and build as built-in for boot debug The memory dump device stub driver was registered with module_init(), which runs before late_initcall(). The memory dump subsystem depends on resources that are not yet available at that point, causing the driver to fail silently during early boot. Switch to late_initcall() so the driver initialises after all subsystem dependencies are ready. Remove the module_exit() registration since the driver is now built-in only. Update qcom_debug.config to build CONFIG_QCOM_MEMORY_DUMP_DEV as built-in (=y) instead of a loadable module (=m) to match the late_initcall() requirement and allow early boot debugging. Signed-off-by: Jie Gan (cherry picked from commit a8695a4a179e6003a346cf0ec16978ab6f689a6e) --- arch/arm64/configs/qcom_debug.config | 2 +- drivers/firmware/qcom/memory_dump_dev.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/configs/qcom_debug.config b/arch/arm64/configs/qcom_debug.config index 0419414d6c51b..1399972795b68 100644 --- a/arch/arm64/configs/qcom_debug.config +++ b/arch/arm64/configs/qcom_debug.config @@ -1,4 +1,4 @@ CONFIG_QCOM_DCC=y CONFIG_QCOM_DCC_DEV=y CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_QCOM_MEMORY_DUMP_DEV=m +CONFIG_QCOM_MEMORY_DUMP_DEV=y diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c index 0c0cb06462cc5..0845aa152dc2f 100644 --- a/drivers/firmware/qcom/memory_dump_dev.c +++ b/drivers/firmware/qcom/memory_dump_dev.c @@ -513,7 +513,6 @@ static void __exit mem_dump_dev_exit(void) platform_device_unregister(mem_dump_pdev); } -module_init(mem_dump_dev_init); -module_exit(mem_dump_dev_exit); +late_initcall(mem_dump_dev_init); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Qualcomm Technologies Inc. Memory Dump driver V2, device stub"); From 2cc8bdf3aae0ff37cc248b71a02009088e442cce Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 7 Apr 2026 11:07:38 +0530 Subject: [PATCH 0582/1330] PENDING: media: iris: enable sm8550 context banks via init_cb_devs Wire up sm8550_init_cb_devs() in iris_platform_gen2.c to register the two child context-bank devices (iris_non_pixel and iris_pixel) using iris_create_cb_dev(), and hook it into the sm8550_data platform data via the .init_cb_devs callback. Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Signed-off-by: Gourav Kumar (cherry picked from commit e864a8117b070665f1a054c59b95d577b6b7708c) --- .../platform/qcom/iris/iris_platform_gen2.c | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index e0c99d28762cd..f0c4504a9cc61 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -762,6 +762,47 @@ static void iris_set_sm8550_preset_registers(struct iris_core *core) writel(0x0, core->reg_base + 0xB0088); } +static int sm8550_init_cb_devs(struct iris_core *core) +{ + const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ + const u32 f_id_p = 1; /* IRIS_PIXEL */ + struct device *dev; + + dev = iris_create_cb_dev(core, "iris_non_pixel", &f_id_np); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + core->dev_np = dev; + core->dev_bs = core->dev_np; + + dev = iris_create_cb_dev(core, "iris_pixel", &f_id_p); + if (IS_ERR(dev)) + goto err_unreg_dev_np; + + core->dev_p = dev; + + return 0; + +err_unreg_dev_np: + platform_device_unregister(to_platform_device(core->dev_np)); + core->dev_np = NULL; + core->dev_bs = NULL; + + return PTR_ERR(dev); +} + +static void sm8550_deinit_cb_devs(struct iris_core *core) +{ + if (core->dev_np) + platform_device_unregister(to_platform_device(core->dev_np)); + if (core->dev_p) + platform_device_unregister(to_platform_device(core->dev_p)); + + core->dev_np = NULL; + core->dev_bs = NULL; + core->dev_p = NULL; +} + static const struct icc_info sm8550_icc_table[] = { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -1016,6 +1057,8 @@ const struct iris_platform_data sm8550_data = { .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .set_preset_registers = iris_set_sm8550_preset_registers, + .init_cb_devs = sm8550_init_cb_devs, + .deinit_cb_devs = sm8550_deinit_cb_devs, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8550_clk_reset_table, From 011ba5ef3c10fefb9c938153c4636c3af529103a Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Fri, 13 Mar 2026 18:49:38 +0530 Subject: [PATCH 0583/1330] PENDING: media: iris: add context bank devices using iommu-map Different stream IDs from VPU would be associated to one of these CB. Multiple CBs are needed to increase the IOVA for the video usecases like higher concurrent sessions. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia (cherry picked from commit b4ee04ac22e727c817eeee627d502369cb37282c) --- drivers/media/platform/qcom/iris/iris_core.h | 6 ++++ .../platform/qcom/iris/iris_platform_common.h | 2 ++ drivers/media/platform/qcom/iris/iris_probe.c | 31 ++++++++++++++--- .../media/platform/qcom/iris/iris_resources.c | 34 +++++++++++++++++++ .../media/platform/qcom/iris/iris_resources.h | 1 + 5 files changed, 70 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index ef081ccc3429d..c85fd7f292467 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -34,6 +34,9 @@ enum domain_type { * struct iris_core - holds core parameters valid for all instances * * @dev: reference to device structure + * @dev_np: reference to non-pixel context bank device structure + * @dev_p: reference to pixel context bank device structure + * @dev_bs: reference to bitstream context bank device structure * @reg_base: IO memory base address * @irq: iris irq * @v4l2_dev: a holder for v4l2 device structure @@ -77,6 +80,9 @@ enum domain_type { struct iris_core { struct device *dev; + struct device *dev_np; + struct device *dev_p; + struct device *dev_bs; void __iomem *reg_base; int irq; struct v4l2_device v4l2_dev; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 8c1ad8ae46025..a373407abadfb 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -220,6 +220,8 @@ struct iris_platform_data { u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; void (*set_preset_registers)(struct iris_core *core); + int (*init_cb_devs)(struct iris_core *core); + void (*deinit_cb_devs)(struct iris_core *core); const struct icc_info *icc_tbl; unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index fb5b31270c56a..bfc71c4448f8f 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -123,6 +123,20 @@ static int iris_init_resets(struct iris_core *core) core->iris_platform_data->controller_rst_tbl_size); } +static int iris_init_cb_devs(struct iris_core *core) +{ + if (core->iris_platform_data->init_cb_devs) + return core->iris_platform_data->init_cb_devs(core); + + return 0; +} + +static void iris_deinit_cb_devs(struct iris_core *core) +{ + if (core->iris_platform_data->deinit_cb_devs) + core->iris_platform_data->deinit_cb_devs(core); +} + static int iris_init_resources(struct iris_core *core) { int ret; @@ -193,6 +207,7 @@ static void iris_remove(struct platform_device *pdev) return; iris_core_deinit(core); + iris_deinit_cb_devs(core); video_unregister_device(core->vdev_dec); video_unregister_device(core->vdev_enc); @@ -259,11 +274,15 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; + ret = iris_init_cb_devs(core); + if (ret) + return ret; + iris_session_init_caps(core); ret = v4l2_device_register(dev, &core->v4l2_dev); if (ret) - return ret; + goto err_deinit_cb; ret = iris_register_video_device(core, DECODER); if (ret) @@ -277,9 +296,11 @@ static int iris_probe(struct platform_device *pdev) dma_mask = core->iris_platform_data->dma_mask; - ret = dma_set_mask_and_coherent(dev, dma_mask); - if (ret) - goto err_vdev_unreg_enc; + if (device_iommu_mapped(core->dev)) { + ret = dma_set_mask_and_coherent(core->dev, dma_mask); + if (ret) + goto err_vdev_unreg_enc; + } dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32)); @@ -298,6 +319,8 @@ static int iris_probe(struct platform_device *pdev) video_unregister_device(core->vdev_dec); err_v4l2_unreg: v4l2_device_unregister(&core->v4l2_dev); +err_deinit_cb: + iris_deinit_cb_devs(core); return ret; } diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c index 773f6548370a2..b53a66d8851b6 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -141,3 +142,36 @@ int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type return 0; } + +struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id) +{ + struct platform_device *pdev; + int ret; + + pdev = platform_device_alloc(name, 0); + if (!pdev) + return ERR_PTR(-ENOMEM); + + pdev->dev.parent = core->dev; + + ret = platform_device_add(pdev); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(ret); + } + + ret = of_dma_configure_id(&pdev->dev, core->dev->of_node, true, f_id); + if (ret) + goto error_unregister; + + ret = dma_set_mask_and_coherent(&pdev->dev, core->iris_platform_data->dma_mask); + if (ret) + goto error_unregister; + + return &pdev->dev; + +error_unregister: + platform_device_unregister(to_platform_device(&pdev->dev)); + + return ERR_PTR(ret); +} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h index 6bfbd2dc6db09..4a494627ff238 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -15,5 +15,6 @@ int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); +struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id); #endif From 81db4697326884ca79d45b8783f34dc3a482cc97 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Fri, 13 Mar 2026 18:49:39 +0530 Subject: [PATCH 0584/1330] PENDING: media: iris: add helper to select context bank device Depending on the buffer type (input, output and internal), associated context bank is selected, if available. Fallback to parent device for backward compatibility. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia (cherry picked from commit 611187365f68716bd4f8299883c1269ec47684cb) --- .../media/platform/qcom/iris/iris_buffer.c | 8 ++-- .../media/platform/qcom/iris/iris_hfi_queue.c | 16 +++---- .../media/platform/qcom/iris/iris_resources.c | 42 +++++++++++++++++++ .../media/platform/qcom/iris/iris_resources.h | 1 + drivers/media/platform/qcom/iris/iris_vidc.c | 4 +- 5 files changed, 58 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 1d53c7414b754..d927b392fb762 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -336,7 +336,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, enum iris_buffer_type buffer_type, u32 index) { struct iris_buffers *buffers = &inst->buffers[buffer_type]; - struct iris_core *core = inst->core; + struct device *dev = iris_get_cb_dev(inst, buffer_type); struct iris_buffer *buffer; if (!buffers->size) @@ -352,7 +352,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, buffer->buffer_size = buffers->size; buffer->dma_attrs = DMA_ATTR_WRITE_COMBINE | DMA_ATTR_NO_KERNEL_MAPPING; - buffer->kvaddr = dma_alloc_attrs(core->dev, buffer->buffer_size, + buffer->kvaddr = dma_alloc_attrs(dev, buffer->buffer_size, &buffer->device_addr, GFP_KERNEL, buffer->dma_attrs); if (!buffer->kvaddr) { kfree(buffer); @@ -489,10 +489,10 @@ int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer) { - struct iris_core *core = inst->core; + struct device *dev = iris_get_cb_dev(inst, buffer->type); list_del(&buffer->list); - dma_free_attrs(core->dev, buffer->buffer_size, buffer->kvaddr, + dma_free_attrs(dev, buffer->buffer_size, buffer->kvaddr, buffer->device_addr, buffer->dma_attrs); kfree(buffer); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_queue.c b/drivers/media/platform/qcom/iris/iris_hfi_queue.c index bf6db23b53e21..f465ff00a9ba3 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_queue.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_queue.c @@ -245,25 +245,26 @@ static void iris_hfi_queue_deinit(struct iris_iface_q_info *iface_q) int iris_hfi_queues_init(struct iris_core *core) { + struct device *dev = core->dev_np ? core->dev_np : core->dev; struct iris_hfi_queue_table_header *q_tbl_hdr; u32 queue_size; /* Iris hardware requires 4K queue alignment */ queue_size = ALIGN((sizeof(*q_tbl_hdr) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ)), SZ_4K); - core->iface_q_table_vaddr = dma_alloc_attrs(core->dev, queue_size, + core->iface_q_table_vaddr = dma_alloc_attrs(dev, queue_size, &core->iface_q_table_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->iface_q_table_vaddr) { - dev_err(core->dev, "queues alloc and map failed\n"); + dev_err(dev, "queues alloc and map failed\n"); return -ENOMEM; } - core->sfr_vaddr = dma_alloc_attrs(core->dev, SFR_SIZE, + core->sfr_vaddr = dma_alloc_attrs(dev, SFR_SIZE, &core->sfr_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->sfr_vaddr) { - dev_err(core->dev, "sfr alloc and map failed\n"); - dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, + dev_err(dev, "sfr alloc and map failed\n"); + dma_free_attrs(dev, sizeof(*q_tbl_hdr), core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); return -ENOMEM; } @@ -291,6 +292,7 @@ int iris_hfi_queues_init(struct iris_core *core) void iris_hfi_queues_deinit(struct iris_core *core) { + struct device *dev = core->dev_np ? core->dev_np : core->dev; u32 queue_size; if (!core->iface_q_table_vaddr) @@ -300,7 +302,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) iris_hfi_queue_deinit(&core->message_queue); iris_hfi_queue_deinit(&core->command_queue); - dma_free_attrs(core->dev, SFR_SIZE, core->sfr_vaddr, + dma_free_attrs(dev, SFR_SIZE, core->sfr_vaddr, core->sfr_daddr, DMA_ATTR_WRITE_COMBINE); core->sfr_vaddr = NULL; @@ -309,7 +311,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) queue_size = ALIGN(sizeof(struct iris_hfi_queue_table_header) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K); - dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, + dma_free_attrs(dev, queue_size, core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); core->iface_q_table_vaddr = NULL; diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c index b53a66d8851b6..b10884eb3ac64 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -13,6 +13,7 @@ #include #include "iris_core.h" +#include "iris_instance.h" #include "iris_resources.h" #define BW_THRESHOLD 50000 @@ -175,3 +176,44 @@ struct device *iris_create_cb_dev(struct iris_core *core, const char *name, cons return ERR_PTR(ret); } + +struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_type buffer_type) +{ + struct iris_core *core = inst->core; + struct device *dev = NULL; + + switch (buffer_type) { + case BUF_INPUT: + if (inst->domain == DECODER) + dev = core->dev_bs; + else + dev = core->dev_p; + break; + case BUF_OUTPUT: + if (inst->domain == DECODER) + dev = core->dev_p; + else + dev = core->dev_bs; + break; + case BUF_BIN: + dev = core->dev_bs; + break; + case BUF_DPB: + case BUF_PARTIAL: + case BUF_SCRATCH_2: + case BUF_VPSS: + dev = core->dev_p; + break; + case BUF_ARP: + case BUF_COMV: + case BUF_LINE: + case BUF_NON_COMV: + case BUF_PERSIST: + dev = core->dev_np; + break; + default: + dev_err(core->dev, "invalid buffer type: %d\n", buffer_type); + } + + return dev ? dev : core->dev; +} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h index 4a494627ff238..e6a6dc24a7f12 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -16,5 +16,6 @@ int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id); +struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_type buffer_type); #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 5eb1786b07371..83010a8c5f217 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -107,7 +107,7 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_ src_vq->drv_priv = inst; src_vq->buf_struct_size = sizeof(struct iris_buffer); src_vq->min_reqbufs_allocation = MIN_BUFFERS; - src_vq->dev = inst->core->dev; + src_vq->dev = iris_get_cb_dev(inst, BUF_INPUT); src_vq->lock = &inst->ctx_q_lock; ret = vb2_queue_init(src_vq); if (ret) @@ -121,7 +121,7 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_ dst_vq->drv_priv = inst; dst_vq->buf_struct_size = sizeof(struct iris_buffer); dst_vq->min_reqbufs_allocation = MIN_BUFFERS; - dst_vq->dev = inst->core->dev; + dst_vq->dev = iris_get_cb_dev(inst, BUF_OUTPUT); dst_vq->lock = &inst->ctx_q_lock; return vb2_queue_init(dst_vq); From f6d7229ae0823d1d0013082c86a0fc515ba10465 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Fri, 10 Apr 2026 18:23:23 +0530 Subject: [PATCH 0585/1330] PENDING: dt-bindings: media: iris: add sm8550 iris context bank function IDs Add a dt-bindings header include/dt-bindings/media/qcom,sm8550-iris.h defining IRIS_NON_PIXEL_VCODEC (0) and IRIS_PIXEL (1) function IDs used to identify the non-pixel and pixel context bank SMMU stream mappings via iommu-map. Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Signed-off-by: Gourav Kumar (cherry picked from commit 31259253b0534c1a8c43cd6806d9658f916750c5) --- include/dt-bindings/media/qcom,sm8550-iris.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 include/dt-bindings/media/qcom,sm8550-iris.h diff --git a/include/dt-bindings/media/qcom,sm8550-iris.h b/include/dt-bindings/media/qcom,sm8550-iris.h new file mode 100644 index 0000000000000..5165ef817f8bb --- /dev/null +++ b/include/dt-bindings/media/qcom,sm8550-iris.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_MEDIA_QCOM_SM8550_IRIS_H_ +#define _DT_BINDINGS_MEDIA_QCOM_SM8550_IRIS_H_ + +/* Function identifiers for iommu-map to attach for the context bank devices */ +#define IRIS_NON_PIXEL_VCODEC 0 +#define IRIS_PIXEL 1 + +#endif From 9709e051cad29cdf77d3a49e2bb74c8b56c72e54 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:02 +0200 Subject: [PATCH 0586/1330] FROMLIST: media: qcom: iris: drop pas_id from the iris_platform_data struct The PAS ID, the authentication service ID, used by the Iris is a constant and it is not expected to change anytime. Drop it from the platform data and use the constant instead. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-1-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Konrad Dybcio Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov (cherry picked from commit 541c9ac086f06bd742b83ed98db3e8575ca52b1f) --- drivers/media/platform/qcom/iris/iris_firmware.c | 7 ++++--- drivers/media/platform/qcom/iris/iris_platform_common.h | 2 -- drivers/media/platform/qcom/iris/iris_platform_gen1.c | 2 -- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 5 ----- 4 files changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index e19daf0c41262..da4da3648f983 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -17,11 +17,12 @@ #include "iris_core.h" #include "iris_firmware.h" +#define IRIS_PAS_ID 9 + #define MAX_FIRMWARE_NAME_SIZE 128 static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) { - u32 pas_id = core->iris_platform_data->pas_id; struct qcom_scm_pas_context *ctx; const struct firmware *firmware = NULL; struct device *dev = core->dev; @@ -43,7 +44,7 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) dev = core->fw.dev ? : core->dev; - ctx = devm_qcom_scm_pas_context_alloc(dev, pas_id, mem_phys, res_size); + ctx = devm_qcom_scm_pas_context_alloc(dev, IRIS_PAS_ID, mem_phys, res_size); if (!ctx) return -ENOMEM; @@ -112,7 +113,7 @@ int iris_fw_load(struct iris_core *core) cp_config->cp_nonpixel_size); if (ret) { dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + qcom_scm_pas_shutdown(IRIS_PAS_ID); return ret; } } diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index a373407abadfb..4b1e27367bc30 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -12,7 +12,6 @@ struct iris_core; struct iris_inst; -#define IRIS_PAS_ID 9 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ @@ -239,7 +238,6 @@ struct iris_platform_data { unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; - u32 pas_id; struct iris_fmt *inst_iris_fmts; u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index df8e6bf9430ed..1bbdefc48d718 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -360,7 +360,6 @@ const struct iris_platform_data sm8250_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu-1.0/venus.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, @@ -413,7 +412,6 @@ const struct iris_platform_data sc7280_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu20_p1.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index f0c4504a9cc61..e4cb38cecbb82 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -986,7 +986,6 @@ const struct iris_platform_data kaanapali_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu40_p2_s7.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1075,7 +1074,6 @@ const struct iris_platform_data sm8550_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu30_p4.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1180,7 +1178,6 @@ const struct iris_platform_data sm8650_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu33_p4.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1276,7 +1273,6 @@ const struct iris_platform_data sm8750_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu35_p4.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1376,7 +1372,6 @@ const struct iris_platform_data qcs8300_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu30_p4_s6.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_qcs8300, From 85fb80a1a26d59ea2108e5eba1f54609c9a66899 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:03 +0200 Subject: [PATCH 0587/1330] FROMLIST: media: qcom: iris: use common set_preset_registers function The set_preset_registers is (currently) common to all supported devices. Extract it to a iris_vpu_common.c and call it directly from iris_vpu_power_on(). Later, if any of the devices requires special handling, it can be sorted out separately. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-2-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov (cherry picked from commit 8f3507faaa439bda85698e7192230cca71e1f2f5) --- drivers/media/platform/qcom/iris/iris_platform_gen1.c | 7 ------- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 10 ---------- drivers/media/platform/qcom/iris/iris_vpu_common.c | 7 ++++++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 4 files changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 1bbdefc48d718..546f6c025d547 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -260,11 +260,6 @@ static struct platform_inst_caps platform_inst_cap_sm8250 = { .max_operating_rate = MAXIMUM_FPS, }; -static void iris_set_sm8250_preset_registers(struct iris_core *core) -{ - writel(0x0, core->reg_base + 0xB0088); -} - static const struct icc_info sm8250_icc_table[] = { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -343,7 +338,6 @@ const struct iris_platform_data sm8250_data = { .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, - .set_preset_registers = iris_set_sm8250_preset_registers, .icc_tbl = sm8250_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), .clk_rst_tbl = sm8250_clk_reset_table, @@ -397,7 +391,6 @@ const struct iris_platform_data sc7280_data = { .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, - .set_preset_registers = iris_set_sm8250_preset_registers, .icc_tbl = sm8250_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), .bw_tbl_dec = sc7280_bw_table_dec, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index e4cb38cecbb82..8e98857f76f99 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -757,11 +757,6 @@ static struct platform_inst_caps platform_inst_cap_sm8550 = { .max_operating_rate = MAXIMUM_FPS, }; -static void iris_set_sm8550_preset_registers(struct iris_core *core) -{ - writel(0x0, core->reg_base + 0xB0088); -} - static int sm8550_init_cb_devs(struct iris_core *core) { const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ @@ -969,7 +964,6 @@ const struct iris_platform_data kaanapali_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu4x_buf_size, .vpu_ops = &iris_vpu4x_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = kaanapali_clk_reset_table, @@ -1055,7 +1049,6 @@ const struct iris_platform_data sm8550_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .init_cb_devs = sm8550_init_cb_devs, .deinit_cb_devs = sm8550_deinit_cb_devs, .icc_tbl = sm8550_icc_table, @@ -1159,7 +1152,6 @@ const struct iris_platform_data sm8650_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8650_clk_reset_table, @@ -1256,7 +1248,6 @@ const struct iris_platform_data sm8750_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8750_clk_reset_table, @@ -1355,7 +1346,6 @@ const struct iris_platform_data qcs8300_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8550_clk_reset_table, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 3e3482d1841d2..96e5b305c5f4a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -476,7 +476,7 @@ int iris_vpu_power_on(struct iris_core *core) iris_opp_set_rate(core->dev, freq); - core->iris_platform_data->set_preset_registers(core); + iris_vpu_set_preset_registers(core); iris_vpu_interrupt_init(core); core->intr_status = 0; @@ -493,3 +493,8 @@ int iris_vpu_power_on(struct iris_core *core) return ret; } + +void iris_vpu_set_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + 0xb0088); +} diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index dee3b1349c5e8..09799a375c142 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -42,4 +42,6 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core); void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core); u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size); +void iris_vpu_set_preset_registers(struct iris_core *core); + #endif From ddd892fa941518f8c7d95f850c96e832d7cfe088 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:04 +0200 Subject: [PATCH 0588/1330] FROMLIST: media: qcom: iris: don't use function indirection in gen2-specific code To note that iris_set_num_comv() is gen2-internal, rename it to iris_hfi_gen2_set_num_comv() and then stop using hfi_ops indirection to set session property (like other functions in this file do). Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-3-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Konrad Dybcio Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov (cherry picked from commit d26f3c50ce8007de43d3798c6723185f9f36e875) --- .../platform/qcom/iris/iris_hfi_gen2_command.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 30bfd90d423ba..e4f25b7f5d048 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1205,7 +1205,7 @@ static u32 iris_hfi_gen2_buf_type_from_driver(u32 domain, enum iris_buffer_type } } -static int iris_set_num_comv(struct iris_inst *inst) +static int iris_hfi_gen2_set_num_comv(struct iris_inst *inst) { struct platform_inst_caps *caps; struct iris_core *core = inst->core; @@ -1220,12 +1220,12 @@ static int iris_set_num_comv(struct iris_inst *inst) num_comv = (inst->codec == V4L2_PIX_FMT_AV1) ? NUM_COMV_AV1 : caps->num_comv; - return core->hfi_ops->session_set_property(inst, - HFI_PROP_COMV_BUFFER_COUNT, - HFI_HOST_FLAGS_NONE, - HFI_PORT_BITSTREAM, - HFI_PAYLOAD_U32, - &num_comv, sizeof(u32)); + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_COMV_BUFFER_COUNT, + HFI_HOST_FLAGS_NONE, + HFI_PORT_BITSTREAM, + HFI_PAYLOAD_U32, + &num_comv, sizeof(u32)); } static void iris_hfi_gen2_get_buffer(u32 domain, struct iris_buffer *buffer, @@ -1257,7 +1257,7 @@ static int iris_hfi_gen2_session_queue_buffer(struct iris_inst *inst, struct iri iris_hfi_gen2_get_buffer(inst->domain, buffer, &hfi_buffer); if (buffer->type == BUF_COMV) { - ret = iris_set_num_comv(inst); + ret = iris_hfi_gen2_set_num_comv(inst); if (ret) return ret; } From 8c4b698e6f938013e6118eff53b39ec83f20171b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:05 +0200 Subject: [PATCH 0589/1330] FROMLIST: media: qcom: iris: split HFI session ops from core ops Calling HFI instance-specific ops should not require double indirection through the core ops. Split instance-specific ops to a separate struct, keep a pointer to it in struct iris_inst and set it directly in the get_instance function. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-4-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov (cherry picked from commit cd8ce6d0965135996c80d08cf4e75b1143d81aa4) --- .../media/platform/qcom/iris/iris_buffer.c | 4 +- .../media/platform/qcom/iris/iris_common.c | 8 ++-- drivers/media/platform/qcom/iris/iris_ctrls.c | 46 +++++++++---------- .../platform/qcom/iris/iris_hfi_common.h | 3 ++ .../qcom/iris/iris_hfi_gen1_command.c | 23 +++++++--- .../qcom/iris/iris_hfi_gen2_command.c | 17 +++++-- .../media/platform/qcom/iris/iris_instance.h | 4 ++ drivers/media/platform/qcom/iris/iris_vb2.c | 2 +- drivers/media/platform/qcom/iris/iris_vdec.c | 6 +-- drivers/media/platform/qcom/iris/iris_venc.c | 4 +- drivers/media/platform/qcom/iris/iris_vidc.c | 2 +- 11 files changed, 72 insertions(+), 47 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index d927b392fb762..68336824aee1d 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -404,7 +404,7 @@ int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; int ret; ret = hfi_ops->session_queue_buf(inst, buf); @@ -572,7 +572,7 @@ int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 plane) static int iris_release_internal_buffers(struct iris_inst *inst, enum iris_buffer_type buffer_type) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct iris_buffers *buffers = &inst->buffers[buffer_type]; struct iris_buffer *buffer, *next; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media/platform/qcom/iris/iris_common.c index 7f1c7fe144f70..25836561bcf3e 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -48,7 +48,7 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_process_streamon_input(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_inst_sub_state set_sub_state = 0; int ret; @@ -90,7 +90,7 @@ int iris_process_streamon_input(struct iris_inst *inst) int iris_process_streamon_output(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state = 0; bool drain_active, drc_active, first_ipsc; int ret = 0; @@ -189,7 +189,7 @@ static void iris_flush_deferred_buffers(struct iris_inst *inst, static void iris_kill_session(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; if (!inst->session_id) return; @@ -200,7 +200,7 @@ static void iris_kill_session(struct iris_inst *inst) int iris_session_streamoff(struct iris_inst *inst, u32 plane) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_buffer_type buffer_type; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c index 3cec957580f5e..5a24aa869b2dc 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -399,7 +399,7 @@ static u32 iris_get_port_info(struct iris_inst *inst, int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_value = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -412,7 +412,7 @@ int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_value = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -425,7 +425,7 @@ int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct v4l2_format *inp_f = inst->fmt_src; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 height = inp_f->fmt.pix_mp.height; @@ -446,7 +446,7 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 work_route = inst->fw_caps[PIPE].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -459,7 +459,7 @@ int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id, hfi_value; if (inst->codec == V4L2_PIX_FMT_H264) { @@ -479,7 +479,7 @@ int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id, hfi_value; if (inst->codec == V4L2_PIX_FMT_H264) { @@ -499,7 +499,7 @@ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; struct hfi_profile_level pl; @@ -520,7 +520,7 @@ int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_ca int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 header_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -539,7 +539,7 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; u32 header_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -561,7 +561,7 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; u32 bitrate = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -586,7 +586,7 @@ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; u32 peak_bitrate = inst->fw_caps[cap_id].value; u32 bitrate = inst->fw_caps[BITRATE].value; @@ -613,7 +613,7 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; @@ -640,7 +640,7 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; @@ -667,7 +667,7 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 entropy_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -687,7 +687,7 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 entropy_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 profile; @@ -712,7 +712,7 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; u32 min_qp_enable = 0, client_qp_enable = 0; @@ -776,7 +776,7 @@ int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; u32 max_qp_enable = 0, client_qp_enable; u32 i_frame_qp, p_frame_qp, b_frame_qp; @@ -841,7 +841,7 @@ int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; u32 i_frame_qp, p_frame_qp, b_frame_qp; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -902,7 +902,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct hfi_quantization_range_v2 range; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -923,7 +923,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -953,7 +953,7 @@ int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val = HFI_DISABLE_FLIP; @@ -972,7 +972,7 @@ int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct vb2_queue *q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); u32 ir_period = inst->fw_caps[cap_id].value; u32 ir_type = 0; @@ -998,7 +998,7 @@ int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type ca int iris_set_properties(struct iris_inst *inst, u32 plane) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct platform_inst_fw_cap *cap; int ret; u32 i; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 3edb5ae582b49..18684ada78b21 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -110,6 +110,9 @@ struct iris_hfi_command_ops { int (*sys_image_version)(struct iris_core *core); int (*sys_interframe_powercollapse)(struct iris_core *core); int (*sys_pc_prep)(struct iris_core *core); +}; + +struct iris_hfi_session_ops { int (*session_set_config_params)(struct iris_inst *inst, u32 plane); int (*session_set_property)(struct iris_inst *inst, u32 packet_type, u32 flag, u32 plane, u32 payload_type, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index e42d17653c2c3..a28b0c7ebbadd 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1063,11 +1063,7 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p return 0; } -static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { - .sys_init = iris_hfi_gen1_sys_init, - .sys_image_version = iris_hfi_gen1_sys_image_version, - .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, - .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, +static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_open = iris_hfi_gen1_session_open, .session_set_config_params = iris_hfi_gen1_session_set_config_params, .session_set_property = iris_hfi_gen1_session_set_property, @@ -1080,6 +1076,13 @@ static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { .session_close = iris_hfi_gen1_session_close, }; +static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { + .sys_init = iris_hfi_gen1_sys_init, + .sys_image_version = iris_hfi_gen1_sys_image_version, + .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, + .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, +}; + void iris_hfi_gen1_command_ops_init(struct iris_core *core) { core->hfi_ops = &iris_hfi_gen1_command_ops; @@ -1087,5 +1090,13 @@ void iris_hfi_gen1_command_ops_init(struct iris_core *core) struct iris_inst *iris_hfi_gen1_get_instance(void) { - return kzalloc_obj(struct iris_inst); + struct iris_inst *out; + + out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->hfi_session_ops = &iris_hfi_gen1_session_ops; + + return out; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index e4f25b7f5d048..ffb70fd9499cb 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1300,11 +1300,7 @@ static int iris_hfi_gen2_session_release_buffer(struct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } -static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { - .sys_init = iris_hfi_gen2_sys_init, - .sys_image_version = iris_hfi_gen2_sys_image_version, - .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, - .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, +static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_open = iris_hfi_gen2_session_open, .session_set_config_params = iris_hfi_gen2_session_set_config_params, .session_set_property = iris_hfi_gen2_session_set_property, @@ -1319,6 +1315,13 @@ static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { .session_close = iris_hfi_gen2_session_close, }; +static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { + .sys_init = iris_hfi_gen2_sys_init, + .sys_image_version = iris_hfi_gen2_sys_image_version, + .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, + .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, +}; + void iris_hfi_gen2_command_ops_init(struct iris_core *core) { core->hfi_ops = &iris_hfi_gen2_command_ops; @@ -1330,6 +1333,10 @@ struct iris_inst *iris_hfi_gen2_get_instance(void) /* The allocation is intentionally larger than struct iris_inst. */ out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; return &out->inst; } diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h index 63dd889c9992a..9fa635e27a28d 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -15,6 +15,8 @@ #define DEFAULT_WIDTH 320 #define DEFAULT_HEIGHT 240 +struct iris_hfi_session_ops; + enum iris_fmt_type_out { IRIS_FMT_H264, IRIS_FMT_HEVC, @@ -38,6 +40,7 @@ struct iris_fmt { * @list: used for attach an instance to the core * @core: pointer to core structure * @session_id: id of current video session + * @hfi_session_ops: iris HFI session ops * @ctx_q_lock: lock to serialize queues related ioctls * @lock: lock to seralise forward and reverse threads * @fh: reference of v4l2 file handler @@ -82,6 +85,7 @@ struct iris_inst { struct list_head list; struct iris_core *core; u32 session_id; + const struct iris_hfi_session_ops *hfi_session_ops; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ struct mutex lock; /* lock to serialize forward and reverse threads */ struct v4l2_fh fh; diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/platform/qcom/iris/iris_vb2.c index bf0b8400996ec..a2ea2d67f60d0 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -129,7 +129,7 @@ int iris_vb2_queue_setup(struct vb2_queue *q, if (!inst->once_per_session_set) { inst->once_per_session_set = true; - ret = core->hfi_ops->session_open(inst); + ret = inst->hfi_session_ops->session_open(inst); if (ret) { ret = -EINVAL; dev_err(core->dev, "session open failed\n"); diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index fa4dc09ba26ee..7a3fd6a2fd505 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -371,7 +371,7 @@ int iris_vdec_streamon_input(struct iris_inst *inst) int iris_vdec_streamon_output(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; int ret; ret = hfi_ops->session_set_config_params(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); @@ -448,7 +448,7 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_vdec_start_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state = 0; struct vb2_queue *dst_vq; int ret; @@ -511,7 +511,7 @@ int iris_vdec_start_cmd(struct iris_inst *inst) int iris_vdec_stop_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; int ret; ret = hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c index 4d886769d958b..c11fee4799cdd 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -575,7 +575,7 @@ int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_venc_start_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state = 0; struct vb2_queue *dst_vq; int ret; @@ -617,7 +617,7 @@ int iris_venc_start_cmd(struct iris_inst *inst) int iris_venc_stop_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; int ret; ret = hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 83010a8c5f217..64b1f6997dd4a 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -224,7 +224,7 @@ int iris_open(struct file *filp) static void iris_session_close(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; bool wait_for_response = true; int ret; From 913b7a011602ae1d7476cab41020b4d3c3505469 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:06 +0200 Subject: [PATCH 0590/1330] FROMLIST: media: qcom: iris: merge hfi_response_ops and hfi_command_ops There is little point in having two different structures for HFI-related core ops. Merge both of them into the new iris_hfi_ops structure. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-5-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov (cherry picked from commit 92e9a0c31a05765b21ee0af692d1df563b755458) --- drivers/media/platform/qcom/iris/iris_core.h | 6 ++---- .../media/platform/qcom/iris/iris_hfi_common.c | 6 +++--- .../media/platform/qcom/iris/iris_hfi_common.h | 8 +++----- drivers/media/platform/qcom/iris/iris_hfi_gen1.h | 4 ++-- .../platform/qcom/iris/iris_hfi_gen1_command.c | 8 +++++--- .../platform/qcom/iris/iris_hfi_gen1_response.c | 11 +---------- drivers/media/platform/qcom/iris/iris_hfi_gen2.h | 4 ++-- .../platform/qcom/iris/iris_hfi_gen2_command.c | 8 +++++--- .../platform/qcom/iris/iris_hfi_gen2_response.c | 11 +---------- .../platform/qcom/iris/iris_platform_common.h | 3 +-- .../media/platform/qcom/iris/iris_platform_gen1.c | 6 ++---- .../media/platform/qcom/iris/iris_platform_gen2.c | 15 +++++---------- drivers/media/platform/qcom/iris/iris_probe.c | 3 +-- .../media/platform/qcom/iris/iris_vpu_common.c | 2 +- 14 files changed, 34 insertions(+), 61 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index c85fd7f292467..5f8668e1a16d7 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -68,8 +68,7 @@ enum domain_type { * @header_id: id of packet header * @packet_id: id of packet * @power: a structure for clock and bw information - * @hfi_ops: iris hfi command ops - * @hfi_response_ops: iris hfi response ops + * @hfi_sys_ops: iris HFI system ops * @core_init_done: structure of signal completion for system response * @intr_status: interrupt status * @sys_error_handler: a delayed work for handling system fatal error @@ -119,8 +118,7 @@ struct iris_core { u32 header_id; u32 packet_id; struct iris_core_power power; - const struct iris_hfi_command_ops *hfi_ops; - const struct iris_hfi_response_ops *hfi_response_ops; + const struct iris_hfi_sys_ops *hfi_sys_ops; struct completion core_init_done; u32 intr_status; struct delayed_work sys_error_handler; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/media/platform/qcom/iris/iris_hfi_common.c index 621c66593d88d..8769ec61f1176 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c @@ -76,7 +76,7 @@ u32 iris_hfi_get_v4l2_matrix_coefficients(u32 hfi_coefficients) int iris_hfi_core_init(struct iris_core *core) { - const struct iris_hfi_command_ops *hfi_ops = core->hfi_ops; + const struct iris_hfi_sys_ops *hfi_ops = core->hfi_sys_ops; int ret; ret = hfi_ops->sys_init(core); @@ -109,7 +109,7 @@ irqreturn_t iris_hfi_isr_handler(int irq, void *data) iris_vpu_clear_interrupt(core); mutex_unlock(&core->lock); - core->hfi_response_ops->hfi_response_handler(core); + core->hfi_sys_ops->sys_hfi_response_handler(core); if (!iris_vpu_watchdog(core, core->intr_status)) enable_irq(irq); @@ -144,7 +144,7 @@ int iris_hfi_pm_suspend(struct iris_core *core) int iris_hfi_pm_resume(struct iris_core *core) { - const struct iris_hfi_command_ops *ops = core->hfi_ops; + const struct iris_hfi_sys_ops *ops = core->hfi_sys_ops; int ret; ret = iris_vpu_power_on(core); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 18684ada78b21..9aa84a1d8f950 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -105,11 +105,13 @@ struct iris_hfi_prop_type_handle { int (*handle)(struct iris_inst *inst, u32 plane); }; -struct iris_hfi_command_ops { +struct iris_hfi_sys_ops { int (*sys_init)(struct iris_core *core); int (*sys_image_version)(struct iris_core *core); int (*sys_interframe_powercollapse)(struct iris_core *core); int (*sys_pc_prep)(struct iris_core *core); + + void (*sys_hfi_response_handler)(struct iris_core *core); }; struct iris_hfi_session_ops { @@ -129,10 +131,6 @@ struct iris_hfi_session_ops { int (*session_close)(struct iris_inst *inst); }; -struct iris_hfi_response_ops { - void (*hfi_response_handler)(struct iris_core *core); -}; - struct hfi_subscription_params { u32 bitstream_resolution; u32 crop_offsets[2]; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h index 19b8e9054a757..38e9d262d7df4 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h @@ -9,8 +9,8 @@ struct iris_core; struct iris_inst; -void iris_hfi_gen1_command_ops_init(struct iris_core *core); -void iris_hfi_gen1_response_ops_init(struct iris_core *core); +void iris_hfi_gen1_sys_ops_init(struct iris_core *core); +void iris_hfi_gen1_response_handler(struct iris_core *core); struct iris_inst *iris_hfi_gen1_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index a28b0c7ebbadd..26b7feb05d15b 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1076,16 +1076,18 @@ static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_close = iris_hfi_gen1_session_close, }; -static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { +static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { .sys_init = iris_hfi_gen1_sys_init, .sys_image_version = iris_hfi_gen1_sys_image_version, .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, + + .sys_hfi_response_handler = iris_hfi_gen1_response_handler, }; -void iris_hfi_gen1_command_ops_init(struct iris_core *core) +void iris_hfi_gen1_sys_ops_init(struct iris_core *core) { - core->hfi_ops = &iris_hfi_gen1_command_ops; + core->hfi_sys_ops = &iris_hfi_gen1_sys_ops; } struct iris_inst *iris_hfi_gen1_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 8e864c239e293..bfd7495bf44f0 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -688,7 +688,7 @@ static void iris_hfi_gen1_flush_debug_queue(struct iris_core *core, u8 *packet) } } -static void iris_hfi_gen1_response_handler(struct iris_core *core) +void iris_hfi_gen1_response_handler(struct iris_core *core) { memset(core->response_packet, 0, sizeof(struct hfi_pkt_hdr)); while (!iris_hfi_queue_msg_read(core, core->response_packet)) { @@ -698,12 +698,3 @@ static void iris_hfi_gen1_response_handler(struct iris_core *core) iris_hfi_gen1_flush_debug_queue(core, core->response_packet); } - -static const struct iris_hfi_response_ops iris_hfi_gen1_response_ops = { - .hfi_response_handler = iris_hfi_gen1_response_handler, -}; - -void iris_hfi_gen1_response_ops_init(struct iris_core *core) -{ - core->hfi_response_ops = &iris_hfi_gen1_response_ops; -} diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h index b9d3749a10efe..6cc6d9890c128 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h @@ -34,8 +34,8 @@ struct iris_inst_hfi_gen2 { struct hfi_subscription_params dst_subcr_params; }; -void iris_hfi_gen2_command_ops_init(struct iris_core *core); -void iris_hfi_gen2_response_ops_init(struct iris_core *core); +void iris_hfi_gen2_sys_ops_init(struct iris_core *core); +void iris_hfi_gen2_response_handler(struct iris_core *core); struct iris_inst *iris_hfi_gen2_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index ffb70fd9499cb..0c98d680bf094 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1315,16 +1315,18 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_close = iris_hfi_gen2_session_close, }; -static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { +static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { .sys_init = iris_hfi_gen2_sys_init, .sys_image_version = iris_hfi_gen2_sys_image_version, .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, + + .sys_hfi_response_handler = iris_hfi_gen2_response_handler, }; -void iris_hfi_gen2_command_ops_init(struct iris_core *core) +void iris_hfi_gen2_sys_ops_init(struct iris_core *core) { - core->hfi_ops = &iris_hfi_gen2_command_ops; + core->hfi_sys_ops = &iris_hfi_gen2_sys_ops; } struct iris_inst *iris_hfi_gen2_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 8e19f61bbbf9e..c350d231265e5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -977,7 +977,7 @@ static void iris_hfi_gen2_flush_debug_queue(struct iris_core *core, u8 *packet) } } -static void iris_hfi_gen2_response_handler(struct iris_core *core) +void iris_hfi_gen2_response_handler(struct iris_core *core) { if (iris_vpu_watchdog(core, core->intr_status)) { struct iris_hfi_packet pkt = {.type = HFI_SYS_ERROR_WD_TIMEOUT}; @@ -997,12 +997,3 @@ static void iris_hfi_gen2_response_handler(struct iris_core *core) iris_hfi_gen2_flush_debug_queue(core, core->response_packet); } - -static const struct iris_hfi_response_ops iris_hfi_gen2_response_ops = { - .hfi_response_handler = iris_hfi_gen2_response_handler, -}; - -void iris_hfi_gen2_response_ops_init(struct iris_core *core) -{ - core->hfi_response_ops = &iris_hfi_gen2_response_ops; -} diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 4b1e27367bc30..35e375ed27ea4 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -213,8 +213,7 @@ enum platform_pm_domain_type { }; struct iris_platform_data { - void (*init_hfi_command_ops)(struct iris_core *core); - void (*init_hfi_response_ops)(struct iris_core *core); + void (*init_hfi_ops)(struct iris_core *core); struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 546f6c025d547..9eeb500c65d90 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -334,8 +334,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { const struct iris_platform_data sm8250_data = { .get_instance = iris_hfi_gen1_get_instance, - .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, + .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -387,8 +386,7 @@ const struct iris_platform_data sm8250_data = { const struct iris_platform_data sc7280_data = { .get_instance = iris_hfi_gen1_get_instance, - .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, + .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 8e98857f76f99..655098e260740 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -960,8 +960,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { const struct iris_platform_data kaanapali_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu4x_buf_size, .vpu_ops = &iris_vpu4x_ops, .icc_tbl = sm8550_icc_table, @@ -1045,8 +1044,7 @@ const struct iris_platform_data kaanapali_data = { const struct iris_platform_data sm8550_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .init_cb_devs = sm8550_init_cb_devs, @@ -1148,8 +1146,7 @@ const struct iris_platform_data sm8550_data = { */ const struct iris_platform_data sm8650_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, .icc_tbl = sm8550_icc_table, @@ -1244,8 +1241,7 @@ const struct iris_platform_data sm8650_data = { const struct iris_platform_data sm8750_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, .icc_tbl = sm8550_icc_table, @@ -1342,8 +1338,7 @@ const struct iris_platform_data sm8750_data = { */ const struct iris_platform_data qcs8300_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .icc_tbl = sm8550_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index bfc71c4448f8f..dbc99f6a0ebe8 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -267,8 +267,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); iris_init_ops(core); - core->iris_platform_data->init_hfi_command_ops(core); - core->iris_platform_data->init_hfi_response_ops(core); + core->iris_platform_data->init_hfi_ops(core); ret = iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 96e5b305c5f4a..aa0b66954680d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -149,7 +149,7 @@ int iris_vpu_prepare_pc(struct iris_core *core) if (!wfi_status || !idle_status) goto skip_power_off; - ret = core->hfi_ops->sys_pc_prep(core); + ret = core->hfi_sys_ops->sys_pc_prep(core); if (ret) goto skip_power_off; From 25cac4d6233adf0f67c5c7702e4ddfa829fda43f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:07 +0200 Subject: [PATCH 0591/1330] FROMLIST: media: qcom: iris: move get_instance to iris_hfi_sys_ops The get_instance() is a callback tightly connected to the HFI implementation. Move it into the new iris_hfi_sys_ops structure, merging all core callbacks into a single vtable. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-6-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov (cherry picked from commit 50209bf968b5c3fd0d676256d7e5449cd4788a40) --- .../platform/qcom/iris/iris_hfi_common.h | 2 ++ .../media/platform/qcom/iris/iris_hfi_gen1.h | 2 -- .../qcom/iris/iris_hfi_gen1_command.c | 28 +++++++++-------- .../media/platform/qcom/iris/iris_hfi_gen2.h | 1 - .../qcom/iris/iris_hfi_gen2_command.c | 30 ++++++++++--------- .../platform/qcom/iris/iris_platform_common.h | 1 - .../platform/qcom/iris/iris_platform_gen1.c | 2 -- .../platform/qcom/iris/iris_platform_gen2.c | 4 --- drivers/media/platform/qcom/iris/iris_vidc.c | 2 +- 9 files changed, 34 insertions(+), 38 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 9aa84a1d8f950..a27447eb25199 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -112,6 +112,8 @@ struct iris_hfi_sys_ops { int (*sys_pc_prep)(struct iris_core *core); void (*sys_hfi_response_handler)(struct iris_core *core); + + struct iris_inst *(*sys_get_instance)(void); }; struct iris_hfi_session_ops { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h index 38e9d262d7df4..c37adf65055a5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h @@ -7,10 +7,8 @@ #define __IRIS_HFI_GEN1_H__ struct iris_core; -struct iris_inst; void iris_hfi_gen1_sys_ops_init(struct iris_core *core); void iris_hfi_gen1_response_handler(struct iris_core *core); -struct iris_inst *iris_hfi_gen1_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 26b7feb05d15b..0017ade4adbd9 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1076,6 +1076,19 @@ static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_close = iris_hfi_gen1_session_close, }; +static struct iris_inst *iris_hfi_gen1_get_instance(void) +{ + struct iris_inst *out; + + out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->hfi_session_ops = &iris_hfi_gen1_session_ops; + + return out; +} + static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { .sys_init = iris_hfi_gen1_sys_init, .sys_image_version = iris_hfi_gen1_sys_image_version, @@ -1083,22 +1096,11 @@ static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, .sys_hfi_response_handler = iris_hfi_gen1_response_handler, + + .sys_get_instance = iris_hfi_gen1_get_instance, }; void iris_hfi_gen1_sys_ops_init(struct iris_core *core) { core->hfi_sys_ops = &iris_hfi_gen1_sys_ops; } - -struct iris_inst *iris_hfi_gen1_get_instance(void) -{ - struct iris_inst *out; - - out = kzalloc_obj(*out); - if (!out) - return NULL; - - out->hfi_session_ops = &iris_hfi_gen1_session_ops; - - return out; -} diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h index 6cc6d9890c128..21ab58e0aa840 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h @@ -36,6 +36,5 @@ struct iris_inst_hfi_gen2 { void iris_hfi_gen2_sys_ops_init(struct iris_core *core); void iris_hfi_gen2_response_handler(struct iris_core *core); -struct iris_inst *iris_hfi_gen2_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 0c98d680bf094..639b75fca1abd 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1315,6 +1315,20 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_close = iris_hfi_gen2_session_close, }; +static struct iris_inst *iris_hfi_gen2_get_instance(void) +{ + struct iris_inst_hfi_gen2 *out; + + /* The allocation is intentionally larger than struct iris_inst. */ + out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; + + return &out->inst; +} + static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { .sys_init = iris_hfi_gen2_sys_init, .sys_image_version = iris_hfi_gen2_sys_image_version, @@ -1322,23 +1336,11 @@ static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, .sys_hfi_response_handler = iris_hfi_gen2_response_handler, + + .sys_get_instance = iris_hfi_gen2_get_instance, }; void iris_hfi_gen2_sys_ops_init(struct iris_core *core) { core->hfi_sys_ops = &iris_hfi_gen2_sys_ops; } - -struct iris_inst *iris_hfi_gen2_get_instance(void) -{ - struct iris_inst_hfi_gen2 *out; - - /* The allocation is intentionally larger than struct iris_inst. */ - out = kzalloc_obj(*out); - if (!out) - return NULL; - - out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; - - return &out->inst; -} diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 35e375ed27ea4..5013b6f5ce453 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -214,7 +214,6 @@ enum platform_pm_domain_type { struct iris_platform_data { void (*init_hfi_ops)(struct iris_core *core); - struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; void (*set_preset_registers)(struct iris_core *core); diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 9eeb500c65d90..293834d6359b8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -333,7 +333,6 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { }; const struct iris_platform_data sm8250_data = { - .get_instance = iris_hfi_gen1_get_instance, .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, @@ -385,7 +384,6 @@ const struct iris_platform_data sm8250_data = { }; const struct iris_platform_data sc7280_data = { - .get_instance = iris_hfi_gen1_get_instance, .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 655098e260740..856caf46b9dfc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -1043,7 +1043,6 @@ const struct iris_platform_data kaanapali_data = { }; const struct iris_platform_data sm8550_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, @@ -1145,7 +1144,6 @@ const struct iris_platform_data sm8550_data = { * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, @@ -1240,7 +1238,6 @@ const struct iris_platform_data sm8650_data = { }; const struct iris_platform_data sm8750_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, @@ -1337,7 +1334,6 @@ const struct iris_platform_data sm8750_data = { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 64b1f6997dd4a..338e6738f35f1 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -156,7 +156,7 @@ int iris_open(struct file *filp) pm_runtime_put_sync(core->dev); - inst = core->iris_platform_data->get_instance(); + inst = core->hfi_sys_ops->sys_get_instance(); if (!inst) return -ENOMEM; From 3f392c78f33f6cd87d70fa336123f91c30f31a8b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:08 +0200 Subject: [PATCH 0592/1330] FROMLIST: media: qcom: iris: drop hw_response_timeout_val from platform data The HW response time is a constant between platforms. Remove it from the iris_platform_data structure and use it directly. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-7-eea672b03a95@oss.qualcomm.com/ Suggested-by: Vikash Garodia Reviewed-by: Vikash Garodia Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov (cherry picked from commit 4c7cde6bc964e8712375750703b9ca134761dc57) --- drivers/media/platform/qcom/iris/iris_core.c | 3 +-- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 - drivers/media/platform/qcom/iris/iris_platform_gen1.c | 2 -- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 6 ------ drivers/media/platform/qcom/iris/iris_utils.c | 5 +---- 5 files changed, 2 insertions(+), 15 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c index 7a901a310e757..48a5bd39d836f 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -29,14 +29,13 @@ void iris_core_deinit(struct iris_core *core) static int iris_wait_for_system_response(struct iris_core *core) { - u32 hw_response_timeout_val = core->iris_platform_data->hw_response_timeout; int ret; if (core->state == IRIS_CORE_ERROR) return -EIO; ret = wait_for_completion_timeout(&core->core_init_done, - msecs_to_jiffies(hw_response_timeout_val)); + msecs_to_jiffies(HW_RESPONSE_TIMEOUT_VALUE)); if (!ret) { core->state = IRIS_CORE_ERROR; return -ETIMEDOUT; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 5013b6f5ce453..193e249132c53 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -246,7 +246,6 @@ struct iris_platform_data { const struct tz_cp_config *tz_cp_config_data; u32 tz_cp_config_data_size; u32 core_arch; - u32 hw_response_timeout; struct ubwc_config_data *ubwc_config; u32 num_vpp_pipe; bool no_aon; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 293834d6359b8..6592c1ed9ca50 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -361,7 +361,6 @@ const struct iris_platform_data sm8250_data = { .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K, @@ -410,7 +409,6 @@ const struct iris_platform_data sc7280_data = { .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 1, .no_aon = true, .max_session_count = 16, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 856caf46b9dfc..deaf6248f7f9e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -959,7 +959,6 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { }; const struct iris_platform_data kaanapali_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu4x_buf_size, .vpu_ops = &iris_vpu4x_ops, @@ -989,7 +988,6 @@ const struct iris_platform_data kaanapali_data = { .tz_cp_config_data = tz_cp_config_kaanapali, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 2, .max_session_count = 16, @@ -1074,7 +1072,6 @@ const struct iris_platform_data sm8550_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, @@ -1175,7 +1172,6 @@ const struct iris_platform_data sm8650_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, @@ -1267,7 +1263,6 @@ const struct iris_platform_data sm8750_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, @@ -1363,7 +1358,6 @@ const struct iris_platform_data qcs8300_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 2, .max_session_count = 16, diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/platform/qcom/iris/iris_utils.c index cfc5b576ec56b..29b07d88507eb 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -55,16 +55,13 @@ void iris_helper_buffers_done(struct iris_inst *inst, unsigned int type, int iris_wait_for_session_response(struct iris_inst *inst, bool is_flush) { - struct iris_core *core = inst->core; - u32 hw_response_timeout_val; struct completion *done; int ret; - hw_response_timeout_val = core->iris_platform_data->hw_response_timeout; done = is_flush ? &inst->flush_completion : &inst->completion; mutex_unlock(&inst->lock); - ret = wait_for_completion_timeout(done, msecs_to_jiffies(hw_response_timeout_val)); + ret = wait_for_completion_timeout(done, msecs_to_jiffies(HW_RESPONSE_TIMEOUT_VALUE)); mutex_lock(&inst->lock); if (!ret) { iris_inst_change_state(inst, IRIS_INST_ERROR); From daf7a7ba5d576fc4bbe727cd8b0a3924868cbc3a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:09 +0200 Subject: [PATCH 0593/1330] FROMLIST: media: qcom: iris: split firmware_data from raw platform data Having firmware-related fields in platform data results in the tying platform data to the HFI firmware data rather than the actual hardware. For example, SM8450 uses Gen2 firmware, so currently its platform data should be placed next to the other gen2 platforms, although it has the VPU2.0 core, similar to the one found on SM8250 and SC7280 and so the hardware-specific platform data is also close to those devices. Split firmware data to a separate struct, separating hardware-related data from the firmware interfaces. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-8-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov (cherry picked from commit 101d5d9f641259a1df42858fbc7b9e64b24d7ee5) --- .../media/platform/qcom/iris/iris_buffer.c | 82 ++--- drivers/media/platform/qcom/iris/iris_core.h | 2 + drivers/media/platform/qcom/iris/iris_ctrls.c | 8 +- .../qcom/iris/iris_hfi_gen1_command.c | 8 +- .../qcom/iris/iris_hfi_gen2_command.c | 66 ++-- .../platform/qcom/iris/iris_platform_common.h | 89 +++-- .../platform/qcom/iris/iris_platform_gen1.c | 67 ++-- .../platform/qcom/iris/iris_platform_gen2.c | 320 +++--------------- drivers/media/platform/qcom/iris/iris_probe.c | 3 +- drivers/media/platform/qcom/iris/iris_vidc.c | 10 +- .../platform/qcom/iris/iris_vpu_common.c | 2 +- 11 files changed, 221 insertions(+), 436 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 68336824aee1d..762cdbf728b07 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -301,31 +301,31 @@ static void iris_fill_internal_buf_info(struct iris_inst *inst, void iris_get_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type = platform_data->enc_op_int_buf_tbl; - internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_op_int_buf_tbl; + internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } @@ -366,7 +366,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; u32 internal_buffer_count, i, j; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -374,19 +374,19 @@ int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->enc_op_int_buf_tbl; - internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_op_int_buf_tbl; + internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; } } @@ -442,7 +442,7 @@ int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris_buffe int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; struct iris_buffer *buffer, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -451,19 +451,19 @@ int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->enc_op_int_buf_tbl; - internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_op_int_buf_tbl; + internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; } } @@ -501,7 +501,7 @@ int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buf static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool force) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -510,19 +510,19 @@ static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - len = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + len = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - len = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + len = firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - len = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + len = firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->enc_op_int_buf_tbl; - len = platform_data->enc_op_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_op_int_buf_tbl; + len = firmware_data->enc_op_int_buf_tbl_size; } } @@ -595,17 +595,17 @@ static int iris_release_internal_buffers(struct iris_inst *inst, static int iris_release_input_internal_buffers(struct iris_inst *inst) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; int ret; if (inst->domain == DECODER) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; } for (i = 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 5f8668e1a16d7..7d128e7724ed1 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -55,6 +55,7 @@ enum domain_type { * @resets: table of iris reset clocks * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data + * @iris_firmware_data: a pointer to the firmware (or HFI) specific data * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory @@ -105,6 +106,7 @@ struct iris_core { struct reset_control_bulk_data *resets; struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; + const struct iris_firmware_data *iris_firmware_data; enum iris_core_state state; dma_addr_t iface_q_table_daddr; dma_addr_t sfr_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c index 5a24aa869b2dc..ef7adac3764d7 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -332,8 +332,8 @@ void iris_session_init_caps(struct iris_core *core) const struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; - caps = core->iris_platform_data->inst_fw_caps_dec; - num_cap = core->iris_platform_data->inst_fw_caps_dec_size; + caps = core->iris_firmware_data->inst_fw_caps_dec; + num_cap = core->iris_firmware_data->inst_fw_caps_dec_size; for (i = 0; i < num_cap; i++) { cap_id = caps[i].cap_id; @@ -360,8 +360,8 @@ void iris_session_init_caps(struct iris_core *core) } } - caps = core->iris_platform_data->inst_fw_caps_enc; - num_cap = core->iris_platform_data->inst_fw_caps_enc_size; + caps = core->iris_firmware_data->inst_fw_caps_enc; + num_cap = core->iris_firmware_data->inst_fw_caps_enc_size; for (i = 0; i < num_cap; i++) { cap_id = caps[i].cap_id; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 0017ade4adbd9..3fb90a466a64e 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1033,8 +1033,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p }; if (inst->domain == DECODER) { - config_params = core->iris_platform_data->dec_input_config_params_default; - config_params_size = core->iris_platform_data->dec_input_config_params_default_size; + config_params = core->iris_firmware_data->dec_input_config_params_default; + config_params_size = core->iris_firmware_data->dec_input_config_params_default_size; if (V4L2_TYPE_IS_OUTPUT(plane)) { handler = vdec_prop_type_handle_inp_arr; handler_size = ARRAY_SIZE(vdec_prop_type_handle_inp_arr); @@ -1043,8 +1043,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p handler_size = ARRAY_SIZE(vdec_prop_type_handle_out_arr); } } else { - config_params = core->iris_platform_data->enc_input_config_params; - config_params_size = core->iris_platform_data->enc_input_config_params_size; + config_params = core->iris_firmware_data->enc_input_config_params; + config_params_size = core->iris_firmware_data->enc_input_config_params_size; handler = venc_prop_type_handle_inp_arr; handler_size = ARRAY_SIZE(venc_prop_type_handle_inp_arr); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 639b75fca1abd..c90b22a75bc56 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -601,7 +601,7 @@ static int iris_hfi_gen2_set_super_block(struct iris_inst *inst, u32 plane) static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *pdata = inst->core->iris_platform_data; + const struct iris_firmware_data *fdata = inst->core->iris_firmware_data; u32 config_params_size = 0, i, j; const u32 *config_params = NULL; int ret; @@ -630,31 +630,31 @@ static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 p if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { if (inst->codec == V4L2_PIX_FMT_H264) { - config_params = pdata->dec_input_config_params_default; - config_params_size = pdata->dec_input_config_params_default_size; + config_params = fdata->dec_input_config_params_default; + config_params_size = fdata->dec_input_config_params_default_size; } else if (inst->codec == V4L2_PIX_FMT_HEVC) { - config_params = pdata->dec_input_config_params_hevc; - config_params_size = pdata->dec_input_config_params_hevc_size; + config_params = fdata->dec_input_config_params_hevc; + config_params_size = fdata->dec_input_config_params_hevc_size; } else if (inst->codec == V4L2_PIX_FMT_VP9) { - config_params = pdata->dec_input_config_params_vp9; - config_params_size = pdata->dec_input_config_params_vp9_size; + config_params = fdata->dec_input_config_params_vp9; + config_params_size = fdata->dec_input_config_params_vp9_size; } else if (inst->codec == V4L2_PIX_FMT_AV1) { - config_params = pdata->dec_input_config_params_av1; - config_params_size = pdata->dec_input_config_params_av1_size; + config_params = fdata->dec_input_config_params_av1; + config_params_size = fdata->dec_input_config_params_av1_size; } else { return -EINVAL; } } else { - config_params = pdata->dec_output_config_params; - config_params_size = pdata->dec_output_config_params_size; + config_params = fdata->dec_output_config_params; + config_params_size = fdata->dec_output_config_params_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - config_params = pdata->enc_input_config_params; - config_params_size = pdata->enc_input_config_params_size; + config_params = fdata->enc_input_config_params; + config_params_size = fdata->enc_input_config_params_size; } else { - config_params = pdata->enc_output_config_params; - config_params_size = pdata->enc_output_config_params_size; + config_params = fdata->enc_output_config_params; + config_params_size = fdata->enc_output_config_params_size; } } @@ -849,24 +849,24 @@ static int iris_hfi_gen2_subscribe_change_param(struct iris_inst *inst, u32 plan switch (inst->codec) { case V4L2_PIX_FMT_H264: - change_param = core->iris_platform_data->dec_input_config_params_default; + change_param = core->iris_firmware_data->dec_input_config_params_default; change_param_size = - core->iris_platform_data->dec_input_config_params_default_size; + core->iris_firmware_data->dec_input_config_params_default_size; break; case V4L2_PIX_FMT_HEVC: - change_param = core->iris_platform_data->dec_input_config_params_hevc; + change_param = core->iris_firmware_data->dec_input_config_params_hevc; change_param_size = - core->iris_platform_data->dec_input_config_params_hevc_size; + core->iris_firmware_data->dec_input_config_params_hevc_size; break; case V4L2_PIX_FMT_VP9: - change_param = core->iris_platform_data->dec_input_config_params_vp9; + change_param = core->iris_firmware_data->dec_input_config_params_vp9; change_param_size = - core->iris_platform_data->dec_input_config_params_vp9_size; + core->iris_firmware_data->dec_input_config_params_vp9_size; break; case V4L2_PIX_FMT_AV1: - change_param = core->iris_platform_data->dec_input_config_params_av1; + change_param = core->iris_firmware_data->dec_input_config_params_av1; change_param_size = - core->iris_platform_data->dec_input_config_params_av1_size; + core->iris_firmware_data->dec_input_config_params_av1_size; break; } @@ -996,29 +996,29 @@ static int iris_hfi_gen2_subscribe_property(struct iris_inst *inst, u32 plane) return 0; if (V4L2_TYPE_IS_OUTPUT(plane)) { - subscribe_prop_size = core->iris_platform_data->dec_input_prop_size; - subcribe_prop = core->iris_platform_data->dec_input_prop; + subscribe_prop_size = core->iris_firmware_data->dec_input_prop_size; + subcribe_prop = core->iris_firmware_data->dec_input_prop; } else { switch (inst->codec) { case V4L2_PIX_FMT_H264: - subcribe_prop = core->iris_platform_data->dec_output_prop_avc; + subcribe_prop = core->iris_firmware_data->dec_output_prop_avc; subscribe_prop_size = - core->iris_platform_data->dec_output_prop_avc_size; + core->iris_firmware_data->dec_output_prop_avc_size; break; case V4L2_PIX_FMT_HEVC: - subcribe_prop = core->iris_platform_data->dec_output_prop_hevc; + subcribe_prop = core->iris_firmware_data->dec_output_prop_hevc; subscribe_prop_size = - core->iris_platform_data->dec_output_prop_hevc_size; + core->iris_firmware_data->dec_output_prop_hevc_size; break; case V4L2_PIX_FMT_VP9: - subcribe_prop = core->iris_platform_data->dec_output_prop_vp9; + subcribe_prop = core->iris_firmware_data->dec_output_prop_vp9; subscribe_prop_size = - core->iris_platform_data->dec_output_prop_vp9_size; + core->iris_firmware_data->dec_output_prop_vp9_size; break; case V4L2_PIX_FMT_AV1: - subcribe_prop = core->iris_platform_data->dec_output_prop_av1; + subcribe_prop = core->iris_firmware_data->dec_output_prop_av1; subscribe_prop_size = - core->iris_platform_data->dec_output_prop_av1_size; + core->iris_firmware_data->dec_output_prop_av1_size; break; } } diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 193e249132c53..4dd17aed12606 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -212,48 +212,16 @@ enum platform_pm_domain_type { IRIS_APV_HW_POWER_DOMAIN, }; -struct iris_platform_data { +struct iris_firmware_data { void (*init_hfi_ops)(struct iris_core *core); - u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); - const struct vpu_ops *vpu_ops; - void (*set_preset_registers)(struct iris_core *core); - int (*init_cb_devs)(struct iris_core *core); - void (*deinit_cb_devs)(struct iris_core *core); - const struct icc_info *icc_tbl; - unsigned int icc_tbl_size; - const struct bw_info *bw_tbl_dec; - unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; - const char * const *opp_pd_tbl; - unsigned int opp_pd_tbl_size; - const struct platform_clk_data *clk_tbl; - const char * const *opp_clk_tbl; - unsigned int clk_tbl_size; - const char * const *clk_rst_tbl; - unsigned int clk_rst_tbl_size; - const char * const *controller_rst_tbl; - unsigned int controller_rst_tbl_size; - u64 dma_mask; - const char *fwname; - struct iris_fmt *inst_iris_fmts; - u32 inst_iris_fmts_size; - struct platform_inst_caps *inst_caps; + + u32 core_arch; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; - const struct tz_cp_config *tz_cp_config_data; - u32 tz_cp_config_data_size; - u32 core_arch; - struct ubwc_config_data *ubwc_config; - u32 num_vpp_pipe; - bool no_aon; - u32 max_session_count; - /* max number of macroblocks per frame supported */ - u32 max_core_mbpf; - /* max number of macroblocks per second supported */ - u32 max_core_mbps; + const u32 *dec_input_config_params_default; unsigned int dec_input_config_params_default_size; const u32 *dec_input_config_params_hevc; @@ -268,6 +236,7 @@ struct iris_platform_data { unsigned int enc_input_config_params_size; const u32 *enc_output_config_params; unsigned int enc_output_config_params_size; + const u32 *dec_input_prop; unsigned int dec_input_prop_size; const u32 *dec_output_prop_avc; @@ -278,6 +247,7 @@ struct iris_platform_data { unsigned int dec_output_prop_vp9_size; const u32 *dec_output_prop_av1; unsigned int dec_output_prop_av1_size; + const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; @@ -288,4 +258,49 @@ struct iris_platform_data { unsigned int enc_op_int_buf_tbl_size; }; +struct iris_platform_data { + /* + * XXX: remove firmware_data pointer and consider moving + * get_vpu_buffer_size pointer once we have platforms supporting both + * firmware kinds. + */ + const struct iris_firmware_data *firmware_data; + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); + + const struct vpu_ops *vpu_ops; + void (*set_preset_registers)(struct iris_core *core); + int (*init_cb_devs)(struct iris_core *core); + void (*deinit_cb_devs)(struct iris_core *core); + const struct icc_info *icc_tbl; + unsigned int icc_tbl_size; + const struct bw_info *bw_tbl_dec; + unsigned int bw_tbl_dec_size; + const char * const *pmdomain_tbl; + unsigned int pmdomain_tbl_size; + const char * const *opp_pd_tbl; + unsigned int opp_pd_tbl_size; + const struct platform_clk_data *clk_tbl; + const char * const *opp_clk_tbl; + unsigned int clk_tbl_size; + const char * const *clk_rst_tbl; + unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; + u64 dma_mask; + const char *fwname; + struct iris_fmt *inst_iris_fmts; + u32 inst_iris_fmts_size; + struct platform_inst_caps *inst_caps; + const struct tz_cp_config *tz_cp_config_data; + u32 tz_cp_config_data_size; + struct ubwc_config_data *ubwc_config; + u32 num_vpp_pipe; + bool no_aon; + u32 max_session_count; + /* max number of macroblocks per frame supported */ + u32 max_core_mbpf; + /* max number of macroblocks per second supported */ + u32 max_core_mbps; +}; + #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 6592c1ed9ca50..9e632a973f476 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -332,8 +332,33 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { BUF_SCRATCH_2, }; -const struct iris_platform_data sm8250_data = { +const struct iris_firmware_data iris_hfi_gen1_data = { .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, + + .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), + + .dec_input_config_params_default = + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params = sm8250_venc_input_config_param, + .enc_input_config_params_size = + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; + +const struct iris_platform_data sm8250_data = { + .firmware_data = &iris_hfi_gen1_data, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -355,35 +380,16 @@ const struct iris_platform_data sm8250_data = { .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, - .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K, .max_core_mbps = ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default = - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params = sm8250_venc_input_config_param, - .enc_input_config_params_size = - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; const struct iris_platform_data sc7280_data = { - .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, + .firmware_data = &iris_hfi_gen1_data, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -403,10 +409,6 @@ const struct iris_platform_data sc7280_data = { .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, - .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), .num_vpp_pipe = 1, @@ -415,19 +417,4 @@ const struct iris_platform_data sc7280_data = { .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ .max_core_mbps = 4096 * 2176 / 256 * 60, - .dec_input_config_params_default = - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params = sm8250_venc_input_config_param, - .enc_input_config_params_size = - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index deaf6248f7f9e..b83a2af4cb7d4 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -958,41 +958,16 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { BUF_SCRATCH_2, }; -const struct iris_platform_data kaanapali_data = { +const struct iris_firmware_data iris_hfi_gen2_data = { .init_hfi_ops = iris_hfi_gen2_sys_ops_init, - .get_vpu_buffer_size = iris_vpu4x_buf_size, - .vpu_ops = &iris_vpu4x_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = kaanapali_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = kaanapali_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = kaanapali_clk_table, - .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), - .opp_clk_tbl = kaanapali_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu40_p2_s7.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, + + .core_arch = VIDEO_ARCH_LX, + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data = tz_cp_config_kaanapali, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), - .core_arch = VIDEO_ARCH_LX, - .ubwc_config = &ubwc_config_sm8550, - .num_vpp_pipe = 2, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((8192 * 4352) / 256) * 60, + .dec_input_config_params_default = sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size = @@ -1005,6 +980,10 @@ const struct iris_platform_data kaanapali_data = { sm8550_vdec_input_config_param_vp9, .dec_input_config_params_vp9_size = ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 = + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), .dec_output_config_params = sm8550_vdec_output_config_params, .dec_output_config_params_size = @@ -1030,18 +1009,55 @@ const struct iris_platform_data kaanapali_data = { .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, .dec_output_prop_vp9_size = ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; +const struct iris_platform_data kaanapali_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu4x_buf_size, + .vpu_ops = &iris_vpu4x_ops, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = kaanapali_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = kaanapali_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = kaanapali_clk_table, + .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), + .opp_clk_tbl = kaanapali_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu40_p2_s7.mbn", + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_kaanapali, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 2, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4352) / 256) * 60, +}; + const struct iris_platform_data sm8550_data = { - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .init_cb_devs = sm8550_init_cb_devs, @@ -1065,72 +1081,13 @@ const struct iris_platform_data sm8550_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, - .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch = VIDEO_ARCH_LX, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default = - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc = - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 = - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 = - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params = - sm8550_vdec_output_config_params, - .dec_output_config_params_size = - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params = - sm8550_venc_input_config_params, - .enc_input_config_params_size = - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params = - sm8550_venc_output_config_params, - .enc_output_config_params_size = - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop = sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), - .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; /* @@ -1141,7 +1098,7 @@ const struct iris_platform_data sm8550_data = { * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, .icc_tbl = sm8550_icc_table, @@ -1165,76 +1122,17 @@ const struct iris_platform_data sm8650_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, - .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch = VIDEO_ARCH_LX, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default = - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc = - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 = - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 = - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params = - sm8550_vdec_output_config_params, - .dec_output_config_params_size = - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params = - sm8550_venc_input_config_params, - .enc_input_config_params_size = - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params = - sm8550_venc_output_config_params, - .enc_output_config_params_size = - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop = sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), - .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; const struct iris_platform_data sm8750_data = { - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, .icc_tbl = sm8550_icc_table, @@ -1256,72 +1154,13 @@ const struct iris_platform_data sm8750_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, - .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch = VIDEO_ARCH_LX, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default = - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc = - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 = - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 = - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params = - sm8550_vdec_output_config_params, - .dec_output_config_params_size = - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params = - sm8550_venc_input_config_params, - .enc_input_config_params_size = - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params = - sm8550_venc_output_config_params, - .enc_output_config_params_size = - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop = sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), - .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; /* @@ -1329,7 +1168,7 @@ const struct iris_platform_data sm8750_data = { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .icc_tbl = sm8550_icc_table, @@ -1351,70 +1190,11 @@ const struct iris_platform_data qcs8300_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_qcs8300, - .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch = VIDEO_ARCH_LX, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 2, .max_session_count = 16, .max_core_mbpf = ((4096 * 2176) / 256) * 4, .max_core_mbps = (((3840 * 2176) / 256) * 120), - .dec_input_config_params_default = - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc = - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 = - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 = - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params = - sm8550_vdec_output_config_params, - .dec_output_config_params_size = - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params = - sm8550_venc_input_config_params, - .enc_input_config_params_size = - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params = - sm8550_venc_output_config_params, - .enc_output_config_params_size = - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop = sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), - .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index dbc99f6a0ebe8..62725cfdb7a9f 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -258,6 +258,7 @@ static int iris_probe(struct platform_device *pdev) return core->irq; core->iris_platform_data = of_device_get_match_data(core->dev); + core->iris_firmware_data = core->iris_platform_data->firmware_data; ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr, iris_hfi_isr_handler, IRQF_TRIGGER_HIGH, "iris", core); @@ -267,7 +268,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); iris_init_ops(core); - core->iris_platform_data->init_hfi_ops(core); + core->iris_firmware_data->init_hfi_ops(core); ret = iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 338e6738f35f1..26df872fb4fa1 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -243,7 +243,7 @@ static void iris_session_close(struct iris_inst *inst) static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -251,11 +251,11 @@ static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 p u32 count = 0; if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; } for (i = 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index aa0b66954680d..ca96e91222c67 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -63,7 +63,7 @@ static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core) writel(QTBL_ENABLE, core->reg_base + QTBL_INFO); if (core->sfr_daddr) { - value = (u32)core->sfr_daddr + core->iris_platform_data->core_arch; + value = (u32)core->sfr_daddr + core->iris_firmware_data->core_arch; writel(value, core->reg_base + SFR_ADDR); } From 807f19ca910a6660113fe2b9f7b903be63617519 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:10 +0200 Subject: [PATCH 0594/1330] FROMLIST: media: qcom: iris: split platform data from firmware data Finalize the logical separation of the software and hardware interface descriptions by moving hardware properties to the files specific to the particular VPU version. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-9-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov (cherry picked from commit bb7434ba065d3a4c2e580ae2f1192b8cf3bec969) --- drivers/media/platform/qcom/iris/Makefile | 7 +- .../{iris_platform_gen1.c => iris_hfi_gen1.c} | 134 -------- .../{iris_platform_gen2.c => iris_hfi_gen2.c} | 304 ------------------ .../platform/qcom/iris/iris_platform_common.h | 3 + .../platform/qcom/iris/iris_platform_sm8250.h | 29 ++ .../platform/qcom/iris/iris_platform_sm8550.h | 31 ++ .../platform/qcom/iris/iris_platform_vpu2.c | 124 +++++++ .../platform/qcom/iris/iris_platform_vpu3x.c | 261 +++++++++++++++ .../platform/qcom/iris/iris_platform_vpu4x.c | 104 ++++++ 9 files changed, 557 insertions(+), 440 deletions(-) rename drivers/media/platform/qcom/iris/{iris_platform_gen1.c => iris_hfi_gen1.c} (67%) rename drivers/media/platform/qcom/iris/{iris_platform_gen2.c => iris_hfi_gen2.c} (71%) create mode 100644 drivers/media/platform/qcom/iris/iris_platform_sm8250.h create mode 100644 drivers/media/platform/qcom/iris/iris_platform_sm8550.h create mode 100644 drivers/media/platform/qcom/iris/iris_platform_vpu2.c create mode 100644 drivers/media/platform/qcom/iris/iris_platform_vpu3x.c create mode 100644 drivers/media/platform/qcom/iris/iris_platform_vpu4x.c diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 2fde45f817276..f8a017d878d62 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -4,14 +4,17 @@ qcom-iris-objs += iris_buffer.o \ iris_ctrls.o \ iris_firmware.o \ iris_hfi_common.o \ + iris_hfi_gen1.o \ iris_hfi_gen1_command.o \ iris_hfi_gen1_response.o \ + iris_hfi_gen2.o \ iris_hfi_gen2_command.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_gen1.o \ - iris_platform_gen2.o \ + iris_platform_vpu2.o \ + iris_platform_vpu3x.o \ + iris_platform_vpu4x.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c similarity index 67% rename from drivers/media/platform/qcom/iris/iris_platform_gen1.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen1.c index 9e632a973f476..60f51a1ba9412 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -3,38 +3,16 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_platform_common.h" -#include "iris_resources.h" #include "iris_hfi_gen1.h" #include "iris_hfi_gen1_defines.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" -#include "iris_instance.h" - -#include "iris_platform_sc7280.h" #define BITRATE_MIN 32000 #define BITRATE_MAX 160000000 -#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 -static struct iris_fmt platform_fmts_sm8250_dec[] = { - [IRIS_FMT_H264] = { - .pixfmt = V4L2_PIX_FMT_H264, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] = { - .pixfmt = V4L2_PIX_FMT_HEVC, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] = { - .pixfmt = V4L2_PIX_FMT_VP9, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = { { .cap_id = PIPE, @@ -248,56 +226,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = { }, }; -static struct platform_inst_caps platform_inst_cap_sm8250 = { - .min_frame_width = 128, - .max_frame_width = 8192, - .min_frame_height = 128, - .max_frame_height = 8192, - .max_mbpf = 138240, - .mb_cycles_vsp = 25, - .mb_cycles_vpp = 200, - .max_frame_rate = MAXIMUM_FPS, - .max_operating_rate = MAXIMUM_FPS, -}; - -static const struct icc_info sm8250_icc_table[] = { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8250_clk_reset_table[] = { "bus", "core" }; - -static const struct bw_info sm8250_bw_table_dec[] = { - { ((4096 * 2160) / 256) * 60, 2403000 }, - { ((4096 * 2160) / 256) * 30, 1224000 }, - { ((1920 * 1080) / 256) * 60, 812000 }, - { ((1920 * 1080) / 256) * 30, 416000 }, -}; - -static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" }; - -static const char * const sm8250_opp_pd_table[] = { "mx" }; - -static const struct platform_clk_data sm8250_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8250_opp_clk_table[] = { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8250[] = { - { - .cp_start = 0, - .cp_size = 0x25800000, - .cp_nonpixel_start = 0x01000000, - .cp_nonpixel_size = 0x24800000, - }, -}; - static const u32 sm8250_vdec_input_config_param_default[] = { HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, @@ -356,65 +284,3 @@ const struct iris_firmware_data iris_hfi_gen1_data = { .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; - -const struct iris_platform_data sm8250_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu2_ops, - .icc_tbl = sm8250_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), - .clk_rst_tbl = sm8250_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table), - .bw_tbl_dec = sm8250_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl = sm8250_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl = sm8250_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), - .clk_tbl = sm8250_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table), - .opp_clk_tbl = sm8250_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu-1.0/venus.mbn", - .inst_iris_fmts = platform_fmts_sm8250_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps = &platform_inst_cap_sm8250, - .tz_cp_config_data = tz_cp_config_sm8250, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sc7280_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu2_ops, - .icc_tbl = sm8250_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), - .bw_tbl_dec = sc7280_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl = sm8250_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl = sc7280_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), - .clk_tbl = sc7280_clk_table, - .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table), - .opp_clk_tbl = sc7280_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu20_p1.mbn", - .inst_iris_fmts = platform_fmts_sm8250_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps = &platform_inst_cap_sm8250, - .tz_cp_config_data = tz_cp_config_sm8250, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), - .num_vpp_pipe = 1, - .no_aon = true, - .max_session_count = 16, - .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, - /* max spec for SC7280 is 4096x2176@60fps */ - .max_core_mbps = 4096 * 2176 / 256 * 60, -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c similarity index 71% rename from drivers/media/platform/qcom/iris/iris_platform_gen2.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen2.c index b83a2af4cb7d4..ce8490d64854c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c @@ -4,41 +4,15 @@ * Copyright (c) 2025 Linaro Ltd */ -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_hfi_gen2.h" #include "iris_hfi_gen2_defines.h" #include "iris_platform_common.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" - -#include "iris_platform_kaanapali.h" -#include "iris_platform_qcs8300.h" -#include "iris_platform_sm8650.h" -#include "iris_platform_sm8750.h" #define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 -static struct iris_fmt platform_fmts_sm8550_dec[] = { - [IRIS_FMT_H264] = { - .pixfmt = V4L2_PIX_FMT_H264, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] = { - .pixfmt = V4L2_PIX_FMT_HEVC, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] = { - .pixfmt = V4L2_PIX_FMT_VP9, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_AV1] = { - .pixfmt = V4L2_PIX_FMT_AV1, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = { { .cap_id = PROFILE_H264, @@ -743,109 +717,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = { }, }; -static struct platform_inst_caps platform_inst_cap_sm8550 = { - .min_frame_width = 96, - .max_frame_width = 8192, - .min_frame_height = 96, - .max_frame_height = 8192, - .max_mbpf = (8192 * 4352) / 256, - .mb_cycles_vpp = 200, - .mb_cycles_fw = 489583, - .mb_cycles_fw_vpp = 66234, - .num_comv = 0, - .max_frame_rate = MAXIMUM_FPS, - .max_operating_rate = MAXIMUM_FPS, -}; - -static int sm8550_init_cb_devs(struct iris_core *core) -{ - const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ - const u32 f_id_p = 1; /* IRIS_PIXEL */ - struct device *dev; - - dev = iris_create_cb_dev(core, "iris_non_pixel", &f_id_np); - if (IS_ERR(dev)) - return PTR_ERR(dev); - - core->dev_np = dev; - core->dev_bs = core->dev_np; - - dev = iris_create_cb_dev(core, "iris_pixel", &f_id_p); - if (IS_ERR(dev)) - goto err_unreg_dev_np; - - core->dev_p = dev; - - return 0; - -err_unreg_dev_np: - platform_device_unregister(to_platform_device(core->dev_np)); - core->dev_np = NULL; - core->dev_bs = NULL; - - return PTR_ERR(dev); -} - -static void sm8550_deinit_cb_devs(struct iris_core *core) -{ - if (core->dev_np) - platform_device_unregister(to_platform_device(core->dev_np)); - if (core->dev_p) - platform_device_unregister(to_platform_device(core->dev_p)); - - core->dev_np = NULL; - core->dev_bs = NULL; - core->dev_p = NULL; -} - -static const struct icc_info sm8550_icc_table[] = { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8550_clk_reset_table[] = { "bus" }; - -static const struct bw_info sm8550_bw_table_dec[] = { - { ((4096 * 2160) / 256) * 60, 1608000 }, - { ((4096 * 2160) / 256) * 30, 826000 }, - { ((1920 * 1080) / 256) * 60, 567000 }, - { ((1920 * 1080) / 256) * 30, 294000 }, -}; - -static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" }; - -static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" }; - -static const struct platform_clk_data sm8550_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8550_opp_clk_table[] = { - "vcodec0_core", - NULL, -}; - -static struct ubwc_config_data ubwc_config_sm8550 = { - .max_channels = 8, - .mal_length = 32, - .highest_bank_bit = 16, - .bank_swzl_level = 0, - .bank_swz2_level = 1, - .bank_swz3_level = 1, - .bank_spreading = 1, -}; - -static const struct tz_cp_config tz_cp_config_sm8550[] = { - { - .cp_start = 0, - .cp_size = 0x25800000, - .cp_nonpixel_start = 0x01000000, - .cp_nonpixel_size = 0x24800000, - }, -}; - static const u32 sm8550_vdec_input_config_params_default[] = { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, @@ -1023,178 +894,3 @@ const struct iris_firmware_data iris_hfi_gen2_data = { .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; - -const struct iris_platform_data kaanapali_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu4x_buf_size, - .vpu_ops = &iris_vpu4x_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = kaanapali_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = kaanapali_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = kaanapali_clk_table, - .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), - .opp_clk_tbl = kaanapali_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu40_p2_s7.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_kaanapali, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), - .ubwc_config = &ubwc_config_sm8550, - .num_vpp_pipe = 2, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((8192 * 4352) / 256) * 60, -}; - -const struct iris_platform_data sm8550_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu3_ops, - .init_cb_devs = sm8550_init_cb_devs, - .deinit_cb_devs = sm8550_deinit_cb_devs, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8550_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .ubwc_config = &ubwc_config_sm8550, - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - vpu_ops to iris_vpu33_ops - * - clk_rst_tbl to sm8650_clk_reset_table - * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" - */ -const struct iris_platform_data sm8650_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, - .vpu_ops = &iris_vpu33_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8650_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table), - .controller_rst_tbl = sm8650_controller_reset_table, - .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu33_p4.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .ubwc_config = &ubwc_config_sm8550, - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sm8750_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, - .vpu_ops = &iris_vpu35_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8750_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8750_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu35_p4.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .ubwc_config = &ubwc_config_sm8550, - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - inst_caps to platform_inst_cap_qcs8300 - */ -const struct iris_platform_data qcs8300_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu3_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8550_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4_s6.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_qcs8300, - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .ubwc_config = &ubwc_config_sm8550, - .num_vpp_pipe = 2, - .max_session_count = 16, - .max_core_mbpf = ((4096 * 2176) / 256) * 4, - .max_core_mbps = (((3840 * 2176) / 256) * 120), -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 4dd17aed12606..acf8c5be4940c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -40,6 +40,9 @@ enum pipe_type { PIPE_4 = 4, }; +extern const struct iris_firmware_data iris_hfi_gen1_data; +extern const struct iris_firmware_data iris_hfi_gen2_data; + extern const struct iris_platform_data kaanapali_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h new file mode 100644 index 0000000000000..50306043eb8ec --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __IRIS_PLATFORM_SM8250_H__ +#define __IRIS_PLATFORM_SM8250_H__ + +static const struct bw_info sm8250_bw_table_dec[] = { + { ((4096 * 2160) / 256) * 60, 2403000 }, + { ((4096 * 2160) / 256) * 30, 1224000 }, + { ((1920 * 1080) / 256) * 60, 812000 }, + { ((1920 * 1080) / 256) * 30, 416000 }, +}; + +static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" }; + +static const struct platform_clk_data sm8250_clk_table[] = { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static const char * const sm8250_opp_clk_table[] = { + "vcodec0_core", + NULL, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h new file mode 100644 index 0000000000000..a9d9709c2e352 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_SM8550_H__ +#define __IRIS_PLATFORM_SM8550_H__ + +static const char * const sm8550_clk_reset_table[] = { "bus" }; + +static const struct platform_clk_data sm8550_clk_table[] = { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static struct platform_inst_caps platform_inst_cap_sm8550 = { + .min_frame_width = 96, + .max_frame_width = 8192, + .min_frame_height = 96, + .max_frame_height = 8192, + .max_mbpf = (8192 * 4352) / 256, + .mb_cycles_vpp = 200, + .mb_cycles_fw = 489583, + .mb_cycles_fw_vpp = 66234, + .num_comv = 0, + .max_frame_rate = MAXIMUM_FPS, + .max_operating_rate = MAXIMUM_FPS, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c new file mode 100644 index 0000000000000..ab2a19aa9c36c --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_platform_common.h" +#include "iris_resources.h" +#include "iris_hfi_gen1.h" +#include "iris_hfi_gen1_defines.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" +#include "iris_instance.h" + +#include "iris_platform_sc7280.h" +#include "iris_platform_sm8250.h" + +static struct iris_fmt iris_fmts_vpu2_dec[] = { + [IRIS_FMT_H264] = { + .pixfmt = V4L2_PIX_FMT_H264, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] = { + .pixfmt = V4L2_PIX_FMT_HEVC, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] = { + .pixfmt = V4L2_PIX_FMT_VP9, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static struct platform_inst_caps platform_inst_cap_vpu2 = { + .min_frame_width = 128, + .max_frame_width = 8192, + .min_frame_height = 128, + .max_frame_height = 8192, + .max_mbpf = 138240, + .mb_cycles_vsp = 25, + .mb_cycles_vpp = 200, + .max_frame_rate = MAXIMUM_FPS, + .max_operating_rate = MAXIMUM_FPS, +}; + +static const struct icc_info iris_icc_info_vpu2[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" }; + +static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" }; + +static const struct tz_cp_config tz_cp_config_vpu2[] = { + { + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x01000000, + .cp_nonpixel_size = 0x24800000, + }, +}; + +const struct iris_platform_data sc7280_data = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu2_ops, + .icc_tbl = iris_icc_info_vpu2, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), + .bw_tbl_dec = sc7280_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), + .pmdomain_tbl = iris_pmdomain_table_vpu2, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), + .opp_pd_tbl = sc7280_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), + .clk_tbl = sc7280_clk_table, + .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table), + .opp_clk_tbl = sc7280_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu20_p1.mbn", + .inst_iris_fmts = iris_fmts_vpu2_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), + .inst_caps = &platform_inst_cap_vpu2, + .tz_cp_config_data = tz_cp_config_vpu2, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), + .num_vpp_pipe = 1, + .no_aon = true, + .max_session_count = 16, + .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, + /* max spec for SC7280 is 4096x2176@60fps */ + .max_core_mbps = 4096 * 2176 / 256 * 60, +}; + +const struct iris_platform_data sm8250_data = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu2_ops, + .icc_tbl = iris_icc_info_vpu2, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), + .clk_rst_tbl = iris_clk_reset_table_vpu2, + .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2), + .bw_tbl_dec = sm8250_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), + .pmdomain_tbl = iris_pmdomain_table_vpu2, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), + .opp_pd_tbl = sm8250_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), + .clk_tbl = sm8250_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table), + .opp_clk_tbl = sm8250_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu-1.0/venus.mbn", + .inst_iris_fmts = iris_fmts_vpu2_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), + .inst_caps = &platform_inst_cap_vpu2, + .tz_cp_config_data = tz_cp_config_vpu2, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c new file mode 100644 index 0000000000000..f5cf933c3d445 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Linaro Ltd + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#include "iris_platform_qcs8300.h" +#include "iris_platform_sm8550.h" +#include "iris_platform_sm8650.h" +#include "iris_platform_sm8750.h" + +static struct iris_fmt iris_fmts_vpu3x_dec[] = { + [IRIS_FMT_H264] = { + .pixfmt = V4L2_PIX_FMT_H264, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] = { + .pixfmt = V4L2_PIX_FMT_HEVC, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] = { + .pixfmt = V4L2_PIX_FMT_VP9, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_AV1] = { + .pixfmt = V4L2_PIX_FMT_AV1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static const struct icc_info iris_icc_info_vpu3x[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const struct bw_info iris_bw_table_dec_vpu3x[] = { + { ((4096 * 2160) / 256) * 60, 1608000 }, + { ((4096 * 2160) / 256) * 30, 826000 }, + { ((1920 * 1080) / 256) * 60, 567000 }, + { ((1920 * 1080) / 256) * 30, 294000 }, +}; + +static const char * const iris_pmdomain_table_vpu3x[] = { "venus", "vcodec0" }; + +static const char * const iris_opp_pd_table_vpu3x[] = { "mxc", "mmcx" }; + +static const char * const iris_opp_clk_table_vpu3x[] = { + "vcodec0_core", + NULL, +}; + +static struct ubwc_config_data iris_ubwc_config_vpu3x = { + .max_channels = 8, + .mal_length = 32, + .highest_bank_bit = 16, + .bank_swzl_level = 0, + .bank_swz2_level = 1, + .bank_swz3_level = 1, + .bank_spreading = 1, +}; + +static const struct tz_cp_config tz_cp_config_vpu3[] = { + { + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x01000000, + .cp_nonpixel_size = 0x24800000, + }, +}; + +static int sm8550_init_cb_devs(struct iris_core *core) +{ + const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ + const u32 f_id_p = 1; /* IRIS_PIXEL */ + struct device *dev; + + dev = iris_create_cb_dev(core, "iris_non_pixel", &f_id_np); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + core->dev_np = dev; + core->dev_bs = core->dev_np; + + dev = iris_create_cb_dev(core, "iris_pixel", &f_id_p); + if (IS_ERR(dev)) + goto err_unreg_dev_np; + + core->dev_p = dev; + + return 0; + +err_unreg_dev_np: + platform_device_unregister(to_platform_device(core->dev_np)); + core->dev_np = NULL; + core->dev_bs = NULL; + + return PTR_ERR(dev); +} + +static void sm8550_deinit_cb_devs(struct iris_core *core) +{ + if (core->dev_np) + platform_device_unregister(to_platform_device(core->dev_np)); + if (core->dev_p) + platform_device_unregister(to_platform_device(core->dev_p)); + + core->dev_np = NULL; + core->dev_bs = NULL; + core->dev_p = NULL; +} + +/* + * Shares most of SM8550 data except: + * - inst_caps to platform_inst_cap_qcs8300 + */ +const struct iris_platform_data qcs8300_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu3_ops, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu30_p4_s6.mbn", + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_qcs8300, + .tz_cp_config_data = tz_cp_config_vpu3, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), + .ubwc_config = &iris_ubwc_config_vpu3x, + .num_vpp_pipe = 2, + .max_session_count = 16, + .max_core_mbpf = ((4096 * 2176) / 256) * 4, + .max_core_mbps = (((3840 * 2176) / 256) * 120), +}; + +const struct iris_platform_data sm8550_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu3_ops, + .init_cb_devs = sm8550_init_cb_devs, + .deinit_cb_devs = sm8550_deinit_cb_devs, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_vpu3, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), + .ubwc_config = &iris_ubwc_config_vpu3x, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +const struct iris_platform_data sm8650_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .vpu_ops = &iris_vpu33_ops, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = sm8650_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl = sm8650_controller_reset_table, + .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu33_p4.mbn", + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_vpu3, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), + .ubwc_config = &iris_ubwc_config_vpu3x, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; + +const struct iris_platform_data sm8750_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .vpu_ops = &iris_vpu35_ops, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = sm8750_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = sm8750_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table), + .opp_clk_tbl = iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu35_p4.mbn", + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_vpu3, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), + .ubwc_config = &iris_ubwc_config_vpu3x, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c new file mode 100644 index 0000000000000..ad283afddda6f --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Linaro Ltd + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#include "iris_platform_kaanapali.h" + +static struct iris_fmt iris_fmts_vpu4x_dec[] = { + [IRIS_FMT_H264] = { + .pixfmt = V4L2_PIX_FMT_H264, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] = { + .pixfmt = V4L2_PIX_FMT_HEVC, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] = { + .pixfmt = V4L2_PIX_FMT_VP9, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_AV1] = { + .pixfmt = V4L2_PIX_FMT_AV1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static const struct icc_info iris_icc_info_vpu4x[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const struct bw_info iris_bw_table_dec_vpu4x[] = { + { ((4096 * 2160) / 256) * 60, 1608000 }, + { ((4096 * 2160) / 256) * 30, 826000 }, + { ((1920 * 1080) / 256) * 60, 567000 }, + { ((1920 * 1080) / 256) * 30, 294000 }, +}; + +static const char * const iris_opp_pd_table_vpu4x[] = { "mxc", "mmcx" }; + +static struct platform_inst_caps iris_inst_cap_vpu4x = { + .min_frame_width = 96, + .max_frame_width = 8192, + .min_frame_height = 96, + .max_frame_height = 8192, + .max_mbpf = (8192 * 4352) / 256, + .mb_cycles_vpp = 200, + .mb_cycles_fw = 489583, + .mb_cycles_fw_vpp = 66234, + .num_comv = 0, + .max_frame_rate = MAXIMUM_FPS, + .max_operating_rate = MAXIMUM_FPS, +}; + +static struct ubwc_config_data iris_ubwc_config_vpu4x = { + .max_channels = 8, + .mal_length = 32, + .highest_bank_bit = 16, + .bank_swzl_level = 0, + .bank_swz2_level = 1, + .bank_swz3_level = 1, + .bank_spreading = 1, +}; + +const struct iris_platform_data kaanapali_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu4x_buf_size, + .vpu_ops = &iris_vpu4x_ops, + .icc_tbl = iris_icc_info_vpu4x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu4x), + .clk_rst_tbl = kaanapali_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu4x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu4x), + .pmdomain_tbl = kaanapali_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), + .opp_pd_tbl = iris_opp_pd_table_vpu4x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu4x), + .clk_tbl = kaanapali_clk_table, + .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), + .opp_clk_tbl = kaanapali_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu40_p2_s7.mbn", + .inst_iris_fmts = iris_fmts_vpu4x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu4x_dec), + .inst_caps = &iris_inst_cap_vpu4x, + .tz_cp_config_data = tz_cp_config_kaanapali, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), + .ubwc_config = &iris_ubwc_config_vpu4x, + .num_vpp_pipe = 2, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4352) / 256) * 60, +}; From f2394601f48094003ddda74be14e2086d694d15b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:11 +0200 Subject: [PATCH 0595/1330] FROMLIST: media: qcom: iris: use new firmware name for SM8250 The linux-firmware is providing the vpuNN_pM.mbn firmware for SM8250 since August of 2024. Stop using the legacy firmware name (vpu-1.0/venus.mbn) and switch to the standard firmware name schema (vpu/vpu20_p4.mbn). Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-10-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Vikash Garodia Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov (cherry picked from commit fe66b1f754ad02587e06364cd9705a45de463408) --- drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index ab2a19aa9c36c..692fbc2aab564 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -111,7 +111,7 @@ const struct iris_platform_data sm8250_data = { .opp_clk_tbl = sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu-1.0/venus.mbn", + .fwname = "qcom/vpu/vpu20_p4.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, From 23a8a379862dee5b6f5879cf9c39dace9495f4e2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:12 +0200 Subject: [PATCH 0596/1330] FROMLIST: media: qcom: iris: extract firmware description data In preparation to adding support for several firmware revisions to be used for a platform, extract the firmware description data. It incorporates firmware name, HFI ops and buffer requirements of the particular firmware build. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-11-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov (cherry picked from commit 50f7940d2539484363d0078785cce728f321bb2f) --- .../media/platform/qcom/iris/iris_buffer.c | 2 +- drivers/media/platform/qcom/iris/iris_core.h | 2 + .../media/platform/qcom/iris/iris_firmware.c | 2 +- .../qcom/iris/iris_hfi_gen1_command.c | 2 +- .../platform/qcom/iris/iris_platform_common.h | 15 ++++--- .../platform/qcom/iris/iris_platform_vpu2.c | 20 ++++++--- .../platform/qcom/iris/iris_platform_vpu3x.c | 41 +++++++++++++------ .../platform/qcom/iris/iris_platform_vpu4x.c | 10 +++-- drivers/media/platform/qcom/iris/iris_probe.c | 3 +- 9 files changed, 65 insertions(+), 32 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 762cdbf728b07..32b941c10cd96 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -295,7 +295,7 @@ static void iris_fill_internal_buf_info(struct iris_inst *inst, { struct iris_buffers *buffers = &inst->buffers[buffer_type]; - buffers->size = inst->core->iris_platform_data->get_vpu_buffer_size(inst, buffer_type); + buffers->size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, buffer_type); buffers->min_count = iris_vpu_buf_count(inst, buffer_type); } diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 7d128e7724ed1..2a47fb7001331 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -56,6 +56,7 @@ enum domain_type { * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data * @iris_firmware_data: a pointer to the firmware (or HFI) specific data + * @iris_firmware_desc: a pointer to the firmware-specific descriptive data * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory @@ -107,6 +108,7 @@ struct iris_core { struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; const struct iris_firmware_data *iris_firmware_data; + const struct iris_firmware_desc *iris_firmware_desc; enum iris_core_state state; dma_addr_t iface_q_table_daddr; dma_addr_t sfr_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index da4da3648f983..07b1d71505baf 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -97,7 +97,7 @@ int iris_fw_load(struct iris_core *core) ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0, &fwpath); if (ret) - fwpath = core->iris_platform_data->fwname; + fwpath = core->iris_firmware_desc->fwname; ret = iris_load_fw_to_memory(core, fwpath); if (ret) { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 3fb90a466a64e..83373862655f7 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -918,7 +918,7 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst *inst, u32 plane) if (iris_split_mode_enabled(inst)) { bufsz.type = HFI_BUFFER_OUTPUT; - bufsz.size = inst->core->iris_platform_data->get_vpu_buffer_size(inst, BUF_DPB); + bufsz.size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, BUF_DPB); ret = hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz)); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index acf8c5be4940c..1204342aa6c5d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -261,14 +261,18 @@ struct iris_firmware_data { unsigned int enc_op_int_buf_tbl_size; }; +struct iris_firmware_desc { + const struct iris_firmware_data *firmware_data; + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); + const char *fwname; +}; + struct iris_platform_data { /* - * XXX: remove firmware_data pointer and consider moving - * get_vpu_buffer_size pointer once we have platforms supporting both - * firmware kinds. + * XXX: replace with gen1 / gen2 pointers once we have platforms + * supporting both firmware kinds. */ - const struct iris_firmware_data *firmware_data; - u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); + const struct iris_firmware_desc *firmware_desc; const struct vpu_ops *vpu_ops; void (*set_preset_registers)(struct iris_core *core); @@ -290,7 +294,6 @@ struct iris_platform_data { const char * const *controller_rst_tbl; unsigned int controller_rst_tbl_size; u64 dma_mask; - const char *fwname; struct iris_fmt *inst_iris_fmts; u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 692fbc2aab564..ff8ce078238a5 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -16,6 +16,18 @@ #include "iris_platform_sc7280.h" #include "iris_platform_sm8250.h" +const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu20_p1.mbn", +}; + +const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu20_p4.mbn", +}; + static struct iris_fmt iris_fmts_vpu2_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -62,8 +74,7 @@ static const struct tz_cp_config tz_cp_config_vpu2[] = { }; const struct iris_platform_data sc7280_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, + .firmware_desc = &iris_vpu20_p1_gen1_desc, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), @@ -78,7 +89,6 @@ const struct iris_platform_data sc7280_data = { .opp_clk_tbl = sc7280_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu20_p1.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, @@ -93,8 +103,7 @@ const struct iris_platform_data sc7280_data = { }; const struct iris_platform_data sm8250_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, + .firmware_desc = &iris_vpu20_p4_gen1_desc, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), @@ -111,7 +120,6 @@ const struct iris_platform_data sm8250_data = { .opp_clk_tbl = sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu20_p4.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index f5cf933c3d445..0d33196cc396d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -17,6 +17,30 @@ #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" +const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu30_p4_s6.mbn", +}; + +const struct iris_firmware_desc iris_vpu30_p4_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu30_p4.mbn", +}; + +const struct iris_firmware_desc iris_vpu33_p4_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .fwname = "qcom/vpu/vpu33_p4.mbn", +}; + +const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .fwname = "qcom/vpu/vpu35_p4.mbn", +}; + static struct iris_fmt iris_fmts_vpu3x_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -122,8 +146,7 @@ static void sm8550_deinit_cb_devs(struct iris_core *core) * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, + .firmware_desc = &iris_vpu30_p4_s6_gen2_desc, .vpu_ops = &iris_vpu3_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -140,7 +163,6 @@ const struct iris_platform_data qcs8300_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4_s6.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_qcs8300, @@ -154,8 +176,7 @@ const struct iris_platform_data qcs8300_data = { }; const struct iris_platform_data sm8550_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, + .firmware_desc = &iris_vpu30_p4_gen2_desc, .vpu_ops = &iris_vpu3_ops, .init_cb_devs = sm8550_init_cb_devs, .deinit_cb_devs = sm8550_deinit_cb_devs, @@ -174,7 +195,6 @@ const struct iris_platform_data sm8550_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -192,11 +212,9 @@ const struct iris_platform_data sm8550_data = { * - vpu_ops to iris_vpu33_ops * - clk_rst_tbl to sm8650_clk_reset_table * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, + .firmware_desc = &iris_vpu33_p4_gen2_desc, .vpu_ops = &iris_vpu33_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -215,7 +233,6 @@ const struct iris_platform_data sm8650_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu33_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -229,8 +246,7 @@ const struct iris_platform_data sm8650_data = { }; const struct iris_platform_data sm8750_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, + .firmware_desc = &iris_vpu35_p4_gen2_desc, .vpu_ops = &iris_vpu35_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -247,7 +263,6 @@ const struct iris_platform_data sm8750_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu35_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c index ad283afddda6f..cbd5af0e651db 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c @@ -14,6 +14,12 @@ #include "iris_platform_kaanapali.h" +const struct iris_firmware_desc iris_vpu40_p2_s7_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu4x_buf_size, + .fwname = "qcom/vpu/vpu40_p2_s7.mbn", +}; + static struct iris_fmt iris_fmts_vpu4x_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -72,8 +78,7 @@ static struct ubwc_config_data iris_ubwc_config_vpu4x = { }; const struct iris_platform_data kaanapali_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu4x_buf_size, + .firmware_desc = &iris_vpu40_p2_s7_gen2_desc, .vpu_ops = &iris_vpu4x_ops, .icc_tbl = iris_icc_info_vpu4x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu4x), @@ -90,7 +95,6 @@ const struct iris_platform_data kaanapali_data = { .opp_clk_tbl = kaanapali_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu40_p2_s7.mbn", .inst_iris_fmts = iris_fmts_vpu4x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu4x_dec), .inst_caps = &iris_inst_cap_vpu4x, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 62725cfdb7a9f..5ef4e26df0c4b 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -258,7 +258,8 @@ static int iris_probe(struct platform_device *pdev) return core->irq; core->iris_platform_data = of_device_get_match_data(core->dev); - core->iris_firmware_data = core->iris_platform_data->firmware_data; + core->iris_firmware_desc = core->iris_platform_data->firmware_desc; + core->iris_firmware_data = core->iris_firmware_desc->firmware_data; ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr, iris_hfi_isr_handler, IRQF_TRIGGER_HIGH, "iris", core); From 109a621940fe319e56bbe0e7ba40ce84bf4b6bb0 Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Thu, 22 Jan 2026 15:11:17 +0800 Subject: [PATCH 0597/1330] FROMLIST: dt-bindings: media: qcom,sm8550-iris: Add X1P42100 compatible Document the new compatible string "qcom,x1p42100-iris". The x1p42100 SoC integrates the same IRIS video hardware block as SM8550, but represents a distinct hardware instance and therefore uses its own compatible string. The x1p42100 variant includes an additional Bitstream Engine (BSE) clock that is not present on SM8550. This clock is described explicitly in the binding. Link: https://lore.kernel.org/linux-arm-msm/20260401-enable_iris_on_purwa-v4-1-ca784552a3e9@oss.qualcomm.com/ Signed-off-by: Wangao Wang (cherry picked from commit ae4c2b647d7e637883be095362c372f65b730dbe) --- .../bindings/media/qcom,sm8550-iris.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index 9c4b760508b50..0400ca1bff05d 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -26,6 +26,7 @@ properties: - qcom,qcs8300-iris - qcom,sm8550-iris - qcom,sm8650-iris + - qcom,x1p42100-iris reg: maxItems: 1 @@ -41,13 +42,16 @@ properties: - const: mmcx clocks: - maxItems: 3 + minItems: 3 + maxItems: 4 clock-names: + minItems: 3 items: - const: iface - const: core - const: vcodec0_core + - const: vcodec0_bse firmware-name: maxItems: 1 @@ -115,6 +119,23 @@ allOf: maxItems: 1 reset-names: maxItems: 1 + - if: + properties: + compatible: + enum: + - qcom,x1p42100-iris + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + else: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 unevaluatedProperties: false From 735ed59b8c100e5610197f7f43ddc475a3e9850a Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Thu, 22 Jan 2026 16:43:56 +0800 Subject: [PATCH 0598/1330] FROMLIST: media: iris: Add hardware power on/off ops for X1P42100 On X1P42100 the Iris block has an extra BSE clock. Wire this clock into the power on/off sequence. The BSE clock is used to drive the Bin Stream Engine, which is a sub-block of the video codec hardware responsible for bitstream-level processing. It is required to be enabled separately from the core clock to ensure proper codec operation. Link: https://lore.kernel.org/linux-arm-msm/20260401-enable_iris_on_purwa-v4-2-ca784552a3e9@oss.qualcomm.com/ Signed-off-by: Wangao Wang (cherry picked from commit 56446579a4478d9f99baf417016573f4e3d50b9e) --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 41 +++++++++++++++++++ .../platform/qcom/iris/iris_vpu_common.h | 1 + 2 files changed, 42 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 3dad47be78b58..5799e7e2aae2b 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -71,6 +71,38 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) iris_vpu_power_off_hw(core); } +static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) +{ + int ret; + + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto err_disable_power; + + ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); + if (ret) + goto err_disable_hw_clock; + + return 0; + +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + + return ret; +} + +static void iris_vpu3_purwa_power_off_hardware(struct iris_core *core) +{ + iris_vpu3_power_off_hardware(core); + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); +} + static void iris_vpu33_power_off_hardware(struct iris_core *core) { bool handshake_done = false, handshake_busy = false; @@ -263,6 +295,15 @@ const struct vpu_ops iris_vpu3_ops = { .set_hwmode = iris_vpu_set_hwmode, }; +const struct vpu_ops iris_vpu3_purwa_ops = { + .power_off_hw = iris_vpu3_purwa_power_off_hardware, + .power_on_hw = iris_vpu3_purwa_power_on_hw, + .power_off_controller = iris_vpu_power_off_controller, + .power_on_controller = iris_vpu_power_on_controller, + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode = iris_vpu_set_hwmode, +}; + const struct vpu_ops iris_vpu33_ops = { .power_off_hw = iris_vpu33_power_off_hardware, .power_on_hw = iris_vpu_power_on_hw, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index 09799a375c142..9d531fd8c3cc6 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,6 +10,7 @@ struct iris_core; extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; +extern const struct vpu_ops iris_vpu3_purwa_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; extern const struct vpu_ops iris_vpu4x_ops; From 58c98caa3d8a89b326a1b3c8fdb76cc861b0701d Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Thu, 22 Jan 2026 16:52:10 +0800 Subject: [PATCH 0599/1330] FROMLIST: media: iris: Add platform data for X1P42100 Introduce platform data for X1P42100, derived from SM8550 but using a different clock configuration and a dedicated OPP setup. Link: https://lore.kernel.org/linux-arm-msm/20260401-enable_iris_on_purwa-v4-3-ca784552a3e9@oss.qualcomm.com/ Signed-off-by: Wangao Wang (cherry picked from commit 72e188f0f619bc30402752be652ac87603c5a295) --- .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_vpu3x.c | 33 +++++++++++++++++++ .../qcom/iris/iris_platform_x1p42100.h | 22 +++++++++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 +++ 4 files changed, 60 insertions(+) create mode 100644 drivers/media/platform/qcom/iris/iris_platform_x1p42100.h diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 1204342aa6c5d..4db1690cddbeb 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -50,6 +50,7 @@ extern const struct iris_platform_data sm8250_data; extern const struct iris_platform_data sm8550_data; extern const struct iris_platform_data sm8650_data; extern const struct iris_platform_data sm8750_data; +extern const struct iris_platform_data x1p42100_data; enum platform_clk_type { IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index 0d33196cc396d..bb1df13563952 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -16,6 +16,7 @@ #include "iris_platform_sm8550.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" +#include "iris_platform_x1p42100.h" const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, @@ -274,3 +275,35 @@ const struct iris_platform_data sm8750_data = { .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, }; + +const struct iris_platform_data x1p42100_data = { + .firmware_desc = &iris_vpu30_p4_gen2_desc, + .vpu_ops = &iris_vpu3_purwa_ops, + .init_cb_devs = sm8550_init_cb_devs, + .deinit_cb_devs = sm8550_deinit_cb_devs, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = x1p42100_clk_table, + .clk_tbl_size = ARRAY_SIZE(x1p42100_clk_table), + .opp_clk_tbl = x1p42100_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_vpu3, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), + .ubwc_config = &iris_ubwc_config_vpu3x, + .num_vpp_pipe = 1, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h new file mode 100644 index 0000000000000..d89acfbc1233d --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __IRIS_PLATFORM_X1P42100_H__ +#define __IRIS_PLATFORM_X1P42100_H__ + +static const struct platform_clk_data x1p42100_clk_table[] = { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_BSE_HW_CLK, "vcodec0_bse" }, +}; + +static const char *const x1p42100_opp_clk_table[] = { + "vcodec0_core", + "vcodec0_bse", + NULL, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 5ef4e26df0c4b..7fc9d2e7ff05c 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -400,6 +400,10 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,sm8750-iris", .data = &sm8750_data, }, + { + .compatible = "qcom,x1p42100-iris", + .data = &x1p42100_data, + }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match); From 6ca8d2c165f5aba9ef125043c973aa3b91918d6f Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 7 Apr 2026 18:07:13 +0530 Subject: [PATCH 0600/1330] FROMLIST: iommu/arm-smmu-qcom: Fix fastrpc compatible string in ACTLR client match table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The qcom_smmu_actlr_client_of_match table contained "qcom,fastrpc" as the compatible string for applying ACTLR prefetch settings to FastRPC devices. However, "qcom,fastrpc" is the compatible string for the parent rpmsg channel node, which is not an IOMMU client — it carries no "iommus" property in the device tree and is never attached to an SMMU context bank. The actual IOMMU clients are the compute context bank (CB) child nodes, which use the compatible string "qcom,fastrpc-compute-cb". These nodes carry the "iommus" property and are probed by fastrpc_cb_driver via fastrpc_cb_probe(), which sets up the DMA mask and IOMMU mappings for each FastRPC session. The device tree structure is: fastrpc { compatible = "qcom,fastrpc"; /* rpmsg channel, no iommus */ ... compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; iommus = <&apps_smmu 0x1823 0x0>; /* actual IOMMU client */ }; }; Since qcom_smmu_set_actlr_dev() calls of_match_device() against the device being attached to the SMMU context bank, the "qcom,fastrpc" entry was never matching any device. As a result, the ACTLR prefetch settings (PREFETCH_DEEP | CPRE | CMTLB) were silently never applied for FastRPC compute context banks. Fix this by replacing "qcom,fastrpc" with "qcom,fastrpc-compute-cb" in the match table so that the ACTLR settings are correctly applied to the compute CB devices that are the true IOMMU clients. Link: https://lore.kernel.org/all/20260408130825.3268733-1-bibek.patro@oss.qualcomm.com/ Assisted-by: Anthropic:claude-4-6-sonnet Fixes: 3e35c3e725de ("iommu/arm-smmu: Add ACTLR data and support for qcom_smmu_500") Signed-off-by: Bibek Kumar Patro (cherry picked from commit 216e8f6f4f1633bf6c64789530c0d350cd25065f) --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index edd41b5a3b6ac..2d006049dd610 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -39,7 +39,7 @@ static const struct of_device_id qcom_smmu_actlr_client_of_match[] = { .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, { .compatible = "qcom,adreno-smmu", .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, - { .compatible = "qcom,fastrpc", + { .compatible = "qcom,fastrpc-compute-cb", .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, { .compatible = "qcom,qcm2290-mdss", .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, From cd05a53c3d2303bc3f629bb98ee47c0f231e607b Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Tue, 14 Oct 2025 17:49:02 +0100 Subject: [PATCH 0601/1330] FROMLIST: of: Add convenience wrappers for of_map_id() Since we now have quite a few users parsing "iommu-map" and "msi-map" properties, give them some wrappers to conveniently encapsulate the appropriate sets of property names. This will also make it easier to then change of_map_id() to correctly account for specifier cells. Link: https://lore.kernel.org/lkml/20260424-parse_iommu_cells-v14-1-fd02f11b6c38@oss.qualcomm.com/ Reviewed-by: Rob Herring (Arm) Reviewed-by: Frank Li Acked-by: Marc Zyngier Acked-by: Bjorn Helgaas Signed-off-by: Robin Murphy Signed-off-by: Vijayanand Jitta (cherry picked from commit badf51b1869eecc56bdffef72078b98a8c9c7af3) --- drivers/cdx/cdx_msi.c | 3 +- drivers/iommu/of_iommu.c | 4 +-- drivers/irqchip/irq-gic-its-msi-parent.c | 2 +- drivers/of/base.c | 38 ++++++++++++++++++++++++ drivers/of/irq.c | 3 +- drivers/pci/controller/dwc/pci-imx6.c | 6 ++-- drivers/pci/controller/pcie-apple.c | 3 +- drivers/xen/grant-dma-ops.c | 3 +- include/linux/of.h | 18 +++++++++++ 9 files changed, 64 insertions(+), 16 deletions(-) diff --git a/drivers/cdx/cdx_msi.c b/drivers/cdx/cdx_msi.c index 91b95422b2634..63b3544ec9978 100644 --- a/drivers/cdx/cdx_msi.c +++ b/drivers/cdx/cdx_msi.c @@ -128,8 +128,7 @@ static int cdx_msi_prepare(struct irq_domain *msi_domain, int ret; /* Retrieve device ID from requestor ID using parent device */ - ret = of_map_id(parent->of_node, cdx_dev->msi_dev_id, "msi-map", "msi-map-mask", - NULL, &dev_id); + ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &dev_id); if (ret) { dev_err(dev, "of_map_id failed for MSI: %d\n", ret); return ret; diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 6b989a62def20..a511ecf21fcdf 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -48,9 +48,7 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, struct of_phandle_args iommu_spec = { .args_count = 1 }; int err; - err = of_map_id(master_np, *id, "iommu-map", - "iommu-map-mask", &iommu_spec.np, - iommu_spec.args); + err = of_map_iommu_id(master_np, *id, &iommu_spec.np, iommu_spec.args); if (err) return err; diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c index a832cdb2e6978..b30d0dc0a1aa3 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -179,7 +179,7 @@ static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u struct device_node *msi_ctrl __free(device_node) = NULL; - return of_map_id(dev->of_node, dev->id, "msi-map", "msi-map-mask", &msi_ctrl, dev_id); + return of_map_msi_id(dev->of_node, dev->id, &msi_ctrl, dev_id); } static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, diff --git a/drivers/of/base.c b/drivers/of/base.c index 8d1972e181610..f972e5552ba25 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2201,3 +2201,41 @@ int of_map_id(const struct device_node *np, u32 id, return 0; } EXPORT_SYMBOL_GPL(of_map_id); + +/** + * of_map_iommu_id - Translate an ID using "iommu-map" bindings. + * @np: root complex device node. + * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform + * stream/device ID) used as the lookup key in the iommu-map table. + * @target: optional pointer to a target device node. + * @id_out: optional pointer to receive the translated ID. + * + * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". + * + * Return: 0 on success or a standard error code on failure. + */ +int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return of_map_id(np, id, "iommu-map", "iommu-map-mask", target, id_out); +} +EXPORT_SYMBOL_GPL(of_map_iommu_id); + +/** + * of_map_msi_id - Translate an ID using "msi-map" bindings. + * @np: root complex device node. + * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform + * stream/device ID) used as the lookup key in the msi-map table. + * @target: optional pointer to a target device node. + * @id_out: optional pointer to receive the translated ID. + * + * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". + * + * Return: 0 on success or a standard error code on failure. + */ +int of_map_msi_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return of_map_id(np, id, "msi-map", "msi-map-mask", target, id_out); +} +EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 6367c67732d26..e37c1b3f87362 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -817,8 +817,7 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in) * "msi-map" or an "msi-parent" property. */ for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) { - if (!of_map_id(parent_dev->of_node, id_in, "msi-map", - "msi-map-mask", msi_np, &id_out)) + if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out)) break; if (!of_check_msi_parent(parent_dev->of_node, msi_np)) break; diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 0a494c9dd6aa1..27cfc30e99b32 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1146,8 +1146,7 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) u32 sid = 0; target = NULL; - err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", - &target, &sid_i); + err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i); if (target) { of_node_put(target); } else { @@ -1160,8 +1159,7 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) } target = NULL; - err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", - &target, &sid_m); + err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m); /* * err_m target diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c index 2d92fc79f6ddf..a0937b7b3c4d9 100644 --- a/drivers/pci/controller/pcie-apple.c +++ b/drivers/pci/controller/pcie-apple.c @@ -764,8 +764,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d dev_dbg(&pdev->dev, "added to bus %s, index %d\n", pci_name(pdev->bus->self), port->idx); - err = of_map_id(port->pcie->dev->of_node, rid, "iommu-map", - "iommu-map-mask", NULL, &sid); + err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid); if (err) return err; diff --git a/drivers/xen/grant-dma-ops.c b/drivers/xen/grant-dma-ops.c index c2603e7001786..1b7696b2d762f 100644 --- a/drivers/xen/grant-dma-ops.c +++ b/drivers/xen/grant-dma-ops.c @@ -325,8 +325,7 @@ static int xen_dt_grant_init_backend_domid(struct device *dev, struct pci_dev *pdev = to_pci_dev(dev); u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn); - if (of_map_id(np, rid, "iommu-map", "iommu-map-mask", &iommu_spec.np, - iommu_spec.args)) { + if (of_map_iommu_id(np, rid, &iommu_spec.np, iommu_spec.args)) { dev_dbg(dev, "Cannot translate ID\n"); return -ESRCH; } diff --git a/include/linux/of.h b/include/linux/of.h index be6ec4916adf5..fe841f3cc747e 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -465,6 +465,12 @@ int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, struct device_node **target, u32 *id_out); +int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out); + +int of_map_msi_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out); + phys_addr_t of_dma_get_max_cpu_address(struct device_node *np); struct kimage; @@ -934,6 +940,18 @@ static inline int of_map_id(const struct device_node *np, u32 id, return -EINVAL; } +static inline int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return -EINVAL; +} + +static inline int of_map_msi_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return -EINVAL; +} + static inline phys_addr_t of_dma_get_max_cpu_address(struct device_node *np) { return PHYS_ADDR_MAX; From 7bf3319ff7a6a5f1904e92d7116e71b63a8f4b26 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Sat, 29 Nov 2025 08:48:34 +0530 Subject: [PATCH 0602/1330] FROMLIST: of: Factor arguments passed to of_map_id() into a struct Change of_map_id() to take a pointer to struct of_phandle_args instead of passing target device node and translated IDs separately. Update all callers accordingly. Add an explicit filter_np parameter to of_map_id() and of_map_msi_id() to separate the filter input from the output. Previously, the target parameter served dual purpose: as an input filter (if non-NULL, only match entries targeting that node) and as an output (receiving the matched node with a reference held). Now filter_np is the explicit input filter and arg->np is the pure output. Previously, of_map_id() would call of_node_put() on the matched node when a filter was provided, making reference ownership inconsistent. Remove this internal of_node_put() call so that of_map_id() now always transfers ownership of the matched node reference to the caller via arg->np. Callers are now consistently responsible for releasing this reference with of_node_put(arg->np) when done. Link: https://lore.kernel.org/lkml/20260424-parse_iommu_cells-v14-2-fd02f11b6c38@oss.qualcomm.com/ Acked-by: Frank Li Suggested-by: Rob Herring (Arm) Suggested-by: Dmitry Baryshkov Signed-off-by: Charan Teja Kalla Signed-off-by: Vijayanand Jitta (cherry picked from commit 6fe53855cdfd13e0712f5901bf3d638640d2b40f) --- drivers/cdx/cdx_msi.c | 7 +-- drivers/iommu/of_iommu.c | 4 +- drivers/irqchip/irq-gic-its-msi-parent.c | 11 ++-- drivers/of/base.c | 68 +++++++++++++----------- drivers/of/irq.c | 30 ++++++++--- drivers/pci/controller/dwc/pci-imx6.c | 32 +++++------ drivers/pci/controller/pcie-apple.c | 5 +- drivers/xen/grant-dma-ops.c | 4 +- include/linux/of.h | 14 ++--- 9 files changed, 104 insertions(+), 71 deletions(-) diff --git a/drivers/cdx/cdx_msi.c b/drivers/cdx/cdx_msi.c index 63b3544ec9978..6924e07c75283 100644 --- a/drivers/cdx/cdx_msi.c +++ b/drivers/cdx/cdx_msi.c @@ -121,22 +121,23 @@ static int cdx_msi_prepare(struct irq_domain *msi_domain, struct device *dev, int nvec, msi_alloc_info_t *info) { + struct of_phandle_args msi_spec = {}; struct cdx_device *cdx_dev = to_cdx_device(dev); struct device *parent = cdx_dev->cdx->dev; struct msi_domain_info *msi_info; - u32 dev_id; int ret; /* Retrieve device ID from requestor ID using parent device */ - ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &dev_id); + ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &msi_spec); if (ret) { dev_err(dev, "of_map_id failed for MSI: %d\n", ret); return ret; } + of_node_put(msi_spec.np); #ifdef GENERIC_MSI_DOMAIN_OPS /* Set the device Id to be passed to the GIC-ITS */ - info->scratchpad[0].ul = dev_id; + info->scratchpad[0].ul = msi_spec.args[0]; #endif msi_info = msi_get_domain_info(msi_domain->parent); diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index a511ecf21fcdf..a18bb60f6f3df 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -45,10 +45,10 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, struct device *dev, const u32 *id) { - struct of_phandle_args iommu_spec = { .args_count = 1 }; + struct of_phandle_args iommu_spec = {}; int err; - err = of_map_iommu_id(master_np, *id, &iommu_spec.np, iommu_spec.args); + err = of_map_iommu_id(master_np, *id, &iommu_spec); if (err) return err; diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c index b30d0dc0a1aa3..b64b74dd907ce 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -151,6 +151,8 @@ static int its_v5_pci_msi_prepare(struct irq_domain *domain, struct device *dev, static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u32 *dev_id, phys_addr_t *pa) { + struct device_node *msi_ctrl __free(device_node) = NULL; + struct of_phandle_args msi_spec = {}; struct of_phandle_iterator it; int ret; @@ -177,9 +179,12 @@ static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u } } - struct device_node *msi_ctrl __free(device_node) = NULL; - - return of_map_msi_id(dev->of_node, dev->id, &msi_ctrl, dev_id); + ret = of_map_msi_id(dev->of_node, dev->id, NULL, &msi_spec); + if (!ret) { + msi_ctrl = msi_spec.np; + *dev_id = msi_spec.args[0]; + } + return ret; } static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, diff --git a/drivers/of/base.c b/drivers/of/base.c index f972e5552ba25..ce85d73f9898f 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2102,36 +2102,37 @@ int of_find_last_cache_level(unsigned int cpu) * @id: device ID to map. * @map_name: property name of the map to use. * @map_mask_name: optional property name of the mask to use. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @filter_np: optional device node to filter matches by, or NULL to match any. + * If non-NULL, only map entries targeting this node will be matched. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] will contain the translated ID. If a map entry was + * matched, @arg->np will be set to the target node with a reference + * held that the caller must release with of_node_put(). * * Given a device ID, look up the appropriate implementation-defined * platform ID and/or the target device which receives transactions on that - * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or - * @id_out may be NULL if only the other is required. If @target points to - * a non-NULL device node pointer, only entries targeting that node will be - * matched; if it points to a NULL value, it will receive the device node of - * the first matching target phandle, with a reference held. + * ID, as per the "iommu-map" and "msi-map" bindings. * * Return: 0 on success or a standard error code on failure. */ int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, struct of_phandle_args *arg) { u32 map_mask, masked_id; int map_len; const __be32 *map = NULL; - if (!np || !map_name || (!target && !id_out)) + if (!np || !map_name || !arg) return -EINVAL; map = of_get_property(np, map_name, &map_len); if (!map) { - if (target) + if (filter_np) return -ENODEV; /* Otherwise, no map implies no translation */ - *id_out = id; + arg->args[0] = id; + arg->args_count = 1; return 0; } @@ -2173,18 +2174,14 @@ int of_map_id(const struct device_node *np, u32 id, if (!phandle_node) return -ENODEV; - if (target) { - if (*target) - of_node_put(phandle_node); - else - *target = phandle_node; - - if (*target != phandle_node) - continue; + if (filter_np && filter_np != phandle_node) { + of_node_put(phandle_node); + continue; } - if (id_out) - *id_out = masked_id - id_base + out_base; + arg->np = phandle_node; + arg->args[0] = masked_id - id_base + out_base; + arg->args_count = 1; pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n", np, map_name, map_mask, id_base, out_base, @@ -2193,11 +2190,11 @@ int of_map_id(const struct device_node *np, u32 id, } pr_info("%pOF: no %s translation for id 0x%x on %pOF\n", np, map_name, - id, target && *target ? *target : NULL); + id, filter_np); /* Bypasses translation */ - if (id_out) - *id_out = id; + arg->args[0] = id; + arg->args_count = 1; return 0; } EXPORT_SYMBOL_GPL(of_map_id); @@ -2207,17 +2204,19 @@ EXPORT_SYMBOL_GPL(of_map_id); * @np: root complex device node. * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the iommu-map table. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] contains the translated ID. If a map entry was matched, + * @arg->np holds a reference to the target node that the caller must + * release with of_node_put(). * * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + struct of_phandle_args *arg) { - return of_map_id(np, id, "iommu-map", "iommu-map-mask", target, id_out); + return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg); } EXPORT_SYMBOL_GPL(of_map_iommu_id); @@ -2226,16 +2225,21 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id); * @np: root complex device node. * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the msi-map table. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @filter_np: optional MSI controller node to filter matches by, or NULL + * to match any. If non-NULL, only map entries targeting this node will + * be matched. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] contains the translated ID. If a map entry was matched, + * @arg->np holds a reference to the target node that the caller must + * release with of_node_put(). * * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, struct of_phandle_args *arg) { - return of_map_id(np, id, "msi-map", "msi-map-mask", target, id_out); + return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg); } EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/drivers/of/irq.c b/drivers/of/irq.c index e37c1b3f87362..4040467742c40 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -796,19 +796,22 @@ static int of_check_msi_parent(struct device_node *dev_node, struct device_node /** * of_msi_xlate - map a MSI ID and find relevant MSI controller node * @dev: device for which the mapping is to be done. - * @msi_np: Pointer to target MSI controller node + * @msi_np: Pointer to target MSI controller node, or NULL if the caller + * only needs the translated ID without receiving the controller node. + * If non-NULL and pointing to a non-NULL node, only entries targeting + * that node will be matched. If non-NULL and pointing to NULL, it will + * receive the first matching target node with a reference held. * @id_in: Device ID. * * Walk up the device hierarchy looking for devices with a "msi-map" * or "msi-parent" property. If found, apply the mapping to @id_in. - * If @msi_np points to a non-NULL device node pointer, only entries targeting - * that node will be matched; if it points to a NULL value, it will receive the - * device node of the first matching target phandle, with a reference held. * * Returns: The mapped MSI id. */ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in) { + struct device_node *local_np = NULL; + struct device_node **np = msi_np ?: &local_np; struct device *parent_dev; u32 id_out = id_in; @@ -817,11 +820,26 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in) * "msi-map" or an "msi-parent" property. */ for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) { - if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out)) + struct of_phandle_args msi_spec = {}; + + if (!of_map_msi_id(parent_dev->of_node, id_in, *np, &msi_spec)) { + /* + * Pass-through result: no msi-map on this node (or no + * matching entry). Keep walking up the hierarchy. + */ + if (!msi_spec.np) + continue; + id_out = msi_spec.args[0]; + if (!*np) + *np = msi_spec.np; + else + of_node_put(msi_spec.np); break; - if (!of_check_msi_parent(parent_dev->of_node, msi_np)) + } + if (!of_check_msi_parent(parent_dev->of_node, np)) break; } + of_node_put(local_np); return id_out; } EXPORT_SYMBOL_GPL(of_msi_xlate); diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 27cfc30e99b32..b13d42e113fb3 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1139,30 +1139,32 @@ static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid) static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) { + struct of_phandle_args iommu_spec = {}; + struct of_phandle_args msi_spec = {}; struct device *dev = imx_pcie->pci->dev; - struct device_node *target; u32 sid_i, sid_m; int err_i, err_m; u32 sid = 0; - target = NULL; - err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i); - if (target) { - of_node_put(target); - } else { + err_i = of_map_iommu_id(dev->of_node, rid, &iommu_spec); + if (!err_i) + sid_i = iommu_spec.args[0]; + of_node_put(iommu_spec.np); + if (!err_i && !iommu_spec.np) { /* - * "target == NULL && err_i == 0" means RID out of map range. - * Use 1:1 map RID to streamID. Hardware can't support this - * because the streamID is only 6 bits + * "iommu_spec.np == NULL && err_i == 0" means RID out of map + * range. Use 1:1 map RID to streamID. Hardware can't support + * this because the streamID is only 6 bits. */ err_i = -EINVAL; } - target = NULL; - err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m); - + err_m = of_map_msi_id(dev->of_node, rid, NULL, &msi_spec); + if (!err_m) + sid_m = msi_spec.args[0]; + of_node_put(msi_spec.np); /* - * err_m target + * err_m msi_spec.np * 0 NULL RID out of range. Use 1:1 map RID to * streamID, Current hardware can't * support it, so return -EINVAL. @@ -1170,10 +1172,8 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) * 0 != NULL Get correct streamID from RID * != 0 != NULL Invalid combination */ - if (!err_m && !target) + if (!err_m && !msi_spec.np) return -EINVAL; - else if (target) - of_node_put(target); /* Find streamID map entry for RID in msi-map */ /* * msi-map iommu-map diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c index a0937b7b3c4d9..c2cffc0659f44 100644 --- a/drivers/pci/controller/pcie-apple.c +++ b/drivers/pci/controller/pcie-apple.c @@ -755,6 +755,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d { u32 sid, rid = pci_dev_id(pdev); struct apple_pcie_port *port; + struct of_phandle_args iommu_spec = {}; int idx, err; port = apple_pcie_get_port(pdev); @@ -764,10 +765,12 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d dev_dbg(&pdev->dev, "added to bus %s, index %d\n", pci_name(pdev->bus->self), port->idx); - err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid); + err = of_map_iommu_id(port->pcie->dev->of_node, rid, &iommu_spec); if (err) return err; + of_node_put(iommu_spec.np); + sid = iommu_spec.args[0]; mutex_lock(&port->pcie->lock); idx = bitmap_find_free_region(port->sid_map, port->sid_map_sz, 0); diff --git a/drivers/xen/grant-dma-ops.c b/drivers/xen/grant-dma-ops.c index 1b7696b2d762f..2aa1a772a0ffc 100644 --- a/drivers/xen/grant-dma-ops.c +++ b/drivers/xen/grant-dma-ops.c @@ -319,13 +319,13 @@ static int xen_dt_grant_init_backend_domid(struct device *dev, struct device_node *np, domid_t *backend_domid) { - struct of_phandle_args iommu_spec = { .args_count = 1 }; + struct of_phandle_args iommu_spec = {}; if (dev_is_pci(dev)) { struct pci_dev *pdev = to_pci_dev(dev); u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn); - if (of_map_iommu_id(np, rid, &iommu_spec.np, iommu_spec.args)) { + if (of_map_iommu_id(np, rid, &iommu_spec)) { dev_dbg(dev, "Cannot translate ID\n"); return -ESRCH; } diff --git a/include/linux/of.h b/include/linux/of.h index fe841f3cc747e..8548cd9eb4f14 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -463,13 +463,13 @@ bool of_console_check(const struct device_node *dn, char *name, int index); int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out); + const struct device_node *filter_np, struct of_phandle_args *arg); int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out); + struct of_phandle_args *arg); int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out); + const struct device_node *filter_np, struct of_phandle_args *arg); phys_addr_t of_dma_get_max_cpu_address(struct device_node *np); @@ -935,19 +935,21 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag static inline int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, + struct of_phandle_args *arg) { return -EINVAL; } static inline int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + struct of_phandle_args *arg) { return -EINVAL; } static inline int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, + struct of_phandle_args *arg) { return -EINVAL; } From a2a78ef6b4698419a50ba3087d1daed9641a633a Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Wed, 25 Mar 2026 12:19:57 +0530 Subject: [PATCH 0603/1330] FROMLIST: of: Respect #{iommu,msi}-cells in maps So far our parsing of {iommu,msi}-map properties has always blindly assumed that the output specifiers will always have exactly 1 cell. This typically does happen to be the case, but is not actually enforced (and the PCI msi-map binding even explicitly states support for 0 or 1 cells) - as a result we've now ended up with dodgy DTs out in the field which depend on this behaviour to map a 1-cell specifier for a 2-cell provider, despite that being bogus per the bindings themselves. Since there is some potential use in being able to map at least single input IDs to multi-cell output specifiers (and properly support 0-cell outputs as well), add support for properly parsing and using the target nodes' #cells values, albeit with the unfortunate complication of still having to work around expectations of the old behaviour too. Since there are multi-cell output specifiers, the callers of of_map_id() may need to get the exact cell output value for further processing. Update of_map_id() to set args_count in the output to reflect the actual number of output specifier cells. Link: https://lore.kernel.org/lkml/20260424-parse_iommu_cells-v14-3-fd02f11b6c38@oss.qualcomm.com/ Signed-off-by: Robin Murphy Signed-off-by: Charan Teja Kalla Signed-off-by: Vijayanand Jitta (cherry picked from commit 1fa98cb308186a3c850369ade7be19f644199f66) --- drivers/of/base.c | 157 ++++++++++++++++++++++++++++++++++----------- include/linux/of.h | 6 +- 2 files changed, 125 insertions(+), 38 deletions(-) diff --git a/drivers/of/base.c b/drivers/of/base.c index ce85d73f9898f..ec06c45e8fe36 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2096,18 +2096,48 @@ int of_find_last_cache_level(unsigned int cpu) return cache_level; } +/* + * Some DTs have an iommu-map targeting a 2-cell IOMMU node while + * specifying only 1 cell. Fortunately they all consist of value '1' + * as the 2nd cell entry with the same target, so check for that pattern. + * + * Example: + * IOMMU node: + * #iommu-cells = <2>; + * + * Device node: + * iommu-map = <0x0000 &smmu 0x0000 0x1>, + * <0x0100 &smmu 0x0100 0x1>; + */ +static bool of_check_bad_map(const __be32 *map, int len) +{ + __be32 phandle = map[1]; + + if (len % 4) + return false; + for (int i = 0; i < len; i += 4) { + if (map[i + 1] != phandle || map[i + 3] != cpu_to_be32(1)) + return false; + } + return true; +} + /** * of_map_id - Translate an ID through a downstream mapping. * @np: root complex device node. * @id: device ID to map. * @map_name: property name of the map to use. + * @cells_name: property name of target specifier cells. * @map_mask_name: optional property name of the mask to use. * @filter_np: optional device node to filter matches by, or NULL to match any. * If non-NULL, only map entries targeting this node will be matched. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] will contain the translated ID. If a map entry was - * matched, @arg->np will be set to the target node with a reference - * held that the caller must release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * as defined by @cells_name in the target node, and + * @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np will be set + * to the target node with a reference held that the caller must release + * with of_node_put(). * * Given a device ID, look up the appropriate implementation-defined * platform ID and/or the target device which receives transactions on that @@ -2116,17 +2146,19 @@ int of_find_last_cache_level(unsigned int cpu) * Return: 0 on success or a standard error code on failure. */ int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg) { u32 map_mask, masked_id; - int map_len; + int map_bytes, map_len, offset = 0; + bool bad_map = false; const __be32 *map = NULL; if (!np || !map_name || !arg) return -EINVAL; - map = of_get_property(np, map_name, &map_len); + map = of_get_property(np, map_name, &map_bytes); if (!map) { if (filter_np) return -ENODEV; @@ -2136,11 +2168,9 @@ int of_map_id(const struct device_node *np, u32 id, return 0; } - if (!map_len || map_len % (4 * sizeof(*map))) { - pr_err("%pOF: Error: Bad %s length: %d\n", np, - map_name, map_len); - return -EINVAL; - } + if (map_bytes % sizeof(*map)) + goto err_map_len; + map_len = map_bytes / sizeof(*map); /* The default is to select all bits. */ map_mask = 0xffffffff; @@ -2153,39 +2183,84 @@ int of_map_id(const struct device_node *np, u32 id, of_property_read_u32(np, map_mask_name, &map_mask); masked_id = map_mask & id; - for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) { + + while (offset < map_len) { struct device_node *phandle_node; - u32 id_base = be32_to_cpup(map + 0); - u32 phandle = be32_to_cpup(map + 1); - u32 out_base = be32_to_cpup(map + 2); - u32 id_len = be32_to_cpup(map + 3); + u32 id_base, phandle, id_len, id_off, cells = 0; + const __be32 *out_base; + + if (map_len - offset < 2) + goto err_map_len; + + id_base = be32_to_cpup(map + offset); if (id_base & ~map_mask) { - pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores id-base (0x%x)\n", - np, map_name, map_name, - map_mask, id_base); + pr_err("%pOF: Invalid %s translation - %s (0x%x) ignores id-base (0x%x)\n", + np, map_name, map_mask_name, map_mask, id_base); return -EFAULT; } - if (masked_id < id_base || masked_id >= id_base + id_len) - continue; - + phandle = be32_to_cpup(map + offset + 1); phandle_node = of_find_node_by_phandle(phandle); if (!phandle_node) return -ENODEV; + if (bad_map) { + cells = 1; + } else if (of_property_read_u32(phandle_node, cells_name, &cells)) { + pr_err("%pOF: missing %s property\n", phandle_node, cells_name); + of_node_put(phandle_node); + return -EINVAL; + } + + if (map_len - offset < 3 + cells) { + of_node_put(phandle_node); + goto err_map_len; + } + + if (offset == 0 && cells == 2) { + bad_map = of_check_bad_map(map, map_len); + if (bad_map) { + pr_warn_once("%pOF: %s mismatches target %s, assuming extra cell of 0\n", + np, map_name, cells_name); + cells = 1; + } + } + + out_base = map + offset + 2; + offset += 3 + cells; + + id_len = be32_to_cpup(map + offset - 1); + if (id_len > 1 && cells > 1) { + /* + * With 1 output cell we reasonably assume its value + * has a linear relationship to the input; with more, + * we'd need help from the provider to know what to do. + */ + pr_err("%pOF: Unsupported %s - cannot handle %d-ID range with %d-cell output specifier\n", + np, map_name, id_len, cells); + of_node_put(phandle_node); + return -EINVAL; + } + id_off = masked_id - id_base; + if (masked_id < id_base || id_off >= id_len) { + of_node_put(phandle_node); + continue; + } + if (filter_np && filter_np != phandle_node) { of_node_put(phandle_node); continue; } arg->np = phandle_node; - arg->args[0] = masked_id - id_base + out_base; - arg->args_count = 1; + for (int i = 0; i < cells; i++) + arg->args[i] = id_off + be32_to_cpu(out_base[i]); + arg->args_count = cells; pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n", - np, map_name, map_mask, id_base, out_base, - id_len, id, masked_id - id_base + out_base); + np, map_name, map_mask, id_base, be32_to_cpup(out_base), + id_len, id, id_off + be32_to_cpup(out_base)); return 0; } @@ -2196,6 +2271,10 @@ int of_map_id(const struct device_node *np, u32 id, arg->args[0] = id; arg->args_count = 1; return 0; + +err_map_len: + pr_err("%pOF: Error: Bad %s length: %d\n", np, map_name, map_bytes); + return -EINVAL; } EXPORT_SYMBOL_GPL(of_map_id); @@ -2205,18 +2284,21 @@ EXPORT_SYMBOL_GPL(of_map_id); * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the iommu-map table. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] contains the translated ID. If a map entry was matched, - * @arg->np holds a reference to the target node that the caller must - * release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * and @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np holds a + * reference to the target node that the caller must release with + * of_node_put(). * - * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". + * Convenience wrapper around of_map_id() using "iommu-map", "#iommu-cells", + * and "iommu-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_iommu_id(const struct device_node *np, u32 id, struct of_phandle_args *arg) { - return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg); + return of_map_id(np, id, "iommu-map", "#iommu-cells", "iommu-map-mask", NULL, arg); } EXPORT_SYMBOL_GPL(of_map_iommu_id); @@ -2229,17 +2311,20 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id); * to match any. If non-NULL, only map entries targeting this node will * be matched. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] contains the translated ID. If a map entry was matched, - * @arg->np holds a reference to the target node that the caller must - * release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * and @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np holds a + * reference to the target node that the caller must release with + * of_node_put(). * - * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". + * Convenience wrapper around of_map_id() using "msi-map", "#msi-cells", + * and "msi-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_msi_id(const struct device_node *np, u32 id, const struct device_node *filter_np, struct of_phandle_args *arg) { - return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg); + return of_map_id(np, id, "msi-map", "#msi-cells", "msi-map-mask", filter_np, arg); } EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/include/linux/of.h b/include/linux/of.h index 8548cd9eb4f14..51ac8539f2c39 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -462,7 +462,8 @@ const char *of_prop_next_string(const struct property *prop, const char *cur); bool of_console_check(const struct device_node *dn, char *name, int index); int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg); int of_map_iommu_id(const struct device_node *np, u32 id, @@ -934,7 +935,8 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag } static inline int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg) { From f04e7a8485c689c08765617a6b20fc4a7d30fa9f Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 29 Apr 2026 11:34:26 +0800 Subject: [PATCH 0604/1330] QCLINUX: qcom-dcc: add lemans register list and move config to header Add the full DCC register capture list for the Lemans platform derived from debug_config_qcs9100.sh. The registers cover LPM, TSENS, PLL, LIMITS, and DDR subsystems, all configured on linked list 6 to match the runtime script (LLNUM=6 in configure_dcc()). Consecutive single-word reads are merged into burst entries (e.g. "R addr N") to keep the array compact; the kernel driver merges them identically via dcc_config_add(). Estimated SRAM usage is ~19 KB, within the 24 KB (0x6000) budget for the Lemans DCC RAM. Move the lemans DCC configuration (entries array, link config, dcc config, and pdata) into a dedicated header qcom-dcc-lemans-config.h to avoid bloating qcom-dcc-dev.c with the large register table. Signed-off-by: Jie Gan (cherry picked from commit e4c2182d6741e7d5ab987e32ca7f3b8ef5befed9) --- drivers/misc/qcom-dcc-dev.c | 29 +- drivers/misc/qcom-dcc-lemans-config.h | 1630 +++++++++++++++++++++++++ 2 files changed, 1631 insertions(+), 28 deletions(-) create mode 100644 drivers/misc/qcom-dcc-lemans-config.h diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index 4d0c9c9526da3..d3dcda2d3e5fc 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -7,6 +7,7 @@ #include #include #include "qcom-dcc.h" +#include "qcom-dcc-lemans-config.h" #define DEV_NAME "qcom-dcc" @@ -793,34 +794,6 @@ static const struct dcc_pdata talos_pdata = { .config = &talos_config, }; -static const struct dcc_register_entry lemans_dcc_entries[] = { - { "R 0x610110 1" }, - { "R 0x9050008 1" }, -}; - -static const struct dcc_link_config lemans_link_configs[] = { - { - .link_list = 6, - .entries = lemans_dcc_entries, - .num_entries = ARRAY_SIZE(lemans_dcc_entries), - }, -}; - -static const struct dcc_config lemans_config = { - .lists = lemans_link_configs, - .num_lists = ARRAY_SIZE(lemans_link_configs), -}; - -static const struct dcc_pdata lemans_pdata = { - .base = 0x040ff000, - .size = 0x00001000, - .ram_base = 0x040b8800, - .ram_size = 0x00006000, - .dcc_offset = 0x38800, - .map_ver = 0x3, - .config = &lemans_config, -}; - static const struct dcc_pdata kodiak_pdata = { .base = 0x0117f000, .size = 0x00001000, diff --git a/drivers/misc/qcom-dcc-lemans-config.h b/drivers/misc/qcom-dcc-lemans-config.h new file mode 100644 index 0000000000000..01327a67eac91 --- /dev/null +++ b/drivers/misc/qcom-dcc-lemans-config.h @@ -0,0 +1,1630 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _QCOM_DCC_LEMANS_CONFIG_H +#define _QCOM_DCC_LEMANS_CONFIG_H + +#include "qcom-dcc.h" + +static const struct dcc_register_entry lemans_dcc_entries[] = { + /* lpm */ + { "R 0x18000040" }, + { "R 0x18000024" }, + { "R 0x18010024" }, + { "R 0x18010040" }, + { "R 0x18020024" }, + { "R 0x18020040" }, + { "R 0x18030024" }, + { "R 0x18030040" }, + { "R 0x18040024" }, + { "R 0x18040040" }, + { "R 0x18050024" }, + { "R 0x18050040" }, + { "R 0x18060024" }, + { "R 0x18060040" }, + { "R 0x18070024" }, + { "R 0x18070040" }, + { "R 0x18080024" }, + { "R 0x18080040" }, + { "R 0x18090024" }, + { "R 0x18090040" }, + { "R 0x18090104" }, + { "R 0x180900f8" }, + { "R 0x180800f4" }, + { "R 0x18080104" }, + { "R 0x180800f8" }, + { "R 0x180900f4" }, + { "R 0x18210404 2" }, + { "R 0xb201024" }, + { "R 0xb201020" }, + { "R 0xb211020" }, + { "R 0xb221020" }, + { "R 0xb232020" }, + /* tsens */ + { "R 0xc222004" }, + { "R 0xc263014" }, + { "R 0xc2630e0" }, + { "R 0xc2630ec" }, + { "R 0xc2630a0 16" }, + { "R 0xc2630e8" }, + { "R 0xc26313c" }, + { "R 0xc223004" }, + { "R 0xc265014" }, + { "R 0xc2650e0" }, + { "R 0xc2650ec" }, + { "R 0xc2650a0 16" }, + { "R 0xc2650e8" }, + { "R 0xc26513c" }, + { "R 0xc224004" }, + { "R 0xc251014" }, + { "R 0xc2510e0" }, + { "R 0xc2510ec" }, + { "R 0xc2510a0 16" }, + { "R 0xc2510e8" }, + { "R 0xc25113c" }, + { "R 0xc225004" }, + { "R 0xc252014" }, + { "R 0xc2520e0" }, + { "R 0xc2520ec" }, + { "R 0xc2520a0 16" }, + { "R 0xc2520e8" }, + { "R 0xc25213c" }, + /* pll */ + { "R 0x182b0000 12" }, + { "R 0x182b003c" }, + { "R 0x182b4000 12" }, + { "R 0x182b403c" }, + { "R 0x18280044" }, + { "R 0x1828004c" }, + { "R 0x18280060" }, + { "R 0x18284044" }, + { "R 0x1828404c" }, + { "R 0x18284060" }, + { "R 0x182b2000 12" }, + { "R 0x182b203c" }, + { "R 0x182b6000 12" }, + { "R 0x182b603c" }, + { "R 0x18282044" }, + { "R 0x1828204c" }, + { "R 0x18282060" }, + { "R 0x18286044" }, + { "R 0x1828604c" }, + { "R 0x18286060" }, + /* limits */ + { "R 0xec80010" }, + { "R 0xec81000" }, + { "R 0xec81010 64" }, + { "R 0x18378220 2" }, + { "R 0x183782a0 2" }, + { "R 0x183784a0 12" }, + { "R 0x18378520" }, + { "R 0x18378588" }, + { "R 0x18378d90 12" }, + { "R 0x18379010 10" }, + { "R 0x18379090 10" }, + { "R 0x18379a90 8" }, + { "R 0x18370220 2" }, + { "R 0x183702a0 2" }, + { "R 0x183704a0 12" }, + { "R 0x18370520" }, + { "R 0x18370588" }, + { "R 0x18370d90 12" }, + { "R 0x18371010 10" }, + { "R 0x18371090 10" }, + { "R 0x18371a90 8" }, + { "R 0x26310220 3" }, + { "R 0x263102a0 3" }, + { "R 0x263104a0 6" }, + { "R 0x26310520" }, + { "R 0x26310588" }, + { "R 0x26310d90 8" }, + { "R 0x26311010 6" }, + { "R 0x26311090 6" }, + { "R 0x26311a90 3" }, + { "R 0x2a310220 3" }, + { "R 0x2a3102a0 3" }, + { "R 0x2a3104a0 6" }, + { "R 0x2a310520" }, + { "R 0x2a310588" }, + { "R 0x2a310d90 8" }, + { "R 0x2a311010 6" }, + { "R 0x2a311090 6" }, + { "R 0x2a311a90 3" }, + /* ddr */ + { "R 0x610110" }, + { "R 0x9050008" }, + { "R 0x905001c" }, + { "R 0x9050030" }, + { "R 0x9050050" }, + { "R 0x9050070" }, + { "R 0x9050948" }, + { "R 0x905104c" }, + { "R 0x9050078" }, + { "R 0x9050114" }, + { "R 0x90a0008 2" }, + { "R 0x90a0080" }, + { "R 0x90a1008 2" }, + { "R 0x90a80e4 2" }, + { "R 0x90a816c 2" }, + { "R 0x90a80f8" }, + { "R 0x90a8180 2" }, + { "R 0x90a81a0 2" }, + { "R 0x90a81c0 2" }, + { "R 0x90a81e4" }, + { "R 0x90a81f4" }, + { "R 0x90a8204" }, + { "R 0x90a8218" }, + { "R 0x90a8228" }, + { "R 0x90a8264 2" }, + { "R 0x90a8270" }, + { "R 0x90a80fc 4" }, + { "R 0x90a8148 2" }, + { "R 0x90a8158 2" }, + { "R 0x90a8190 2" }, + { "R 0x90a81b0 2" }, + { "R 0x90a81d0 2" }, + { "R 0x90a84f4" }, + { "R 0x90a8138" }, + { "R 0x90a8150" }, + { "R 0x90a8160" }, + { "R 0x90a8198" }, + { "R 0x90a81b8" }, + { "R 0x90a81d8" }, + { "R 0x90a8280" }, + { "R 0x90a819c" }, + { "R 0x90a81bc" }, + { "R 0x90a81dc" }, + { "R 0x90a821c" }, + { "R 0x90a822c" }, + { "R 0x90a84f8" }, + { "R 0x90a9204" }, + { "R 0x90a880c" }, + { "R 0x90a8834" }, + { "R 0x90a8840 2" }, + { "R 0x90a8850 2" }, + { "R 0x90a8860 3" }, + { "R 0x90a8878" }, + { "R 0x90a8884" }, + { "R 0x90a9260" }, + { "R 0x90a8900" }, + { "R 0x90a9134 2" }, + { "R 0x90a8880 3" }, + { "R 0x90e0000" }, + { "R 0x90e0008" }, + { "R 0x90e0010" }, + { "R 0x90e0020 8" }, + { "R 0x90e0248" }, + { "R 0x90e3100" }, + { "R 0x90e4100 7" }, + { "R 0x90e5008" }, + { "R 0x90e5010 3" }, + { "R 0x9080024" }, + { "R 0x908002c" }, + { "R 0x9080034" }, + { "R 0x908003c" }, + { "R 0x9080044" }, + { "R 0x908004c" }, + { "R 0x9080054 3" }, + { "R 0x90800b8 2" }, + { "R 0x90800c8" }, + { "R 0x90800d4" }, + { "R 0x90800e0" }, + { "R 0x90800ec" }, + { "R 0x90800f8" }, + { "R 0x9080104 2" }, + { "R 0x9080114" }, + { "R 0x9080144" }, + { "R 0x908014c" }, + { "R 0x9080168" }, + { "R 0x9080174" }, + { "R 0x90801ac" }, + { "R 0x90801b4" }, + { "R 0x90801bc" }, + { "R 0x90801c4" }, + { "R 0x90801cc" }, + { "R 0x90801d4" }, + { "R 0x90801dc" }, + { "R 0x90801e4" }, + { "R 0x90801ec" }, + { "R 0x90801f4 2" }, + { "R 0x90ba000" }, + { "R 0x90ba050" }, + { "R 0x90ba280" }, + { "R 0x90ba288" }, + { "R 0x9280610 4" }, + { "R 0x9280680 4" }, + { "R 0x9380610" }, + { "R 0x9280614" }, + { "R 0x9380618 2" }, + { "R 0x9380680 4" }, + { "R 0x9480610 4" }, + { "R 0x9480680 4" }, + { "R 0x9580610 4" }, + { "R 0x9580680 4" }, + { "R 0x9680610 4" }, + { "R 0x9680680 4" }, + { "R 0x9380610" }, + { "R 0x9280614" }, + { "R 0x9380618 2" }, + { "R 0x9380680 4" }, + { "R 0x9100008" }, + { "R 0x9100010" }, + { "R 0x9100408" }, + { "R 0x9100410" }, + { "R 0x9100808" }, + { "R 0x9100810" }, + { "R 0x9100c08" }, + { "R 0x9100c10" }, + { "R 0x9101008" }, + { "R 0x9101010" }, + { "R 0x9101408" }, + { "R 0x9101410" }, + { "R 0x9101808" }, + { "R 0x9101810" }, + { "R 0x9101c08" }, + { "R 0x9101c10" }, + { "R 0x9102008" }, + { "R 0x9102010" }, + { "R 0x9102408" }, + { "R 0x9102410" }, + { "R 0x9102808" }, + { "R 0x9102810" }, + { "R 0x9102c08" }, + { "R 0x9102c10" }, + { "R 0x9103000 3" }, + { "R 0x9103010 3" }, + { "R 0x9103080 3" }, + { "R 0x9103090 3" }, + { "R 0x9104008" }, + { "R 0x9105008" }, + { "R 0x9106008" }, + { "R 0x9107008" }, + { "R 0x9108008" }, + { "R 0x9108808" }, + { "R 0x9109008" }, + { "R 0x9109808" }, + { "R 0x9122008" }, + { "R 0x9122408" }, + { "R 0x9122808" }, + { "R 0x9122c08" }, + { "R 0x9123008" }, + { "R 0x9123408" }, + { "R 0x9123808" }, + { "R 0x9123c08" }, + { "R 0x9124008" }, + { "R 0x9124408" }, + { "R 0x9124808" }, + { "R 0x9124c08" }, + { "R 0x9138008" }, + { "R 0x9138088" }, + { "R 0x9138108" }, + { "R 0x9138188" }, + { "R 0x9138208" }, + { "R 0x9138288" }, + { "R 0x9138308" }, + { "R 0x9138388" }, + { "R 0x9138408" }, + { "R 0x9138488" }, + { "R 0x9138508" }, + { "R 0x9138588" }, + { "R 0x9138608" }, + { "R 0x9138688" }, + { "R 0x9140000 5" }, + { "R 0x9140018" }, + { "R 0x9140020 3" }, + { "R 0x9140030 3" }, + { "R 0x9140040 3" }, + { "R 0x9140400 5" }, + { "R 0x9140418" }, + { "R 0x9140420 3" }, + { "R 0x9140430 3" }, + { "R 0x9140440 3" }, + { "R 0x9140800 5" }, + { "R 0x9140818" }, + { "R 0x9140820 3" }, + { "R 0x9140830 3" }, + { "R 0x9140840 3" }, + { "R 0x9140c00 5" }, + { "R 0x9140c18" }, + { "R 0x9140c20 3" }, + { "R 0x9140c30 3" }, + { "R 0x9140c40 3" }, + { "R 0x9141000 5" }, + { "R 0x9141018" }, + { "R 0x9141020 3" }, + { "R 0x9141030 3" }, + { "R 0x9141040 3" }, + { "R 0x9141400 5" }, + { "R 0x9141418" }, + { "R 0x9141420 3" }, + { "R 0x9141430 3" }, + { "R 0x9141440 3" }, + { "R 0x9141800 3" }, + { "R 0x9141810 3" }, + { "R 0x9141880 3" }, + { "R 0x9141890 3" }, + { "R 0x9142008" }, + { "R 0x9143008" }, + { "R 0x9144008" }, + { "R 0x9145008" }, + { "R 0x9146008" }, + { "R 0x9147008" }, + { "R 0x9148008" }, + { "R 0x9149008" }, + { "R 0x914a008" }, + { "R 0x914b008" }, + { "R 0x914c008" }, + { "R 0x914d008" }, + { "R 0x914e008" }, + { "R 0x914e208" }, + { "R 0x914e408" }, + { "R 0x914e608" }, + { "R 0x914e808" }, + { "R 0x914ea08" }, + { "R 0x914f008" }, + { "R 0x914f808" }, + { "R 0x9150008" }, + { "R 0x9150808" }, + { "R 0x9151008" }, + { "R 0x9151808" }, + { "R 0x9152008" }, + { "R 0x9153008" }, + { "R 0x9154008" }, + { "R 0x9155008" }, + { "R 0x9156008" }, + { "R 0x9157008" }, + { "R 0x9163008" }, + { "R 0x9163010" }, + { "R 0x9165008" }, + { "R 0x9165010" }, + { "R 0x9167008" }, + { "R 0x9167010" }, + { "R 0x9169008" }, + { "R 0x9169010" }, + { "R 0x916b008" }, + { "R 0x916b010" }, + { "R 0x916d008" }, + { "R 0x916d010" }, + { "R 0x9170000 3" }, + { "R 0x9170010" }, + { "R 0x9170018" }, + { "R 0x9170020 6" }, + { "R 0x9170400 3" }, + { "R 0x9170410" }, + { "R 0x9170418" }, + { "R 0x9170420 6" }, + { "R 0x9170800 3" }, + { "R 0x9170810" }, + { "R 0x9170818" }, + { "R 0x9170820 6" }, + { "R 0x9170c00 3" }, + { "R 0x9170c10" }, + { "R 0x9170c18" }, + { "R 0x9170c20 6" }, + { "R 0x9171000 3" }, + { "R 0x9171010" }, + { "R 0x9171018" }, + { "R 0x9171020 6" }, + { "R 0x9171400 3" }, + { "R 0x9171410" }, + { "R 0x9171418" }, + { "R 0x9171420 6" }, + { "R 0x9178008" }, + { "R 0x9178088" }, + { "R 0x9178108" }, + { "R 0x9178188" }, + { "R 0x9178208" }, + { "R 0x9178288" }, + { "R 0x9178308" }, + { "R 0x9178388" }, + { "R 0x9178408" }, + { "R 0x9178488" }, + { "R 0x9178508" }, + { "R 0x9180000 5" }, + { "R 0x9180018" }, + { "R 0x9180020 3" }, + { "R 0x9180030 3" }, + { "R 0x9180040 3" }, + { "R 0x9180400 5" }, + { "R 0x9180418" }, + { "R 0x9180420 3" }, + { "R 0x9180430 3" }, + { "R 0x9180440 3" }, + { "R 0x9180800 3" }, + { "R 0x9180810 3" }, + { "R 0x9180880 3" }, + { "R 0x9180890 3" }, + { "R 0x9180900 3" }, + { "R 0x9180910 3" }, + { "R 0x9180a08" }, + { "R 0x9181008" }, + { "R 0x9181808" }, + { "R 0x9182208" }, + { "R 0x9182408" }, + { "R 0x9182608" }, + { "R 0x9182808" }, + { "R 0x9182a08" }, + { "R 0x9182c08" }, + { "R 0x9182e08" }, + { "R 0x9183008" }, + { "R 0x9183808" }, + { "R 0x9184008" }, + { "R 0x9185008" }, + { "R 0x9186008" }, + { "R 0x9187008" }, + { "R 0x9188008" }, + { "R 0x9189008" }, + { "R 0x918a008" }, + { "R 0x918b008" }, + { "R 0x9190000 3" }, + { "R 0x9190010" }, + { "R 0x9190018" }, + { "R 0x9190020 6" }, + { "R 0x9190400 3" }, + { "R 0x9190410" }, + { "R 0x9190418" }, + { "R 0x9190420 6" }, + { "R 0x9197008" }, + { "R 0x9197088" }, + { "R 0x9198008" }, + { "R 0x9198088" }, + { "R 0x9198108" }, + { "R 0x9198188" }, + { "R 0x9198208" }, + { "R 0x9198288" }, + { "R 0x9198308" }, + { "R 0x9198388" }, + { "R 0x9198408" }, + { "R 0x9198508" }, + { "R 0x9198588" }, + { "R 0x9198608" }, + { "R 0x9198688" }, + { "R 0x9198708" }, + { "R 0x9198788" }, + { "R 0x9198808" }, + { "R 0x9198888" }, + { "R 0x9198908" }, + { "R 0x9198988" }, + { "R 0x9198a08" }, + { "R 0x9198a88" }, + { "R 0x9198b08" }, + { "R 0x9198b88" }, + { "R 0x9198c08" }, + { "R 0x9198e40" }, + { "R 0x9198e48" }, + { "R 0x91a0008" }, + { "R 0x91a1008" }, + { "R 0x91a2008" }, + { "R 0x91a6040" }, + { "R 0x91a6048" }, + { "R 0x91a8100 4" }, + { "R 0x91ab100" }, + { "R 0x91ac040" }, + { "R 0x91ac048" }, + { "R 0x91ad008" }, + { "R 0x91ad010" }, + { "R 0x91ae008" }, + { "R 0x91ae010" }, + { "R 0x91af008" }, + { "R 0x91af010" }, + { "R 0x91b0008" }, + { "R 0x91b0010" }, + { "R 0x91b1008" }, + { "R 0x91b1010" }, + { "R 0x91b2008" }, + { "R 0x91b2010" }, + { "R 0x91b3008" }, + { "R 0x91b3010" }, + { "R 0x91b4008" }, + { "R 0x91b4010" }, + { "R 0x91b5008" }, + { "R 0x91b5010" }, + { "R 0x91b6008" }, + { "R 0x91b6010" }, + { "R 0x91b7008" }, + { "R 0x91b7010" }, + { "R 0x91b8008" }, + { "R 0x91b8010" }, + { "R 0x91b9008" }, + { "R 0x91b9010" }, + { "R 0x91ba008" }, + { "R 0x91ba010" }, + { "R 0x91c0008" }, + { "R 0x91c0208" }, + { "R 0x91c0408" }, + { "R 0x91c0608" }, + { "R 0x91c0808" }, + { "R 0x91c0a08" }, + { "R 0x91c0c08" }, + { "R 0x91c0e08" }, + { "R 0x91c1008" }, + { "R 0x91c1208" }, + { "R 0x91c1408" }, + { "R 0x91c1608" }, + { "R 0x91c1808" }, + { "R 0x91c1a08" }, + { "R 0x91c1c08" }, + { "R 0x91c1e08" }, + { "R 0x91d8008" }, + { "R 0x91d8088" }, + { "R 0x91d8108" }, + { "R 0x91d8188" }, + { "R 0x91d8208" }, + { "R 0x91d8288" }, + { "R 0x91d8308" }, + { "R 0x91d8388" }, + { "R 0x91d8408" }, + { "R 0x91d8488" }, + { "R 0x91d8508" }, + { "R 0x91d8588" }, + { "R 0x91d8608" }, + { "R 0x91d8688" }, + { "R 0x91d8708" }, + { "R 0x91d8788" }, + { "R 0x91e1008" }, + { "R 0x91e1088" }, + { "R 0x91e1108" }, + { "R 0x91e3008" }, + { "R 0x91e3010" }, + { "R 0x91e4008" }, + { "R 0x91e4010" }, + { "R 0x91e5008" }, + { "R 0x91e5010" }, + { "R 0x91e6008" }, + { "R 0x91e6010" }, + { "R 0x91e7008" }, + { "R 0x91e7010" }, + { "R 0x91e8008" }, + { "R 0x91e8010" }, + { "R 0x91e9008" }, + { "R 0x91e9010" }, + { "R 0x91ea008" }, + { "R 0x91ea010" }, + { "R 0x91eb008" }, + { "R 0x91eb010" }, + { "R 0x91ec008" }, + { "R 0x91ec010" }, + { "R 0x91ed008" }, + { "R 0x91ed010" }, + { "R 0x91ee008" }, + { "R 0x91ee010" }, + { "R 0x91ef008" }, + { "R 0x91ef010" }, + { "R 0x91f0008" }, + { "R 0x91f0010" }, + { "R 0x91f1008" }, + { "R 0x91f1010" }, + { "R 0x91f2008" }, + { "R 0x91f2010" }, + { "R 0x91f3008" }, + { "R 0x91f3010" }, + { "R 0x91f4008" }, + { "R 0x91f4010" }, + { "R 0x91f5008" }, + { "R 0x91f5010" }, + { "R 0x91f6008" }, + { "R 0x91f6010" }, + { "R 0x9220344 9" }, + { "R 0x9220370 7" }, + { "R 0x9220480" }, + { "R 0x9222400 26" }, + { "R 0x9222470 5" }, + { "R 0x922320c" }, + { "R 0x9223214 2" }, + { "R 0x9223220 4" }, + { "R 0x9223308" }, + { "R 0x9223318" }, + { "R 0x922358c" }, + { "R 0x9234010" }, + { "R 0x923801c 8" }, + { "R 0x9238050" }, + { "R 0x9238100 7" }, + { "R 0x923c004" }, + { "R 0x923c014" }, + { "R 0x923c020" }, + { "R 0x923c030" }, + { "R 0x923c05c 3" }, + { "R 0x923c074" }, + { "R 0x923c088" }, + { "R 0x923c0a0" }, + { "R 0x923c0b0" }, + { "R 0x923c0c0" }, + { "R 0x923c0d0" }, + { "R 0x923c0e0" }, + { "R 0x923c0f0" }, + { "R 0x923c100" }, + { "R 0x923d064" }, + { "R 0x9240008 6" }, + { "R 0x9240028" }, + { "R 0x924203c 6" }, + { "R 0x9242058 7" }, + { "R 0x924208c" }, + { "R 0x92420b0" }, + { "R 0x92420b8 3" }, + { "R 0x92420f4" }, + { "R 0x92420fc 7" }, + { "R 0x9242324 14" }, + { "R 0x9242410" }, + { "R 0x92430a8" }, + { "R 0x9248004 7" }, + { "R 0x9248024" }, + { "R 0x9248040" }, + { "R 0x9248048" }, + { "R 0x9249064" }, + { "R 0x924c000" }, + { "R 0x924c030 3" }, + { "R 0x924c040 3" }, + { "R 0x924c054 2" }, + { "R 0x924c078" }, + { "R 0x924c108" }, + { "R 0x924c110" }, + { "R 0x9250020" }, + { "R 0x9251054" }, + { "R 0x9252014 3" }, + { "R 0x9252028 17" }, + { "R 0x9252070 8" }, + { "R 0x9252098" }, + { "R 0x92520a0" }, + { "R 0x92520b4" }, + { "R 0x92520c0 4" }, + { "R 0x92520f4 10" }, + { "R 0x9252120 12" }, + { "R 0x925802c" }, + { "R 0x925809c 2" }, + { "R 0x92580a8 3" }, + { "R 0x92580b8" }, + { "R 0x92580c0 7" }, + { "R 0x92580e0" }, + { "R 0x92580e8" }, + { "R 0x92580f0" }, + { "R 0x92580f8" }, + { "R 0x9258100" }, + { "R 0x9258108" }, + { "R 0x9258110" }, + { "R 0x9258118" }, + { "R 0x9258120" }, + { "R 0x9258128" }, + { "R 0x9258210 3" }, + { "R 0x9259010" }, + { "R 0x9259070" }, + { "R 0x925b004" }, + { "R 0x926004c 10" }, + { "R 0x9260078" }, + { "R 0x926020c" }, + { "R 0x9260214" }, + { "R 0x9261084" }, + { "R 0x9262020" }, + { "R 0x9263020" }, + { "R 0x9264020" }, + { "R 0x9265020" }, + { "R 0x9320344 9" }, + { "R 0x9320370 7" }, + { "R 0x9320480" }, + { "R 0x9322400 26" }, + { "R 0x9322470 5" }, + { "R 0x932320c" }, + { "R 0x9323214 2" }, + { "R 0x9323220 4" }, + { "R 0x9323308" }, + { "R 0x9323318" }, + { "R 0x932358c" }, + { "R 0x9334010" }, + { "R 0x933801c 8" }, + { "R 0x9338050" }, + { "R 0x9338100 7" }, + { "R 0x933c004" }, + { "R 0x933c014" }, + { "R 0x933c020" }, + { "R 0x933c030" }, + { "R 0x933c05c 3" }, + { "R 0x933c074" }, + { "R 0x933c088" }, + { "R 0x933c0a0" }, + { "R 0x933c0b0" }, + { "R 0x933c0c0" }, + { "R 0x933c0d0" }, + { "R 0x933c0e0" }, + { "R 0x933c0f0" }, + { "R 0x933c100" }, + { "R 0x933d064" }, + { "R 0x9340008 6" }, + { "R 0x9340028" }, + { "R 0x934203c 6" }, + { "R 0x9342058 7" }, + { "R 0x934208c" }, + { "R 0x93420b0" }, + { "R 0x93420b8 3" }, + { "R 0x93420f4" }, + { "R 0x93420fc 7" }, + { "R 0x9342324 14" }, + { "R 0x9342410" }, + { "R 0x93430a8" }, + { "R 0x9348004 7" }, + { "R 0x9348024" }, + { "R 0x9348040" }, + { "R 0x9348048" }, + { "R 0x9349064" }, + { "R 0x934c000" }, + { "R 0x934c030 3" }, + { "R 0x934c040 3" }, + { "R 0x934c054 2" }, + { "R 0x934c078" }, + { "R 0x934c108" }, + { "R 0x934c110" }, + { "R 0x9350020" }, + { "R 0x9351054" }, + { "R 0x9352014 3" }, + { "R 0x9352028 17" }, + { "R 0x9352070 8" }, + { "R 0x9352098" }, + { "R 0x93520a0" }, + { "R 0x93520b4" }, + { "R 0x93520c0 4" }, + { "R 0x93520f4 10" }, + { "R 0x9352120 12" }, + { "R 0x935802c" }, + { "R 0x935809c 2" }, + { "R 0x93580a8 3" }, + { "R 0x93580b8" }, + { "R 0x93580c0 7" }, + { "R 0x93580e0" }, + { "R 0x93580e8" }, + { "R 0x93580f0" }, + { "R 0x93580f8" }, + { "R 0x9358100" }, + { "R 0x9358108" }, + { "R 0x9358110" }, + { "R 0x9358118" }, + { "R 0x9358120" }, + { "R 0x9358128" }, + { "R 0x9358210 3" }, + { "R 0x9359010" }, + { "R 0x9359070" }, + { "R 0x935b004" }, + { "R 0x936004c 10" }, + { "R 0x9360078" }, + { "R 0x936020c" }, + { "R 0x9360214" }, + { "R 0x9361084" }, + { "R 0x9362020" }, + { "R 0x9363020" }, + { "R 0x9364020" }, + { "R 0x9365020" }, + { "R 0x9420344 9" }, + { "R 0x9420370 7" }, + { "R 0x9420480" }, + { "R 0x9422400 26" }, + { "R 0x9422470 5" }, + { "R 0x942320c" }, + { "R 0x9423214 2" }, + { "R 0x9423220 4" }, + { "R 0x9423308" }, + { "R 0x9423318" }, + { "R 0x942358c" }, + { "R 0x9434010" }, + { "R 0x943801c 8" }, + { "R 0x9438050" }, + { "R 0x9438100 7" }, + { "R 0x943c004" }, + { "R 0x943c014" }, + { "R 0x943c020" }, + { "R 0x943c030" }, + { "R 0x943c05c 3" }, + { "R 0x943c074" }, + { "R 0x943c088" }, + { "R 0x943c0a0" }, + { "R 0x943c0b0" }, + { "R 0x943c0c0" }, + { "R 0x943c0d0" }, + { "R 0x943c0e0" }, + { "R 0x943c0f0" }, + { "R 0x943c100" }, + { "R 0x943d064" }, + { "R 0x9440008 6" }, + { "R 0x9440028" }, + { "R 0x944203c 6" }, + { "R 0x9442058 7" }, + { "R 0x944208c" }, + { "R 0x94420b0" }, + { "R 0x94420b8 3" }, + { "R 0x94420f4" }, + { "R 0x94420fc 7" }, + { "R 0x9442324 14" }, + { "R 0x9442410" }, + { "R 0x94430a8" }, + { "R 0x9448004 7" }, + { "R 0x9448024" }, + { "R 0x9448040" }, + { "R 0x9448048" }, + { "R 0x9449064" }, + { "R 0x944c000" }, + { "R 0x944c030 3" }, + { "R 0x944c040 3" }, + { "R 0x944c054 2" }, + { "R 0x944c078" }, + { "R 0x944c108" }, + { "R 0x944c110" }, + { "R 0x9450020" }, + { "R 0x9451054" }, + { "R 0x9452014 3" }, + { "R 0x9452028 17" }, + { "R 0x9452070 8" }, + { "R 0x9452098" }, + { "R 0x94520a0" }, + { "R 0x94520b4" }, + { "R 0x94520c0 4" }, + { "R 0x94520f4 10" }, + { "R 0x9452120 12" }, + { "R 0x945802c" }, + { "R 0x945809c 2" }, + { "R 0x94580a8 3" }, + { "R 0x94580b8" }, + { "R 0x94580c0 7" }, + { "R 0x94580e0" }, + { "R 0x94580e8" }, + { "R 0x94580f0" }, + { "R 0x94580f8" }, + { "R 0x9458100" }, + { "R 0x9458108" }, + { "R 0x9458110" }, + { "R 0x9458118" }, + { "R 0x9458120" }, + { "R 0x9458128" }, + { "R 0x9458210 3" }, + { "R 0x9459010" }, + { "R 0x9459070" }, + { "R 0x945b004" }, + { "R 0x946004c 10" }, + { "R 0x9460078" }, + { "R 0x946020c" }, + { "R 0x9460214" }, + { "R 0x9461084" }, + { "R 0x9462020" }, + { "R 0x9463020" }, + { "R 0x9464020" }, + { "R 0x9465020" }, + { "R 0x9520344 9" }, + { "R 0x9520370 7" }, + { "R 0x9520480" }, + { "R 0x9522400 26" }, + { "R 0x9522470 5" }, + { "R 0x952320c" }, + { "R 0x9523214 2" }, + { "R 0x9523220 4" }, + { "R 0x9523308" }, + { "R 0x9523318" }, + { "R 0x952358c" }, + { "R 0x9534010" }, + { "R 0x953801c 8" }, + { "R 0x9538050" }, + { "R 0x9538100 7" }, + { "R 0x953c004" }, + { "R 0x953c014" }, + { "R 0x953c020" }, + { "R 0x953c030" }, + { "R 0x953c05c 3" }, + { "R 0x953c074" }, + { "R 0x953c088" }, + { "R 0x953c0a0" }, + { "R 0x953c0b0" }, + { "R 0x953c0c0" }, + { "R 0x953c0d0" }, + { "R 0x953c0e0" }, + { "R 0x953c0f0" }, + { "R 0x953c100" }, + { "R 0x953d064" }, + { "R 0x9540008 6" }, + { "R 0x9540028" }, + { "R 0x954203c 6" }, + { "R 0x9542058 7" }, + { "R 0x954208c" }, + { "R 0x95420b0" }, + { "R 0x95420b8 3" }, + { "R 0x95420f4" }, + { "R 0x95420fc 7" }, + { "R 0x9542324 14" }, + { "R 0x9542410" }, + { "R 0x95430a8" }, + { "R 0x9548004 7" }, + { "R 0x9548024" }, + { "R 0x9548040" }, + { "R 0x9548048" }, + { "R 0x9549064" }, + { "R 0x954c000" }, + { "R 0x954c030 3" }, + { "R 0x954c040 3" }, + { "R 0x954c054 2" }, + { "R 0x954c078" }, + { "R 0x954c108" }, + { "R 0x954c110" }, + { "R 0x9550020" }, + { "R 0x9551054" }, + { "R 0x9552014 3" }, + { "R 0x9552028 17" }, + { "R 0x9552070 8" }, + { "R 0x9552098" }, + { "R 0x95520a0" }, + { "R 0x95520b4" }, + { "R 0x95520c0 4" }, + { "R 0x95520f4 10" }, + { "R 0x9552120 12" }, + { "R 0x955802c" }, + { "R 0x955809c 2" }, + { "R 0x95580a8 3" }, + { "R 0x95580b8" }, + { "R 0x95580c0 7" }, + { "R 0x95580e0" }, + { "R 0x95580e8" }, + { "R 0x95580f0" }, + { "R 0x95580f8" }, + { "R 0x9558100" }, + { "R 0x9558108" }, + { "R 0x9558110" }, + { "R 0x9558118" }, + { "R 0x9558120" }, + { "R 0x9558128" }, + { "R 0x9558210 3" }, + { "R 0x9559010" }, + { "R 0x9559070" }, + { "R 0x955b004" }, + { "R 0x956004c 10" }, + { "R 0x9560078" }, + { "R 0x956020c" }, + { "R 0x9560214" }, + { "R 0x9561084" }, + { "R 0x9562020" }, + { "R 0x9563020" }, + { "R 0x9564020" }, + { "R 0x9565020" }, + { "R 0x9620344 9" }, + { "R 0x9620370 7" }, + { "R 0x9620480" }, + { "R 0x9622400 26" }, + { "R 0x9622470 5" }, + { "R 0x962320c" }, + { "R 0x9623214 2" }, + { "R 0x9623220 4" }, + { "R 0x9623308" }, + { "R 0x9623318" }, + { "R 0x962358c" }, + { "R 0x9634010" }, + { "R 0x963801c 8" }, + { "R 0x9638050" }, + { "R 0x9638100 7" }, + { "R 0x963c004" }, + { "R 0x963c014" }, + { "R 0x963c020" }, + { "R 0x963c030" }, + { "R 0x963c05c 3" }, + { "R 0x963c074" }, + { "R 0x963c088" }, + { "R 0x963c0a0" }, + { "R 0x963c0b0" }, + { "R 0x963c0c0" }, + { "R 0x963c0d0" }, + { "R 0x963c0e0" }, + { "R 0x963c0f0" }, + { "R 0x963c100" }, + { "R 0x963d064" }, + { "R 0x9640008 6" }, + { "R 0x9640028" }, + { "R 0x964203c 6" }, + { "R 0x9642058 7" }, + { "R 0x964208c" }, + { "R 0x96420b0" }, + { "R 0x96420b8 3" }, + { "R 0x96420f4" }, + { "R 0x96420fc 7" }, + { "R 0x9642324 14" }, + { "R 0x9642410" }, + { "R 0x96430a8" }, + { "R 0x9648004 7" }, + { "R 0x9648024" }, + { "R 0x9648040" }, + { "R 0x9648048" }, + { "R 0x9649064" }, + { "R 0x964c000" }, + { "R 0x964c030 3" }, + { "R 0x964c040 3" }, + { "R 0x964c054 2" }, + { "R 0x964c078" }, + { "R 0x964c108" }, + { "R 0x964c110" }, + { "R 0x9650020" }, + { "R 0x9651054" }, + { "R 0x9652014 3" }, + { "R 0x9652028 17" }, + { "R 0x9652070 8" }, + { "R 0x9652098" }, + { "R 0x96520a0" }, + { "R 0x96520b4" }, + { "R 0x96520c0 4" }, + { "R 0x96520f4 10" }, + { "R 0x9652120 12" }, + { "R 0x965802c" }, + { "R 0x965809c 2" }, + { "R 0x96580a8 3" }, + { "R 0x96580b8" }, + { "R 0x96580c0 7" }, + { "R 0x96580e0" }, + { "R 0x96580e8" }, + { "R 0x96580f0" }, + { "R 0x96580f8" }, + { "R 0x9658100" }, + { "R 0x9658108" }, + { "R 0x9658110" }, + { "R 0x9658118" }, + { "R 0x9658120" }, + { "R 0x9658128" }, + { "R 0x9658210 3" }, + { "R 0x9659010" }, + { "R 0x9659070" }, + { "R 0x965b004" }, + { "R 0x966004c 10" }, + { "R 0x9660078" }, + { "R 0x966020c" }, + { "R 0x9660214" }, + { "R 0x9661084" }, + { "R 0x9662020" }, + { "R 0x9663020" }, + { "R 0x9664020" }, + { "R 0x9665020" }, + { "R 0x9720344 9" }, + { "R 0x9720370 7" }, + { "R 0x9720480" }, + { "R 0x9722400 26" }, + { "R 0x9722470 5" }, + { "R 0x972320c" }, + { "R 0x9723214 2" }, + { "R 0x9723220 4" }, + { "R 0x9723308" }, + { "R 0x9723318" }, + { "R 0x972358c" }, + { "R 0x9734010" }, + { "R 0x973801c 8" }, + { "R 0x9738050" }, + { "R 0x9738100 7" }, + { "R 0x973c004" }, + { "R 0x973c014" }, + { "R 0x973c020" }, + { "R 0x973c030" }, + { "R 0x973c05c 3" }, + { "R 0x973c074" }, + { "R 0x973c088" }, + { "R 0x973c0a0" }, + { "R 0x973c0b0" }, + { "R 0x973c0c0" }, + { "R 0x973c0d0" }, + { "R 0x973c0e0" }, + { "R 0x973c0f0" }, + { "R 0x973c100" }, + { "R 0x973d064" }, + { "R 0x9740008 6" }, + { "R 0x9740028" }, + { "R 0x974203c 6" }, + { "R 0x9742058 7" }, + { "R 0x974208c" }, + { "R 0x97420b0" }, + { "R 0x97420b8 3" }, + { "R 0x97420f4" }, + { "R 0x97420fc 7" }, + { "R 0x9742324 14" }, + { "R 0x9742410" }, + { "R 0x97430a8" }, + { "R 0x9748004 7" }, + { "R 0x9748024" }, + { "R 0x9748040" }, + { "R 0x9748048" }, + { "R 0x9749064" }, + { "R 0x974c000" }, + { "R 0x974c030 3" }, + { "R 0x974c040 3" }, + { "R 0x974c054 2" }, + { "R 0x974c078" }, + { "R 0x974c108" }, + { "R 0x974c110" }, + { "R 0x9750020" }, + { "R 0x9751054" }, + { "R 0x9752014 3" }, + { "R 0x9752028 17" }, + { "R 0x9752070 8" }, + { "R 0x9752098" }, + { "R 0x97520a0" }, + { "R 0x97520b4" }, + { "R 0x97520c0 4" }, + { "R 0x97520f4 10" }, + { "R 0x9752120 12" }, + { "R 0x975802c" }, + { "R 0x975809c 2" }, + { "R 0x97580a8 3" }, + { "R 0x97580b8" }, + { "R 0x97580c0 7" }, + { "R 0x97580e0" }, + { "R 0x97580e8" }, + { "R 0x97580f0" }, + { "R 0x97580f8" }, + { "R 0x9758100" }, + { "R 0x9758108" }, + { "R 0x9758110" }, + { "R 0x9758118" }, + { "R 0x9758120" }, + { "R 0x9758128" }, + { "R 0x9758210 3" }, + { "R 0x9759010" }, + { "R 0x9759070" }, + { "R 0x975b004" }, + { "R 0x976004c 10" }, + { "R 0x9760078" }, + { "R 0x976020c" }, + { "R 0x9760214" }, + { "R 0x9761084" }, + { "R 0x9762020" }, + { "R 0x9763020" }, + { "R 0x9764020" }, + { "R 0x9765020" }, + { "R 0x92a0304" }, + { "R 0x92a0080" }, + { "R 0x92a0310" }, + { "R 0x92a0400 2" }, + { "R 0x92a0410 6" }, + { "R 0x92a0430" }, + { "R 0x92a0440" }, + { "R 0x92a0448" }, + { "R 0x92a04a0" }, + { "R 0x92a04b0 4" }, + { "R 0x92a04d0 2" }, + { "R 0x92a1400" }, + { "R 0x92a1408" }, + { "R 0x92a2400 2" }, + { "R 0x92a2438 2" }, + { "R 0x92a2454" }, + { "R 0x92a3400 4" }, + { "R 0x92a3418 3" }, + { "R 0x92a4700" }, + { "R 0x92a53b0" }, + { "R 0x92a5804" }, + { "R 0x92a590c" }, + { "R 0x92a5a14" }, + { "R 0x92a5c0c" }, + { "R 0x92a5c18 2" }, + { "R 0x92a5c2c 2" }, + { "R 0x92a5c38" }, + { "R 0x92a5c4c" }, + { "R 0x92a5ca4" }, + { "R 0x92a5cac 3" }, + { "R 0x92a6400" }, + { "R 0x92a6418 2" }, + { "R 0x92a9100" }, + { "R 0x92a9110" }, + { "R 0x92a9120" }, + { "R 0x92a9180 2" }, + { "R 0x92a91a0" }, + { "R 0x92a91b0" }, + { "R 0x92a91c0 2" }, + { "R 0x92a91e0" }, + { "R 0x93a0304" }, + { "R 0x93a0080" }, + { "R 0x93a0310" }, + { "R 0x93a0400 2" }, + { "R 0x93a0410 6" }, + { "R 0x93a0430" }, + { "R 0x93a0440" }, + { "R 0x93a0448" }, + { "R 0x93a04a0" }, + { "R 0x93a04b0 4" }, + { "R 0x93a04d0 2" }, + { "R 0x93a1400" }, + { "R 0x93a1408" }, + { "R 0x93a2400 2" }, + { "R 0x93a2438 2" }, + { "R 0x93a2454" }, + { "R 0x93a3400 4" }, + { "R 0x93a3418 3" }, + { "R 0x93a4700" }, + { "R 0x93a53b0" }, + { "R 0x93a5804" }, + { "R 0x93a590c" }, + { "R 0x93a5a14" }, + { "R 0x93a5c0c" }, + { "R 0x93a5c18 2" }, + { "R 0x93a5c2c 2" }, + { "R 0x93a5c38" }, + { "R 0x93a5c4c" }, + { "R 0x93a5ca4" }, + { "R 0x93a5cac 3" }, + { "R 0x93a6400" }, + { "R 0x93a6418 2" }, + { "R 0x93a9100" }, + { "R 0x93a9110" }, + { "R 0x93a9120" }, + { "R 0x93a9180 2" }, + { "R 0x93a91a0" }, + { "R 0x93a91b0" }, + { "R 0x93a91c0 2" }, + { "R 0x93a91e0" }, + { "R 0x94a0304" }, + { "R 0x94a0080" }, + { "R 0x94a0310" }, + { "R 0x94a0400 2" }, + { "R 0x94a0410 6" }, + { "R 0x94a0430" }, + { "R 0x94a0440" }, + { "R 0x94a0448" }, + { "R 0x94a04a0" }, + { "R 0x94a04b0 4" }, + { "R 0x94a04d0 2" }, + { "R 0x94a1400" }, + { "R 0x94a1408" }, + { "R 0x94a2400 2" }, + { "R 0x94a2438 2" }, + { "R 0x94a2454" }, + { "R 0x94a3400 4" }, + { "R 0x94a3418 3" }, + { "R 0x94a4700" }, + { "R 0x94a53b0" }, + { "R 0x94a5804" }, + { "R 0x94a590c" }, + { "R 0x94a5a14" }, + { "R 0x94a5c0c" }, + { "R 0x94a5c18 2" }, + { "R 0x94a5c2c 2" }, + { "R 0x94a5c38" }, + { "R 0x94a5c4c" }, + { "R 0x94a5ca4" }, + { "R 0x94a5cac 3" }, + { "R 0x94a6400" }, + { "R 0x94a6418 2" }, + { "R 0x94a9100" }, + { "R 0x94a9110" }, + { "R 0x94a9120" }, + { "R 0x94a9180 2" }, + { "R 0x94a91a0" }, + { "R 0x94a91b0" }, + { "R 0x94a91c0 2" }, + { "R 0x94a91e0" }, + { "R 0x95a0304" }, + { "R 0x95a0080" }, + { "R 0x95a0310" }, + { "R 0x95a0400 2" }, + { "R 0x95a0410 6" }, + { "R 0x95a0430" }, + { "R 0x95a0440" }, + { "R 0x95a0448" }, + { "R 0x95a04a0" }, + { "R 0x95a04b0 4" }, + { "R 0x95a04d0 2" }, + { "R 0x95a1400" }, + { "R 0x95a1408" }, + { "R 0x95a2400 2" }, + { "R 0x95a2438 2" }, + { "R 0x95a2454" }, + { "R 0x95a3400 4" }, + { "R 0x95a3418 3" }, + { "R 0x95a4700" }, + { "R 0x95a53b0" }, + { "R 0x95a5804" }, + { "R 0x95a590c" }, + { "R 0x95a5a14" }, + { "R 0x95a5c0c" }, + { "R 0x95a5c18 2" }, + { "R 0x95a5c2c 2" }, + { "R 0x95a5c38" }, + { "R 0x95a5c4c" }, + { "R 0x95a5ca4" }, + { "R 0x95a5cac 3" }, + { "R 0x95a6400" }, + { "R 0x95a6418 2" }, + { "R 0x95a9100" }, + { "R 0x95a9110" }, + { "R 0x95a9120" }, + { "R 0x95a9180 2" }, + { "R 0x95a91a0" }, + { "R 0x95a91b0" }, + { "R 0x95a91c0 2" }, + { "R 0x95a91e0" }, + { "R 0x96a0304" }, + { "R 0x96a0080" }, + { "R 0x96a0310" }, + { "R 0x96a0400 2" }, + { "R 0x96a0410 6" }, + { "R 0x96a0430" }, + { "R 0x96a0440" }, + { "R 0x96a0448" }, + { "R 0x96a04a0" }, + { "R 0x96a04b0 4" }, + { "R 0x96a04d0 2" }, + { "R 0x96a1400" }, + { "R 0x96a1408" }, + { "R 0x96a2400 2" }, + { "R 0x96a2438 2" }, + { "R 0x96a2454" }, + { "R 0x96a3400 4" }, + { "R 0x96a3418 3" }, + { "R 0x96a4700" }, + { "R 0x96a53b0" }, + { "R 0x96a5804" }, + { "R 0x96a590c" }, + { "R 0x96a5a14" }, + { "R 0x96a5c0c" }, + { "R 0x96a5c18 2" }, + { "R 0x96a5c2c 2" }, + { "R 0x96a5c38" }, + { "R 0x96a5c4c" }, + { "R 0x96a5ca4" }, + { "R 0x96a5cac 3" }, + { "R 0x96a6400" }, + { "R 0x96a6418 2" }, + { "R 0x96a9100" }, + { "R 0x96a9110" }, + { "R 0x96a9120" }, + { "R 0x96a9180 2" }, + { "R 0x96a91a0" }, + { "R 0x96a91b0" }, + { "R 0x96a91c0 2" }, + { "R 0x96a91e0" }, + { "R 0x97a0304" }, + { "R 0x97a0080" }, + { "R 0x97a0310" }, + { "R 0x97a0400 2" }, + { "R 0x97a0410 6" }, + { "R 0x97a0430" }, + { "R 0x97a0440" }, + { "R 0x97a0448" }, + { "R 0x97a04a0" }, + { "R 0x97a04b0 4" }, + { "R 0x97a04d0 2" }, + { "R 0x97a1400" }, + { "R 0x97a1408" }, + { "R 0x97a2400 2" }, + { "R 0x97a2438 2" }, + { "R 0x97a2454" }, + { "R 0x97a3400 4" }, + { "R 0x97a3418 3" }, + { "R 0x97a4700" }, + { "R 0x97a53b0" }, + { "R 0x97a5804" }, + { "R 0x97a590c" }, + { "R 0x97a5a14" }, + { "R 0x97a5c0c" }, + { "R 0x97a5c18 2" }, + { "R 0x97a5c2c 2" }, + { "R 0x97a5c38" }, + { "R 0x97a5c4c" }, + { "R 0x97a5ca4" }, + { "R 0x97a5cac 3" }, + { "R 0x97a6400" }, + { "R 0x97a6418 2" }, + { "R 0x97a9100" }, + { "R 0x97a9110" }, + { "R 0x97a9120" }, + { "R 0x97a9180 2" }, + { "R 0x97a91a0" }, + { "R 0x97a91b0" }, + { "R 0x97a91c0 2" }, + { "R 0x97a91e0" }, + { "R 0x9b01e64" }, + { "R 0x9b01ea0" }, + { "R 0x9b01f30 2" }, + { "R 0x9b03e64" }, + { "R 0x9b03ea0" }, + { "R 0x9b03f30 2" }, + { "R 0x9b0527c" }, + { "R 0x9b05290" }, + { "R 0x9b054ec" }, + { "R 0x9b054f4" }, + { "R 0x9b05514" }, + { "R 0x9b0551c" }, + { "R 0x9b05524" }, + { "R 0x9b05548" }, + { "R 0x9b05550" }, + { "R 0x9b05558" }, + { "R 0x9b055b8" }, + { "R 0x9b055c0" }, + { "R 0x9b055ec" }, + { "R 0x9b05860" }, + { "R 0x9b05870" }, + { "R 0x9b058a0" }, + { "R 0x9b058a8" }, + { "R 0x9b058b0" }, + { "R 0x9b058b8" }, + { "R 0x9b058d8 2" }, + { "R 0x9b058f4" }, + { "R 0x9b058fc" }, + { "R 0x9b05920" }, + { "R 0x9b05928" }, + { "R 0x9b05944" }, + { "R 0x9b06604" }, + { "R 0x9b0660c" }, + { "R 0x9b41e64" }, + { "R 0x9b41ea0" }, + { "R 0x9b41f30 2" }, + { "R 0x9b43e64" }, + { "R 0x9b43ea0" }, + { "R 0x9b43f30 2" }, + { "R 0x9b4527c" }, + { "R 0x9b45290" }, + { "R 0x9b454ec" }, + { "R 0x9b454f4" }, + { "R 0x9b45514" }, + { "R 0x9b4551c" }, + { "R 0x9b45524" }, + { "R 0x9b45548" }, + { "R 0x9b45550" }, + { "R 0x9b45558" }, + { "R 0x9b455b8" }, + { "R 0x9b455c0" }, + { "R 0x9b455ec" }, + { "R 0x9b45860" }, + { "R 0x9b45870" }, + { "R 0x9b458a0" }, + { "R 0x9b458a8" }, + { "R 0x9b458b0" }, + { "R 0x9b458b8" }, + { "R 0x9b458d8 2" }, + { "R 0x9b458f4" }, + { "R 0x9b458fc" }, + { "R 0x9b45920" }, + { "R 0x9b45928" }, + { "R 0x9b45944" }, + { "R 0x9b46604" }, + { "R 0x9b4660c" }, + { "R 0x9b81e64" }, + { "R 0x9b81ea0" }, + { "R 0x9b81f30 2" }, + { "R 0x9b83e64" }, + { "R 0x9b83ea0" }, + { "R 0x9b83f30 2" }, + { "R 0x9b8527c" }, + { "R 0x9b85290" }, + { "R 0x9b854ec" }, + { "R 0x9b854f4" }, + { "R 0x9b85514" }, + { "R 0x9b8551c" }, + { "R 0x9b85524" }, + { "R 0x9b85548" }, + { "R 0x9b85550" }, + { "R 0x9b85558" }, + { "R 0x9b855b8" }, + { "R 0x9b855c0" }, + { "R 0x9b855ec" }, + { "R 0x9b85860" }, + { "R 0x9b85870" }, + { "R 0x9b858a0" }, + { "R 0x9b858a8" }, + { "R 0x9b858b0" }, + { "R 0x9b858b8" }, + { "R 0x9b858d8 2" }, + { "R 0x9b858f4" }, + { "R 0x9b858fc" }, + { "R 0x9b85920" }, + { "R 0x9b85928" }, + { "R 0x9b85944" }, + { "R 0x9b86604" }, + { "R 0x9b8660c" }, + { "R 0x9bc1e64" }, + { "R 0x9bc1ea0" }, + { "R 0x9bc1f30 2" }, + { "R 0x9bc3e64" }, + { "R 0x9bc3ea0" }, + { "R 0x9bc3f30 2" }, + { "R 0x9bc527c" }, + { "R 0x9bc5290" }, + { "R 0x9bc54ec" }, + { "R 0x9bc54f4" }, + { "R 0x9bc5514" }, + { "R 0x9bc551c" }, + { "R 0x9bc5524" }, + { "R 0x9bc5548" }, + { "R 0x9bc5550" }, + { "R 0x9bc5558" }, + { "R 0x9bc55b8" }, + { "R 0x9bc55c0" }, + { "R 0x9bc55ec" }, + { "R 0x9bc5860" }, + { "R 0x9bc5870" }, + { "R 0x9bc58a0" }, + { "R 0x9bc58a8" }, + { "R 0x9bc58b0" }, + { "R 0x9bc58b8" }, + { "R 0x9bc58d8 2" }, + { "R 0x9bc58f4" }, + { "R 0x9bc58fc" }, + { "R 0x9bc5920" }, + { "R 0x9bc5928" }, + { "R 0x9bc5944" }, + { "R 0x9bc6604" }, + { "R 0x9bc660c" }, + { "R 0x9c01e64" }, + { "R 0x9c01ea0" }, + { "R 0x9c01f30 2" }, + { "R 0x9c03e64" }, + { "R 0x9c03ea0" }, + { "R 0x9c03f30 2" }, + { "R 0x9c0527c" }, + { "R 0x9c05290" }, + { "R 0x9c054ec" }, + { "R 0x9c054f4" }, + { "R 0x9c05514" }, + { "R 0x9c0551c" }, + { "R 0x9c05524" }, + { "R 0x9c05548" }, + { "R 0x9c05550" }, + { "R 0x9c05558" }, + { "R 0x9c055b8" }, + { "R 0x9c055c0" }, + { "R 0x9c055ec" }, + { "R 0x9c05860" }, + { "R 0x9c05870" }, + { "R 0x9c058a0" }, + { "R 0x9c058a8" }, + { "R 0x9c058b0" }, + { "R 0x9c058b8" }, + { "R 0x9c058d8 2" }, + { "R 0x9c058f4" }, + { "R 0x9c058fc" }, + { "R 0x9c05920" }, + { "R 0x9c05928" }, + { "R 0x9c05944" }, + { "R 0x9c06604" }, + { "R 0x9c0660c" }, + { "R 0x9c41e64" }, + { "R 0x9c41ea0" }, + { "R 0x9c41f30 2" }, + { "R 0x9c43e64" }, + { "R 0x9c43ea0" }, + { "R 0x9c43f30 2" }, + { "R 0x9c4527c" }, + { "R 0x9c45290" }, + { "R 0x9c454ec" }, + { "R 0x9c454f4" }, + { "R 0x9c45514" }, + { "R 0x9c4551c" }, + { "R 0x9c45524" }, + { "R 0x9c45548" }, + { "R 0x9c45550" }, + { "R 0x9c45558" }, + { "R 0x9c455b8" }, + { "R 0x9c455c0" }, + { "R 0x9c455ec" }, + { "R 0x9c45860" }, + { "R 0x9c45870" }, + { "R 0x9c458a0" }, + { "R 0x9c458a8" }, + { "R 0x9c458b0" }, + { "R 0x9c458b8" }, + { "R 0x9c458d8 2" }, + { "R 0x9c458f4" }, + { "R 0x9c458fc" }, + { "R 0x9c45920" }, + { "R 0x9c45928" }, + { "R 0x9c45944" }, + { "R 0x9c46604" }, + { "R 0x9c4660c" }, +}; + +static const struct dcc_link_config lemans_link_configs[] = { + { + .link_list = 6, + .entries = lemans_dcc_entries, + .num_entries = ARRAY_SIZE(lemans_dcc_entries), + }, +}; + +static const struct dcc_config lemans_config = { + .lists = lemans_link_configs, + .num_lists = ARRAY_SIZE(lemans_link_configs), +}; + +static const struct dcc_pdata lemans_pdata = { + .base = 0x040ff000, + .size = 0x00001000, + .ram_base = 0x040b8800, + .ram_size = 0x00006000, + .dcc_offset = 0x38800, + .map_ver = 0x3, + .config = &lemans_config, +}; + +#endif /* _QCOM_DCC_LEMANS_CONFIG_H */ From 26b487ed89616635c015b0209d5fae01d6014594 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 29 Apr 2026 11:34:33 +0800 Subject: [PATCH 0605/1330] QCLINUX: qcom-dcc: move talos config to qcom-dcc-talos-config.h Move the talos DCC configuration (entries array, link config, dcc config, and pdata) into a dedicated header qcom-dcc-talos-config.h, consistent with the approach used for the lemans config. Signed-off-by: Jie Gan (cherry picked from commit 3feb4d9e64e2f54665c8d5b9617d78b7180197a3) --- drivers/misc/qcom-dcc-dev.c | 782 +------------------------- drivers/misc/qcom-dcc-talos-config.h | 792 +++++++++++++++++++++++++++ 2 files changed, 793 insertions(+), 781 deletions(-) create mode 100644 drivers/misc/qcom-dcc-talos-config.h diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index d3dcda2d3e5fc..83efad89b4d76 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -7,793 +7,13 @@ #include #include #include "qcom-dcc.h" +#include "qcom-dcc-talos-config.h" #include "qcom-dcc-lemans-config.h" #define DEV_NAME "qcom-dcc" static struct platform_device *dcc_pdev; -static const struct dcc_register_entry talos_dcc_entries[] = { - { "R 0x9680000" }, - { "R 0x9680004" }, - { "R 0x9681000" }, - { "R 0x9681004" }, - { "R 0x9681008" }, - { "R 0x968100c" }, - { "R 0x9681010" }, - { "R 0x9681014" }, - { "R 0x968101c" }, - { "R 0x9681020" }, - { "R 0x9681024" }, - { "R 0x9681028" }, - { "R 0x968102c" }, - { "R 0x9681030" }, - { "R 0x9681034" }, - { "R 0x968103c" }, - { "R 0x9698100" }, - { "R 0x9698104" }, - { "R 0x9698108" }, - { "R 0x9698110" }, - { "R 0x9698120" }, - { "R 0x9698124" }, - { "R 0x9698128" }, - { "R 0x969812c" }, - { "R 0x9698130" }, - { "R 0x9698134" }, - { "R 0x9698138" }, - { "R 0x969813c" }, - { "R 0x9698500" }, - { "R 0x9698504" }, - { "R 0x9698508" }, - { "R 0x969850c" }, - { "R 0x9698510" }, - { "R 0x9698514" }, - { "R 0x9698518" }, - { "R 0x969851c" }, - { "R 0x9698700" }, - { "R 0x9698704" }, - { "R 0x9698708" }, - { "R 0x969870c" }, - { "R 0x9698714" }, - { "R 0x9698718" }, - { "R 0x969871c" }, - { "R 0x1620204" }, - { "R 0x1620240" }, - { "R 0x1620248" }, - { "R 0x1620288" }, - { "R 0x162028C" }, - { "R 0x1620290" }, - { "R 0x1620294" }, - { "R 0x16202A8" }, - { "R 0x16202AC" }, - { "R 0x16202B0" }, - { "R 0x16202B4" }, - { "R 0x1620300" }, - { "R 0x1700204" }, - { "R 0x1700240" }, - { "R 0x1700248" }, - { "R 0x1700288" }, - { "R 0x1700290" }, - { "R 0x1700300" }, - { "R 0x1700304" }, - { "R 0x1700308" }, - { "R 0x170030C" }, - { "R 0x1700310" }, - { "R 0x1700314" }, - { "R 0x1700C08" }, - { "R 0x1700C10" }, - { "R 0x1700C20" }, - { "R 0x1700C24" }, - { "R 0x1700C28" }, - { "R 0x1700C2C" }, - { "R 0x1700C30" }, - { "R 0x1700C34" }, - { "R 0x1700C38" }, - { "R 0x1700C3C" }, - { "R 0x1740240" }, - { "R 0x1740248" }, - { "R 0x1740288" }, - { "R 0x1740290" }, - { "R 0x1740300" }, - { "R 0x1740304" }, - { "R 0x1740308" }, - { "R 0x174030C" }, - { "R 0x1740310" }, - { "R 0x1740314" }, - { "R 0x1740004" }, - { "R 0x1740008" }, - { "R 0x1740010" }, - { "R 0x1740020" }, - { "R 0x1740024" }, - { "R 0x1740028" }, - { "R 0x174002C" }, - { "R 0x1740030" }, - { "R 0x1740034" }, - { "R 0x1740038" }, - { "R 0x174003C" }, - { "R 0x9698204" }, - { "R 0x9698240" }, - { "R 0x9698244" }, - { "R 0x9698248" }, - { "R 0x969824C" }, - { "R 0x9681010" }, - { "R 0x9681014" }, - { "R 0x9681018" }, - { "R 0x968101C" }, - { "R 0x9681020" }, - { "R 0x9681024" }, - { "R 0x9681028" }, - { "R 0x968102C" }, - { "R 0x9681030" }, - { "R 0x9681034" }, - { "R 0x968103C" }, - { "R 0x9698100" }, - { "R 0x9698104" }, - { "R 0x9698108" }, - { "R 0x9698110" }, - { "R 0x9698120" }, - { "R 0x9698124" }, - { "R 0x9698128" }, - { "R 0x969812C" }, - { "R 0x9698130" }, - { "R 0x9698134" }, - { "R 0x9698138" }, - { "R 0x969813C" }, - { "R 0x62BE2004" }, - { "R 0x62BE2040" }, - { "R 0x62BE2048" }, - { "R 0x62BE2088" }, - { "R 0x62BE2090" }, - { "R 0x62BE2100" }, - { "R 0x62BE2104" }, - { "R 0x62BE2108" }, - { "R 0x62BE210C" }, - { "R 0x62BE2110" }, - { "R 0x62BE2114" }, - { "R 0x62BE2118" }, - { "R 0x62BE0010" }, - { "R 0x62BE0020" }, - { "R 0x62BE0024" }, - { "R 0x62BE0028" }, - { "R 0x62BE002C" }, - { "R 0x62BE0030" }, - { "R 0x62BE0034" }, - { "R 0x62BE0038" }, - { "R 0x62BE003C" }, - { "R 0x9160204" }, - { "R 0x9160240" }, - { "R 0x9160248" }, - { "R 0x9160288" }, - { "R 0x9160290" }, - { "R 0x9160300" }, - { "R 0x9160304" }, - { "R 0x9160308" }, - { "R 0x916030C" }, - { "R 0x9160310" }, - { "R 0x9160314" }, - { "R 0x9160318" }, - { "R 0x9160008" }, - { "R 0x9160010" }, - { "R 0x9160020" }, - { "R 0x9160024" }, - { "R 0x9160028" }, - { "R 0x916002C" }, - { "R 0x9160030" }, - { "R 0x9160034" }, - { "R 0x9160038" }, - { "R 0x916003C" }, - { "R 0x1620500 4" }, - { "R 0x1620700 4" }, - { "R 0x1620300" }, - { "R 0x1620F00 2" }, - { "R 0x1620B00 2" }, - { "R 0x1700B00 2" }, - { "R 0x1700700 3" }, - { "R 0x9163100" }, - { "R 0x96AA100" }, - { "R 0x9050008" }, - { "R 0x9050068" }, - { "R 0x9050078" }, - { "R 0x18200400" }, - { "R 0x18200404" }, - { "R 0x18200408" }, - { "R 0x18200038" }, - { "R 0x18200040" }, - { "R 0x18200048" }, - { "R 0x18220038" }, - { "R 0x18220040" }, - { "R 0x182200D0" }, - { "R 0x18200030" }, - { "R 0x18200010" }, - { "R 0x1822000c" }, - { "R 0x18220d14" }, - { "R 0x18220fb4" }, - { "R 0x18221254" }, - { "R 0x182214f4" }, - { "R 0x18221794" }, - { "R 0x18221a34" }, - { "R 0x18221cd4" }, - { "R 0x18221f74" }, - { "R 0x18220d18" }, - { "R 0x18220fb8" }, - { "R 0x18221258" }, - { "R 0x182214f8" }, - { "R 0x18221798" }, - { "R 0x18221a38" }, - { "R 0x18221cd8" }, - { "R 0x18221f78" }, - { "R 0x18220d00" }, - { "R 0x18220d04" }, - { "R 0x18220d1c" }, - { "R 0x18220fbc" }, - { "R 0x1822125c" }, - { "R 0x182214fc" }, - { "R 0x1822179c" }, - { "R 0x18221a3c" }, - { "R 0x18221cdc" }, - { "R 0x18221f7c" }, - { "R 0x18221274" }, - { "R 0x18221288" }, - { "R 0x1822129c" }, - { "R 0x182212b0" }, - { "R 0x182212c4" }, - { "R 0x182212d8" }, - { "R 0x182212ec" }, - { "R 0x18221300" }, - { "R 0x18221314" }, - { "R 0x18221328" }, - { "R 0x1822133c" }, - { "R 0x18221350" }, - { "R 0x18221364" }, - { "R 0x18221378" }, - { "R 0x1822138c" }, - { "R 0x182213a0" }, - { "R 0x18221514" }, - { "R 0x18221528" }, - { "R 0x1822153c" }, - { "R 0x18221550" }, - { "R 0x18221564" }, - { "R 0x18221578" }, - { "R 0x1822158c" }, - { "R 0x182215a0" }, - { "R 0x182215b4" }, - { "R 0x182215c8" }, - { "R 0x182215dc" }, - { "R 0x182215f0" }, - { "R 0x18221604" }, - { "R 0x18221618" }, - { "R 0x1822162c" }, - { "R 0x18221640" }, - { "R 0x182217b4" }, - { "R 0x182217c8" }, - { "R 0x182217dc" }, - { "R 0x182217f0" }, - { "R 0x18221804" }, - { "R 0x18221818" }, - { "R 0x1822182c" }, - { "R 0x18221840" }, - { "R 0x18221854" }, - { "R 0x18221868" }, - { "R 0x1822187c" }, - { "R 0x18221890" }, - { "R 0x182218a4" }, - { "R 0x182218b8" }, - { "R 0x182218cc" }, - { "R 0x182218e0" }, - { "R 0x18221a54" }, - { "R 0x18221a68" }, - { "R 0x18221a7c" }, - { "R 0x18221a90" }, - { "R 0x18221aa4" }, - { "R 0x18221ab8" }, - { "R 0x18221acc" }, - { "R 0x18221ae0" }, - { "R 0x18221af4" }, - { "R 0x18221b08" }, - { "R 0x18221b1c" }, - { "R 0x18221b30" }, - { "R 0x18221b44" }, - { "R 0x18221b58" }, - { "R 0x18221b6c" }, - { "R 0x18221b80" }, - { "R 0x18221cf4" }, - { "R 0x18221d08" }, - { "R 0x18221d1c" }, - { "R 0x18221d30" }, - { "R 0x18221d44" }, - { "R 0x18221d58" }, - { "R 0x18221d6c" }, - { "R 0x18221d80" }, - { "R 0x18221d94" }, - { "R 0x18221da8" }, - { "R 0x18221dbc" }, - { "R 0x18221dd0" }, - { "R 0x18221de4" }, - { "R 0x18221df8" }, - { "R 0x18221e0c" }, - { "R 0x18221e20" }, - { "R 0x18221f94" }, - { "R 0x18221fa8" }, - { "R 0x18221fbc" }, - { "R 0x18221fd0" }, - { "R 0x18221fe4" }, - { "R 0x18221ff8" }, - { "R 0x1822200c" }, - { "R 0x18222020" }, - { "R 0x18222034" }, - { "R 0x18222048" }, - { "R 0x1822205c" }, - { "R 0x18222070" }, - { "R 0x18222084" }, - { "R 0x18222098" }, - { "R 0x182220ac" }, - { "R 0x182220c0" }, - { "R 0x18221278" }, - { "R 0x1822128c" }, - { "R 0x182212a0" }, - { "R 0x182212b4" }, - { "R 0x182212c8" }, - { "R 0x182212dc" }, - { "R 0x182212f0" }, - { "R 0x18221304" }, - { "R 0x18221318" }, - { "R 0x1822132c" }, - { "R 0x18221340" }, - { "R 0x18221354" }, - { "R 0x18221368" }, - { "R 0x1822137c" }, - { "R 0x18221390" }, - { "R 0x182213a4" }, - { "R 0x18221518" }, - { "R 0x1822152c" }, - { "R 0x18221540" }, - { "R 0x18221554" }, - { "R 0x18221568" }, - { "R 0x1822157c" }, - { "R 0x18221590" }, - { "R 0x182215a4" }, - { "R 0x182215b8" }, - { "R 0x182215cc" }, - { "R 0x182215e0" }, - { "R 0x182215f4" }, - { "R 0x18221608" }, - { "R 0x1822161c" }, - { "R 0x18221630" }, - { "R 0x18221644" }, - { "R 0x182217b8" }, - { "R 0x182217cc" }, - { "R 0x182217e0" }, - { "R 0x182217f4" }, - { "R 0x18221808" }, - { "R 0x1822181c" }, - { "R 0x18221830" }, - { "R 0x18221844" }, - { "R 0x18221858" }, - { "R 0x1822186c" }, - { "R 0x18221880" }, - { "R 0x18221894" }, - { "R 0x182218a8" }, - { "R 0x182218bc" }, - { "R 0x182218d0" }, - { "R 0x182218e4" }, - { "R 0x18221a58" }, - { "R 0x18221a6c" }, - { "R 0x18221a80" }, - { "R 0x18221a94" }, - { "R 0x18221aa8" }, - { "R 0x18221abc" }, - { "R 0x18221ad0" }, - { "R 0x18221ae4" }, - { "R 0x18221af8" }, - { "R 0x18221b0c" }, - { "R 0x18221b20" }, - { "R 0x18221b34" }, - { "R 0x18221b48" }, - { "R 0x18221b5c" }, - { "R 0x18221b70" }, - { "R 0x18221b84" }, - { "R 0x18221cf8" }, - { "R 0x18221d0c" }, - { "R 0x18221d20" }, - { "R 0x18221d34" }, - { "R 0x18221d48" }, - { "R 0x18221d5c" }, - { "R 0x18221d70" }, - { "R 0x18221d84" }, - { "R 0x18221d98" }, - { "R 0x18221dac" }, - { "R 0x18221dc0" }, - { "R 0x18221dd4" }, - { "R 0x18221de8" }, - { "R 0x18221dfc" }, - { "R 0x18221e10" }, - { "R 0x18221e24" }, - { "R 0x18221f98" }, - { "R 0x18221fac" }, - { "R 0x18221fc0" }, - { "R 0x18221fd4" }, - { "R 0x18221fe8" }, - { "R 0x18221ffc" }, - { "R 0x18222010" }, - { "R 0x18222024" }, - { "R 0x18222038" }, - { "R 0x1822204c" }, - { "R 0x18222060" }, - { "R 0x18222074" }, - { "R 0x18222088" }, - { "R 0x1822209c" }, - { "R 0x182220b0" }, - { "R 0x182220c4" }, - { "R 0x18000024" }, - { "R 0x18000040" }, - { "R 0x18010024" }, - { "R 0x18010040" }, - { "R 0x18020024" }, - { "R 0x18020040" }, - { "R 0x18030024" }, - { "R 0x18030040" }, - { "R 0x18040024" }, - { "R 0x18040040" }, - { "R 0x18050024" }, - { "R 0x18050040" }, - { "R 0x18060024" }, - { "R 0x18060040" }, - { "R 0x18070024" }, - { "R 0x18070040" }, - { "R 0x18080024" }, - { "R 0x18080040" }, - { "R 0x180800F8" }, - { "R 0x18080104" }, - { "R 0x1808011C" }, - { "R 0x18080128" }, - { "R 0x90b0280" }, - { "R 0x90b0288" }, - { "R 0x90b028c" }, - { "R 0x90b0290" }, - { "R 0x90b0294" }, - { "R 0x90b0298" }, - { "R 0x90b029c" }, - { "R 0x90b02a0" }, - { "R 0x18321700" }, - { "R 0x18322C18" }, - { "R 0x18323700" }, - { "R 0x18324C18" }, - { "R 0x18325F00" }, - { "R 0x18327418" }, - { "R 0x9236028" }, - { "R 0x923602C" }, - { "R 0x9236030" }, - { "R 0x9236034" }, - { "R 0x9236038" }, - { "R 0x9232100" }, - { "R 0x92360b0" }, - { "R 0x9236044" }, - { "R 0x9236048" }, - { "R 0x923604c" }, - { "R 0x9236050" }, - { "R 0x923e030" }, - { "R 0x923e034" }, - { "R 0x9241000" }, - { "R 0x9248058" }, - { "R 0x924805c" }, - { "R 0x9248060" }, - { "R 0x9248064" }, - { "R 0x9260410" }, - { "R 0x92e0410" }, - { "R 0x9260414" }, - { "R 0x92e0414" }, - { "R 0x9260418" }, - { "R 0x92e0418" }, - { "R 0x9260420" }, - { "R 0x9260424" }, - { "R 0x9260430" }, - { "R 0x9260440" }, - { "R 0x9260448" }, - { "R 0x92604a0" }, - { "R 0x92e0420" }, - { "R 0x92e0424" }, - { "R 0x92e0430" }, - { "R 0x92e0440" }, - { "R 0x92e0448" }, - { "R 0x92e04a0" }, - { "R 0x9600000" }, - { "R 0x9601000" }, - { "R 0x9602000" }, - { "R 0x9603000" }, - { "R 0x9604000" }, - { "R 0x9605000" }, - { "R 0x9606000" }, - { "R 0x9607000" }, - { "R 0x9608000" }, - { "R 0x9609000" }, - { "R 0x960a000" }, - { "R 0x960b000" }, - { "R 0x960c000" }, - { "R 0x960d000" }, - { "R 0x960e000" }, - { "R 0x960f000" }, - { "R 0x9610000" }, - { "R 0x9611000" }, - { "R 0x9612000" }, - { "R 0x9613000" }, - { "R 0x9614000" }, - { "R 0x9615000" }, - { "R 0x9616000" }, - { "R 0x9617000" }, - { "R 0x9618000" }, - { "R 0x9619000" }, - { "R 0x961a000" }, - { "R 0x961b000" }, - { "R 0x961c000" }, - { "R 0x961d000" }, - { "R 0x961e000" }, - { "R 0x961f000" }, - { "R 0x9600004" }, - { "R 0x9601004" }, - { "R 0x9602004" }, - { "R 0x9603004" }, - { "R 0x9604004" }, - { "R 0x9605004" }, - { "R 0x9606004" }, - { "R 0x9607004" }, - { "R 0x9608004" }, - { "R 0x9609004" }, - { "R 0x960a004" }, - { "R 0x960b004" }, - { "R 0x960c004" }, - { "R 0x960d004" }, - { "R 0x960e004" }, - { "R 0x960f004" }, - { "R 0x9610004" }, - { "R 0x9611004" }, - { "R 0x9612004" }, - { "R 0x9613004" }, - { "R 0x9614004" }, - { "R 0x9615004" }, - { "R 0x9616004" }, - { "R 0x9617004" }, - { "R 0x9618004" }, - { "R 0x9619004" }, - { "R 0x961a004" }, - { "R 0x961b004" }, - { "R 0x961c004" }, - { "R 0x961d004" }, - { "R 0x961e004" }, - { "R 0x961f004" }, - { "R 0x9266418" }, - { "R 0x92e6418" }, - { "R 0x9265804" }, - { "R 0x92e5804" }, - { "R 0x92604b8" }, - { "R 0x92e04b8" }, - { "R 0x0C201244 1" }, - { "R 0x0C202244 1" }, - { "R 0x18100C18 1" }, - { "R 0x18101C18 1" }, - { "R 0x18300000 1" }, - { "R 0x183A3A84 2" }, - { "R 0x18393A84 2" }, - { "R 0x00100000" }, - { "R 0x00100004" }, - { "R 0x00100008" }, - { "R 0x0010000C" }, - { "R 0x00100010" }, - { "R 0x00100014" }, - { "R 0x00100018" }, - { "R 0x0010001C" }, - { "R 0x00100020" }, - { "R 0x00100024" }, - { "R 0x00100028" }, - { "R 0x0010002C" }, - { "R 0x00100030" }, - { "R 0x00100034" }, - { "R 0x00100100" }, - { "R 0x00100104" }, - { "R 0x00100108" }, - { "R 0x0010010C" }, - { "R 0x00101000" }, - { "R 0x00101004" }, - { "R 0x00101008" }, - { "R 0x0010100C" }, - { "R 0x00101010" }, - { "R 0x00101014" }, - { "R 0x00101018" }, - { "R 0x0010101C" }, - { "R 0x00101020" }, - { "R 0x00101024" }, - { "R 0x00101028" }, - { "R 0x0010102C" }, - { "R 0x00101030" }, - { "R 0x00101034" }, - { "R 0x00102000" }, - { "R 0x00102004" }, - { "R 0x00102008" }, - { "R 0x0010200C" }, - { "R 0x00102010" }, - { "R 0x00102014" }, - { "R 0x00102018" }, - { "R 0x0010201C" }, - { "R 0x00102020" }, - { "R 0x00102024" }, - { "R 0x00102028" }, - { "R 0x0010202C" }, - { "R 0x00102030" }, - { "R 0x00102034" }, - { "R 0x00103000" }, - { "R 0x00103004" }, - { "R 0x00103008" }, - { "R 0x0010300C" }, - { "R 0x00103010" }, - { "R 0x00103014" }, - { "R 0x00103018" }, - { "R 0x0010301C" }, - { "R 0x00103020" }, - { "R 0x00103024" }, - { "R 0x00103028" }, - { "R 0x0010302C" }, - { "R 0x00103030" }, - { "R 0x00103034" }, - { "R 0x00113000" }, - { "R 0x00113004" }, - { "R 0x00113008" }, - { "R 0x0011300C" }, - { "R 0x00113010" }, - { "R 0x00113014" }, - { "R 0x00113018" }, - { "R 0x0011301C" }, - { "R 0x00113020" }, - { "R 0x00113024" }, - { "R 0x00113028" }, - { "R 0x0011302C" }, - { "R 0x00113030" }, - { "R 0x00113034" }, - { "R 0x0011A000" }, - { "R 0x0011A004" }, - { "R 0x0011A008" }, - { "R 0x0011A00C" }, - { "R 0x0011A010" }, - { "R 0x0011A014" }, - { "R 0x0011A018" }, - { "R 0x0011A01C" }, - { "R 0x0011A020" }, - { "R 0x0011A024" }, - { "R 0x0011A028" }, - { "R 0x0011A02C" }, - { "R 0x0011A030" }, - { "R 0x0011A034" }, - { "R 0x0011B000" }, - { "R 0x0011B004" }, - { "R 0x0011B008" }, - { "R 0x0011B00C" }, - { "R 0x0011B010" }, - { "R 0x0011B014" }, - { "R 0x0011B018" }, - { "R 0x0011B01C" }, - { "R 0x0011B020" }, - { "R 0x0011B024" }, - { "R 0x0011B028" }, - { "R 0x0011B02C" }, - { "R 0x0011B030" }, - { "R 0x0011B034" }, - { "R 0x00174000" }, - { "R 0x00174004" }, - { "R 0x00174008" }, - { "R 0x0017400C" }, - { "R 0x00174010" }, - { "R 0x00174014" }, - { "R 0x00174018" }, - { "R 0x0017401C" }, - { "R 0x00174020" }, - { "R 0x00174024" }, - { "R 0x00174028" }, - { "R 0x0017402C" }, - { "R 0x00174030" }, - { "R 0x00174034" }, - { "R 0x00176000" }, - { "R 0x00176004" }, - { "R 0x00176008" }, - { "R 0x0017600C" }, - { "R 0x00176010" }, - { "R 0x00176014" }, - { "R 0x00176018" }, - { "R 0x0017601C" }, - { "R 0x00176020" }, - { "R 0x00176024" }, - { "R 0x00176028" }, - { "R 0x0017602C" }, - { "R 0x00176030" }, - { "R 0x00176034" }, - { "R 0x0010401C" }, - { "R 0x00183024" }, - { "R 0x00144168" }, - { "R 0x0011702C" }, - { "R 0x0010904C" }, - { "R 0x00189038" }, - { "R 0x001443E8" }, - { "R 0x001442B8" }, - { "R 0x00105060" }, - { "R 0x00141024" }, - { "R 0x00145038" }, - { "R 0x00109004" }, - { "R 0x00189004" }, - { "R 0x00190004" }, - { "R 0x0C2A0000" }, - { "R 0x0C2A0004" }, - { "R 0x0C2A0008" }, - { "R 0x0C2A000C" }, - { "R 0x0C2A0010" }, - { "R 0x0C2A0014" }, - { "R 0x0C2A0018" }, - { "R 0x0C2A001C" }, - { "R 0x0C2A0020" }, - { "R 0x0C2A0024" }, - { "R 0x0C2A0028" }, - { "R 0x0C2A002C" }, - { "R 0x0C2A0030" }, - { "R 0x0C2A0034" }, - { "R 0x0C2A1000" }, - { "R 0x0C2A1004" }, - { "R 0x0C2A1008" }, - { "R 0x0C2A100C" }, - { "R 0x0C2A1010" }, - { "R 0x0C2A1014" }, - { "R 0x0C2A1018" }, - { "R 0x0C2A101C" }, - { "R 0x0C2A1020" }, - { "R 0x0C2A1024" }, - { "R 0x0C2A1028" }, - { "R 0x0C2A102C" }, - { "R 0x0C2A1030" }, - { "R 0x0C2A2260" }, - { "R 0x0C2A2264" }, - { "R 0x0C2A3008" }, - { "R 0x0C2A300C" }, - { "R 0x0C2A3010" }, - { "R 0x0C2A3014" }, - { "R 0x0C2A3024" }, - { "R 0x0C2A2034" }, - { "R 0x0C2A214C" }, - { "R 0x0C2A2150" }, - { "R 0x0C2A2154" }, - { "R 0x0C2630A0 4" }, - { "R 0x0C2630B0 4" }, - { "R 0x0C2630C0 4" }, - { "R 0x0C2630D0 4" }, - { "R 0x1800005C 1" }, - { "R 0x1801005C 1" }, - { "R 0x1802005C 1" }, - { "R 0x1803005C 1" }, - { "R 0x1804005C 1" }, - { "R 0x1805005C 1" }, - { "R 0x1806005C 1" }, - { "R 0x1807005C 1" }, - { "R 0x3d96000" }, - { "R 0x3d96004" }, -}; - -static const struct dcc_link_config talos_link_configs[] = { - { - .link_list = 3, - .entries = talos_dcc_entries, - .num_entries = ARRAY_SIZE(talos_dcc_entries), - }, -}; - -static const struct dcc_config talos_config = { - .lists = talos_link_configs, - .num_lists = ARRAY_SIZE(talos_link_configs), -}; - -static const struct dcc_pdata talos_pdata = { - .base = 0x010a2000, - .size = 0x00001000, - .ram_base = 0x010ae000, - .ram_size = 0x00002000, - .dcc_offset = 0x6000, - .map_ver = 0x1, - .config = &talos_config, -}; - static const struct dcc_pdata kodiak_pdata = { .base = 0x0117f000, .size = 0x00001000, diff --git a/drivers/misc/qcom-dcc-talos-config.h b/drivers/misc/qcom-dcc-talos-config.h new file mode 100644 index 0000000000000..2c2316ae37853 --- /dev/null +++ b/drivers/misc/qcom-dcc-talos-config.h @@ -0,0 +1,792 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _QCOM_DCC_TALOS_CONFIG_H +#define _QCOM_DCC_TALOS_CONFIG_H + +#include "qcom-dcc.h" + +static const struct dcc_register_entry talos_dcc_entries[] = { + { "R 0x9680000" }, + { "R 0x9680004" }, + { "R 0x9681000" }, + { "R 0x9681004" }, + { "R 0x9681008" }, + { "R 0x968100c" }, + { "R 0x9681010" }, + { "R 0x9681014" }, + { "R 0x968101c" }, + { "R 0x9681020" }, + { "R 0x9681024" }, + { "R 0x9681028" }, + { "R 0x968102c" }, + { "R 0x9681030" }, + { "R 0x9681034" }, + { "R 0x968103c" }, + { "R 0x9698100" }, + { "R 0x9698104" }, + { "R 0x9698108" }, + { "R 0x9698110" }, + { "R 0x9698120" }, + { "R 0x9698124" }, + { "R 0x9698128" }, + { "R 0x969812c" }, + { "R 0x9698130" }, + { "R 0x9698134" }, + { "R 0x9698138" }, + { "R 0x969813c" }, + { "R 0x9698500" }, + { "R 0x9698504" }, + { "R 0x9698508" }, + { "R 0x969850c" }, + { "R 0x9698510" }, + { "R 0x9698514" }, + { "R 0x9698518" }, + { "R 0x969851c" }, + { "R 0x9698700" }, + { "R 0x9698704" }, + { "R 0x9698708" }, + { "R 0x969870c" }, + { "R 0x9698714" }, + { "R 0x9698718" }, + { "R 0x969871c" }, + { "R 0x1620204" }, + { "R 0x1620240" }, + { "R 0x1620248" }, + { "R 0x1620288" }, + { "R 0x162028C" }, + { "R 0x1620290" }, + { "R 0x1620294" }, + { "R 0x16202A8" }, + { "R 0x16202AC" }, + { "R 0x16202B0" }, + { "R 0x16202B4" }, + { "R 0x1620300" }, + { "R 0x1700204" }, + { "R 0x1700240" }, + { "R 0x1700248" }, + { "R 0x1700288" }, + { "R 0x1700290" }, + { "R 0x1700300" }, + { "R 0x1700304" }, + { "R 0x1700308" }, + { "R 0x170030C" }, + { "R 0x1700310" }, + { "R 0x1700314" }, + { "R 0x1700C08" }, + { "R 0x1700C10" }, + { "R 0x1700C20" }, + { "R 0x1700C24" }, + { "R 0x1700C28" }, + { "R 0x1700C2C" }, + { "R 0x1700C30" }, + { "R 0x1700C34" }, + { "R 0x1700C38" }, + { "R 0x1700C3C" }, + { "R 0x1740240" }, + { "R 0x1740248" }, + { "R 0x1740288" }, + { "R 0x1740290" }, + { "R 0x1740300" }, + { "R 0x1740304" }, + { "R 0x1740308" }, + { "R 0x174030C" }, + { "R 0x1740310" }, + { "R 0x1740314" }, + { "R 0x1740004" }, + { "R 0x1740008" }, + { "R 0x1740010" }, + { "R 0x1740020" }, + { "R 0x1740024" }, + { "R 0x1740028" }, + { "R 0x174002C" }, + { "R 0x1740030" }, + { "R 0x1740034" }, + { "R 0x1740038" }, + { "R 0x174003C" }, + { "R 0x9698204" }, + { "R 0x9698240" }, + { "R 0x9698244" }, + { "R 0x9698248" }, + { "R 0x969824C" }, + { "R 0x9681010" }, + { "R 0x9681014" }, + { "R 0x9681018" }, + { "R 0x968101C" }, + { "R 0x9681020" }, + { "R 0x9681024" }, + { "R 0x9681028" }, + { "R 0x968102C" }, + { "R 0x9681030" }, + { "R 0x9681034" }, + { "R 0x968103C" }, + { "R 0x9698100" }, + { "R 0x9698104" }, + { "R 0x9698108" }, + { "R 0x9698110" }, + { "R 0x9698120" }, + { "R 0x9698124" }, + { "R 0x9698128" }, + { "R 0x969812C" }, + { "R 0x9698130" }, + { "R 0x9698134" }, + { "R 0x9698138" }, + { "R 0x969813C" }, + { "R 0x62BE2004" }, + { "R 0x62BE2040" }, + { "R 0x62BE2048" }, + { "R 0x62BE2088" }, + { "R 0x62BE2090" }, + { "R 0x62BE2100" }, + { "R 0x62BE2104" }, + { "R 0x62BE2108" }, + { "R 0x62BE210C" }, + { "R 0x62BE2110" }, + { "R 0x62BE2114" }, + { "R 0x62BE2118" }, + { "R 0x62BE0010" }, + { "R 0x62BE0020" }, + { "R 0x62BE0024" }, + { "R 0x62BE0028" }, + { "R 0x62BE002C" }, + { "R 0x62BE0030" }, + { "R 0x62BE0034" }, + { "R 0x62BE0038" }, + { "R 0x62BE003C" }, + { "R 0x9160204" }, + { "R 0x9160240" }, + { "R 0x9160248" }, + { "R 0x9160288" }, + { "R 0x9160290" }, + { "R 0x9160300" }, + { "R 0x9160304" }, + { "R 0x9160308" }, + { "R 0x916030C" }, + { "R 0x9160310" }, + { "R 0x9160314" }, + { "R 0x9160318" }, + { "R 0x9160008" }, + { "R 0x9160010" }, + { "R 0x9160020" }, + { "R 0x9160024" }, + { "R 0x9160028" }, + { "R 0x916002C" }, + { "R 0x9160030" }, + { "R 0x9160034" }, + { "R 0x9160038" }, + { "R 0x916003C" }, + { "R 0x1620500 4" }, + { "R 0x1620700 4" }, + { "R 0x1620300" }, + { "R 0x1620F00 2" }, + { "R 0x1620B00 2" }, + { "R 0x1700B00 2" }, + { "R 0x1700700 3" }, + { "R 0x9163100" }, + { "R 0x96AA100" }, + { "R 0x9050008" }, + { "R 0x9050068" }, + { "R 0x9050078" }, + { "R 0x18200400" }, + { "R 0x18200404" }, + { "R 0x18200408" }, + { "R 0x18200038" }, + { "R 0x18200040" }, + { "R 0x18200048" }, + { "R 0x18220038" }, + { "R 0x18220040" }, + { "R 0x182200D0" }, + { "R 0x18200030" }, + { "R 0x18200010" }, + { "R 0x1822000c" }, + { "R 0x18220d14" }, + { "R 0x18220fb4" }, + { "R 0x18221254" }, + { "R 0x182214f4" }, + { "R 0x18221794" }, + { "R 0x18221a34" }, + { "R 0x18221cd4" }, + { "R 0x18221f74" }, + { "R 0x18220d18" }, + { "R 0x18220fb8" }, + { "R 0x18221258" }, + { "R 0x182214f8" }, + { "R 0x18221798" }, + { "R 0x18221a38" }, + { "R 0x18221cd8" }, + { "R 0x18221f78" }, + { "R 0x18220d00" }, + { "R 0x18220d04" }, + { "R 0x18220d1c" }, + { "R 0x18220fbc" }, + { "R 0x1822125c" }, + { "R 0x182214fc" }, + { "R 0x1822179c" }, + { "R 0x18221a3c" }, + { "R 0x18221cdc" }, + { "R 0x18221f7c" }, + { "R 0x18221274" }, + { "R 0x18221288" }, + { "R 0x1822129c" }, + { "R 0x182212b0" }, + { "R 0x182212c4" }, + { "R 0x182212d8" }, + { "R 0x182212ec" }, + { "R 0x18221300" }, + { "R 0x18221314" }, + { "R 0x18221328" }, + { "R 0x1822133c" }, + { "R 0x18221350" }, + { "R 0x18221364" }, + { "R 0x18221378" }, + { "R 0x1822138c" }, + { "R 0x182213a0" }, + { "R 0x18221514" }, + { "R 0x18221528" }, + { "R 0x1822153c" }, + { "R 0x18221550" }, + { "R 0x18221564" }, + { "R 0x18221578" }, + { "R 0x1822158c" }, + { "R 0x182215a0" }, + { "R 0x182215b4" }, + { "R 0x182215c8" }, + { "R 0x182215dc" }, + { "R 0x182215f0" }, + { "R 0x18221604" }, + { "R 0x18221618" }, + { "R 0x1822162c" }, + { "R 0x18221640" }, + { "R 0x182217b4" }, + { "R 0x182217c8" }, + { "R 0x182217dc" }, + { "R 0x182217f0" }, + { "R 0x18221804" }, + { "R 0x18221818" }, + { "R 0x1822182c" }, + { "R 0x18221840" }, + { "R 0x18221854" }, + { "R 0x18221868" }, + { "R 0x1822187c" }, + { "R 0x18221890" }, + { "R 0x182218a4" }, + { "R 0x182218b8" }, + { "R 0x182218cc" }, + { "R 0x182218e0" }, + { "R 0x18221a54" }, + { "R 0x18221a68" }, + { "R 0x18221a7c" }, + { "R 0x18221a90" }, + { "R 0x18221aa4" }, + { "R 0x18221ab8" }, + { "R 0x18221acc" }, + { "R 0x18221ae0" }, + { "R 0x18221af4" }, + { "R 0x18221b08" }, + { "R 0x18221b1c" }, + { "R 0x18221b30" }, + { "R 0x18221b44" }, + { "R 0x18221b58" }, + { "R 0x18221b6c" }, + { "R 0x18221b80" }, + { "R 0x18221cf4" }, + { "R 0x18221d08" }, + { "R 0x18221d1c" }, + { "R 0x18221d30" }, + { "R 0x18221d44" }, + { "R 0x18221d58" }, + { "R 0x18221d6c" }, + { "R 0x18221d80" }, + { "R 0x18221d94" }, + { "R 0x18221da8" }, + { "R 0x18221dbc" }, + { "R 0x18221dd0" }, + { "R 0x18221de4" }, + { "R 0x18221df8" }, + { "R 0x18221e0c" }, + { "R 0x18221e20" }, + { "R 0x18221f94" }, + { "R 0x18221fa8" }, + { "R 0x18221fbc" }, + { "R 0x18221fd0" }, + { "R 0x18221fe4" }, + { "R 0x18221ff8" }, + { "R 0x1822200c" }, + { "R 0x18222020" }, + { "R 0x18222034" }, + { "R 0x18222048" }, + { "R 0x1822205c" }, + { "R 0x18222070" }, + { "R 0x18222084" }, + { "R 0x18222098" }, + { "R 0x182220ac" }, + { "R 0x182220c0" }, + { "R 0x18221278" }, + { "R 0x1822128c" }, + { "R 0x182212a0" }, + { "R 0x182212b4" }, + { "R 0x182212c8" }, + { "R 0x182212dc" }, + { "R 0x182212f0" }, + { "R 0x18221304" }, + { "R 0x18221318" }, + { "R 0x1822132c" }, + { "R 0x18221340" }, + { "R 0x18221354" }, + { "R 0x18221368" }, + { "R 0x1822137c" }, + { "R 0x18221390" }, + { "R 0x182213a4" }, + { "R 0x18221518" }, + { "R 0x1822152c" }, + { "R 0x18221540" }, + { "R 0x18221554" }, + { "R 0x18221568" }, + { "R 0x1822157c" }, + { "R 0x18221590" }, + { "R 0x182215a4" }, + { "R 0x182215b8" }, + { "R 0x182215cc" }, + { "R 0x182215e0" }, + { "R 0x182215f4" }, + { "R 0x18221608" }, + { "R 0x1822161c" }, + { "R 0x18221630" }, + { "R 0x18221644" }, + { "R 0x182217b8" }, + { "R 0x182217cc" }, + { "R 0x182217e0" }, + { "R 0x182217f4" }, + { "R 0x18221808" }, + { "R 0x1822181c" }, + { "R 0x18221830" }, + { "R 0x18221844" }, + { "R 0x18221858" }, + { "R 0x1822186c" }, + { "R 0x18221880" }, + { "R 0x18221894" }, + { "R 0x182218a8" }, + { "R 0x182218bc" }, + { "R 0x182218d0" }, + { "R 0x182218e4" }, + { "R 0x18221a58" }, + { "R 0x18221a6c" }, + { "R 0x18221a80" }, + { "R 0x18221a94" }, + { "R 0x18221aa8" }, + { "R 0x18221abc" }, + { "R 0x18221ad0" }, + { "R 0x18221ae4" }, + { "R 0x18221af8" }, + { "R 0x18221b0c" }, + { "R 0x18221b20" }, + { "R 0x18221b34" }, + { "R 0x18221b48" }, + { "R 0x18221b5c" }, + { "R 0x18221b70" }, + { "R 0x18221b84" }, + { "R 0x18221cf8" }, + { "R 0x18221d0c" }, + { "R 0x18221d20" }, + { "R 0x18221d34" }, + { "R 0x18221d48" }, + { "R 0x18221d5c" }, + { "R 0x18221d70" }, + { "R 0x18221d84" }, + { "R 0x18221d98" }, + { "R 0x18221dac" }, + { "R 0x18221dc0" }, + { "R 0x18221dd4" }, + { "R 0x18221de8" }, + { "R 0x18221dfc" }, + { "R 0x18221e10" }, + { "R 0x18221e24" }, + { "R 0x18221f98" }, + { "R 0x18221fac" }, + { "R 0x18221fc0" }, + { "R 0x18221fd4" }, + { "R 0x18221fe8" }, + { "R 0x18221ffc" }, + { "R 0x18222010" }, + { "R 0x18222024" }, + { "R 0x18222038" }, + { "R 0x1822204c" }, + { "R 0x18222060" }, + { "R 0x18222074" }, + { "R 0x18222088" }, + { "R 0x1822209c" }, + { "R 0x182220b0" }, + { "R 0x182220c4" }, + { "R 0x18000024" }, + { "R 0x18000040" }, + { "R 0x18010024" }, + { "R 0x18010040" }, + { "R 0x18020024" }, + { "R 0x18020040" }, + { "R 0x18030024" }, + { "R 0x18030040" }, + { "R 0x18040024" }, + { "R 0x18040040" }, + { "R 0x18050024" }, + { "R 0x18050040" }, + { "R 0x18060024" }, + { "R 0x18060040" }, + { "R 0x18070024" }, + { "R 0x18070040" }, + { "R 0x18080024" }, + { "R 0x18080040" }, + { "R 0x180800F8" }, + { "R 0x18080104" }, + { "R 0x1808011C" }, + { "R 0x18080128" }, + { "R 0x90b0280" }, + { "R 0x90b0288" }, + { "R 0x90b028c" }, + { "R 0x90b0290" }, + { "R 0x90b0294" }, + { "R 0x90b0298" }, + { "R 0x90b029c" }, + { "R 0x90b02a0" }, + { "R 0x18321700" }, + { "R 0x18322C18" }, + { "R 0x18323700" }, + { "R 0x18324C18" }, + { "R 0x18325F00" }, + { "R 0x18327418" }, + { "R 0x9236028" }, + { "R 0x923602C" }, + { "R 0x9236030" }, + { "R 0x9236034" }, + { "R 0x9236038" }, + { "R 0x9232100" }, + { "R 0x92360b0" }, + { "R 0x9236044" }, + { "R 0x9236048" }, + { "R 0x923604c" }, + { "R 0x9236050" }, + { "R 0x923e030" }, + { "R 0x923e034" }, + { "R 0x9241000" }, + { "R 0x9248058" }, + { "R 0x924805c" }, + { "R 0x9248060" }, + { "R 0x9248064" }, + { "R 0x9260410" }, + { "R 0x92e0410" }, + { "R 0x9260414" }, + { "R 0x92e0414" }, + { "R 0x9260418" }, + { "R 0x92e0418" }, + { "R 0x9260420" }, + { "R 0x9260424" }, + { "R 0x9260430" }, + { "R 0x9260440" }, + { "R 0x9260448" }, + { "R 0x92604a0" }, + { "R 0x92e0420" }, + { "R 0x92e0424" }, + { "R 0x92e0430" }, + { "R 0x92e0440" }, + { "R 0x92e0448" }, + { "R 0x92e04a0" }, + { "R 0x9600000" }, + { "R 0x9601000" }, + { "R 0x9602000" }, + { "R 0x9603000" }, + { "R 0x9604000" }, + { "R 0x9605000" }, + { "R 0x9606000" }, + { "R 0x9607000" }, + { "R 0x9608000" }, + { "R 0x9609000" }, + { "R 0x960a000" }, + { "R 0x960b000" }, + { "R 0x960c000" }, + { "R 0x960d000" }, + { "R 0x960e000" }, + { "R 0x960f000" }, + { "R 0x9610000" }, + { "R 0x9611000" }, + { "R 0x9612000" }, + { "R 0x9613000" }, + { "R 0x9614000" }, + { "R 0x9615000" }, + { "R 0x9616000" }, + { "R 0x9617000" }, + { "R 0x9618000" }, + { "R 0x9619000" }, + { "R 0x961a000" }, + { "R 0x961b000" }, + { "R 0x961c000" }, + { "R 0x961d000" }, + { "R 0x961e000" }, + { "R 0x961f000" }, + { "R 0x9600004" }, + { "R 0x9601004" }, + { "R 0x9602004" }, + { "R 0x9603004" }, + { "R 0x9604004" }, + { "R 0x9605004" }, + { "R 0x9606004" }, + { "R 0x9607004" }, + { "R 0x9608004" }, + { "R 0x9609004" }, + { "R 0x960a004" }, + { "R 0x960b004" }, + { "R 0x960c004" }, + { "R 0x960d004" }, + { "R 0x960e004" }, + { "R 0x960f004" }, + { "R 0x9610004" }, + { "R 0x9611004" }, + { "R 0x9612004" }, + { "R 0x9613004" }, + { "R 0x9614004" }, + { "R 0x9615004" }, + { "R 0x9616004" }, + { "R 0x9617004" }, + { "R 0x9618004" }, + { "R 0x9619004" }, + { "R 0x961a004" }, + { "R 0x961b004" }, + { "R 0x961c004" }, + { "R 0x961d004" }, + { "R 0x961e004" }, + { "R 0x961f004" }, + { "R 0x9266418" }, + { "R 0x92e6418" }, + { "R 0x9265804" }, + { "R 0x92e5804" }, + { "R 0x92604b8" }, + { "R 0x92e04b8" }, + { "R 0x0C201244 1" }, + { "R 0x0C202244 1" }, + { "R 0x18100C18 1" }, + { "R 0x18101C18 1" }, + { "R 0x18300000 1" }, + { "R 0x183A3A84 2" }, + { "R 0x18393A84 2" }, + { "R 0x00100000" }, + { "R 0x00100004" }, + { "R 0x00100008" }, + { "R 0x0010000C" }, + { "R 0x00100010" }, + { "R 0x00100014" }, + { "R 0x00100018" }, + { "R 0x0010001C" }, + { "R 0x00100020" }, + { "R 0x00100024" }, + { "R 0x00100028" }, + { "R 0x0010002C" }, + { "R 0x00100030" }, + { "R 0x00100034" }, + { "R 0x00100100" }, + { "R 0x00100104" }, + { "R 0x00100108" }, + { "R 0x0010010C" }, + { "R 0x00101000" }, + { "R 0x00101004" }, + { "R 0x00101008" }, + { "R 0x0010100C" }, + { "R 0x00101010" }, + { "R 0x00101014" }, + { "R 0x00101018" }, + { "R 0x0010101C" }, + { "R 0x00101020" }, + { "R 0x00101024" }, + { "R 0x00101028" }, + { "R 0x0010102C" }, + { "R 0x00101030" }, + { "R 0x00101034" }, + { "R 0x00102000" }, + { "R 0x00102004" }, + { "R 0x00102008" }, + { "R 0x0010200C" }, + { "R 0x00102010" }, + { "R 0x00102014" }, + { "R 0x00102018" }, + { "R 0x0010201C" }, + { "R 0x00102020" }, + { "R 0x00102024" }, + { "R 0x00102028" }, + { "R 0x0010202C" }, + { "R 0x00102030" }, + { "R 0x00102034" }, + { "R 0x00103000" }, + { "R 0x00103004" }, + { "R 0x00103008" }, + { "R 0x0010300C" }, + { "R 0x00103010" }, + { "R 0x00103014" }, + { "R 0x00103018" }, + { "R 0x0010301C" }, + { "R 0x00103020" }, + { "R 0x00103024" }, + { "R 0x00103028" }, + { "R 0x0010302C" }, + { "R 0x00103030" }, + { "R 0x00103034" }, + { "R 0x00113000" }, + { "R 0x00113004" }, + { "R 0x00113008" }, + { "R 0x0011300C" }, + { "R 0x00113010" }, + { "R 0x00113014" }, + { "R 0x00113018" }, + { "R 0x0011301C" }, + { "R 0x00113020" }, + { "R 0x00113024" }, + { "R 0x00113028" }, + { "R 0x0011302C" }, + { "R 0x00113030" }, + { "R 0x00113034" }, + { "R 0x0011A000" }, + { "R 0x0011A004" }, + { "R 0x0011A008" }, + { "R 0x0011A00C" }, + { "R 0x0011A010" }, + { "R 0x0011A014" }, + { "R 0x0011A018" }, + { "R 0x0011A01C" }, + { "R 0x0011A020" }, + { "R 0x0011A024" }, + { "R 0x0011A028" }, + { "R 0x0011A02C" }, + { "R 0x0011A030" }, + { "R 0x0011A034" }, + { "R 0x0011B000" }, + { "R 0x0011B004" }, + { "R 0x0011B008" }, + { "R 0x0011B00C" }, + { "R 0x0011B010" }, + { "R 0x0011B014" }, + { "R 0x0011B018" }, + { "R 0x0011B01C" }, + { "R 0x0011B020" }, + { "R 0x0011B024" }, + { "R 0x0011B028" }, + { "R 0x0011B02C" }, + { "R 0x0011B030" }, + { "R 0x0011B034" }, + { "R 0x00174000" }, + { "R 0x00174004" }, + { "R 0x00174008" }, + { "R 0x0017400C" }, + { "R 0x00174010" }, + { "R 0x00174014" }, + { "R 0x00174018" }, + { "R 0x0017401C" }, + { "R 0x00174020" }, + { "R 0x00174024" }, + { "R 0x00174028" }, + { "R 0x0017402C" }, + { "R 0x00174030" }, + { "R 0x00174034" }, + { "R 0x00176000" }, + { "R 0x00176004" }, + { "R 0x00176008" }, + { "R 0x0017600C" }, + { "R 0x00176010" }, + { "R 0x00176014" }, + { "R 0x00176018" }, + { "R 0x0017601C" }, + { "R 0x00176020" }, + { "R 0x00176024" }, + { "R 0x00176028" }, + { "R 0x0017602C" }, + { "R 0x00176030" }, + { "R 0x00176034" }, + { "R 0x0010401C" }, + { "R 0x00183024" }, + { "R 0x00144168" }, + { "R 0x0011702C" }, + { "R 0x0010904C" }, + { "R 0x00189038" }, + { "R 0x001443E8" }, + { "R 0x001442B8" }, + { "R 0x00105060" }, + { "R 0x00141024" }, + { "R 0x00145038" }, + { "R 0x00109004" }, + { "R 0x00189004" }, + { "R 0x00190004" }, + { "R 0x0C2A0000" }, + { "R 0x0C2A0004" }, + { "R 0x0C2A0008" }, + { "R 0x0C2A000C" }, + { "R 0x0C2A0010" }, + { "R 0x0C2A0014" }, + { "R 0x0C2A0018" }, + { "R 0x0C2A001C" }, + { "R 0x0C2A0020" }, + { "R 0x0C2A0024" }, + { "R 0x0C2A0028" }, + { "R 0x0C2A002C" }, + { "R 0x0C2A0030" }, + { "R 0x0C2A0034" }, + { "R 0x0C2A1000" }, + { "R 0x0C2A1004" }, + { "R 0x0C2A1008" }, + { "R 0x0C2A100C" }, + { "R 0x0C2A1010" }, + { "R 0x0C2A1014" }, + { "R 0x0C2A1018" }, + { "R 0x0C2A101C" }, + { "R 0x0C2A1020" }, + { "R 0x0C2A1024" }, + { "R 0x0C2A1028" }, + { "R 0x0C2A102C" }, + { "R 0x0C2A1030" }, + { "R 0x0C2A2260" }, + { "R 0x0C2A2264" }, + { "R 0x0C2A3008" }, + { "R 0x0C2A300C" }, + { "R 0x0C2A3010" }, + { "R 0x0C2A3014" }, + { "R 0x0C2A3024" }, + { "R 0x0C2A2034" }, + { "R 0x0C2A214C" }, + { "R 0x0C2A2150" }, + { "R 0x0C2A2154" }, + { "R 0x0C2630A0 4" }, + { "R 0x0C2630B0 4" }, + { "R 0x0C2630C0 4" }, + { "R 0x0C2630D0 4" }, + { "R 0x1800005C 1" }, + { "R 0x1801005C 1" }, + { "R 0x1802005C 1" }, + { "R 0x1803005C 1" }, + { "R 0x1804005C 1" }, + { "R 0x1805005C 1" }, + { "R 0x1806005C 1" }, + { "R 0x1807005C 1" }, + { "R 0x3d96000" }, + { "R 0x3d96004" }, +}; + +static const struct dcc_link_config talos_link_configs[] = { + { + .link_list = 3, + .entries = talos_dcc_entries, + .num_entries = ARRAY_SIZE(talos_dcc_entries), + }, +}; + +static const struct dcc_config talos_config = { + .lists = talos_link_configs, + .num_lists = ARRAY_SIZE(talos_link_configs), +}; + +static const struct dcc_pdata talos_pdata = { + .base = 0x010a2000, + .size = 0x00001000, + .ram_base = 0x010ae000, + .ram_size = 0x00002000, + .dcc_offset = 0x6000, + .map_ver = 0x1, + .config = &talos_config, +}; + +#endif /* _QCOM_DCC_TALOS_CONFIG_H */ From 75e28e9518622e3eaaca6ebea67b353caea931e7 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 29 Apr 2026 12:18:22 +0800 Subject: [PATCH 0606/1330] QCLINUX: qcom-dcc: group lemans and monaco SoC IDs with comments The lemans_pdata is shared by both Lemans (534, 667, 676) and Monaco (606, 674, 675) SoC variants. Add comments to distinguish the two groups and reorder the case labels accordingly. Signed-off-by: Jie Gan (cherry picked from commit 8e551dc5b09bad842190bc0605dca1d8c1c444fa) --- drivers/misc/qcom-dcc-dev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index 83efad89b4d76..3595200b37d7a 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -82,12 +82,14 @@ static int __init dcc_dev_init(void) goto fail; break; + /* lemans IDs */ case 534: - case 606: case 667: + case 676: + /* monaco IDs */ + case 606: case 674: case 675: - case 676: ret = platform_device_add_data(dcc_pdev, &lemans_pdata, sizeof(lemans_pdata)); if (ret) goto fail; From 9fd9cc3923d39203d979676f779a5a3b1c870315 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 25 Feb 2026 15:42:12 +0530 Subject: [PATCH 0607/1330] arm64: dts: qcom: sm8750: Add camera clock controller The camera clock controller is split into cambistmclk and camcc. The cambist clock controller handles the mclks and the rest of the clocks of camera are part of the camcc clock controller. Add the camcc clock controller device node for SM8750 SoC. Link: https://lore.kernel.org/all/20260225-sm8750_camcc_dt-v3-1-a19d3173a160@oss.qualcomm.com/ Reviewed-by: Abel Vesa Signed-off-by: Taniya Das (cherry picked from commit 10199ae7f8566854d991070d6c0dce91ada6796a) --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 74e0f88a0f9c0..b9f0cf64e104d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2,8 +2,9 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ - #include +#include +#include #include #include #include @@ -2907,6 +2908,23 @@ }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8750-camcc"; + reg = <0x0 0xade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + iris: video-codec@aa00000 { compatible = "qcom,sm8750-iris"; reg = <0x0 0x0aa00000 0x0 0xf0000>; From 5a9583ff2e19d8385733649c5d1c5e3a2245df63 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Mar 2026 18:08:20 +0100 Subject: [PATCH 0608/1330] arm64: dts: qcom: sm8750-mtp: Enable display Enable display on MTP8750 board with Novatek NT37801 panel. Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-2-fb53371e251c@oss.qualcomm.com (cherry picked from commit e9ecb2652be8cd3fe63a4359a6d12de90761b2c8) --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 11d6fdc44e620..f63e0cd54f2ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -941,6 +941,16 @@ status = "okay"; }; +<<<<<<< HEAD +======= +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; +>>>>>>> e9ecb2652be8 (arm64: dts: qcom: sm8750-mtp: Enable display) &mdss_dsi0 { vdda-supply = <&vreg_l3g_1p2>; From 7597296c3c8f7c246827f6e838fa5a03f0a88976 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Mar 2026 18:08:19 +0100 Subject: [PATCH 0609/1330] arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, DisplayPort and Display Clock Controller. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-1-fb53371e251c@oss.qualcomm.com (cherry picked from commit 4c548acaa0b6d9a60be21112d3ac734db34863af) --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index b9f0cf64e104d..f4c0aac959a64 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5,6 +5,7 @@ #include #include #include + #include #include #include From 341ef8d9bcf9068b98af66d18ee074863bf44be1 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 29 Apr 2026 13:56:57 +0800 Subject: [PATCH 0610/1330] QCLINUX: qcom-dcc: add kodiak register list and move config to header Add the full DCC register capture list for the Kodiak platform derived from debug_config_qcm6490.sh. The registers are distributed across three linked lists: - Link list 6: pcu, epss, pimem, core, gemnoc, tsens, spmi, gpu, sysnoc, aggrenoc, gcc (430 entries) - Link list 4: confignoc, limits, gic, mmssnoc, apps_rsc, misc, ddr (450 entries) - Link list 3: lpass_rsc, nsp_rsc, sdi_debug, lpass_cdsp_tunning, wpss_rsc, video_noc (231 entries) Estimated SRAM usage is ~14 KB, well within the 24 KB (0x6000) budget. Move the kodiak DCC configuration (entries arrays, link configs, dcc config, and pdata) into a dedicated header qcom-dcc-kodiak-config.h, consistent with the approach used for talos and lemans. Signed-off-by: Jie Gan (cherry picked from commit 275d5cadb9afc6daf1fe4d9cbf607dadb7f9afc8) --- drivers/misc/qcom-dcc-dev.c | 10 +- drivers/misc/qcom-dcc-kodiak-config.h | 1188 +++++++++++++++++++++++++ 2 files changed, 1189 insertions(+), 9 deletions(-) create mode 100644 drivers/misc/qcom-dcc-kodiak-config.h diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index 3595200b37d7a..cd8bad68a6077 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -9,20 +9,12 @@ #include "qcom-dcc.h" #include "qcom-dcc-talos-config.h" #include "qcom-dcc-lemans-config.h" +#include "qcom-dcc-kodiak-config.h" #define DEV_NAME "qcom-dcc" static struct platform_device *dcc_pdev; -static const struct dcc_pdata kodiak_pdata = { - .base = 0x0117f000, - .size = 0x00001000, - .ram_base = 0x01112000, - .ram_size = 0x00006000, - .dcc_offset = 0x12000, - .map_ver = 0x2, -}; - static const struct dcc_pdata pakala_pdata = { .base = 0x100ff000, .size = 0x00001000, diff --git a/drivers/misc/qcom-dcc-kodiak-config.h b/drivers/misc/qcom-dcc-kodiak-config.h new file mode 100644 index 0000000000000..7184252734917 --- /dev/null +++ b/drivers/misc/qcom-dcc-kodiak-config.h @@ -0,0 +1,1188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _QCOM_DCC_KODIAK_CONFIG_H +#define _QCOM_DCC_KODIAK_CONFIG_H + +#include "qcom-dcc.h" + +static const struct dcc_register_entry kodiak_dcc_entries_ll6[] = { + /* pcu */ + { "R 0x18000010" }, + { "R 0x18000024" }, + { "R 0x18000038 6" }, + { "R 0x18010010" }, + { "R 0x18010024" }, + { "R 0x18010038 6" }, + { "R 0x18020010" }, + { "R 0x18020024" }, + { "R 0x18020038 6" }, + { "R 0x18030010" }, + { "R 0x18030024" }, + { "R 0x18030038 6" }, + { "R 0x18040010" }, + { "R 0x18040024" }, + { "R 0x18040038 6" }, + { "R 0x18050010" }, + { "R 0x18050024" }, + { "R 0x18050038 6" }, + { "R 0x18060010" }, + { "R 0x18060024" }, + { "R 0x18060038 6" }, + { "R 0x18070010" }, + { "R 0x18070024" }, + { "R 0x18070038 6" }, + { "R 0x18080010" }, + { "R 0x18080024" }, + { "R 0x18080038 6" }, + { "R 0x1808006c 5" }, + { "R 0x18080084" }, + { "R 0x180800f4 18" }, + { "R 0x18080158 5" }, + { "R 0x18080170 2" }, + { "R 0x18080188 5" }, + { "R 0x180801ac 6" }, + { "R 0x180801c8" }, + { "R 0x180801f0" }, + /* epss */ + { "R 0x18598020" }, + { "R 0x1859001c 2" }, + { "R 0x1859002c" }, + { "R 0x18590064 6" }, + { "R 0x1859008c" }, + { "R 0x185900dc" }, + { "R 0x185900e8 3" }, + { "R 0x18590300" }, + { "R 0x1859030c" }, + { "R 0x18590320" }, + { "R 0x1859034c" }, + { "R 0x185903bc 2" }, + { "R 0x1859101c 2" }, + { "R 0x1859102c" }, + { "R 0x18591064 6" }, + { "R 0x1859108c" }, + { "R 0x185910dc" }, + { "R 0x185910e8 3" }, + { "R 0x18591300" }, + { "R 0x1859130c" }, + { "R 0x18591320" }, + { "R 0x1859134c" }, + { "R 0x185913bc 2" }, + { "R 0x1859201c 2" }, + { "R 0x1859202c" }, + { "R 0x18592064 6" }, + { "R 0x1859208c" }, + { "R 0x185920dc" }, + { "R 0x185920e8 3" }, + { "R 0x18592300" }, + { "R 0x1859230c" }, + { "R 0x18592320" }, + { "R 0x1859234c" }, + { "R 0x185923bc 2" }, + { "R 0x1859301c 2" }, + { "R 0x18593064 6" }, + { "R 0x1859308c" }, + { "R 0x185930dc" }, + { "R 0x185930e8 3" }, + { "R 0x18593300" }, + { "R 0x1859330c" }, + { "R 0x18593320" }, + { "R 0x1859302c" }, + { "R 0x1859334c" }, + { "R 0x185933bc 2" }, + { "R 0x18300000" }, + { "R 0x1830000c" }, + { "R 0x18300018" }, + { "R 0x17c21000 2" }, + { "R 0x18393a84 2" }, + { "R 0x183a3a84 2" }, + { "R 0x18280000 2" }, + { "R 0x18282000 2" }, + { "R 0x18284000 2" }, + { "R 0x18286000 2" }, + { "R 0x18300000" }, + { "R 0x18200400 3" }, + { "R 0x18200038" }, + { "R 0x18200040" }, + { "R 0x18200048" }, + { "R 0x18220038" }, + { "R 0x18220040" }, + { "R 0x182200d0" }, + { "R 0x18200030" }, + { "R 0x18200010" }, + /* pimem */ + { "R 0x610100 11" }, + /* core */ + { "R 0x18000058 4" }, + { "R 0x1800006c" }, + { "R 0x180000f0 2" }, + { "R 0x18010058 4" }, + { "R 0x1801006c" }, + { "R 0x180100f0 2" }, + { "R 0x18020058 4" }, + { "R 0x1802006c" }, + { "R 0x180200f0 2" }, + { "R 0x18030058 4" }, + { "R 0x1803006c" }, + { "R 0x180300f0 2" }, + { "R 0x18040058 4" }, + { "R 0x1804006c" }, + { "R 0x180400f0 2" }, + { "R 0x18050058 4" }, + { "R 0x1805006c" }, + { "R 0x180500f0 2" }, + { "R 0x18060058 4" }, + { "R 0x1806006c" }, + { "R 0x180600f0 2" }, + { "R 0x18070058 4" }, + { "R 0x1807006c" }, + { "R 0x180700f0 2" }, + { "R 0x18101908" }, + { "R 0x18101c18" }, + { "R 0x18390810" }, + { "R 0x18390c50" }, + { "R 0x18390814" }, + { "R 0x18390c54" }, + { "R 0x18390818" }, + { "R 0x18390c58" }, + { "R 0x18393a84 2" }, + { "R 0x18100908" }, + { "R 0x18100c18" }, + { "R 0x183a0810" }, + { "R 0x183a0c50" }, + { "R 0x183a0814" }, + { "R 0x183a0c54" }, + { "R 0x183a0818" }, + { "R 0x183a0c58" }, + { "R 0x183a3a84 2" }, + { "R 0x18393500" }, + { "R 0x18393580" }, + { "R 0x183a3500" }, + { "R 0x183a3580" }, + { "R 0x18282000 4" }, + { "R 0x18282028" }, + { "R 0x18282038" }, + { "R 0x18282080 5" }, + { "R 0x18286000 4" }, + { "R 0x18286028" }, + { "R 0x18286038" }, + { "R 0x18286080 5" }, + { "R 0xc201244" }, + { "R 0xc202244" }, + { "R 0x18300000" }, + { "R 0x1829208c" }, + { "R 0x18292098" }, + { "R 0x18292098" }, + { "R 0x1829608c" }, + { "R 0x18296098" }, + { "R 0x18296098" }, + { "R 0x784184" }, + /* gemnoc */ + { "R 0x9103008" }, + { "R 0x9103408" }, + { "R 0x9143008" }, + { "R 0x9143408" }, + { "R 0x91b0008" }, + { "R 0x91b1008" }, + { "R 0x9101808 2" }, + { "R 0x9141808 2" }, + { "R 0x91a8008 2" }, + { "R 0x91a8808 2" }, + { "R 0x9100000" }, + { "R 0x9100008 2" }, + { "R 0x9140000" }, + { "R 0x9140008 2" }, + { "R 0x9180000" }, + { "R 0x9180008 2" }, + { "R 0x9180404 3" }, + { "R 0x9181010" }, + { "R 0x9181020 8" }, + { "R 0x91e1048" }, + { "R 0x9121010" }, + { "R 0x9122010" }, + { "R 0x9123010" }, + { "R 0x9125010" }, + { "R 0x9161010" }, + { "R 0x9162010" }, + { "R 0x9163010" }, + { "R 0x9165010" }, + { "R 0x91cf010" }, + { "R 0x91d0010" }, + { "R 0x91d1010" }, + { "R 0x91d2010" }, + { "R 0x91d3010" }, + { "R 0x91d4010" }, + { "R 0x91d5010" }, + { "R 0x91d6010" }, + { "R 0x91d7010" }, + { "R 0x9101408" }, + { "R 0x9141410" }, + { "R 0x9100810" }, + { "R 0x9140810" }, + { "R 0x9100820" }, + { "R 0x9140820" }, + { "R 0x9100828 2" }, + { "R 0x9140828 2" }, + /* tsens */ + { "R 0xc222004" }, + { "R 0xc263014" }, + { "R 0xc2630e0" }, + { "R 0xc2630ec" }, + { "R 0xc2630a0 16" }, + { "R 0xc2630e8" }, + { "R 0xc26313c" }, + { "R 0xc223004" }, + { "R 0xc265014" }, + { "R 0xc2650e0" }, + { "R 0xc2650ec" }, + { "R 0xc2650a0 16" }, + { "R 0xc2650e8" }, + { "R 0xc26513c" }, + /* spmi */ + { "R 0xc410000" }, + { "R 0xc40af04" }, + { "R 0xc40af10" }, + { "R 0xc40a000" }, + { "R 0xc40a018" }, + { "R 0xc40a028 2" }, + { "R 0xc40a100" }, + { "R 0xc2a22fc 3" }, + { "R 0xc440200 2" }, + { "R 0xc442200 4" }, + /* gpu */ + { "R 0x3d9100c 3" }, + { "R 0x3d9106c 3" }, + { "R 0x3d91004" }, + { "R 0x3d91054 5" }, + { "R 0x3d91070 2" }, + { "R 0x3d91080 3" }, + { "R 0x3d91078 2" }, + { "R 0x3d9108c 2" }, + { "R 0x3d91098 2" }, + { "R 0x3d910a4 2" }, + { "R 0x3d910f0 2" }, + { "R 0x3d91100" }, + { "R 0x3d91118" }, + { "R 0x3d91164 2" }, + { "R 0x3d91170" }, + { "R 0x3d91178" }, + { "R 0x3d91204" }, + { "R 0x3d9120c" }, + { "R 0x3d98024" }, + { "R 0x3d9802c 2" }, + { "R 0x3d92000 2" }, + { "R 0x3d93000 2" }, + { "R 0x3d95000 2" }, + { "R 0x3d96000 2" }, + { "R 0x3d97000 2" }, + { "R 0x119000" }, + { "R 0x11903c" }, + { "R 0x171004 3" }, + { "R 0x171014 2" }, + { "R 0x171154 3" }, + { "R 0x17a04c" }, + { "R 0x17b000" }, + { "R 0x17b03c" }, + { "R 0x17c000" }, + { "R 0x17c03c" }, + { "R 0x17d000" }, + { "R 0x17d03c" }, + { "R 0x17e000" }, + { "R 0x17e03c" }, + { "R 0x187000" }, + { "R 0x18703c" }, + { "R 0x3d91534" }, + { "R 0x3d002b4" }, + { "R 0x3d00410 2" }, + { "R 0x3d00818" }, + { "R 0x3d7e220 2" }, + /* sysnoc */ + { "R 0x1680000" }, + { "R 0x1680008" }, + { "R 0x1680010" }, + { "R 0x1680020 8" }, + { "R 0x1680248" }, + { "R 0x1680b00 6" }, + /* aggrenoc */ + { "R 0x16e4008" }, + { "R 0x1706208" }, + { "R 0x16e0000" }, + { "R 0x16e0010" }, + { "R 0x16e0008" }, + { "R 0x16e0020 8" }, + { "R 0x16e5048" }, + { "R 0x16e5248" }, + { "R 0x16e5448" }, + { "R 0x16e5100 5" }, + { "R 0x16e5300 2" }, + { "R 0x16e5500 2" }, + { "R 0x1700000" }, + { "R 0x1700008" }, + { "R 0x1700010" }, + { "R 0x1700020 8" }, + { "R 0x170b100 5" }, + { "R 0x170b048" }, + /* gcc */ + { "R 0x100000 15" }, + { "R 0x101000 15" }, + { "R 0x176000 15" }, + { "R 0x174000 15" }, + { "R 0x113000 15" }, + { "R 0x11a000 15" }, + { "R 0x11c000 15" }, + { "R 0x11c048 3" }, + { "R 0x11e000 15" }, + { "R 0x10401c" }, + { "R 0x105074" }, + { "R 0x183024" }, + { "R 0x109050" }, + { "R 0x123020" }, + { "R 0x117024" }, + { "R 0x117154" }, + { "R 0x117284" }, + { "R 0x1173b4" }, + { "R 0x1174e4" }, + { "R 0x117614" }, + { "R 0x117744" }, + { "R 0x117874" }, + { "R 0x118024" }, + { "R 0x118154" }, + { "R 0x118284" }, + { "R 0x1183b4" }, + { "R 0x1184e4" }, + { "R 0x118614" }, + { "R 0x118744" }, + { "R 0x118874" }, + { "R 0x129020" }, + { "R 0x11d020" }, + { "R 0x134024" }, + { "R 0x141024" }, + { "R 0x14415c" }, + { "R 0x14504c" }, + { "R 0x18903c" }, + { "R 0x151000" }, + { "R 0x151008" }, + { "R 0x151010" }, + { "R 0x152000" }, + { "R 0x152008" }, + { "R 0x152010" }, + { "R 0x153020" }, + { "R 0x153028" }, + { "R 0x153030" }, + { "R 0x155000" }, + { "R 0x155008" }, + { "R 0x155010" }, + { "R 0x15b000" }, + { "R 0x15b008" }, + { "R 0x15b010" }, + { "R 0x157000" }, + { "R 0x157008" }, + { "R 0x157010" }, + { "R 0x135020" }, + { "R 0x135028" }, + { "R 0x135030" }, + { "R 0x156000" }, + { "R 0x156008" }, + { "R 0x156010" }, + { "R 0x15a000" }, + { "R 0x15a008" }, + { "R 0x15a010" }, + { "R 0x190004" }, + { "R 0x109008" }, + { "R 0x190010" }, + { "R 0x190020" }, + { "R 0x190028" }, + { "R 0x109010" }, + { "R 0x109018" }, + { "R 0x109018" }, + { "R 0x109020" }, + { "R 0x18d080" }, + { "R 0x145014" }, + { "R 0x14501c" }, + { "R 0x183004 2" }, + { "R 0x183140" }, + { "R 0x171158 2" }, + { "R 0x109004 3" }, + { "R 0x109160" }, + { "R 0x109468" }, + { "R 0x10f004 3" }, + { "R 0x145000 3" }, + { "R 0x16b004 3" }, + { "R 0x18d004 3" }, + { "R 0x177004 3" }, + { "R 0x189004 3" }, + { "R 0x153000 9" }, + { "R 0x135000 9" }, + { "R 0x106100" }, + { "R 0x147004" }, + { "R 0x17b000 12" }, + { "R 0x17b03c 12" }, + { "R 0x17c000 12" }, + { "R 0x17c03c 12" }, + { "R 0x153124" }, + { "R 0x156124" }, + { "R 0x1453a4" }, + { "R 0x182884" }, + { "R 0x145384" }, + { "R 0xc2a0000 15" }, + { "R 0xc2a1000 15" }, + { "R 0x17101c 2" }, + { "R 0x14401c 2" }, + { "R 0x183010 2" }, + { "R 0x18a160 2" }, + { "R 0x18a004" }, + { "R 0x18a01c 3" }, + { "R 0x19d004 2" }, + { "R 0x196100" }, + { "R 0x10003c" }, + { "R 0x10103c" }, + { "R 0x10203c" }, + { "R 0x10303c" }, + { "R 0x11303c" }, + { "R 0x11a03c" }, + { "R 0x11c03c" }, + { "R 0x17403c" }, + { "R 0x17603c" }, + { "R 0x11e03c" }, + { "R 0xbbf0004 12" }, + { "R 0xbbf0800 12" }, + { "R 0xbbf0004 12" }, + { "R 0xbbf0800 12" }, +}; + +static const struct dcc_register_entry kodiak_dcc_entries_ll4[] = { + /* confignoc */ + { "R 0x1510008" }, + { "R 0x151d208" }, + { "R 0x1507008" }, + { "R 0x151d308" }, + { "R 0x1509008" }, + { "R 0x1514008" }, + { "R 0x1500000" }, + { "R 0x1500010" }, + { "R 0x1510010" }, + { "R 0x1500020 8" }, + { "R 0x1510020 8" }, + { "R 0x1511048" }, + { "R 0x1501048 2" }, + { "R 0x1501058" }, + { "R 0x1501248" }, + { "R 0x1511248" }, + { "R 0x1501248" }, + { "R 0x1511b00" }, + { "R 0x151e100" }, + { "R 0x150b100" }, + /* limits */ + { "R 0xec80004" }, + { "R 0xec80058" }, + { "R 0xec80060 8" }, + { "R 0xec800a0 40" }, + { "R 0x634008" }, + { "R 0x634f00 8" }, + { "R 0x635560" }, + { "R 0x635570" }, + { "R 0x635580" }, + { "R 0x635590" }, + { "R 0x6355a0 4" }, + { "R 0x635600" }, + { "R 0x635610" }, + { "R 0x636008" }, + { "R 0x636f00 8" }, + { "R 0x637560" }, + { "R 0x637570" }, + { "R 0x637580" }, + { "R 0x637590" }, + { "R 0x6375a0 4" }, + { "R 0x637600" }, + { "R 0x637610" }, + { "R 0x18370220 2" }, + { "R 0x183702a0 2" }, + { "R 0x183704a0 12" }, + { "R 0x18370520" }, + { "R 0x18370588" }, + { "R 0x18370d10 12" }, + { "R 0x18370f90 10" }, + { "R 0x18371010 10" }, + { "R 0x18371a10 8" }, + { "R 0x183784a0 12" }, + { "R 0x18378520" }, + { "R 0x18378588" }, + { "R 0x18378d10 8" }, + { "R 0x18378f90 6" }, + { "R 0x18379010 6" }, + { "R 0x18379a10 4" }, + { "R 0xa310220 3" }, + { "R 0xa3102a0 3" }, + { "R 0xa3104a0 6" }, + { "R 0xa310520" }, + { "R 0xa310588" }, + { "R 0xa310d10 8" }, + { "R 0xa310f90 6" }, + { "R 0xa311010 6" }, + { "R 0xa311a10 3" }, + /* gic */ + { "R 0x17a00104 29" }, + { "R 0x17a00204 29" }, + /* mmssnoc */ + { "R 0x1741008" }, + { "R 0x1740000" }, + { "R 0x1740008" }, + { "R 0x1740010" }, + { "R 0x1740020 8" }, + { "R 0x174b048" }, + { "R 0x174b100 8" }, + { "R 0x90e0000" }, + { "R 0x90e0008" }, + { "R 0x90e0010" }, + { "R 0x90e0020 8" }, + { "R 0x90e0248" }, + { "R 0x90e3100" }, + { "R 0x90e4100 7" }, + { "R 0x1750010" }, + { "R 0x1750190" }, + { "R 0x1751010" }, + { "R 0x1752010" }, + { "R 0x1754010" }, + { "R 0x1755010" }, + { "R 0x1756010" }, + { "R 0x1758010" }, + { "R 0x1758090" }, + { "R 0x1759010" }, + { "R 0x175a010" }, + { "R 0x175c010" }, + { "R 0x175d010" }, + { "R 0x175e010" }, + /* apps_rsc */ + { "R 0xb201020 2" }, + { "R 0xb200010 4" }, + { "R 0xb220010 4" }, + { "R 0xb200900 4" }, + { "R 0xb220900 4" }, + { "R 0xb201030" }, + { "R 0xb201204" }, + { "R 0xb201218" }, + { "R 0xb20122c" }, + { "R 0xb201240" }, + { "R 0xb201254" }, + { "R 0xb201208" }, + { "R 0xb20121c" }, + { "R 0xb201230" }, + { "R 0xb201244" }, + { "R 0xb201258" }, + { "R 0xb204510 2" }, + { "R 0xb204520" }, + { "R 0xb211024" }, + { "R 0xb221024" }, + { "R 0xb231024" }, + { "R 0x18220010" }, + { "R 0x18220030" }, + { "R 0x182200d0" }, + { "R 0x18220408" }, + { "R 0x18230408" }, + /* misc */ + { "R 0x17e00434" }, + { "R 0x17e0043c 2" }, + { "R 0x17c00038 2" }, + { "R 0x17c00438" }, + { "R 0x17e0041c 2" }, + { "R 0x17e00404" }, + { "R 0xc220000 2" }, + { "R 0xc230000 6" }, + { "R 0xc260008" }, + { "R 0x18598014" }, + { "R 0x4d8634" }, + { "R 0x4d8834" }, + { "R 0x418620" }, + { "R 0x418820" }, + /* ddr */ + { "R 0x9084208" }, + { "R 0x9084204" }, + { "R 0x9084108" }, + { "R 0x90841c0" }, + { "R 0x10c034 2" }, + { "R 0x144018" }, + { "R 0x9050078" }, + { "R 0x9050110 8" }, + { "R 0x9080058 2" }, + { "R 0x90800c8" }, + { "R 0x90800d4" }, + { "R 0x90800e0" }, + { "R 0x90800fc" }, + { "R 0x9084030" }, + { "R 0x9084038 2" }, + { "R 0x90840e4" }, + { "R 0x90840f4" }, + { "R 0x9084104 2" }, + { "R 0x9084198" }, + { "R 0x9084804" }, + { "R 0x908480c" }, + { "R 0x9084844" }, + { "R 0x9084850 2" }, + { "R 0x9084860 3" }, + { "R 0x9084888 2" }, + { "R 0x908409c 2" }, + { "R 0x908426c" }, + { "R 0x908439c" }, + { "R 0x9085124" }, + { "R 0x9085134 2" }, + { "R 0x9084840" }, + { "R 0x9084834" }, + { "R 0x9085124" }, + { "R 0x90ba280" }, + { "R 0x90ba288 7" }, + { "R 0x9258610 4" }, + { "R 0x92d8610 4" }, + { "R 0x9220344 8" }, + { "R 0x9220370 6" }, + { "R 0x9220480" }, + { "R 0x9222400" }, + { "R 0x922240c" }, + { "R 0x9223214 2" }, + { "R 0x9223220 3" }, + { "R 0x9223308" }, + { "R 0x9223318" }, + { "R 0x9232100" }, + { "R 0x9236040 6" }, + { "R 0x92360b0" }, + { "R 0x923a004 4" }, + { "R 0x923e030 2" }, + { "R 0x9241000" }, + { "R 0x9242028" }, + { "R 0x9242044 3" }, + { "R 0x9242070" }, + { "R 0x9248030" }, + { "R 0x9248048 8" }, + { "R 0x9238030" }, + { "R 0x9238060 2" }, + { "R 0x9238074" }, + { "R 0x9238088" }, + { "R 0x92380a0" }, + { "R 0x92380b0" }, + { "R 0x92a0344 8" }, + { "R 0x92a0370 6" }, + { "R 0x92a0480" }, + { "R 0x92a2400" }, + { "R 0x92a240c" }, + { "R 0x92a3214 2" }, + { "R 0x92a3220 3" }, + { "R 0x92a3308" }, + { "R 0x92a3318" }, + { "R 0x92b2100" }, + { "R 0x92b6040 6" }, + { "R 0x92b60b0" }, + { "R 0x92ba004 4" }, + { "R 0x92be030 2" }, + { "R 0x92c1000" }, + { "R 0x92c2028" }, + { "R 0x92c2044 3" }, + { "R 0x92c2070" }, + { "R 0x92c8030" }, + { "R 0x92c8048 8" }, + { "R 0x92b8030" }, + { "R 0x92b8060 2" }, + { "R 0x92b8074" }, + { "R 0x92b8088" }, + { "R 0x92b80a0" }, + { "R 0x92b80b0" }, + { "R 0x92c8064" }, + { "R 0x9270080" }, + { "R 0x9270310" }, + { "R 0x9270400" }, + { "R 0x9270410 6" }, + { "R 0x9270430" }, + { "R 0x9270440" }, + { "R 0x9270448" }, + { "R 0x92704a0" }, + { "R 0x92704b0" }, + { "R 0x92704b8 2" }, + { "R 0x92704d0 2" }, + { "R 0x9271400" }, + { "R 0x9271408" }, + { "R 0x927341c 2" }, + { "R 0x92753b0" }, + { "R 0x9275804" }, + { "R 0x9275c18 2" }, + { "R 0x9275c2c" }, + { "R 0x9275c38" }, + { "R 0x9276418 2" }, + { "R 0x9279100" }, + { "R 0x9279110" }, + { "R 0x9279120" }, + { "R 0x9279180 2" }, + { "R 0x92f0080" }, + { "R 0x92f0310" }, + { "R 0x92f0400" }, + { "R 0x92f0410 6" }, + { "R 0x92f0430" }, + { "R 0x92f0440" }, + { "R 0x92f0448" }, + { "R 0x92f04a0" }, + { "R 0x92f04b0" }, + { "R 0x92f04b8 2" }, + { "R 0x92f04d0 2" }, + { "R 0x92f1400" }, + { "R 0x92f1408" }, + { "R 0x92f341c 2" }, + { "R 0x92f53b0" }, + { "R 0x92f5804" }, + { "R 0x92f5c18 2" }, + { "R 0x92f5c2c" }, + { "R 0x92f5c38" }, + { "R 0x92f6418 2" }, + { "R 0x92f9100" }, + { "R 0x92f9110" }, + { "R 0x92f9120" }, + { "R 0x92f9180 2" }, + { "R 0x9260080" }, + { "R 0x9260400" }, + { "R 0x9260410 3" }, + { "R 0x9260420 2" }, + { "R 0x9260430" }, + { "R 0x9260440" }, + { "R 0x9260448" }, + { "R 0x92604a0" }, + { "R 0x92604b0" }, + { "R 0x92604b8 2" }, + { "R 0x92604d0 2" }, + { "R 0x9261400" }, + { "R 0x9263410" }, + { "R 0x92653b0" }, + { "R 0x9265804" }, + { "R 0x9265b1c" }, + { "R 0x9265b2c" }, + { "R 0x9265b38" }, + { "R 0x9269100" }, + { "R 0x9269108" }, + { "R 0x9269110" }, + { "R 0x9269118" }, + { "R 0x9269120" }, + { "R 0x9269180 2" }, + { "R 0x92e0080" }, + { "R 0x92e0400" }, + { "R 0x92e0410 3" }, + { "R 0x92e0420 2" }, + { "R 0x92e0430" }, + { "R 0x92e0440" }, + { "R 0x92e0448" }, + { "R 0x92e04a0" }, + { "R 0x92e04b0" }, + { "R 0x92e04b8 2" }, + { "R 0x92e04d0 2" }, + { "R 0x92e1400" }, + { "R 0x92e3410" }, + { "R 0x92e53b0" }, + { "R 0x92e5804" }, + { "R 0x92e5b1c" }, + { "R 0x92e5b2c" }, + { "R 0x92e5b38" }, + { "R 0x92e9100" }, + { "R 0x92e9108" }, + { "R 0x92e9110" }, + { "R 0x92e9118" }, + { "R 0x92e9120" }, + { "R 0x92e9180 2" }, + { "R 0x96b0868" }, + { "R 0x96b0870" }, + { "R 0x96b1004" }, + { "R 0x96b100c" }, + { "R 0x96b1014" }, + { "R 0x96b1204" }, + { "R 0x96b120c" }, + { "R 0x96b1214" }, + { "R 0x96b1504" }, + { "R 0x96b150c" }, + { "R 0x96b1514" }, + { "R 0x96b1604" }, + { "R 0x96b8100" }, + { "R 0x96b813c" }, + { "R 0x96b8500" }, + { "R 0x96b853c" }, + { "R 0x96b8a04" }, + { "R 0x96b8a18" }, + { "R 0x96b8ea8" }, + { "R 0x96b9044" }, + { "R 0x96b904c" }, + { "R 0x96b9054" }, + { "R 0x96b905c" }, + { "R 0x96b910c 2" }, + { "R 0x96b9204" }, + { "R 0x96b920c" }, + { "R 0x96b9238" }, + { "R 0x96b9240" }, + { "R 0x96b926c" }, + { "R 0x96b9394" }, + { "R 0x96b939c" }, + { "R 0x96b9704" }, + { "R 0x96b970c" }, + { "R 0x96f0868" }, + { "R 0x96f0870" }, + { "R 0x96f1004" }, + { "R 0x96f100c" }, + { "R 0x96f1014" }, + { "R 0x96f1204" }, + { "R 0x96f120c" }, + { "R 0x96f1214" }, + { "R 0x96f1504" }, + { "R 0x96f150c" }, + { "R 0x96f1514" }, + { "R 0x96f1604" }, + { "R 0x96f8100" }, + { "R 0x96f813c" }, + { "R 0x96f8500" }, + { "R 0x96f853c" }, + { "R 0x96f8a04" }, + { "R 0x96f8a18" }, + { "R 0x96f8ea8" }, + { "R 0x96f9044" }, + { "R 0x96f904c" }, + { "R 0x96f9054" }, + { "R 0x96f905c" }, + { "R 0x96f910c 2" }, + { "R 0x96f9204" }, + { "R 0x96f920c" }, + { "R 0x96f9238" }, + { "R 0x96f9240" }, + { "R 0x96f926c" }, + { "R 0x96f9394" }, + { "R 0x96f939c" }, + { "R 0x96f9704" }, + { "R 0x96f970c" }, + { "R 0x9130100 3" }, + { "R 0x9170100 3" }, + { "R 0x91dd100 4" }, + { "R 0x91df100" }, + { "R 0x610110 5" }, + { "R 0x9230010" }, + { "R 0x9230020" }, + { "R 0x9230030" }, + { "R 0x9230040" }, + { "R 0x92b0010" }, + { "R 0x92b0020" }, + { "R 0x92b0030" }, + { "R 0x92b0040" }, + { "R 0x9232050" }, + { "R 0x923605c 2" }, + { "R 0x92360a0" }, + { "R 0x923a018 2" }, + { "R 0x92b2050" }, + { "R 0x92b605c 2" }, + { "R 0x92b60a0" }, + { "R 0x92ba018 2" }, + { "R 0x9222404 2" }, + { "R 0x9222410" }, + { "R 0x9238004" }, + { "R 0x9238014" }, + { "R 0x923805c" }, + { "R 0x923a014" }, + { "R 0x92a2404 2" }, + { "R 0x92a2410" }, + { "R 0x92b8004" }, + { "R 0x92b8014" }, + { "R 0x92b805c" }, + { "R 0x92ba014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x6e0a014" }, + { "R 0x9067e00 124" }, + { "R 0x905000c" }, + { "R 0x9050948" }, + { "R 0x9050078" }, + { "R 0x9050008" }, +}; + +static const struct dcc_register_entry kodiak_dcc_entries_ll3[] = { + /* lpass_rsc */ + { "R 0xb254520" }, + { "R 0xb251020 2" }, + { "R 0xb251030" }, + { "R 0xb251200" }, + { "R 0xb251214" }, + { "R 0xb251228" }, + { "R 0xb25123c" }, + { "R 0xb251250" }, + { "R 0xb251204" }, + { "R 0xb251218" }, + { "R 0xb25122c" }, + { "R 0xb251240" }, + { "R 0xb251254" }, + { "R 0xb251208" }, + { "R 0xb25121c" }, + { "R 0xb251230" }, + { "R 0xb251244" }, + { "R 0xb251258" }, + { "R 0xb254510 2" }, + { "R 0xb250010 2" }, + { "R 0xb250900 2" }, + { "R 0x3500010 3" }, + { "R 0x3500030" }, + { "R 0x3500038" }, + { "R 0x3500040" }, + { "R 0x3500048" }, + { "R 0x35000d0" }, + { "R 0x3500210" }, + { "R 0x3500230" }, + { "R 0x3500250" }, + { "R 0x3500270" }, + { "R 0x3500290" }, + { "R 0x35002b0" }, + { "R 0x3500208" }, + { "R 0x3500228" }, + { "R 0x3500248" }, + { "R 0x3500268" }, + { "R 0x3500288" }, + { "R 0x35002a8" }, + { "R 0x350020c" }, + { "R 0x350022c" }, + { "R 0x350024c" }, + { "R 0x350026c" }, + { "R 0x350028c" }, + { "R 0x35002ac" }, + { "R 0x3500400 3" }, + { "R 0x3500d04" }, + { "R 0x30b0010 3" }, + { "R 0x30b0210" }, + { "R 0x30b0230" }, + { "R 0x30b0250" }, + { "R 0x30b0270" }, + { "R 0x30b0290" }, + { "R 0x30b02b0" }, + { "R 0x30b0208" }, + { "R 0x30b0228" }, + { "R 0x30b0248" }, + { "R 0x30b0268" }, + { "R 0x30b0288" }, + { "R 0x30b02a8" }, + { "R 0x30b020c" }, + { "R 0x30b022c" }, + { "R 0x30b024c" }, + { "R 0x30b026c" }, + { "R 0x30b028c" }, + { "R 0x30b02ac" }, + { "R 0x30b0400 3" }, + /* nsp_rsc */ + { "R 0xb2b4520" }, + { "R 0xb2b1020 2" }, + { "R 0xb2b1030" }, + { "R 0xb2b1200" }, + { "R 0xb2b1214" }, + { "R 0xb2b1228" }, + { "R 0xb2b123c" }, + { "R 0xb2b1250" }, + { "R 0xb2b1204" }, + { "R 0xb2b1218" }, + { "R 0xb2b122c" }, + { "R 0xb2b1240" }, + { "R 0xb2b1254" }, + { "R 0xb2b1208" }, + { "R 0xb2b121c" }, + { "R 0xb2b1230" }, + { "R 0xb2b1244" }, + { "R 0xb2b1258" }, + { "R 0xb2b4510 2" }, + { "R 0xb2b0010" }, + { "R 0xb2b0900" }, + { "R 0xa302028" }, + { "R 0xa0a4010 3" }, + { "R 0xa0a4030" }, + { "R 0xa0a4038" }, + { "R 0xa0a4040 2" }, + { "R 0xa0a40d0" }, + { "R 0xa0a4210" }, + { "R 0xa0a4230" }, + { "R 0xa0a4250" }, + { "R 0xa0a4270" }, + { "R 0xa0a4290" }, + { "R 0xa0a42b0" }, + { "R 0xa0a4208" }, + { "R 0xa0a4228" }, + { "R 0xa0a4248" }, + { "R 0xa0a4268" }, + { "R 0xa0a4288" }, + { "R 0xa0a42a8" }, + { "R 0xa0a420c" }, + { "R 0xa0a422c" }, + { "R 0xa0a424c" }, + { "R 0xa0a426c" }, + { "R 0xa0a428c" }, + { "R 0xa0a42ac" }, + { "R 0xa0a4400 2" }, + { "R 0xa0a4d04" }, + { "R 0xa3b0010 3" }, + { "R 0xa3b0210" }, + { "R 0xa3b0230" }, + { "R 0xa3b0250" }, + { "R 0xa3b0270" }, + { "R 0xa3b0290" }, + { "R 0xa3b02b0" }, + { "R 0xa3b0208" }, + { "R 0xa3b0228" }, + { "R 0xa3b0248" }, + { "R 0xa3b0268" }, + { "R 0xa3b0288" }, + { "R 0xa3b02a8" }, + { "R 0xa3b020c" }, + { "R 0xa3b022c" }, + { "R 0xa3b024c" }, + { "R 0xa3b026c" }, + { "R 0xa3b028c" }, + { "R 0xa3b02ac" }, + { "R 0xa3b0400 3" }, + /* sdi_debug */ + { "R 0x10413c" }, + { "R 0x105024" }, + { "R 0x108008" }, + { "R 0x108004" }, + { "R 0x10500c" }, + { "R 0x105658" }, + { "R 0x105640 2" }, + { "R 0x105010" }, + { "R 0x10500c" }, + { "R 0x105024" }, + /* lpass_cdsp_tunning */ + { "R 0x3500d00 3" }, + { "R 0x3500d10 4" }, + { "R 0x3500fb0 4" }, + { "R 0x3501250 4" }, + { "R 0x35014f0 4" }, + { "R 0x3501790 4" }, + { "R 0x3501a30 4" }, + { "R 0x3503d44 4" }, + { "R 0x35000d0 3" }, + { "R 0x3500100" }, + { "R 0x3500d3c" }, + { "R 0xa0a40d0 3" }, + { "R 0xa0a4100" }, + { "R 0xa0a4d3c" }, + { "R 0xa0a7d44 4" }, + { "R 0xa0a4d00 3" }, + /* wpss_rsc */ + { "R 0x8a02028" }, + { "R 0x8b00000 2" }, + { "R 0x8b00010 15" }, + { "R 0x8b000d0" }, + { "R 0x8b000d8" }, + { "R 0x8b00100 3" }, + { "R 0x8b00200 2" }, + { "R 0x8b00224" }, + { "R 0x8b00244" }, + { "R 0x8b00264" }, + { "R 0x8b00284" }, + { "R 0x8b002a4" }, + { "R 0x8b00208" }, + { "R 0x8b00228" }, + { "R 0x8b00248" }, + { "R 0x8b00268" }, + { "R 0x8b00288" }, + { "R 0x8b002a8" }, + { "R 0x8b0020c" }, + { "R 0x8b0022c" }, + { "R 0x8b0024c" }, + { "R 0x8b0026c" }, + { "R 0x8b0028c" }, + { "R 0x8b002ac" }, + { "R 0x8b00210" }, + { "R 0x8b00230" }, + { "R 0x8b00250" }, + { "R 0x8b00270" }, + { "R 0x8b00290" }, + { "R 0x8b002b0" }, + { "R 0x8b00400 3" }, + { "R 0x8b00460 2" }, + { "R 0x8b004a0 7" }, + { "R 0x8ab0000 2" }, + { "R 0x8ab0010 3" }, + { "R 0x8ab00d0" }, + { "R 0x8ab00d8" }, + { "R 0x8ab0100 3" }, + { "R 0x8ab0200 2" }, + { "R 0x8ab0224" }, + { "R 0x8ab0244" }, + { "R 0x8ab0264" }, + { "R 0x8ab0284" }, + { "R 0x8ab02a4" }, + { "R 0x8ab0208" }, + { "R 0x8ab0228" }, + { "R 0x8ab0248" }, + { "R 0x8ab0268" }, + { "R 0x8ab0288" }, + { "R 0x8ab02a8" }, + { "R 0x8ab020c" }, + { "R 0x8ab022c" }, + { "R 0x8ab024c" }, + { "R 0x8ab026c" }, + { "R 0x8ab028c" }, + { "R 0x8ab02ac" }, + { "R 0x8ab0210" }, + { "R 0x8ab0230" }, + { "R 0x8ab0250" }, + { "R 0x8ab0270" }, + { "R 0x8ab0290" }, + { "R 0x8ab02b0" }, + { "R 0x8ab0400 3" }, + { "R 0x8ab0460 2" }, + { "R 0x8ab04a0 7" }, + /* video_noc */ + { "R 0xaa10504 2" }, + { "R 0xaa10510" }, + { "R 0xaa10520 8" }, + { "R 0xaa10300" }, + { "R 0xaa10010" }, + { "R 0xaa10020" }, +}; + +static const struct dcc_link_config kodiak_link_configs[] = { + { + .link_list = 6, + .entries = kodiak_dcc_entries_ll6, + .num_entries = ARRAY_SIZE(kodiak_dcc_entries_ll6), + }, + { + .link_list = 4, + .entries = kodiak_dcc_entries_ll4, + .num_entries = ARRAY_SIZE(kodiak_dcc_entries_ll4), + }, + { + .link_list = 3, + .entries = kodiak_dcc_entries_ll3, + .num_entries = ARRAY_SIZE(kodiak_dcc_entries_ll3), + }, +}; + +static const struct dcc_config kodiak_config = { + .lists = kodiak_link_configs, + .num_lists = ARRAY_SIZE(kodiak_link_configs), +}; + +static const struct dcc_pdata kodiak_pdata = { + .base = 0x0117f000, + .size = 0x00001000, + .ram_base = 0x01112000, + .ram_size = 0x00006000, + .dcc_offset = 0x12000, + .map_ver = 0x2, + .config = &kodiak_config, +}; + +#endif /* _QCOM_DCC_KODIAK_CONFIG_H */ From fd0d04bb6d7f697dc94ff9d7501c3cc95c7df426 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 29 Apr 2026 14:12:34 +0800 Subject: [PATCH 0611/1330] QCLINUX: qcom-dcc: add pakala register list and move config to header Add the DCC register capture list for the Pakala platform. The registers are distributed across two linked lists: - Link list 6: 910 entries - Link list 4: 212 entries Estimated SRAM usage is ~15 KB, within the 16 KB (0x4000) budget. Move the pakala DCC configuration (entries arrays, link configs, dcc config, and pdata) into a dedicated header qcom-dcc-pakala-config.h, consistent with the approach used for other platforms. Signed-off-by: Jie Gan (cherry picked from commit 53e8e4b953a1812f7460d3d0bbec56eb62d091e3) --- drivers/misc/qcom-dcc-dev.c | 10 +- drivers/misc/qcom-dcc-pakala-config.h | 1167 +++++++++++++++++++++++++ 2 files changed, 1168 insertions(+), 9 deletions(-) create mode 100644 drivers/misc/qcom-dcc-pakala-config.h diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index cd8bad68a6077..a77b5bc144982 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -10,20 +10,12 @@ #include "qcom-dcc-talos-config.h" #include "qcom-dcc-lemans-config.h" #include "qcom-dcc-kodiak-config.h" +#include "qcom-dcc-pakala-config.h" #define DEV_NAME "qcom-dcc" static struct platform_device *dcc_pdev; -static const struct dcc_pdata pakala_pdata = { - .base = 0x100ff000, - .size = 0x00001000, - .ram_base = 0x10084000, - .ram_size = 0x4000, - .dcc_offset = 0x4000, - .map_ver = 0x3, -}; - static const struct dcc_pdata kaanapali_pdata = { .base = 0x100ff000, .size = 0x1000, diff --git a/drivers/misc/qcom-dcc-pakala-config.h b/drivers/misc/qcom-dcc-pakala-config.h new file mode 100644 index 0000000000000..25e6221805d27 --- /dev/null +++ b/drivers/misc/qcom-dcc-pakala-config.h @@ -0,0 +1,1167 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _QCOM_DCC_PAKALA_CONFIG_H +#define _QCOM_DCC_PAKALA_CONFIG_H + +#include "qcom-dcc.h" + +static const struct dcc_register_entry pakala_dcc_entries_ll6[] = { + { "R 0x16801000 2" }, + { "R 0x18880258 10" }, + { "R 0x18880288 6" }, + { "R 0x188802a8 10" }, + { "R 0x18880328 6" }, + { "R 0x188803d8 10" }, + { "R 0x18880408 2" }, + { "R 0x19880258 10" }, + { "R 0x19880288 6" }, + { "R 0x198802a8 10" }, + { "R 0x19880328 6" }, + { "R 0x198803d8 10" }, + { "R 0x19880408 2" }, + { "R 0x188b0000 4" }, + { "R 0x188b0050 2" }, + { "R 0x188b00e8 36" }, + { "R 0x188b0788 2" }, + { "R 0x188b0c18 2" }, + { "R 0x198b0000 4" }, + { "R 0x198b0050 2" }, + { "R 0x198b00e8 36" }, + { "R 0x198b0788 2" }, + { "R 0x198b0c18 2" }, + { "R 0x17988814 2" }, + { "R 0x17998814 2" }, + { "R 0x179d2000 3" }, + { "R 0x179d2020 3" }, + { "R 0x179d2040 2" }, + { "R 0x179d2060 2" }, + { "R 0x179d2080 2" }, + { "R 0x179d20a0" }, + { "R 0x179d20b0" }, + { "R 0x179d20c0" }, + { "R 0x179d2200 2" }, + { "R 0x179d2220 2" }, + { "R 0x179d2280 2" }, + { "R 0x179d22f0" }, + { "R 0x179d2304" }, + { "R 0x179d2310" }, + { "R 0x179d2400 4" }, + { "R 0x179d2420" }, + { "R 0x179d2428 2" }, + { "R 0x179d2440 2" }, + { "R 0x179d2520 2" }, + { "R 0x179d2600 2" }, + { "R 0x179d2710 2" }, + { "R 0x179d2720 2" }, + { "R 0x179d2740 2" }, + { "R 0x179d3080 2" }, + { "R 0x17846018 2" }, + { "R 0x17846060" }, + { "R 0x17846100 2" }, + { "R 0x17846110" }, + { "R 0x17847030 2" }, + { "R 0x17847040 2" }, + { "R 0x17847050 2" }, + { "R 0x17847060 2" }, + { "R 0x17847070 2" }, + { "R 0x17847080 2" }, + { "R 0x17847090 2" }, + { "R 0x178470a0 2" }, + { "R 0x178470b0 2" }, + { "R 0x178470c0 2" }, + { "R 0x17850000 2" }, + { "R 0x17850010 2" }, + { "R 0x17850030 2" }, + { "R 0x17850040" }, + { "R 0x17854000" }, + { "R 0x17854008 4" }, + { "R 0x179c8814 2" }, + { "R 0x179d0104" }, + { "R 0x179d0118 2" }, + { "R 0x179d0148 2" }, + { "R 0x179d1600" }, + { "R 0x179d1678" }, + { "R 0x179d1688 2" }, + { "R 0x179d1694 3" }, + { "R 0x179d1820 3" }, + { "R 0x17b70000" }, + { "R 0x17b70008 2" }, + { "R 0x17b71000" }, + { "R 0x17b71008 2" }, + { "R 0x164807f8" }, + { "R 0x16480810 3" }, + { "R 0x16483000 40" }, + { "R 0x16483a00 2" }, + { "R 0x16488908" }, + { "R 0x16488c18" }, + { "R 0x164a8908" }, + { "R 0x164a8c18" }, + { "R 0x164a07f8" }, + { "R 0x164a0810 3" }, + { "R 0x164a3000 40" }, + { "R 0x164a3a00 2" }, + { "R 0x16493000 40" }, + { "R 0x16493a00 2" }, + { "R 0x16498c18" }, + { "R 0x164b8c18" }, + { "R 0x164b3a00 2" }, + { "R 0x16440000 2" }, + { "R 0x16440020 3" }, + { "R 0x16440030" }, + { "R 0x1644003c" }, + { "R 0x16440044 3" }, + { "R 0x16440438" }, + { "R 0x16440500 5" }, + { "R 0x16562000 2" }, + { "R 0x16565004" }, + { "R 0x17000bd0" }, + { "R 0x170404a0" }, + { "R 0x170a0590" }, + { "R 0x170c0330" }, + { "R 0x170c0338" }, + { "R 0x170c0340" }, + { "R 0x170c0518" }, + { "R 0x170c0528" }, + { "R 0x170c0538" }, + { "R 0x170c0560 4" }, + { "R 0x17200bd0" }, + { "R 0x172404a0" }, + { "R 0x172a0590" }, + { "R 0x172c0330" }, + { "R 0x172c0338" }, + { "R 0x172c0340" }, + { "R 0x172c0518" }, + { "R 0x172c0528" }, + { "R 0x172c0538" }, + { "R 0x172c0560 4" }, + { "R 0x1641000c" }, + { "R 0x1641400c" }, + { "R 0x18830320 2" }, + { "R 0x19830320 2" }, + { "R 0x18040010 6" }, + { "R 0x18040040 10" }, + { "R 0x18040090 6" }, + { "R 0x18850020 2" }, + { "R 0x18850060 2" }, + { "R 0x188500a0 2" }, + { "R 0x188500e0 2" }, + { "R 0x18850120 2" }, + { "R 0x18850160 2" }, + { "R 0x189c1000" }, + { "R 0x199c1000" }, + { "R 0x18a30000 9" }, + { "R 0x18a30030" }, + { "R 0x18a3003c 2" }, + { "R 0x19a30000 9" }, + { "R 0x19a30030" }, + { "R 0x19a3003c 2" }, + { "R 0x24201040" }, + { "R 0x24201048" }, + { "R 0x24100010" }, + { "R 0x24100020 6" }, + { "R 0x24180010" }, + { "R 0x24180020 6" }, + { "R 0x24200010" }, + { "R 0x24200020 6" }, + { "R 0x24200410" }, + { "R 0x24200420 6" }, + { "R 0x24102010" }, + { "R 0x24102038" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 3" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 3" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 3" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102008 2" }, + { "R 0x24181010" }, + { "R 0x24181038" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 3" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 3" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 3" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181008 2" }, + { "R 0x24203010" }, + { "R 0x24203038" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203030 3" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203030 3" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203030 3" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203030 2" }, + { "R 0x24203008 2" }, + { "R 0x24203410" }, + { "R 0x24203438" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203430 3" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203430 3" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203430 3" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203430 2" }, + { "R 0x24203408 2" }, + { "R 0x24104018" }, + { "R 0x24104008" }, + { "R 0x24104010 2" }, + { "R 0x24104010 2" }, + { "R 0x24104010 2" }, + { "R 0x24104010 2" }, + { "R 0x24104098" }, + { "R 0x24104088" }, + { "R 0x24104090 2" }, + { "R 0x24104090 2" }, + { "R 0x24104090 2" }, + { "R 0x24104090 2" }, + { "R 0x24104090 2" }, + { "R 0x24182018" }, + { "R 0x24182008" }, + { "R 0x24182010 2" }, + { "R 0x24182010 2" }, + { "R 0x24182010 2" }, + { "R 0x24182010 2" }, + { "R 0x24182098" }, + { "R 0x24182088" }, + { "R 0x24182090 2" }, + { "R 0x24182090 2" }, + { "R 0x24182090 2" }, + { "R 0x24182090 2" }, + { "R 0x24182090 2" }, + { "R 0x24204018" }, + { "R 0x24204008" }, + { "R 0x24204010 2" }, + { "R 0x24204010 2" }, + { "R 0x24204010 2" }, + { "R 0x24204098" }, + { "R 0x24204088" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24204090 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24102030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x24181030 2" }, + { "R 0x16801000 2" }, + { "R 0x240ba050" }, + { "R 0x240ba164" }, + { "R 0x240ba280" }, + { "R 0x240ba288 8" }, + { "R 0x240ba2c0 2" }, + { "R 0x24bc0610 11" }, + { "R 0x24bc0640 2" }, + { "R 0x24bc06a0" }, + { "R 0x24fc0610 11" }, + { "R 0x24fc0640 2" }, + { "R 0x24fc06a0" }, + { "R 0x25bc0610 11" }, + { "R 0x25bc0640 2" }, + { "R 0x25bc06a0" }, + { "R 0x25fc0610 11" }, + { "R 0x25fc0640 2" }, + { "R 0x25fc06a0" }, + { "R 0x240a801c 2" }, + { "R 0x240a8038 3" }, + { "R 0x240a8058 5" }, + { "R 0x240a8074 4" }, + { "R 0x240a80a8" }, + { "R 0x240a80b8" }, + { "R 0x240a80ec 5" }, + { "R 0x240a8140" }, + { "R 0x240a8164 2" }, + { "R 0x240a81c4 2" }, + { "R 0x240a81dc 2" }, + { "R 0x240a844c" }, + { "R 0x240a845c" }, + { "R 0x240a84c8 27" }, + { "R 0x240a9000 2" }, + { "R 0x240a9010 2" }, + { "R 0x240a9020 3" }, + { "R 0x240a9034 2" }, + { "R 0x240a9130 3" }, + { "R 0x240a9140 18" }, + { "R 0x240a91ac 6" }, + { "R 0x240a91c8" }, + { "R 0x240a920c" }, + { "R 0x240a9220 2" }, + { "R 0x240a9264" }, + { "R 0x240a9294 7" }, + { "R 0x240a92b8" }, + { "R 0x240a92f8" }, + { "R 0x24800004" }, + { "R 0x24801004" }, + { "R 0x24802004" }, + { "R 0x24803004" }, + { "R 0x24804004" }, + { "R 0x24805004" }, + { "R 0x24806004" }, + { "R 0x24807004" }, + { "R 0x24808004" }, + { "R 0x24809004" }, + { "R 0x2480a004" }, + { "R 0x2480b004" }, + { "R 0x2480c004" }, + { "R 0x2480d004" }, + { "R 0x2480e004" }, + { "R 0x2480f004" }, + { "R 0x24810004" }, + { "R 0x24811004" }, + { "R 0x24812004" }, + { "R 0x24813004" }, + { "R 0x24814004" }, + { "R 0x24815004" }, + { "R 0x24816004" }, + { "R 0x24817004" }, + { "R 0x24818004" }, + { "R 0x24819004" }, + { "R 0x2481a004" }, + { "R 0x2481b004" }, + { "R 0x2481c004" }, + { "R 0x2481d004" }, + { "R 0x2481e004" }, + { "R 0x2481f004" }, + { "R 0x24820004" }, + { "R 0x24821004" }, + { "R 0x24822004" }, + { "R 0x24823004" }, + { "R 0x24843350 2" }, + { "R 0x248433f4 11" }, + { "R 0x248434c0 6" }, + { "R 0x24843600" }, + { "R 0x2484360c" }, + { "R 0x24845040" }, + { "R 0x24845048" }, + { "R 0x24845050" }, + { "R 0x24845058" }, + { "R 0x24845060" }, + { "R 0x24845068" }, + { "R 0x24845070 4" }, + { "R 0x24845090 14" }, + { "R 0x248450cc 2" }, + { "R 0x24845240" }, + { "R 0x248452a0" }, + { "R 0x24845300" }, + { "R 0x24845310" }, + { "R 0x24845320" }, + { "R 0x24845330 3" }, + { "R 0x24847404" }, + { "R 0x2484740c 3" }, + { "R 0x24847448" }, + { "R 0x24847450" }, + { "R 0x24847458 2" }, + { "R 0x24847600" }, + { "R 0x24849000" }, + { "R 0x24849010" }, + { "R 0x2487c000" }, + { "R 0x2487c01c 3" }, + { "R 0x2487c030 8" }, + { "R 0x2487c054 2" }, + { "R 0x2487c078" }, + { "R 0x2487c108 9" }, + { "R 0x2487c20c 3" }, + { "R 0x248a600c 4" }, + { "R 0x248a6020 3" }, + { "R 0x248a6034 2" }, + { "R 0x248a6040" }, + { "R 0x248a6050" }, + { "R 0x248a6058" }, + { "R 0x248a6060 4" }, + { "R 0x248a7020" }, + { "R 0x248a7030 2" }, + { "R 0x248a7078 4" }, + { "R 0x248a708c 6" }, + { "R 0x248e002c" }, + { "R 0x248e009c 2" }, + { "R 0x248e00a8 3" }, + { "R 0x248e00b8" }, + { "R 0x248e00c0 7" }, + { "R 0x248e00e0" }, + { "R 0x248e00e8" }, + { "R 0x248e00f0" }, + { "R 0x248e00f8" }, + { "R 0x248e0100" }, + { "R 0x248e0108" }, + { "R 0x248e0110" }, + { "R 0x248e0118" }, + { "R 0x248e0120" }, + { "R 0x248e0128" }, + { "R 0x248e0150 4" }, + { "R 0x248e0164" }, + { "R 0x248e01e8" }, + { "R 0x248e1010" }, + { "R 0x248e1060 3" }, + { "R 0x248e1070" }, + { "R 0x248e1084 3" }, + { "R 0x248e3004" }, + { "R 0x248e300c" }, + { "R 0x248e4004" }, + { "R 0x248e4010 2" }, + { "R 0x248e4024 2" }, + { "R 0x248e4038 2" }, + { "R 0x248e600c 5" }, + { "R 0x248e700c 5" }, + { "R 0x248e9004" }, + { "R 0x248e9010 3" }, + { "R 0x248e9020 3" }, + { "R 0x248e9030 3" }, + { "R 0x248e9040 3" }, + { "R 0x248e9050 3" }, + { "R 0x248ea004" }, + { "R 0x248ea010 3" }, + { "R 0x248ea020 3" }, + { "R 0x248ea030 3" }, + { "R 0x248ea040 3" }, + { "R 0x248ea050 3" }, + { "R 0x248f001c" }, + { "R 0x248f0050" }, + { "R 0x248f0058" }, + { "R 0x24c00004" }, + { "R 0x24c01004" }, + { "R 0x24c02004" }, + { "R 0x24c03004" }, + { "R 0x24c04004" }, + { "R 0x24c05004" }, + { "R 0x24c06004" }, + { "R 0x24c07004" }, + { "R 0x24c08004" }, + { "R 0x24c09004" }, + { "R 0x24c0a004" }, + { "R 0x24c0b004" }, + { "R 0x24c0c004" }, + { "R 0x24c0d004" }, + { "R 0x24c0e004" }, + { "R 0x24c0f004" }, + { "R 0x24c10004" }, + { "R 0x24c11004" }, + { "R 0x24c12004" }, + { "R 0x24c13004" }, + { "R 0x24c14004" }, + { "R 0x24c15004" }, + { "R 0x24c16004" }, + { "R 0x24c17004" }, + { "R 0x24c18004" }, + { "R 0x24c19004" }, + { "R 0x24c1a004" }, + { "R 0x24c1b004" }, + { "R 0x24c1c004" }, + { "R 0x24c1d004" }, + { "R 0x24c1e004" }, + { "R 0x24c1f004" }, + { "R 0x24c20004" }, + { "R 0x24c21004" }, + { "R 0x24c22004" }, + { "R 0x24c23004" }, + { "R 0x24c43350 2" }, + { "R 0x24c433f4 11" }, + { "R 0x24c434c0 6" }, + { "R 0x24c43600" }, + { "R 0x24c4360c" }, + { "R 0x24c45040" }, + { "R 0x24c45048" }, + { "R 0x24c45050" }, + { "R 0x24c45058" }, + { "R 0x24c45060" }, + { "R 0x24c45068" }, + { "R 0x24c45070 4" }, + { "R 0x24c45090 14" }, + { "R 0x24c450cc 2" }, + { "R 0x24c45240" }, + { "R 0x24c452a0" }, + { "R 0x24c45300" }, + { "R 0x24c45310" }, + { "R 0x24c45320" }, + { "R 0x24c45330 3" }, + { "R 0x24c47404" }, + { "R 0x24c4740c 3" }, + { "R 0x24c47448" }, + { "R 0x24c47450" }, + { "R 0x24c47458 2" }, + { "R 0x24c47600" }, + { "R 0x24c49000" }, + { "R 0x24c49010" }, + { "R 0x24c7c000" }, + { "R 0x24c7c01c 3" }, + { "R 0x24c7c030 8" }, + { "R 0x24c7c054 2" }, + { "R 0x24c7c078" }, + { "R 0x24c7c108 9" }, + { "R 0x24c7c20c 3" }, + { "R 0x24ca600c 4" }, + { "R 0x24ca6020 3" }, + { "R 0x24ca6034 2" }, + { "R 0x24ca6040" }, + { "R 0x24ca6050" }, + { "R 0x24ca6058" }, + { "R 0x24ca6060 4" }, + { "R 0x24ca7020" }, + { "R 0x24ca7030 2" }, + { "R 0x24ca7078 4" }, + { "R 0x24ca708c 6" }, + { "R 0x24ce002c" }, + { "R 0x24ce009c 2" }, + { "R 0x24ce00a8 3" }, + { "R 0x24ce00b8" }, + { "R 0x24ce00c0 7" }, + { "R 0x24ce00e0" }, + { "R 0x24ce00e8" }, + { "R 0x24ce00f0" }, + { "R 0x24ce00f8" }, + { "R 0x24ce0100" }, + { "R 0x24ce0108" }, + { "R 0x24ce0110" }, + { "R 0x24ce0118" }, + { "R 0x24ce0120" }, + { "R 0x24ce0128" }, + { "R 0x24ce0150 4" }, + { "R 0x24ce0164" }, + { "R 0x24ce01e8" }, + { "R 0x24ce1010" }, + { "R 0x24ce1060 3" }, + { "R 0x24ce1070" }, + { "R 0x24ce1084 3" }, + { "R 0x24ce3004" }, + { "R 0x24ce300c" }, + { "R 0x24ce4004" }, + { "R 0x24ce4010 2" }, + { "R 0x24ce4024 2" }, + { "R 0x24ce4038 2" }, + { "R 0x24ce600c 5" }, + { "R 0x24ce700c 5" }, + { "R 0x24ce9004" }, + { "R 0x24ce9010 3" }, + { "R 0x24ce9020 3" }, + { "R 0x24ce9030 3" }, + { "R 0x24ce9040 3" }, + { "R 0x24ce9050 3" }, + { "R 0x24cea004" }, + { "R 0x24cea010 3" }, + { "R 0x24cea020 3" }, + { "R 0x24cea030 3" }, + { "R 0x24cea040 3" }, + { "R 0x24cea050 3" }, + { "R 0x24cf001c" }, + { "R 0x24cf0050" }, + { "R 0x24cf0058" }, + { "R 0x25800004" }, + { "R 0x25801004" }, + { "R 0x25802004" }, + { "R 0x25803004" }, + { "R 0x25804004" }, + { "R 0x25805004" }, + { "R 0x25806004" }, + { "R 0x25807004" }, + { "R 0x25808004" }, + { "R 0x25809004" }, + { "R 0x2580a004" }, + { "R 0x2580b004" }, + { "R 0x2580c004" }, + { "R 0x2580d004" }, + { "R 0x2580e004" }, + { "R 0x2580f004" }, + { "R 0x25810004" }, + { "R 0x25811004" }, + { "R 0x25812004" }, + { "R 0x25813004" }, + { "R 0x25814004" }, + { "R 0x25815004" }, + { "R 0x25816004" }, + { "R 0x25817004" }, + { "R 0x25818004" }, + { "R 0x25819004" }, + { "R 0x2581a004" }, + { "R 0x2581b004" }, + { "R 0x2581c004" }, + { "R 0x2581d004" }, + { "R 0x2581e004" }, + { "R 0x2581f004" }, + { "R 0x25820004" }, + { "R 0x25821004" }, + { "R 0x25822004" }, + { "R 0x25823004" }, + { "R 0x25843350 2" }, + { "R 0x258433f4 11" }, + { "R 0x258434c0 6" }, + { "R 0x25843600" }, + { "R 0x2584360c" }, + { "R 0x25845040" }, + { "R 0x25845048" }, + { "R 0x25845050" }, + { "R 0x25845058" }, + { "R 0x25845060" }, + { "R 0x25845068" }, + { "R 0x25845070 4" }, + { "R 0x25845090 14" }, + { "R 0x258450cc 2" }, + { "R 0x25845240" }, + { "R 0x258452a0" }, + { "R 0x25845300" }, + { "R 0x25845310" }, + { "R 0x25845320" }, + { "R 0x25845330 3" }, + { "R 0x25847404" }, + { "R 0x2584740c 3" }, + { "R 0x25847448" }, + { "R 0x25847450" }, + { "R 0x25847458 2" }, + { "R 0x25847600" }, + { "R 0x25849000" }, + { "R 0x25849010" }, + { "R 0x2587c000" }, + { "R 0x2587c01c 3" }, + { "R 0x2587c030 8" }, + { "R 0x2587c054 2" }, + { "R 0x2587c078" }, + { "R 0x2587c108 9" }, + { "R 0x2587c20c 3" }, + { "R 0x258a600c 4" }, + { "R 0x258a6020 3" }, + { "R 0x258a6034 2" }, + { "R 0x258a6040" }, + { "R 0x258a6050" }, + { "R 0x258a6058" }, + { "R 0x258a6060 4" }, + { "R 0x258a7020" }, + { "R 0x258a7030 2" }, + { "R 0x258a7078 4" }, + { "R 0x258a708c 6" }, + { "R 0x258e002c" }, + { "R 0x258e009c 2" }, + { "R 0x258e00a8 3" }, + { "R 0x258e00b8" }, + { "R 0x258e00c0 7" }, + { "R 0x258e00e0" }, + { "R 0x258e00e8" }, + { "R 0x258e00f0" }, + { "R 0x258e00f8" }, + { "R 0x258e0100" }, + { "R 0x258e0108" }, + { "R 0x258e0110" }, + { "R 0x258e0118" }, + { "R 0x258e0120" }, + { "R 0x258e0128" }, + { "R 0x258e0150 4" }, + { "R 0x258e0164" }, + { "R 0x258e01e8" }, + { "R 0x258e1010" }, + { "R 0x258e1060 3" }, + { "R 0x258e1070" }, + { "R 0x258e1084 3" }, + { "R 0x258e3004" }, + { "R 0x258e300c" }, + { "R 0x258e4004" }, + { "R 0x258e4010 2" }, + { "R 0x258e4024 2" }, + { "R 0x258e4038 2" }, + { "R 0x258e600c 5" }, + { "R 0x258e700c 5" }, + { "R 0x258e9004" }, + { "R 0x258e9010 3" }, + { "R 0x258e9020 3" }, + { "R 0x258e9030 3" }, + { "R 0x258e9040 3" }, + { "R 0x258e9050 3" }, + { "R 0x258ea004" }, + { "R 0x258ea010 3" }, + { "R 0x258ea020 3" }, + { "R 0x258ea030 3" }, + { "R 0x258ea040 3" }, + { "R 0x258ea050 3" }, + { "R 0x258f001c" }, + { "R 0x258f0050" }, + { "R 0x258f0058" }, + { "R 0x25c00004" }, + { "R 0x25c01004" }, + { "R 0x25c02004" }, + { "R 0x25c03004" }, + { "R 0x25c04004" }, + { "R 0x25c05004" }, + { "R 0x25c06004" }, + { "R 0x25c07004" }, + { "R 0x25c08004" }, + { "R 0x25c09004" }, + { "R 0x25c0a004" }, + { "R 0x25c0b004" }, + { "R 0x25c0c004" }, + { "R 0x25c0d004" }, + { "R 0x25c0e004" }, + { "R 0x25c0f004" }, + { "R 0x25c10004" }, + { "R 0x25c11004" }, + { "R 0x25c12004" }, + { "R 0x25c13004" }, + { "R 0x25c14004" }, + { "R 0x25c15004" }, + { "R 0x25c16004" }, + { "R 0x25c17004" }, + { "R 0x25c18004" }, + { "R 0x25c19004" }, + { "R 0x25c1a004" }, + { "R 0x25c1b004" }, + { "R 0x25c1c004" }, + { "R 0x25c1d004" }, + { "R 0x25c1e004" }, + { "R 0x25c1f004" }, + { "R 0x25c20004" }, + { "R 0x25c21004" }, + { "R 0x25c22004" }, + { "R 0x25c23004" }, + { "R 0x25c43350 2" }, + { "R 0x25c433f4 11" }, + { "R 0x25c434c0 6" }, + { "R 0x25c43600" }, + { "R 0x25c4360c" }, + { "R 0x25c45040" }, + { "R 0x25c45048" }, + { "R 0x25c45050" }, + { "R 0x25c45058" }, + { "R 0x25c45060" }, + { "R 0x25c45068" }, + { "R 0x25c45070 4" }, + { "R 0x25c45090 14" }, + { "R 0x25c450cc 2" }, + { "R 0x25c45240" }, + { "R 0x25c452a0" }, + { "R 0x25c45300" }, + { "R 0x25c45310" }, + { "R 0x25c45320" }, + { "R 0x25c45330 3" }, + { "R 0x25c47404" }, + { "R 0x25c4740c 3" }, + { "R 0x25c47448" }, + { "R 0x25c47450" }, + { "R 0x25c47458 2" }, + { "R 0x25c47600" }, + { "R 0x25c49000" }, + { "R 0x25c49010" }, + { "R 0x25c7c000" }, + { "R 0x25c7c01c 3" }, + { "R 0x25c7c030 8" }, + { "R 0x25c7c054 2" }, + { "R 0x25c7c078" }, + { "R 0x25c7c108 9" }, + { "R 0x25c7c20c 3" }, + { "R 0x25ca600c 4" }, + { "R 0x25ca6020 3" }, + { "R 0x25ca6034 2" }, + { "R 0x25ca6040" }, + { "R 0x25ca6050" }, + { "R 0x25ca6058" }, + { "R 0x25ca6060 4" }, + { "R 0x25ca7020" }, + { "R 0x25ca7030 2" }, + { "R 0x25ca7078 4" }, + { "R 0x25ca708c 6" }, + { "R 0x25ce002c" }, + { "R 0x25ce009c 2" }, + { "R 0x25ce00a8 3" }, + { "R 0x25ce00b8" }, + { "R 0x25ce00c0 7" }, + { "R 0x25ce00e0" }, + { "R 0x25ce00e8" }, + { "R 0x25ce00f0" }, + { "R 0x25ce00f8" }, + { "R 0x25ce0100" }, + { "R 0x25ce0108" }, + { "R 0x25ce0110" }, + { "R 0x25ce0118" }, + { "R 0x25ce0120" }, + { "R 0x25ce0128" }, + { "R 0x25ce0150 4" }, + { "R 0x25ce0164" }, + { "R 0x25ce01e8" }, + { "R 0x25ce1010" }, + { "R 0x25ce1060 3" }, + { "R 0x25ce1070" }, + { "R 0x25ce1084 3" }, + { "R 0x25ce3004" }, + { "R 0x25ce300c" }, + { "R 0x25ce4004" }, + { "R 0x25ce4010 2" }, + { "R 0x25ce4024 2" }, + { "R 0x25ce4038 2" }, + { "R 0x25ce600c 5" }, + { "R 0x25ce700c 5" }, + { "R 0x25ce9004" }, + { "R 0x25ce9010 3" }, + { "R 0x25ce9020 3" }, + { "R 0x25ce9030 3" }, + { "R 0x25ce9040 3" }, + { "R 0x25ce9050 3" }, + { "R 0x25cea004" }, + { "R 0x25cea010 3" }, + { "R 0x25cea020 3" }, + { "R 0x25cea030 3" }, + { "R 0x25cea040 3" }, + { "R 0x25cea050 3" }, + { "R 0x25cf001c" }, + { "R 0x25cf0050" }, + { "R 0x25cf0058" }, + { "R 0x240a0008 2" }, + { "R 0x240a1008 2" }, + { "R 0x248e0070 7" }, + { "R 0x248e0094 2" }, + { "R 0x248e012c 9" }, + { "R 0x248e0160" }, + { "R 0x248e0364 2" }, + { "R 0x24ce0070 7" }, + { "R 0x24ce0094 2" }, + { "R 0x24ce012c 9" }, + { "R 0x24ce0160" }, + { "R 0x24ce0364 2" }, + { "R 0x258e0070 7" }, + { "R 0x258e0094 2" }, + { "R 0x258e012c 9" }, + { "R 0x258e0160" }, + { "R 0x258e0364 2" }, + { "R 0x25ce0070 7" }, + { "R 0x25ce0094 2" }, + { "R 0x25ce012c 9" }, + { "R 0x25ce0160" }, + { "R 0x25ce0364 2" }, + { "R 0x248e0358" }, + { "R 0x24ce0358" }, + { "R 0x258e0358" }, + { "R 0x25ce0358" }, + { "R 0x248e0008" }, + { "R 0x24ce0008" }, + { "R 0x258e0008" }, + { "R 0x25ce0008" }, + { "R 0x24076b00 2" }, + { "R 0x24076b0c 2" }, + { "R 0x24076b18 2" }, + { "R 0x24076b24 2" }, + { "R 0x24076b30 2" }, + { "R 0x24076b3c 2" }, + { "R 0x24076b48 2" }, + { "R 0x24076b54 2" }, + { "R 0x24076b60 2" }, + { "R 0x24076b6c 2" }, + { "R 0x24076b78 2" }, + { "R 0x24076b84 2" }, + { "R 0x24076b90 2" }, + { "R 0x24076b9c 2" }, + { "R 0x24076ba8 2" }, + { "R 0x24076bb4 2" }, + { "R 0x24076bc0 2" }, + { "R 0x24076bcc 2" }, + { "R 0x24076bd8 2" }, + { "R 0x24076be4 2" }, + { "R 0x24076bf0 2" }, + { "R 0x24076bfc 2" }, + { "R 0x24076c08 2" }, + { "R 0x24076c14 2" }, + { "R 0x24076c20 2" }, + { "R 0x24076c2c 2" }, + { "R 0x24076c38 2" }, + { "R 0x24076c44 2" }, + { "R 0x24076c50 2" }, + { "R 0x24076c5c 2" }, + { "R 0x24076c68 2" }, + { "R 0x24076c74 2" }, + { "R 0x24076950" }, + { "R 0x240760a4" }, + { "R 0x248720b0" }, + { "R 0x258720b0" }, + { "R 0x24c720b0" }, + { "R 0x25c720b0" }, +}; + +static const struct dcc_register_entry pakala_dcc_entries_ll4[] = { + { "R 0x16801000 2" }, + { "R 0x240e0010" }, + { "R 0x240e0020 8" }, + { "R 0x240e0248" }, + { "R 0x24330010" }, + { "R 0x24330020 8" }, + { "R 0x24330248" }, + { "R 0x240e1018" }, + { "R 0x240e1008" }, + { "R 0x240e1010 2" }, + { "R 0x24331018" }, + { "R 0x24331008" }, + { "R 0x24331010 2" }, + { "R 0x1780010" }, + { "R 0x1780020 8" }, + { "R 0x1780248" }, + { "R 0x1782018" }, + { "R 0x1782008" }, + { "R 0x1782010 2" }, + { "R 0x1783018" }, + { "R 0x1783008" }, + { "R 0x1783010 2" }, + { "R 0x1680010" }, + { "R 0x1680020 8" }, + { "R 0x1681048" }, + { "R 0x1682018" }, + { "R 0x1682008" }, + { "R 0x1682010 2" }, + { "R 0x16e0010" }, + { "R 0x16e0020 8" }, + { "R 0x16e0248" }, + { "R 0x16e1018" }, + { "R 0x16e1008" }, + { "R 0x16e1010 2" }, + { "R 0x16e1098" }, + { "R 0x16e1088" }, + { "R 0x16e1090 2" }, + { "R 0x16e1118" }, + { "R 0x16e1108" }, + { "R 0x16e1110 2" }, + { "R 0x1700010" }, + { "R 0x1700020 8" }, + { "R 0x1700248" }, + { "R 0x1702018" }, + { "R 0x1702008" }, + { "R 0x1702010 2" }, + { "R 0x1702218" }, + { "R 0x1702208" }, + { "R 0x1702210 2" }, + { "R 0x1702118" }, + { "R 0x1702108" }, + { "R 0x1702110 2" }, + { "R 0x1600010" }, + { "R 0x1600020 8" }, + { "R 0x1600248 2" }, + { "R 0x1600258" }, + { "R 0x1602018" }, + { "R 0x1602008" }, + { "R 0x1602010 2" }, + { "R 0x1602098" }, + { "R 0x1602088" }, + { "R 0x1602090 2" }, + { "R 0x1602118" }, + { "R 0x1602108" }, + { "R 0x1602110 2" }, + { "R 0x1602198" }, + { "R 0x1602188" }, + { "R 0x1602190 2" }, + { "R 0x1602218" }, + { "R 0x1602208" }, + { "R 0x1602210 2" }, + { "R 0x1602098" }, + { "R 0x1602088" }, + { "R 0x1602090 2" }, + { "R 0x1500010" }, + { "R 0x1500020 8" }, + { "R 0x1500248" }, + { "R 0x1500448" }, + { "R 0x1502018" }, + { "R 0x1502008" }, + { "R 0x1502010 2" }, + { "R 0x1502098" }, + { "R 0x1502088" }, + { "R 0x1502090 2" }, + { "R 0x16e00010" }, + { "R 0x16e00020 8" }, + { "R 0x16e00248" }, + { "R 0x16e01018" }, + { "R 0x16e01008" }, + { "R 0x16e01010 2" }, + { "R 0x1b600010" }, + { "R 0x1b600020 8" }, + { "R 0x1b600248" }, + { "R 0x1b601018" }, + { "R 0x1b601008" }, + { "R 0x1b601010 2" }, + { "R 0x16000104 30" }, + { "R 0x16000204 29" }, + { "R 0x16000384 30" }, + { "R 0xb291024" }, + { "R 0xc201244" }, + { "R 0xc202244" }, + { "R 0xbde1034 2" }, + { "R 0xb201020 2" }, + { "R 0xb211020 2" }, + { "R 0xb221020 2" }, + { "R 0xb231020 2" }, + { "R 0xb204520" }, + { "R 0xb200000" }, + { "R 0xb210000" }, + { "R 0xb220000" }, + { "R 0xb230000" }, + { "R 0x16500010" }, + { "R 0x16510010" }, + { "R 0x16520010" }, + { "R 0x16530010" }, + { "R 0x16500030" }, + { "R 0x16510030" }, + { "R 0x16520030" }, + { "R 0x16530030" }, + { "R 0x16500038" }, + { "R 0x16510038" }, + { "R 0x16520038" }, + { "R 0x16530038" }, + { "R 0x16500040" }, + { "R 0x16510040" }, + { "R 0x16520040" }, + { "R 0x16530040" }, + { "R 0x16500048" }, + { "R 0x16500400 3" }, + { "R 0x16510400 3" }, + { "R 0x16520400 3" }, + { "R 0x16530400 3" }, + { "R 0x16510d3c" }, + { "R 0x16510d54" }, + { "R 0x16510d6c" }, + { "R 0x16510d84" }, + { "R 0x16510d9c" }, + { "R 0x16510db4" }, + { "R 0x16510dcc" }, + { "R 0x16510de4" }, + { "R 0x16510dfc" }, + { "R 0x16510e14" }, + { "R 0x16510e2c" }, + { "R 0x16510e44" }, + { "R 0x16510e5c" }, + { "R 0x16510e74" }, + { "R 0x16510e8c" }, + { "R 0x16510ea4" }, + { "R 0x16510fdc" }, + { "R 0x16510ff4" }, + { "R 0x1651100c" }, + { "R 0x16511024" }, + { "R 0x1651103c" }, + { "R 0x16511054" }, + { "R 0x1651106c" }, + { "R 0x16511084" }, + { "R 0x1651109c" }, + { "R 0x165110b4" }, + { "R 0x165110cc" }, + { "R 0x165110e4" }, + { "R 0x165110fc" }, + { "R 0x16511114" }, + { "R 0x1651112c" }, + { "R 0x16511144" }, + { "R 0x1651127c" }, + { "R 0x16511294" }, + { "R 0x165112ac" }, + { "R 0x165112c4" }, + { "R 0x165112dc" }, + { "R 0x165112f4" }, + { "R 0x1651130c" }, + { "R 0x16511324" }, + { "R 0x1651133c" }, + { "R 0x16511354" }, + { "R 0x1651136c" }, + { "R 0x16511384" }, + { "R 0x1651139c" }, + { "R 0x165113b4" }, + { "R 0x165113cc" }, + { "R 0x165113e4" }, + { "R 0x1651151c" }, + { "R 0x16511534" }, + { "R 0x1651154c" }, + { "R 0x16511564" }, + { "R 0x1651157c" }, + { "R 0x16511594" }, + { "R 0x165115ac" }, + { "R 0x165115c4" }, + { "R 0x165115dc" }, + { "R 0x165115f4" }, + { "R 0x1651160c" }, + { "R 0x16511624" }, + { "R 0x1651163c" }, + { "R 0x16511654" }, + { "R 0x1651166c" }, + { "R 0x16511684" }, + { "R 0x110004 2" }, + { "R 0x11003c 3" }, + { "R 0x176040" }, + { "R 0x10c0000 4" }, + { "R 0x10c1000 2" }, + { "R 0x10c1010 7" }, + { "R 0x10c1100 3" }, + { "R 0x10c1110 5" }, + { "R 0x10c1130 2" }, + { "R 0x10c113c 2" }, + { "R 0x10c1148 3" }, + { "R 0x10c1800 11" }, + { "R 0x10c2000" }, + { "R 0x10cf004" }, + { "R 0x16801000 2" }, +}; + +static const struct dcc_link_config pakala_link_configs[] = { + { + .link_list = 6, + .entries = pakala_dcc_entries_ll6, + .num_entries = ARRAY_SIZE(pakala_dcc_entries_ll6), + }, + { + .link_list = 4, + .entries = pakala_dcc_entries_ll4, + .num_entries = ARRAY_SIZE(pakala_dcc_entries_ll4), + }, +}; + +static const struct dcc_config pakala_config = { + .lists = pakala_link_configs, + .num_lists = ARRAY_SIZE(pakala_link_configs), +}; + +static const struct dcc_pdata pakala_pdata = { + .base = 0x100ff000, + .size = 0x00001000, + .ram_base = 0x10084000, + .ram_size = 0x4000, + .dcc_offset = 0x4000, + .map_ver = 0x3, + .config = &pakala_config, +}; + +#endif /* _QCOM_DCC_PAKALA_CONFIG_H */ From 59e6403140b19d8b78b3a77fb2afbbe421defe33 Mon Sep 17 00:00:00 2001 From: Ignatius Michael Jihan Date: Tue, 7 Apr 2026 11:07:43 +0530 Subject: [PATCH 0612/1330] QCLINUX: arm64: dts: qcom: Add Hamoa camx overlay dts Add CAMX overlay dts file for Hamoa boards. This change also enables the compilation of the CAMX overlay for Hamoa boards. Signed-off-by: Ignatius Michael Jihan (cherry picked from commit 6489c6f75d0c94454198e0af505d5d2d8dae98c7) --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../boot/dts/qcom/hamoa-camera-camx.dtso | 26 + .../boot/dts/qcom/hamoa-camera-sensor.dtsi | 53 + arch/arm64/boot/dts/qcom/hamoa-camera.dtsi | 2473 +++++++++++++++++ 4 files changed, 2556 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/hamoa-camera-camx.dtso create mode 100644 arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/hamoa-camera.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 61fb9d55add0e..e5e41bce4d51b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -447,6 +447,10 @@ dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-dena x1p64100-acer-swift-sf14-11-el2-dtbs := x1p64100-acer-swift-sf14-11.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-acer-swift-sf14-11.dtb x1p64100-acer-swift-sf14-11-el2.dtb +hamoa-camera-dtbs := hamoa-iot-evk.dtb hamoa-camera-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += hamoa-camera-camx.dtb + lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/hamoa-camera-camx.dtso b/arch/arm64/boot/dts/qcom/hamoa-camera-camx.dtso new file mode 100644 index 0000000000000..d63daf990f2a1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-camera-camx.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hamoa-camera.dtsi" +#include "hamoa-camera-sensor.dtsi" + +&camss { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi new file mode 100644 index 0000000000000..7ebfcf1ec3912 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci0 { + /*cam0-cmk_imx577*/ + qcom,cam-sensor0 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l4m_1p8>; + regulator-names = "cam_vio"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend &cam_sensor_suspend_rst1>; + gpios = <&tlmm 97 0>, + <&tlmm 110 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK1", + "CAMIF_RESET1", + "CAM_CUSTOM1"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <0>; + status = "okay"; + }; +}; + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/hamoa-camera.dtsi b/arch/arm64/boot/dts/qcom/hamoa-camera.dtsi new file mode 100644 index 0000000000000..94dd42b380f4e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-camera.dtsi @@ -0,0 +1,2473 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +&soc { + cam_icp: qcom,icp@ac01000 { + compatible = "qcom,cam-icp_v2"; + icp-version = <0x0200>; + reg = <0x0 0xac01000 0x0 0x400>, + <0x0 0xac01800 0x0 0x400>, + <0x0 0x0ac04000 0x0 0x1000>; + reg-names = "icp_csr", "icp_cirq", "icp_wd0"; + reg-cam-base = <0x1000 0x1800 0x4000>; + interrupts = ; + interrupt-names = "icp"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + memory-region = <&camera_mem>; + clocks = <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + clock-names = "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + clock-rates = <0 300000000 0>, + <0 400000000 0>, + <0 480000000 0>, + <0 600000000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "nominal"; + nrt-device; + src-clock-name = "icp_clk_src"; + operating-points-v2 = <&icp_opp_table>; + clock-control-debugfs = "true"; + fw_name = "qcom/x1e80100/CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x00000A0A>; + cam_hw_pid = <3>; + cell-index = <0>; + status = "okay"; + + icp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_cpas: qcom,cam-cpas@ac13000 { + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg = <0x0 0xac13000 0x0 0x1000>, + <0x0 0xac19000 0x0 0xC000>, + <0x0 0xbbf0000 0x0 0x1F00>; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg-cam-base = <0x13000 0x19000 0x0bbf0000>; + interrupts = ; + interrupt-names = "cpas_camnoc"; + camnoc-axi-min-ib-bw = <3000000000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names = "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk", + "camnoc_axi_nrt_clk", + "camcc_debug_clk"; + clock-rates = < 0 0 0 0 0 0 0 0 0 0 0 0>, + < 0 0 0 64000000 0 0 80000000 0 240000000 0 0 0>, + < 0 0 0 80000000 0 0 100000000 0 300000000 0 0 0>, + < 0 0 0 80000000 0 0 400000000 0 400000000 0 0 0>; + clock-cntl-level = "suspend", "lowsvsd1", "lowsvs", "nominal"; + clock-names-option = "cam_icp_clk"; + clocks-option = <&camcc CAM_CC_ICP_CLK>; + clock-rates-option = <400000000>; + src-clock-name = "camnoc_axi_clk_src"; + operating-points-v2 = <&cpas_opp_table>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + cam-icc-path-names = "cam_ahb"; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnects =<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_sf_0", + "cam_sf_icp"; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = <0 0>, <0 76800>, <0 76800>, <0 150000>, + <0 150000>, <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy4", + "cci0", "cci1", "csid0", "csid1", "csid2", + "csid3", "ife0", "ife1", "ife2", "ife3", "sfe0", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", + "rt-cdm3", "cam-cdm-intf0", "bps0", "icp0", + "jpeg-dma0", "jpeg-enc0", "tpg13", "tpg14", + "tpg15"; + cell-index = <0>; + status = "okay"; + + camera-bus-nodes { + level0-nodes { + level-index = <0>; + + bps0_all_rd: bps0-all-rd { + cell-index = <0>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <1>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_wr>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <2>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt1_rd>; + }; + + ife0_linear_stats_wr: ife0-linear-stats-wr { + cell-index = <3>; + node-name = "ife0-linear-stats-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr3>; + }; + + ife0_pdaf_wr: ife0-pdaf-wr { + cell-index = <4>; + node-name = "ife0-pdaf-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_rt0_wr2>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <5>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <6>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_linear_stats_wr: ife1-linear-stats-wr { + cell-index = <7>; + node-name = "ife1-linear-stats-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr3>; + }; + + ife1_pdaf_wr: ife1-pdaf-wr { + cell-index = <8>; + node-name = "ife1-pdaf-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <9>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <10>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr0>; + }; + + ife2_rdi_stats_pixel_raw_wr: ife2-rdi-stats-pixel-raw-wr { + cell-index = <11>; + node-name = "ife2-rdi-stats-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr4>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <12>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr4>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <13>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level2_nrt0_wr>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <14>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <15>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <16>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <17>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_wr0>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <18>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <19>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_wr0>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <20>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <21>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + /* IFE Lite 0 */ + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <22>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + /* IFE Lite 1 */ + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <23>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + sfe0_all_rd: sfe0-all-rd { + cell-index = <24>; + node-name = "sfe0-all-rd"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level2_rt0_rd>; + }; + + sfe0_rdi_stats_nrdi_wr: sfe0-rdi-stats-nrdi-wr { + cell-index = <25>; + node-name = "sfe0-rdi-stats-nrdi-wr"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr1>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <26>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <27>; + node-name = "level1-nrt0-rd1"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <28>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <29>; + node-name = "level1-sfe-rd"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = ; + }; + + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <30>; + node-name = "level1-ife-ubwc-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <31>; + node-name = "level1-ife-rdi-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <32>; + node-name = "level1-ife-pdaf"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr3: level1-rt0-wr3 { + cell-index = <33>; + node-name = "level1-ife01-linear-stats"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr4: level1-rt0-wr4 { + cell-index = <34>; + node-name = "level1-ifelite"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <35>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <36>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <37>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = ; + bus-width-factor = <4>; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <38>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_wr: level2-rt0-wr { + cell-index = <39>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + }; + + level3-nodes { + level-index = <3>; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <40>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <41>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_icp"; + }; + }; + + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <42>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0"; + }; + }; + }; + }; + + cpas_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_cci0: qcom,cci0@ac15000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac15000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupts = ; + interrupt-names = "cci0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + operating-points-v2 = <&cci0_opp_table>; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci0_active>; + pinctrl-1 = <&cci0_suspend>; + pinctrl-2 = <&cci1_active>; + pinctrl-3 = <&cci1_suspend>; + cell-index = <0>; + status = "okay"; + + cci0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci0: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_100Khz_cci0: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + }; + + cam_cci1: qcom,cci1@ac16000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac16000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupts = ; + interrupt-names = "cci1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + pinctrl-2 = <&cci3_active>; + pinctrl-3 = <&cci3_suspend>; + operating-points-v2 = <&cci1_opp_table>; + cell-index = <1>; + status = "okay"; + + cci1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci1: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_100Khz_cci1: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + }; + + qcom,rt-cdm0@ac25000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac25000 0x0 0x400>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupts = ; + interrupt-names = "rt-cdm0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <400000000 0>; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table0>; + nrt-device; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <0>; + status = "okay"; + + cdm_cpas_opp_table0: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm1@ac26000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac26000 0x0 0x400>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x26000>; + interrupts = ; + interrupt-names = "rt-cdm1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + clock-rates = <400000000 0>; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table1>; + nrt-device; + cdm-client-names = "ife1", "dualife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <1>; + status = "okay"; + + cdm_cpas_opp_table1: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_jpeg_enc: qcom,jpegenc@ac2a000 { + compatible = "qcom,cam_jpeg_enc_680"; + reg = <0x0 0xac2a000 0x0 0x1000>, + <0x0 0x0ac19000 0x0 0xc000>; + reg-names = "jpegenc_hw", "cam_camnoc"; + reg-cam-base = <0x2a000 0x19000>; + interrupts = ; + interrupt-names = "jpeg"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "jpegenc_clk_src", + "jpegenc_clk"; + clock-rates = <160000000 0>, + <200000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + operating-points-v2 = <&jpeg_enc_opp_table>; + nrt-device; + cam_hw_pid = <12 14>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + cell-index = <0>; + status = "okay"; + + jpeg_enc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-48000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_jpeg_dma: qcom,jpegdma@ac2b000 { + compatible = "qcom,cam_jpeg_dma_680"; + reg = <0x0 0xac2b000 0x0 0x1000>, + <0x0 0x0ac19000 0x0 0xc000>; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg-cam-base = <0x2b000 0x19000>; + interrupts = ; + interrupt-names = "jpegdma"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "jpegdma_clk_src", + "jpegdma_clk"; + clock-rates = <160000000 0>, + <200000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + operating-points-v2 = <&jpeg_dma_opp_table>; + nrt-device; + cam_hw_pid = <13 15>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + cell-index = <0>; + status = "okay"; + + jpeg_dma_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-48000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_bps: qcom,bps@ac2c000 { + compatible = "qcom,cam-bps680"; + reg = <0x0 0xac2c000 0x0 0xb000>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + power-domains = <&camcc CAM_CC_BPS_GDSC>; + clocks = <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_CPAS_BPS_CLK>; + clock-names = "bps_ahb_clk", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk", + "cam_cc_cpas_bps_clk"; + clock-rates = <0 0 160000000 0 0>, + <0 0 200000000 0 0>, + <0 0 400000000 0 0>, + <0 0 600000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "nominal"; + nrt-device; + src-clock-name = "bps_clk_src"; + operating-points-v2 = <&bps_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <6 7>; + cell-index = <0>; + status = "okay"; + + bps_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + compatible = "qcom,cam-ipe680"; + reg = <0x0 0xac42000 0x0 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + power-domains = <&camcc CAM_CC_IPE_0_GDSC>; + clocks = <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CPAS_IPE_NPS_CLK>; + clock-names = "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_cpas_ipe_nps_clk"; + clock-rates = <0 0 0 304000000 0 0 0>, + <0 0 0 364000000 0 0 0>, + <0 0 0 500000000 0 0 0>, + <0 0 0 600000000 0 0 0>, + <0 0 0 700000000 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + operating-points-v2 = <&ipe0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <22 23 30>; + cell-index = <0>; + status = "okay"; + + ipe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-304000000 { + opp-hz = /bits/ 64 <304000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-364000000 { + opp-hz = /bits/ 64 <364000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe0: qcom,ife0@ac62000 { + compatible = "qcom,vfe680"; + reg = <0x0 0xac62000 0x0 0xf000>, + <0x0 0xac19000 0x0 0xc000>; + reg-names = "ife", "cam_camnoc"; + reg-cam-base = <0x62000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "ife0"; + power-domains = <&camcc CAM_CC_IFE_0_GDSC>; + clocks = <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>; + clock-names = "ife_0_fast_ahb", + "ife_0_clk_src", + "ife_0_clk", + "cam_cc_cpas_ife_0_clk"; + clock-rates = <0 345600000 0 0>, + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_0_clk_src"; + operating-points-v2 = <&vfe0_opp_table>; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 4 20 8>; + cell-index = <0>; + status = "okay"; + + vfe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-727000000 { + opp-hz = /bits/ 64 <727000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe1: qcom,ife1@ac71000 { + compatible = "qcom,vfe680"; + reg = <0x0 0xac71000 0x0 0xf000>, + <0x0 0xac19000 0x0 0xc000>; + reg-names = "ife", "cam_camnoc"; + reg-cam-base = <0x71000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "ife1"; + power-domains = <&camcc CAM_CC_IFE_1_GDSC>; + clocks = <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>; + clock-names = "ife_1_fast_ahb", + "ife_1_clk_src", + "ife_1_clk", + "cam_cc_cpas_ife_1_clk"; + clock-rates = <0 345600000 0 0>, + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_1_clk_src"; + operating-points-v2 = <&vfe1_opp_table>; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <17 5 21 9>; + cell-index = <1>; + status = "okay"; + + vfe1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-727000000 { + opp-hz = /bits/ 64 <727000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_sfe0: qcom,sfe0@ac9e000 { + compatible = "qcom,sfe680"; + reg = <0x0 0xac9e000 0x0 0x8000>; + reg-names = "sfe0"; + reg-cam-base = <0x9e000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "sfe"; + power-domains = <&camcc CAM_CC_SFE_0_GDSC>; + clocks = <&camcc CAM_CC_SFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_0_CLK_SRC>, + <&camcc CAM_CC_SFE_0_CLK>, + <&camcc CAM_CC_CPAS_SFE_0_CLK>; + clock-names = "sfe_0_fast_ahb", + "sfe_0_clk_src", + "sfe_0_clk", + "cam_cc_cpas_sfe_0_clk"; + clock-rates = <0 345600000 0 0>, + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "sfe_0_clk_src"; + operating-points-v2 = <&sfe0_opp_table>; + cam_hw_pid = <10 2>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "okay"; + + sfe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-727000000 { + opp-hz = /bits/ 64 <727000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid0: qcom,csid0@acb7000 { + compatible = "qcom,csid695"; + reg = <0x0 0xacb7000 0x0 0xd00>, + <0x0 0xacb6000 0x0 0x1000>; + reg-names = "csid", "csid_top"; + reg-cam-base = <0xb7000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "csid0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0 0>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clock-rates = <300000000 0 0>, + <400000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "csid_clk_src"; + operating-points-v2 = <&csid0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "okay"; + + csid0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid1: qcom,csid1@acb9000 { + compatible = "qcom,csid695"; + reg = <0x0 0xacb9000 0x0 0xd00>, + <0x0 0xacb6000 0x0 0x1000>; + reg-names = "csid", "csid_top"; + reg-cam-base = <0xb9000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "csid1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0 0>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clock-rates = <300000000 0 0>, + <400000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "csid_clk_src"; + operating-points-v2 = <&csid1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "okay"; + + csid1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite0: qcom,csid-lite0@acc6000 { + compatible = "qcom,csid-lite680"; + reg = <0x0 0xacc6000 0x0 0xa00>; + reg-names = "csid-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xc6000>; + interrupts = ; + interrupt-names = "csid-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 1 0 0 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <2>; + status = "okay"; + + csid_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite0: qcom,ife-lite0@acc6000 { + compatible = "qcom,vfe-lite695"; + reg = <0x0 0xacc6000 0x0 0x4000>; + reg-names = "ife-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xc6000>; + interrupts = ; + interrupt-names = "ife-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 0 0 1 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <0>; + cell-index = <2>; + status = "okay"; + + vfe_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite1: qcom,csid-lite1@acca000 { + compatible = "qcom,csid-lite680"; + reg = <0x0 0xacca000 0x0 0xa00>; + reg-names = "csid-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xca000>; + interrupts = ; + interrupt-names = "csid-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 1 0 0 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <3>; + status = "okay"; + + csid_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite1: qcom,ife-lite1@acca000 { + compatible = "qcom,vfe-lite695"; + reg = <0x0 0xacca000 0x0 0x4000>; + reg-names = "ife-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xca000>; + interrupts = ; + interrupt-names = "ife-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 0 0 1 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite1_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <1>; + cell-index = <3>; + status = "okay"; + + vfe_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xace4000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupts = ; + interrupt-names = "CSIPHY0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l1c_1p2>; + csi-vdd-0p9-supply = <&vreg_l2c_0p8>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 920000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy0_opp_table>; + cell-index = <0>; + status = "okay"; + + csiphy0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xace6000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupts = ; + interrupt-names = "CSIPHY1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l1c_1p2>; + csi-vdd-0p9-supply = <&vreg_l2c_0p8>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 920000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy1_opp_table>; + cell-index = <1>; + status = "okay"; + + csiphy1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy2: qcom,csiphy2@ace8000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xace8000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupts = ; + interrupt-names = "CSIPHY2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l1c_1p2>; + csi-vdd-0p9-supply = <&vreg_l2c_0p8>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 920000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy2_opp_table>; + cell-index = <2>; + status = "okay"; + + csiphy2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xacec000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupts = ; + interrupt-names = "CSIPHY4"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l1c_1p2>; + csi-vdd-0p9-supply = <&vreg_l2c_0p8>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 920000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy4_opp_table>; + cell-index = <4>; + status = "okay"; + + csiphy4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf6000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg0", "cam_cpas_top"; + reg-cam-base = <0xf6000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg0"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg0_opp_table>; + cell-index = <13>; + phy-id = <0>; + status = "okay"; + + csiphy_tpg0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf7000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg1", "cam_cpas_top"; + reg-cam-base = <0xf7000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg1"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg1_opp_table>; + cell-index = <14>; + phy-id = <1>; + status = "okay"; + + csiphy_tpg1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg15: qcom,tpg15@acf8000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf8000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg2", "cam_cpas_top"; + reg-cam-base = <0xf8000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg2"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg2_opp_table>; + cell-index = <15>; + phy-id = <2>; + status = "okay"; + + csiphy_tpg2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm2@acf9000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xacf9000 0x0 0x400>; + reg-names = "rt-cdm2"; + reg-cam-base = <0xf9000>; + interrupts = ; + interrupt-names = "rt-cdm2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_lite_ahb"; + clock-rates = <80000000 0>; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table2>; + nrt-device; + cdm-client-names = "ife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <2>; + status = "okay"; + + cdm_cpas_opp_table2: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm3@acfa000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xacfa000 0x0 0x400>; + reg-names = "rt-cdm3"; + reg-cam-base = <0xfa000>; + interrupts = ; + interrupt-names = "rt-cdm3"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_lite_ahb"; + clock-rates = <80000000 0>; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table3>; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <3>; + status = "okay"; + + cdm_cpas_opp_table3: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + cell-index = <0>; + status = "okay"; + }; + + cam_icp_firmware: qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "okay"; + icp_pc_en; + icp_use_pil; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "okay"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "okay"; + }; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "okay"; + }; + + cam_smmu: qcom,cam-smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "okay"; + force_cache_allocs; + need_shared_buffer_padding; + + msm-cam-smmu-cpas-cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x0000>; + cam-smmu-label = "rt-cdm"; + dma-coherent; + multiple-client-devices; + + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1800 0x0060>, + <&apps_smmu 0x1820 0x0060>, + <&apps_smmu 0x1840 0x0060>, + <&apps_smmu 0x1860 0x0060>, + <&apps_smmu 0x1900 0x0000>, + <&apps_smmu 0x1980 0x0020>, + <&apps_smmu 0x19A0 0x0020>; + cam-smmu-label = "icp"; + iova-region-discard = <0xe0000000 0x800000>; + dma-coherent; + + icp_iova_mem_map: iova-mem-map { + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "okay"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + iova-region-start = <0x10400000>; + iova-region-len = <0x700000>; + iova-region-id = <0x6>; + status = "okay"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.8 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xe0000000 0x800000>; + status = "okay"; + }; + + iova-mem-region-shared { + /* Shared region is ~250MB long */ + iova-region-name = "shared"; + iova-region-start = <0x800000>; + iova-region-len = <0xFC00000>; + iova-region-id = <0x1>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0800 0x0060>, + <&apps_smmu 0x0820 0x0060>, + <&apps_smmu 0x0840 0x0060>, + <&apps_smmu 0x0860 0x0060>; + dma-coherent; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18E0 0x0000>; + cam-smmu-label = "jpeg"; + dma-coherent; + + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "okay"; + }; + + qcom,camera-main { + compatible = "qcom,camera_x1e80100"; + status = "okay"; + }; +}; + +&tlmm { + cam_sensor_active_int: cam-sensor-active-int { + /* CUSTOM */ + mux { + pins = "gpio19"; + function = "cam_pwe"; + }; + + config { + pins = "gpio19"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam-sensor-active-rst0 { + /* RESET REAR */ + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + pins = "gpio109"; + function = "gpio"; + }; + }; + + cam_sensor_active_rst1: cam-sensor-active-rst1 { + /* RESET */ + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst4: cam-sensor-active-rst4 { + /* RESET REAR */ + config { + pins = "gpio237"; + bias-disable; /* No PULL */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio237"; + function = "gpio"; + }; + }; + + cam_sensor_mclk0_active: cam-sensor-mclk0-active { + /* mclk0 */ + config { + pins = "gpio96"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk0_suspend: cam-sensor-mclk0-suspend { + /* mclk0 */ + config { + pins = "gpio96"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk1_active: cam-sensor-mclk1-active { + /* MCLK1 */ + mux { + pins = "gpio97"; + function = "cam_mclk"; + }; + + config { + pins = "gpio97"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam-sensor-mclk1-suspend { + /* MCLK1 */ + mux { + pins = "gpio97"; + function = "cam_mclk"; + }; + + config { + pins = "gpio97"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam-sensor-mclk4-active { + /* mclk4 */ + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio100"; + function = "cam_aon"; + }; + }; + + cam_sensor_mclk4_suspend: cam-sensor-mclk4-suspend { + /* mclk4 */ + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio100"; + function = "cam_aon"; + }; + }; + + cam_sensor_suspend_int: cam-sensor-suspend-int { + /* CUSTOM */ + mux { + pins = "gpio19"; + function = "cam_pwe"; + }; + + config { + pins = "gpio19"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam-sensor-suspend-rst0 { + /* RESET REAR */ + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + + mux { + pins = "gpio109"; + function = "gpio"; + }; + }; + + cam_sensor_suspend_rst1: cam-sensor-suspend-rst1 { + /* RESET */ + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst4: cam-sensor-suspend-rst4 { + /* RESET REAR */ + config { + pins = "gpio237"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <12>; /* 12 MA */ + output-low; + }; + + mux { + pins = "gpio237"; + function = "gpio"; + }; + }; + + cci0_active: cci0-active { + config { + /* DATA, CLK */ + pins = "gpio101","gpio102"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio101","gpio102"; // Only 2 + function = "cci_i2c"; + }; + }; + + cci0_suspend: cci0-suspend { + config { + /* DATA, CLK */ + pins = "gpio101","gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio101","gpio102"; + function = "cci_i2c"; + }; + }; + + cci1_active: cci1-active { + config { + /* DATA, CLK */ + pins = "gpio103","gpio104"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio103","gpio104"; // Only 2 + function = "cci_i2c"; + }; + }; + + cci1_suspend: cci1-suspend { + config { + /* DATA, CLK */ + pins = "gpio103","gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio103","gpio104"; + function = "cci_i2c"; + }; + }; + + cci2_active: cci2-active { + config { + /* DATA, CLK */ + pins = "gpio105","gpio106"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio105","gpio106"; // Only 2 + function = "cci_i2c"; + }; + }; + + cci2_suspend: cci2-suspend { + config { + /* DATA, CLK */ + pins = "gpio105","gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + }; + }; + + cci3_active: cci3-active { + config { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + }; + }; + + cci3_suspend: cci3-suspend { + config { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + }; + }; +}; From f2e387451e4f9cdb2f6ede9effd109f3bc886da2 Mon Sep 17 00:00:00 2001 From: Ignatius Michael Jihan Date: Tue, 7 Apr 2026 16:37:49 +0530 Subject: [PATCH 0613/1330] QCLINUX: arm64: dts: qcom: align hamoa camera DTB variable naming Rename the hamoa camera DTBs variable to match the hamoa-camera-camx DTB target naming and improve consistency with existing Makefile conventions. Fixes: 9041882f7c4c ("QCLINUX: arm64: dts: qcom: Add hamoa camx overlay dts") Signed-off-by: Ignatius Michael Jihan (cherry picked from commit 47a350b7080859f4a63a7fc95c4df091a716f28a) --- arch/arm64/boot/dts/qcom/Makefile | 4 ++-- .../dts/qcom/{hamoa-camera-camx.dtso => hamoa-evk-camx.dtso} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm64/boot/dts/qcom/{hamoa-camera-camx.dtso => hamoa-evk-camx.dtso} (100%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e5e41bce4d51b..b5818421f81f8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -447,9 +447,9 @@ dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-dena x1p64100-acer-swift-sf14-11-el2-dtbs := x1p64100-acer-swift-sf14-11.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-acer-swift-sf14-11.dtb x1p64100-acer-swift-sf14-11-el2.dtb -hamoa-camera-dtbs := hamoa-iot-evk.dtb hamoa-camera-camx.dtbo +hamoa-evk-camx-dtbs := hamoa-iot-evk.dtb hamoa-evk-camx.dtbo -dtb-$(CONFIG_ARCH_QCOM) += hamoa-camera-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += hamoa-evk-camx.dtb lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo diff --git a/arch/arm64/boot/dts/qcom/hamoa-camera-camx.dtso b/arch/arm64/boot/dts/qcom/hamoa-evk-camx.dtso similarity index 100% rename from arch/arm64/boot/dts/qcom/hamoa-camera-camx.dtso rename to arch/arm64/boot/dts/qcom/hamoa-evk-camx.dtso From df8c4594117e032feefaf609bf299f37c064a347 Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Wed, 8 Apr 2026 02:13:12 +0530 Subject: [PATCH 0614/1330] PENDING: arm64: dts: qcom: lemans-evk: add overlay for QPS615 ethernet Add an overlay devicetree for Lemans EVK for temporary enablement of the QPS615 PCIE switch's 10GbE and 2.5Gbe ethernet ports. Signed-off-by: Mohd Ayaan Anwar (cherry picked from commit a9127f4cdf000654e7dd68f0c0e436ab727ac5a6) --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/lemans-evk-staging.dtso | 68 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b5818421f81f8..e54c4a0b90257 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -459,6 +459,8 @@ lemans-camx-el2-dtbs := lemans-evk-el2.dtb lemans-evk-camx.dtbo lemans-camx-el2. dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo + monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-staging.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-staging.dtso new file mode 100644 index 0000000000000..cf345ec5d06c9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-staging.dtso @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c18 { + eeprom@52 { + nvmem-layout { + mac_addr2: mac-addr@6 { + reg = <0x6 0x6>; + }; + mac_addr3: mac-addr@c { + reg = <0xc 0x6>; + }; + }; + }; +}; + +&pcieport0 { + pcie@0,0 { + pcie@3,0 { + pci@0,0 { + interrupts-extended = <&tlmm 56 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + nvmem-cells = <&mac_addr2>; + nvmem-cell-names = "mac-address"; + pinctrl-names = "default"; + pinctrl-0 = <&aqr_intn_wol_sig>; + phy-reset-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; + reset-deassert-us = <221000>; + }; + + pci@0,1 { + interrupts-extended = <&tlmm 57 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + nvmem-cells = <&mac_addr3>; + nvmem-cell-names = "mac-address"; + pinctrl-names = "default"; + pinctrl-0 = <&napa_intn_wol_sig>; + phy-reset-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; + reset-deassert-us = <20000>; + }; + }; + }; +}; + +&tlmm { + qps615_intn_wol { + aqr_intn_wol_sig: aqr-intn-wol-sig { + pins = "gpio56"; + function = "gpio"; + input-enable; + bias-disable; + }; + napa_intn_wol_sig: napa-intn-wol-sig { + pins = "gpio57"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; +}; From 6d406706dd3883517380153668483c1073197efc Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Wed, 8 Apr 2026 02:19:46 +0530 Subject: [PATCH 0615/1330] PENDING: arm64: dts: qcom: monaco-evk: add overlay for QPS615 ethernet Add an overlay devicetree for Monaco EVK for temporary enablement of the QPS615 PCIE switch's 10GbE and 2.5Gbe ethernet ports. Signed-off-by: Mohd Ayaan Anwar (cherry picked from commit ddb0a6e20863b3ea03f1b4b4d58f4397af9bf4e2) --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/monaco-evk-staging.dtso | 68 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e54c4a0b90257..05923f605a542 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -469,6 +469,8 @@ monaco-camx-el2-dtbs := monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2. dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo + qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-staging.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-staging.dtso new file mode 100644 index 0000000000000..a646b28f6f9d0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-staging.dtso @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&eeprom1 { + nvmem-layout { + mac_addr1: mac-addr@0 { + reg = <0x0 0x6>; + }; + + mac_addr2: mac-addr@6 { + reg = <0x6 0x6>; + }; + }; +}; + +&pcieport0 { + pcie@0,0 { + pcie@3,0 { + pci@0,0 { + interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + nvmem-cells = <&mac_addr1>; + nvmem-cell-names = "mac-address"; + pinctrl-names = "default"; + pinctrl-0 = <&aqr_intn_wol_sig>; + phy-reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + reset-deassert-us = <221000>; + }; + + pci@0,1 { + interrupts-extended = <&tlmm 39 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + nvmem-cells = <&mac_addr2>; + nvmem-cell-names = "mac-address"; + pinctrl-names = "default"; + pinctrl-0 = <&napa_intn_wol_sig>; + phy-reset-gpios = <&expander5 0 GPIO_ACTIVE_HIGH>; + reset-deassert-us = <20000>; + }; + }; + }; +}; + +&tlmm { + qps615_intn_wol { + aqr_intn_wol_sig: aqr-intn-wol-sig { + pins = "gpio40"; + function = "gpio"; + input-enable; + bias-disable; + }; + + napa_intn_wol_sig: napa-intn-wol-sig { + pins = "gpio39"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; +}; From b604e763fc63132bae523c0686b3d59210749d3a Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Wed, 8 Apr 2026 02:24:07 +0530 Subject: [PATCH 0616/1330] PENDING: arm64: dts: qcom: rb3gen2: add overlay for QPS615 ethernet Add an overlay devicetree for Rb3Gen2 for temporary enablement of the QPS615 PCIE switch's 10GbE and 2.5Gbe ethernet ports. Signed-off-by: Mohd Ayaan Anwar (cherry picked from commit 7fe3c3e36a45366e0dbb4122254a26ae80f01b14) --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../dts/qcom/qcs6490-rb3gen2-staging.dtso | 95 +++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 05923f605a542..71d564768c4a5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -480,6 +480,8 @@ qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.d dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-staging.dtbo + qcs8300-ride-camx-dtbs:= qcs8300-ride.dtb qcs8300-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso new file mode 100644 index 0000000000000..79f9c055c9776 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +/ { + qep_vreg: qep_vreg { + compatible = "regulator-fixed"; + regulator-name = "qep_vreg"; + gpio = <&pm7325_gpios 8 0>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + }; + + aqr_vreg: aqr_vreg { + compatible = "regulator-fixed"; + regulator-name = "aqr_vreg"; + gpio = <&pm7250b_gpios 4 0>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + }; +}; + +&pcie1_port0 { + pcie@0,0 { + pcie@3,0 { + /* + * PF0: also acts as the QPS615 GPIO controller. + * gpio-controller / #gpio-cells expose the TC956X + * internal GPIO lines (hardware numbers 0-13) so that + * phy-reset-gpios can reference them. + */ + qps615: pci@0,0 { + interrupts-extended = <&tlmm 141 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + phy-supply = <&aqr_vreg>; + pinctrl-names = "default"; + pinctrl-0 = <&aqr_intn_wol_sig>; + phy-reset-gpios = <&qps615 0 GPIO_ACTIVE_LOW>; + reset-deassert-us = <221000>; + + gpio-controller; + #gpio-cells = <2>; + }; + + pci@0,1 { + interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + phy-supply = <&qep_vreg>; + pinctrl-names = "default"; + pinctrl-0 = <&napa_intn_wol_sig>; + phy-reset-gpios = <&qps615 1 GPIO_ACTIVE_LOW>; + reset-deassert-us = <20000>; + }; + }; + }; +}; + +&tlmm { + qps615_intn_wol { + aqr_intn_wol_sig: aqr_intn_wol_sig { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + input-enable; + bias-disable; + }; + }; + + napa_intn_wol_sig: napa_intn_wol_sig { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + input-enable; + bias-disable; + }; + }; + }; +}; From 2a06144f57861a92a76e380b73f19fb66abb63fb Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Mon, 13 Apr 2026 09:41:19 +0530 Subject: [PATCH 0617/1330] PEDNING: arm64: dts: qcom: qcs6490-rb3gen2: fix root node overlay for phy-vreg The staging overlay used a bare "/ {" root node block to define the qep_vreg and aqr_vreg fixed regulators. In a DT overlay, a bare "/ {" creates a new root fragment that is not merged into the base tree's root node; as a result the regulator nodes are never instantiated and the tc956x driver cannot resolve the phy-supply phandle, leading to a failed MDIO probe: tc956x_pci-eth 0001:05:00.1: No PHY found Replace "/ {" with the overlay-correct "&{/} {" syntax so that the fragment is properly applied as an amendment to the base device-tree root node. This ensures the regulator nodes are present at boot and the PHY powers up correctly. Fixes: 00ba37e0f45d ("PENDING: arm64: dts: qcom: rb3gen2: add overlay for QPS615 ethernet") Signed-off-by: Mohd Ayaan Anwar (cherry picked from commit cd6b5bd29ed731447ac9208c10a1210c1a877d39) --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso index 79f9c055c9776..6c112224f0ce9 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso @@ -9,7 +9,7 @@ #include #include -/ { +&{/} { qep_vreg: qep_vreg { compatible = "regulator-fixed"; regulator-name = "qep_vreg"; From 194f8ac2df821a523d486581608283ba47d22c41 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 8 Apr 2026 16:36:42 +0800 Subject: [PATCH 0618/1330] PENDING: arm64: qcom: dts: talos: add TGU device in staging dtso Add TGU device for supporting IPCB feature in staging dtso file. Signed-off-by: Jie Gan (cherry picked from commit af180658a1b0f0d939bda0b93aea7cf0843d8611) --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/talos-staging.dtso | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 71d564768c4a5..bca290d1fbc56 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -505,3 +505,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3-camx.dtb talos-evk-camx-dtbs := talos-evk.dtb talos-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camx.dtb + +dtb-$(CONFIG_ARCH_QCOM) += talos-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/talos-staging.dtso b/arch/arm64/boot/dts/qcom/talos-staging.dtso new file mode 100644 index 0000000000000..04602073418d4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-staging.dtso @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Talos staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +&soc { + tgu@6b0c000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x6b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; From a193514eea9c323ab61eb5669eeb74a31e30479a Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 14:46:05 +0800 Subject: [PATCH 0619/1330] PENDING: arm64: dts: qcom: lemans: add TGU device in staging dtso Add TGU devices for supporting IPCB feature in staging dtso file. Signed-off-by: Jie Gan (cherry picked from commit 8e1e5d78d03ce789177df30d3b68e5554483b39b) --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/lemans-staging.dtso | 27 ++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index bca290d1fbc56..bdbf734fe6b24 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -461,6 +461,8 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo +dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo + monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-staging.dtso b/arch/arm64/boot/dts/qcom/lemans-staging.dtso new file mode 100644 index 0000000000000..ad919bfb6b19a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-staging.dtso @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Lemans staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +&soc { + tgu@4b0e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x4b0e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@4b0f000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x4b0f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; From 1e6d6f05561e4e9f5d814589d6a565859fe2ee2c Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 14:59:42 +0800 Subject: [PATCH 0620/1330] PENDING: arm64: dts: qcom: monaco: add TGU device in staging dtso Add TGU devices for supporting IPCB feature in staging dtso file. Signed-off-by: Jie Gan (cherry picked from commit 39ba536c16047b37ee7524ccf9ee664b370f341c) --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/monaco-staging.dtso | 27 ++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index bdbf734fe6b24..143181fbe620c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -473,6 +473,8 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo + qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-staging.dtso b/arch/arm64/boot/dts/qcom/monaco-staging.dtso new file mode 100644 index 0000000000000..fc44741b8caab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-staging.dtso @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Monaco staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +&soc { + tgu@4b0e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x4b0e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@4b0f000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x4b0f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; From cda85abb331f902c813a9ef6d66a761f4edfc418 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 15:11:57 +0800 Subject: [PATCH 0621/1330] PENDING: arm64: dts: qcom: kodiak: add TGU device in staging dtso Add TGU device for supporting IPCB feature in staging dtso file. Signed-off-by: Jie Gan (cherry picked from commit c536706c5d2521ecf3d36cede2b9bc83306ac95b) --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/kodiak-staging.dtso | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kodiak-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 143181fbe620c..78c0cdffbdb1f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -511,3 +511,5 @@ talos-evk-camx-dtbs := talos-evk.dtb talos-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camx.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-staging.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += kodiak-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/kodiak-staging.dtso b/arch/arm64/boot/dts/qcom/kodiak-staging.dtso new file mode 100644 index 0000000000000..1d4c6d7d39dd0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kodiak-staging.dtso @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Kodiak staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +&soc { + tgu@6b0e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x6b0e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; From 7f220126b20f393ff61bd4368e0d5933ade3170f Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 22 Apr 2026 16:49:21 +0530 Subject: [PATCH 0622/1330] QCLINUX: arm64: dts: qcom: talos-evk: Switch to interrupt-cells 4 Update Talos EVK camera DT nodes to use 4-cell interrupt specifiers, aligning with upstream Talos GIC changes required for PPI interrupt partitioning. This Change is required to remain compliant with the updated GIC binding, even for SPI-based camera interrupts. Link: https://lore.kernel.org/all/20260108092542.1371-2-yuanjie.yang@oss.qualcomm.com/ Signed-off-by: Chandan Kumar Jha (cherry picked from commit 23ab4dc46ced53978b3ffbf9567226f070d5a5ed) --- arch/arm64/boot/dts/qcom/talos-camera.dtsi | 32 +++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos-camera.dtsi b/arch/arm64/boot/dts/qcom/talos-camera.dtsi index e0f59fb00a5fc..7d6f1268fa396 100644 --- a/arch/arm64/boot/dts/qcom/talos-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-camera.dtsi @@ -15,7 +15,7 @@ <0x0 0xac18000 0x0 0x3000>; reg-names = "icp_qgic", "icp_sierra", "icp_csr"; reg-cam-base = <0x00000 0x10000 0x18000>; - interrupts = ; + interrupts = ; interrupt-names = "a5"; power-domains = <&camcc TITAN_TOP_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -92,7 +92,7 @@ <0x0 0xac42000 0x0 0x5000>; reg-names = "cam_cpas_top", "cam_camnoc"; reg-cam-base = <0x40000 0x42000>; - interrupts = ; + interrupts = ; interrupt-names = "cpas_camnoc"; camnoc-axi-min-ib-bw = <3000000000>; power-domains = <&camcc TITAN_TOP_GDSC>; @@ -505,7 +505,7 @@ reg = <0x0 0xac48000 0x0 0x1000>; reg-names = "cpas-cdm"; reg-cam-base = <0x48000>; - interrupts = ; + interrupts = ; interrupt-names = "cpas-cdm"; power-domains = <&camcc TITAN_TOP_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -545,7 +545,7 @@ reg = <0x0 0xac4a000 0x0 0x4000>; reg-names = "cci"; reg-cam-base = <0x4a000>; - interrupts = ; + interrupts = ; interrupt-names = "CCI"; operating-points-v2 = <&cci_opp_table>; power-domains = <&camcc TITAN_TOP_GDSC>; @@ -642,7 +642,7 @@ reg = <0x0 0xac4e000 0x0 0x4000>; reg-names = "jpege_hw"; reg-cam-base = <0x4e000>; - interrupts = ; + interrupts = ; interrupt-names = "jpeg"; power-domains = <&camcc TITAN_TOP_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -681,7 +681,7 @@ reg = <0x0 0xac52000 0x0 0x4000>; reg-names = "jpegdma_hw"; reg-cam-base = <0x52000>; - interrupts = ; + interrupts = ; interrupt-names = "jpegdma"; power-domains = <&camcc TITAN_TOP_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -721,7 +721,7 @@ reg-names = "csiphy"; operating-points-v2 = <&csiphy0_opp_table>; reg-cam-base = <0x65000>; - interrupts = ; + interrupts = ; interrupt-names = "CSIPHY0"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&vreg_l11a>; @@ -770,7 +770,7 @@ reg-names = "csiphy"; operating-points-v2 = <&csiphy1_opp_table>; reg-cam-base = <0x66000>; - interrupts = ; + interrupts = ; interrupt-names = "CSIPHY1"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&vreg_l11a>; @@ -819,7 +819,7 @@ reg-names = "csiphy"; operating-points-v2 = <&csiphy2_opp_table>; reg-cam-base = <0x67000>; - interrupts = ; + interrupts = ; interrupt-names = "CSIPHY2"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&vreg_l11a>; @@ -867,7 +867,7 @@ reg = <0x0 0xac6b000 0x0 0xa00>; reg-names = "lrme"; reg-cam-base = <0x6b000>; - interrupts = ; + interrupts = ; interrupt-names = "lrme"; power-domains = <&camcc TITAN_TOP_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -1056,7 +1056,7 @@ <0x0 0xac42000 0x0 0x5000>; reg-names = "ife0", "cam_camnoc"; reg-cam-base = <0xaf000 0x42000>; - interrupts = ; + interrupts = ; interrupt-names = "ife0"; power-domains = <&camcc IFE_0_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -1128,7 +1128,7 @@ reg = <0x0 0xacb3000 0x0 0x1000>; reg-names = "csid0"; reg-cam-base = <0xb3000>; - interrupts = ; + interrupts = ; interrupt-names = "csid0"; power-domains = <&camcc IFE_0_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -1211,7 +1211,7 @@ <0x0 0xac42000 0x0 0x5000>; reg-names = "ife1", "cam_camnoc"; reg-cam-base = <0xb6000 0x42000>; - interrupts = ; + interrupts = ; interrupt-names = "ife1"; power-domains = <&camcc IFE_1_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -1283,7 +1283,7 @@ reg = <0x0 0xacba000 0x0 0x1000>; reg-names = "csid1"; reg-cam-base = <0xba000>; - interrupts = ; + interrupts = ; interrupt-names = "csid1"; power-domains = <&camcc IFE_1_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -1365,7 +1365,7 @@ reg = <0x0 0xacc4000 0x0 0x4000>; reg-names = "ife-lite0"; reg-cam-base = <0xc4000>; - interrupts = ; + interrupts = ; interrupt-names = "ife-lite0"; power-domains = <&camcc TITAN_TOP_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, @@ -1432,7 +1432,7 @@ reg = <0x0 0xacc8000 0x0 0x1000>; reg-names = "csid-lite0"; reg-cam-base = <0xc8000>; - interrupts = ; + interrupts = ; interrupt-names = "csid-lite0"; power-domains = <&camcc TITAN_TOP_GDSC>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, From 0f522583344e6b975d98c931816578edf6085e7f Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Sun, 19 Apr 2026 20:35:15 +0530 Subject: [PATCH 0623/1330] PENDING: arm64: dts: qcom: rb3gen2-industrial-mezzanine: add overlay for QPS615 Add an overlay devicetree to enable Rb3Gen2 industrial board's 4 ethernet ports provided by two QPS615 PCIe Ethernet switches. Signed-off-by: Mohd Ayaan Anwar (cherry picked from commit f88c2dedeaf12861c77ec7aa35588fd9c5ac9a2e) --- arch/arm64/boot/dts/qcom/Makefile | 2 + ...-rb3gen2-industrial-mezzanine-staging.dtso | 119 ++++++++++++++++++ 2 files changed, 121 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 78c0cdffbdb1f..8c62544fcfc88 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -486,6 +486,8 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-staging.dtbo +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine-staging.dtbo + qcs8300-ride-camx-dtbs:= qcs8300-ride.dtb qcs8300-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-staging.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-staging.dtso new file mode 100644 index 0000000000000..edb284558b5a6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-staging.dtso @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + qep_vreg: qep_vreg { + compatible = "regulator-fixed"; + regulator-name = "qep_vreg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pm7325_gpios 8 0>; + enable-active-high; + }; + + aqr_vreg: aqr_vreg { + compatible = "regulator-fixed"; + regulator-name = "aqr_vreg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pm7250b_gpios 4 0>; + enable-active-high; + }; +}; + +&pcie1_port0 { + pcie@0,0 { + pcie@3,0 { + qps615: pci@0,0 { + compatible = "pci1179,0220"; + interrupts-extended = <&tlmm 141 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + pinctrl-names = "default"; + pinctrl-0 = <&aqr_intn_wol_sig>; + phy-reset-gpios = <&qps615 0 GPIO_ACTIVE_LOW>; + phy-supply = <&aqr_vreg>; + reset-deassert-us = <221000>; + + gpio-controller; + #gpio-cells = <2>; + }; + + pci@0,1 { + compatible = "pci1179,0220"; + interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + pinctrl-names = "default"; + pinctrl-0 = <&napa_intn_wol_sig>; + phy-reset-gpios = <&qps615 1 GPIO_ACTIVE_LOW>; + phy-supply = <&qep_vreg>; + reset-deassert-us = <20000>; + }; + }; + }; +}; + +&pcie0_port { + pcie@0,0 { + pcie@3,0 { + pci@0,0 { + interrupts-extended = <&tlmm 136 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + pinctrl-names = "default"; + pinctrl-0 = <&rtl_rc0_intn_wol_sig>; + phy-mode = "sgmii"; + phy-reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>; + reset-deassert-us = <75000>; + }; + + pci@0,1 { + interrupts-extended = <&tlmm 142 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + pinctrl-names = "default"; + pinctrl-0 = <&napa_rc0_intn_wol_sig>; + phy-reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; + phy-supply = <&qep_vreg>; + reset-deassert-us = <20000>; + }; + }; + }; +}; + +&tlmm { + qps615_intn_wol { + aqr_intn_wol_sig: aqr_intn_wol_sig { + pins = "gpio141"; + function = "gpio"; + input-enable; + bias-disable; + }; + + napa_intn_wol_sig: napa_intn_wol_sig { + pins = "gpio101"; + function = "gpio"; + input-enable; + bias-disable; + }; + + rtl_rc0_intn_wol_sig: rtl_rc0_intn_wol_sig { + pins = "gpio136"; + function = "gpio"; + input-enable; + bias-disable; + }; + + napa_rc0_intn_wol_sig: napa_rc0_intn_wol_sig { + pins = "gpio142"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; +}; From ab85b3ba653e202cda6e99f744ed7c4d9225bb13 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Nandam Date: Thu, 2 Apr 2026 17:24:11 +0530 Subject: [PATCH 0624/1330] FROMLIST: pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Link: https://lore.kernel.org/all/20260413122233.375945-2-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam (cherry picked from commit 63415f5ae006de634d8969d00e441d375a0202d5) --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 36 +++++++++++++------ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 2 ++ .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 5 +++ 3 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 76aed32962794..6d50e06ef68a8 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -14,15 +14,16 @@ #include #include +#include #include #include "../pinctrl-utils.h" #include "pinctrl-lpass-lpi.h" +#include #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 struct lpi_pinctrl { struct device *dev; @@ -31,7 +32,6 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); @@ -480,9 +480,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data = data; pctrl->dev = &pdev->dev; - pctrl->clks[0].id = "core"; - pctrl->clks[1].id = "audio"; - pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -495,13 +492,17 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } - ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret = devm_pm_clk_create(dev); if (ret) return ret; - ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); - if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + ret = of_pm_clk_add_clks(dev); + if (ret < 0) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; @@ -539,20 +540,33 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return 0; err_pinctrl: + pm_runtime_disable(dev); mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); return ret; } EXPORT_SYMBOL_GPL(lpi_pinctrl_probe); +int lpi_pinctrl_runtime_suspend(struct device *dev) +{ + return pm_clk_suspend(dev); +} +EXPORT_SYMBOL_GPL(lpi_pinctrl_runtime_suspend); + +int lpi_pinctrl_runtime_resume(struct device *dev) +{ + return pm_clk_resume(dev); +} +EXPORT_SYMBOL_GPL(lpi_pinctrl_runtime_resume); + void lpi_pinctrl_remove(struct platform_device *pdev) { struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); int i; + pm_runtime_disable(pctrl->dev); + mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); for (i = 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index f483684928613..ae94ef48da8ba 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -107,5 +107,7 @@ struct lpi_pinctrl_variant_data { int lpi_pinctrl_probe(struct platform_device *pdev); void lpi_pinctrl_remove(struct platform_device *pdev); +int lpi_pinctrl_runtime_suspend(struct device *dev); +int lpi_pinctrl_runtime_resume(struct device *dev); #endif /*__PINCTRL_LPASS_LPI_H__*/ diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f410311a8f..2d955643d2f00 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -139,10 +139,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(lpi_pinctrl_runtime_suspend, lpi_pinctrl_runtime_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-sc7280-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, From 5bdcc05e4c181ccdd74a4dcc1ce25e83b78da538 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Nandam Date: Fri, 10 Apr 2026 22:05:00 +0530 Subject: [PATCH 0625/1330] FROMLIST: pinctrl: qcom: lpass-lpi: Fix GPIO register access helper return types The LPI GPIO register access helpers previously returned the value from ioread32(), even though their return type was int. This mixes data return with status and is inconsistent with common kernel helper conventions. Rework lpi_gpio_read() and lpi_gpio_write() to return an int status and use output parameters to pass register values. Update all callers to match the new helper interface. This change fixes the helper API and resulting call sites without intending any functional change in GPIO or pinctrl behavior. Link: https://lore.kernel.org/all/20260413122233.375945-3-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam (cherry picked from commit 1dcf8dab60c284ce5ad0a78cf602880478714fd5) --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 66 +++++++++++++++++------- 1 file changed, 47 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 6d50e06ef68a8..d108e7321483a 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -39,22 +39,26 @@ struct lpi_pinctrl { }; static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr) + unsigned int addr, u32 *val) { u32 pin_offset; + int ret; if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset = state->data->groups[pin].pin_offset; else pin_offset = LPI_TLMM_REG_OFFSET * pin; - return ioread32(state->tlmm_base + pin_offset + addr); + *val = ioread32(state->tlmm_base + pin_offset + addr); + + return 0; } static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { u32 pin_offset; + int ret; if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset = state->data->groups[pin].pin_offset; @@ -107,7 +111,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, { struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct lpi_pingroup *g = &pctrl->data->groups[group]; - u32 val; + u32 val, io_val; + int ret; int i, pin = g->pin; for (i = 0; i < g->nfuncs; i++) { @@ -119,7 +124,9 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, return -EINVAL; mutex_lock(&pctrl->lock); - val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + ret = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val); + if (ret) + goto out_unlock; /* * If this is the first time muxing to GPIO and the direction is @@ -129,24 +136,28 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, */ if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && !test_and_set_bit(group, pctrl->ever_gpio)) { - u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + ret = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); + if (ret) + goto out_unlock; if (io_val & LPI_GPIO_VALUE_IN_MASK) { if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val | LPI_GPIO_VALUE_OUT_MASK); + ret = lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); } else { if (io_val & LPI_GPIO_VALUE_OUT_MASK) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val & ~LPI_GPIO_VALUE_OUT_MASK); + ret = lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); } } u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); - lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + ret = lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + +out_unlock: mutex_unlock(&pctrl->lock); - return 0; + return ret; } static const struct pinmux_ops lpi_gpio_pinmux_ops = { @@ -165,8 +176,11 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, int is_out; int pull; u32 ctl_reg; + int ret; - ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); + ret = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) + return ret; is_out = ctl_reg & LPI_GPIO_OE_MASK; pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); @@ -293,17 +307,22 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, } mutex_lock(&pctrl->lock); - val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + ret = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val); + if (ret) { + mutex_unlock(&pctrl->lock); + goto out_unlock; + } u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), LPI_GPIO_OUT_STRENGTH_MASK); u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); + ret = lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); - return 0; +out_unlock: + mutex_unlock(&pctrl->lock); + return ret; } static const struct pinconf_ops lpi_gpio_pinconf_ops = { @@ -352,9 +371,13 @@ static int lpi_gpio_direction_output(struct gpio_chip *chip, static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) { struct lpi_pinctrl *state = gpiochip_get_data(chip); + u32 val; + int ret; - return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & - LPI_GPIO_VALUE_IN_MASK; + ret = lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); + if (ret) + return ret; + return val & LPI_GPIO_VALUE_IN_MASK; } static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) @@ -387,6 +410,7 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, int drive; int pull; u32 ctl_reg; + int ret; static const char * const pulls[] = { "no pull", @@ -397,7 +421,11 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, pctldev = pctldev ? : state->ctrl; pindesc = pctldev->desc->pins[offset]; - ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + ret = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) { + seq_printf(s, " %-8s: ", pindesc.name, ret); + return; + } is_out = ctl_reg & LPI_GPIO_OE_MASK; func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); From 4ad07e17fe27f8fb7911dfec5d1b44c7bc24dde2 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Nandam Date: Fri, 10 Apr 2026 22:23:11 +0530 Subject: [PATCH 0626/1330] FROMLIST: pinctrl: qcom: lpass-lpi: Resume clocks for GPIO access Ensure the LPI pinctrl device clocks are runtime resumed before accessing GPIO registers and autosuspended after the access completes. Guard GPIO register read and write helpers with synchronous runtime PM calls so the device is active during MMIO operations. Link: https://lore.kernel.org/all/20260413122233.375945-4-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam (cherry picked from commit 6315b0f585be746932fef2f63f7144664b9ee021) --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index d108e7321483a..4275f27343c10 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -49,8 +49,17 @@ static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, else pin_offset = LPI_TLMM_REG_OFFSET * pin; + ret = pm_runtime_get_sync(state->dev); + if (ret < 0) { + pm_runtime_put_noidle(state->dev); + return ret; + } + *val = ioread32(state->tlmm_base + pin_offset + addr); + pm_runtime_mark_last_busy(state->dev); + pm_runtime_put_autosuspend(state->dev); + return 0; } @@ -65,8 +74,17 @@ static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, else pin_offset = LPI_TLMM_REG_OFFSET * pin; + ret = pm_runtime_get_sync(state->dev); + if (ret < 0) { + pm_runtime_put_noidle(state->dev); + return ret; + } + iowrite32(val, state->tlmm_base + pin_offset + addr); + pm_runtime_mark_last_busy(state->dev); + pm_runtime_put_autosuspend(state->dev); + return 0; } From 6bb701f68f343ed8985dd7cec62c2b08f005c060 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Nandam Date: Thu, 12 Mar 2026 19:53:06 +0530 Subject: [PATCH 0627/1330] FROMLIST: ASoC: codecs: lpass-wsa-macro: Switch to PM clock framework for runtime PM Convert the LPASS WSA macro codec driver to use the PM clock framework for runtime power management. The driver now relies on pm_clk helpers and runtime PM instead of manually enabling and disabling macro, dcodec, mclk, npl, and fsgen clocks. Runtime suspend and resume handling is delegated to the PM core via pm_clk_suspend() and pm_clk_resume(), while existing runtime PM callbacks continue to manage regcache state. This ensures clocks are enabled only when the WSA macro is active, improves power efficiency on LPASS platforms supporting LPI/island modes, and aligns the driver with common ASoC runtime PM patterns used across Qualcomm LPASS codec drivers. Link: https://lore.kernel.org/all/20260413121824.375473-2-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam (cherry picked from commit a13b7731711ba419aea98b5f02207b02dc2726e1) --- sound/soc/codecs/lpass-wsa-macro.c | 118 +++++++++-------------------- 1 file changed, 37 insertions(+), 81 deletions(-) diff --git a/sound/soc/codecs/lpass-wsa-macro.c b/sound/soc/codecs/lpass-wsa-macro.c index 5ad0448af649d..6aa6c4d959c04 100644 --- a/sound/soc/codecs/lpass-wsa-macro.c +++ b/sound/soc/codecs/lpass-wsa-macro.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "lpass-macro-common.h" @@ -2529,15 +2530,15 @@ static const struct snd_soc_dapm_route wsa_audio_map[] = { static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) { struct regmap *regmap = wsa->regmap; + int ret; - if (enable) { - int ret; + ret = pm_runtime_get_sync(wsa->dev); + if (ret < 0) { + pm_runtime_put_noidle(wsa->dev); + return ret; + } - ret = clk_prepare_enable(wsa->mclk); - if (ret) { - dev_err(wsa->dev, "failed to enable mclk\n"); - return ret; - } + if (enable) { wsa_macro_mclk_enable(wsa, true); regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, @@ -2548,9 +2549,10 @@ static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, CDC_WSA_SWR_CLK_EN_MASK, 0); wsa_macro_mclk_enable(wsa, false); - clk_disable_unprepare(wsa->mclk); } + pm_runtime_mark_last_busy(wsa->dev); + pm_runtime_put_autosuspend(wsa->dev); return 0; } @@ -2774,25 +2776,23 @@ static int wsa_macro_probe(struct platform_device *pdev) clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ); clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ); - ret = clk_prepare_enable(wsa->macro); + ret = devm_pm_clk_create(dev); if (ret) - goto err; + return ret; - ret = clk_prepare_enable(wsa->dcodec); - if (ret) - goto err_dcodec; + ret = of_pm_clk_add_clks(dev); + if (ret < 0) + return ret; - ret = clk_prepare_enable(wsa->mclk); - if (ret) - goto err_mclk; + pm_runtime_set_autosuspend_delay(dev, 3000); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); - ret = clk_prepare_enable(wsa->npl); - if (ret) - goto err_npl; - ret = clk_prepare_enable(wsa->fsgen); - if (ret) - goto err_fsgen; + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) { + goto err_rpm_disable; + } /* reset swr ip */ regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, @@ -2809,44 +2809,26 @@ static int wsa_macro_probe(struct platform_device *pdev) wsa_macro_dai, ARRAY_SIZE(wsa_macro_dai)); if (ret) - goto err_clkout; - - pm_runtime_set_autosuspend_delay(dev, 3000); - pm_runtime_use_autosuspend(dev); - pm_runtime_mark_last_busy(dev); - pm_runtime_set_active(dev); - pm_runtime_enable(dev); + goto err_rpm_put; ret = wsa_macro_register_mclk_output(wsa); if (ret) - goto err_clkout; + goto err_rpm_put; - return 0; + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); -err_clkout: - clk_disable_unprepare(wsa->fsgen); -err_fsgen: - clk_disable_unprepare(wsa->npl); -err_npl: - clk_disable_unprepare(wsa->mclk); -err_mclk: - clk_disable_unprepare(wsa->dcodec); -err_dcodec: - clk_disable_unprepare(wsa->macro); -err: + return 0; +err_rpm_put: + pm_runtime_put_noidle(dev); +err_rpm_disable: + pm_runtime_disable(dev); return ret; - } static void wsa_macro_remove(struct platform_device *pdev) { - struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev); - - clk_disable_unprepare(wsa->macro); - clk_disable_unprepare(wsa->dcodec); - clk_disable_unprepare(wsa->mclk); - clk_disable_unprepare(wsa->npl); - clk_disable_unprepare(wsa->fsgen); + pm_runtime_disable(&pdev->dev); } static int wsa_macro_runtime_suspend(struct device *dev) @@ -2856,11 +2838,7 @@ static int wsa_macro_runtime_suspend(struct device *dev) regcache_cache_only(wsa->regmap, true); regcache_mark_dirty(wsa->regmap); - clk_disable_unprepare(wsa->fsgen); - clk_disable_unprepare(wsa->npl); - clk_disable_unprepare(wsa->mclk); - - return 0; + return pm_clk_suspend(dev); } static int wsa_macro_runtime_resume(struct device *dev) @@ -2868,34 +2846,12 @@ static int wsa_macro_runtime_resume(struct device *dev) struct wsa_macro *wsa = dev_get_drvdata(dev); int ret; - ret = clk_prepare_enable(wsa->mclk); - if (ret) { - dev_err(dev, "unable to prepare mclk\n"); - return ret; - } - - ret = clk_prepare_enable(wsa->npl); - if (ret) { - dev_err(dev, "unable to prepare mclkx2\n"); - goto err_npl; - } - - ret = clk_prepare_enable(wsa->fsgen); - if (ret) { - dev_err(dev, "unable to prepare fsgen\n"); - goto err_fsgen; - } - regcache_cache_only(wsa->regmap, false); - regcache_sync(wsa->regmap); - - return 0; -err_fsgen: - clk_disable_unprepare(wsa->npl); -err_npl: - clk_disable_unprepare(wsa->mclk); + ret = pm_clk_resume(dev); + if (ret) + return ret; - return ret; + return regcache_sync(wsa->regmap); } static const struct dev_pm_ops wsa_macro_pm_ops = { From 102bc10b86246ae38ec9f2f66c478d4b76ee5c10 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Nandam Date: Thu, 12 Mar 2026 19:46:37 +0530 Subject: [PATCH 0628/1330] FROMLIST: ASoC: codecs: lpass-va-macro: Switch to PM clock framework for runtime PM Convert the LPASS VA macro codec driver to use the PM clock framework for runtime power management. The driver now relies on pm_clk helpers and runtime PM instead of manually enabling and disabling macro, dcodec, mclk, and npl clocks. All clock control during runtime suspend and resume is delegated to the PM core via pm_clk_suspend() and pm_clk_resume(). This change ensures clocks are only enabled when the VA macro is active, improves power efficiency on LPASS platforms supporting LPI/island modes, and aligns the driver with common ASoC runtime PM patterns used across Qualcomm LPASS codec drivers. Link: https://lore.kernel.org/all/20260413121824.375473-3-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam (cherry picked from commit 569c784877f86c008a0845d2515936e35f21cd90) --- sound/soc/codecs/lpass-va-macro.c | 120 ++++++++++++++---------------- 1 file changed, 54 insertions(+), 66 deletions(-) diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c index 528d5b167ecff..b909f8befa10e 100644 --- a/sound/soc/codecs/lpass-va-macro.c +++ b/sound/soc/codecs/lpass-va-macro.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1348,18 +1349,22 @@ static int fsgen_gate_enable(struct clk_hw *hw) struct regmap *regmap = va->regmap; int ret; - if (va->has_swr_master) { - ret = clk_prepare_enable(va->mclk); - if (ret) - return ret; + ret = pm_runtime_get_sync(va->dev); + if (ret < 0) { + pm_runtime_put_noidle(va->dev); + return ret; } ret = va_macro_mclk_enable(va, true); + if (ret) { + pm_runtime_put_noidle(va->dev); + return ret; + } if (va->has_swr_master) regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE); - return ret; + return 0; } static void fsgen_gate_disable(struct clk_hw *hw) @@ -1372,8 +1377,24 @@ static void fsgen_gate_disable(struct clk_hw *hw) CDC_VA_SWR_CLK_EN_MASK, 0x0); va_macro_mclk_enable(va, false); - if (va->has_swr_master) - clk_disable_unprepare(va->mclk); + + pm_runtime_mark_last_busy(va->dev); + pm_runtime_put_autosuspend(va->dev); +} + +static int va_macro_setup_pm_clocks(struct device *dev, struct va_macro *va) +{ + int ret; + + ret = devm_pm_clk_create(dev); + if (ret) + return ret; + + ret = of_pm_clk_add_clks(dev); + if (ret < 0) + return ret; + + return 0; } static int fsgen_gate_is_enabled(struct clk_hw *hw) @@ -1534,6 +1555,7 @@ static int va_macro_probe(struct platform_device *pdev) void __iomem *base; u32 sample_rate = 0; int ret; + int rpm_ret; va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL); if (!va) @@ -1601,22 +1623,18 @@ static int va_macro_probe(struct platform_device *pdev) clk_set_rate(va->npl, 2 * VA_MACRO_MCLK_FREQ); } - ret = clk_prepare_enable(va->macro); - if (ret) - goto err; - - ret = clk_prepare_enable(va->dcodec); + ret = va_macro_setup_pm_clocks(dev, va); if (ret) - goto err_dcodec; + goto err_rpm_disable; - ret = clk_prepare_enable(va->mclk); - if (ret) - goto err_mclk; + pm_runtime_set_autosuspend_delay(dev, 3000); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); - if (va->has_npl_clk) { - ret = clk_prepare_enable(va->npl); - if (ret) - goto err_npl; + rpm_ret = pm_runtime_resume_and_get(dev); + if (rpm_ret < 0) { + ret = rpm_ret; + goto err_rpm_disable; } /** @@ -1629,7 +1647,7 @@ static int va_macro_probe(struct platform_device *pdev) /* read version from register */ ret = va_macro_set_lpass_codec_version(va); if (ret) - goto err_clkout; + goto err_rpm_put; } if (va->has_swr_master) { @@ -1659,35 +1677,27 @@ static int va_macro_probe(struct platform_device *pdev) va_macro_dais, ARRAY_SIZE(va_macro_dais)); if (ret) - goto err_clkout; - - pm_runtime_set_autosuspend_delay(dev, 3000); - pm_runtime_use_autosuspend(dev); - pm_runtime_mark_last_busy(dev); - pm_runtime_set_active(dev); - pm_runtime_enable(dev); + goto err_rpm_put; ret = va_macro_register_fsgen_output(va); if (ret) - goto err_clkout; + goto err_rpm_put; va->fsgen = devm_clk_hw_get_clk(dev, &va->hw, "fsgen"); if (IS_ERR(va->fsgen)) { ret = PTR_ERR(va->fsgen); - goto err_clkout; + goto err_rpm_put; } + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + return 0; -err_clkout: - if (va->has_npl_clk) - clk_disable_unprepare(va->npl); -err_npl: - clk_disable_unprepare(va->mclk); -err_mclk: - clk_disable_unprepare(va->dcodec); -err_dcodec: - clk_disable_unprepare(va->macro); +err_rpm_put: + pm_runtime_put_noidle(dev); +err_rpm_disable: + pm_runtime_disable(dev); err: lpass_macro_pds_exit(va->pds); @@ -1698,12 +1708,7 @@ static void va_macro_remove(struct platform_device *pdev) { struct va_macro *va = dev_get_drvdata(&pdev->dev); - if (va->has_npl_clk) - clk_disable_unprepare(va->npl); - - clk_disable_unprepare(va->mclk); - clk_disable_unprepare(va->dcodec); - clk_disable_unprepare(va->macro); + pm_runtime_disable(&pdev->dev); lpass_macro_pds_exit(va->pds); } @@ -1715,12 +1720,7 @@ static int va_macro_runtime_suspend(struct device *dev) regcache_cache_only(va->regmap, true); regcache_mark_dirty(va->regmap); - if (va->has_npl_clk) - clk_disable_unprepare(va->npl); - - clk_disable_unprepare(va->mclk); - - return 0; + return pm_clk_suspend(dev); } static int va_macro_runtime_resume(struct device *dev) @@ -1728,25 +1728,13 @@ static int va_macro_runtime_resume(struct device *dev) struct va_macro *va = dev_get_drvdata(dev); int ret; - ret = clk_prepare_enable(va->mclk); - if (ret) { - dev_err(va->dev, "unable to prepare mclk\n"); + ret = pm_clk_resume(dev); + if (ret) return ret; - } - - if (va->has_npl_clk) { - ret = clk_prepare_enable(va->npl); - if (ret) { - clk_disable_unprepare(va->mclk); - dev_err(va->dev, "unable to prepare npl\n"); - return ret; - } - } regcache_cache_only(va->regmap, false); - regcache_sync(va->regmap); - return 0; + return regcache_sync(va->regmap); } From 2a30166a94975c116a7cdd6c14f49dc94ba712b0 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Nandam Date: Fri, 10 Apr 2026 17:01:17 +0530 Subject: [PATCH 0629/1330] FROMLIST: ASoC: codecs: lpass-wsa-macro: Guard optional NPL clock rate programming The NPL clock is only present on some platforms. When it is absent, wsa->npl remains NULL, but the driver unconditionally programs its rate. Guard clk_set_rate() for the NPL clock so platforms without NPL do not attempt to access it. No functional change on platforms that provide the NPL clock. Link: https://lore.kernel.org/all/20260413121824.375473-4-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam (cherry picked from commit 3d44b19ae11af7f3b605321f1b44eea949eb9b1d) --- sound/soc/codecs/lpass-wsa-macro.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/lpass-wsa-macro.c b/sound/soc/codecs/lpass-wsa-macro.c index 6aa6c4d959c04..8c8c50a63f4e2 100644 --- a/sound/soc/codecs/lpass-wsa-macro.c +++ b/sound/soc/codecs/lpass-wsa-macro.c @@ -2774,7 +2774,8 @@ static int wsa_macro_probe(struct platform_device *pdev) /* set MCLK and NPL rates */ clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ); - clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ); + if (wsa->npl) + clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ); ret = devm_pm_clk_create(dev); if (ret) From 585b173af95070a0a2d9d5a70ad6f83e01425fa1 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Nandam Date: Mon, 20 Apr 2026 16:07:24 +0530 Subject: [PATCH 0630/1330] FROMLIST: pinctrl: qcom: lpass-lpi: Enable runtime PM hooks on remaining SoCs The LPASS LPI core was switched to the PM clock framework and runtime PM, but only the sc7280 variant driver wired runtime PM callbacks. Hook up runtime PM callbacks for the remaining LPASS LPI variant drivers so all SoCs using the common core get consistent pm_clk based clock handling: - sc8280xp - sm4250 - sm6115 - sm8250 - sm8450 - sm8550 - sm8650 This is a mechanical per-variant driver update that relies on the same generic PM clock flow (of_pm_clk_add_clks() + pm_clk_suspend/ pm_clk_resume()) and DT-provided clocks. Runtime behavior was validated on Kodiak (sc7280). Link: https://lore.kernel.org/all/20260420123135.350446-3-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam (cherry picked from commit cab3357f188207843476df34b2a294a9009efa5b) --- drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 11 +++++++++-- 7 files changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index 0e839b6aaaf4b..1a61316c8c473 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include "pinctrl-lpass-lpi.h" @@ -173,10 +175,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sc8280xp-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sc8280xp-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c index c0e178be9cfc3..75bafa62426a2 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include "pinctrl-lpass-lpi.h" @@ -221,10 +223,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-sm4250-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c index b7d9186861a2f..05435ea6e17a6 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include "pinctrl-lpass-lpi.h" @@ -141,10 +143,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-sm6115-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c index c27452eece3e6..656f22da7dde3 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include "pinctrl-lpass-lpi.h" @@ -134,10 +136,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8250-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c index 439f6541622e9..a79f99ec6df9d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include "pinctrl-lpass-lpi.h" @@ -202,10 +204,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8450-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c index 73065919c8c26..9037ef0020dac 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include "pinctrl-lpass-lpi.h" @@ -210,10 +212,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8550-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c index f9fcedf5a65d7..513ddc99dd378 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include "pinctrl-lpass-lpi.h" @@ -217,10 +219,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8650-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8650-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, From 519226910759bb549a10983b50e1608390773b40 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 25 Mar 2026 21:47:57 +0000 Subject: [PATCH 0631/1330] FROMLIST: phy: dphy: Add lane_positions to DPHY config struct Add lane_positions to the DPHY configuration struct. This data-field represents the physical positions of the data-lanes indexed by lane number. Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-1-c6df5599284a@linaro.org/ Signed-off-by: Bryan O'Donoghue (cherry picked from commit 12d66c1dbecb8ba1d5e8facfeb4837d3daf04bed) --- include/linux/phy/phy-mipi-dphy.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index 1ac128d78dfeb..c7eb11c41d7ec 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -6,6 +6,8 @@ #ifndef __PHY_MIPI_DPHY_H_ #define __PHY_MIPI_DPHY_H_ +#define PHY_MIPI_DPHY_MAX_DATA_LANES 4 + /** * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set * @@ -269,10 +271,19 @@ struct phy_configure_opts_mipi_dphy { /** * @lanes: * - * Number of active, consecutive, data lanes, starting from - * lane 0, used for the transmissions. + * Number of active data lanes used for the transmission. + * When @lane_positions is not populated, lanes are consecutive + * starting from lane 0. */ unsigned char lanes; + + /** + * @lane_positions: + * + * Array representing the physical positions of the data-lanes. + * Indexed by logical lane number. + */ + unsigned char lane_positions[PHY_MIPI_DPHY_MAX_DATA_LANES]; }; int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, From 3b059bfa9499690a5812e397ed7a08bd5661fdca Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 25 Mar 2026 21:47:58 +0000 Subject: [PATCH 0632/1330] FROMLIST: phy: dphy: Add lane_polarities to DPHY config struct Pass an array of data-lane polarities from controller to PHY. A true value means the lane polarity is inverted. Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-2-c6df5599284a@linaro.org/ Signed-off-by: Bryan O'Donoghue (cherry picked from commit ee2bec5efc9d9306a23b173445e7395d513570b1) --- include/linux/phy/phy-mipi-dphy.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index c7eb11c41d7ec..3e0333b5a1a71 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -284,6 +284,14 @@ struct phy_configure_opts_mipi_dphy { * Indexed by logical lane number. */ unsigned char lane_positions[PHY_MIPI_DPHY_MAX_DATA_LANES]; + + /** + * @lane_polarities: + * + * Array representing data-lane polarities. True means inverted. + * Indexed by logical lane number. + */ + bool lane_polarities[PHY_MIPI_DPHY_MAX_DATA_LANES]; }; int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, From 363ddfcce8269d8c0b8417c935f7a51cf0ab8694 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 25 Mar 2026 21:47:59 +0000 Subject: [PATCH 0633/1330] FROMLIST: phy: dphy: Add clock_lane_position to DPHY config struct We need to identify which lane is the clock-lane as many different PHYs allow for a range of lanes, potentially any of the lanes to be the clock input lane on a PHY. Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-3-c6df5599284a@linaro.org/ Signed-off-by: Bryan O'Donoghue (cherry picked from commit 22f80d57dd57a6a8ff15bf83d18ab7de5ecf98f0) --- include/linux/phy/phy-mipi-dphy.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index 3e0333b5a1a71..76d41580e225a 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -292,6 +292,13 @@ struct phy_configure_opts_mipi_dphy { * Indexed by logical lane number. */ bool lane_polarities[PHY_MIPI_DPHY_MAX_DATA_LANES]; + + /** + * @clock_lane_position: + * + * Physical lane number used as the clock lane. + */ + unsigned char clock_lane_position; }; int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, From 986aa9cdfbf3de857b95303e65774becd0be68f7 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 25 Mar 2026 21:48:00 +0000 Subject: [PATCH 0634/1330] FROMLIST: phy: dphy: Add clock_lane_polarity to DPHY config struct Specify the polarity of the clock lane in DPHY mode. When true this bool means the polarity is inverted. Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-4-c6df5599284a@linaro.org/ Signed-off-by: Bryan O'Donoghue (cherry picked from commit 6c3e9fd12262dd50787dd221ffef699ff8ec0c15) --- include/linux/phy/phy-mipi-dphy.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index 76d41580e225a..f7b4ad29e6f83 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -299,6 +299,13 @@ struct phy_configure_opts_mipi_dphy { * Physical lane number used as the clock lane. */ unsigned char clock_lane_position; + + /** + * @clock_lane_polarity: + * + * Clock lane polarity. True means inverted. + */ + bool clock_lane_polarity; }; int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, From b1618338d4eb737ce972247b2bd8fe05230ffd99 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Mar 2026 01:28:31 +0000 Subject: [PATCH 0635/1330] FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Describe iommu entries The original iommus list included entries for ICP and BPS/IPE S1 contexts. Only the five S1 HLOS stream IDs are required by the CAMSS ISP hardware: IFE/IFE_LITE read and write, SFE read and write, and CDM IFE. The remaining entries serve other hardware blocks which will be described in their own nodes as support is added. Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-3-5b93415be6dd@linaro.org/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue (cherry picked from commit 094e80511ebc9bf981e5ca65d9c3cfcb4ae8e760) --- .../bindings/media/qcom,x1e80100-camss.yaml | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml index 9f52068d628b5..f1686e1998c2c 100644 --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -116,8 +116,22 @@ properties: - const: sf_icp_mnoc iommus: - minItems: 5 - maxItems: 8 + oneOf: + - items: + - description: S1 HLOS IFE and IFE_LITE non-protected read + - description: S1 HLOS IFE and IFE_LITE non-protected write + - description: S1 HLOS SFE non-protected read + - description: S1 HLOS SFE non-protected write + - description: S1 HLOS CDM IFE non-protected + - description: Legacy slot 0 - do not use + - description: Legacy slot 1 - do not use + - description: Legacy slot 2 - do not use + - items: + - description: S1 HLOS IFE and IFE_LITE non-protected read + - description: S1 HLOS IFE and IFE_LITE non-protected write + - description: S1 HLOS SFE non-protected read + - description: S1 HLOS SFE non-protected write + - description: S1 HLOS CDM IFE non-protected power-domains: items: @@ -422,9 +436,7 @@ examples: <&apps_smmu 0x820 0x60>, <&apps_smmu 0x840 0x60>, <&apps_smmu 0x860 0x60>, - <&apps_smmu 0x1860 0x60>, - <&apps_smmu 0x18e0 0x00>, - <&apps_smmu 0x19a0 0x20>; + <&apps_smmu 0x18a0 0x0>; power-domains = <&camcc CAM_CC_IFE_0_GDSC>, <&camcc CAM_CC_IFE_1_GDSC>, From e7f76db6bc0e89173bf98767cd88af648405d0f4 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Mar 2026 01:28:32 +0000 Subject: [PATCH 0636/1330] FROMLIST: media: qcom: camss: Add support to populate sub-devices Use devm_of_platform_populate() to populate subs in the tree. Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-4-5b93415be6dd@linaro.org/ Signed-off-by: Bryan O'Donoghue Reviewed-by: Loic Poulain (cherry picked from commit c8d31c127d453794d80413ee0b909b058db5f2b2) --- drivers/media/platform/qcom/camss/camss.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 9db2d0ddfb9ae..47da76dd87f7e 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -5326,6 +5327,8 @@ static int camss_probe(struct platform_device *pdev) if (!camss) return -ENOMEM; + devm_of_platform_populate(dev); + camss->res = of_device_get_match_data(dev); atomic_set(&camss->ref_count, 0); From 024375170e5524e29458fe90fd1a9bdfdf19561a Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 6 Feb 2026 02:44:08 +0530 Subject: [PATCH 0637/1330] FROMLIST: arm64: dts: qcom: pm8350c: Enable Qualcomm BCL device Enable Qualcomm BCL hardware devicetree binding configuration for pm8350c. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20260206-qcom-bcl-hwmon-v1-4-7b426f0b77a1@oss.qualcomm.com (cherry picked from commit fb8f5355de91d4053b649308744c1aa8ca95461b) --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index 1a24e6439e36d..f0cf55a7fc9e5 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -41,6 +41,15 @@ #pwm-cells = <2>; status = "disabled"; }; + + sensor@4700 { + compatible = "qcom,pm8350c-bcl", "qcom,bcl-v2"; + reg = <0x4700>; + interrupts = <0x2 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "bcl-max-min", + "bcl-critical"; + }; }; }; From 3b7fc440e64baf0ab59abfdb2a23efb2adbc3c3a Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 6 Feb 2026 02:44:07 +0530 Subject: [PATCH 0638/1330] FROMLIST: arm64: dts: qcom: pm7250b: Enable Qualcomm BCL device Enable Qualcomm BCL hardware devicetree binding configuration for pm7250b. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20260206-qcom-bcl-hwmon-v1-3-7b426f0b77a1@oss.qualcomm.com (cherry picked from commit 7513a12c69ef472861f4e293328a42535aebc7fe) --- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 0761e6b5fd8d1..dffd84dd87a85 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -202,6 +202,16 @@ interrupt-controller; #interrupt-cells = <2>; }; + + sensor@1d00 { + compatible = "qcom,pm7250b-bcl", "qcom,bcl-v1"; + reg = <0x1d00>; + interrupts = , + ; + interrupt-names = "bcl-max-min", + "bcl-critical"; + overcurrent-thresholds-milliamp = <5500 6000>; + }; }; pmic@PM7250B_SID1 { From c557f5385bebce986781c6b904def5972800010d Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Mon, 20 Apr 2026 15:30:02 +0530 Subject: [PATCH 0639/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable 4-lane DisplayPort Alt Mode Add the mode-switch property to the QMP combo PHY so that mode-switch events are routed to it, allowing the PHY to enter DisplayPort Alternate Mode. Expand the DP data-lanes assignment from two to four lanes to make use of the full link bandwidth available in this configuration. Signed-off-by: Mahadevan P Link: https://lore.kernel.org/all/20260420-kodiak_4k-v1-1-83dfc66b8f06@oss.qualcomm.com/ (cherry picked from commit 9e842b409bea2d1344126d1369bc6e36fed0ac60) --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 45526a5c8cbad..86eb67639c3dc 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -774,7 +774,7 @@ }; &mdss_dp_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; @@ -1359,6 +1359,7 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p912>; + mode-switch; orientation-switch; status = "okay"; From ebe213356d4b219ab458f90757c2f273fc71913b Mon Sep 17 00:00:00 2001 From: Qian Zhang Date: Tue, 17 Mar 2026 17:20:25 +0800 Subject: [PATCH 0640/1330] QCLINUX: debug: Enable ATH11K CFR Enable RELAY and ATH11K_CFR for channel Frequency Response (CFR) module. Signed-off-by: Qian Zhang (cherry picked from commit 573e3332a64adff6ea94b747253c3b8566dc5c5d) --- kernel/configs/debug.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/configs/debug.config b/kernel/configs/debug.config index 6a9237a66deb7..8d45cf4500bfb 100644 --- a/kernel/configs/debug.config +++ b/kernel/configs/debug.config @@ -120,6 +120,7 @@ CONFIG_PREEMPT=y # # Qualcomm Debug Configs # +CONFIG_ATH11K_CFR=y CONFIG_ATH11K_COREDUMP=y CONFIG_ATH11K_DEBUG=y CONFIG_ATH11K_DEBUGFS=y @@ -146,6 +147,7 @@ CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_PM_ADVANCED_DEBUG=y CONFIG_PM_DEBUG=y CONFIG_PM_SLEEP_DEBUG=y +CONFIG_RELAY=y CONFIG_SCHED_TRACER=y CONFIG_STACK_TRACER=y CONFIG_TRACEPOINTS=y From 1968031c9e0719a64cdc542dc9470fbbcd48c0ec Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 24 Mar 2026 12:18:21 +0530 Subject: [PATCH 0641/1330] QCLINUX: qcom.config: Enable MMC_CRYPTO for ICE emmc To enable ICE, require MMC_CRYPTO for sdhci and SCSI_UFS_CRYPTO for ufs based targets. SCSI_UFS_CRYPTO is already present, add MMC_CRYPTO for enabling inline encryption. Signed-off-by: Kuldeep Singh (cherry picked from commit 1d8f0fc1826cb89dfa051899f09c4c464d8cde15) --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 344120e9c330f..a022018736e7e 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -99,6 +99,7 @@ CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_QCOM_INLINE_CRYPTO_ENGINE=m CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_MMC_CRYPTO=y CONFIG_FS_ENCRYPTION=y # Support performance profiling From 38a6cd441331f5deb9a9cfb60fac33a3f0628e8d Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Wed, 15 Apr 2026 10:08:10 +0530 Subject: [PATCH 0642/1330] QCLINUX: prune.config: Enable Realtek PHY config for Rb3Gen2 Industrial board The Rb3Gen2 Industrial board has the Realtek RTL8221 PHY which fails to function correctly without the Realtek PHY driver. Remove CONFIG_REALTEK_PHY from prune.config to properly enable it. Signed-off-by: Mohd Ayaan Anwar (cherry picked from commit 4087f0b8d5d58e7bcb6f7ea983e28903c4972d87) --- arch/arm64/configs/prune.config | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/prune.config b/arch/arm64/configs/prune.config index fba07d6ebe12d..a13ad5e28c009 100644 --- a/arch/arm64/configs/prune.config +++ b/arch/arm64/configs/prune.config @@ -92,7 +92,6 @@ # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_MICROSEMI_PHY is not set -# CONFIG_REALTEK_PHY is not set # CONFIG_ROCKCHIP_PHY is not set # CONFIG_DP83867_PHY is not set # CONFIG_DP83TD510_PHY is not set From 7d9c538897c30b916979f8f5149146aefc9244e9 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Fri, 17 Apr 2026 11:17:28 +0530 Subject: [PATCH 0643/1330] QCLINUX: qcom.config: Enable SYSFS config Enable CONFIG_WATCHDOG_SYSFS=y in arch/arm64/configs/qcom.config. Without this option, watchdog core does not expose sysfs watchdog attributes (e.g. timeout, timeleft, status, bootstatus, etc.) under /sys/class/watchdog/watchdogN/, which matches the observed behavior on iq-9075-evk where only basic entries were present. This makes watchdog sysfs nodes available on qcom-next/6.18.y builds that use this config fragment. Signed-off-by: Anurag Pateriya (cherry picked from commit 3110b6b3c49547a7c09aeefd7b3801b078e54e17) --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index a022018736e7e..72f860a6dec2c 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -77,6 +77,7 @@ CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_WATCHDOG_SYSFS=y CONFIG_ZRAM=y # Kubernetes support From d952e052629ad5ae79e276520d116b314417ae3f Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Thu, 23 Apr 2026 12:38:59 +0530 Subject: [PATCH 0644/1330] QCLINUX: prune.config: Disable MMU_500 CPRE ERRATA workaround for Qualcomm SOC Disable MMU-500's CPRE ERRATA workaround for Qualcomm SOCs, to not disable prefetch functionality by CPRE bit reset in arm_mmu500_reset path during system suspend-resume cycle. Signed-off-by: Bibek Kumar Patro (cherry picked from commit 771ebbc98bd03048ea231a8d1e4fa52637202620) --- arch/arm64/configs/prune.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/prune.config b/arch/arm64/configs/prune.config index a13ad5e28c009..fd35e50601532 100644 --- a/arch/arm64/configs/prune.config +++ b/arch/arm64/configs/prune.config @@ -322,3 +322,4 @@ # CONFIG_SUN_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set +# CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA is not set From 5845d8a56350b7557475f7ca09a3747793ba805d Mon Sep 17 00:00:00 2001 From: Aastha Pandey Date: Fri, 3 Apr 2026 17:26:33 +0530 Subject: [PATCH 0645/1330] FROMLIST: arm64: dts: qcom: sm8750: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Reviewed-by: Dmitry Baryshkov Reviewed-by: Gaurav Kohli Link: https://patch.msgid.link/20260403-cpufreq-v1-1-9d465988c3f9@oss.qualcomm.com Signed-off-by: Aastha Pandey (cherry picked from commit 705ac5445b8a756b1cac0a8c4d6b4a621d42b147) --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index f4c0aac959a64..2441bb7063bc6 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -46,6 +46,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -62,6 +63,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -72,6 +74,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -82,6 +85,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -92,6 +96,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd4>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -102,6 +107,7 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd5>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu6: cpu@10000 { @@ -112,6 +118,7 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -128,6 +135,7 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu-map { From 88c7eb2263d6e5f835c863f01bfdc160022ff4bb Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Mon, 30 Mar 2026 20:59:30 +0530 Subject: [PATCH 0646/1330] PENDING: arm64: dts: qcom: Add EL2 support for Iris for monaco Add support for IRIS on monaco when Linux host running at EL2. Signed-off-by: Gourav Kumar (cherry picked from commit 629134fe3d4c6e28c9c35770aaec38750b52b3e4) --- arch/arm64/boot/dts/qcom/monaco-el2.dtso | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-el2.dtso b/arch/arm64/boot/dts/qcom/monaco-el2.dtso index a7e3270f86090..7cae65ae499c3 100644 --- a/arch/arm64/boot/dts/qcom/monaco-el2.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-el2.dtso @@ -13,7 +13,10 @@ }; &iris { - status = "disabled"; + status = "okay"; + video-firmware { + iommus = <&apps_smmu 0x0882 0x0400>; + }; }; &remoteproc_adsp { From 532eb89e71d0723f2f5c46b05658ba55b9526aaf Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Mon, 13 Apr 2026 17:18:17 +0530 Subject: [PATCH 0647/1330] FROMLIST: arm64: dts: qcom: monaco-evk: Extract common EVK hardware into shared dtsi The monaco-ac EVK is a new board variant which shares the majority of its hardware description with the existing monaco-evk board. In preparation for adding this variant, extract the common hardware nodes from monaco-evk.dts into a new shared monaco-evk-common.dtsi include file, and update monaco-evk.dts to include it and keep only board-specific overrides. No functional change intended. Link: https://lore.kernel.org/lkml/20260413114819.3894307-2-umang.chheda@oss.qualcomm.com/ Signed-off-by: Umang Chheda (cherry picked from commit be25c6934adcf138707bf5c53f6d705570f4964b) --- .../boot/dts/qcom/monaco-evk-common.dtsi | 1162 +++++++++++++++++ arch/arm64/boot/dts/qcom/monaco-evk.dts | 1077 +-------------- 2 files changed, 1174 insertions(+), 1065 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi new file mode 100644 index 0000000000000..8cd45642c5196 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi @@ -0,0 +1,1162 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" + +/ { + aliases { + ethernet0 = ðernet0; + i2c1 = &i2c1; + serial0 = &uart7; + serial1 = &uart2; + serial2 = &uart6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector-1 { + compatible = "usb-c-connector"; + label = "USB1-Type-C"; + data-role = "host"; + power-role = "source"; + + vbus-supply = <&vbus_supply_regulator_1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_con_ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_1_in_ep>; + }; + }; + + port@1 { + reg = <1>; + + usb1_hs_in: endpoint { + remote-endpoint = <&usb_hub_2_1>; + }; + + }; + + port@2 { + reg = <2>; + + usb1_ss_in: endpoint { + remote-endpoint = <&usb_hub_3_1>; + }; + }; + }; + }; + + connector-2 { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + + id-gpios = <&pmm8620au_0_gpios 9 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&expander6 7 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb2_vbus>; + + pinctrl-0 = <&usb2_id>; + pinctrl-names = "default"; + + port { + usb2_con_hs_ep: endpoint { + remote-endpoint = <&usb_2_dwc3_hs>; + }; + }; + }; + + dmic: audio-codec-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <1>; + }; + + max98357a: audio-codec-1 { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + }; + + dp-connector-0 { + compatible = "dp-connector"; + label = "DP0"; + type = "mini"; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <<8713sx_dp0_out>; + }; + }; + }; + + dp-connector-1 { + compatible = "dp-connector"; + label = "DP1"; + type = "mini"; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <<8713sx_dp1_out>; + }; + }; + }; + + vbus_supply_regulator_1: regulator-vbus-supply-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus_supply_1"; + gpio = <&expander1 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&pmm8650au_1_gpios 7 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + sound { + compatible = "qcom,qcs8275-sndcard"; + model = "MONACO-EVK"; + + pinctrl-0 = <&hs0_mi2s_active>, <&mi2s1_active>; + pinctrl-names = "default"; + + hs0-mi2s-playback-dai-link { + link-name = "HS0 MI2S Playback"; + + codec { + sound-dai = <&max98357a>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + sec-mi2s-capture-dai-link { + link-name = "Secondary MI2S Capture"; + + codec { + sound-dai = <&dmic>; + }; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_cam0_2p8: vreg-cam0-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam0_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + vreg_cam1_2p8: vreg-cam1-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam1_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + vreg_cam2_2p8: vreg-cam2-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam2_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 75 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam2_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + /* This comes from a PMIC handled within the SAIL domain */ + vreg_s2s: vreg-s2s { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2s"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_dcin_12v: regulator-dcin-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_DCIN_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_dcin_12v>; + + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s5c: smps5 { + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <512000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +ðernet0 { + phy-mode = "2500base-x"; + phy-handle = <&hsgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + nvmem-cells = <&mac_addr0>; + nvmem-cell-names = "mac-address"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + +&i2c0 { + status = "okay"; + + bridge@4f { + compatible = "lontium,lt8713sx"; + reg = <0x4f>; + reset-gpios = <&expander5 6 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt8713sx_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8713sx_dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + + port@2 { + reg = <2>; + + lt8713sx_dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; + }; + }; + + usb-typec@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + + interrupts = <45 IRQ_TYPE_EDGE_FALLING>; + + id-gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb1_id>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_1_in_ep: endpoint { + remote-endpoint = <&usb1_con_ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_1_out_ep: endpoint { + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_addr0: mac-addr@0 { + reg = <0x0 0x6>; + }; + }; + }; +}; + +&i2c15 { + pinctrl-0 = <&qup_i2c15_default>; + pinctrl-names = "default"; + + status = "okay"; + + expander0: gpio@38 { + compatible = "ti,tca9538"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 56 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander0_int>; + pinctrl-names = "default"; + }; + + expander1: gpio@39 { + compatible = "ti,tca9538"; + reg = <0x39>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander1_int>; + pinctrl-names = "default"; + }; + + expander2: gpio@3a { + compatible = "ti,tca9538"; + reg = <0x3a>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 95 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander2_int>; + pinctrl-names = "default"; + }; + + expander3: gpio@3b { + compatible = "ti,tca9538"; + reg = <0x3b>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander3_int>; + pinctrl-names = "default"; + }; + + expander4: gpio@3c { + compatible = "ti,tca9538"; + reg = <0x3c>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 96 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander4_int>; + pinctrl-names = "default"; + }; + + expander5: gpio@3d { + compatible = "ti,tca9538"; + reg = <0x3d>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander5_int>; + pinctrl-names = "default"; + + gpio5-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb1-ss-high-gpio5"; + }; + }; + + expander6: gpio@3e { + compatible = "ti,tca9538"; + reg = <0x3e>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 52 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander6_int>; + pinctrl-names = "default"; + wakeup-source; + }; +}; + +&iris { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <<8713sx_dp_in>; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; +}; + +&pmm8620au_0_gpios { + usb2_id: usb2-id-state { + pins = "gpio9"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + +&qup_i2c0_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8300/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8300/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp { + firmware-name = "qcom/qcs8300/gpdsp0.mbn"; + + status = "okay"; +}; + +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; + + no-sd; + no-sdio; + non-removable; + + status = "okay"; +}; + +&serdes0 { + phy-supply = <&vreg_l5a>; + vdda-0p9-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&spi10 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&tlmm { + gpio7_hog: gpio7-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bootup-high-gpio7"; + }; + + gpio14_hog: gpio14-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb1-hs-high-gpio14"; + }; + + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio5"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio6"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + expander5_int: expander5-int-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + expander1_int: expander1-int-state { + pins = "gpio16"; + function = "gpio"; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-state { + pins = "gpio19", "gpio20"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + expander3_int: expander3-int-state { + pins = "gpio24"; + function = "gpio"; + bias-pull-up; + }; + + expander6_int: expander6-int-state { + pins = "gpio52"; + function = "gpio"; + bias-pull-up; + }; + + expander0_int: expander0-int-state { + pins = "gpio56"; + function = "gpio"; + bias-pull-up; + }; + + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state { + pins = "gpio75"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c15_default: qup-i2c15-state { + pins = "gpio91", "gpio92"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + expander2_int: expander2-int-state { + pins = "gpio95"; + function = "gpio"; + bias-pull-up; + }; + + expander4_int: expander4-int-state { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; + }; + + usb1_id: usb1-id-state { + pins = "gpio13"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart2 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6855-bt"; + max-speed = <3200000>; + + vddrfacmn-supply = <&vreg_wcn_3p3>; + vddaon-supply = <&vreg_wcn_3p3>; + vddwlcx-supply = <&vreg_wcn_3p3>; + vddwlmx-supply = <&vreg_wcn_3p3>; + vddbtcmx-supply = <&vreg_wcn_3p3>; + vddrfa0p8-supply = <&vreg_wcn_3p3>; + vddrfa1p2-supply = <&vreg_wcn_3p3>; + vddrfa1p8-supply = <&vreg_wcn_3p3>; + }; +}; + +&uart6 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_1 { + dr_mode = "host"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + usb_hub_2_x: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + + peer-hub = <&usb_hub_3_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_2_1: endpoint { + remote-endpoint = <&usb1_hs_in>; + }; + }; + + /* + * Port-2 and port-3 are not connected to anything on corekit. + */ + port@2 { + reg = <2>; + + usb_hub_2_2: endpoint { + }; + }; + + port@3 { + reg = <3>; + + usb_hub_2_3: endpoint { + }; + }; + + /* + * Port-4 is connected to M.2 E key connector on corekit. + */ + port@4 { + reg = <4>; + + usb_hub_2_4: endpoint { + }; + }; + }; + }; + + usb_hub_3_x: hub@2 { + compatible = "usb5e3,625"; + reg = <2>; + + peer-hub = <&usb_hub_2_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_3_1: endpoint { + remote-endpoint = <&usb1_ss_in>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_3_2: endpoint { + }; + }; + + port@3 { + reg = <3>; + + usb_hub_3_3: endpoint { + }; + }; + + port@4 { + reg = <4>; + + usb_hub_3_4: endpoint { + }; + }; + }; + }; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3_hs { + remote-endpoint = <&usb2_con_hs_ep>; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 5248086304419..f01eef1c2e16f 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -5,1082 +5,29 @@ /dts-v1/; -#include -#include -#include -#include - -#include "monaco.dtsi" -#include "monaco-pmics.dtsi" +#include "monaco-evk-common.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco EVK"; compatible = "qcom,monaco-evk", "qcom,qcs8300"; - aliases { - ethernet0 = ðernet0; - i2c1 = &i2c1; - serial0 = &uart7; - serial1 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector-1 { - compatible = "usb-c-connector"; - label = "USB1-Type-C"; - data-role = "host"; - power-role = "source"; - - vbus-supply = <&vbus_supply_regulator_1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb1_con_ss_ep: endpoint { - remote-endpoint = <&hd3ss3220_1_in_ep>; - }; - }; - - port@1 { - reg = <1>; - - usb1_hs_in: endpoint { - remote-endpoint = <&usb_hub_2_1>; - }; - - }; - - port@2 { - reg = <2>; - - usb1_ss_in: endpoint { - remote-endpoint = <&usb_hub_3_1>; - }; - }; - }; - }; - - connector-2 { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - - id-gpios = <&pmm8620au_0_gpios 9 GPIO_ACTIVE_HIGH>; - vbus-gpios = <&expander6 7 GPIO_ACTIVE_HIGH>; - vbus-supply = <&vbus_supply_regulator_2>; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2_id>; - - port { - usb2_con_hs_ep: endpoint { - remote-endpoint = <&usb_2_dwc3_hs>; - }; - }; - }; - - dmic: audio-codec-0 { - compatible = "dmic-codec"; - #sound-dai-cells = <0>; - num-channels = <1>; - }; - - dp-connector0 { - compatible = "dp-connector"; - label = "DP"; - type = "mini"; - - port { - dp0_connector_in: endpoint { - remote-endpoint = <<8713sx_dp0_out>; - }; - }; - }; - - dp-connector1 { - compatible = "dp-connector"; - label = "DP"; - type = "mini"; - - port { - dp1_connector_in: endpoint { - remote-endpoint = <<8713sx_dp1_out>; - }; - }; - }; - - max98357a: audio-codec-1 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - }; - - sound { - compatible = "qcom,qcs8275-sndcard"; - model = "MONACO-EVK"; - - pinctrl-0 = <&hs0_mi2s_active>, <&mi2s1_active>; - pinctrl-names = "default"; - - hs0-mi2s-playback-dai-link { - link-name = "HS0 MI2S Playback"; - - codec { - sound-dai = <&max98357a>; - }; - - cpu { - sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - sec-mi2s-capture-dai-link { - link-name = "Secondary MI2S Capture"; - - codec { - sound-dai = <&dmic>; - }; - - cpu { - sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - }; - - vbus_supply_regulator_1: regulator-vbus-supply-1 { - compatible = "regulator-fixed"; - regulator-name = "vbus_supply_1"; - gpio = <&expander1 3 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - vbus_supply_regulator_2: regulator-vbus-supply-2 { - compatible = "regulator-fixed"; - regulator-name = "vbus_supply_2"; - gpio = <&pmm8650au_1_gpios 7 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - vreg_cam1_2p8: vreg-cam1-2p8 { - compatible = "regulator-fixed"; - regulator-name = "vreg_cam1_2p8"; - startup-delay-us = <10000>; - enable-active-high; - gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&cam1_avdd_2v8_en_default>; - pinctrl-names = "default"; - }; - - vreg_dcin_12v: regulator-dcin-12v { - compatible = "regulator-fixed"; - - regulator-name = "VREG_DCIN_12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - - regulator-boot-on; - regulator-always-on; - }; - - vreg_wcn_3p3: regulator-wcn-3p3 { + /* This comes from a PMIC handled within the SAIL domain */ + vreg_s2s: vreg-s2s { compatible = "regulator-fixed"; + regulator-name = "vreg_s2s"; - regulator-name = "VREG_WCN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vreg_dcin_12v>; - - regulator-boot-on; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vreg_l3a: ldo3 { - regulator-name = "vreg_l3a"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l4a: ldo4 { - regulator-name = "vreg_l4a"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l5a: ldo5 { - regulator-name = "vreg_l5a"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l6a: ldo6 { - regulator-name = "vreg_l6a"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l7a: ldo7 { - regulator-name = "vreg_l7a"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l8a: ldo8 { - regulator-name = "vreg_l8a"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l9a: ldo9 { - regulator-name = "vreg_l9a"; - regulator-min-microvolt = <2970000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - }; - - regulators-1 { - compatible = "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_s5c: smps5 { - regulator-name = "vreg_s5c"; - regulator-min-microvolt = <1104000>; - regulator-max-microvolt = <1104000>; - regulator-initial-mode = ; - }; - - vreg_l1c: ldo1 { - regulator-name = "vreg_l1c"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <512000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l2c: ldo2 { - regulator-name = "vreg_l2c"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <904000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l4c: ldo4 { - regulator-name = "vreg_l4c"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l7c: ldo7 { - regulator-name = "vreg_l7c"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l8c: ldo8 { - regulator-name = "vreg_l8c"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l9c: ldo9 { - regulator-name = "vreg_l9c"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - }; -}; - -ðernet0 { - phy-mode = "2500base-x"; - phy-handle = <&hsgmii_phy0>; - - pinctrl-0 = <ðernet0_default>; - pinctrl-names = "default"; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - nvmem-cells = <&mac_addr0>; - nvmem-cell-names = "mac-address"; - - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - hsgmii_phy0: ethernet-phy@1c { - compatible = "ethernet-phy-id004d.d101"; - reg = <0x1c>; - reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; -}; - -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&gpu_zap_shader { - firmware-name = "qcom/qcs8300/a623_zap.mbn"; -}; - -&i2c0 { - status = "okay"; - - bridge@4f { - compatible = "lontium,lt8713sx"; - reg = <0x4f>; - reset-gpios = <&expander5 6 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lt8713sx_dp_in: endpoint { - remote-endpoint = <&mdss_dp0_out>; - }; - }; - - port@1 { - reg = <1>; - lt8713sx_dp0_out: endpoint { - remote-endpoint = <&dp0_connector_in>; - }; - }; - - port@2 { - reg = <2>; - lt8713sx_dp1_out: endpoint { - remote-endpoint = <&dp1_connector_in>; - }; - }; - }; - }; - - usb-typec@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - - interrupts = <45 IRQ_TYPE_EDGE_FALLING>; - - id-gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&usb1_id>; - pinctrl-names = "default"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hd3ss3220_1_in_ep: endpoint { - remote-endpoint = <&usb1_con_ss_ep>; - }; - }; - - port@1 { - reg = <1>; - - hd3ss3220_1_out_ep: endpoint { - }; - }; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&qup_i2c1_default>; - pinctrl-names = "default"; - - status = "okay"; - - fan_controller: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #pwm-cells = <2>; - - fan { - pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; - }; - }; - - eeprom0: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - mac_addr0: mac-addr@0 { - reg = <0x0 0x6>; - }; - }; - }; -}; - -&i2c15 { - pinctrl-0 = <&qup_i2c15_default>; - pinctrl-names = "default"; - - status = "okay"; - - expander0: gpio@38 { - compatible = "ti,tca9538"; - reg = <0x38>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - interrupts-extended = <&tlmm 56 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&expander0_int>; - pinctrl-names = "default"; - }; - - expander1: gpio@39 { - compatible = "ti,tca9538"; - reg = <0x39>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&expander1_int>; - pinctrl-names = "default"; - }; - - expander2: gpio@3a { - compatible = "ti,tca9538"; - reg = <0x3a>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - interrupts-extended = <&tlmm 95 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&expander2_int>; - pinctrl-names = "default"; - }; - - expander3: gpio@3b { - compatible = "ti,tca9538"; - reg = <0x3b>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&expander3_int>; - pinctrl-names = "default"; - }; - - expander4: gpio@3c { - compatible = "ti,tca9538"; - reg = <0x3c>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - interrupts-extended = <&tlmm 96 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&expander4_int>; - pinctrl-names = "default"; - }; - - expander5: gpio@3d { - compatible = "ti,tca9538"; - reg = <0x3d>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&expander5_int>; - pinctrl-names = "default"; - - gpio5-hog { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb1-ss-high-gpio5"; - }; - }; - - expander6: gpio@3e { - compatible = "ti,tca9538"; - reg = <0x3e>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - interrupts-extended = <&tlmm 52 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&expander6_int>; - pinctrl-names = "default"; - wakeup-source; - }; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dp0 { - pinctrl-0 = <&dp_hot_plug_det>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&mdss_dp0_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <<8713sx_dp_in>; -}; - -&mdss_dp0_phy { - vdda-phy-supply = <&vreg_l5a>; - vdda-pll-supply = <&vreg_l4a>; - - status = "okay"; -}; - -&iris { - status = "okay"; -}; - -&pcie0 { - pinctrl-0 = <&pcie0_default_state>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie0_phy { - vdda-phy-supply = <&vreg_l6a>; - vdda-pll-supply = <&vreg_l5a>; - - status = "okay"; -}; - -&pcie1 { - pinctrl-0 = <&pcie1_default_state>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie1_phy { - vdda-phy-supply = <&vreg_l6a>; - vdda-pll-supply = <&vreg_l5a>; - - status = "okay"; -}; - -&pcieport0 { - reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; -}; - -&pcieport1 { - reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; -}; - -&pmm8620au_0_gpios { - usb2_id: usb2-id-state { - pins = "gpio9"; - function = "normal"; - input-enable; - bias-pull-up; - power-source = <0>; - }; -}; - -&qup_i2c0_data_clk { - drive-strength = <2>; - bias-pull-up; -}; - -&qupv3_id_0 { - firmware-name = "qcom/qcs8300/qupv3fw.elf"; - status = "okay"; -}; - -&qupv3_id_1 { - firmware-name = "qcom/qcs8300/qupv3fw.elf"; - status = "okay"; -}; - -&remoteproc_adsp { - firmware-name = "qcom/qcs8300/adsp.mbn"; - - status = "okay"; -}; - -&remoteproc_cdsp { - firmware-name = "qcom/qcs8300/cdsp0.mbn"; - - status = "okay"; -}; - -&remoteproc_gpdsp { - firmware-name = "qcom/qcs8300/gpdsp0.mbn"; - - status = "okay"; -}; - -&serdes0 { - phy-supply = <&vreg_l5a>; - vdda-0p9-supply = <&vreg_l4a>; - - status = "okay"; -}; - -&spi10 { - status = "okay"; - - tpm@0 { - compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&tlmm { - - expander0_int: expander0-int-state { - pins = "gpio56"; - function = "gpio"; - bias-pull-up; - }; - - expander1_int: expander1-int-state { - pins = "gpio16"; - function = "gpio"; - bias-pull-up; - }; - - expander2_int: expander2-int-state { - pins = "gpio95"; - function = "gpio"; - bias-pull-up; - }; - - expander3_int: expander3-int-state { - pins = "gpio24"; - function = "gpio"; - bias-pull-up; - }; - - expander4_int: expander4-int-state { - pins = "gpio96"; - function = "gpio"; - bias-pull-up; - }; - - expander5_int: expander5-int-state { - pins = "gpio3"; - function = "gpio"; - bias-pull-up; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - - expander6_int: expander6-int-state { - pins = "gpio52"; - function = "gpio"; - bias-pull-up; - }; - - gpio7_hog: gpio7-hog { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "bootup-high-gpio7"; - }; - - gpio14_hog: gpio14-hog { - gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb1-hs-high-gpio14"; - }; - - pcie0_default_state: pcie0-default-state { - wake-pins { - pins = "gpio0"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - clkreq-pins { - pins = "gpio1"; - function = "pcie0_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-pins { - pins = "gpio2"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - ethernet0_default: ethernet0-default-state { - ethernet0_mdc: ethernet0-mdc-pins { - pins = "gpio5"; - function = "emac0_mdc"; - drive-strength = <16>; - bias-pull-up; - }; - - ethernet0_mdio: ethernet0-mdio-pins { - pins = "gpio6"; - function = "emac0_mdio"; - drive-strength = <16>; - bias-pull-up; - }; - }; - - qup_i2c1_default: qup-i2c1-state { - pins = "gpio19", "gpio20"; - function = "qup0_se1"; - drive-strength = <2>; - bias-pull-up; - }; - - pcie1_default_state: pcie1-default-state { - wake-pins { - pins = "gpio21"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - clkreq-pins { - pins = "gpio22"; - function = "pcie1_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-pins { - pins = "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qup_i2c15_default: qup-i2c15-state { - pins = "gpio91", "gpio92"; - function = "qup1_se7"; - drive-strength = <2>; - bias-pull-up; - }; - - usb1_id: usb1-id-state { - pins = "gpio13"; - function = "gpio"; - bias-pull-up; - }; -}; - -&uart2 { - status = "okay"; - - bluetooth: bluetooth { - compatible = "qcom,wcn6855-bt"; - max-speed = <3200000>; - - vddrfacmn-supply = <&vreg_wcn_3p3>; - vddaon-supply = <&vreg_wcn_3p3>; - vddwlcx-supply = <&vreg_wcn_3p3>; - vddwlmx-supply = <&vreg_wcn_3p3>; - vddbtcmx-supply = <&vreg_wcn_3p3>; - vddrfa0p8-supply = <&vreg_wcn_3p3>; - vddrfa1p2-supply = <&vreg_wcn_3p3>; - vddrfa1p8-supply = <&vreg_wcn_3p3>; - }; -}; - -&uart7 { - status = "okay"; -}; - -&ufs_mem_hc { - reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; - vcc-supply = <&vreg_l8a>; - vcc-max-microamp = <1100000>; - vccq-supply = <&vreg_l4c>; - vccq-max-microamp = <1200000>; - - status = "okay"; -}; - -&ufs_mem_phy { - vdda-phy-supply = <&vreg_l4a>; - vdda-pll-supply = <&vreg_l5a>; - - status = "okay"; }; -&usb_1 { - dr_mode = "host"; +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; - #address-cells = <1>; - #size-cells = <0>; - - status = "okay"; - - usb_hub_2_x: hub@1 { - compatible = "usb5e3,610"; - reg = <1>; - - peer-hub = <&usb_hub_3_x>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - usb_hub_2_1: endpoint { - remote-endpoint = <&usb1_hs_in>; - }; - }; - - /* - * Port-2 and port-3 are not connected to anything on corekit. - */ - port@2 { - reg = <2>; - - usb_hub_2_2: endpoint { - }; - }; - - port@3 { - reg = <3>; - - usb_hub_2_3: endpoint { - }; - }; - - /* - * Port-4 is connected to M.2 E key connector on corekit. - */ - port@4 { - reg = <4>; - - usb_hub_2_4: endpoint { - }; - }; - }; - }; - - usb_hub_3_x: hub@2 { - compatible = "usb5e3,625"; - reg = <2>; - - peer-hub = <&usb_hub_2_x>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - usb_hub_3_1: endpoint { - remote-endpoint = <&usb1_ss_in>; - }; - }; - - port@2 { - reg = <2>; - - usb_hub_3_2: endpoint { - }; - }; - - port@3 { - reg = <3>; - - usb_hub_3_3: endpoint { - }; - }; - - port@4 { - reg = <4>; - - usb_hub_3_4: endpoint { - }; - }; - }; - }; -}; - -&usb_1_hsphy { - vdda-pll-supply = <&vreg_l7a>; - vdda18-supply = <&vreg_l7c>; - vdda33-supply = <&vreg_l9a>; - - status = "okay"; -}; - -&usb_qmpphy { - vdda-phy-supply = <&vreg_l7a>; - vdda-pll-supply = <&vreg_l5a>; - - status = "okay"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3_hs { - remote-endpoint = <&usb2_con_hs_ep>; -}; + no-sd; + no-sdio; + non-removable; -&usb_2_hsphy { - vdda-pll-supply = <&vreg_l7a>; - vdda18-supply = <&vreg_l7c>; - vdda33-supply = <&vreg_l9a>; status = "okay"; }; From 774e99b222a113d892882092afdedf966e316eda Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Mon, 13 Apr 2026 17:18:18 +0530 Subject: [PATCH 0648/1330] FROMLIST: dt-bindings: arm: qcom: Add monaco-ac-evk support Introduce bindings for the monaco-ac-evk IoT board, which is based on the monaco-ac (QCS8300-AC) SoC variant. Link: https://lore.kernel.org/lkml/20260413114819.3894307-3-umang.chheda@oss.qualcomm.com/ Signed-off-by: Umang Chheda Acked-by: Krzysztof Kozlowski (cherry picked from commit 9e9f8be6df0c410bdcff6b6692aee757f1a02eb5) --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 44c0b082737df..98fa0a7a165c2 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -881,6 +881,11 @@ properties: - items: - enum: +<<<<<<< HEAD +======= + - arduino,monza + - qcom,monaco-ac-evk +>>>>>>> 9e9f8be6df0c (FROMLIST: dt-bindings: arm: qcom: Add monaco-ac-evk support) - qcom,monaco-evk - qcom,qcs8300-ride - const: qcom,qcs8300 From cc1dae1ed3cd4ac6c623d322314f195812d27526 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Mon, 13 Apr 2026 17:18:19 +0530 Subject: [PATCH 0649/1330] FROMLIST: arm64: dts: qcom: monaco: Add monaco-ac EVK board Add initial device tree support for monaco-ac EVK board, based on Qualcomm's monaco-ac (QCS8300-AC) variant SoC. Compared to the existing monaco-evk board, which is based on the QCS8300-AA SKU and uses a four-PMIC power delivery network (2x PM8650AU, Maxim MAX20018, TI TPS6594) to support higher power requirements, the monaco-ac EVK uses QCS8300-AC SKU (with 20 TOPS NPU capability) and a simplified two-PMIC power delivery network (2x PM8650AU). Apart from the SoC SKU and PDN differences, the board layout and peripherals are equivalent to the monaco-evk design and are reused accordingly. Link: https://lore.kernel.org/lkml/20260413114819.3894307-4-umang.chheda@oss.qualcomm.com/ Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda (cherry picked from commit 57fe496d225090fc0458d0e9513f9e493b82c225) --- arch/arm64/boot/dts/qcom/Makefile | 5 ++-- arch/arm64/boot/dts/qcom/monaco-ac-evk.dts | 31 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/monaco-ac-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8c62544fcfc88..512a4615e0682 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -51,12 +51,13 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb - lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo - dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-ac-evk.dtb monaco-evk-el2-dtbs := monaco-evk.dtb monaco-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/monaco-ac-evk.dts b/arch/arm64/boot/dts/qcom/monaco-ac-evk.dts new file mode 100644 index 0000000000000..6405d1e1939b1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-ac-evk.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "monaco-evk-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco-ac EVK"; + compatible = "qcom,monaco-ac-evk", "qcom,qcs8300"; +}; + +&apps_rsc { + regulators-0 { + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + }; +}; From e5ef77d363ea89d97c27841b6eec5ae4455bff81 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Fri, 17 Apr 2026 13:30:04 +0530 Subject: [PATCH 0650/1330] WORKAROUND: arm64: dts: qcom: monaco-evk: Use refgen regulator for usb2 HS PHY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Problem Statement:- After the Introduction of commits (1 and 2) ADB goes offline a few seconds after USB enumeration on the micro‑USB (USB2) port. The failure is consistently observed shortly after enumeration, with the following log indicating regulator shutdown: [ 40.220063][ T49] refgen: disabling On RB4, ADB operates over the USB2 HSPHY, which requires three power rails: 0.8 V (vdda‑pll) 1.8 V (vdda18) 3.3 V (vdda33) Based on the current DTS configuration, the USB2 HS PHY regulators are as follows as per monaco power grid: vdda-pll-supply (0.8 V): l7a vdda18-supply (1.8 V): l7c vdda33-supply (3.3 V): l9a However, according to the Monaco power grid analysis, the regulators for the USB2 HS PHY should be: vdda-pll-supply (0.8 V): l4a vdda18-supply (1.8 V): s4a vdda33-supply (3.3 V): l8a This mismatch in regulator assignment results in unstable PHY power, causing ADB to drop offline shortly after USB enumeration. Workaround solution:- As an interim workaround, the refgen regulator is used for the 0.8 V (vdda‑pll) rail instead of l7a. This change restores stable USB2 HS PHY operation and prevents ADB from disconnecting. Presently this is taken as a workaround while we confirm the mismatch in the power grid understanding. 1) fc406be (add Display Serial Interface device nodes) 2) 2c9e4d7 (add refgen regulator) Signed-off-by: Swati Agarwal (cherry picked from commit 210ebe882e463faf09048ede8af6a39e64bebf1d) --- arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi index 8cd45642c5196..635ee3e06a9cf 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi @@ -1154,7 +1154,7 @@ }; &usb_2_hsphy { - vdda-pll-supply = <&vreg_l7a>; + vdda-pll-supply = <&refgen>; vdda18-supply = <&vreg_l7c>; vdda33-supply = <&vreg_l9a>; From 3b247bdf0d57d3e21a5c898cb64480e7c4573b3c Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 27 Apr 2026 11:27:10 +0800 Subject: [PATCH 0651/1330] FROMLIST: arm64: dts: qcom: monaco: fix wrong connection for the replicator Fix the wrong connection for the qdss replicator device. Link: https://lore.kernel.org/all/20260427-fix-monaco-coresight-dt-v1-1-1707017f20c5@oss.qualcomm.com/ Fixes: 0f43254763b3 ("arm64: dts: qcom: qcs8300: Add coresight nodes") Signed-off-by: Jie Gan (cherry picked from commit 90ba0063424e047ccea4f3c96e9786bee0ff18f1) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 7213c27405e83..e7de7bea7c424 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2950,14 +2950,6 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - - swao_rep_out0: endpoint { - remote-endpoint = <&qdss_rep_in>; - }; - }; - port@1 { reg = <1>; @@ -3667,6 +3659,14 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; From 9ff74bb4aaeb35009e13d8eac6ed3febd9c53b31 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 2 Apr 2026 11:45:43 +0530 Subject: [PATCH 0652/1330] FROMLIST: dt-bindings: clock: qcom: Add Glymur camera clock controller Add device tree bindings for the camera clock controller on Qualcomm Glymur SoC. Signed-off-by: Jagadeesh Kona Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260402-glymur_camcc-v1-1-e8da05a21da7@oss.qualcomm.com (cherry picked from commit 28958dc3738ad1e8b64fc9e40acee10ec69123b0) --- .../bindings/clock/qcom,x1e80100-camcc.yaml | 3 + include/dt-bindings/clock/qcom,glymur-camcc.h | 122 ++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,glymur-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml index b28614186cc09..e7cb8cfa957a4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml @@ -8,12 +8,14 @@ title: Qualcomm Camera Clock & Reset Controller on x1e80100 maintainers: - Bryan O'Donoghue + - Jagadeesh Kona description: | Qualcomm camera clock control module provides the clocks, resets and power domains on x1e80100. See also: + include/dt-bindings/clock/qcom,glymur-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: @@ -22,6 +24,7 @@ allOf: properties: compatible: enum: + - qcom,glymur-camcc - qcom,x1e80100-camcc - qcom,x1p42100-camcc diff --git a/include/dt-bindings/clock/qcom,glymur-camcc.h b/include/dt-bindings/clock/qcom,glymur-camcc.h new file mode 100644 index 0000000000000..0c93fc77ef268 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-camcc.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_GLYMUR_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_NRT_CLK 4 +#define CAM_CC_CAMNOC_AXI_RT_CLK 5 +#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6 +#define CAM_CC_CAMNOC_DCD_XO_CLK 7 +#define CAM_CC_CAMNOC_XO_CLK 8 +#define CAM_CC_CCI_0_CLK 9 +#define CAM_CC_CCI_0_CLK_SRC 10 +#define CAM_CC_CCI_1_CLK 11 +#define CAM_CC_CCI_1_CLK_SRC 12 +#define CAM_CC_CORE_AHB_CLK 13 +#define CAM_CC_CPAS_AHB_CLK 14 +#define CAM_CC_CPAS_BPS_CLK 15 +#define CAM_CC_CPAS_FAST_AHB_CLK 16 +#define CAM_CC_CPAS_IFE_0_CLK 17 +#define CAM_CC_CPAS_IFE_1_CLK 18 +#define CAM_CC_CPAS_IFE_LITE_CLK 19 +#define CAM_CC_CPAS_IPE_NPS_CLK 20 +#define CAM_CC_CPHY_RX_CLK_SRC 21 +#define CAM_CC_CSI0PHYTIMER_CLK 22 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 23 +#define CAM_CC_CSI1PHYTIMER_CLK 24 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI4PHYTIMER_CLK 26 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSID_CLK 28 +#define CAM_CC_CSID_CLK_SRC 29 +#define CAM_CC_CSID_CSIPHY_RX_CLK 30 +#define CAM_CC_CSIPHY0_CLK 31 +#define CAM_CC_CSIPHY1_CLK 32 +#define CAM_CC_CSIPHY4_CLK 33 +#define CAM_CC_FAST_AHB_CLK_SRC 34 +#define CAM_CC_GDSC_CLK 35 +#define CAM_CC_ICP_AHB_CLK 36 +#define CAM_CC_ICP_CLK 37 +#define CAM_CC_ICP_CLK_SRC 38 +#define CAM_CC_IFE_0_CLK 39 +#define CAM_CC_IFE_0_CLK_SRC 40 +#define CAM_CC_IFE_0_DSP_CLK 41 +#define CAM_CC_IFE_0_FAST_AHB_CLK 42 +#define CAM_CC_IFE_1_CLK 43 +#define CAM_CC_IFE_1_CLK_SRC 44 +#define CAM_CC_IFE_1_DSP_CLK 45 +#define CAM_CC_IFE_1_FAST_AHB_CLK 46 +#define CAM_CC_IFE_LITE_AHB_CLK 47 +#define CAM_CC_IFE_LITE_CLK 48 +#define CAM_CC_IFE_LITE_CLK_SRC 49 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 50 +#define CAM_CC_IFE_LITE_CSID_CLK 51 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 52 +#define CAM_CC_IPE_NPS_AHB_CLK 53 +#define CAM_CC_IPE_NPS_CLK 54 +#define CAM_CC_IPE_NPS_CLK_SRC 55 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 56 +#define CAM_CC_IPE_PPS_CLK 57 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 58 +#define CAM_CC_JPEG_CLK 59 +#define CAM_CC_JPEG_CLK_SRC 60 +#define CAM_CC_MCLK0_CLK 61 +#define CAM_CC_MCLK0_CLK_SRC 62 +#define CAM_CC_MCLK1_CLK 63 +#define CAM_CC_MCLK1_CLK_SRC 64 +#define CAM_CC_MCLK2_CLK 65 +#define CAM_CC_MCLK2_CLK_SRC 66 +#define CAM_CC_MCLK3_CLK 67 +#define CAM_CC_MCLK3_CLK_SRC 68 +#define CAM_CC_MCLK4_CLK 69 +#define CAM_CC_MCLK4_CLK_SRC 70 +#define CAM_CC_MCLK5_CLK 71 +#define CAM_CC_MCLK5_CLK_SRC 72 +#define CAM_CC_MCLK6_CLK 73 +#define CAM_CC_MCLK6_CLK_SRC 74 +#define CAM_CC_MCLK7_CLK 75 +#define CAM_CC_MCLK7_CLK_SRC 76 +#define CAM_CC_PLL0 77 +#define CAM_CC_PLL0_OUT_EVEN 78 +#define CAM_CC_PLL0_OUT_ODD 79 +#define CAM_CC_PLL1 80 +#define CAM_CC_PLL1_OUT_EVEN 81 +#define CAM_CC_PLL2 82 +#define CAM_CC_PLL3 83 +#define CAM_CC_PLL3_OUT_EVEN 84 +#define CAM_CC_PLL4 85 +#define CAM_CC_PLL4_OUT_EVEN 86 +#define CAM_CC_PLL5 87 +#define CAM_CC_PLL5_OUT_EVEN 88 +#define CAM_CC_QDSS_DEBUG_CLK 89 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 90 +#define CAM_CC_QDSS_DEBUG_XO_CLK 91 +#define CAM_CC_SLEEP_CLK 92 +#define CAM_CC_SLEEP_CLK_SRC 93 +#define CAM_CC_SLOW_AHB_CLK_SRC 94 +#define CAM_CC_XO_CLK_SRC 95 + +/* CAM_CC power domains */ +#define CAM_CC_BPS_GDSC 0 +#define CAM_CC_IFE_0_GDSC 1 +#define CAM_CC_IFE_1_GDSC 2 +#define CAM_CC_IPE_0_GDSC 3 +#define CAM_CC_TITAN_TOP_GDSC 4 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IPE_0_BCR 4 +#define CAM_CC_QDSS_DEBUG_BCR 5 + +#endif From a4fe0e347bdaec314ea71961300483bc19a5d7f5 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 6 Apr 2026 14:50:04 +0530 Subject: [PATCH 0653/1330] FROMLIST: clk: qcom: camcc-glymur: Add camera clock controller driver Add support for the camera clock controller for camera clients to be able to request for camcc clocks on Glymur platform. Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260402-glymur_camcc-v1-2-e8da05a21da7@oss.qualcomm.com (cherry picked from commit 95651c63b27852b3cc7b9236d9db5642c0d4066f) --- drivers/clk/qcom/Kconfig | 36 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-glymur.c | 2280 +++++++++++++++++++++++++++++++ 3 files changed, 2317 insertions(+) create mode 100644 drivers/clk/qcom/camcc-glymur.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d45f0166ee04d..dbe88d8da3841 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -19,6 +19,42 @@ menuconfig COMMON_CLK_QCOM if COMMON_CLK_QCOM +config CLK_ELIZA_DISPCC + tristate "Eliza Display Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_ELIZA_GCC + help + Support for the display clock controllers on Eliza SoCs. + Say Y if you want to support display devices and functionality such as + splash screen. + +config CLK_ELIZA_GCC + tristate "Eliza Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on Eliza devices. + Say Y if you want to use peripheral devices such as UART, SPI, + I2C, USB, UFS, SDCC, etc. + +config CLK_ELIZA_TCSRCC + tristate "Eliza TCSR Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the TCSR clock controller on Eliza devices. + Say Y if you want to use peripheral devices such as USB/PCIe/UFS. + +config CLK_GLYMUR_CAMCC + tristate "Glymur Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_GLYMUR_GCC + help + Support for the camera clock controller on Qualcomm Technologies, Inc + Glymur devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config CLK_GLYMUR_DISPCC tristate "GLYMUR Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9daa97f5ecf99..21ade4469588c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -21,6 +21,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o +obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o diff --git a/drivers/clk/qcom/camcc-glymur.c b/drivers/clk/qcom/camcc-glymur.c new file mode 100644 index 0000000000000..b21e6830a72b4 --- /dev/null +++ b/drivers/clk/qcom/camcc-glymur.c @@ -0,0 +1,2280 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL2_OUT_MAIN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco rivian_eko_t_vco[] = { + { 883200000, 1171200000, 0 }, +}; + +static const struct pll_vco taycan_eko_t_vco[] = { + { 249600000, 2500000000, 0 }, +}; + +/* 1200.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x25c400e7, + .config_ctl_hi_val = 0x0a8060e0, + .config_ctl_hi1_val = 0xf51dea20, + .user_ctl_val = 0x00008408, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll0 = { + .offset = 0x0, + .config = &cam_cc_pll0_config, + .vco_table = taycan_eko_t_vco, + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { + .offset = 0x0, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll0_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 608.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll1_config = { + .l = 0x1f, + .alpha = 0xaaaa, + .config_ctl_val = 0x25c400e7, + .config_ctl_hi_val = 0x0a8060e0, + .config_ctl_hi1_val = 0xf51dea20, + .user_ctl_val = 0x00000408, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll1 = { + .offset = 0x1000, + .config = &cam_cc_pll1_config, + .vco_table = taycan_eko_t_vco, + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { + .offset = 0x1000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll1_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll2_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x12000000, + .config_ctl_hi_val = 0x00890263, + .config_ctl_hi1_val = 0x1af04237, + .config_ctl_hi2_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll2 = { + .offset = 0x2000, + .config = &cam_cc_pll2_config, + .vco_table = rivian_eko_t_vco, + .num_vco = ARRAY_SIZE(rivian_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_rivian_eko_t_ops, + }, + }, +}; + +/* 691.2 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll3_config = { + .l = 0x24, + .alpha = 0x0, + .config_ctl_val = 0x25c400e7, + .config_ctl_hi_val = 0x0a8060e0, + .config_ctl_hi1_val = 0xf51dea20, + .user_ctl_val = 0x00000408, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll3 = { + .offset = 0x3000, + .config = &cam_cc_pll3_config, + .vco_table = taycan_eko_t_vco, + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { + .offset = 0x3000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 691.2 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll4_config = { + .l = 0x24, + .alpha = 0x0, + .config_ctl_val = 0x25c400e7, + .config_ctl_hi_val = 0x0a8060e0, + .config_ctl_hi1_val = 0xf51dea20, + .user_ctl_val = 0x00000408, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll4 = { + .offset = 0x4000, + .config = &cam_cc_pll4_config, + .vco_table = taycan_eko_t_vco, + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { + .offset = 0x4000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll4_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll5_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x25c400e7, + .config_ctl_hi_val = 0x0a8060e0, + .config_ctl_hi1_val = 0xf51dea20, + .user_ctl_val = 0x00000408, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll5 = { + .offset = 0x5000, + .config = &cam_cc_pll5_config, + .vco_table = taycan_eko_t_vco, + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { + .offset = 0x5000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll5_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL5_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, + { .hw = &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll2.clkr.hw }, + { .hw = &cam_cc_pll2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_6_ao[] = { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { + { .index = DT_BI_TCXO_AO }, +}; + +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { + F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_bps_clk_src = { + .cmd_rcgr = 0x10278, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { + F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { + .cmd_rcgr = 0x137b4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { + F(30000000, P_CAM_CC_PLL5_OUT_EVEN, 16, 0, 0), + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src = { + .cmd_rcgr = 0x1350c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src = { + .cmd_rcgr = 0x1363c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { + .cmd_rcgr = 0x11168, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cphy_rx_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { + F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x150e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x15104, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { + .cmd_rcgr = 0x15124, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_csid_clk_src = { + .cmd_rcgr = 0x1378c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { + .cmd_rcgr = 0x10018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_fast_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_clk_src = { + .cmd_rcgr = 0x133cc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_icp_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { + F(345600000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src = { + .cmd_rcgr = 0x11018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { + F(345600000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_clk_src = { + .cmd_rcgr = 0x12018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ife_1_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { + F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { + .cmd_rcgr = 0x13000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0x13140, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { + F(304000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { + .cmd_rcgr = 0x103d0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_4, + .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk_src", + .parent_data = cam_cc_parent_data_4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { + F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src = { + .cmd_rcgr = 0x13284, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_jpeg_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), + F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src = { + .cmd_rcgr = 0x15000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src = { + .cmd_rcgr = 0x1501c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src = { + .cmd_rcgr = 0x15038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src = { + .cmd_rcgr = 0x15054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_mclk4_clk_src = { + .cmd_rcgr = 0x15070, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_mclk5_clk_src = { + .cmd_rcgr = 0x1508c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_mclk6_clk_src = { + .cmd_rcgr = 0x150a8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 cam_cc_mclk7_clk_src = { + .cmd_rcgr = 0x150c4, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { + F(60000000, P_CAM_CC_PLL5_OUT_EVEN, 8, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { + .cmd_rcgr = 0x137fc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src = { + .cmd_rcgr = 0x13964, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_5, + .freq_tbl = ftbl_cam_cc_sleep_clk_src, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sleep_clk_src", + .parent_data = cam_cc_parent_data_5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { + F(64000000, P_CAM_CC_PLL5_OUT_EVEN, 7.5, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { + .cmd_rcgr = 0x10148, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_slow_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src = { + .cmd_rcgr = 0x13948, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_6_ao, + .freq_tbl = ftbl_cam_cc_xo_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_xo_clk_src", + .parent_data = cam_cc_parent_data_6_ao, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_ahb_clk = { + .halt_reg = 0x10274, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10274, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_clk = { + .halt_reg = 0x103a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x103a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_fast_ahb_clk = { + .halt_reg = 0x10144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { + .halt_reg = 0x137e0, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x137e0, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x137e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_nrt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_rt_clk = { + .halt_reg = 0x137cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x137cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { + .halt_reg = 0x137f0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x137f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_dcd_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_xo_clk = { + .halt_reg = 0x137f4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x137f4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk = { + .halt_reg = 0x13638, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13638, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk = { + .halt_reg = 0x13768, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13768, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk = { + .halt_reg = 0x13944, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x13944, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_core_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk = { + .halt_reg = 0x1376c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1376c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_bps_clk = { + .halt_reg = 0x103b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x103b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_fast_ahb_clk = { + .halt_reg = 0x1377c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1377c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_0_clk = { + .halt_reg = 0x11154, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11154, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_1_clk = { + .halt_reg = 0x12040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_lite_clk = { + .halt_reg = 0x1313c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1313c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ipe_nps_clk = { + .halt_reg = 0x1050c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1050c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk = { + .halt_reg = 0x150f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk = { + .halt_reg = 0x1511c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1511c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk = { + .halt_reg = 0x15250, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15250, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk = { + .halt_reg = 0x137a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x137a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_csiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk = { + .halt_reg = 0x150fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk = { + .halt_reg = 0x15120, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk = { + .halt_reg = 0x15254, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15254, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_ahb_clk = { + .halt_reg = 0x13508, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13508, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk = { + .halt_reg = 0x134f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x134f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_icp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk = { + .halt_reg = 0x11144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_dsp_clk = { + .halt_reg = 0x11158, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11158, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_dsp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { + .halt_reg = 0x11164, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11164, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_clk = { + .halt_reg = 0x12030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_dsp_clk = { + .halt_reg = 0x12044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_dsp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { + .halt_reg = 0x12050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk = { + .halt_reg = 0x13280, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13280, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk = { + .halt_reg = 0x1312c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1312c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { + .halt_reg = 0x1327c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1327c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk = { + .halt_reg = 0x1326c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1326c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk = { + .halt_reg = 0x10528, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10528, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk = { + .halt_reg = 0x104fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x104fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { + .halt_reg = 0x1052c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1052c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk = { + .halt_reg = 0x10510, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10510, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { + .halt_reg = 0x10530, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10530, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk = { + .halt_reg = 0x133b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x133b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk = { + .halt_reg = 0x15018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk = { + .halt_reg = 0x15034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk = { + .halt_reg = 0x15050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk = { + .halt_reg = 0x1506c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1506c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk4_clk = { + .halt_reg = 0x15088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk5_clk = { + .halt_reg = 0x150a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk6_clk = { + .halt_reg = 0x150c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk7_clk = { + .halt_reg = 0x150dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk = { + .halt_reg = 0x13928, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13928, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk = { + .halt_reg = 0x1392c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1392c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc = { + .gdscr = 0x13930, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_titan_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_bps_gdsc = { + .gdscr = 0x10004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_bps_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_0_gdsc = { + .gdscr = 0x11004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_1_gdsc = { + .gdscr = 0x12004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc = { + .gdscr = 0x103bc, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ipe_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_glymur_clocks[] = { + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, + [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, + [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, + [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, + [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, + [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, + [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, + [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, + [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, + [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, + [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, + [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, + [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, + [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] = &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_glymur_gdscs[] = { + [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, + [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, + [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, + [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, + [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, +}; + +static const struct qcom_reset_map cam_cc_glymur_resets[] = { + [CAM_CC_BPS_BCR] = { 0x10000 }, + [CAM_CC_ICP_BCR] = { 0x133c8 }, + [CAM_CC_IFE_0_BCR] = { 0x11000 }, + [CAM_CC_IFE_1_BCR] = { 0x12000 }, + [CAM_CC_IPE_0_BCR] = { 0x103b8 }, + [CAM_CC_QDSS_DEBUG_BCR] = { 0x137f8 }, +}; + +static struct clk_alpha_pll *cam_cc_glymur_plls[] = { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, +}; + +static u32 cam_cc_glymur_critical_cbcrs[] = { + 0x13960, /* CAM_CC_GDSC_CLK */ + 0x1397c, /* CAM_CC_SLEEP_CLK */ +}; + +static const struct regmap_config cam_cc_glymur_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1603c, + .fast_io = true, +}; + +static struct qcom_cc_driver_data cam_cc_glymur_driver_data = { + .alpha_plls = cam_cc_glymur_plls, + .num_alpha_plls = ARRAY_SIZE(cam_cc_glymur_plls), + .clk_cbcrs = cam_cc_glymur_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(cam_cc_glymur_critical_cbcrs), +}; + +static const struct qcom_cc_desc cam_cc_glymur_desc = { + .config = &cam_cc_glymur_regmap_config, + .clks = cam_cc_glymur_clocks, + .num_clks = ARRAY_SIZE(cam_cc_glymur_clocks), + .resets = cam_cc_glymur_resets, + .num_resets = ARRAY_SIZE(cam_cc_glymur_resets), + .gdscs = cam_cc_glymur_gdscs, + .num_gdscs = ARRAY_SIZE(cam_cc_glymur_gdscs), + .use_rpm = true, + .driver_data = &cam_cc_glymur_driver_data, +}; + +static const struct of_device_id cam_cc_glymur_match_table[] = { + { .compatible = "qcom,glymur-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_glymur_match_table); + +static int cam_cc_glymur_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_cc_glymur_desc); +} + +static struct platform_driver cam_cc_glymur_driver = { + .probe = cam_cc_glymur_probe, + .driver = { + .name = "camcc-glymur", + .of_match_table = cam_cc_glymur_match_table, + }, +}; + +module_platform_driver(cam_cc_glymur_driver); + +MODULE_DESCRIPTION("QTI CAMCC GLYMUR Driver"); +MODULE_LICENSE("GPL"); From 2087f1e389be469b0a3e360cc0542fddad050a5a Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 3 Apr 2026 09:38:36 +0530 Subject: [PATCH 0654/1330] FROMLIST: cpuidle: Deny idle entry when CPU already have IPI interrupt pending CPU can get IPI interrupt from another CPU while it is executing cpuidle_select() or about to execute same. The selection do not account for pending interrupts and may continue to enter selected idle state only to exit immediately. Example trace collected when there is cross CPU IPI. [000] 154.892148: sched_waking: comm=sugov:4 pid=491 prio=-1 target_cpu=007 [000] 154.892148: ipi_raise: target_mask=00000000,00000080 (Function call interrupts) [007] 154.892162: cpu_idle: state=2 cpu_id=7 [007] 154.892208: cpu_idle: state=4294967295 cpu_id=7 [007] 154.892211: irq_handler_entry: irq=2 name=IPI [007] 154.892211: ipi_entry: (Function call interrupts) [007] 154.892213: sched_wakeup: comm=sugov:4 pid=491 prio=-1 target_cpu=007 [007] 154.892214: ipi_exit: (Function call interrupts) This impacts performance and the above count increments. commit ccde6525183c ("smp: Introduce a helper function to check for pending IPIs") already introduced a helper function to check the pending IPIs and it is used in pmdomain governor to deny the cluster level idle state when there is a pending IPI on any of cluster CPUs. This however does not stop CPU to enter CPU level idle state. Make use of same at CPUidle to deny the idle entry when there is already IPI pending. With change observing glmark2 [1] off screen scores improving in the range of 25% to 30% on Qualcomm lemans-evk board which is arm64 based having two clusters each with 4 CPUs. [1] https://github.com/glmark2/glmark2 Link: https://lore.kernel.org/r/20260403-cpuidle_ipi-v2-1-b3e44b032e2c@oss.qualcomm.com Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad (cherry picked from commit c7d331220fb1f9437c8a3cd76a08e3bf9530d01f) --- drivers/cpuidle/cpuidle.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c index c7876e9e024f9..c01e57df64ca5 100644 --- a/drivers/cpuidle/cpuidle.c +++ b/drivers/cpuidle/cpuidle.c @@ -224,6 +224,9 @@ noinstr int cpuidle_enter_state(struct cpuidle_device *dev, bool broadcast = !!(target_state->flags & CPUIDLE_FLAG_TIMER_STOP); ktime_t time_start, time_end; + if (cpus_peek_for_pending_ipi(cpumask_of(dev->cpu))) + return -EBUSY; + instrumentation_begin(); /* From 9d581753e73951e4d670ab5c31d054d41b30d6f1 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 31 Mar 2026 17:17:39 +0530 Subject: [PATCH 0655/1330] FROMLIST: dt-bindings: i2c: qcom,i2c-geni: Document multi-owner controller support Document a DeviceTree property to describe QUP-based I2C controllers that are shared with one or more other system processors. On some Qualcomm platforms, a QUP-based I2C controller may be accessed by multiple system processors (for example, APPS and DSP). In such configurations, the operating system must not assume exclusive ownership of the controller or its associated hardware resources. The new qcom,qup-multi-owner property indicates that the controller is externally shared and that the operating system must avoid operations which rely on sole control of the hardware. Link: https://lore.kernel.org/all/20260331114742.2896317-2-mukesh.savaliya@oss.qualcomm.com/ Signed-off-by: Mukesh Kumar Savaliya (cherry picked from commit e237543cbf2ad562d73e7b992a6eea48de54e23f) --- .../devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 51534953a69cf..9401dc2d50522 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -60,6 +60,13 @@ properties: power-domains: maxItems: 1 + qcom,qup-multi-owner: + type: boolean + description: + Indicates that the QUP-based controller is shared with one or more + other system processors and must not be assumed to have exclusive + ownership by the operating system. + reg: maxItems: 1 From ac0f6a098a18f921d397cde63a9e533ceff07101 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 31 Mar 2026 17:17:40 +0530 Subject: [PATCH 0656/1330] FROMLIST: dmaengine: qcom: gpi: Add lock/unlock TREs for multi-owner I2C transfers Some platforms use a QUP-based I2C controller in a configuration where the controller is shared with another system processor (described in DT using qcom,qup-multi-owner). In such setups, GPI hardware lock/unlock TREs can be used to serialize access to the controller. Add support to emit lock and unlock TREs around I2C transfers and increase the maximum TRE count to account for the additional elements. Also simplify the client interface by replacing multiple boolean fields (shared flag and message position tracking) with a single lock_action selector (acquire/release/none), as the GPI driver only needs to know whether to emit lock/unlock TREs for a given transfer. Link: https://lore.kernel.org/all/20260331114742.2896317-3-mukesh.savaliya@oss.qualcomm.com/ Signed-off-by: Mukesh Kumar Savaliya (cherry picked from commit 9586b3ee9a5899d65e4e64b03b3cb17ffb3eb1f2) --- drivers/dma/qcom/gpi.c | 44 +++++++++++++++++++++++++++++++- include/linux/dma/qcom-gpi-dma.h | 18 +++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index c9a6f610ffd9f..3cb20d854b00e 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020, Linaro Limited + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -67,6 +68,14 @@ #define TRE_DMA_LEN GENMASK(23, 0) #define TRE_DMA_IMMEDIATE_LEN GENMASK(3, 0) +/* Lock TRE */ +#define TRE_LOCK BIT(0) +#define TRE_MINOR_TYPE GENMASK(19, 16) +#define TRE_MAJOR_TYPE GENMASK(23, 20) + +/* Unlock TRE */ +#define TRE_UNLOCK BIT(8) + /* Register offsets from gpi-top */ #define GPII_n_CH_k_CNTXT_0_OFFS(n, k) (0x20000 + (0x4000 * (n)) + (0x80 * (k))) #define GPII_n_CH_k_CNTXT_0_EL_SIZE GENMASK(31, 24) @@ -518,7 +527,7 @@ struct gpii { bool ieob_set; }; -#define MAX_TRE 3 +#define MAX_TRE 5 struct gpi_desc { struct virt_dma_desc vd; @@ -1625,12 +1634,27 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, unsigned long flags) { struct gpi_i2c_config *i2c = chan->config; + enum gpi_lock_action lock_action = i2c->lock_action; struct device *dev = chan->gpii->gpi_dev->dev; unsigned int tre_idx = 0; dma_addr_t address; struct gpi_tre *tre; unsigned int i; + /* Optional lock TRE before transfer */ + if (lock_action == GPI_LOCK_ACQUIRE) { + tre = &desc->tre[tre_idx]; + tre_idx++; + + tre->dword[0] = 0; + tre->dword[1] = 0; + tre->dword[2] = 0; + tre->dword[3] = u32_encode_bits(1, TRE_LOCK); + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB); + tre->dword[3] |= u32_encode_bits(0, TRE_MINOR_TYPE); + tre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE); + } + /* first create config tre if applicable */ if (i2c->set_config) { tre = &desc->tre[tre_idx]; @@ -1690,6 +1714,24 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, if (!(flags & DMA_PREP_INTERRUPT)) tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_BEI); + + /* If multi-owner and this is the release boundary, chain it */ + if (i2c->lock_action == GPI_LOCK_RELEASE) + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); + } + + /* Optional unlock TRE after transfer */ + if (lock_action == GPI_LOCK_RELEASE && i2c->op != I2C_READ) { + tre = &desc->tre[tre_idx]; + tre_idx++; + + tre->dword[0] = 0; + tre->dword[1] = 0; + tre->dword[2] = 0; + tre->dword[3] = u32_encode_bits(1, TRE_UNLOCK); + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB); + tre->dword[3] |= u32_encode_bits(1, TRE_MINOR_TYPE); + tre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE); } for (i = 0; i < tre_idx; i++) diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h index 6680dd1a43c68..36cbb85499b4c 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2020, Linaro Limited + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef QCOM_GPI_DMA_H @@ -51,6 +52,21 @@ enum i2c_op { I2C_READ, }; +/** + * enum gpi_lock_action - request lock/unlock TRE sequencing + * @GPI_LOCK_NONE: No lock/unlock TRE requested for this transfer + * @GPI_LOCK_ACQUIRE: Emit a lock TRE before the transfer + * @GPI_LOCK_RELEASE: Emit an unlock TRE after the transfer + * + * Used by protocol drivers for multi-owner controller setups (e.g. when + * DeviceTree indicates the controller is shared via qcom,qup-multi-owner). + */ +enum gpi_lock_action { + GPI_LOCK_NONE = 0, + GPI_LOCK_ACQUIRE, + GPI_LOCK_RELEASE, +}; + /** * struct gpi_i2c_config - i2c config for peripheral * @@ -65,6 +81,7 @@ enum i2c_op { * @rx_len: receive length for buffer * @op: i2c cmd * @muli-msg: is part of multi i2c r-w msgs + * @lock_action: request lock/unlock TRE sequencing for this transfer */ struct gpi_i2c_config { u8 set_config; @@ -78,6 +95,7 @@ struct gpi_i2c_config { u32 rx_len; enum i2c_op op; bool multi_msg; + enum gpi_lock_action lock_action; }; #endif /* QCOM_GPI_DMA_H */ From dbc9f92771c4c01368037ad34fc3067fb9400822 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 31 Mar 2026 17:17:41 +0530 Subject: [PATCH 0657/1330] FROMLIST: soc: qcom: geni-se: Keep pinctrl active for multi-owner controllers On platforms where a GENI Serial Engine is shared with another system processor, selecting the "sleep" pinctrl state can disrupt ongoing transfers initiated by the other processor. Teach geni_se_resources_off() to skip selecting the pinctrl sleep state when the Serial Engine is marked as shared, while still allowing the rest of the resource shutdown sequence to proceed. This is required for multi-owner configurations (described via DeviceTree with qcom,qup-multi-owner on the protocol controller node). Link: https://lore.kernel.org/all/20260331114742.2896317-4-mukesh.savaliya@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Kumar Savaliya (cherry picked from commit 309f43904792bf00550bdc2ce604271f8decaa65) --- drivers/soc/qcom/qcom-geni-se.c | 15 +++++++++++---- include/linux/soc/qcom/geni-se.h | 2 ++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index cd1779b6a91a7..1a60832ace168 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -597,10 +597,17 @@ int geni_se_resources_off(struct geni_se *se) if (has_acpi_companion(se->dev)) return 0; - - ret = pinctrl_pm_select_sleep_state(se->dev); - if (ret) - return ret; + /* + * Select the "sleep" pinctrl state only when the serial engine is + * exclusively owned by this system processor. For shared controller + * configurations, another system processor may still be using the pins, + * and switching them to "sleep" can disrupt ongoing transfers. + */ + if (!se->multi_owner) { + ret = pinctrl_pm_select_sleep_state(se->dev); + if (ret) + return ret; + } geni_se_clks_off(se); return 0; diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 0a984e2579fe2..326744e311cea 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -63,6 +63,7 @@ struct geni_icc_path { * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE + * @multi_owner: True if SE is shared between multiprocessors. */ struct geni_se { void __iomem *base; @@ -72,6 +73,7 @@ struct geni_se { unsigned int num_clk_levels; unsigned long *clk_perf_tbl; struct geni_icc_path icc_paths[3]; + bool multi_owner; }; /* Common SE registers */ From 1bf7107789cbf0209c6a857d272872feb84e938f Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 31 Mar 2026 17:17:42 +0530 Subject: [PATCH 0658/1330] FROMLIST: i2c: qcom-geni: Support multi-owner controllers in GPI mode Some platforms use a QUP-based I2C controller in a configuration where the controller is shared with another system processor. In this setup the operating system must not assume exclusive ownership of the controller or its associated pins. Add support for enabling multi-owner operation when DeviceTree specifies qcom,qup-multi-owner. When enabled, mark the underlying serial engine as shared so the common GENI resource handling avoids selecting the "sleep" pinctrl state, which could disrupt transfers initiated by the other processor. For GPI mode transfers, request lock/unlock TRE sequencing from the GPI driver by setting a single lock_action selector per message, emitting lock before the first message and unlock after the last message (handling the single-message case as well). This serializes access to the shared controller without requiring message-position flags to be passed into the DMA engine layer. Link: https://lore.kernel.org/all/20260331114742.2896317-5-mukesh.savaliya@oss.qualcomm.com/ Signed-off-by: Mukesh Kumar Savaliya (cherry picked from commit d00f47452c64ad7f227539a67ae247421037f273) --- drivers/i2c/busses/i2c-qcom-geni.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index a4acb78fafb66..243dac7e483ed 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -815,6 +815,14 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i if (i < num - 1) peripheral.stretch = 1; + peripheral.lock_action = GPI_LOCK_NONE; + if (gi2c->se.multi_owner) { + if (i == 0) + peripheral.lock_action = GPI_LOCK_ACQUIRE; + else if (i == num - 1) + peripheral.lock_action = GPI_LOCK_RELEASE; + } + peripheral.addr = msgs[i].addr; if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) peripheral.multi_msg = false; @@ -1014,6 +1022,17 @@ static int geni_i2c_probe(struct platform_device *pdev) gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ; } + if (of_property_read_bool(pdev->dev.of_node, "qcom,qup-multi-owner")) { + /* + * Multi-owner controller configuration: the controller may be + * used by another system processor. Mark the SE as shared so + * common GENI resource handling can avoid pin state changes + * that would disrupt the other user. + */ + gi2c->se.multi_owner = true; + dev_dbg(&pdev->dev, "I2C controller is shared with another system processor\n"); + } + if (has_acpi_companion(dev)) ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); @@ -1089,7 +1108,9 @@ static int geni_i2c_probe(struct platform_device *pdev) } if (fifo_disable) { - /* FIFO is disabled, so we can only use GPI DMA */ + /* FIFO is disabled, so we can only use GPI DMA. + * SE can be shared in GSI mode between subsystems, each SS owns a GPII. + */ gi2c->gpi_mode = true; ret = setup_gpi_dma(gi2c); if (ret) @@ -1098,6 +1119,10 @@ static int geni_i2c_probe(struct platform_device *pdev) dev_dbg(dev, "Using GPI DMA mode for I2C\n"); } else { gi2c->gpi_mode = false; + + if (gi2c->se.multi_owner) + dev_err_probe(dev, -EINVAL, "I2C sharing not supported in non GSI mode\n"); + tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ From 2e57c4f8fe002bf9ee431fa19df0f284a78277d5 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 31 Mar 2026 17:47:12 +0530 Subject: [PATCH 0659/1330] WORKAROUND: i2c: qcom-geni: Fix -EACCES error during system resume When other drivers attempt I2C transfers during early resume phase, the I2C controller is still runtime suspended, causing pm_runtime_get_sync() to fail with -EACCES (-13): [ 101.914202] geni_i2c 980000.i2c: error turning SE resources:-13 The PM runtime core returns -EACCES when runtime PM is disabled (dev->power.disable_depth > 0). This occurs because: 1. During suspend_noirq, I2C driver calls geni_i2c_runtime_suspend() and then pm_runtime_disable() 2. I2C driver's noirq_resume only marks adapter as resumed but doesn't re-enable runtime PM or power up the hardware 3. Other drivers resuming later attempt I2C transfers 4. pm_runtime_get_sync() returns -EACCES because runtime PM is still disabled Fix this by calling pm_runtime_force_resume() in geni_i2c_resume_noirq() to properly resume the hardware and re-enable runtime PM during the noirq phase. This ensures the I2C controller is powered and ready for use when other drivers need it during resume. Upstream-Status: Pending Signed-off-by: Viken Dadhaniya Signed-off-by: Mukesh Kumar Savaliya (cherry picked from commit 6fe71bfe83c710423071f0109216a78a78b05e50) --- drivers/i2c/busses/i2c-qcom-geni.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 243dac7e483ed..0172f23d4c514 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -1050,8 +1050,14 @@ static int geni_i2c_probe(struct platform_device *pdev) spin_lock_init(&gi2c->lock); platform_set_drvdata(pdev, gi2c); - /* Keep interrupts disabled initially to allow for low-power modes */ - ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN, + /* + * Keep interrupts disabled initially to allow for low-power modes. + * IRQF_NO_SUSPEND: Keep IRQ enabled during suspend to handle I2C transfers + * in noirq phase (e.g., from PCIe driver's noirq_resume). + * IRQF_EARLY_RESUME: Enable IRQ early during resume sequence. + */ + ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, + IRQF_NO_AUTOEN | IRQF_NO_SUSPEND | IRQF_EARLY_RESUME, dev_name(dev), gi2c); if (ret) return dev_err_probe(dev, ret, @@ -1269,6 +1275,20 @@ static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) static int __maybe_unused geni_i2c_resume_noirq(struct device *dev) { struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); + int ret = 0; + + /* + * Resume hardware to handle I2C transfers from other drivers' + * noirq_resume callbacks (e.g., PCIe driver). + * pm_runtime_force_resume() properly handles PM state and usage_count. + */ + if (gi2c->suspended) { + ret = pm_runtime_force_resume(dev); + if (ret) { + dev_err(dev, "Failed to resume I2C during noirq: %d\n", ret); + return ret; + } + } i2c_mark_adapter_resumed(&gi2c->adap); return 0; From 4dc1ca9c27418ea6cc9a17b3d03414749c6b9f3e Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Thu, 25 Sep 2025 12:05:09 +0800 Subject: [PATCH 0660/1330] FROMLIT: drm/display: add hw_params callback function to drm_connector_hdmi_audio_ops After reusing drm_hdmi_audio_* helpers and drm_bridge_connector integration in drm/msm/dp, we have dropped msm_dp_audio_hw_params and use msm_dp_audio_prepare instead. While userspace is still calling hw_params to do audio initialization, and we get the following errors: q6apm-lpass-dais 3700000.remoteproc:glink-edge:gpr:service@1:bedais: q6apm_lpass_dai_prepare() started q6apm-lpass-dais 3700000.remoteproc:glink-edge:gpr:service@1:bedais: q6apm_lpass_dai_prepare() started q6apm-lpass-dais 3700000.remoteproc:glink-edge:gpr:service@1:bedais: q6apm_lpass_dai_prepare() started hdmi-audio-codec hdmi-audio-codec.0.auto: hdmi_codec_hw_params() started q6apm-lpass-dais 3700000.remoteproc:glink-edge:gpr:service@1:bedais: q6apm_lpass_dai_prepare() started qcom-apm gprsvc:service:2:1: Error (1) Processing 0x01001002 cmd qcom-apm gprsvc:service:2:1: DSP returned error[1001002] 1 q6apm-lpass-dais 3700000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to start APM port 104 q6apm-lpass-dais 3700000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC error (-22): at snd_soc_dai_prepare() on DISPLAY_PORT_RX_0 MultiMedia2 Playback: ASoC error (-22): at dpcm_run_update_startup() on MultiMedia2 Playback msm_dp_audio_prepare is not called because hdmi-codec driver only checks and runs hw_params before q6apm_lpass_dai_prepare(). This commit will add hw_params callback same as drm_connector_hdmi_audio_prepare, so that hdmi-codec driver can work with userspace alsa. Tested with Radxa Dragon Q6A. Link: https://lore.kernel.org/linux-arm-msm/20250925040530.20731-1-liujianfeng1994@gmail.com/ Fixes: 98a8920e7b07 ("drm/msm/dp: reuse generic HDMI codec implementation") Signed-off-by: Jianfeng Liu Tested-by: Krzysztof Kozlowski (cherry picked from commit 6b3f275f96732f6e6f279fb0bd2e6bca08ef172a) --- drivers/gpu/drm/display/drm_hdmi_audio_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/display/drm_hdmi_audio_helper.c b/drivers/gpu/drm/display/drm_hdmi_audio_helper.c index 7d78b02c14462..6ca1c7ad0632f 100644 --- a/drivers/gpu/drm/display/drm_hdmi_audio_helper.c +++ b/drivers/gpu/drm/display/drm_hdmi_audio_helper.c @@ -130,6 +130,7 @@ EXPORT_SYMBOL(drm_connector_hdmi_audio_plugged_notify); static const struct hdmi_codec_ops drm_connector_hdmi_audio_ops = { .audio_startup = drm_connector_hdmi_audio_startup, + .hw_params = drm_connector_hdmi_audio_prepare, .prepare = drm_connector_hdmi_audio_prepare, .audio_shutdown = drm_connector_hdmi_audio_shutdown, .mute_stream = drm_connector_hdmi_audio_mute_stream, From d958c5b8c4c9d38a45490f9d0ddaa48866dfb5db Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Sat, 14 Mar 2026 03:09:05 +0200 Subject: [PATCH 0661/1330] FROMLIST: drm/msm/dp: fix HPD state status bit shift value The HPD state status is the 3 most significant bits, not 4 bits of the HPD_INT_STATUS register. Fix the bit shift macro so that the correct bits are returned in msm_dp_aux_is_link_connected(). Fixes: 19e52bcb27c2 ("drm/msm/dp: return correct connection status after suspend") Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/all/20260314-hpd-refactor-v5-1-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit a3fc7d03c53df32cb656d111e31d2f088ed825fd) --- drivers/gpu/drm/msm/dp/dp_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 7c44d4e2cf139..3689642b7fc06 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -68,8 +68,8 @@ #define DP_DP_IRQ_HPD_INT_ACK (0x00000002) #define DP_DP_HPD_REPLUG_INT_ACK (0x00000004) #define DP_DP_HPD_UNPLUG_INT_ACK (0x00000008) -#define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F) -#define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C) +#define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x00000007) +#define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1D) #define REG_DP_DP_HPD_INT_MASK (0x0000000C) #define DP_DP_HPD_PLUG_INT_MASK (0x00000001) From 1a8fb0b9e39d40a872ce38638fe95c5afe617951 Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Sat, 14 Mar 2026 03:09:06 +0200 Subject: [PATCH 0662/1330] FROMLIST:drm/msm/dp: Fix the ISR_* enum values The ISR_HPD_* enum should represent values that can be read from the REG_DP_DP_HPD_INT_STATUS register. Swap ISR_HPD_IO_GLITCH_COUNT and ISR_HPD_REPLUG_COUNT to map them correctly to register values. While we are at it, correct the spelling for ISR_HPD_REPLUG_COUNT. Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-2-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit 11cf58a2f271d4b8a3d98414bbfd82d5f5edde83) --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index d2124d6254855..cf2415635c426 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -38,9 +38,9 @@ enum { ISR_DISCONNECTED, ISR_CONNECT_PENDING, ISR_CONNECTED, - ISR_HPD_REPLUG_COUNT, + ISR_HPD_IO_GLITCH_COUNT, ISR_IRQ_HPD_PULSE_COUNT, - ISR_HPD_LO_GLITH_COUNT, + ISR_HPD_REPLUG_COUNT, }; /* event thread connection state */ From 4b5e48b6711c7eca1137d0c9fc3a9f114faf3efd Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Sat, 14 Mar 2026 03:09:07 +0200 Subject: [PATCH 0663/1330] FROMLIST:drm/msm/dp: Read DPCD and sink count in bridge detect() Instead of relying on the link_ready flag to specify if DP is connected, read the DPCD bits and get the sink count to accurately detect if DP is connected. Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-3-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit 08c80c775163309e55004c86b6225f46b8465e65) --- drivers/gpu/drm/msm/dp/dp_display.c | 60 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_drm.c | 20 ---------- drivers/gpu/drm/msm/dp/dp_drm.h | 2 + 3 files changed, 62 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index cf2415635c426..df650a7dff0f5 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1152,6 +1152,66 @@ static int msm_dp_hpd_event_thread_start(struct msm_dp_display_private *msm_dp_p return 0; } +/** + * msm_dp_bridge_detect - callback to determine if connector is connected + * @bridge: Pointer to drm bridge structure + * @connector: Pointer to drm connector structure + * Returns: Bridge's 'is connected' status + */ +enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(bridge); + struct msm_dp *dp = msm_dp_bridge->msm_dp_display; + struct msm_dp_display_private *priv; + int ret = 0; + int status = connector_status_disconnected; + u8 dpcd[DP_RECEIVER_CAP_SIZE]; + struct drm_dp_desc desc; + + dp = to_dp_bridge(bridge)->msm_dp_display; + + priv = container_of(dp, struct msm_dp_display_private, msm_dp_display); + + if (!dp->link_ready) + return status; + + msm_dp_aux_enable_xfers(priv->aux, true); + + ret = pm_runtime_resume_and_get(&dp->pdev->dev); + if (ret) { + DRM_ERROR("failed to pm_runtime_resume\n"); + msm_dp_aux_enable_xfers(priv->aux, false); + return status; + } + + ret = msm_dp_aux_is_link_connected(priv->aux); + if (dp->internal_hpd && !ret) + goto end; + + ret = drm_dp_read_dpcd_caps(priv->aux, dpcd); + if (ret) + goto end; + + ret = drm_dp_read_desc(priv->aux, &desc, drm_dp_is_branch(dpcd)); + if (ret) + goto end; + + status = connector_status_connected; + if (drm_dp_read_sink_count_cap(connector, dpcd, &desc)) { + int sink_count = drm_dp_read_sink_count(priv->aux); + + drm_dbg_dp(dp->drm_dev, "sink_count = %d\n", sink_count); + + if (sink_count <= 0) + status = connector_status_disconnected; + } + +end: + pm_runtime_put_sync(&dp->pdev->dev); + return status; +} + static irqreturn_t msm_dp_display_irq_handler(int irq, void *dev_id) { struct msm_dp_display_private *dp = dev_id; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index fd6443d2b6cea..e4622c85fb66a 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -15,26 +15,6 @@ #include "dp_audio.h" #include "dp_drm.h" -/** - * msm_dp_bridge_detect - callback to determine if connector is connected - * @bridge: Pointer to drm bridge structure - * @connector: Pointer to drm connector structure - * Returns: Bridge's 'is connected' status - */ -static enum drm_connector_status -msm_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) -{ - struct msm_dp *dp; - - dp = to_dp_bridge(bridge)->msm_dp_display; - - drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", - str_true_false(dp->link_ready)); - - return (dp->link_ready) ? connector_status_connected : - connector_status_disconnected; -} - static int msm_dp_bridge_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h index 9eb3431dd93ad..6c0426803d78c 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -25,6 +25,8 @@ int msm_dp_bridge_init(struct msm_dp *msm_dp_display, struct drm_device *dev, struct drm_encoder *encoder, bool yuv_supported); +enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, + struct drm_connector *connector); void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, struct drm_atomic_state *state); void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, From b6d5f3242251ea3d731d4c059f33f2b9caca004d Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Sat, 14 Mar 2026 03:09:08 +0200 Subject: [PATCH 0664/1330] FROMLIST:drm/msm/dp: Move link training to atomic_enable() Currently, the DP link training is being done during HPD. Move link training to atomic_enable() in accordance with the atomic_enable() documentation. Link disabling is already done in atomic_post_disable() (as part of the dp_ctrl_off_link_stream() helper). Finally, call the plug/unplug handlers directly in hpd_notify() instead of queueing them in the event thread so that they aren't preempted by other events. Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-4-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit 62f68e4da80d727b02bb5936a87079840e464eb7) --- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index df650a7dff0f5..1bc792b3a7302 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -437,11 +437,6 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, false); msm_dp_link_reset_phy_params_vx_px(dp->link); - rc = msm_dp_ctrl_on_link(dp->ctrl); - if (rc) { - DRM_ERROR("failed to complete DP link training\n"); - goto end; - } msm_dp_add_event(dp, EV_USER_NOTIFICATION, true, 0); @@ -1696,6 +1691,11 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, force_link_train = true; } + rc = msm_dp_ctrl_on_link(msm_dp_display->ctrl); + if (rc) + DRM_ERROR("Failed link training (rc=%d)\n", rc); + // TODO: schedule drm_connector_set_link_status_property() + msm_dp_display_enable(msm_dp_display, force_link_train); rc = msm_dp_display_post_enable(dp); From 75d3e317ebbe86426dfba9d3f8965e2f33f2150e Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Sat, 14 Mar 2026 03:09:09 +0200 Subject: [PATCH 0665/1330] FROMLIST:drm/msm/dp: Drop EV_USER_NOTIFICATION Currently, we queue an event for signalling HPD connect/disconnect. This can mean a delay in plug/unplug handling and notifying DRM core when a hotplug happens. Drop EV_USER_NOTIFICATION and signal the IRQ event as part of hotplug handling. Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-5-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit 9c5d9263353f026e64672df372535fa448e527e1) --- drivers/gpu/drm/msm/dp/dp_display.c | 28 ++++++++-------------------- drivers/gpu/drm/msm/dp/dp_display.h | 1 + drivers/gpu/drm/msm/dp/dp_drm.c | 2 ++ 3 files changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 1bc792b3a7302..0c22f684ddf49 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -58,7 +58,6 @@ enum { EV_HPD_PLUG_INT, EV_IRQ_HPD_INT, EV_HPD_UNPLUG_INT, - EV_USER_NOTIFICATION, }; #define EVENT_TIMEOUT (HZ/10) /* 100ms */ @@ -344,17 +343,6 @@ static const struct component_ops msm_dp_display_comp_ops = { .unbind = msm_dp_display_unbind, }; -static void msm_dp_display_send_hpd_event(struct msm_dp *msm_dp_display) -{ - struct msm_dp_display_private *dp; - struct drm_connector *connector; - - dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - - connector = dp->msm_dp_display.connector; - drm_helper_hpd_irq_event(connector->dev); -} - static int msm_dp_display_send_hpd_notification(struct msm_dp_display_private *dp, bool hpd) { @@ -378,7 +366,11 @@ static int msm_dp_display_send_hpd_notification(struct msm_dp_display_private *d drm_dbg_dp(dp->drm_dev, "type=%d hpd=%d\n", dp->msm_dp_display.connector_type, hpd); - msm_dp_display_send_hpd_event(&dp->msm_dp_display); + + drm_bridge_hpd_notify(dp->msm_dp_display.bridge, + hpd ? + connector_status_connected : + connector_status_disconnected); return 0; } @@ -438,7 +430,7 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) msm_dp_link_reset_phy_params_vx_px(dp->link); - msm_dp_add_event(dp, EV_USER_NOTIFICATION, true, 0); + msm_dp_display_send_hpd_notification(dp, true); end: return rc; @@ -507,7 +499,7 @@ static int msm_dp_display_notify_disconnect(struct device *dev) { struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); - msm_dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); + msm_dp_display_send_hpd_notification(dp, false); return 0; } @@ -528,7 +520,7 @@ static int msm_dp_display_handle_port_status_changed(struct msm_dp_display_priva drm_dbg_dp(dp->drm_dev, "sink count is zero, nothing to do\n"); if (dp->hpd_state != ST_DISCONNECTED) { dp->hpd_state = ST_DISCONNECT_PENDING; - msm_dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); + msm_dp_display_send_hpd_notification(dp, false); } } else { if (dp->hpd_state == ST_DISCONNECTED) { @@ -1122,10 +1114,6 @@ static int hpd_event_thread(void *data) case EV_IRQ_HPD_INT: msm_dp_irq_hpd_handle(msm_dp_priv, todo->data); break; - case EV_USER_NOTIFICATION: - msm_dp_display_send_hpd_notification(msm_dp_priv, - todo->data); - break; default: break; } diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index cc6e2cab36e9c..60094061c1029 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -16,6 +16,7 @@ struct msm_dp { struct platform_device *pdev; struct drm_connector *connector; struct drm_bridge *next_bridge; + struct drm_bridge *bridge; bool link_ready; bool audio_enabled; bool power_on; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index e4622c85fb66a..f935093c4df46 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -340,6 +340,8 @@ int msm_dp_bridge_init(struct msm_dp *msm_dp_display, struct drm_device *dev, } } + msm_dp_display->bridge = bridge; + return 0; } From eeacd4d737bad0a15acc790bd561968be91cc7fb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 14 Mar 2026 03:09:10 +0200 Subject: [PATCH 0666/1330] FROMLIST:drm/msm/dp: drop event data With EV_USER_NOTIFICATION gone event's data is no longer useful. Drop it, removing also the argument from event handlers. Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-6-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit 440d9453e60aff5ed7caa0d8607ec0fc239df8f0) --- drivers/gpu/drm/msm/dp/dp_display.c | 39 +++++++++++++---------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 0c22f684ddf49..cd2bc5c12d432 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -69,7 +69,6 @@ enum { struct msm_dp_event { u32 event_id; - u32 data; u32 delay; }; @@ -219,7 +218,7 @@ static struct msm_dp_display_private *dev_get_dp_display_private(struct device * } static int msm_dp_add_event(struct msm_dp_display_private *msm_dp_priv, u32 event, - u32 data, u32 delay) + u32 delay) { unsigned long flag; struct msm_dp_event *todo; @@ -237,7 +236,6 @@ static int msm_dp_add_event(struct msm_dp_display_private *msm_dp_priv, u32 even todo = &msm_dp_priv->event_list[msm_dp_priv->event_pndx++]; msm_dp_priv->event_pndx %= DP_EVENT_Q_MAX; todo->event_id = event; - todo->data = data; todo->delay = delay; wake_up(&msm_dp_priv->event_q); spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); @@ -577,7 +575,7 @@ static int msm_dp_display_usbpd_attention_cb(struct device *dev) return rc; } -static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp, u32 data) +static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp) { u32 state; int ret; @@ -603,7 +601,7 @@ static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp, u32 data) if (state == ST_DISCONNECT_PENDING) { /* wait until ST_DISCONNECTED */ - msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0, 1); /* delay = 1 */ + msm_dp_add_event(dp, EV_HPD_PLUG_INT, 1); mutex_unlock(&dp->event_mutex); return 0; } @@ -645,7 +643,7 @@ static void msm_dp_display_handle_plugged_change(struct msm_dp *msm_dp_display, plugged); } -static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp, u32 data) +static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) { u32 state; struct platform_device *pdev = dp->msm_dp_display.pdev; @@ -707,7 +705,7 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp, u32 data) return 0; } -static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp, u32 data) +static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp) { u32 state; @@ -725,7 +723,7 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp, u32 data) if (state == ST_MAINLINK_READY || state == ST_DISCONNECT_PENDING) { /* wait until ST_CONNECTED */ - msm_dp_add_event(dp, EV_IRQ_HPD_INT, 0, 1); /* delay = 1 */ + msm_dp_add_event(dp, EV_IRQ_HPD_INT, 1); mutex_unlock(&dp->event_mutex); return 0; } @@ -1080,7 +1078,6 @@ static int hpd_event_thread(void *data) todo_next = &msm_dp_priv->event_list[msm_dp_priv->event_pndx++]; msm_dp_priv->event_pndx %= DP_EVENT_Q_MAX; todo_next->event_id = todo->event_id; - todo_next->data = todo->data; todo_next->delay = todo->delay - 1; /* clean up older event */ @@ -1106,13 +1103,13 @@ static int hpd_event_thread(void *data) switch (todo->event_id) { case EV_HPD_PLUG_INT: - msm_dp_hpd_plug_handle(msm_dp_priv, todo->data); + msm_dp_hpd_plug_handle(msm_dp_priv); break; case EV_HPD_UNPLUG_INT: - msm_dp_hpd_unplug_handle(msm_dp_priv, todo->data); + msm_dp_hpd_unplug_handle(msm_dp_priv); break; case EV_IRQ_HPD_INT: - msm_dp_irq_hpd_handle(msm_dp_priv, todo->data); + msm_dp_irq_hpd_handle(msm_dp_priv); break; default: break; @@ -1213,19 +1210,19 @@ static irqreturn_t msm_dp_display_irq_handler(int irq, void *dev_id) dp->msm_dp_display.connector_type, hpd_isr_status); /* hpd related interrupts */ if (hpd_isr_status & DP_DP_HPD_PLUG_INT_MASK) - msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0); + msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0); if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) { - msm_dp_add_event(dp, EV_IRQ_HPD_INT, 0, 0); + msm_dp_add_event(dp, EV_IRQ_HPD_INT, 0); } if (hpd_isr_status & DP_DP_HPD_REPLUG_INT_MASK) { - msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); - msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0, 3); + msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0); + msm_dp_add_event(dp, EV_HPD_PLUG_INT, 3); } if (hpd_isr_status & DP_DP_HPD_UNPLUG_INT_MASK) - msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); + msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0); ret = IRQ_HANDLED; } @@ -1650,7 +1647,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, } if (dp->is_edp) - msm_dp_hpd_plug_handle(msm_dp_display, 0); + msm_dp_hpd_plug_handle(msm_dp_display); mutex_lock(&msm_dp_display->event_mutex); if (pm_runtime_resume_and_get(&dp->pdev->dev)) { @@ -1722,7 +1719,7 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); if (dp->is_edp) - msm_dp_hpd_unplug_handle(msm_dp_display, 0); + msm_dp_hpd_unplug_handle(msm_dp_display); mutex_lock(&msm_dp_display->event_mutex); @@ -1844,7 +1841,7 @@ void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, return; if (!msm_dp_display->link_ready && status == connector_status_connected) - msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0); + msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0); else if (msm_dp_display->link_ready && status == connector_status_disconnected) - msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); + msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0); } From 2ee7597583ed395652d0182e7aec524b2eca59ba Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Mon, 4 May 2026 13:31:01 +0530 Subject: [PATCH 0667/1330] FROMLIST:drm/msm/dp: rework HPD handling Handling of the HPD events in the MSM DP driver is plagued with lots of problems. It tries to work aside of the main DRM framework, handling the HPD signals on its own. There are two separate paths, one for the HPD signals coming from the DP HPD pin and another path for signals coming from outside (e.g. from the Type-C AltMode). It lies about the connected state, returning the link established state instead. It is not easy to understand or modify it. Having a separate event machine doesn't add extra clarity. Drop the whole event machine. When the DP receives a HPD event, send it to the DRM core. Then handle the events in the hpd_notify callback, unifying paths for HPD signals. Signed-off-by: Jessica Zhang Co-developed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-7-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit c262e372027a2064d44faca02d062f1e2347ad66) --- drivers/gpu/drm/msm/dp/dp_ctrl.h | 1 - drivers/gpu/drm/msm/dp/dp_display.c | 601 +++++++--------------------- drivers/gpu/drm/msm/dp/dp_display.h | 1 - 3 files changed, 134 insertions(+), 469 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 124b9b21bb7f2..f68bee62713f1 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,6 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); -void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index cd2bc5c12d432..236791a46d3cb 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -43,35 +43,6 @@ enum { ISR_HPD_REPLUG_COUNT, }; -/* event thread connection state */ -enum { - ST_DISCONNECTED, - ST_MAINLINK_READY, - ST_CONNECTED, - ST_DISCONNECT_PENDING, - ST_DISPLAY_OFF, -}; - -enum { - EV_NO_EVENT, - /* hpd events */ - EV_HPD_PLUG_INT, - EV_IRQ_HPD_INT, - EV_HPD_UNPLUG_INT, -}; - -#define EVENT_TIMEOUT (HZ/10) /* 100ms */ -#define DP_EVENT_Q_MAX 8 - -#define DP_TIMEOUT_NONE 0 - -#define WAIT_FOR_RESUME_TIMEOUT_JIFFIES (HZ / 2) - -struct msm_dp_event { - u32 event_id; - u32 delay; -}; - struct msm_dp_display_private { int irq; @@ -95,15 +66,9 @@ struct msm_dp_display_private { /* wait for audio signaling */ struct completion audio_comp; - /* event related only access by event thread */ - struct mutex event_mutex; - wait_queue_head_t event_q; - u32 hpd_state; - u32 event_pndx; - u32 event_gndx; - struct task_struct *ev_tsk; - struct msm_dp_event event_list[DP_EVENT_Q_MAX]; - spinlock_t event_lock; + /* HPD IRQ handling */ + spinlock_t irq_thread_lock; + u32 hpd_isr_status; bool wide_bus_supported; @@ -217,59 +182,6 @@ static struct msm_dp_display_private *dev_get_dp_display_private(struct device * return container_of(dp, struct msm_dp_display_private, msm_dp_display); } -static int msm_dp_add_event(struct msm_dp_display_private *msm_dp_priv, u32 event, - u32 delay) -{ - unsigned long flag; - struct msm_dp_event *todo; - int pndx; - - spin_lock_irqsave(&msm_dp_priv->event_lock, flag); - pndx = msm_dp_priv->event_pndx + 1; - pndx %= DP_EVENT_Q_MAX; - if (pndx == msm_dp_priv->event_gndx) { - pr_err("event_q is full: pndx=%d gndx=%d\n", - msm_dp_priv->event_pndx, msm_dp_priv->event_gndx); - spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); - return -EPERM; - } - todo = &msm_dp_priv->event_list[msm_dp_priv->event_pndx++]; - msm_dp_priv->event_pndx %= DP_EVENT_Q_MAX; - todo->event_id = event; - todo->delay = delay; - wake_up(&msm_dp_priv->event_q); - spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); - - return 0; -} - -static int msm_dp_del_event(struct msm_dp_display_private *msm_dp_priv, u32 event) -{ - unsigned long flag; - struct msm_dp_event *todo; - u32 gndx; - - spin_lock_irqsave(&msm_dp_priv->event_lock, flag); - if (msm_dp_priv->event_pndx == msm_dp_priv->event_gndx) { - spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); - return -ENOENT; - } - - gndx = msm_dp_priv->event_gndx; - while (msm_dp_priv->event_pndx != gndx) { - todo = &msm_dp_priv->event_list[gndx]; - if (todo->event_id == event) { - todo->event_id = EV_NO_EVENT; /* deleted */ - todo->delay = 0; - } - gndx++; - gndx %= DP_EVENT_Q_MAX; - } - spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); - - return 0; -} - void msm_dp_display_signal_audio_start(struct msm_dp *msm_dp_display) { struct msm_dp_display_private *dp; @@ -288,8 +200,6 @@ void msm_dp_display_signal_audio_complete(struct msm_dp *msm_dp_display) complete_all(&dp->audio_comp); } -static int msm_dp_hpd_event_thread_start(struct msm_dp_display_private *msm_dp_priv); - static int msm_dp_display_bind(struct device *dev, struct device *master, void *data) { @@ -309,12 +219,6 @@ static int msm_dp_display_bind(struct device *dev, struct device *master, goto end; } - rc = msm_dp_hpd_event_thread_start(dp); - if (rc) { - DRM_ERROR("Event thread create failed\n"); - goto end; - } - return 0; end: return rc; @@ -326,8 +230,6 @@ static void msm_dp_display_unbind(struct device *dev, struct device *master, struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); struct msm_drm_private *priv = dev_get_drvdata(master); - kthread_stop(dp->ev_tsk); - of_dp_aux_depopulate_bus(dp->aux); msm_dp_aux_unregister(dp->aux); @@ -341,38 +243,6 @@ static const struct component_ops msm_dp_display_comp_ops = { .unbind = msm_dp_display_unbind, }; -static int msm_dp_display_send_hpd_notification(struct msm_dp_display_private *dp, - bool hpd) -{ - if ((hpd && dp->msm_dp_display.link_ready) || - (!hpd && !dp->msm_dp_display.link_ready)) { - drm_dbg_dp(dp->drm_dev, "HPD already %s\n", str_on_off(hpd)); - return 0; - } - - /* reset video pattern flag on disconnect */ - if (!hpd) { - dp->panel->video_test = false; - if (!dp->msm_dp_display.is_edp) - drm_dp_set_subconnector_property(dp->msm_dp_display.connector, - connector_status_disconnected, - dp->panel->dpcd, - dp->panel->downstream_ports); - } - - dp->msm_dp_display.link_ready = hpd; - - drm_dbg_dp(dp->drm_dev, "type=%d hpd=%d\n", - dp->msm_dp_display.connector_type, hpd); - - drm_bridge_hpd_notify(dp->msm_dp_display.bridge, - hpd ? - connector_status_connected : - connector_status_disconnected); - - return 0; -} - static int msm_dp_display_lttpr_init(struct msm_dp_display_private *dp, u8 *dpcd) { int rc, lttpr_count; @@ -415,6 +285,8 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) dp->panel->dpcd, dp->panel->downstream_ports); + dp->msm_dp_display.link_ready = true; + dp->msm_dp_display.psr_supported = dp->panel->psr_cap.version && psr_enabled; dp->audio_supported = info->has_audio; @@ -428,8 +300,6 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) msm_dp_link_reset_phy_params_vx_px(dp->link); - msm_dp_display_send_hpd_notification(dp, true); - end: return rc; } @@ -484,24 +354,6 @@ static void msm_dp_display_host_deinit(struct msm_dp_display_private *dp) dp->core_initialized = false; } -static int msm_dp_display_usbpd_configure_cb(struct device *dev) -{ - struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); - - msm_dp_display_host_phy_init(dp); - - return msm_dp_display_process_hpd_high(dp); -} - -static int msm_dp_display_notify_disconnect(struct device *dev) -{ - struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); - - msm_dp_display_send_hpd_notification(dp, false); - - return 0; -} - static void msm_dp_display_handle_video_request(struct msm_dp_display_private *dp) { if (dp->link->sink_request & DP_TEST_LINK_VIDEO_PATTERN) { @@ -510,34 +362,12 @@ static void msm_dp_display_handle_video_request(struct msm_dp_display_private *d } } -static int msm_dp_display_handle_port_status_changed(struct msm_dp_display_private *dp) -{ - int rc = 0; - - if (drm_dp_is_branch(dp->panel->dpcd) && dp->link->sink_count == 0) { - drm_dbg_dp(dp->drm_dev, "sink count is zero, nothing to do\n"); - if (dp->hpd_state != ST_DISCONNECTED) { - dp->hpd_state = ST_DISCONNECT_PENDING; - msm_dp_display_send_hpd_notification(dp, false); - } - } else { - if (dp->hpd_state == ST_DISCONNECTED) { - dp->hpd_state = ST_MAINLINK_READY; - rc = msm_dp_display_process_hpd_high(dp); - if (rc) - dp->hpd_state = ST_DISCONNECTED; - } - } - - return rc; -} - static int msm_dp_display_handle_irq_hpd(struct msm_dp_display_private *dp) { u32 sink_request = dp->link->sink_request; drm_dbg_dp(dp->drm_dev, "%d\n", sink_request); - if (dp->hpd_state == ST_DISCONNECTED) { + if (!dp->msm_dp_display.link_ready) { if (sink_request & DP_LINK_STATUS_UPDATED) { drm_dbg_dp(dp->drm_dev, "Disconnected sink_request: %d\n", sink_request); @@ -554,76 +384,36 @@ static int msm_dp_display_handle_irq_hpd(struct msm_dp_display_private *dp) return 0; } -static int msm_dp_display_usbpd_attention_cb(struct device *dev) -{ - int rc = 0; - u32 sink_request; - struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); - - /* check for any test request issued by sink */ - rc = msm_dp_link_process_request(dp->link); - if (!rc) { - sink_request = dp->link->sink_request; - drm_dbg_dp(dp->drm_dev, "hpd_state=%d sink_request=%d\n", - dp->hpd_state, sink_request); - if (sink_request & DS_PORT_STATUS_CHANGED) - rc = msm_dp_display_handle_port_status_changed(dp); - else - rc = msm_dp_display_handle_irq_hpd(dp); - } - - return rc; -} - static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp) { - u32 state; int ret; struct platform_device *pdev = dp->msm_dp_display.pdev; - msm_dp_aux_enable_xfers(dp->aux, true); - - mutex_lock(&dp->event_mutex); - - state = dp->hpd_state; - drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n", - dp->msm_dp_display.connector_type, state); - - if (state == ST_DISPLAY_OFF) { - mutex_unlock(&dp->event_mutex); - return 0; - } - - if (state == ST_MAINLINK_READY || state == ST_CONNECTED) { - mutex_unlock(&dp->event_mutex); - return 0; - } + drm_dbg_dp(dp->drm_dev, "Before, type=%d\n", + dp->msm_dp_display.connector_type); - if (state == ST_DISCONNECT_PENDING) { - /* wait until ST_DISCONNECTED */ - msm_dp_add_event(dp, EV_HPD_PLUG_INT, 1); - mutex_unlock(&dp->event_mutex); + if (dp->msm_dp_display.link_ready) return 0; - } ret = pm_runtime_resume_and_get(&pdev->dev); if (ret) { DRM_ERROR("failed to pm_runtime_resume\n"); - mutex_unlock(&dp->event_mutex); return ret; } - ret = msm_dp_display_usbpd_configure_cb(&pdev->dev); + msm_dp_aux_enable_xfers(dp->aux, true); + + msm_dp_display_host_phy_init(dp); + + ret = msm_dp_display_process_hpd_high(dp); if (ret) { /* link train failed */ - dp->hpd_state = ST_DISCONNECTED; + dp->msm_dp_display.link_ready = false; + msm_dp_aux_enable_xfers(dp->aux, false); pm_runtime_put_sync(&pdev->dev); - } else { - dp->hpd_state = ST_MAINLINK_READY; } - drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", - dp->msm_dp_display.connector_type, state); - mutex_unlock(&dp->event_mutex); + drm_dbg_dp(dp->drm_dev, "After, type=%d\n", + dp->msm_dp_display.connector_type); /* uevent will complete connection part */ return 0; @@ -645,97 +435,69 @@ static void msm_dp_display_handle_plugged_change(struct msm_dp *msm_dp_display, static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) { - u32 state; struct platform_device *pdev = dp->msm_dp_display.pdev; - msm_dp_aux_enable_xfers(dp->aux, false); - - mutex_lock(&dp->event_mutex); - - state = dp->hpd_state; + dp->panel->video_test = false; - drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n", - dp->msm_dp_display.connector_type, state); + msm_dp_aux_enable_xfers(dp->aux, false); - /* unplugged, no more irq_hpd handle */ - msm_dp_del_event(dp, EV_IRQ_HPD_INT); + drm_dbg_dp(dp->drm_dev, "Before, type=%d\n", + dp->msm_dp_display.connector_type); - if (state == ST_DISCONNECTED) { - /* triggered by irq_hdp with sink_count = 0 */ - if (dp->link->sink_count == 0) { - msm_dp_display_host_phy_exit(dp); - } - msm_dp_display_notify_disconnect(&dp->msm_dp_display.pdev->dev); - mutex_unlock(&dp->event_mutex); + if (!dp->msm_dp_display.link_ready) return 0; - } else if (state == ST_DISCONNECT_PENDING) { - mutex_unlock(&dp->event_mutex); - return 0; - } else if (state == ST_MAINLINK_READY) { - msm_dp_ctrl_off_link(dp->ctrl); + + /* triggered by irq_hdp with sink_count = 0 */ + if (dp->link->sink_count == 0) msm_dp_display_host_phy_exit(dp); - dp->hpd_state = ST_DISCONNECTED; - msm_dp_display_notify_disconnect(&dp->msm_dp_display.pdev->dev); - pm_runtime_put_sync(&pdev->dev); - mutex_unlock(&dp->event_mutex); - return 0; - } /* * We don't need separate work for disconnect as * connect/attention interrupts are disabled */ - msm_dp_display_notify_disconnect(&dp->msm_dp_display.pdev->dev); + if (!dp->msm_dp_display.is_edp) + drm_dp_set_subconnector_property(dp->msm_dp_display.connector, + connector_status_disconnected, + dp->panel->dpcd, + dp->panel->downstream_ports); - if (state == ST_DISPLAY_OFF) { - dp->hpd_state = ST_DISCONNECTED; - } else { - dp->hpd_state = ST_DISCONNECT_PENDING; - } + dp->msm_dp_display.link_ready = false; /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); - drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", - dp->msm_dp_display.connector_type, state); + drm_dbg_dp(dp->drm_dev, "After, type=%d\n", + dp->msm_dp_display.connector_type); /* uevent will complete disconnection part */ pm_runtime_put_sync(&pdev->dev); - mutex_unlock(&dp->event_mutex); return 0; } static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp) { - u32 state; - - mutex_lock(&dp->event_mutex); + u32 sink_request; + int rc = 0; /* irq_hpd can happen at either connected or disconnected state */ - state = dp->hpd_state; - drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n", - dp->msm_dp_display.connector_type, state); + drm_dbg_dp(dp->drm_dev, "Before, type=%d\n", + dp->msm_dp_display.connector_type); - if (state == ST_DISPLAY_OFF) { - mutex_unlock(&dp->event_mutex); - return 0; - } - - if (state == ST_MAINLINK_READY || state == ST_DISCONNECT_PENDING) { - /* wait until ST_CONNECTED */ - msm_dp_add_event(dp, EV_IRQ_HPD_INT, 1); - mutex_unlock(&dp->event_mutex); - return 0; + /* check for any test request issued by sink */ + rc = msm_dp_link_process_request(dp->link); + if (!rc) { + sink_request = dp->link->sink_request; + drm_dbg_dp(dp->drm_dev, "sink_request=%d\n", sink_request); + if (sink_request & DS_PORT_STATUS_CHANGED) + rc = msm_dp_display_process_hpd_high(dp); + else + rc = msm_dp_display_handle_irq_hpd(dp); } - msm_dp_display_usbpd_attention_cb(&dp->msm_dp_display.pdev->dev); + drm_dbg_dp(dp->drm_dev, "After, type=%d\n", + dp->msm_dp_display.connector_type); - drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", - dp->msm_dp_display.connector_type, state); - - mutex_unlock(&dp->event_mutex); - - return 0; + return rc; } static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_private *dp) @@ -1011,12 +773,8 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) * power_on status before dumping DP registers to avoid crash due * to unclocked access */ - mutex_lock(&msm_dp_display->event_mutex); - - if (!dp->power_on) { - mutex_unlock(&msm_dp_display->event_mutex); + if (!dp->power_on) return; - } msm_disp_snapshot_add_block(disp_state, msm_dp_display->ahb_len, msm_dp_display->ahb_base, "dp_ahb"); @@ -1026,8 +784,6 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) msm_dp_display->link_base, "dp_link"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, msm_dp_display->p0_base, "dp_p0"); - - mutex_unlock(&msm_dp_display->event_mutex); } void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) @@ -1043,95 +799,6 @@ void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) msm_dp_ctrl_set_psr(dp->ctrl, enter); } -static int hpd_event_thread(void *data) -{ - struct msm_dp_display_private *msm_dp_priv; - unsigned long flag; - struct msm_dp_event *todo; - int timeout_mode = 0; - - msm_dp_priv = (struct msm_dp_display_private *)data; - - while (1) { - if (timeout_mode) { - wait_event_timeout(msm_dp_priv->event_q, - (msm_dp_priv->event_pndx == msm_dp_priv->event_gndx) || - kthread_should_stop(), EVENT_TIMEOUT); - } else { - wait_event_interruptible(msm_dp_priv->event_q, - (msm_dp_priv->event_pndx != msm_dp_priv->event_gndx) || - kthread_should_stop()); - } - - if (kthread_should_stop()) - break; - - spin_lock_irqsave(&msm_dp_priv->event_lock, flag); - todo = &msm_dp_priv->event_list[msm_dp_priv->event_gndx]; - if (todo->delay) { - struct msm_dp_event *todo_next; - - msm_dp_priv->event_gndx++; - msm_dp_priv->event_gndx %= DP_EVENT_Q_MAX; - - /* re enter delay event into q */ - todo_next = &msm_dp_priv->event_list[msm_dp_priv->event_pndx++]; - msm_dp_priv->event_pndx %= DP_EVENT_Q_MAX; - todo_next->event_id = todo->event_id; - todo_next->delay = todo->delay - 1; - - /* clean up older event */ - todo->event_id = EV_NO_EVENT; - todo->delay = 0; - - /* switch to timeout mode */ - timeout_mode = 1; - spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); - continue; - } - - /* timeout with no events in q */ - if (msm_dp_priv->event_pndx == msm_dp_priv->event_gndx) { - spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); - continue; - } - - msm_dp_priv->event_gndx++; - msm_dp_priv->event_gndx %= DP_EVENT_Q_MAX; - timeout_mode = 0; - spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); - - switch (todo->event_id) { - case EV_HPD_PLUG_INT: - msm_dp_hpd_plug_handle(msm_dp_priv); - break; - case EV_HPD_UNPLUG_INT: - msm_dp_hpd_unplug_handle(msm_dp_priv); - break; - case EV_IRQ_HPD_INT: - msm_dp_irq_hpd_handle(msm_dp_priv); - break; - default: - break; - } - } - - return 0; -} - -static int msm_dp_hpd_event_thread_start(struct msm_dp_display_private *msm_dp_priv) -{ - /* set event q to empty */ - msm_dp_priv->event_gndx = 0; - msm_dp_priv->event_pndx = 0; - - msm_dp_priv->ev_tsk = kthread_run(hpd_event_thread, msm_dp_priv, "dp_hpd_handler"); - if (IS_ERR(msm_dp_priv->ev_tsk)) - return PTR_ERR(msm_dp_priv->ev_tsk); - - return 0; -} - /** * msm_dp_bridge_detect - callback to determine if connector is connected * @bridge: Pointer to drm bridge structure @@ -1156,26 +823,31 @@ enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, if (!dp->link_ready) return status; - msm_dp_aux_enable_xfers(priv->aux, true); - ret = pm_runtime_resume_and_get(&dp->pdev->dev); if (ret) { DRM_ERROR("failed to pm_runtime_resume\n"); - msm_dp_aux_enable_xfers(priv->aux, false); return status; } + msm_dp_aux_enable_xfers(priv->aux, true); + ret = msm_dp_aux_is_link_connected(priv->aux); - if (dp->internal_hpd && !ret) + if (!ret) { + DRM_DEBUG_DP("aux not connected\n"); goto end; + } ret = drm_dp_read_dpcd_caps(priv->aux, dpcd); - if (ret) + if (ret) { + DRM_DEBUG_DP("failed to read caps\n"); goto end; + } ret = drm_dp_read_desc(priv->aux, &desc, drm_dp_is_branch(dpcd)); - if (ret) + if (ret) { + DRM_DEBUG_DP("failed to read desc\n"); goto end; + } status = connector_status_connected; if (drm_dp_read_sink_count_cap(connector, dpcd, &desc)) { @@ -1195,36 +867,20 @@ enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, static irqreturn_t msm_dp_display_irq_handler(int irq, void *dev_id) { struct msm_dp_display_private *dp = dev_id; - irqreturn_t ret = IRQ_NONE; u32 hpd_isr_status; - - if (!dp) { - DRM_ERROR("invalid data\n"); - return IRQ_NONE; - } + unsigned long flags; + irqreturn_t ret = IRQ_HANDLED; hpd_isr_status = msm_dp_aux_get_hpd_intr_status(dp->aux); if (hpd_isr_status & 0x0F) { drm_dbg_dp(dp->drm_dev, "type=%d isr=0x%x\n", dp->msm_dp_display.connector_type, hpd_isr_status); - /* hpd related interrupts */ - if (hpd_isr_status & DP_DP_HPD_PLUG_INT_MASK) - msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0); - - if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) { - msm_dp_add_event(dp, EV_IRQ_HPD_INT, 0); - } - if (hpd_isr_status & DP_DP_HPD_REPLUG_INT_MASK) { - msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0); - msm_dp_add_event(dp, EV_HPD_PLUG_INT, 3); - } - - if (hpd_isr_status & DP_DP_HPD_UNPLUG_INT_MASK) - msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0); - - ret = IRQ_HANDLED; + spin_lock_irqsave(&dp->irq_thread_lock, flags); + dp->hpd_isr_status |= hpd_isr_status; + ret = IRQ_WAKE_THREAD; + spin_unlock_irqrestore(&dp->irq_thread_lock, flags); } /* DP controller isr */ @@ -1233,6 +889,36 @@ static irqreturn_t msm_dp_display_irq_handler(int irq, void *dev_id) return ret; } +static irqreturn_t msm_dp_display_irq_thread(int irq, void *dev_id) +{ + struct msm_dp_display_private *dp = dev_id; + irqreturn_t ret = IRQ_NONE; + unsigned long flags; + u32 hpd_isr_status; + + spin_lock_irqsave(&dp->irq_thread_lock, flags); + hpd_isr_status = dp->hpd_isr_status; + dp->hpd_isr_status = 0; + spin_unlock_irqrestore(&dp->irq_thread_lock, flags); + + if (hpd_isr_status & DP_DP_HPD_UNPLUG_INT_MASK) + drm_bridge_hpd_notify(dp->msm_dp_display.bridge, + connector_status_disconnected); + + if (hpd_isr_status & DP_DP_HPD_PLUG_INT_MASK) + drm_bridge_hpd_notify(dp->msm_dp_display.bridge, + connector_status_connected); + + /* Send HPD as connected and distinguish it in the notifier */ + if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) + drm_bridge_hpd_notify(dp->msm_dp_display.bridge, + connector_status_connected); + + ret = IRQ_HANDLED; + + return ret; +} + static int msm_dp_display_request_irq(struct msm_dp_display_private *dp) { int rc = 0; @@ -1244,9 +930,13 @@ static int msm_dp_display_request_irq(struct msm_dp_display_private *dp) return dp->irq; } - rc = devm_request_irq(&pdev->dev, dp->irq, msm_dp_display_irq_handler, - IRQF_TRIGGER_HIGH|IRQF_NO_AUTOEN, - "dp_display_isr", dp); + spin_lock_init(&dp->irq_thread_lock); + irq_set_status_flags(dp->irq, IRQ_NOAUTOEN); + rc = devm_request_threaded_irq(&pdev->dev, dp->irq, + msm_dp_display_irq_handler, + msm_dp_display_irq_thread, + IRQ_TYPE_LEVEL_HIGH, + "dp_display_isr", dp); if (rc < 0) { DRM_ERROR("failed to request IRQ%u: %d\n", @@ -1426,6 +1116,7 @@ static int msm_dp_display_probe(struct platform_device *pdev) dp->wide_bus_supported = desc->wide_bus_supported; dp->msm_dp_display.is_edp = (dp->msm_dp_display.connector_type == DRM_MODE_CONNECTOR_eDP); + dp->hpd_isr_status = 0; rc = msm_dp_display_get_io(dp); if (rc) @@ -1437,11 +1128,6 @@ static int msm_dp_display_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - /* setup event q */ - mutex_init(&dp->event_mutex); - init_waitqueue_head(&dp->event_q); - spin_lock_init(&dp->event_lock); - /* Store DP audio handle inside DP display */ dp->msm_dp_display.msm_dp_audio = dp->audio; @@ -1637,7 +1323,6 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, struct msm_dp *dp = msm_dp_bridge->msm_dp_display; int rc = 0; struct msm_dp_display_private *msm_dp_display; - u32 hpd_state; bool force_link_train = false; msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); @@ -1649,29 +1334,21 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, if (dp->is_edp) msm_dp_hpd_plug_handle(msm_dp_display); - mutex_lock(&msm_dp_display->event_mutex); if (pm_runtime_resume_and_get(&dp->pdev->dev)) { DRM_ERROR("failed to pm_runtime_resume\n"); - mutex_unlock(&msm_dp_display->event_mutex); return; } - hpd_state = msm_dp_display->hpd_state; - if (hpd_state != ST_DISPLAY_OFF && hpd_state != ST_MAINLINK_READY) { - mutex_unlock(&msm_dp_display->event_mutex); + if (msm_dp_display->link->sink_count == 0) return; - } rc = msm_dp_display_set_mode(dp, &msm_dp_display->msm_dp_mode); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=%d\n", rc); - mutex_unlock(&msm_dp_display->event_mutex); return; } - hpd_state = msm_dp_display->hpd_state; - - if (hpd_state == ST_DISPLAY_OFF) { + if (dp->link_ready && !dp->power_on) { msm_dp_display_host_phy_init(msm_dp_display); force_link_train = true; } @@ -1689,11 +1366,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, msm_dp_display_disable(msm_dp_display); } - /* completed connection */ - msm_dp_display->hpd_state = ST_CONNECTED; - drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type); - mutex_unlock(&msm_dp_display->event_mutex); } void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -1713,7 +1386,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, { struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = msm_dp_bridge->msm_dp_display; - u32 hpd_state; struct msm_dp_display_private *msm_dp_display; msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); @@ -1721,27 +1393,14 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, if (dp->is_edp) msm_dp_hpd_unplug_handle(msm_dp_display); - mutex_lock(&msm_dp_display->event_mutex); - - hpd_state = msm_dp_display->hpd_state; - if (hpd_state != ST_DISCONNECT_PENDING && hpd_state != ST_CONNECTED) - drm_dbg_dp(dp->drm_dev, "type=%d wrong hpd_state=%d\n", - dp->connector_type, hpd_state); + if (!dp->link_ready) + drm_dbg_dp(dp->drm_dev, "type=%d is disconnected\n", dp->connector_type); msm_dp_display_disable(msm_dp_display); - hpd_state = msm_dp_display->hpd_state; - if (hpd_state == ST_DISCONNECT_PENDING) { - /* completed disconnection */ - msm_dp_display->hpd_state = ST_DISCONNECTED; - } else { - msm_dp_display->hpd_state = ST_DISPLAY_OFF; - } - drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type); pm_runtime_put_sync(&dp->pdev->dev); - mutex_unlock(&msm_dp_display->event_mutex); } void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, @@ -1797,18 +1456,13 @@ void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) * step-4: DP PHY is initialized at plugin handler before link training * */ - mutex_lock(&dp->event_mutex); if (pm_runtime_resume_and_get(&msm_dp_display->pdev->dev)) { DRM_ERROR("failed to resume power\n"); - mutex_unlock(&dp->event_mutex); return; } msm_dp_aux_hpd_enable(dp->aux); msm_dp_aux_hpd_intr_enable(dp->aux); - - msm_dp_display->internal_hpd = true; - mutex_unlock(&dp->event_mutex); } void msm_dp_bridge_hpd_disable(struct drm_bridge *bridge) @@ -1817,15 +1471,10 @@ void msm_dp_bridge_hpd_disable(struct drm_bridge *bridge) struct msm_dp *msm_dp_display = msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - mutex_lock(&dp->event_mutex); - msm_dp_aux_hpd_intr_disable(dp->aux); msm_dp_aux_hpd_disable(dp->aux); - msm_dp_display->internal_hpd = false; - pm_runtime_put_sync(&msm_dp_display->pdev->dev); - mutex_unlock(&dp->event_mutex); } void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, @@ -1835,13 +1484,31 @@ void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(bridge); struct msm_dp *msm_dp_display = msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + u32 hpd_link_status = 0; - /* Without next_bridge interrupts are handled by the DP core directly */ - if (msm_dp_display->internal_hpd) + if (pm_runtime_resume_and_get(&msm_dp_display->pdev->dev)) { + DRM_ERROR("failed to pm_runtime_resume\n"); return; + } + + hpd_link_status = msm_dp_aux_is_link_connected(dp->aux); - if (!msm_dp_display->link_ready && status == connector_status_connected) - msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0); - else if (msm_dp_display->link_ready && status == connector_status_disconnected) - msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0); + drm_dbg_dp(dp->drm_dev, "type=%d link hpd_link_status=0x%x, link_ready=%d, status=%d\n", + msm_dp_display->connector_type, hpd_link_status, + msm_dp_display->link_ready, status); + + if (status == connector_status_connected) { + if (hpd_link_status == ISR_HPD_REPLUG_COUNT) { + msm_dp_hpd_unplug_handle(dp); + msm_dp_hpd_plug_handle(dp); + } else if (hpd_link_status == ISR_IRQ_HPD_PULSE_COUNT) { + msm_dp_irq_hpd_handle(dp); + } else { + msm_dp_hpd_plug_handle(dp); + } + } else { + msm_dp_hpd_unplug_handle(dp); + } + + pm_runtime_put_sync(&msm_dp_display->pdev->dev); } diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 60094061c1029..d2d3d61eb0b07 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -22,7 +22,6 @@ struct msm_dp { bool power_on; unsigned int connector_type; bool is_edp; - bool internal_hpd; struct msm_dp_audio *msm_dp_audio; bool psr_supported; From e0cdf47c07e38511a7a39eda2fc606f94b55a19f Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Sat, 14 Mar 2026 03:09:12 +0200 Subject: [PATCH 0668/1330] FROMLIST:drm/msm/dp: Add sink_count to debug logs Add sink count to the debug logs for [un]plug and HPD IRQ handling. Signed-off-by: Jessica Zhang [DB: dropped link_ready handling] Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-8-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit 0485e158b62551c21e1013bd372d525caec148fe) --- drivers/gpu/drm/msm/dp/dp_display.c | 30 +++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 236791a46d3cb..e8c6b3570a6f6 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -389,8 +389,9 @@ static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp) int ret; struct platform_device *pdev = dp->msm_dp_display.pdev; - drm_dbg_dp(dp->drm_dev, "Before, type=%d\n", - dp->msm_dp_display.connector_type); + drm_dbg_dp(dp->drm_dev, "Before, type=%d sink_count=%d\n", + dp->msm_dp_display.connector_type, + dp->link->sink_count); if (dp->msm_dp_display.link_ready) return 0; @@ -412,8 +413,9 @@ static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp) pm_runtime_put_sync(&pdev->dev); } - drm_dbg_dp(dp->drm_dev, "After, type=%d\n", - dp->msm_dp_display.connector_type); + drm_dbg_dp(dp->drm_dev, "After, type=%d sink_count=%d\n", + dp->msm_dp_display.connector_type, + dp->link->sink_count); /* uevent will complete connection part */ return 0; @@ -441,8 +443,9 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) msm_dp_aux_enable_xfers(dp->aux, false); - drm_dbg_dp(dp->drm_dev, "Before, type=%d\n", - dp->msm_dp_display.connector_type); + drm_dbg_dp(dp->drm_dev, "Before, type=%d sink_count=%d\n", + dp->msm_dp_display.connector_type, + dp->link->sink_count); if (!dp->msm_dp_display.link_ready) return 0; @@ -466,8 +469,9 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); - drm_dbg_dp(dp->drm_dev, "After, type=%d\n", - dp->msm_dp_display.connector_type); + drm_dbg_dp(dp->drm_dev, "After, type=%d, sink_count=%d\n", + dp->msm_dp_display.connector_type, + dp->link->sink_count); /* uevent will complete disconnection part */ pm_runtime_put_sync(&pdev->dev); @@ -480,8 +484,9 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp) int rc = 0; /* irq_hpd can happen at either connected or disconnected state */ - drm_dbg_dp(dp->drm_dev, "Before, type=%d\n", - dp->msm_dp_display.connector_type); + drm_dbg_dp(dp->drm_dev, "Before, type=%d, sink_count=%d\n", + dp->msm_dp_display.connector_type, + dp->link->sink_count); /* check for any test request issued by sink */ rc = msm_dp_link_process_request(dp->link); @@ -494,8 +499,9 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp) rc = msm_dp_display_handle_irq_hpd(dp); } - drm_dbg_dp(dp->drm_dev, "After, type=%d\n", - dp->msm_dp_display.connector_type); + drm_dbg_dp(dp->drm_dev, "After, type=%d, sink_count=%d\n", + dp->msm_dp_display.connector_type, + dp->link->sink_count); return rc; } From 6a17360252ce2b96e352a8751d770f25c21e493e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 14 Mar 2026 03:09:13 +0200 Subject: [PATCH 0669/1330] FROMLIST:drm/msm/dp: turn link_ready into plugged Tracking when the DP link is ready isn't that useful from the driver point of view. It doesn't provide a direct information if the device should be suspended, etc. Replace it with the 'plugged' boolean, which is set when the driver knows that there is DPRX plugged. Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-9-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit 27afe10194732094da0fcb6d5446a4a85963ca40) --- drivers/gpu/drm/msm/dp/dp_display.c | 94 +++++++++++++++++------------ drivers/gpu/drm/msm/dp/dp_display.h | 1 - drivers/gpu/drm/msm/dp/dp_drm.c | 41 ++----------- 3 files changed, 61 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index e8c6b3570a6f6..8eafed4b693d3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -53,6 +53,9 @@ struct msm_dp_display_private { bool phy_initialized; bool audio_supported; + struct mutex plugged_lock; + bool plugged; + struct drm_device *drm_dev; struct drm_dp_aux *aux; @@ -285,8 +288,6 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) dp->panel->dpcd, dp->panel->downstream_ports); - dp->msm_dp_display.link_ready = true; - dp->msm_dp_display.psr_supported = dp->panel->psr_cap.version && psr_enabled; dp->audio_supported = info->has_audio; @@ -304,7 +305,7 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) return rc; } -static void msm_dp_display_host_phy_init(struct msm_dp_display_private *dp) +static bool msm_dp_display_host_phy_init(struct msm_dp_display_private *dp) { drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n", dp->msm_dp_display.connector_type, dp->core_initialized, @@ -313,7 +314,10 @@ static void msm_dp_display_host_phy_init(struct msm_dp_display_private *dp) if (!dp->phy_initialized) { msm_dp_ctrl_phy_init(dp->ctrl); dp->phy_initialized = true; + return true; } + + return false; } static void msm_dp_display_host_phy_exit(struct msm_dp_display_private *dp) @@ -367,14 +371,6 @@ static int msm_dp_display_handle_irq_hpd(struct msm_dp_display_private *dp) u32 sink_request = dp->link->sink_request; drm_dbg_dp(dp->drm_dev, "%d\n", sink_request); - if (!dp->msm_dp_display.link_ready) { - if (sink_request & DP_LINK_STATUS_UPDATED) { - drm_dbg_dp(dp->drm_dev, "Disconnected sink_request: %d\n", - sink_request); - DRM_ERROR("Disconnected, no DP_LINK_STATUS_UPDATED\n"); - return -EINVAL; - } - } msm_dp_ctrl_handle_sink_request(dp->ctrl); @@ -393,11 +389,11 @@ static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp) dp->msm_dp_display.connector_type, dp->link->sink_count); - if (dp->msm_dp_display.link_ready) - return 0; + mutex_lock(&dp->plugged_lock); ret = pm_runtime_resume_and_get(&pdev->dev); if (ret) { + mutex_unlock(&dp->plugged_lock); DRM_ERROR("failed to pm_runtime_resume\n"); return ret; } @@ -407,18 +403,16 @@ static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp) msm_dp_display_host_phy_init(dp); ret = msm_dp_display_process_hpd_high(dp); - if (ret) { /* link train failed */ - dp->msm_dp_display.link_ready = false; - msm_dp_aux_enable_xfers(dp->aux, false); - pm_runtime_put_sync(&pdev->dev); - } drm_dbg_dp(dp->drm_dev, "After, type=%d sink_count=%d\n", dp->msm_dp_display.connector_type, dp->link->sink_count); - /* uevent will complete connection part */ - return 0; + dp->plugged = true; + + mutex_unlock(&dp->plugged_lock); + + return ret; }; static void msm_dp_display_handle_plugged_change(struct msm_dp *msm_dp_display, @@ -447,8 +441,12 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) dp->msm_dp_display.connector_type, dp->link->sink_count); - if (!dp->msm_dp_display.link_ready) + mutex_lock(&dp->plugged_lock); + if (!dp->plugged) { + mutex_unlock(&dp->plugged_lock); + return 0; + } /* triggered by irq_hdp with sink_count = 0 */ if (dp->link->sink_count == 0) @@ -464,8 +462,6 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) dp->panel->dpcd, dp->panel->downstream_ports); - dp->msm_dp_display.link_ready = false; - /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); @@ -473,8 +469,12 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) dp->msm_dp_display.connector_type, dp->link->sink_count); - /* uevent will complete disconnection part */ - pm_runtime_put_sync(&pdev->dev); + if (dp->plugged) { + pm_runtime_put_sync(&pdev->dev); + dp->plugged = false; + } + mutex_unlock(&dp->plugged_lock); + return 0; } @@ -821,41 +821,49 @@ enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, int status = connector_status_disconnected; u8 dpcd[DP_RECEIVER_CAP_SIZE]; struct drm_dp_desc desc; + bool phy_deinit; dp = to_dp_bridge(bridge)->msm_dp_display; priv = container_of(dp, struct msm_dp_display_private, msm_dp_display); - if (!dp->link_ready) - return status; - + mutex_lock(&priv->plugged_lock); ret = pm_runtime_resume_and_get(&dp->pdev->dev); if (ret) { DRM_ERROR("failed to pm_runtime_resume\n"); + mutex_unlock(&priv->plugged_lock); return status; } + phy_deinit = msm_dp_display_host_phy_init(priv); + msm_dp_aux_enable_xfers(priv->aux, true); ret = msm_dp_aux_is_link_connected(priv->aux); - if (!ret) { + DRM_DEBUG_DP("aux link status: %x\n", ret); + if (!priv->plugged && !ret) { DRM_DEBUG_DP("aux not connected\n"); + priv->plugged = false; goto end; } ret = drm_dp_read_dpcd_caps(priv->aux, dpcd); if (ret) { DRM_DEBUG_DP("failed to read caps\n"); + priv->plugged = false; goto end; } ret = drm_dp_read_desc(priv->aux, &desc, drm_dp_is_branch(dpcd)); if (ret) { DRM_DEBUG_DP("failed to read desc\n"); + priv->plugged = false; goto end; } status = connector_status_connected; + priv->plugged = true; + if (drm_dp_read_sink_count_cap(connector, dpcd, &desc)) { int sink_count = drm_dp_read_sink_count(priv->aux); @@ -866,7 +874,21 @@ enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, } end: - pm_runtime_put_sync(&dp->pdev->dev); + /* + * If we detected the DPRX, leave the controller on so that it doesn't + * loose the state. + */ + if (!priv->plugged) { + if (phy_deinit) { + msm_dp_aux_enable_xfers(priv->aux, false); + msm_dp_display_host_phy_exit(priv); + } + + pm_runtime_put_sync(&dp->pdev->dev); + } + + mutex_unlock(&priv->plugged_lock); + return status; } @@ -1124,6 +1146,8 @@ static int msm_dp_display_probe(struct platform_device *pdev) (dp->msm_dp_display.connector_type == DRM_MODE_CONNECTOR_eDP); dp->hpd_isr_status = 0; + mutex_init(&dp->plugged_lock); + rc = msm_dp_display_get_io(dp); if (rc) return rc; @@ -1354,7 +1378,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, return; } - if (dp->link_ready && !dp->power_on) { + if (!dp->power_on) { msm_dp_display_host_phy_init(msm_dp_display); force_link_train = true; } @@ -1399,9 +1423,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, if (dp->is_edp) msm_dp_hpd_unplug_handle(msm_dp_display); - if (!dp->link_ready) - drm_dbg_dp(dp->drm_dev, "type=%d is disconnected\n", dp->connector_type); - msm_dp_display_disable(msm_dp_display); drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type); @@ -1499,9 +1520,8 @@ void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, hpd_link_status = msm_dp_aux_is_link_connected(dp->aux); - drm_dbg_dp(dp->drm_dev, "type=%d link hpd_link_status=0x%x, link_ready=%d, status=%d\n", - msm_dp_display->connector_type, hpd_link_status, - msm_dp_display->link_ready, status); + drm_dbg_dp(dp->drm_dev, "type=%d link hpd_link_status=0x%x, status=%d\n", + msm_dp_display->connector_type, hpd_link_status, status); if (status == connector_status_connected) { if (hpd_link_status == ISR_HPD_REPLUG_COUNT) { diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index d2d3d61eb0b07..0b65e16c790da 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -17,7 +17,6 @@ struct msm_dp { struct drm_connector *connector; struct drm_bridge *next_bridge; struct drm_bridge *bridge; - bool link_ready; bool audio_enabled; bool power_on; unsigned int connector_type; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index f935093c4df46..8dc0dabd275cd 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -15,36 +15,6 @@ #include "dp_audio.h" #include "dp_drm.h" -static int msm_dp_bridge_atomic_check(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct msm_dp *dp; - - dp = to_dp_bridge(bridge)->msm_dp_display; - - drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", - str_true_false(dp->link_ready)); - - /* - * There is no protection in the DRM framework to check if the display - * pipeline has been already disabled before trying to disable it again. - * Hence if the sink is unplugged, the pipeline gets disabled, but the - * crtc->active is still true. Any attempt to set the mode or manually - * disable this encoder will result in the crash. - * - * TODO: add support for telling the DRM subsystem that the pipeline is - * disabled by the hardware and thus all access to it should be forbidden. - * After that this piece of code can be removed. - */ - if (bridge->ops & DRM_BRIDGE_OP_HPD) - return (dp->link_ready) ? 0 : -ENOTCONN; - - return 0; -} - - /** * msm_dp_bridge_get_modes - callback to add drm modes via drm_mode_probed_add() * @bridge: Poiner to drm bridge @@ -62,12 +32,10 @@ static int msm_dp_bridge_get_modes(struct drm_bridge *bridge, struct drm_connect dp = to_dp_bridge(bridge)->msm_dp_display; /* pluggable case assumes EDID is read when HPD */ - if (dp->link_ready) { - rc = msm_dp_display_get_modes(dp); - if (rc <= 0) { - DRM_ERROR("failed to get DP sink modes, rc=%d\n", rc); - return rc; - } + rc = msm_dp_display_get_modes(dp); + if (rc <= 0) { + DRM_ERROR("failed to get DP sink modes, rc=%d\n", rc); + return rc; } else { drm_dbg_dp(connector->dev, "No sink connected\n"); } @@ -92,7 +60,6 @@ static const struct drm_bridge_funcs msm_dp_bridge_ops = { .mode_valid = msm_dp_bridge_mode_valid, .get_modes = msm_dp_bridge_get_modes, .detect = msm_dp_bridge_detect, - .atomic_check = msm_dp_bridge_atomic_check, .hpd_enable = msm_dp_bridge_hpd_enable, .hpd_disable = msm_dp_bridge_hpd_disable, .hpd_notify = msm_dp_bridge_hpd_notify, From 52961d0a093d1773d93221464af4d3652fe3b1cf Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 14 Mar 2026 03:09:14 +0200 Subject: [PATCH 0670/1330] FROMLIST:drm/msm/dp: clear EDID on display unplug Currently the driver only updates the EDID when it detects a connected monitor, which results in the connector still listing outdated modes even after the display is unplugged. Set connector's EDID to NULL on unplug to clear the list of modes. Signed-off-by: Dmitry Baryshkov Link:https://lore.kernel.org/all/20260314-hpd-refactor-v5-10-0c8450737d64@oss.qualcomm.com/ (cherry picked from commit 9b75bf511619dfd178a3e39d999fd59965a556ce) --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ drivers/gpu/drm/msm/dp/dp_panel.c | 8 ++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 8eafed4b693d3..7ac4b8dd372ae 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -448,6 +448,10 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) return 0; } + /* Don't forget modes for eDP */ + if (!dp->msm_dp_display.is_edp) + msm_dp_panel_unplugged(dp->panel, dp->msm_dp_display.connector); + /* triggered by irq_hdp with sink_count = 0 */ if (dp->link->sink_count == 0) msm_dp_display_host_phy_exit(dp); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 891211b232023..6bb021820d7c5 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -293,6 +293,14 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, return rc; } +void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector) +{ + drm_edid_connector_update(connector, NULL); + drm_edid_free(msm_dp_panel->drm_edid); + msm_dp_panel->drm_edid = NULL; +} + u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_edid_bpp, u32 mode_pclk_khz) { diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 177c1328fd997..9173e90a50530 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -49,6 +49,8 @@ int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en); int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, struct drm_connector *connector); +void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector); u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_max_bpp, u32 mode_pclk_khz); int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, From 98ca6857f3f9a4777100959e7126403dad971d7d Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Sun, 19 Apr 2026 15:45:56 +0530 Subject: [PATCH 0671/1330] FROMLIST: phy: qualcomm: qmp-combo: update DP PHY PLL programming on Glymur The existing DP PHY PLL and AUX configuration for the Glymur platform does not fully follow the Hardware Programming Guide requirements for DP over Type-C, which results in DP link bring-up failures. Update the DP PHY programming sequence and PLL-related register settings to align with the latest HPG recommendations. With this change, DP link training completes successfully on Glymur-based platforms. Fixes: d10736db98d2 ("phy: qualcomm: qmp-combo: Add DP offsets and settings for Glymur platforms") Link: https://lore.kernel.org/r/20260419-glymur_dp-v1-1-ad1067a8e8ae@oss.qualcomm.com Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P (cherry picked from commit a366b4f0d4a51ed7dffe9717666cbda052b02cb6) --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 213 +++++++++++++----- .../qualcomm/phy-qcom-qmp-qserdes-com-v8.h | 2 + 2 files changed, 154 insertions(+), 61 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 93f1aa10d4008..bb5e4091fd0c9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -283,8 +283,8 @@ static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_DP_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE, [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, - [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, - [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, + [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS_N3, + [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS_N3, [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, [QPHY_DP_PHY_STATUS] = QSERDES_V8_DP_PHY_STATUS, @@ -1386,10 +1386,10 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = { }; static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), @@ -1404,12 +1404,13 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x56), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), @@ -1445,26 +1446,26 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = { }; static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x1a), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VMODE_CTRL1, 0x40), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT1, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x18), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x50), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0d), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x87), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRAN_DRVR_EMP_EN, 0x5f), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x2b), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_PRE1_EMPH, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_PRE1_EMPH, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_DRV_LVL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_DRV_LVL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x3f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x50), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x51), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x0c), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), @@ -1589,11 +1590,12 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = { static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_rbr[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x7a), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x8d), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x27), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x83), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x37), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x54), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x06), @@ -1601,16 +1603,17 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_rbr[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa4), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa7), }; static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x21), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x08), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), @@ -1627,7 +1630,8 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr2[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x10), @@ -1637,9 +1641,9 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr2[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x17), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x03), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), @@ -1647,8 +1651,8 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr2[] = { static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr3[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x63), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x25), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x5b), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), @@ -1656,7 +1660,7 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr3[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x18), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x15), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x4f), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), @@ -1675,19 +1679,19 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr3[] = { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x17), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x05), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0x84), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0x87), }; static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { @@ -3145,6 +3149,30 @@ static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) return 0; } +static bool qmp_v8_combo_configure_dp_mode(struct qmp_combo *qmp) +{ + bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; + u32 val; + + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; + + if (dp_opts->lanes == 1 || dp_opts->lanes == 2) { + if (reverse) + val &= ~DP_PHY_PD_CTL_LANE_2_3_PWRDN; + else + val &= ~DP_PHY_PD_CTL_LANE_0_1_PWRDN; + } + + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); + + return reverse; +} + static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) { const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; @@ -3324,16 +3352,70 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); } +static int qmp_v8_helper_configure_dp_phy(struct qmp_combo *qmp) +{ + const struct qmp_phy_cfg *cfg = qmp->cfg; + u32 status; + int ret; + + writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); + + qmp_v8_combo_configure_dp_mode(qmp); + + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); + writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); + + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); + + ret = qmp->cfg->configure_dp_clocks(qmp); + if (ret) + return ret; + + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + return 0; +} + static void qmp_v8_dp_aux_init(struct qmp_combo *qmp) { const struct qmp_phy_cfg *cfg = qmp->cfg; - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + writel(0x3f, qmp->dp_serdes + QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1); + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); /* Turn on BIAS current for PHY/PLL */ - writel(0x1c, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); + writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); @@ -3361,8 +3443,8 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); - writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); - writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); + writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); + writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); qmp_combo_configure_dp_swing(qmp); } @@ -3370,48 +3452,41 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp) { const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; - u32 phy_vco_div; unsigned long pixel_freq; - const struct qmp_phy_cfg *cfg = qmp->cfg; switch (dp_opts->link_rate) { case 1620: - phy_vco_div = 0x4; pixel_freq = 1620000000UL / 2; break; case 2700: - phy_vco_div = 0x2; pixel_freq = 2700000000UL / 2; break; case 5400: - phy_vco_div = 0x4; pixel_freq = 5400000000UL / 4; break; case 8100: - phy_vco_div = 0x3; pixel_freq = 8100000000UL / 6; break; default: /* Other link rates aren't supported */ return -EINVAL; } - writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); /* disable core reset tsync */ writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - writel(0x04, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); - writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); + writel(0x09, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); + writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_CYC); - writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); + writel(0x33, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL); writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL); writel(0x01, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_CFG1); - writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); + writel(0x33, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN0_DRV_LVL); - writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); + writel(0x02, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); @@ -3558,7 +3633,7 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) u32 status; int ret; - ret = qmp_v456_configure_dp_phy(qmp); + ret = qmp_v8_helper_configure_dp_phy(qmp); if (ret < 0) return ret; @@ -3570,13 +3645,13 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) } else if (dp_opts->lanes == 2) { bias0_en = reverse ? 0x3f : 0x15; bias1_en = reverse ? 0x15 : 0x3f; - drvr0_en = 0x10; - drvr1_en = 0x10; + drvr0_en = 0x30; + drvr1_en = 0x30; } else { bias0_en = 0x3f; bias1_en = 0x3f; - drvr0_en = 0x34; - drvr1_en = 0x34; + drvr0_en = 0x30; + drvr1_en = 0x30; } writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); @@ -3584,6 +3659,14 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); + writel(0x03, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + writel(0x23, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + writel(0x22, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + + writel(0x0a, qmp->dp_tx + QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL); + writel(0x0a, qmp->dp_tx2 + QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL); + + writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); writel(0x08, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); udelay(100); writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); @@ -3591,16 +3674,24 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], status, - ((status & BIT(1)) > 0), + ((status & BIT(0)) > 0), 500, 10000)) return -ETIMEDOUT; - writel(0x00, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); - writel(0x00, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; - writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); - writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; return 0; } diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h index d8ac4c4a2c316..b35b486cfa566 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h @@ -71,5 +71,7 @@ #define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4 #define QSERDES_V8_COM_CMN_STATUS 0x2c8 #define QSERDES_V8_COM_C_READY_STATUS 0x2f0 +#define QSERDES_V8_COM_CMN_STATUS_N3 0x314 +#define QSERDES_V8_COM_C_READY_STATUS_N3 0x33c #endif From 5bd6547d5fb633e25aa8d3776863c9e200a0a4bb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Apr 2026 21:29:39 +0530 Subject: [PATCH 0672/1330] FROMLIST: PCI: Introduce an API to check if RC/platform can retain device context during suspend Currently, the PCI endpoint drivers like NVMe checks whether the device context will be retained or not during system suspend, with the help of pm_suspend_via_firmware() API. But it is possible that the device context might be lost due to some platform limitation as well. Having those checks in the endpoint drivers will not scale and will cause a lot of code duplication. So introduce an API that acts as a sole point of truth that the endpoint drivers can rely on to check whether they can expect the device context to be retained or not. If the API returns 'false', then the client drivers need to prepare for context loss by performing actions such as resetting the device, saving the context, shutting it down etc... If it returns 'true', then the drivers do not need to perform any special action and can leave the device in active state. Right now, this API only incorporates the pm_suspend_via_firmware() check. But will be extended in the future commits. Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260414-l1ss-fix-v1-1-adbb4555b5ab@oss.qualcomm.com (cherry picked from commit 6461bc78abccced02401cb736979d60dfa28f91c) --- drivers/pci/pci.c | 23 +++++++++++++++++++++++ include/linux/pci.h | 7 +++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 9298a461bd302..3a861f6ad1c3b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "pci.h" DEFINE_MUTEX(pci_slot_mutex); @@ -2899,6 +2900,28 @@ void pci_config_pm_runtime_put(struct pci_dev *pdev) pm_runtime_put_sync(parent); } +/** + * pci_dev_suspend_retention_supported - Check if the platform can retain the device + * context during system suspend + * @pdev: PCI device to check + * + * Returns true if the platform can guarantee to retain the device context, + * false otherwise. + */ +bool pci_dev_suspend_retention_supported(struct pci_dev *pdev) +{ + /* + * If the platform firmware (like ACPI) is involved at the end of system + * suspend, device context may not be retained. + */ + if (pm_suspend_via_firmware()) + return false; + + /* Assume that the context is retained by default */ + return true; +} +EXPORT_SYMBOL_GPL(pci_dev_suspend_retention_supported); + static const struct dmi_system_id bridge_d3_blacklist[] = { #ifdef CONFIG_X86 { diff --git a/include/linux/pci.h b/include/linux/pci.h index 14bbdea91919e..a314e02ad36e8 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2075,6 +2075,8 @@ pci_release_mem_regions(struct pci_dev *pdev) pci_select_bars(pdev, IORESOURCE_MEM)); } +bool pci_dev_suspend_retention_supported(struct pci_dev *pdev); + #else /* CONFIG_PCI is not enabled */ static inline void pci_set_flags(int flags) { } @@ -2234,6 +2236,11 @@ pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, static inline void pci_free_irq_vectors(struct pci_dev *dev) { } + +static inline bool pci_dev_suspend_retention_supported(struct pci_dev *pdev) +{ + return true; +} #endif /* CONFIG_PCI */ /* Include architecture-dependent settings and functions */ From 689e79d86105ba2d99277ba7d2f096244ba012b8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Apr 2026 21:29:40 +0530 Subject: [PATCH 0673/1330] FROMLIST: PCI: Indicate context lost if L1ss exit is broken during resume from system suspend The PCIe spec v7.0, sec 5.5.3.3.1, states that for exiting L1.2 due to an endpoint asserting CLKREQ# signal, the refclk must be turned on no earlier than TL10_REFCLK_ON, and within the latency advertised in the LTR message. This same behavior applies to L1.1 as well. On some platforms like Qcom, these requirements are satisfied during OS runtime, but not while resuming from the system suspend. This happens because the PCIe RC driver may remove all resource votes and turns off the PHY during suspend to maximize power savings while keeping the link in L1ss. Consequently, when the endpoint asserts CLKREQ# to wake up, the OS must first resume and the RC driver must restore the PHY and enable the refclk. This recovery process exceeds the L1ss exit latency time. And this latency violation results in an L1ss exit timeout, followed by Link Down (LDn). If the endpoint device is used to host the RootFS, it will result in an OS crash. For other endpoints, it may result in a complete device reset/recovery. So to indicate this platform limitation to the client drivers, introduce a new flag 'pci_host_bridge::broken_l1ss_resume' and check it in the pci_dev_suspend_retention_supported() API. If the flag is set by the RC driver, the API will return 'false' indicating the client drivers that the device context may not be retained and the drivers must be prepared for context loss. Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260414-l1ss-fix-v1-2-adbb4555b5ab@oss.qualcomm.com (cherry picked from commit f8b9cb1e0818a5953381ba5a9b853b9fd69edf55) --- drivers/pci/pci.c | 11 +++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 3a861f6ad1c3b..faf39d74bc8a9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2910,6 +2910,8 @@ void pci_config_pm_runtime_put(struct pci_dev *pdev) */ bool pci_dev_suspend_retention_supported(struct pci_dev *pdev) { + struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); + /* * If the platform firmware (like ACPI) is involved at the end of system * suspend, device context may not be retained. @@ -2917,6 +2919,15 @@ bool pci_dev_suspend_retention_supported(struct pci_dev *pdev) if (pm_suspend_via_firmware()) return false; + /* + * Some host bridges power off the PHY to enter deep low-power modes + * during system suspend. Exiting L1 PM Substates from this condition + * violates strict timing requirements and results in Link Down (LDn). + * On such platforms, the endpoint must be prepared for context loss. + */ + if (bridge && bridge->broken_l1ss_resume) + return false; + /* Assume that the context is retained by default */ return true; } diff --git a/include/linux/pci.h b/include/linux/pci.h index a314e02ad36e8..4330a30ecad89 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -653,6 +653,8 @@ struct pci_host_bridge { unsigned int preserve_config:1; /* Preserve FW resource setup */ unsigned int size_windows:1; /* Enable root bus sizing */ unsigned int msi_domain:1; /* Bridge wants MSI domain */ + unsigned int broken_l1ss_resume:1; /* Resuming from L1ss during + system suspend is broken */ /* Resource alignment requirements */ resource_size_t (*align_resource)(struct pci_dev *dev, From 6bcdaa40bb65df85a77319a2e1b5dbf05c9aa397 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Apr 2026 21:29:41 +0530 Subject: [PATCH 0674/1330] FROMLIST: PCI: qcom: Indicate broken L1ss exit during resume from system suspend Qcom PCIe RCs can successfully exit from L1ss during OS runtime. However, during system suspend, the Qcom PCIe RC driver may remove all resource votes and turns off the PHY to maximize power savings. Consequently, when the host is in system suspend with the link in L1ss and the endpoint asserts CLKREQ#, the OS must first wake up and the RC driver must restore the PHY and enable the refclk. This recovery process causes the strict L1ss exit latency time to be exceeded. (If the RC driver were to retain all votes during suspend, L1ss exit would succeed without issue, but at the expense of higher power consumption). This latency violation leads to an L1ss exit timeout, followed by a Link Down (LDn) condition during resume. This LDn can crash the OS if the endpoint hosts the RootFS, and for other types of devices, it may result in a full device reset/recovery. So to ensure that the client drivers can properly handle this scenario, let them know about this platform limitation by setting the 'pci_host_bridge::broken_l1ss_resume' flag. Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260414-l1ss-fix-v1-3-adbb4555b5ab@oss.qualcomm.com (cherry picked from commit cc1f76ae7d68c7cafdb3fcb8e02e6b2ff438b9e2) --- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 871eeca189ba9..d3f90e3d10cbb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1385,6 +1385,17 @@ static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct qcom_pcie *pcie = to_qcom_pcie(pci); + /* + * During system suspend, the Qcom RC driver may turn off the PHY and + * remove votes to save power. If the endpoint asserts CLKREQ# to + * exit L1ss, the time required to wake the system and restore the + * PHY/refclk exceeds the strict L1ss exit timing, resulting in Link + * Down (LDn). Set this flag to indicate this limitation to client + * drivers so that they will avoid relying on L1ss during system + * suspend. + */ + pp->bridge->broken_l1ss_resume = true; + if (pcie->cfg->ops->host_post_init) pcie->cfg->ops->host_post_init(pcie); } From 72fdf27697c07761e090c07b8b0dc1bc772dcd5a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Apr 2026 21:29:42 +0530 Subject: [PATCH 0675/1330] FROMLIST: nvme-pci: Use pci_dev_suspend_retention_supported() API during suspend The pci_dev_suspend_retention_supported() API lets PCI client drivers know if the platform can retain the device context during suspend. This is decided based on several factors like: 1. Firmware involvement at the end of suspend 2. Any platform limitation in waking from low power state (L1ss) And this API might also get extended in the future to cover other platform specific issues impacting the device low power mode during system suspend. So use this API instead of checks like pm_suspend_via_firmware(). When this API returns false, then assume that the platform cannot retain the context and shutdown the controller. If it returns true, then assume that the context will be retained and keep the device in low power mode. Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260414-l1ss-fix-v1-4-adbb4555b5ab@oss.qualcomm.com (cherry picked from commit 13f302ced37e4e647c50f669e91aeacc66677a55) --- drivers/nvme/host/pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index a0e9767bc21e6..6a34759704b77 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -3944,6 +3944,7 @@ static int nvme_suspend(struct device *dev) * use host managed nvme power settings for lowest idle power if * possible. This should have quicker resume latency than a full device * shutdown. But if the firmware is involved after the suspend or the + * platform has any limitation in waking from low power states or the * device does not support any non-default power states, shut down the * device fully. * @@ -3952,7 +3953,7 @@ static int nvme_suspend(struct device *dev) * down, so as to allow the platform to achieve its minimum low-power * state (which may not be possible if the link is up). */ - if (pm_suspend_via_firmware() || !ctrl->npss || + if (!pci_dev_suspend_retention_supported(pdev) || !ctrl->npss || !pcie_aspm_enabled(pdev) || (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) return nvme_disable_prepare_reset(ndev, true); From 713ed43abc2792e5409c17023b874b6f9df319bf Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 21 Apr 2026 18:55:52 +0800 Subject: [PATCH 0676/1330] FROMLIST: coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs read operations Introduce tmc_sysfs_ops as a wrapper, wrap sysfs read operations, for reading trace data from the TMC buffer. Link: https://lore.kernel.org/linux-arm-msm/20260421-enable-byte-cntr-for-ctcu-v17-3-9cf36ff55fc0@oss.qualcomm.com/ Reviewed-by: Mike Leach Signed-off-by: Jie Gan (cherry picked from commit 1ea7ee1292db6109f27a4327b6c5d254f612b06e) --- .../hwtracing/coresight/coresight-tmc-core.c | 168 ++++++------------ 1 file changed, 50 insertions(+), 118 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 5e873bdcf7bb3..25b06f3e08eb1 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -262,11 +262,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; int ret = 0; - byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); - if (byte_cntr_sysfs_ops) { - ret = byte_cntr_sysfs_ops->read_prepare(drvdata); - goto out; - } + if (drvdata->sysfs_ops) + ret = drvdata->sysfs_ops->read_prepare(drvdata); + else + ret = -EINVAL; if (drvdata->sysfs_ops) ret = drvdata->sysfs_ops->read_prepare(drvdata); @@ -285,11 +284,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvdata) const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; int ret = 0; - byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); - if (byte_cntr_sysfs_ops) { - ret = byte_cntr_sysfs_ops->read_unprepare(drvdata); - goto out; - } + if (drvdata->sysfs_ops) + ret = drvdata->sysfs_ops->read_unprepare(drvdata); + else + ret = -EINVAL; if (drvdata->sysfs_ops) ret = drvdata->sysfs_ops->read_unprepare(drvdata); @@ -322,12 +320,6 @@ static int tmc_open(struct inode *inode, struct file *file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp) { - const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; - - byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); - if (byte_cntr_sysfs_ops) - return byte_cntr_sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); - return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); } @@ -923,14 +915,40 @@ static const struct tmc_sysfs_ops etr_sysfs_ops = { .get_trace_data = tmc_etr_get_sysfs_trace, }; -static int tmc_add_coresight_dev(struct device *dev) +static int __tmc_probe(struct device *dev, struct resource *res) { - struct tmc_drvdata *drvdata = dev_get_drvdata(dev); - struct coresight_desc desc = { 0 }; - struct coresight_dev_list *dev_list = NULL; - int ret = 0; + int cpu, ret = 0; + void __iomem *base; + struct coresight_platform_data *pdata = NULL; + struct tmc_drvdata *drvdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); + if (ret) + return ret; + + ret = -ENOMEM; + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto out; + } + + drvdata->base = base; + + raw_spin_lock_init(&drvdata->spinlock); + /* This device is not associated with a session */ + drvdata->pid = -1; + drvdata->etr_mode = ETR_MODE_AUTO; + tmc_get_reserved_region(dev); - desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); desc.dev = dev; switch (drvdata->config_type) { @@ -939,7 +957,7 @@ static int tmc_add_coresight_dev(struct device *dev) desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops = &tmc_etb_cs_ops; - dev_list = &etb_devs; + dev_list = "tmc_etb"; drvdata->sysfs_ops = &etb_sysfs_ops; break; case TMC_CONFIG_TYPE_ETR: @@ -947,14 +965,14 @@ static int tmc_add_coresight_dev(struct device *dev) desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; desc.ops = &tmc_etr_cs_ops; - ret = tmc_etr_setup_caps(dev, drvdata->devid, &desc.access); + ret = tmc_etr_setup_caps(dev, devid, &desc.access); if (ret) - return ret; + goto out; idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); - dev_list = &etr_devs; - INIT_LIST_HEAD(&drvdata->etr_buf_list); + dev_list = "tmc_etr"; drvdata->sysfs_ops = &etr_sysfs_ops; + INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: desc.groups = coresight_etf_groups; @@ -962,107 +980,21 @@ static int tmc_add_coresight_dev(struct device *dev) desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; desc.ops = &tmc_etf_cs_ops; - dev_list = &etf_devs; + dev_list = "tmc_etf"; drvdata->sysfs_ops = &etb_sysfs_ops; break; default: pr_err("%s: Unsupported TMC config\n", desc.name); - return -EINVAL; + ret = -EINVAL; + goto out; } desc.name = coresight_alloc_device_name(dev_list, dev); - if (!desc.name) - return -ENOMEM; - - drvdata->desc_name = desc.name; - - desc.pdata = dev->platform_data; - - drvdata->csdev = coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) - return PTR_ERR(drvdata->csdev); - - drvdata->miscdev.name = desc.name; - drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; - drvdata->miscdev.fops = &tmc_fops; - ret = misc_register(&drvdata->miscdev); - if (ret) - coresight_unregister(drvdata->csdev); - - return ret; -} - -static void tmc_clear_self_claim_tag(struct tmc_drvdata *drvdata) -{ - struct csdev_access access = CSDEV_ACCESS_IOMEM(drvdata->base); - - coresight_clear_self_claim_tag(&access); -} - -static void tmc_init_hw_config(struct tmc_drvdata *drvdata) -{ - u32 devid; - - devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); - drvdata->config_type = BMVAL(devid, 6, 7); - drvdata->memwidth = tmc_get_memwidth(devid); - drvdata->devid = devid; - drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; - tmc_clear_self_claim_tag(drvdata); -} - -static void tmc_init_on_cpu(void *info) -{ - struct tmc_drvdata *drvdata = info; - - tmc_init_hw_config(drvdata); -} - -static struct cpumask *tmc_get_supported_cpus(struct device *dev) -{ - struct generic_pm_domain *pd; - - pd = pd_to_genpd(dev->pm_domain); - if (pd) - return pd->cpus; - - return NULL; -} - -static int __tmc_probe(struct device *dev, struct resource *res) -{ - int cpu, ret = 0; - void __iomem *base; - struct coresight_platform_data *pdata = NULL; - struct tmc_drvdata *drvdata; - - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); - if (ret) - return ret; - - ret = -ENOMEM; - - /* Validity for the resource is already checked by the AMBA core */ - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) { - ret = PTR_ERR(base); + if (!desc.name) { + ret = -ENOMEM; goto out; } - drvdata->base = base; - - raw_spin_lock_init(&drvdata->spinlock); - /* This device is not associated with a session */ - drvdata->pid = -1; - drvdata->etr_mode = ETR_MODE_AUTO; - tmc_get_reserved_region(dev); - pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) { ret = PTR_ERR(pdata); From 0b7fb37498deb95da0e805a3df012c42b7d7a16e Mon Sep 17 00:00:00 2001 From: Yingchao Deng Date: Sun, 26 Apr 2026 17:44:39 +0800 Subject: [PATCH 0677/1330] FROMLIST: coresight: cti: encode trigger register index in register offsets Introduce a small encoding to carry the register index together with the base offset in a single u32, and use a common helper to compute the final MMIO address. This refactors register access to be based on the encoded (reg, nr) pair, reducing duplicated arithmetic and making it easier to support variants that bank or relocate trigger-indexed registers. Link: https://lore.kernel.org/linux-arm-msm/20260426-extended-cti-v8-2-23b900a4902f@oss.qualcomm.com/ Signed-off-by: Yingchao Deng (cherry picked from commit 9e9d1cdb3eac907e76d7815af91b4e25a15f1b0e) --- .../hwtracing/coresight/coresight-cti-core.c | 55 +++++++++---------- .../hwtracing/coresight/coresight-cti-sysfs.c | 12 ++-- drivers/hwtracing/coresight/coresight-cti.h | 16 +++++- 3 files changed, 47 insertions(+), 36 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index 51b3644e97c4a..dc0bb31916abf 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -91,20 +91,13 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) -/* power management handling */ -static int nr_cti_cpu; - -/* quick lookup list for CPU bound CTIs when power handling */ -static struct cti_drvdata *cti_cpu_drvdata[NR_CPUS]; +static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg) +{ + u32 offset = CTI_REG_CLR_NR(reg); + u32 nr = CTI_REG_GET_NR(reg); -/* - * CTI naming. CTI bound to cores will have the name cti_cpu where - * N is the CPU ID. System CTIs will have the name cti_sys where I - * is an index allocated by order of discovery. - * - * CTI device name list - for CTI not bound to cores. - */ -DEFINE_CORESIGHT_DEVLIST(cti_sys_devs, "cti_sys"); + return drvdata->base + offset + sizeof(u32) * nr; +} /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) @@ -120,15 +113,16 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) /* write the CTI trigger registers */ for (i = 0; i < config->nr_trig_max; i++) { writel_relaxed(config->ctiinen[i], - drvdata->base + cti_offset(drvdata, INDEX_CTIINEN, i)); + cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIINEN, i))); writel_relaxed(config->ctiouten[i], - drvdata->base + cti_offset(drvdata, INDEX_CTIOUTEN, i)); + cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIOUTEN, i))); } /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + cti_offset(drvdata, INDEX_CTIGATE, 0)); - writel_relaxed(config->asicctl, drvdata->base + cti_offset(drvdata, INDEX_ASICCTL, 0)); - writel_relaxed(config->ctiappset, drvdata->base + cti_offset(drvdata, INDEX_CTIAPPSET, 0)); + writel_relaxed(config->ctigate, cti_reg_addr(drvdata, CTIGATE)); + if (config->asicctl_impl) + writel_relaxed(config->asicctl, cti_reg_addr(drvdata, ASICCTL)); + writel_relaxed(config->ctiappset, cti_reg_addr(drvdata, CTIAPPSET)); /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -230,16 +224,21 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) raw_spin_unlock(&drvdata->spinlock); return ret; - /* not disabled this call */ -cti_not_disabled: - raw_spin_unlock(&drvdata->spinlock); - return ret; +u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset) +{ + int val; + + CS_UNLOCK(drvdata->base); + val = readl_relaxed(cti_reg_addr(drvdata, offset)); + CS_LOCK(drvdata->base); + + return val; } void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) { CS_UNLOCK(drvdata->base); - writel_relaxed(value, drvdata->base + offset); + writel_relaxed(value, cti_reg_addr(drvdata, offset)); CS_LOCK(drvdata->base); } @@ -447,8 +446,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, /* update the local register values */ chan_bitmask = BIT(channel_idx); - reg_offset = (direction == CTI_TRIG_IN ? cti_offset(drvdata, INDEX_CTIINEN, trigger_idx) : - cti_offset(drvdata, INDEX_CTIOUTEN, trigger_idx)); + reg_offset = (direction == CTI_TRIG_IN ? CTIINEN : CTIOUTEN); raw_spin_lock(&drvdata->spinlock); @@ -467,9 +465,10 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, config->ctiouten[trigger_idx] = reg_value; /* write through if enabled */ - if (cti_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); - raw_spin_unlock(&drvdata->spinlock); + if (cti_is_active(config)) + cti_write_single_reg(drvdata, + CTI_REG_SET_NR(reg_offset, trigger_idx), + reg_value); return 0; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 12a4953829994..281e0ee70da1e 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -485,9 +485,9 @@ static ssize_t inen_store(struct device *dev, config->ctiinen[index] = val; /* write through if enabled */ - if (cti_active(config)) - cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIINEN, index), val); - raw_spin_unlock(&drvdata->spinlock); + if (cti_is_active(config)) + cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIINEN, index), val); + return size; } static DEVICE_ATTR_RW(inen); @@ -524,9 +524,9 @@ static ssize_t outen_store(struct device *dev, config->ctiouten[index] = val; /* write through if enabled */ - if (cti_active(config)) - cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIOUTEN, index), val); - raw_spin_unlock(&drvdata->spinlock); + if (cti_is_active(config)) + cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIOUTEN, index), val); + return size; } static DEVICE_ATTR_RW(outen); diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index fdd6d8892a95a..6fb9681c59404 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -7,6 +7,7 @@ #ifndef _CORESIGHT_CORESIGHT_CTI_H #define _CORESIGHT_CORESIGHT_CTI_H +#include #include #include #include @@ -30,8 +31,8 @@ struct fwnode_handle; #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01C -#define CTIINEN(n) (0x020 + (4 * n)) -#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTIINEN 0x020 +#define CTIOUTEN 0x0A0 #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 @@ -90,6 +91,17 @@ enum cti_offset_index { INDEX_ITCTRL, }; +/* + * Encode CTI register offset and register index in one u32: + * - bits[0:11] : base register offset (0x000 to 0xFFF) + * - bits[24:31] : register index (nr) + */ +#define CTI_REG_NR_MASK GENMASK(31, 24) +#define CTI_REG_GET_NR(reg) FIELD_GET(CTI_REG_NR_MASK, (reg)) +#define CTI_REG_SET_NR_CONST(reg, nr) ((reg) | FIELD_PREP_CONST(CTI_REG_NR_MASK, (nr))) +#define CTI_REG_SET_NR(reg, nr) ((reg) | FIELD_PREP(CTI_REG_NR_MASK, (nr))) +#define CTI_REG_CLR_NR(reg) ((reg) & (~CTI_REG_NR_MASK)) + /** * Group of related trigger signals * From f3cb22b0fdd453edf788b20b6d3be774358e881a Mon Sep 17 00:00:00 2001 From: Yingchao Deng Date: Sun, 26 Apr 2026 17:44:40 +0800 Subject: [PATCH 0678/1330] FROMLIST: coresight: cti: add Qualcomm extended CTI identification and quirks Qualcomm implements an extended variant of the ARM CoreSight CTI with a different register layout and vendor-specific behavior. While the programming model remains largely compatible, the register offsets differ from the standard ARM CTI and require explicit handling. Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI driver data. Introduce a small mapping layer to translate standard CTI register offsets to Qualcomm-specific offsets, allowing the rest of the driver to use a common register access path. Additionally, handle a Qualcomm-specific quirk where the CLAIMSET register is incorrectly initialized to a non-zero value, which can cause tools or drivers to assume the component is already claimed. Clear the register during probe to reflect the actual unclaimed state. No functional change is intended for standard ARM CTI devices. Link: https://lore.kernel.org/linux-arm-msm/20260426-extended-cti-v8-3-23b900a4902f@oss.qualcomm.com/ Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng (cherry picked from commit 2211919548bf910091ab9bcf124ea96bb5933fe8) --- .../hwtracing/coresight/coresight-cti-core.c | 71 ++++++----------- drivers/hwtracing/coresight/coresight-cti.h | 36 +-------- drivers/hwtracing/coresight/qcom-cti.h | 76 ++++++++++++++----- 3 files changed, 80 insertions(+), 103 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index dc0bb31916abf..d6cdea81682e7 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -23,54 +23,6 @@ #include "coresight-cti.h" #include "qcom-cti.h" -static const u32 cti_normal_offset[] = { - [INDEX_CTIINTACK] = CTIINTACK, - [INDEX_CTIAPPSET] = CTIAPPSET, - [INDEX_CTIAPPCLEAR] = CTIAPPCLEAR, - [INDEX_CTIAPPPULSE] = CTIAPPPULSE, - [INDEX_CTIINEN] = CTIINEN(0), - [INDEX_CTIOUTEN] = CTIOUTEN(0), - [INDEX_CTITRIGINSTATUS] = CTITRIGINSTATUS, - [INDEX_CTITRIGOUTSTATUS] = CTITRIGOUTSTATUS, - [INDEX_CTICHINSTATUS] = CTICHINSTATUS, - [INDEX_CTICHOUTSTATUS] = CTICHOUTSTATUS, - [INDEX_CTIGATE] = CTIGATE, - [INDEX_ASICCTL] = ASICCTL, - [INDEX_ITCHINACK] = ITCHINACK, - [INDEX_ITTRIGINACK] = ITTRIGINACK, - [INDEX_ITCHOUT] = ITCHOUT, - [INDEX_ITTRIGOUT] = ITTRIGOUT, - [INDEX_ITCHOUTACK] = ITCHOUTACK, - [INDEX_ITTRIGOUTACK] = ITTRIGOUTACK, - [INDEX_ITCHIN] = ITCHIN, - [INDEX_ITTRIGIN] = ITTRIGIN, - [INDEX_ITCTRL] = CORESIGHT_ITCTRL, -}; - -static const u32 cti_extended_offset[] = { - [INDEX_CTIINTACK] = QCOM_CTIINTACK, - [INDEX_CTIAPPSET] = QCOM_CTIAPPSET, - [INDEX_CTIAPPCLEAR] = QCOM_CTIAPPCLEAR, - [INDEX_CTIAPPPULSE] = QCOM_CTIAPPPULSE, - [INDEX_CTIINEN] = QCOM_CTIINEN, - [INDEX_CTIOUTEN] = QCOM_CTIOUTEN, - [INDEX_CTITRIGINSTATUS] = QCOM_CTITRIGINSTATUS, - [INDEX_CTITRIGOUTSTATUS] = QCOM_CTITRIGOUTSTATUS, - [INDEX_CTICHINSTATUS] = QCOM_CTICHINSTATUS, - [INDEX_CTICHOUTSTATUS] = QCOM_CTICHOUTSTATUS, - [INDEX_CTIGATE] = QCOM_CTIGATE, - [INDEX_ASICCTL] = QCOM_ASICCTL, - [INDEX_ITCHINACK] = QCOM_ITCHINACK, - [INDEX_ITTRIGINACK] = QCOM_ITTRIGINACK, - [INDEX_ITCHOUT] = QCOM_ITCHOUT, - [INDEX_ITTRIGOUT] = QCOM_ITTRIGOUT, - [INDEX_ITCHOUTACK] = QCOM_ITCHOUTACK, - [INDEX_ITTRIGOUTACK] = QCOM_ITTRIGOUTACK, - [INDEX_ITCHIN] = QCOM_ITCHIN, - [INDEX_ITTRIGIN] = QCOM_ITTRIGIN, - [INDEX_ITCTRL] = CORESIGHT_ITCTRL, -}; - /* * CTI devices can be associated with a PE, or be connected to CoreSight * hardware. We have a list of all CTIs irrespective of CPU bound or @@ -96,6 +48,10 @@ static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg) u32 offset = CTI_REG_CLR_NR(reg); u32 nr = CTI_REG_GET_NR(reg); + /* convert to qcom specific offset */ + if (unlikely(drvdata->is_qcom_cti)) + offset = cti_qcom_reg_off(offset); + return drvdata->base + offset + sizeof(u32) * nr; } @@ -972,6 +928,22 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) raw_spin_lock_init(&drvdata->spinlock); + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { + drvdata->is_qcom_cti = true; + /* + * QCOM CTI does not implement Claimtag functionality as + * per CoreSight specification, but its CLAIMSET register + * is incorrectly initialized to 0xF. This can mislead + * tools or drivers into thinking the component is claimed. + * + * Reset CLAIMSET to 0 to reflect that no claims are active. + */ + CS_UNLOCK(drvdata->base); + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); + CS_LOCK(drvdata->base); + } + /* initialise CTI driver config values */ ret = cti_set_default_config(dev, drvdata); if (ret) @@ -1055,7 +1027,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, "CTI initialized; subtype=%d\n", drvdata->subtype); + dev_info(&drvdata->csdev->dev, + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); return 0; pm_release: diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 6fb9681c59404..b3e9b1b692305 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -55,42 +55,12 @@ struct fwnode_handle; /* * CTI CSSoc 600 has a max of 32 trigger signals per direction. * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. + * QCOM CTI supports up to 128 trigger signals per direction. * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ #define CTIINOUTEN_MAX 128 -/* Qcom CTI supports up to 128 triggers*/ -enum cti_subtype { - ARM_STD_CTI, - QCOM_CTI, -}; - -/* These registers are remapped in Qcom CTI*/ -enum cti_offset_index { - INDEX_CTIINTACK, - INDEX_CTIAPPSET, - INDEX_CTIAPPCLEAR, - INDEX_CTIAPPPULSE, - INDEX_CTIINEN, - INDEX_CTIOUTEN, - INDEX_CTITRIGINSTATUS, - INDEX_CTITRIGOUTSTATUS, - INDEX_CTICHINSTATUS, - INDEX_CTICHOUTSTATUS, - INDEX_CTIGATE, - INDEX_ASICCTL, - INDEX_ITCHINACK, - INDEX_ITTRIGINACK, - INDEX_ITCHOUT, - INDEX_ITTRIGOUT, - INDEX_ITCHOUTACK, - INDEX_ITTRIGOUTACK, - INDEX_ITCHIN, - INDEX_ITTRIGIN, - INDEX_ITCTRL, -}; - /* * Encode CTI register offset and register index in one u32: * - bits[0:11] : base register offset (0x000 to 0xFFF) @@ -226,9 +196,7 @@ struct cti_drvdata { raw_spinlock_t spinlock; struct cti_config config; struct list_head node; - void (*csdev_release)(struct device *dev); - enum cti_subtype subtype; - const u32 *offsets; + bool is_qcom_cti; }; /* diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h index 3c46317dd81f5..fd1bf07d7cb4a 100644 --- a/drivers/hwtracing/coresight/qcom-cti.h +++ b/drivers/hwtracing/coresight/qcom-cti.h @@ -3,27 +3,63 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#ifndef _CORESIGHT_QCOM_CTI_H +#define _CORESIGHT_QCOM_CTI_H + +#include "coresight-cti.h" + #define ARCHITECT_QCOM 0x477 /* CTI programming registers */ -#define QCOM_CTIINTACK 0x020 -#define QCOM_CTIAPPSET 0x004 -#define QCOM_CTIAPPCLEAR 0x008 -#define QCOM_CTIAPPPULSE 0x00C -#define QCOM_CTIINEN 0x400 -#define QCOM_CTIOUTEN 0x800 -#define QCOM_CTITRIGINSTATUS 0x040 -#define QCOM_CTITRIGOUTSTATUS 0x060 -#define QCOM_CTICHINSTATUS 0x080 -#define QCOM_CTICHOUTSTATUS 0x084 -#define QCOM_CTIGATE 0x088 -#define QCOM_ASICCTL 0x08c +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08C /* Integration test registers */ -#define QCOM_ITCHINACK 0xE70 -#define QCOM_ITTRIGINACK 0xE80 -#define QCOM_ITCHOUT 0xE74 -#define QCOM_ITTRIGOUT 0xEA0 -#define QCOM_ITCHOUTACK 0xE78 -#define QCOM_ITTRIGOUTACK 0xEC0 -#define QCOM_ITCHIN 0xE7C -#define QCOM_ITTRIGIN 0xEE0 +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 + +static noinline u32 cti_qcom_reg_off(u32 offset) +{ + switch (offset) { + case CTIINTACK: return QCOM_CTIINTACK; + case CTIAPPSET: return QCOM_CTIAPPSET; + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; + case CTIAPPPULSE: return QCOM_CTIAPPPULSE; + case CTIINEN: return QCOM_CTIINEN; + case CTIOUTEN: return QCOM_CTIOUTEN; + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; + case CTICHINSTATUS: return QCOM_CTICHINSTATUS; + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; + case CTIGATE: return QCOM_CTIGATE; + case ASICCTL: return QCOM_ASICCTL; + case ITCHINACK: return QCOM_ITCHINACK; + case ITTRIGINACK: return QCOM_ITTRIGINACK; + case ITCHOUT: return QCOM_ITCHOUT; + case ITTRIGOUT: return QCOM_ITTRIGOUT; + case ITCHOUTACK: return QCOM_ITCHOUTACK; + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK; + case ITCHIN: return QCOM_ITCHIN; + case ITTRIGIN: return QCOM_ITTRIGIN; + + default: + return offset; + } +} + +#endif /* _CORESIGHT_QCOM_CTI_H */ From b9b8cf0d7be5d4cf67ed97bb333e9d860de321ae Mon Sep 17 00:00:00 2001 From: Yingchao Deng Date: Sun, 26 Apr 2026 17:44:41 +0800 Subject: [PATCH 0679/1330] FROMLIST: coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Qualcomm extended CTI implements banked trigger status and integration registers, where each bank covers 32 triggers. Multiple instances of these registers are required to expose the full trigger space. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Numbered sysfs nodes are hidden on standard ARM CTIs, preserving the existing ABI. On Qualcomm CTIs, only banked registers backed by hardware are exposed, with the number of visible banks derived from nr_trig_max. This ensures that userspace only sees registers that are actually implemented, while maintaining compatibility with existing CTI tooling. Link: https://lore.kernel.org/linux-arm-msm/20260426-extended-cti-v8-4-23b900a4902f@oss.qualcomm.com/ Signed-off-by: Yingchao Deng (cherry picked from commit fdebcc6db37758f82a5ee69da20818879979f022) --- .../hwtracing/coresight/coresight-cti-sysfs.c | 96 ++++++++++++++++--- 1 file changed, 83 insertions(+), 13 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 281e0ee70da1e..75b8f16ee0399 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -610,24 +610,94 @@ static struct attribute *coresight_cti_regs_attrs[] = { &dev_attr_appset.attr, &dev_attr_appclear.attr, &dev_attr_apppulse.attr, - coresight_cti_reg(triginstatus, INDEX_CTITRIGINSTATUS), - coresight_cti_reg(trigoutstatus, INDEX_CTITRIGOUTSTATUS), - coresight_cti_reg(chinstatus, INDEX_CTICHINSTATUS), - coresight_cti_reg(choutstatus, INDEX_CTICHOUTSTATUS), + coresight_cti_reg(triginstatus, CTITRIGINSTATUS), + coresight_cti_reg(triginstatus1, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 1)), + coresight_cti_reg(triginstatus2, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 2)), + coresight_cti_reg(triginstatus3, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 3)), + coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), + coresight_cti_reg(trigoutstatus1, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 1)), + coresight_cti_reg(trigoutstatus2, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 2)), + coresight_cti_reg(trigoutstatus3, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 3)), + coresight_cti_reg(chinstatus, CTICHINSTATUS), + coresight_cti_reg(choutstatus, CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS - coresight_cti_reg_rw(itctrl, INDEX_ITCTRL), - coresight_cti_reg(ittrigin, INDEX_ITTRIGIN), - coresight_cti_reg(itchin, INDEX_ITCHIN), - coresight_cti_reg_rw(ittrigout, INDEX_ITTRIGOUT), - coresight_cti_reg_rw(itchout, INDEX_ITCHOUT), - coresight_cti_reg(itchoutack, INDEX_ITCHOUTACK), - coresight_cti_reg(ittrigoutack, INDEX_ITTRIGOUTACK), - coresight_cti_reg_wo(ittriginack, INDEX_ITTRIGINACK), - coresight_cti_reg_wo(itchinack, INDEX_ITCHINACK), + coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), + coresight_cti_reg(ittrigin, ITTRIGIN), + coresight_cti_reg(ittrigin1, CTI_REG_SET_NR_CONST(ITTRIGIN, 1)), + coresight_cti_reg(ittrigin2, CTI_REG_SET_NR_CONST(ITTRIGIN, 2)), + coresight_cti_reg(ittrigin3, CTI_REG_SET_NR_CONST(ITTRIGIN, 3)), + coresight_cti_reg(itchin, ITCHIN), + coresight_cti_reg_rw(ittrigout, ITTRIGOUT), + coresight_cti_reg_rw(ittrigout1, CTI_REG_SET_NR_CONST(ITTRIGOUT, 1)), + coresight_cti_reg_rw(ittrigout2, CTI_REG_SET_NR_CONST(ITTRIGOUT, 2)), + coresight_cti_reg_rw(ittrigout3, CTI_REG_SET_NR_CONST(ITTRIGOUT, 3)), + coresight_cti_reg_rw(itchout, ITCHOUT), + coresight_cti_reg(itchoutack, ITCHOUTACK), + coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), + coresight_cti_reg(ittrigoutack1, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 1)), + coresight_cti_reg(ittrigoutack2, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 2)), + coresight_cti_reg(ittrigoutack3, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 3)), + coresight_cti_reg_wo(ittriginack, ITTRIGINACK), + coresight_cti_reg_wo(ittriginack1, CTI_REG_SET_NR_CONST(ITTRIGINACK, 1)), + coresight_cti_reg_wo(ittriginack2, CTI_REG_SET_NR_CONST(ITTRIGINACK, 2)), + coresight_cti_reg_wo(ittriginack3, CTI_REG_SET_NR_CONST(ITTRIGINACK, 3)), + coresight_cti_reg_wo(itchinack, ITCHINACK), #endif NULL, }; +static umode_t coresight_cti_regs_is_visible(struct kobject *kobj, + struct attribute *attr, int idx) +{ + struct device *dev = kobj_to_dev(kobj); + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + static const char * const qcom_suffix_registers[] = { + "triginstatus", + "trigoutstatus", +#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS + "ittrigin", + "ittrigout", + "ittriginack", + "ittrigoutack", +#endif + }; + int i, nr, max_bank; + size_t len; + + if (attr == &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) + return 0; + + /* + * Banked regs are exposed as (nr = 1..3). + * - Hide them on standard CTIs. + * - On QCOM CTIs, hide suffixes beyond the number of banks implied + * by nr_trig_max (32 triggers per bank). + */ + for (i = 0; i < ARRAY_SIZE(qcom_suffix_registers); i++) { + len = strlen(qcom_suffix_registers[i]); + + if (strncmp(attr->name, qcom_suffix_registers[i], len)) + continue; + + if (kstrtoint(attr->name + len, 10, &nr)) + continue; + + if (!drvdata->is_qcom_cti) + return 0; + + if (nr < 1 || nr > 3) + return 0; + + max_bank = DIV_ROUND_UP(drvdata->config.nr_trig_max, 32) - 1; + if (nr > max_bank) + return 0; + + break; + } + + return attr->mode; +} + /* CTI channel x-trigger programming */ static int cti_trig_op_parse(struct device *dev, enum cti_chan_op op, From a5eee2b2187f1901e522b00a7682104d6c32fabb Mon Sep 17 00:00:00 2001 From: Qingqing Zhou Date: Thu, 17 Jul 2025 15:44:00 +0530 Subject: [PATCH 0680/1330] PENDING: arm64: dts: qcom: kaanapali: add the GPU SMMU node Add the Adreno GPU SMMU node for kaanapali platform. Signed-off-by: Qingqing Zhou Signed-off-by: Akhil P Oommen (cherry picked from commit 0424db7e067d6e92caf6876724a8eef5a896deda) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 42 +++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 9e335b615110f..f854dd3dd0f57 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2739,6 +2739,48 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,kaanapali-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x3da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + dma-coherent; + + power-domains = <&gpucc GPU_CC_CX_GDSC>; + interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; + + clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; + clock-names = "gpu_cc_gpu_smmu_vote_clk"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + remoteproc_adsp: remoteproc@6800000 { compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; reg = <0x0 0x06800000 0x0 0x10000>; From b0c268adf981135246b6a30e0f490c0623434b8b Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Wed, 27 Aug 2025 05:10:09 +0530 Subject: [PATCH 0681/1330] PENDING: arm64: dts: qcom: kaanapali: Add GPU support for Kaanapali Add GPU and GMU devicetree nodes for the Adreno 840 GPU found on Qualcomm Kaanapali platform. Signed-off-by: Akhil P Oommen (cherry picked from commit 98cc7269103b9c9824b4a73813ff194ddd3d4149) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 201 +++++++++++++++++++++++- 1 file changed, 200 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index f854dd3dd0f57..9d38687d8125f 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2715,6 +2715,204 @@ #power-domain-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-44050a01", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x2000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-222000000 { + opp-hz = /bits/ 64 <222000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + }; + + opp-282000000 { + opp-hz = /bits/ 64 <282000000>; + opp-level = ; + opp-peak-kBps = <5285156>; + qcom,opp-acd-level = <0xca2e5ffd>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + opp-level = ; + opp-peak-kBps = <5285156>; + qcom,opp-acd-level = <0xe22a5ffd>; + }; + + opp-382000000 { + opp-hz = /bits/ 64 <382000000>; + opp-level = ; + opp-peak-kBps = <5285156>; + qcom,opp-acd-level = <0xa22c5ffd>; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xa22c5ffd>; + }; + + opp-461000000 { + opp-hz = /bits/ 64 <461000000>; + opp-level = ; + opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xe82e5ffd>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xe82c5ffd>; + }; + + opp-539000000 { + opp-hz = /bits/ 64 <539000000>; + opp-level = ; + opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xc82b5ffd>; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xc02c5ffd>; + }; + + opp-646000000 { + opp-hz = /bits/ 64 <646000000>; + opp-level = ; + opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0xc02c5ffd>; + }; + + opp-726000000 { + opp-hz = /bits/ 64 <726000000>; + opp-level = ; + opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0x882f5ffd>; + }; + + opp-826000000 { + opp-hz = /bits/ 64 <826000000>; + opp-level = ; + opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0xa82c5ffd>; + }; + + opp-902000000 { + opp-hz = /bits/ 64 <902000000>; + opp-level = ; + opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0xa82b5ffd>; + }; + + opp-967000000 { + opp-hz = /bits/ 64 <967000000>; + opp-level = ; + opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-105000000 { + opp-hz = /bits/ 64 <105000000>; + opp-level = ; + opp-peak-kBps = <20832031>; + qcom,opp-acd-level = <0x88295ffd>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-840.1", "qcom,adreno-gmu"; + + reg = <0x0 0x03d37000 0x0 0x68000>; + reg-names = "gmu"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "memnoc", + "hub"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-475000000 { + opp-hz = /bits/ 64 <475000000>; + opp-level = ; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + opp-level = ; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + }; + + opp-725000000 { + opp-hz = /bits/ 64 <725000000>; + opp-level = ; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-level = ; + }; + }; + }; + gxclkctl: clock-controller@3d64000 { compatible = "qcom,kaanapali-gxclkctl"; reg = <0x0 0x03d64000 0x0 0x6000>; @@ -2748,7 +2946,8 @@ dma-coherent; power-domains = <&gpucc GPU_CC_CX_GDSC>; - interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; clock-names = "gpu_cc_gpu_smmu_vote_clk"; From 080dbb05aa480ccc39375211b493b26f102bf6f3 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Sat, 20 Sep 2025 20:44:34 +0530 Subject: [PATCH 0682/1330] PENDING: arm64: dts: qcom: kaanapali-qrd: Enable GPU Add the secure firmware name property and enable GPU support on Kaanapali QRD device. Signed-off-by: Akhil P Oommen (cherry picked from commit 643c0056ce9b8973a3461c9b1993ee997029b68d) --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 4916d2f3be3ed..95dce0812725c 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -698,6 +698,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/kaanapali/gen80200_zap.mbn"; +}; + &pmh0101_flash { status = "okay"; From 522bbcb765a533bd0d9e12846ce4aa8b254a2087 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Sat, 20 Sep 2025 20:45:25 +0530 Subject: [PATCH 0683/1330] PENDING: arm64: dts: qcom: kaanapali-mtp: Enable GPU Add the secure firmware name property and enable GPU support on Kaanapali MTP device. Signed-off-by: Akhil P Oommen (cherry picked from commit 3fd62b47c5edf864203a3dfe6f5f3591a0afe418) --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index c0e2f2be6a0df..7bce5653ea748 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -870,6 +870,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/kaanapali/gen80200_zap.mbn"; +}; + &lpass_vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; From 4754a6689947c611b2f861c1166f5882a3dbd1db Mon Sep 17 00:00:00 2001 From: Dipa Mantre Date: Wed, 15 Apr 2026 16:27:08 +0530 Subject: [PATCH 0684/1330] FROMLIST: arm64: dts: qcom: kaanapali: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Dipa Mantre Reviewed-by: Gaurav Kohli Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260415-cpufreq_kaanapali-v1-1-1fa94105d5c2@oss.qualcomm.com (cherry picked from commit 7436a0814e107c3b27f4ee0369fd130e6f275474) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 9d38687d8125f..3886cc5b76c3d 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -48,6 +48,7 @@ power-domains = <&cpu_pd0>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -65,6 +66,7 @@ power-domains = <&cpu_pd1>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -76,6 +78,7 @@ power-domains = <&cpu_pd2>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -87,6 +90,7 @@ power-domains = <&cpu_pd3>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -98,6 +102,7 @@ power-domains = <&cpu_pd4>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -109,6 +114,7 @@ power-domains = <&cpu_pd5>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu6: cpu@10000 { @@ -120,6 +126,7 @@ power-domains = <&cpu_pd6>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 1>; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -137,6 +144,7 @@ power-domains = <&cpu_pd7>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 1>; + #cooling-cells = <2>; }; cpu-map { From cb8830f4ae6802424960422f4875e0387de70a05 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Fri, 10 Apr 2026 11:02:30 +0530 Subject: [PATCH 0685/1330] FROMLIST: drivers: soc: qcom: smem: Switch partitions to xarray The partitions array is currently statically sized and uses the remote host ID as an index. Future protocol improvements to allow for more than two hosts in a partition will require hostIDs to be bitwise significant integers. This will result in large, sparse host IDs that generally exceed the current static limit. Switch to using xarray to efficiently handle these sparse indices and allow for dynamic growth. Signed-off-by: Tony Truong Signed-off-by: Pranav Mahesh Phansalkar Tested-by: Konrad Dybcio # Glymur CRD Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260410-smem-v1-1-8e94bb5416a6@oss.qualcomm.com (cherry picked from commit 0aa90b7d45babe6116bcbb3006ae4636256b6e0f) --- drivers/soc/qcom/smem.c | 56 ++++++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 26 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 7e05e0555dcb4..4315512d3a1d4 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -88,9 +88,6 @@ /* Processor/host identifier for the global partition */ #define SMEM_GLOBAL_HOST 0xfffe -/* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 25 - /** * struct smem_proc_comm - proc_comm communication struct (legacy) * @command: current command to be executed @@ -285,7 +282,7 @@ struct qcom_smem { struct platform_device *socinfo; struct smem_ptable *ptable; struct smem_partition global_partition; - struct smem_partition partitions[SMEM_HOST_COUNT]; + struct xarray partitions; struct dentry *debugfs_dir; @@ -387,7 +384,7 @@ static struct qcom_smem *__smem = INIT_ERR_PTR(-EPROBE_DEFER); int qcom_smem_bust_hwspin_lock_by_host(unsigned int host) { /* This function is for remote procs, so ignore SMEM_HOST_APPS */ - if (host == SMEM_HOST_APPS || host >= SMEM_HOST_COUNT) + if (host == SMEM_HOST_APPS || !xa_load(&__smem->partitions, host)) return -EINVAL; return hwspin_lock_bust(__smem->hwlock, SMEM_HOST_ID_TO_HWSPINLOCK_ID(host)); @@ -535,8 +532,8 @@ int qcom_smem_alloc(unsigned host, unsigned item, size_t size) if (ret) return ret; - if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { - part = &__smem->partitions[host]; + part = xa_load(&__smem->partitions, host); + if (part) { ret = qcom_smem_alloc_private(__smem, part, item, size); } else if (__smem->global_partition.virt_base) { part = &__smem->global_partition; @@ -702,8 +699,8 @@ void *qcom_smem_get(unsigned host, unsigned item, size_t *size) if (item >= __smem->item_count) return ERR_PTR(-EINVAL); - if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { - part = &__smem->partitions[host]; + part = xa_load(&__smem->partitions, host); + if (part) { ptr = qcom_smem_get_private(__smem, part, item, size); } else if (__smem->global_partition.virt_base) { part = &__smem->global_partition; @@ -735,8 +732,8 @@ int qcom_smem_get_free_space(unsigned host) if (IS_ERR(__smem)) return PTR_ERR(__smem); - if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { - part = &__smem->partitions[host]; + part = xa_load(&__smem->partitions, host); + if (part) { phdr = part->virt_base; ret = le32_to_cpu(phdr->offset_free_cached) - le32_to_cpu(phdr->offset_free_uncached); @@ -779,12 +776,11 @@ phys_addr_t qcom_smem_virt_to_phys(void *p) { struct smem_partition *part; struct smem_region *area; + unsigned long index; u64 offset; u32 i; - for (i = 0; i < SMEM_HOST_COUNT; i++) { - part = &__smem->partitions[i]; - + xa_for_each(&__smem->partitions, index, part) { if (addr_in_range(part->virt_base, part->size, p)) { offset = p - part->virt_base; @@ -1021,16 +1017,20 @@ static int qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) { struct smem_partition_header *header; + struct smem_partition *part; struct smem_ptable_entry *entry; struct smem_ptable *ptable; u16 remote_host; u16 host0, host1; + int ret; int i; ptable = qcom_smem_get_ptable(smem); if (IS_ERR(ptable)) return PTR_ERR(ptable); + xa_init(&smem->partitions); + for (i = 0; i < le32_to_cpu(ptable->num_entries); i++) { entry = &ptable->entry[i]; if (!le32_to_cpu(entry->offset)) @@ -1047,12 +1047,7 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) else continue; - if (remote_host >= SMEM_HOST_COUNT) { - dev_err(smem->dev, "bad host %u\n", remote_host); - return -EINVAL; - } - - if (smem->partitions[remote_host].virt_base) { + if (xa_load(&smem->partitions, remote_host)) { dev_err(smem->dev, "duplicate host %u\n", remote_host); return -EINVAL; } @@ -1061,11 +1056,20 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) if (!header) return -EINVAL; - smem->partitions[remote_host].virt_base = (void __iomem *)header; - smem->partitions[remote_host].phys_base = smem->regions[0].aux_base + - le32_to_cpu(entry->offset); - smem->partitions[remote_host].size = le32_to_cpu(entry->size); - smem->partitions[remote_host].cacheline = le32_to_cpu(entry->cacheline); + part = devm_kzalloc(smem->dev, sizeof(struct smem_partition), GFP_KERNEL); + if (!part) + return -ENOMEM; + + part->virt_base = (void __iomem *)header; + part->phys_base = smem->regions[0].aux_base + le32_to_cpu(entry->offset); + part->size = le32_to_cpu(entry->size); + part->cacheline = le32_to_cpu(entry->cacheline); + + ret = xa_insert(&smem->partitions, remote_host, part, GFP_KERNEL); + if (ret) { + dev_err(smem->dev, "fail to insert host %u\n", remote_host); + return ret; + } } return 0; @@ -1234,7 +1238,6 @@ static int qcom_smem_probe(struct platform_device *pdev) return -EINVAL; } - BUILD_BUG_ON(SMEM_HOST_APPS >= SMEM_HOST_COUNT); ret = qcom_smem_enumerate_partitions(smem, SMEM_HOST_APPS); if (ret < 0 && ret != -ENOENT) return ret; @@ -1261,6 +1264,7 @@ static void qcom_smem_remove(struct platform_device *pdev) platform_device_unregister(__smem->socinfo); + xa_destroy(&__smem->partitions); /* Set to -EPROBE_DEFER to signal unprobed state */ __smem = ERR_PTR(-EPROBE_DEFER); } From 2b84b91d95a7e6ce137b76cfb43ca90c689f9831 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:47:54 +0530 Subject: [PATCH 0686/1330] dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk The DT bindings for inline-crypto engine do not specify the UFS_PHY_GDSC power-domain and iface clock. Without enabling the iface clock and the associated power-domain the ICE hardware cannot function correctly and leads to unclocked hardware accesses being observed during probe. Fix the DT bindings for inline-crypto engine to require the UFS_PHY_GDSC power-domain and iface clock for new devices (Eliza and Milos) introduced in the current release (7.0) with yet-to-stabilize ABI, while preserving backward compatibility for older devices. Fixes: 618195a7ac3df ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE") Fixes: 85faec1e85555 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE") Signed-off-by: Harshal Dev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-1-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit 2e348560beda37b05b333dd7c365e1cb3866bbba) --- .../crypto/qcom,inline-crypto-engine.yaml | 52 +++++++++++++++++-- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 1078de779c16e..a87db21fc900d 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -29,10 +29,14 @@ properties: maxItems: 1 clocks: + minItems: 1 maxItems: 2 clock-names: - maxItems: 2 + minItems: 1 + items: + - const: core + - const: iface power-domains: maxItems: 1 @@ -46,6 +50,25 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-inline-crypto-engine + - qcom,milos-inline-crypto-engine + + then: + required: + - power-domains + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + examples: - | #include @@ -54,10 +77,31 @@ examples: compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x01d88000 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; + + operating-points-v2 = <&ice_opp_table>; + + ice_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ... From bb0f00fc35add8d0b6a716287b6b0d8fa412c33a Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:47:55 +0530 Subject: [PATCH 0687/1330] soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver de-coupled from the QCOM UFS driver, it explicitly votes for its required clocks during probe. For scenarios where the 'clk_ignore_unused' flag is not passed on the kernel command line, to avoid potential unclocked ICE hardware register access during probe the ICE driver should additionally vote on the 'iface' clock. Also update the suspend and resume callbacks to handle un-voting and voting on the 'iface' clock. Fixes: 2afbf43a4aec6 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver") Signed-off-by: Harshal Dev Reviewed-by: Manivannan Sadhasivam Reviewed-by: Kuldeep Singh Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-2-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit 6869415c954be5f1a1f587c93582eaf2e18913d1) --- drivers/soc/qcom/ice.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 4b50d05ca02a3..722dce4d98eb9 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -316,8 +316,13 @@ int qcom_ice_resume(struct qcom_ice *ice) pm_runtime_get_sync(dev); err = clk_prepare_enable(ice->core_clk); if (err) { - dev_err(dev, "failed to enable core clock (%d)\n", - err); + dev_err(dev, "Failed to enable core clock: %d\n", err); + return err; + } + + err = clk_prepare_enable(ice->iface_clk); + if (err) { + dev_err(dev, "Failed to enable iface clock: %d\n", err); return err; } @@ -592,12 +597,14 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); if (!engine->core_clk) engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_optional_enabled(dev, "core"); if (!engine->core_clk) engine->core_clk = devm_clk_get_enabled(dev, NULL); if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); - engine->iface_clk = devm_clk_get_enabled(dev, "iface_clk"); + engine->iface_clk = devm_clk_get_optional_enabled(dev, "iface"); if (IS_ERR(engine->iface_clk)) return ERR_CAST(engine->iface_clk); From 68fc39b957600c9c9e09d1231e2868ee0a74d7f0 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:47:56 +0530 Subject: [PATCH 0688/1330] arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kaanapali. Fixes: 2eeb5767d53f4 ("arm64: dts: qcom: Introduce Kaanapali SoC") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-3-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit 8599ce043637af45a260629fb94292b3408a5d4d) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 3886cc5b76c3d..89451e7b49ab2 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2548,8 +2548,8 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; From 6dd9c18e416b4dc8bffef44b26dd662da4a58ab6 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:47:57 +0530 Subject: [PATCH 0689/1330] arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for lemans. Fixes: 96272ba7103d4 ("arm64: dts: qcom: sa8775p: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-4-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit 3212650d20acd771dae88ea929ba094621494a42) --- arch/arm64/boot/dts/qcom/lemans.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 96989086f0e9f..948f9f1c65db9 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2765,8 +2765,8 @@ reg = <0x0 0x01d88000 0x0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; From 02033c87e7f08cfb075a899066be7dbab8b12b2f Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:47:58 +0530 Subject: [PATCH 0690/1330] arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for monaco. Fixes: cc9d29aad876d ("arm64: dts: qcom: qcs8300: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-5-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit 95db34a67af72cf00620eab64c4391418d57113b) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index e7de7bea7c424..4d605140da0fe 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2741,8 +2741,8 @@ reg = <0x0 0x01d88000 0x0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; From 410cce05a77b02abfe6f2264e7b22ba48adc511b Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:47:59 +0530 Subject: [PATCH 0691/1330] arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sc7180. Fixes: 858536d9dc946 ("arm64: dts: qcom: sc7180: Add UFS nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-6-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit b7a913f72283681ee75dcc9c6b60b49b80aa51aa) --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 74eb895cf4da7..d6e01aca4c5a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1607,8 +1607,8 @@ reg = <0 0x01d90000 0 0x8000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; From 7a63cfa7dddeb7f27bce4436e0762a480886413f Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:48:00 +0530 Subject: [PATCH 0692/1330] arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kodiak. Fixes: dfd5ee7b34bb7 ("arm64: dts: qcom: sc7280: Add inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Tested-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-7-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit 65e12242d4a088f7451713c2efd8906e13968706) --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 24b240492cf4c..a9f974eaac572 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2590,8 +2590,8 @@ reg = <0 0x01d88000 0 0x8000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; From 74660b723c8fb06a79e39d698b2e019151b20c31 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:48:01 +0530 Subject: [PATCH 0693/1330] arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450. Fixes: 86b0aef435851 ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-8-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit eaa857a6a71fc14528a4e468c3d1d77b098f3873) --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 5d99712f23393..3a003e64c4073 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5376,8 +5376,8 @@ reg = <0 0x01d88000 0 0x8000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; From 3ec86f80ec266e02bd02722fedda7bb93eaa9fd1 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:48:02 +0530 Subject: [PATCH 0694/1330] arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8550. Fixes: b8630c48b43fc ("arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-9-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit b47b00009acd194af70fddbf9ddab5e0f13e242f) --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 04dc9d6a251a5..d2a616fc27835 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2451,8 +2451,8 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; From 6ddfa002a77dc25c5d2f5da38db6d65e2ab64382 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:48:03 +0530 Subject: [PATCH 0695/1330] arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8650. Fixes: 10e0246712951 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-10-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit ff23c9251656ce5f4e6ad3f93c1d7f3707102fdc) --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 802c92bc51e10..f6c2d5b01732e 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4083,8 +4083,8 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; From 91ac555e370fdc5939a1d09d8495982420f6fa2f Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Mon, 23 Mar 2026 14:48:04 +0530 Subject: [PATCH 0696/1330] arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8750. Fixes: b1dac789c650a ("arm64: dts: qcom: sm8750: Add ICE nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260323-qcom_ice_power_and_clk_vote-v4-11-e36044bbdfe9@oss.qualcomm.com (cherry picked from commit 9a09c47c497668220d70d46e3992c0818c184ae8) --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 2441bb7063bc6..0bb75ee63918d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2117,8 +2117,8 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; From 2fe28d8ad87d5cf7bd5355eb78d6ea39467d9c85 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 2 Apr 2026 00:05:09 +0530 Subject: [PATCH 0697/1330] arm64: dts: qcom: kodiak: Fix ICE reg size The ICE register region on Kodiak is currently defined as 0x8000 bytes. According to the hardware specification, the correct register size is 0x18000. Update the ICE node reg property to match the hardware. Fixes: dfd5ee7b34bb ("arm64: dts: qcom: sc7280: Add inline crypto engine") Signed-off-by: Kuldeep Singh Reviewed-by: Harshal Dev Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-1-74e4c2129238@oss.qualcomm.com (cherry picked from commit 13f0207fa579cf5a92d9550043f5435d843f2a8a) --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index a9f974eaac572..385dbc225ca53 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2587,7 +2587,7 @@ ice: crypto@1d88000 { compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; clock-names = "core", From 97a9176f02a65871d56e7a60acb08a1934a1d2ff Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 2 Apr 2026 00:05:10 +0530 Subject: [PATCH 0698/1330] arm64: dts: qcom: sm8450: Fix ICE reg size The ICE register region size was originally described incorrectly when the ICE hardware was first introduced. The same value was later carried over unchanged when the ICE node was split out from the UFS node into its own DT entry. Correct the register size to match the hardware specification. Fixes: 276ee34a40c1 ("arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock") Signed-off-by: Kuldeep Singh Reviewed-by: Harshal Dev Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-2-74e4c2129238@oss.qualcomm.com (cherry picked from commit 6dfd834f61048cec37fc676092baca1128e35ed6) --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 3a003e64c4073..bfbb18532c166 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5373,7 +5373,7 @@ ice: crypto@1d88000 { compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; clock-names = "core", From e8107f0862d1e4ee7eb19f8a46a5120a2c0744be Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 6 Apr 2026 21:13:20 +0530 Subject: [PATCH 0699/1330] arm64: dts: qcom: kodiak: Add iface clock and power domain for ice sdhc Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if power domain is enabled. Specify both power domain and the iface clock. Link: https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-1-90bbcc057361@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh (cherry picked from commit 090f8a6e4d63229c20ec0e80889335a9abb39883) --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 385dbc225ca53..b8bdbd2e0522b 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -1082,7 +1082,11 @@ compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x007c8000 0x0 0x18000>; - clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&rpmhpd SC7280_CX>; }; gpi_dma0: dma-controller@900000 { From b7055878783be041460c61355785b6f73276575b Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 6 Apr 2026 21:18:21 +0530 Subject: [PATCH 0700/1330] arm64: dts: qcom: monaco: Add iface clock and power domain for ice sdhc Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if power domain is enabled. Specify both power domain and the iface clock. Link: https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-2-90bbcc057361@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh (cherry picked from commit 642b88a0cb4caeae047f5e70f516be0c22b26302) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 4d605140da0fe..bd31d526cc8a9 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4796,7 +4796,11 @@ compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x087c8000 0x0 0x18000>; - clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&rpmhpd RPMHPD_CX>; }; usb_1_hsphy: phy@8904000 { From d0359b9eaa65dbe68b009c2e30d2fa70826ce51b Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Fri, 10 Apr 2026 12:02:40 +0530 Subject: [PATCH 0701/1330] FROMLIST: soc: qcom: ice: Add OPP-based clock scaling support for ICE Register optional operation-points-v2 table for ICE device during device probe. Attach the OPP-table with only the ICE core clock. Since, dtbinding is on a trasition phase to include iface clock and clock-names, attaching the opp-table to core clock remains options such that it does not cause probe failures. Introduce clock scaling API qcom_ice_scale_clk which scale ICE core clock based on the target frequency provided and if a valid OPP-table is registered. Use round_ceil passed to decide on the rounding of the clock freq against OPP-table. Clock scaling is disabled when a valid OPP-table is not registered. This ensures when an ICE-device specific OPP table is available, use the PM OPP framework to manage frequency scaling and maintain proper power-domain constraints. Also, ensure to drop the votes in suspend to prevent power/thermal retention. Subsequently restore the frequency in resume from core_clk_freq which stores the last ICE core clock operating frequency. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-1-ca1129798606@oss.qualcomm.com/ Signed-off-by: Abhinaba Rakshit (cherry picked from commit 619f570a7c0815328b876827a0fcb2d8b84a4cd1) --- drivers/soc/qcom/ice.c | 96 ++++++++++++++++++++++++++++++++++++++++-- include/soc/qcom/ice.h | 2 + 2 files changed, 94 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 722dce4d98eb9..e6a0e647c9b1d 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,8 +16,7 @@ #include #include #include -#include -#include +#include #include @@ -114,6 +113,8 @@ struct qcom_ice { bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; + unsigned long core_clk_freq; + bool has_opp; }; static bool qcom_ice_check_supported(struct qcom_ice *ice) @@ -313,7 +314,10 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev = ice->dev; int err; - pm_runtime_get_sync(dev); + /* Restore the ICE core clk freq */ + if (ice->has_opp && ice->core_clk_freq) + dev_pm_opp_set_rate(ice->dev, ice->core_clk_freq); + err = clk_prepare_enable(ice->core_clk); if (err) { dev_err(dev, "Failed to enable core clock: %d\n", err); @@ -341,7 +345,11 @@ int qcom_ice_suspend(struct qcom_ice *ice) { clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); - pm_runtime_put_sync(ice->dev); + + /* Drop the clock votes while suspend */ + if (ice->has_opp) + dev_pm_opp_set_rate(ice->dev, 0); + ice->hwkm_init_complete = false; return 0; @@ -567,6 +575,51 @@ int qcom_ice_import_key(struct qcom_ice *ice, } EXPORT_SYMBOL_GPL(qcom_ice_import_key); +/** + * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations + * @ice: ICE driver data + * @target_freq: requested frequency in Hz + * @round_ceil: when true, selects nearest freq >= @target_freq; + * otherwise, selects nearest freq <= @target_freq + * + * Selects an OPP frequency based on @target_freq and the rounding direction + * specified by @round_ceil, then programs it using dev_pm_opp_set_rate(), + * including any voltage or power-domain transitions handled by the OPP + * framework. Updates ice->core_clk_freq on success. + * + * Return: 0 on success; -EOPNOTSUPP if no OPP table; or error from + * dev_pm_opp_set_rate()/OPP lookup. + */ +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq, + bool round_ceil) +{ + unsigned long ice_freq = target_freq; + struct dev_pm_opp *opp; + int ret; + + if (!ice->has_opp) + return -EOPNOTSUPP; + + if (round_ceil) + opp = dev_pm_opp_find_freq_ceil(ice->dev, &ice_freq); + else + opp = dev_pm_opp_find_freq_floor(ice->dev, &ice_freq); + + if (IS_ERR(opp)) + return PTR_ERR(opp); + dev_pm_opp_put(opp); + + ret = dev_pm_opp_set_rate(ice->dev, ice_freq); + if (ret) { + dev_err(ice->dev, "Unable to scale ICE clock rate\n"); + return ret; + } + ice->core_clk_freq = ice_freq; + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk); + static struct qcom_ice *qcom_ice_create(struct device *dev, void __iomem *base) { @@ -742,6 +795,7 @@ static int qcom_ice_probe(struct platform_device *pdev) { struct qcom_ice *engine; void __iomem *base; + int err; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) { @@ -756,6 +810,40 @@ static int qcom_ice_probe(struct platform_device *pdev) if (IS_ERR(engine)) return PTR_ERR(engine); + /* qcom_ice_create() may return NULL if scm calls are not available */ + if (!engine) + return -EOPNOTSUPP; + + err = devm_pm_opp_set_clkname(&pdev->dev, "core"); + if (err && err != -ENOENT) { + dev_err(&pdev->dev, "Unable to set core clkname to OPP-table\n"); + return err; + } + + /* OPP table is optional */ + err = devm_pm_opp_of_add_table(&pdev->dev); + if (err && err != -ENODEV) { + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); + return err; + } + + /* + * The OPP table is optional. devm_pm_opp_of_add_table() returns + * -ENODEV when no OPP table is present in DT, which is not treated + * as an error. Therefore, track successful OPP registration only + * when the return value is 0. + */ + engine->has_opp = (err == 0); + if (!engine->has_opp) + dev_info(&pdev->dev, "ICE OPP table is not registered, please update your DT\n"); + + /* + * Store the core clock rate for suspend resume cycles, + * against OPP aware DVFS operations. core_clk_freq will + * have a valid value only for non-legacy bindings. + */ + engine->core_clk_freq = clk_get_rate(engine->core_clk); + platform_set_drvdata(pdev, engine); return 0; diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h index 4bee553f0a59d..4eb58a264d416 100644 --- a/include/soc/qcom/ice.h +++ b/include/soc/qcom/ice.h @@ -30,5 +30,7 @@ int qcom_ice_import_key(struct qcom_ice *ice, const u8 *raw_key, size_t raw_key_size, u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]); struct qcom_ice *devm_of_qcom_ice_get(struct device *dev); +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq, + bool round_ceil); #endif /* __QCOM_ICE_H__ */ From 7d7f4eaa08e124b60c49403a0f03e73d91a5f278 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Fri, 10 Apr 2026 12:04:30 +0530 Subject: [PATCH 0702/1330] FROMLIST: ufs: host: Add ICE clock scaling during UFS clock changes Implement ICE (Inline Crypto Engine) clock scaling in sync with UFS controller clock scaling. This ensures that the ICE operates at an appropriate frequency when the UFS clocks are scaled up or down, improving performance and maintaining stability for crypto operations. For scale_up operation ensure to pass ~round_ceil (round_floor) and vice-versa for scale_down operations. Incase of OPP scaling is not supported by ICE, ensure to not prevent devfreq for UFS, as ICE OPP-table is optional. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-2-ca1129798606@oss.qualcomm.com/ Acked-by: Manivannan Sadhasivam Signed-off-by: Abhinaba Rakshit (cherry picked from commit c864c2b431f60ebc66ba156fa03708e405220aa0) --- drivers/ufs/host/ufs-qcom.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 243133f59a896..4c61c31820f01 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -306,6 +306,15 @@ static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile, return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); } +static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq, + bool round_ceil) +{ + if (host->hba->caps & UFSHCD_CAP_CRYPTO) + return qcom_ice_scale_clk(host->ice, target_freq, round_ceil); + + return 0; +} + static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = { .keyslot_program = ufs_qcom_ice_keyslot_program, .keyslot_evict = ufs_qcom_ice_keyslot_evict, @@ -340,6 +349,12 @@ static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) { } +static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq, + bool round_ceil) +{ + return 0; +} + #endif static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) @@ -1743,12 +1758,17 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, else err = ufs_qcom_clk_scale_down_post_change(hba, target_freq); - if (err) { ufshcd_uic_hibern8_exit(hba); return err; } + err = ufs_qcom_ice_scale_clk(host, target_freq, !scale_up); + if (err && err != -EOPNOTSUPP) { + ufshcd_uic_hibern8_exit(hba); + return err; + } + ufs_qcom_icc_update_bw(host); ufshcd_uic_hibern8_exit(hba); } From b467df857f2ed78b6a637de5ee10d139c67f9db2 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Fri, 10 Apr 2026 12:07:58 +0530 Subject: [PATCH 0703/1330] FROMLIST: mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init MMC controller lacks a clock scaling mechanism, unlike the UFS controller. By default, the MMC controller is set to TURBO mode during probe, but the ICE clock remains at XO frequency, leading to read/write performance degradation on eMMC. To address this, set the ICE clock to TURBO during sdhci_msm_ice_init to align it with the controller clock. This ensures consistent performance and avoids mismatches between the controller and ICE clock frequencies. For platforms where ICE is represented as a separate device, use the OPP framework to vote for TURBO mode, maintaining proper voltage and power domain constraints. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-3-ca1129798606@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Abhinaba Rakshit (cherry picked from commit ec066a091ca362d64c30fdcf53d5867b17c0ef83) --- drivers/mmc/host/sdhci-msm.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index d9338387edd58..111a437244d6b 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1889,6 +1889,8 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) #ifdef CONFIG_MMC_CRYPTO static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */ +static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq, + bool round_ceil); /* forward decl */ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, struct cqhci_host *cq_host) @@ -1948,6 +1950,11 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, mmc->caps2 |= MMC_CAP2_CRYPTO; mmc->caps2 |= MMC_CAP2_CRYPTO_NO_REPROG; + + err = sdhci_msm_ice_scale_clk(msm_host, INT_MAX, false); + if (err && err != -EOPNOTSUPP) + dev_warn(dev, "Unable to boost ICE clock to TURBO\n"); + return 0; } @@ -1973,6 +1980,16 @@ static int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host) return 0; } +static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, + unsigned long target_freq, + bool round_ceil) +{ + if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) + return qcom_ice_scale_clk(msm_host->ice, target_freq, round_ceil); + + return 0; +} + static inline struct sdhci_msm_host * sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile) { @@ -2076,6 +2093,13 @@ sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host) { return 0; } + +static inline int +sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq, + bool round_ceil) +{ + return 0; +} #endif /* !CONFIG_MMC_CRYPTO */ /*****************************************************************************\ From cf7d41ab4f5559fc0d470c1392963e0e2429f698 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Fri, 10 Apr 2026 12:10:58 +0530 Subject: [PATCH 0704/1330] FROMLIST: arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE eMMC nodes Qualcomm Inline Crypto Engine (ICE) platform driver now, supports an optional OPP-table. Add OPP-table for ICE UFS and ICE eMMC device nodes for Kodiak platform. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-4-ca1129798606@oss.qualcomm.com/ Signed-off-by: Abhinaba Rakshit (cherry picked from commit 20819a018d8917bfc38d27137962280bc37c3539) --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index b8bdbd2e0522b..cea8581d291ef 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -1087,6 +1087,27 @@ clock-names = "core", "iface"; power-domains = <&rpmhpd SC7280_CX>; + + operating-points-v2 = <&ice_mmc_opp_table>; + + ice_mmc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; gpi_dma0: dma-controller@900000 { @@ -2597,6 +2618,27 @@ clock-names = "core", "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; + + operating-points-v2 = <&ice_opp_table>; + + ice_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; cryptobam: dma-controller@1dc4000 { From dc6eb78e5b85cfb317eb5a39f18aac0d63689e2a Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Fri, 10 Apr 2026 12:14:03 +0530 Subject: [PATCH 0705/1330] FROMLIST: arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE eMMC nodes Qualcomm Inline Crypto Engine (ICE) platform driver now, supports an optional OPP-table. Add OPP-table for ICE UFS and ICE eMMC device nodes for Monaco platform. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-5-ca1129798606@oss.qualcomm.com/ Signed-off-by: Abhinaba Rakshit (cherry picked from commit 1564b829d7522416a7f06506f0c800139c0c1680) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index bd31d526cc8a9..2a2bcce4cb9c3 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2744,6 +2744,22 @@ clock-names = "core", "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; + + operating-points-v2 = <&ice_opp_table>; + + ice_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-201600000 { + opp-hz = /bits/ 64 <201600000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; crypto: crypto@1dfa000 { @@ -4801,6 +4817,22 @@ clock-names = "core", "iface"; power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&ice_mmc_opp_table>; + + ice_mmc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; usb_1_hsphy: phy@8904000 { From 7cdd378c317dc5d43f97f5df9c2975c33199f9d4 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 28 Apr 2026 14:50:22 +0800 Subject: [PATCH 0706/1330] PENDING: arm64: dts: qcom: glymur: add TGU and ETR in staging dtso Add TGU devices for supporting IPCB feature in staging dtso file and add ETR devices for supporting DDR memory trace. Signed-off-by: Jie Gan (cherry picked from commit ef11d92a47a0b9e89ebd385a3e7887d80855c54b) --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/glymur-staging.dtso | 201 +++++++++++++++++++ 2 files changed, 203 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/glymur-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 512a4615e0682..090dd48a0586a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -516,3 +516,5 @@ dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camx.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += kodiak-staging.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += glymur-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/glymur-staging.dtso b/arch/arm64/boot/dts/qcom/glymur-staging.dtso new file mode 100644 index 0000000000000..0b95e568e1c00 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-staging.dtso @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Glymur staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +&soc { + ctcu@10001000 { + compatible = "qcom,glymur-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x10001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + + replicator@10046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc@10048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x00e0 0x0000>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@1004e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x1004e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc@1004f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x1004f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x0100 0x0000>; + + arm,scatter-gather; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + + tgu@11c02000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x11c02000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + replicator@11c06000 { + out-ports { + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + }; + }; + + tgu@11c0e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x11c0e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@11c0f000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x11c0f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@11c10000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x11c10000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; From 1b1da93422691f8f9e099cc6739d4a78939ee97b Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Thu, 16 Apr 2026 08:42:11 +0530 Subject: [PATCH 0707/1330] FROMLIST: phy: qcom: edp: Initialize swing_pre_emph_cfg for sc7280 Aux timeout is observed on few monitors like Benq BL2420-T due to missing swing_pre_emph_cfg. Link: https://lore.kernel.org/r/20260403-phy_for_next-v1-1-3d336b555019@oss.qualcomm.com Signed-off-by: Vishnu Saini (cherry picked from commit 56ccbf40aba9e63c5917bd041bc51dce8a05a75d) --- drivers/phy/qualcomm/phy-qcom-edp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index a817d817ec2f3..e38ec2e972802 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -563,6 +563,7 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = { static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = { .aux_cfg = edp_phy_aux_cfg_v4, .vco_div_cfg = edp_phy_vco_div_cfg_v4, + .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, .ver_ops = &qcom_edp_phy_ops_v4, }; From 82568f4bee3b973cf8f1ad162581ac956d627107 Mon Sep 17 00:00:00 2001 From: Vishwas Udupa Date: Fri, 3 Apr 2026 02:17:06 -0700 Subject: [PATCH 0708/1330] FROMLIST: arm64: dts: qcom: install DT overlays via dtbs_install Overlay binaries (.dtbo) are currently only built implicitly as dependencies of composite firmware images and are therefore absent from the kernel install output. Even when final DTBs are produced at build time, some distributions rely on standalone DTBOs for runtime selection and application by bootloaders or firmware. Without explicit install targets, DTBOs are not picked up by the standard dtbs_install flow and therefore cannot be packaged alongside DTBs. Add explicit dtb-$(CONFIG_ARCH_QCOM) entries for all DT overlays defined in this Makefile so they are installed via dtbs_install, matching existing DTB install behaviour. Link: https://lore.kernel.org/all/20260428123725.3457865-1-vudupa@qti.qualcomm.com Signed-off-by: Vishwas Udupa (cherry picked from commit 7998dbf1695da00ef7a54c3fe90328e251400c90) --- arch/arm64/boot/dts/qcom/Makefile | 36 ++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 090dd48a0586a..f795f8a8ac70e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -7,7 +7,9 @@ apq8016-sbc-usb-host-dtbs := apq8016-sbc.dtb apq8016-sbc-usb-host.dtbo dtb-$(CONFIG_ARCH_QCOM) += sar2130p-qar2130p.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-usb-host.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-usb-host.dtbo dtb-$(CONFIG_ARCH_QCOM) += apq8016-schneider-hmibsc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb @@ -46,18 +48,24 @@ lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx5 lemans-evk-camera-dtbs := lemans-evk.dtb lemans-evk-camera.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtbo lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb -dtb-$(CONFIG_ARCH_QCOM) += monaco-ac-evk.dtb + +monaco-evk-camera-imx577-dtbs := monaco-evk.dtb monaco-evk-camera-imx577.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtbo monaco-evk-el2-dtbs := monaco-evk.dtb monaco-el2.dtbo @@ -69,6 +77,7 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb @@ -166,6 +175,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb qcs615-ride-el2-dtbs := qcs615-ride.dtb talos-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb @@ -173,13 +183,17 @@ qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vis qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtbo +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-minipc-g1iot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb @@ -189,6 +203,7 @@ qcs9100-ride-r3-el2-dtbs := qcs9100-ride-r3.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-arduino-imola.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb @@ -196,6 +211,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb qrb2210-rb1-vision-mezzanine-dtbs := qrb2210-rb1.dtb qrb2210-rb1-vision-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1-vision-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb @@ -203,6 +219,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb qrb5165-rb5-vision-mezzanine-dtbs := qrb5165-rb5.dtb qrb5165-rb5-vision-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb @@ -211,6 +228,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb sc7180-acer-aspire1-el2-dtbs := sc7180-acer-aspire1.dtb sc7180-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb sc7180-acer-aspire1-el2.dtb +sc7180-ecs-liva-qc710-el2-dtbs := sc7180-ecs-liva-qc710.dtb sc7180-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc7180-ecs-liva-qc710.dtb sc7180-ecs-liva-qc710-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb @@ -286,6 +306,7 @@ sc8280xp-microsoft-arcata-el2-dtbs := sc8280xp-microsoft-arcata.dtb sc8280xp-el2 dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb sc8280xp-microsoft-arcata-el2.dtb sc8280xp-microsoft-blackrock-el2-dtbs := sc8280xp-microsoft-blackrock.dtb sc8280xp-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-blackrock.dtb sc8280xp-microsoft-blackrock-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-lenovo-tbx605f.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb @@ -303,6 +324,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb @@ -365,7 +387,11 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb sm8550-hdk-rear-camera-card-dtbs := sm8550-hdk.dtb sm8550-hdk-rear-camera-card.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card-rear-camera-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card.dtbo dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-rear-camera-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-rear-camera-card.dtbo dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb @@ -378,7 +404,9 @@ sm8650-hdk-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-rear-camera-card.d dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card-rear-camera-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtbo dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-rear-camera-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-rear-camera-card.dtbo dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb @@ -386,6 +414,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-evk.dtb talos-evk-usb1-peripheral-dtbs := talos-evk.dtb talos-evk-usb1-peripheral.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-usb1-peripheral.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-usb1-peripheral.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtbo talos-evk-camera-imx577-dtbs := talos-evk.dtb talos-evk-camera-imx577.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-usb1-peripheral.dtb @@ -393,6 +423,7 @@ talos-evk-lvds-auo,g133han01-dtbs := \ talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtbo x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo @@ -445,8 +476,7 @@ x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2 dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb -x1p64100-acer-swift-sf14-11-el2-dtbs := x1p64100-acer-swift-sf14-11.dtb x1-el2.dtbo -dtb-$(CONFIG_ARCH_QCOM) += x1p64100-acer-swift-sf14-11.dtb x1p64100-acer-swift-sf14-11-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += x1-el2.dtbo hamoa-evk-camx-dtbs := hamoa-iot-evk.dtb hamoa-evk-camx.dtbo From bf734d1939687a7f9ed06534a639e1baa96cf2e1 Mon Sep 17 00:00:00 2001 From: Vishwas Udupa Date: Thu, 30 Apr 2026 03:53:25 -0700 Subject: [PATCH 0709/1330] QCLINUX: arm64: dts: qcom: Install camx DTBO overlays Install Qualcomm camx DTBO overlay files by adding them to the dtb-$(CONFIG_ARCH_QCOM) build/install list This makes DTBOs available through the standard dtbs_install flow and ensures they are included in distro kernel packages Signed-off-by: Vishwas Udupa (cherry picked from commit abfeee71ec2257a591930d301f965151539d1380) --- arch/arm64/boot/dts/qcom/Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f795f8a8ac70e..da46dd5d124d7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -481,14 +481,17 @@ dtb-$(CONFIG_ARCH_QCOM) += x1-el2.dtbo hamoa-evk-camx-dtbs := hamoa-iot-evk.dtb hamoa-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-evk-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += hamoa-evk-camx.dtbo lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camx.dtbo lemans-camx-el2-dtbs := lemans-evk-el2.dtb lemans-evk-camx.dtbo lemans-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo @@ -497,10 +500,12 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtbo monaco-camx-el2-dtbs := monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo @@ -509,11 +514,13 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtbo qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.dtb \ qcs6490-rb3gen2-vision-mezzanine-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-staging.dtbo @@ -522,6 +529,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine-staging.dtbo qcs8300-ride-camx-dtbs:= qcs8300-ride.dtb qcs8300-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-camx.dtbo qcs9100-ride-camx-dtbs:= qcs9100-ride.dtb sa8775p-ride-camx.dtbo @@ -534,6 +542,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3-camx.dtb sa8775p-ride-camx-dtbs:= sa8775p-ride.dtb sa8775p-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-camx.dtbo sa8775p-ride-r3-camx-dtbs:= sa8775p-ride-r3.dtb sa8775p-ride-camx.dtbo @@ -542,6 +551,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3-camx.dtb talos-evk-camx-dtbs := talos-evk.dtb talos-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-staging.dtbo From 2e7b786a569081e854e1916a52b5e33ceb87d2ab Mon Sep 17 00:00:00 2001 From: Maya Matuszczyk Date: Mon, 27 Apr 2026 15:34:52 +0530 Subject: [PATCH 0710/1330] FROMLIST: dt-bindings: embedded-controller: Add Qualcomm reference device EC description Add description for the EC firmware running on Hamoa/Purwa and Glymur reference devices. List: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-1-702f74e495f7@oss.qualcomm.com/ Signed-off-by: Maya Matuszczyk Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Reviewed-by: Krzysztof Kozlowski Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P (cherry picked from commit c2f87509a84c782eecda23c43634e9980a18f93d) --- .../qcom,hamoa-crd-ec.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml diff --git a/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml new file mode 100644 index 0000000000000..ac5a08f8f76df --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/qcom,hamoa-crd-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hamoa Embedded Controller + +maintainers: + - Sibi Sankar + - Anvesh Jain P + +description: + Qualcomm Snapdragon based Hamoa/Purwa and Glymur reference devices have an + EC running on different MCU chips. The EC handles things like fan control, + temperature sensors, access to EC internal state changes. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,glymur-crd-ec + - qcom,hamoa-iot-evk-ec + - const: qcom,hamoa-crd-ec + - enum: + - qcom,hamoa-crd-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@76 { + compatible = "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... From 4ceb6f8ea02e641f12fc79c95f17c2db9010e837 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 27 Apr 2026 15:34:53 +0530 Subject: [PATCH 0711/1330] FROMLIST: platform: arm64: Add driver for EC found on Qualcomm reference devices Add Embedded controller driver support for Hamoa/Purwa/Glymur qualcomm reference boards. It handles fan control, temperature sensors, access to EC state changes and supports reporting suspend entry/exit to the EC. List: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-2-702f74e495f7@oss.qualcomm.com/ Co-developed-by: Maya Matuszczyk Signed-off-by: Maya Matuszczyk Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Acked-by: Konrad Dybcio Tested-by: Akhil P Oommen Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P (cherry picked from commit 069ea63569dca468e6fda270ad396ce580a75325) --- MAINTAINERS | 8 + drivers/platform/arm64/Kconfig | 15 +- drivers/platform/arm64/Makefile | 2 +- drivers/platform/arm64/qcom-hamoa-ec.c | 452 +++++++++++++++++++++++++ 4 files changed, 469 insertions(+), 8 deletions(-) create mode 100644 drivers/platform/arm64/qcom-hamoa-ec.c diff --git a/MAINTAINERS b/MAINTAINERS index dcf36cbd90243..33746655481d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21758,6 +21758,14 @@ F: Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml F: drivers/misc/fastrpc.c F: include/uapi/misc/fastrpc.h +QUALCOMM HAMOA EMBEDDED CONTROLLER DRIVER +M: Anvesh Jain P +M: Sibi Sankar +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml +F: drivers/platform/arm64/qcom-hamoa-ec.c + QUALCOMM HEXAGON ARCHITECTURE M: Brian Cain L: linux-hexagon@vger.kernel.org diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig index c1ca1d78eeb86..e32e01b2a9bdd 100644 --- a/drivers/platform/arm64/Kconfig +++ b/drivers/platform/arm64/Kconfig @@ -90,16 +90,17 @@ config EC_LENOVO_THINKPAD_T14S Say M or Y here to include this support. -config EC_LENOVO_YOGA_SLIM7X - tristate "Lenovo Yoga Slim 7x Embedded Controller driver" +config EC_QCOM_HAMOA + tristate "Embedded Controller driver for Qualcomm Hamoa/Glymur reference devices" depends on ARCH_QCOM || COMPILE_TEST depends on I2C + depends on THERMAL || THERMAL=n help - Select this option to enable driver for the EC found in the Lenovo - Yoga Slim 7x. + Say M or Y here to enable the Embedded Controller driver for Qualcomm + Snapdragon-based Hamoa/Glymur reference devices. The driver handles fan + control, temperature sensors, access to EC state changes and supports + reporting suspend entry/exit to the EC. - This driver currently supports reporting input event for microphone - mute button, and reporting device suspend to the EC so it can take - appropriate actions. + This driver currently supports Hamoa/Purwa/Glymur reference devices. endif # ARM64_PLATFORM_DEVICES diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile index c135a895a3ea5..7681be4a46e94 100644 --- a/drivers/platform/arm64/Makefile +++ b/drivers/platform/arm64/Makefile @@ -9,4 +9,4 @@ obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o obj-$(CONFIG_EC_HUAWEI_GAOKUN) += huawei-gaokun-ec.o obj-$(CONFIG_EC_LENOVO_YOGA_C630) += lenovo-yoga-c630.o obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) += lenovo-thinkpad-t14s.o -obj-$(CONFIG_EC_LENOVO_YOGA_SLIM7X) += lenovo-yoga-slim7x.o +obj-$(CONFIG_EC_QCOM_HAMOA) += qcom-hamoa-ec.o diff --git a/drivers/platform/arm64/qcom-hamoa-ec.c b/drivers/platform/arm64/qcom-hamoa-ec.c new file mode 100644 index 0000000000000..253f927c9aca7 --- /dev/null +++ b/drivers/platform/arm64/qcom-hamoa-ec.c @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Maya Matuszczyk + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EC_SCI_EVT_READ_CMD 0x05 +#define EC_FW_VERSION_CMD 0x0e +#define EC_MODERN_STANDBY_CMD 0x23 +#define EC_FAN_DBG_CONTROL_CMD 0x30 +#define EC_SCI_EVT_CONTROL_CMD 0x35 +#define EC_THERMAL_CAP_CMD 0x42 + +#define EC_FW_VERSION_RESP_LEN 4 +#define EC_THERMAL_CAP_RESP_LEN 3 +#define EC_FAN_DEBUG_CMD_LEN 6 +#define EC_FAN_SPEED_DATA_SIZE 4 + +#define EC_MODERN_STANDBY_ENTER 0x01 +#define EC_MODERN_STANDBY_EXIT 0x00 + +#define EC_FAN_DEBUG_MODE_OFF 0 +#define EC_FAN_DEBUG_MODE_ON BIT(0) +#define EC_FAN_ON BIT(1) +#define EC_FAN_DEBUG_TYPE_PWM BIT(2) +#define EC_MAX_FAN_CNT 2 +#define EC_FAN_NAME_SIZE 20 +#define EC_FAN_MAX_PWM 255 + +enum qcom_ec_sci_events { + EC_FAN1_STATUS_CHANGE_EVT = 0x30, + EC_FAN2_STATUS_CHANGE_EVT, + EC_FAN1_SPEED_CHANGE_EVT, + EC_FAN2_SPEED_CHANGE_EVT, + EC_NEW_LUT_SET_EVT, + EC_FAN_PROFILE_SWITCH_EVT, + EC_THERMISTOR_1_THRESHOLD_CROSS_EVT, + EC_THERMISTOR_2_THRESHOLD_CROSS_EVT, + EC_THERMISTOR_3_THRESHOLD_CROSS_EVT, + /* Reserved: 0x39 - 0x3c/0x3f */ + EC_RECOVERED_FROM_RESET_EVT = 0x3d, +}; + +struct qcom_ec_version { + u8 main_version; + u8 sub_version; + u8 test_version; +}; + +struct qcom_ec_thermal_cap { +#define EC_THERMAL_FAN_CNT(x) (FIELD_GET(GENMASK(1, 0), (x))) +#define EC_THERMAL_FAN_TYPE(x) (FIELD_GET(GENMASK(4, 2), (x))) +#define EC_THERMAL_THERMISTOR_MASK(x) (FIELD_GET(GENMASK(7, 0), (x))) + u8 fan_cnt; + u8 fan_type; + u8 thermistor_mask; +}; + +struct qcom_ec_cooling_dev { + struct thermal_cooling_device *cdev; + struct device *parent_dev; + u8 fan_id; + u8 state; +}; + +struct qcom_ec { + struct qcom_ec_cooling_dev *ec_cdev; + struct qcom_ec_thermal_cap thermal_cap; + struct qcom_ec_version version; + struct i2c_client *client; +}; + +static int qcom_ec_read(struct qcom_ec *ec, u8 cmd, u8 resp_len, u8 *resp) +{ + int ret; + + ret = i2c_smbus_read_i2c_block_data(ec->client, cmd, resp_len, resp); + + if (ret < 0) + return ret; + else if (ret == 0 || ret == 0xff) + return -EOPNOTSUPP; + + if (resp[0] >= resp_len) + return -EINVAL; + + return 0; +} + +/* + * EC Device Firmware Version: + * + * Read Response: + * ---------------------------------------------------------------------- + * | Offset | Name | Description | + * ---------------------------------------------------------------------- + * | 0x00 | Byte count | Number of bytes in response | + * | | | (excluding byte count) | + * ---------------------------------------------------------------------- + * | 0x01 | Test-version | Test-version of EC firmware | + * ---------------------------------------------------------------------- + * | 0x02 | Sub-version | Sub-version of EC firmware | + * ---------------------------------------------------------------------- + * | 0x03 | Main-version | Main-version of EC firmware | + * ---------------------------------------------------------------------- + * + */ +static int qcom_ec_read_fw_version(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct qcom_ec *ec = i2c_get_clientdata(client); + struct qcom_ec_version *version = &ec->version; + u8 resp[EC_FW_VERSION_RESP_LEN]; + int ret; + + ret = qcom_ec_read(ec, EC_FW_VERSION_CMD, EC_FW_VERSION_RESP_LEN, resp); + if (ret < 0) + return ret; + + version->main_version = resp[3]; + version->sub_version = resp[2]; + version->test_version = resp[1]; + + dev_dbg(dev, "EC Version %d.%d.%d\n", + version->main_version, version->sub_version, version->test_version); + + return 0; +} + +/* + * EC Device Thermal Capabilities: + * + * Read Response: + * ------------------------------------------------------------------------------ + * | Offset | Name | Description | + * ------------------------------------------------------------------------------ + * | 0x00 | Byte count | Number of bytes in response | + * | | | (excluding byte count) | + * ------------------------------------------------------------------------------ + * | 0x02 (LSB) | EC Thermal | Bit 0-1: Number of fans | + * | 0x03 | Capabilities | Bit 2-4: Type of fan | + * | | | Bit 5-6: Reserved | + * | | | Bit 7: Data Valid/Invalid | + * | | | (Valid - 1, Invalid - 0) | + * | | | Bit 8-15: Thermistor 0 - 7 presence | + * | | | (1 present, 0 absent) | + * ------------------------------------------------------------------------------ + * + */ +static int qcom_ec_thermal_capabilities(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct qcom_ec *ec = i2c_get_clientdata(client); + struct qcom_ec_thermal_cap *cap = &ec->thermal_cap; + u8 resp[EC_THERMAL_CAP_RESP_LEN]; + int ret; + + ret = qcom_ec_read(ec, EC_THERMAL_CAP_CMD, EC_THERMAL_CAP_RESP_LEN, resp); + if (ret < 0) + return ret; + + cap->fan_cnt = min(EC_MAX_FAN_CNT, EC_THERMAL_FAN_CNT(resp[1])); + cap->fan_type = EC_THERMAL_FAN_TYPE(resp[1]); + cap->thermistor_mask = EC_THERMAL_THERMISTOR_MASK(resp[2]); + + dev_dbg(dev, "Fan count: %d Fan Type: %d Thermistor Mask: %x\n", + cap->fan_cnt, cap->fan_type, cap->thermistor_mask); + + return 0; +} + +static irqreturn_t qcom_ec_irq(int irq, void *data) +{ + struct qcom_ec *ec = data; + struct device *dev = &ec->client->dev; + int val; + + val = i2c_smbus_read_byte_data(ec->client, EC_SCI_EVT_READ_CMD); + if (val < 0) { + dev_err_ratelimited(dev, "Failed to read EC SCI Event: %d\n", val); + return IRQ_HANDLED; + } + + switch (val) { + case EC_FAN1_STATUS_CHANGE_EVT: + dev_dbg_ratelimited(dev, "Fan1 status changed\n"); + break; + case EC_FAN2_STATUS_CHANGE_EVT: + dev_dbg_ratelimited(dev, "Fan2 status changed\n"); + break; + case EC_FAN1_SPEED_CHANGE_EVT: + dev_dbg_ratelimited(dev, "Fan1 speed crossed low/high trip point\n"); + break; + case EC_FAN2_SPEED_CHANGE_EVT: + dev_dbg_ratelimited(dev, "Fan2 speed crossed low/high trip point\n"); + break; + case EC_NEW_LUT_SET_EVT: + dev_dbg_ratelimited(dev, "New LUT set\n"); + break; + case EC_FAN_PROFILE_SWITCH_EVT: + dev_dbg_ratelimited(dev, "FAN Profile switched\n"); + break; + case EC_THERMISTOR_1_THRESHOLD_CROSS_EVT: + dev_dbg_ratelimited(dev, "Thermistor 1 threshold crossed\n"); + break; + case EC_THERMISTOR_2_THRESHOLD_CROSS_EVT: + dev_dbg_ratelimited(dev, "Thermistor 2 threshold crossed\n"); + break; + case EC_THERMISTOR_3_THRESHOLD_CROSS_EVT: + dev_dbg_ratelimited(dev, "Thermistor 3 threshold crossed\n"); + break; + case EC_RECOVERED_FROM_RESET_EVT: + dev_dbg_ratelimited(dev, "EC recovered from reset\n"); + break; + default: + dev_notice_ratelimited(dev, "Unknown EC event: %d\n", val); + break; + } + + return IRQ_HANDLED; +} + +static int qcom_ec_sci_evt_control(struct device *dev, bool enable) +{ + struct i2c_client *client = to_i2c_client(dev); + + return i2c_smbus_write_byte_data(client, EC_SCI_EVT_CONTROL_CMD, !!enable); +} + +static int qcom_ec_fan_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) +{ + *state = EC_FAN_MAX_PWM; + + return 0; +} + +static int qcom_ec_fan_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state) +{ + struct qcom_ec_cooling_dev *ec_cdev = cdev->devdata; + + *state = ec_cdev->state; + + return 0; +} + +/* + * Fan Debug control command: + * + * Command Payload: + * -------------------------------------------------------------------------------------- + * | Offset | Name | Description | + * -------------------------------------------------------------------------------------- + * | 0x00 | Command | Fan control command | + * -------------------------------------------------------------------------------------- + * | 0x01 | Fan ID | 0x1 : Fan 1 | + * | | | 0x2 : Fan 2 | + * -------------------------------------------------------------------------------------- + * | 0x02 | Byte count = 4| Size of data to set fan speed | + * -------------------------------------------------------------------------------------- + * | 0x03 | Mode | Bit 0: Debug Mode On/Off (0 - OFF, 1 - ON ) | + * | | | Bit 1: Fan On/Off (0 - Off, 1 - ON) | + * | | | Bit 2: Debug Type (0 - RPM, 1 - PWM) | + * -------------------------------------------------------------------------------------- + * | 0x04 (LSB) | Speed in RPM | RPM value, if mode selected is RPM | + * | 0x05 | | | + * -------------------------------------------------------------------------------------- + * | 0x06 | Speed in PWM | PWM value, if mode selected is PWM (0 - 255) | + * ______________________________________________________________________________________ + * + */ +static int qcom_ec_fan_debug_mode_off(struct qcom_ec_cooling_dev *ec_cdev) +{ + struct device *dev = ec_cdev->parent_dev; + struct i2c_client *client = to_i2c_client(dev); + u8 request[6] = { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE, + EC_FAN_DEBUG_MODE_OFF, 0, 0, 0 }; + int ret; + + ret = i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD, + sizeof(request), request); + if (ret) { + dev_err(dev, "Failed to turn off fan%d debug mode: %d\n", + ec_cdev->fan_id, ret); + } + + return ret; +} + +static int qcom_ec_fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state) +{ + struct qcom_ec_cooling_dev *ec_cdev = cdev->devdata; + struct device *dev = ec_cdev->parent_dev; + struct i2c_client *client = to_i2c_client(dev); + u8 request[6] = { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE, + EC_FAN_DEBUG_MODE_ON | EC_FAN_ON | EC_FAN_DEBUG_TYPE_PWM, + 0, 0, state }; + int ret; + + ret = i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD, + sizeof(request), request); + if (ret) { + dev_err(dev, "Failed to set fan pwm: %d\n", ret); + return ret; + } + + ec_cdev->state = state; + + return 0; +} + +static const struct thermal_cooling_device_ops qcom_ec_thermal_ops = { + .get_max_state = qcom_ec_fan_get_max_state, + .get_cur_state = qcom_ec_fan_get_cur_state, + .set_cur_state = qcom_ec_fan_set_cur_state, +}; + +static int qcom_ec_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD, + EC_MODERN_STANDBY_EXIT); +} + +static int qcom_ec_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD, + EC_MODERN_STANDBY_ENTER); +} + +static int qcom_ec_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct qcom_ec *ec; + unsigned int i; + int ret; + + ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL); + if (!ec) + return -ENOMEM; + + ec->client = client; + + ret = devm_request_threaded_irq(dev, client->irq, NULL, qcom_ec_irq, + IRQF_ONESHOT, "qcom_ec", ec); + if (ret < 0) + return ret; + + i2c_set_clientdata(client, ec); + + ret = qcom_ec_read_fw_version(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to read EC firmware version\n"); + + ret = qcom_ec_sci_evt_control(dev, true); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to enable SCI events\n"); + + ret = qcom_ec_thermal_capabilities(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to read thermal capabilities\n"); + + if (ec->thermal_cap.fan_cnt == 0) { + dev_warn(dev, FW_BUG "Failed to get fan count, firmware update required\n"); + return 0; + } + + ec->ec_cdev = devm_kcalloc(dev, ec->thermal_cap.fan_cnt, sizeof(*ec->ec_cdev), GFP_KERNEL); + if (!ec->ec_cdev) + return -ENOMEM; + + for (i = 0; i < ec->thermal_cap.fan_cnt; i++) { + struct qcom_ec_cooling_dev *ec_cdev = &ec->ec_cdev[i]; + char name[EC_FAN_NAME_SIZE]; + + scnprintf(name, sizeof(name), "qcom_ec_fan_%u", i); + ec_cdev->fan_id = i + 1; + ec_cdev->parent_dev = dev; + + ec_cdev->cdev = devm_thermal_of_cooling_device_register(dev, NULL, name, ec_cdev, + &qcom_ec_thermal_ops); + if (IS_ERR(ec_cdev->cdev)) { + return dev_err_probe(dev, PTR_ERR(ec_cdev->cdev), + "Failed to register fan%d cooling device\n", i); + } + } + + return 0; +} + +static void qcom_ec_remove(struct i2c_client *client) +{ + struct qcom_ec *ec = i2c_get_clientdata(client); + struct device *dev = &client->dev; + int ret; + + ret = qcom_ec_sci_evt_control(dev, false); + if (ret < 0) + dev_err(dev, "Failed to disable SCI events: %d\n", ret); + + for (int i = 0; i < ec->thermal_cap.fan_cnt; i++) { + struct qcom_ec_cooling_dev *ec_cdev = &ec->ec_cdev[i]; + + qcom_ec_fan_debug_mode_off(ec_cdev); + } +} + +static const struct of_device_id qcom_ec_of_match[] = { + { .compatible = "qcom,hamoa-crd-ec" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_ec_of_match); + +static const struct i2c_device_id qcom_ec_i2c_id_table[] = { + { "qcom-hamoa-ec", }, + {} +}; +MODULE_DEVICE_TABLE(i2c, qcom_ec_i2c_id_table); + +static DEFINE_SIMPLE_DEV_PM_OPS(qcom_ec_pm_ops, + qcom_ec_suspend, + qcom_ec_resume); + +static struct i2c_driver qcom_ec_i2c_driver = { + .driver = { + .name = "qcom-hamoa-ec", + .of_match_table = qcom_ec_of_match, + .pm = &qcom_ec_pm_ops + }, + .probe = qcom_ec_probe, + .remove = qcom_ec_remove, + .id_table = qcom_ec_i2c_id_table, +}; +module_i2c_driver(qcom_ec_i2c_driver); + +MODULE_DESCRIPTION("QCOM Hamoa Embedded Controller"); +MODULE_LICENSE("GPL"); From df2b8f7ca0670f24f083ab94cebc7811022c9530 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Thu, 26 Mar 2026 07:21:01 -0700 Subject: [PATCH 0712/1330] FROMLIST: arm64: dts: qcom: Move board nodes to common DTSI The display, peripherals (touchpad/touchscreen/keypad), usb and their dependent device nodes are common to both Glymur and Mahua CRDs, so move them from glymur-crd.dts to glymur-crd.dtsi to enable code reuse. Link: https://lore.kernel.org/lkml/20260326-glymur-mahua-common-nodes-v1-1-12bb26920ea4@oss.qualcomm.com/ Signed-off-by: Gopikrishna Garmidi Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 91cb2612ab16ce45019117f92b3651cbec5966c3) --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 1226 +--------------------- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 1114 ++++++++++++++++++++ 2 files changed, 1115 insertions(+), 1225 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/glymur-crd.dtsi diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 5290b6bbedb10..0efd9e27c82f6 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -5,1234 +5,10 @@ /dts-v1/; -#include - #include "glymur.dtsi" -#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ -#include "pmh0101.dtsi" /* SPMI0: SID-1 */ -#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ -#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ -#include "pmk8850.dtsi" /* SPMI0: SID-0 */ -#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ +#include "glymur-crd.dtsi" / { model = "Qualcomm Technologies, Inc. Glymur CRD"; compatible = "qcom,glymur-crd", "qcom,glymur"; - - aliases { - serial0 = &uart21; - serial1 = &uart14; - i2c0 = &i2c0; - i2c1 = &i2c4; - i2c2 = &i2c5; - spi0 = &spi18; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - clock-frequency = <38400000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&key_vol_up_default>; - pinctrl-names = "default"; - - key-volume-up { - label = "Volume Up"; - linux,code = ; - gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; - debounce-interval = <15>; - linux,can-disable; - wakeup-source; - }; - }; - - pmic-glink { - compatible = "qcom,glymur-pmic-glink"; - #address-cells = <1>; - #size-cells = <0>; - - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_0_qmpphy_out>; - }; - }; - }; - }; - - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_hs_in1: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss_in1: endpoint { - remote-endpoint = <&usb_1_qmpphy_out>; - }; - }; - }; - }; - - connector@2 { - compatible = "usb-c-connector"; - reg = <2>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_hs_in2: endpoint { - remote-endpoint = <&usb_2_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss_in2: endpoint { - remote-endpoint = <&usb_2_qmpphy_out>; - }; - }; - }; - }; - }; - - vreg_edp_3p3: regulator-edp-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&edp_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_misc_3p3: regulator-misc-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_MISC_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&misc_3p3_reg_en>; - - regulator-boot-on; - regulator-always-on; - }; - - vreg_nvme: regulator-nvme { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_nvmesec: regulator-nvmesec { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_SEC_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_sec_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WLAN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wlan_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_wwan: regulator-wwan { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WWAN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wwan_reg_en>; - pinctrl-names = "default"; - }; - - sound { - compatible = "qcom,glymur-sndcard"; - model = "GLYMUR-CRD"; - audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", - "TweeterLeft IN", "WSA WSA_SPK2 OUT", - "WooferRight IN", "WSA2 WSA_SPK2 OUT", - "TweeterRight IN", "WSA2 WSA_SPK2 OUT", - "VA DMIC0", "vdd-micb", - "VA DMIC1", "vdd-micb", - "VA DMIC2", "vdd-micb", - "VA DMIC3", "vdd-micb"; - - wsa-dai-link { - link-name = "WSA Playback"; - - cpu { - sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&left_woofer>, <&left_tweeter>, - <&swr0 0>, <&lpass_wsamacro 0>, - <&right_woofer>, <&right_tweeter>, - <&swr3 0>, <&lpass_wsa2macro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - va-dai-link { - link-name = "VA Capture"; - - codec { - sound-dai = <&lpass_vamacro 0>; - }; - - cpu { - sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmh0101-rpmh-regulators"; - qcom,pmic-id = "B_E0"; - - vreg_bob1_e0: bob1 { - regulator-name = "vreg_bob1_e0"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <4224000>; - regulator-initial-mode = ; - }; - - vreg_bob2_e0: bob2 { - regulator-name = "vreg_bob2_e0"; - regulator-min-microvolt = <2540000>; - regulator-max-microvolt = <3600000>; - regulator-initial-mode = ; - }; - - vreg_l1b_e0_1p8: ldo1 { - regulator-name = "vreg_l1b_e0_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2b_e0_2p9: ldo2 { - regulator-name = "vreg_l2b_e0_2p9"; - regulator-min-microvolt = <2904000>; - regulator-max-microvolt = <2904000>; - regulator-initial-mode = ; - }; - - vreg_l7b_e0_2p79: ldo7 { - regulator-name = "vreg_l7b_e0_2p79"; - regulator-min-microvolt = <2790000>; - regulator-max-microvolt = <2792000>; - regulator-initial-mode = ; - }; - - vreg_l8b_e0_1p50: ldo8 { - regulator-name = "vreg_l8b_e0_1p50"; - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <1504000>; - regulator-initial-mode = ; - }; - - vreg_l9b_e0_2p7: ldo9 { - regulator-name = "vreg_l9b_e0_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l10b_e0_1p8: ldo10 { - regulator-name = "vreg_l10b_e0_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l11b_e0_1p2: ldo11 { - regulator-name = "vreg_l11b_e0_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l12b_e0_1p14: ldo12 { - regulator-name = "vreg_l12b_e0_1p14"; - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1144000>; - regulator-initial-mode = ; - }; - - vreg_l15b_e0_1p8: ldo15 { - regulator-name = "vreg_l15b_e0_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l17b_e0_2p4: ldo17 { - regulator-name = "vreg_l17b_e0_2p4"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2700000>; - regulator-initial-mode = ; - }; - - vreg_l18b_e0_1p2: ldo18 { - regulator-name = "vreg_l18b_e0_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-1 { - compatible = "qcom,pmcx0102-rpmh-regulators"; - qcom,pmic-id = "C_E1"; - - vreg_l1c_e1_0p82: ldo1 { - regulator-name = "vreg_l1c_e1_0p82"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l2c_e1_1p14: ldo2 { - regulator-name = "vreg_l2c_e1_1p14"; - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1144000>; - regulator-initial-mode = ; - }; - - vreg_l3c_e1_0p89: ldo3 { - regulator-name = "vreg_l3c_e1_0p89"; - regulator-min-microvolt = <890000>; - regulator-max-microvolt = <980000>; - regulator-initial-mode = ; - }; - - vreg_l4c_e1_0p72: ldo4 { - regulator-name = "vreg_l4c_e1_0p72"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <720000>; - regulator-initial-mode = ; - }; - }; - - regulators-2 { - compatible = "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id = "F_E0"; - - vreg_s7f_e0_1p32: smps7 { - regulator-name = "vreg_s7f_e0_1p32"; - regulator-min-microvolt = <1320000>; - regulator-max-microvolt = <1352000>; - regulator-initial-mode = ; - }; - - vreg_s8f_e0_0p95: smps8 { - regulator-name = "vreg_s8f_e0_0p95"; - regulator-min-microvolt = <952000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_s9f_e0_1p9: smps9 { - regulator-name = "vreg_s9f_e0_1p9"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_l2f_e0_0p82: ldo2 { - regulator-name = "vreg_l2f_e0_0p82"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l3f_e0_0p72: ldo3 { - regulator-name = "vreg_l3f_e0_0p72"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <720000>; - regulator-initial-mode = ; - }; - - vreg_l4f_e0_0p3: ldo4 { - regulator-name = "vreg_l4f_e0_0p3"; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-3 { - compatible = "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id = "F_E1"; - - vreg_s7f_e1_0p3: smps7 { - regulator-name = "vreg_s7f_e1_0p3"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l1f_e1_0p82: ldo1 { - regulator-name = "vreg_l1f_e1_0p82"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l2f_e1_0p83: ldo2 { - regulator-name = "vreg_l2f_e1_0p83"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l4f_e1_1p08: ldo4 { - regulator-name = "vreg_l4f_e1_1p08"; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-initial-mode = ; - }; - }; - - regulators-4 { - compatible = "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id = "H_E0"; - - vreg_l1h_e0_0p89: ldo1 { - regulator-name = "vreg_l1h_e0_0p89"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l2h_e0_0p72: ldo2 { - regulator-name = "vreg_l2h_e0_0p72"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l3h_e0_0p32: ldo3 { - regulator-name = "vreg_l3h_e0_0p32"; - regulator-min-microvolt = <320000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_l4h_e0_1p2: ldo4 { - regulator-name = "vreg_l4h_e0_1p2"; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-initial-mode = ; - }; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - status = "okay"; - - touchpad@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; - - hid-descr-addr = <0x20>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; - - pinctrl-0 = <&tpad_default>; - pinctrl-names = "default"; - - wakeup-source; - }; - - keyboard@3a { - compatible = "hid-over-i2c"; - reg = <0x3a>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; - - pinctrl-0 = <&kybd_default>; - pinctrl-names = "default"; - - wakeup-source; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - - status = "okay"; - - ptn3222_0: redriver@43 { - compatible = "nxp,ptn3222"; - reg = <0x43>; - - reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; - - vdd3v3-supply = <&vreg_l8b_e0_1p50>; - vdd1v8-supply = <&vreg_l15b_e0_1p8>; - - #phy-cells = <0>; - }; - - ptn3222_1: redriver@4f { - compatible = "nxp,ptn3222"; - reg = <0x4f>; - - reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; - - vdd3v3-supply = <&vreg_l8b_e0_1p50>; - vdd1v8-supply = <&vreg_l15b_e0_1p8>; - - #phy-cells = <0>; - }; - - ptn3222_2: redriver@47 { - compatible = "nxp,ptn3222"; - reg = <0x47>; - - reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; - - vdd3v3-supply = <&vreg_l8b_e0_1p50>; - vdd1v8-supply = <&vreg_l15b_e0_1p8>; - - #phy-cells = <0>; - }; -}; - -&i2c8 { - clock-frequency = <400000>; - - status = "okay"; - - touchscreen@38 { - compatible = "hid-over-i2c"; - reg = <0x38>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; - - pinctrl-0 = <&ts0_default>; - pinctrl-names = "default"; - }; -}; - -&i2c9 { - clock-frequency = <400000>; - - status = "okay"; - - embedded-controller@76 { - compatible = "qcom,glymur-crd-ec", "qcom,hamoa-crd-ec"; - reg = <0x76>; - - interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-0 = <&ec_int_n_default>; - pinctrl-names = "default"; - }; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dp3 { - /delete-property/ #sound-dai-cells; - - status = "okay"; - - aux-bus { - panel { - compatible = "samsung,atna60cl08", "samsung,atna33xc20"; - enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_3p3>; - - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; -}; - -&mdss_dp3_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l2f_e1_0p83>; - vdda-pll-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&lpass_vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic23_default>; - pinctrl-names = "default"; - qcom,dmic-sample-rate = <4800000>; -}; - -&pcie3b { - vddpe-3v3-supply = <&vreg_nvmesec>; - - pinctrl-0 = <&pcie3b_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie3b_phy { - vdda-phy-supply = <&vreg_l3c_e1_0p89>; - vdda-pll-supply = <&vreg_l2c_e1_1p14>; - vdda-qref-supply = <&vreg_l1f_e1_0p82>; - vdda-qref2-supply = <&vreg_l2f_e1_0p83>; - vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>; - vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&pcie3b_port0 { - reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; -}; - -&pcie4 { - vddpe-3v3-supply = <&vreg_wlan>; - - pinctrl-0 = <&pcie4_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l1c_e1_0p82>; - vdda-pll-supply = <&vreg_l4f_e1_1p08>; - - vdda-qref-supply = <&vreg_l1f_e1_0p82>; - vdda-qref2-supply = <&vreg_l2f_e1_0p83>; - status = "okay"; -}; - -&pcie4_port0 { - reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; -}; - -&pcie5 { - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-0 = <&pcie5_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie5_phy { - vdda-phy-supply = <&vreg_l2f_e0_0p82>; - vdda-pll-supply = <&vreg_l4h_e0_1p2>; - - vdda-qref-supply = <&vreg_l3f_e0_0p72>; - status = "okay"; -}; - -&pcie5_port0 { - reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; -}; - -&pcie6 { - vddpe-3v3-supply = <&vreg_wwan>; - - pinctrl-0 = <&pcie6_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie6_phy { - vdda-phy-supply = <&vreg_l1c_e1_0p82>; - vdda-pll-supply = <&vreg_l4f_e1_1p08>; - - vdda-qref-supply = <&vreg_l1f_e1_0p82>; - vdda-qref2-supply = <&vreg_l2f_e1_0p83>; - status = "okay"; -}; - -&pcie6_port0 { - reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; -}; - -&pmh0101_gpios { - nvme_reg_en: nvme-reg-en-state { - pins = "gpio14"; - function = "normal"; - bias-disable; - }; -}; - -&pmh0110_f_e1_gpios { - nvme_sec_reg_en: nvme-reg-en-state { - pins = "gpio14"; - function = "normal"; - bias-disable; - }; -}; - -&pmh0101_gpios { - key_vol_up_default: key-vol-up-default-state { - pins = "gpio6"; - function = "normal"; - output-disable; - bias-pull-up; - }; -}; - -&pmh0110_f_e0_gpios { - misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio6"; - function = "normal"; - bias-disable; - input-disable; - output-enable; - drive-push-pull; - power-source = <1>; /* 1.8 V */ - qcom,drive-strength = ; - }; -}; - -&pmk8850_rtc { - qcom,no-alarm; -}; - -&pon_resin { - linux,code = ; - status = "okay"; -}; - -&smb2370_j_e2_eusb2_repeater { - vdd18-supply = <&vreg_l15b_e0_1p8>; - vdd3-supply = <&vreg_l7b_e0_2p79>; -}; - -&smb2370_k_e2_eusb2_repeater { - vdd18-supply = <&vreg_l15b_e0_1p8>; - vdd3-supply = <&vreg_l7b_e0_2p79>; -}; - -&smb2370_l_e2_eusb2_repeater { - vdd18-supply = <&vreg_l15b_e0_1p8>; - vdd3-supply = <&vreg_l7b_e0_2p79>; -}; - -&swr0 { - status = "okay"; - - /* WSA8845, Left Woofer */ - left_woofer: speaker@0,0 { - compatible = "sdw20217020400"; - reg = <0 0>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "WooferLeft"; - vdd-1p8-supply = <&vreg_l15b_e0_1p8>; - vdd-io-supply = <&vreg_l18b_e0_1p2>; - qcom,port-mapping = <1 2 3 7 12 14>; - }; - - /* WSA8845, Left Tweeter */ - left_tweeter: speaker@0,1 { - compatible = "sdw20217020400"; - reg = <0 1>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "TweeterLeft"; - vdd-1p8-supply = <&vreg_l15b_e0_1p8>; - vdd-io-supply = <&vreg_l18b_e0_1p2>; - qcom,port-mapping = <4 5 6 7 13 15>; - }; -}; - -&swr3 { - status = "okay"; - - /* WSA8845, Right Woofer */ - right_woofer: speaker@0,0 { - compatible = "sdw20217020400"; - reg = <0 0>; - reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "WooferRight"; - vdd-1p8-supply = <&vreg_l15b_e0_1p8>; - vdd-io-supply = <&vreg_l18b_e0_1p2>; - qcom,port-mapping = <1 2 3 7 12 14>; - }; - - /* WSA8845, Right Tweeter */ - right_tweeter: speaker@0,1 { - compatible = "sdw20217020400"; - reg = <0 1>; - reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "TweeterRight"; - vdd-1p8-supply = <&vreg_l15b_e0_1p8>; - vdd-io-supply = <&vreg_l18b_e0_1p2>; - qcom,port-mapping = <4 5 6 7 13 15>; - }; -}; - -&remoteproc_adsp { - firmware-name = "qcom/glymur/adsp.mbn", - "qcom/glymur/adsp_dtb.mbn"; - - status = "okay"; -}; - -&remoteproc_cdsp { - firmware-name = "qcom/glymur/cdsp.mbn", - "qcom/glymur/cdsp_dtb.mbn"; - - status = "okay"; -}; - -&remoteproc_soccp { - firmware-name = "qcom/glymur/soccp.mbn", - "qcom/glymur/soccp_dtb.mbn"; - - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ - <10 2>, /* OOB UART */ - <44 4>; /* Security SPI (TPM) */ - - ec_int_n_default: ec-int-n-state { - pins = "gpio66"; - function = "gpio"; - bias-disable; - }; - - edp_bl_en: edp-bl-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio147"; - function = "pcie4_clk_req_n"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio146"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio148"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - kybd_default: kybd-default-state { - pins = "gpio67"; - function = "gpio"; - bias-disable; - }; - - tpad_default: tpad-default-state { - pins = "gpio3"; - function = "gpio"; - bias-disable; - }; - - ts0_default: ts0-default-state { - int-n-pins { - pins = "gpio51"; - function = "gpio"; - bias-disable; - }; - - reset-n-pins { - pins = "gpio48"; - function = "gpio"; - output-high; - drive-strength = <16>; - }; - }; - - pcie5_default: pcie5-default-state { - clkreq-n-pins { - pins = "gpio153"; - function = "pcie5_clk_req_n"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio152"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie6_default: pcie6-default-state { - clkreq-n-pins { - pins = "gpio150"; - function = "pcie6_clk_req_n"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio149"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio151"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie3b_default: pcie3b-default-state { - clkreq-n-pins { - pins = "gpio156"; - function = "pcie3b_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio155"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio157"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - wlan_reg_en: wlan-reg-en-state { - pins = "gpio94"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wwan_reg_en: wwan-reg-en-state { - pins = "gpio246"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; - -&usb_0 { - dr_mode = "host"; - - status = "okay"; -}; - -&usb_0_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - -&usb_0_hsphy { - vdd-supply = <&vreg_l3f_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&smb2370_j_e2_eusb2_repeater>; - - status = "okay"; -}; - -&usb_0_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l3f_e0_0p72>; - refgen-supply = <&vreg_l2f_e0_0p82>; - - status = "okay"; -}; - -&usb_0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in>; -}; - -&usb_1 { - dr_mode = "host"; - - status = "okay"; -}; - -&usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in1>; -}; - -&usb_1_hsphy { - vdd-supply = <&vreg_l3f_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&smb2370_k_e2_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l1h_e0_0p89>; - refgen-supply = <&vreg_l2f_e0_0p82>; - - status = "okay"; -}; - -&usb_1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in1>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in2>; -}; - -&usb_2_hsphy { - vdd-supply = <&vreg_l4c_e1_0p72>; - vdda12-supply = <&vreg_l4f_e1_1p08>; - - phys = <&smb2370_l_e2_eusb2_repeater>; - - status = "okay"; -}; - -&usb_2_qmpphy { - vdda-phy-supply = <&vreg_l4f_e1_1p08>; - vdda-pll-supply = <&vreg_l4c_e1_0p72>; - refgen-supply = <&vreg_l1c_e1_0p82>; - - status = "okay"; -}; - -&usb_2_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in2>; -}; - -&usb_hs { - status = "okay"; -}; - -&usb_hs_phy { - vdd-supply = <&vreg_l2h_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&ptn3222_2>; - - status = "okay"; -}; - -&usb_mp { - status = "okay"; -}; - -&usb_mp_hsphy0 { - vdd-supply = <&vreg_l2h_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&ptn3222_0>; - - status = "okay"; -}; - -&usb_mp_hsphy1 { - vdd-supply = <&vreg_l2h_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&ptn3222_1>; - - status = "okay"; -}; - -&usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; - refgen-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; - refgen-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi new file mode 100644 index 0000000000000..05aa189fa7884 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -0,0 +1,1114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ + +#include + +/ { + model = "Qualcomm Technologies, Inc. Glymur CRD"; + compatible = "qcom,glymur-crd", "qcom,glymur"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + i2c0 = &i2c0; + i2c1 = &i2c4; + i2c2 = &i2c5; + spi0 = &spi18; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,glymur-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvmesec: regulator-nvmesec { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_SEC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_sec_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WWAN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_reg_en>; + pinctrl-names = "default"; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_e0_1p8>; + vddaon-supply = <&vreg_l15b_e0_1p8>; + vdddig-supply = <&vreg_l15b_e0_1p8>; + vddrfa1p2-supply = <&vreg_l15b_e0_1p8>; + vddrfa1p8-supply = <&vreg_l15b_e0_1p8>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_bob1_e0: bob1 { + regulator-name = "vreg_bob1_e0"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <4224000>; + regulator-initial-mode = ; + }; + + vreg_bob2_e0: bob2 { + regulator-name = "vreg_bob2_e0"; + regulator-min-microvolt = <2540000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + }; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name = "vreg_l1b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_e0_2p9: ldo2 { + regulator-name = "vreg_l2b_e0_2p9"; + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l7b_e0_2p79: ldo7 { + regulator-name = "vreg_l7b_e0_2p79"; + regulator-min-microvolt = <2790000>; + regulator-max-microvolt = <2792000>; + regulator-initial-mode = ; + }; + + vreg_l8b_e0_1p50: ldo8 { + regulator-name = "vreg_l8b_e0_1p50"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_e0_2p7: ldo9 { + regulator-name = "vreg_l9b_e0_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l10b_e0_1p8: ldo10 { + regulator-name = "vreg_l10b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b_e0_1p2: ldo11 { + regulator-name = "vreg_l11b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l12b_e0_1p14: ldo12 { + regulator-name = "vreg_l12b_e0_1p14"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1144000>; + regulator-initial-mode = ; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name = "vreg_l15b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_e0_2p4: ldo17 { + regulator-name = "vreg_l17b_e0_2p4"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name = "vreg_l18b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c_e1_0p82: ldo1 { + regulator-name = "vreg_l1c_e1_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2c_e1_1p14: ldo2 { + regulator-name = "vreg_l2c_e1_1p14"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1144000>; + regulator-initial-mode = ; + }; + + vreg_l3c_e1_0p89: ldo3 { + regulator-name = "vreg_l3c_e1_0p89"; + regulator-min-microvolt = <890000>; + regulator-max-microvolt = <980000>; + regulator-initial-mode = ; + }; + + vreg_l4c_e1_0p72: ldo4 { + regulator-name = "vreg_l4c_e1_0p72"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <720000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s7f_e0_1p32: smps7 { + regulator-name = "vreg_s7f_e0_1p32"; + regulator-min-microvolt = <1320000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s8f_e0_0p95: smps8 { + regulator-name = "vreg_s8f_e0_0p95"; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s9f_e0_1p9: smps9 { + regulator-name = "vreg_s9f_e0_1p9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e0_0p82: ldo2 { + regulator-name = "vreg_l2f_e0_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l3f_e0_0p72: ldo3 { + regulator-name = "vreg_l3f_e0_0p72"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <720000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e0_0p3: ldo4 { + regulator-name = "vreg_l4f_e0_0p3"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_s7f_e1_0p3: smps7 { + regulator-name = "vreg_s7f_e1_0p3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l1f_e1_0p82: ldo1 { + regulator-name = "vreg_l1f_e1_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e1_0p83: ldo2 { + regulator-name = "vreg_l2f_e1_0p83"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e1_1p08: ldo4 { + regulator-name = "vreg_l4f_e1_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + vreg_l1h_e0_0p89: ldo1 { + regulator-name = "vreg_l1h_e0_0p89"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2h_e0_0p72: ldo2 { + regulator-name = "vreg_l2h_e0_0p72"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l3h_e0_0p32: ldo3 { + regulator-name = "vreg_l3h_e0_0p32"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name = "vreg_l4h_e0_1p2"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + ptn3222_0: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; + + ptn3222_1: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna60cl08", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p83>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie3b { + vddpe-3v3-supply = <&vreg_nvmesec>; + + pinctrl-0 = <&pcie3b_default>; + pinctrl-names = "default"; +}; + +&pcie3b_phy { + vdda-phy-supply = <&vreg_l3c_e1_0p89>; + vdda-pll-supply = <&vreg_l2c_e1_1p14>; +}; + +&pcie3b_port0 { + reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0_0p82>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie6_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie6_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0101_gpios { + key_vol_up_default: key-vol-up-default-state { + pins = "gpio6"; + function = "normal"; + output-disable; + bias-pull-up; + }; +}; + +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>; /* Security SPI (TPM) */ + + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie6_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins = "gpio156"; + function = "pcie3b_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio155"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio157"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_reg_en: wwan-reg-en-state { + pins = "gpio246"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l3f_e0_0p72>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l1h_e0_0p89>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb_hs { + status = "okay"; +}; + +&usb_hs_phy { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_1>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_0>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; From 4ff4eaf89e9659aeef200a57a7bb5f6d3a25056f Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 25 Mar 2026 09:23:37 +0530 Subject: [PATCH 0713/1330] FROMLIST: arm64: dts: glymur: Add LPASS macro codecs and pinctrl Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur. for proper sound support. Also add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Link: https://lore.kernel.org/lkml/20260325035338.1393287-5-sibi.sankar@oss.qualcomm.com/ Co-developed-by: Mohammad Rafi Shaik Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 73dc7e699b6cd773f917b69c1022cfc502f446ac) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 112 +++++++++++++-------------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 5ecde8f62fed9..50c31a8e8c7a6 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4474,42 +4474,9 @@ }; }; - lpass_vamacro: codec@7660000 { - compatible = "qcom,glymur-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; - reg = <0 0x07660000 0 0x1000>; - clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "mclk", - "macro", - "dcodec"; - - #clock-cells = <0>; - clock-output-names = "fsgen"; - #sound-dai-cells = <1>; - }; - - lpass_wsamacro: codec@6c90000 { - compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; - reg = <0 0x06c90000 0 0x1000>; - clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&lpass_vamacro>; - clock-names = "mclk", - "macro", - "dcodec", - "fsgen"; - - #clock-cells = <0>; - clock-output-names = "mclk"; - #sound-dai-cells = <1>; - sound-name-prefix = "WSA"; - }; - swr0: soundwire@6c80000 { compatible = "qcom,soundwire-v3.1.0"; - reg = <0 0x06c80000 0 0x10000>; + reg = <0x0 0x06c80000 0x0 0x10000>; interrupts = ; clocks = <&lpass_wsamacro>; clock-names = "iface"; @@ -4533,10 +4500,10 @@ status = "disabled"; }; - lpass_wsa2macro: codec@6cb0000 { + lpass_wsamacro: codec@6c90000 { compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; - reg = <0 0x06cb0000 0 0x1000>; - clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + reg = <0x0 0x06c90000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&lpass_vamacro>; @@ -4546,14 +4513,14 @@ "fsgen"; #clock-cells = <0>; - clock-output-names = "wsa2-mclk"; + clock-output-names = "mclk"; #sound-dai-cells = <1>; - sound-name-prefix = "WSA2"; + sound-name-prefix = "WSA"; }; swr3: soundwire@6ca0000 { compatible = "qcom,soundwire-v3.1.0"; - reg = <0 0x06ca0000 0 0x10000>; + reg = <0x0 0x06ca0000 0x0 0x10000>; interrupts = ; clocks = <&lpass_wsa2macro>; clock-names = "iface"; @@ -4578,9 +4545,56 @@ status = "disabled"; }; - lpass_tlmm: pinctrl@6e80000 { + lpass_wsa2macro: codec@6cb0000 { + compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06cb0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA2"; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,glymur-lpass-lpiaon-noc"; + reg = <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,glymur-lpass-lpicx-noc"; + reg = <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_vamacro: codec@7660000 { + compatible = "qcom,glymur-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; + reg = <0x0 0x07660000 0x0 0x2000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@7760000 { compatible = "qcom,glymur-lpass-lpi-pinctrl", "qcom,sm8650-lpass-lpi-pinctrl"; - reg = <0 0x07760000 0 0x20000>; + reg = <0x0 0x07760000 0x0 0x20000>; clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; @@ -4695,20 +4709,6 @@ }; }; - lpass_lpiaon_noc: interconnect@7400000 { - compatible = "qcom,glymur-lpass-lpiaon-noc"; - reg = <0x0 0x07400000 0x0 0x19080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - lpass_lpicx_noc: interconnect@7420000 { - compatible = "qcom,glymur-lpass-lpicx-noc"; - reg = <0x0 0x07420000 0x0 0x44080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,glymur-lpass-ag-noc"; reg = <0x0 0x07e40000 0x0 0xe080>; From 732cc67be56b686823638040f213e73eea33814d Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 3 Apr 2026 15:18:36 +0530 Subject: [PATCH 0714/1330] FROMLIST: arm64: dts: qcom: glymur-crd: add Audio sound card node Add the sound card of Glymur-crd board with the routing for speakers. Add device nodes for the sound support with WSA884x smart speakers and playback via speakers and recording via DMIC microphones. Link: https://lore.kernel.org/lkml/20260325035338.1393287-6-sibi.sankar@oss.qualcomm.com/ Co-developed-by: Mohammad Rafi Shaik Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit ce095b59d202390e09722ac03728292103a11c94) --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 124 +++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 05aa189fa7884..729b1b527975d 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -226,6 +226,54 @@ pinctrl-names = "default"; }; + sound { + compatible = "qcom,glymur-sndcard"; + model = "GLYMUR-CRD"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + wcn7850-pmu { compatible = "qcom,wcn7850-pmu"; @@ -530,6 +578,12 @@ }; }; +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + qcom,dmic-sample-rate = <4800000>; +}; + &i2c0 { clock-frequency = <400000>; @@ -825,6 +879,76 @@ vdd3-supply = <&vreg_l7b_e0_2p79>; }; +&swr0 { + status = "okay"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/glymur/adsp.mbn", + "qcom/glymur/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/cdsp.mbn", + "qcom/glymur/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ From d1563ffec125ea88129a588ce173c3448cb26d43 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Sat, 14 Mar 2026 19:56:03 +0530 Subject: [PATCH 0715/1330] PENDING: arm64: dts: qcom: Glymur GPU opp-supported-hw Glymur GPU opp-supported-hw Signed-off-by: Akhil P Oommen Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 3e4563933700d403f1712d6cf695c0e507ea0dc1) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 50c31a8e8c7a6..47de47af2f26d 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4118,12 +4118,14 @@ opp-hz = /bits/ 64 <310000000>; opp-level = ; opp-peak-kBps = <2136718>; + opp-supported-hw = <0xf>; }; opp-410000000 { opp-hz = /bits/ 64 <410000000>; opp-level = ; opp-peak-kBps = <2136718>; + opp-supported-hw = <0xf>; }; opp-572000000 { @@ -4131,6 +4133,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0xe02d5ffd>; + opp-supported-hw = <0xf>; }; opp-760000000 { @@ -4138,6 +4141,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0xc0285ffd>; + opp-supported-hw = <0xf>; }; opp-820000000 { @@ -4145,6 +4149,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0xa82e5ffd>; + opp-supported-hw = <0xf>; }; opp-915000000 { @@ -4152,6 +4157,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0x882d5ffd>; + opp-supported-hw = <0xf>; }; opp-1070000000 { @@ -4159,6 +4165,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0x882b5ffd>; + opp-supported-hw = <0xf>; }; opp-1185000000 { @@ -4166,6 +4173,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0x882a5ffd>; + opp-supported-hw = <0xf>; }; opp-1350000000 { @@ -4173,6 +4181,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0x882a5ffd>; + opp-supported-hw = <0xf>; }; opp-1550000000 { @@ -4180,6 +4189,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0xa8295ffd>; + opp-supported-hw = <0x7>; }; opp-1700000000 { @@ -4187,6 +4197,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0x88295ffd>; + opp-supported-hw = <0x7>; }; opp-1850000000 { @@ -4194,6 +4205,7 @@ opp-level = ; opp-peak-kBps = <2136718>; qcom,opp-acd-level = <0x88285ffd>; + opp-supported-hw = <0x3>; }; }; }; From 66a3403e0ca9b66a6aaf7ac5c597c5280d8a4e26 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 17 Mar 2026 12:37:30 +0530 Subject: [PATCH 0716/1330] PENDING: arm64: dts: qcom: Glymur BW update Glymur BW update Signed-off-by: Akhil P Oommen Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit dac42b675cab86dc1ed3407a89b63f4b90daefc3) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 47de47af2f26d..1f685718577aa 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4117,21 +4117,21 @@ opp-310000000 { opp-hz = /bits/ 64 <310000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <2136719>; opp-supported-hw = <0xf>; }; opp-410000000 { opp-hz = /bits/ 64 <410000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <6074219>; opp-supported-hw = <0xf>; }; opp-572000000 { opp-hz = /bits/ 64 <572000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <12449219>; qcom,opp-acd-level = <0xe02d5ffd>; opp-supported-hw = <0xf>; }; @@ -4139,7 +4139,7 @@ opp-760000000 { opp-hz = /bits/ 64 <760000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <12449219>; qcom,opp-acd-level = <0xc0285ffd>; opp-supported-hw = <0xf>; }; @@ -4147,7 +4147,7 @@ opp-820000000 { opp-hz = /bits/ 64 <820000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <16500000>; qcom,opp-acd-level = <0xa82e5ffd>; opp-supported-hw = <0xf>; }; @@ -4155,7 +4155,7 @@ opp-915000000 { opp-hz = /bits/ 64 <915000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <16500000>; qcom,opp-acd-level = <0x882d5ffd>; opp-supported-hw = <0xf>; }; @@ -4163,7 +4163,7 @@ opp-1070000000 { opp-hz = /bits/ 64 <1070000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <16500000>; qcom,opp-acd-level = <0x882b5ffd>; opp-supported-hw = <0xf>; }; @@ -4171,7 +4171,7 @@ opp-1185000000 { opp-hz = /bits/ 64 <1185000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <16500000>; qcom,opp-acd-level = <0x882a5ffd>; opp-supported-hw = <0xf>; }; @@ -4179,7 +4179,7 @@ opp-1350000000 { opp-hz = /bits/ 64 <1350000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <18597657>; qcom,opp-acd-level = <0x882a5ffd>; opp-supported-hw = <0xf>; }; @@ -4187,7 +4187,7 @@ opp-1550000000 { opp-hz = /bits/ 64 <1550000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <18597657>; qcom,opp-acd-level = <0xa8295ffd>; opp-supported-hw = <0x7>; }; @@ -4195,7 +4195,7 @@ opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <18597657>; qcom,opp-acd-level = <0x88295ffd>; opp-supported-hw = <0x7>; }; @@ -4203,7 +4203,7 @@ opp-1850000000 { opp-hz = /bits/ 64 <1850000000>; opp-level = ; - opp-peak-kBps = <2136718>; + opp-peak-kBps = <18597657>; qcom,opp-acd-level = <0x88285ffd>; opp-supported-hw = <0x3>; }; From 5805b28e77f924f4740bcb181fc20e9d164166ad Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 3 Apr 2026 04:39:05 -0700 Subject: [PATCH 0717/1330] FROMLIST: arm64: dts: qcom: glymur: Add remoteproc PAS loader for SoCCP on Glymur DT Add remoteproc PAS loader for SoCCP on Glymur DT Link: https://lore.kernel.org/all/20260403-glymur-soccp-v3-1-f0e8d57f11ba@oss.qualcomm.com/ Signed-off-by: Sibi Sankar Co-developed-by: Ananthu C V Signed-off-by: Ananthu C V Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 96c12036b34f89a141abe2f4ae3b66d58fe5a790) --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++++ arch/arm64/boot/dts/qcom/glymur.dtsi | 10 ++-------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 729b1b527975d..5b0047b3e0c90 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -949,6 +949,13 @@ status = "okay"; }; +&remoteproc_soccp { + firmware-name = "qcom/glymur/soccp.mbn", + "qcom/glymur/soccp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 1f685718577aa..a9b10447bbf5e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2290,15 +2290,13 @@ <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>, - <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>; + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", - "pong", - "wake-ack"; + "pong"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; @@ -2312,12 +2310,8 @@ <&soccpdtb_mem>; qcom,smem-states = <&soccp_smp2p_out 0>, - <&soccp_smp2p_out 10>, - <&soccp_smp2p_out 9>, <&soccp_smp2p_out 8>; qcom,smem-state-names = "stop", - "wakeup", - "sleep", "ping"; status = "disabled"; From 6614eb94c81c0e90e858565665ab61118e74cf2c Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 6 May 2026 00:20:39 +0530 Subject: [PATCH 0718/1330] FROMLIST: arm64: dts: qcom: glymur: Add iris video node Add iris video codec to glymur SoC, which comes with significantly different powering up sequence than previous platforms, thus different clocks and resets. Link: https://lore.kernel.org/all/20260428-glymur-v3-12-8f28930f47d3@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 1f59b5c12efc2ac43c17ae03ba6ca4f7cd42cc34) --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 ++ arch/arm64/boot/dts/qcom/glymur.dtsi | 118 +++++++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 5b0047b3e0c90..7e3cf49c469b0 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -729,6 +729,13 @@ status = "okay"; }; +&iris { + status = "okay"; + video-firmware { + iommus = <&apps_smmu 0x19e2 0x0>; + }; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index a9b10447bbf5e..06dd3bf7fc6cf 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -5155,6 +5156,123 @@ status = "disabled"; }; + iris: video-codec@aa00000 { + compatible = "qcom,glymur-iris"; + reg = <0x0 0xaa00000 0x0 0xf0000>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI0C_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS1_CLK>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun", + "iface2", + "vcodec1_core", + "vcodec1_core_freerun"; + + dma-coherent; + + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = ; + + iommus = <&apps_smmu 0x1940 0x0>, + <&apps_smmu 0x1943 0x0>, + <&apps_smmu 0x1944 0x0>, + <&apps_smmu 0x19e0 0x0>; + + iommu-map = ; + + memory-region = <&video_mem>; + + operating-points-v2 = <&iris_opp_table>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc VIDEO_CC_MVS1_GDSC>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx", + "vcodec1"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI0C_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core", + "bus2", + "vcodec1_core"; + + /* + * IRIS firmware is signed by vendors, only + * enable on boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 240000000 360000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000 338000000 507000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000 366000000 549000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000 444000000 666000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334 533333334 800000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-655000000 { + opp-hz = /bits/ 64 <655000000 655000000 982000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,glymur-mdss"; reg = <0x0 0x0ae00000 0x0 0x1000>; From 5e4598722fb80ae4c8ed473438795345eb396baf Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Tue, 5 May 2026 19:07:27 +0530 Subject: [PATCH 0719/1330] FROMLIST: arm64: dts: qcom: glymur: Add psci reboot-mode edl Add PSCI SYSTEM_RESET2 reboot-modes for glymur to be invoked by the psci reboot-mode driver. The following modes are defined: - edl: reboot into emergency download mode for image loading via the Firehose protocol. Support for these modes is dependent on the psci firmware Signed-off-by: Pankaj Patil Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit cf3480df6c3d94032b10baffd478d38890e079eb) --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 7e3cf49c469b0..c23c95c862c7b 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -963,6 +963,12 @@ status = "okay"; }; +&psci { + reboot-mode { + mode-edl = <0x80000000 0x1>; + }; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 06dd3bf7fc6cf..8a65637e37ff7 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -400,7 +400,7 @@ interrupts = ; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; From 9d76ce67c2beffeb1820b8afeced7977527ed627 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Wed, 22 Apr 2026 12:32:00 +0530 Subject: [PATCH 0720/1330] WORKAROUND: arm64: dts: qcom: Mahua: Removing Qdss DSP node Removing Qdss Dsp node to fix Mahua bootup Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 9741cafa155e5c9775f79fd622c74466f39541b1) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- arch/arm64/boot/dts/qcom/mahua.dtsi | 300 +++++++++++++++++++++++++++ 2 files changed, 301 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 8a65637e37ff7..f765f36bd84e7 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -6889,7 +6889,7 @@ clock-names = "apb_pclk"; }; - cti@111ab000 { + QDSS_DSP: cti@111ab000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x111ab000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi new file mode 100644 index 0000000000000..582a11b37189a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Mahua is heavily based on Glymur, with some meaningful differences */ +#include "glymur.dtsi" + +/delete-node/ &bwmon_cluster2; +/delete-node/ &cluster2_pd; +/delete-node/ &cpu_map_cluster2; +/delete-node/ &cpu12; +/delete-node/ &cpu13; +/delete-node/ &cpu14; +/delete-node/ &cpu15; +/delete-node/ &cpu16; +/delete-node/ &cpu17; +/delete-node/ &cpu_pd12; +/delete-node/ &cpu_pd13; +/delete-node/ &cpu_pd14; +/delete-node/ &cpu_pd15; +/delete-node/ &cpu_pd16; +/delete-node/ &cpu_pd17; +/delete-node/ &thermal_aoss_6; +/delete-node/ &thermal_aoss_7; +/delete-node/ &thermal_cpu_2_0_0; +/delete-node/ &thermal_cpu_2_0_1; +/delete-node/ &thermal_cpu_2_1_0; +/delete-node/ &thermal_cpu_2_1_1; +/delete-node/ &thermal_cpu_2_2_0; +/delete-node/ &thermal_cpu_2_2_1; +/delete-node/ &thermal_cpu_2_3_0; +/delete-node/ &thermal_cpu_2_3_1; +/delete-node/ &thermal_cpu_2_4_0; +/delete-node/ &thermal_cpu_2_4_1; +/delete-node/ &thermal_cpu_2_5_0; +/delete-node/ &thermal_cpu_2_5_1; +/delete-node/ &thermal_cpuillc_2_1; +/delete-node/ &thermal_cpullc_2_0; +/delete-node/ &thermal_ddr_2; +/delete-node/ &thermal_gpu_3_0; +/delete-node/ &thermal_gpu_3_1; +/delete-node/ &thermal_gpu_3_2; +/delete-node/ &thermal_qmx_2_0; +/delete-node/ &thermal_qmx_2_1; +/delete-node/ &thermal_qmx_2_2; +/delete-node/ &thermal_qmx_2_3; +/delete-node/ &thermal_qmx_2_4; +/delete-node/ &thermal_video_1; +/delete-node/ &tsens6; +/delete-node/ &tsens7; +/delete-node/ &QDSS_DSP; + +&aggre1_noc { + compatible = "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc"; +}; + +&aggre2_noc { + compatible = "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc"; +}; + +&aggre3_noc { + compatible = "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc"; +}; + +&aggre4_noc { + compatible = "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc"; +}; + +&clk_virt { + compatible = "qcom,mahua-clk-virt", "qcom,glymur-clk-virt"; +}; + +&cnoc_main { + compatible = "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main"; +}; + +&config_noc { + compatible = "qcom,mahua-cnoc-cfg"; +}; + +&hsc_noc { + compatible = "qcom,mahua-hscnoc"; +}; + +&lpass_ag_noc { + compatible = "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc"; +}; + +&lpass_lpiaon_noc { + compatible = "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-noc"; +}; + +&lpass_lpicx_noc { + compatible = "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc"; +}; + +&mc_virt { + compatible = "qcom,mahua-mc-virt"; +}; + +&mmss_noc { + compatible = "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc"; +}; + +&nsi_noc { + compatible = "qcom,mahua-nsinoc", "qcom,glymur-nsinoc"; +}; + +&nsp_noc { + compatible = "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc"; +}; + +&oobm_ss_noc { + compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; +}; + +&pcie_east_anoc { + compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; +}; + +&pcie_east_slv_noc { + compatible = "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv-noc"; +}; + +&pcie_west_anoc { + compatible = "qcom,mahua-pcie-west-anoc"; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; +}; + +&pcie_west_slv_noc { + compatible = "qcom,mahua-pcie-west-slv-noc"; +}; + +&system_noc { + compatible = "qcom,mahua-system-noc", "qcom,glymur-system-noc"; +}; + +&thermal_camera_0 { + thermal-sensors = <&tsens4 9>; +}; + +&thermal_camera_1 { + thermal-sensors = <&tsens4 10>; +}; + +&thermal_ddr_1 { + thermal-sensors = <&tsens1 7>; +}; + +&thermal_gpu_0_0 { + thermal-sensors = <&tsens5 1>; +}; + +&thermal_gpu_0_1 { + thermal-sensors = <&tsens5 2>; +}; + +&thermal_gpu_0_2 { + thermal-sensors = <&tsens5 3>; +}; + +&thermal_gpu_1_0 { + thermal-sensors = <&tsens5 4>; +}; + +&thermal_gpu_1_1 { + thermal-sensors = <&tsens5 5>; +}; + +&thermal_gpu_1_2 { + thermal-sensors = <&tsens5 6>; +}; + +&thermal_gpu_2_0 { + thermal-sensors = <&tsens5 7>; +}; + +&thermal_gpu_2_1 { + thermal-sensors = <&tsens5 8>; +}; + +&thermal_gpu_2_2 { + thermal-sensors = <&tsens5 9>; +}; + +&thermal_gpuss_0 { + thermal-sensors = <&tsens5 10>; +}; + +&thermal_gpuss_1 { + thermal-sensors = <&tsens5 11>; +}; + +&thermal_nsphmx_0 { + thermal-sensors = <&tsens4 5>; +}; + +&thermal_nsphmx_1 { + thermal-sensors = <&tsens4 6>; +}; + +&thermal_nsphmx_2 { + thermal-sensors = <&tsens4 7>; +}; + +&thermal_nsphmx_3 { + thermal-sensors = <&tsens4 8>; +}; + +&thermal_nsphvx_0 { + thermal-sensors = <&tsens4 1>; +}; + +&thermal_nsphvx_1 { + thermal-sensors = <&tsens4 2>; +}; + +&thermal_nsphvx_2 { + thermal-sensors = <&tsens4 3>; +}; + +&thermal_nsphvx_3 { + thermal-sensors = <&tsens4 4>; +}; + +&thermal_video_0 { + thermal-sensors = <&tsens1 8>; +}; + +&thermal_zones { + gpuss-2-thermal { + thermal-sensors = <&tsens5 12>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors = <&tsens5 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors = <&tsens5 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; +}; + +&tlmm { + compatible = "qcom,mahua-tlmm"; +}; + +&tsens4 { + #qcom,sensors = <11>; +}; + +&tsens5 { + #qcom,sensors = <15>; +}; + From f2511bd5b7021174e5c0f025a59c691875c1d5a3 Mon Sep 17 00:00:00 2001 From: Anvesh Jain P Date: Thu, 7 May 2026 00:34:27 +0530 Subject: [PATCH 0721/1330] FROMLIST: arm64: defconfig: Enable Qualcomm reference device EC driver Enable EC_QCOM_HAMOA as a module to support the embedded controller found on Qualcomm CRD reference devices such as Hamoa and Glymur. Link: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-6-702f74e495f7@oss.qualcomm.com/ Signed-off-by: Anvesh Jain P Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit e3d4f3e53fe41e3aaf9d0b04f99cf3ee31489023) --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7134d0f8e8540..f43c30fecc318 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1425,6 +1425,7 @@ CONFIG_EC_ACER_ASPIRE1=m CONFIG_EC_HUAWEI_GAOKUN=m CONFIG_EC_LENOVO_YOGA_C630=m CONFIG_EC_LENOVO_THINKPAD_T14S=m +CONFIG_EC_QCOM_HAMOA=m CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y From b6f573289c602eb8a196b83d2496db1e6176118d Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Thu, 7 May 2026 12:18:17 +0530 Subject: [PATCH 0722/1330] PENDING: arm64: dts: qcom: glymur: Removed the glymur-iris.h dt-bindings dependency Removed the glymur-iris.h dt-bindings dependency. Signed-off-by: Vishnu Reddy Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 7e40116852c49b6b6300b0c83712a06fb2d6e91a) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index f765f36bd84e7..6650c47d15449 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include From 4b162f5ba490603ba21a91f874ce07f4d9f486ed Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Mar 2026 10:27:39 +0000 Subject: [PATCH 0723/1330] FROMLIST: arm64: dts: qcom: x1e80100: Add CCI definitions Add in two CCI buses. One bus has two CCI bus master pinouts: cci_i2c_sda0 = gpio101 cci_i2c_scl0 = gpio102 cci_i2c_sda1 = gpio103 cci_i2c_scl1 = gpio104 The second bus has two CCI bus master pinouts: cci_i2c_sda2 = gpio105 cci_i2c_scl2 = gpio106 aon_cci_i2c_sda3 = gpio235 aon_cci_i2c_scl3 = gpio236 Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-2-1d5a9306116a@linaro.org/ Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue (cherry picked from commit 486e11c5046cff3c385363c7eb5beef7eb56526a) --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 298 ---------------------------- 1 file changed, 298 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index d2a54b1215a07..221b6f149a62f 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5907,304 +5907,6 @@ }; }; - camss: isp@acb7000 { - compatible = "qcom,x1e80100-camss"; - - reg = <0 0x0acb7000 0 0x2000>, - <0 0x0acb9000 0 0x2000>, - <0 0x0acbb000 0 0x2000>, - <0 0x0acc6000 0 0x1000>, - <0 0x0acca000 0 0x1000>, - <0 0x0acb6000 0 0x1000>, - <0 0x0ace4000 0 0x1000>, - <0 0x0ace6000 0 0x1000>, - <0 0x0ace8000 0 0x1000>, - <0 0x0acec000 0 0x4000>, - <0 0x0acf6000 0 0x1000>, - <0 0x0acf7000 0 0x1000>, - <0 0x0acf8000 0 0x1000>, - <0 0x0ac62000 0 0x4000>, - <0 0x0ac71000 0 0x4000>, - <0 0x0acc7000 0 0x2000>, - <0 0x0accb000 0 0x2000>; - - reg-names = "csid0", - "csid1", - "csid2", - "csid_lite0", - "csid_lite1", - "csid_wrapper", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", - "csitpg0", - "csitpg1", - "csitpg2", - "vfe0", - "vfe1", - "vfe_lite0", - "vfe_lite1"; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CORE_AHB_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, - <&camcc CAM_CC_CPAS_IFE_0_CLK>, - <&camcc CAM_CC_CPAS_IFE_1_CLK>, - <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, - <&camcc CAM_CC_CPHY_RX_CLK_SRC>, - <&camcc CAM_CC_CSID_CLK>, - <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, - <&camcc CAM_CC_CSIPHY0_CLK>, - <&camcc CAM_CC_CSI0PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY1_CLK>, - <&camcc CAM_CC_CSI1PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY2_CLK>, - <&camcc CAM_CC_CSI2PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY4_CLK>, - <&camcc CAM_CC_CSI4PHYTIMER_CLK>, - <&gcc GCC_CAMERA_HF_AXI_CLK>, - <&gcc GCC_CAMERA_SF_AXI_CLK>, - <&camcc CAM_CC_IFE_0_CLK>, - <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, - <&camcc CAM_CC_IFE_1_CLK>, - <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, - <&camcc CAM_CC_IFE_LITE_CLK>, - <&camcc CAM_CC_IFE_LITE_AHB_CLK>, - <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, - <&camcc CAM_CC_IFE_LITE_CSID_CLK>; - - clock-names = "camnoc_nrt_axi", - "camnoc_rt_axi", - "core_ahb", - "cpas_ahb", - "cpas_fast_ahb", - "cpas_vfe0", - "cpas_vfe1", - "cpas_vfe_lite", - "cphy_rx_clk_src", - "csid", - "csid_csiphy_rx", - "csiphy0", - "csiphy0_timer", - "csiphy1", - "csiphy1_timer", - "csiphy2", - "csiphy2_timer", - "csiphy4", - "csiphy4_timer", - "gcc_axi_hf", - "gcc_axi_sf", - "vfe0", - "vfe0_fast_ahb", - "vfe1", - "vfe1_fast_ahb", - "vfe_lite", - "vfe_lite_ahb", - "vfe_lite_cphy_rx", - "vfe_lite_csid"; - - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - - interrupt-names = "csid0", - "csid1", - "csid2", - "csid_lite0", - "csid_lite1", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", - "vfe0", - "vfe1", - "vfe_lite0", - "vfe_lite1"; - - interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, - <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "ahb", - "hf_mnoc", - "sf_mnoc", - "sf_icp_mnoc"; - - iommus = <&apps_smmu 0x800 0x60>, - <&apps_smmu 0x860 0x60>, - <&apps_smmu 0x1860 0x60>, - <&apps_smmu 0x18e0 0x00>, - <&apps_smmu 0x19a0 0x20>; - - phys = <&csiphy0 PHY_TYPE_DPHY>, <&csiphy1 PHY_TYPE_DPHY>, - <&csiphy2 PHY_TYPE_DPHY>, <&csiphy4 PHY_TYPE_DPHY>; - phy-names = "csiphy0", "csiphy1", - "csiphy2", "csiphy4"; - - power-domains = <&camcc CAM_CC_IFE_0_GDSC>, - <&camcc CAM_CC_IFE_1_GDSC>, - <&camcc CAM_CC_TITAN_TOP_GDSC>; - power-domain-names = "ife0", - "ife1", - "top"; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - camss_csiphy0_inep0: endpoint@0 { - reg = <0>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - camss_csiphy1_inep0: endpoint@0 { - reg = <0>; - }; - }; - - port@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - camss_csiphy2_inep0: endpoint@0 { - reg = <0>; - }; - }; - - port@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - camss_csiphy4_inep0: endpoint@0 { - reg = <0>; - }; - }; - }; - }; - - csiphy0: csiphy@ace4000 { - compatible = "qcom,x1e80100-csi2-phy"; - reg = <0 0x0ace4000 0 0x2000>; - - clocks = <&camcc CAM_CC_CSIPHY0_CLK>, - <&camcc CAM_CC_CSI0PHYTIMER_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>; - clock-names = "csiphy", - "csiphy_timer", - "camnoc_axi", - "cpas_ahb"; - - operating-points-v2 = <&csiphy_opp_table>; - - interrupts = ; - - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - - #phy-cells = <1>; - - status = "disabled"; - }; - - csiphy1: csiphy@ace6000 { - compatible = "qcom,x1e80100-csi2-phy"; - reg = <0 0x0ace6000 0 0x2000>; - - clocks = <&camcc CAM_CC_CSIPHY1_CLK>, - <&camcc CAM_CC_CSI1PHYTIMER_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>; - clock-names = "csiphy", - "csiphy_timer", - "camnoc_axi", - "cpas_ahb"; - - operating-points-v2 = <&csiphy_opp_table>; - - interrupts = ; - - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - - #phy-cells = <1>; - - status = "disabled"; - }; - - csiphy2: csiphy@ace8000 { - compatible = "qcom,x1e80100-csi2-phy"; - reg = <0 0x0ace8000 0 0x2000>; - - clocks = <&camcc CAM_CC_CSIPHY2_CLK>, - <&camcc CAM_CC_CSI2PHYTIMER_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>; - clock-names = "csiphy", - "csiphy_timer", - "camnoc_axi", - "cpas_ahb"; - - operating-points-v2 = <&csiphy_opp_table>; - - interrupts = ; - - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - - #phy-cells = <1>; - - status = "disabled"; - }; - - csiphy4: csiphy@acec000 { - compatible = "qcom,x1e80100-csi2-phy"; - reg = <0 0x0acec000 0 0x2000>; - - clocks = <&camcc CAM_CC_CSIPHY4_CLK>, - <&camcc CAM_CC_CSI4PHYTIMER_CLK>, - <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>; - clock-names = "csiphy", - "csiphy_timer", - "camnoc_axi", - "cpas_ahb"; - - operating-points-v2 = <&csiphy_opp_table>; - - interrupts = ; - - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - - #phy-cells = <1>; - - status = "disabled"; - }; - camcc: clock-controller@ade0000 { compatible = "qcom,x1e80100-camcc"; reg = <0 0x0ade0000 0 0x20000>; From 4bcd552936cd083abfa337ef618357d69848f389 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Mar 2026 10:27:43 +0000 Subject: [PATCH 0724/1330] FROMLIST: arm64: dts: qcom: x1e80100-t14s: Add pm8010 camera PMIC with voltage levels for IR and RGB camera Add the PM8010 PMIC providing the following voltage rails: vreg_l1m_r @ 1v2 IR sensor vreg_l2m_r @ 1v2 RGB sensor vreg_l3m_r @ 1v8 IR sensor vreg_l4m_r @ 1v8 RGB sensor vreg_l5m_r @ 2v8 IR sensor vreg_l7m_r @ 2v8 RGB sensor Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-6-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue (cherry picked from commit 1ab7e87f03665e82207a5ee3a8d6d83c67226131) --- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 63 ------------------- 1 file changed, 63 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index c7942479f121f..16c13f9027173 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -988,69 +988,6 @@ }; -&camss { - status = "okay"; - - ports { - /* - * port0 => csiphy0 - * port1 => csiphy1 - * port2 => csiphy2 - * port3 => csiphy4 - */ - port@3 { - camss_csiphy4_inep0: endpoint@0 { - clock-lanes = <7>; - data-lanes = <0 1>; - remote-endpoint = <&ov02c10_ep>; - }; - }; - }; -}; - -&cci1 { - status = "okay"; -}; - -&cci1_i2c1 { - camera@36 { - compatible = "ovti,ov02c10"; - reg = <0x36>; - - reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cam_rgb_default>; - - leds = <&privacy_led>; - led-names = "privacy"; - - clocks = <&camcc CAM_CC_MCLK4_CLK>; - assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; - assigned-clock-rates = <19200000>; - - orientation = <0>; /* front facing */ - - avdd-supply = <&vreg_l7m_2p8>; - dvdd-supply = <&vreg_l2m_1p2>; - dovdd-supply = <&vreg_l4m_1p8>; - - port { - ov02c10_ep: endpoint { - data-lanes = <1 2>; - link-frequencies = /bits/ 64 <400000000>; - remote-endpoint = <&camss_csiphy4_inep0>; - }; - }; - }; -}; - -&csiphy4 { - vdda-0p8-supply = <&vreg_l2c_0p8>; - vdda-1p2-supply = <&vreg_l1c_1p2>; - - status = "okay"; -}; - &gpu { status = "okay"; }; From 56a2a727bc8d1f35f17b880311707d8e19376bfd Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Mar 2026 10:27:44 +0000 Subject: [PATCH 0725/1330] FROMLIST: arm64: dts: qcom: x1e80100-t14s: Add on ov02c10 RGB sensor on CSIPHY4 Switch on the ov02c10 RGB sensor on CSIPHY4. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-7-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue (cherry picked from commit e6517543ce1782053bb63fb5cd0f91799912de76) --- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 61 ++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 16c13f9027173..c6f259b8068f2 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -988,6 +987,66 @@ }; +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + camss_csiphy4_inep0: endpoint@0 { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02c10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7m_2p8>; + dvdd-supply = <&vreg_l2m_1p2>; + dovdd-supply = <&vreg_l4m_1p8>; + + port { + ov02c10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&camss_csiphy4_inep0>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p9-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; +}; + &gpu { status = "okay"; }; From b38d66fa48ab148712b309b80e6c8e0c64602d18 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Mar 2026 10:27:47 +0000 Subject: [PATCH 0726/1330] FROMLIST: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add ov02c10 RGB sensor on CSIPHY4 Add in the RGB sensor on CSIPHY4. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-10-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue (cherry picked from commit e852e9363d0da3cffa8b7424123c56decc8c164c) --- .../boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 5f46e573c7c42..5a1ab0da86696 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -7,7 +7,6 @@ #include #include -#include #include #include @@ -913,9 +912,6 @@ pinctrl-names = "default"; pinctrl-0 = <&cam_rgb_default>; - leds = <&privacy_led>; - led-names = "privacy"; - clocks = <&camcc CAM_CC_MCLK4_CLK>; assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; assigned-clock-rates = <19200000>; @@ -937,7 +933,7 @@ }; &csiphy4 { - vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-0p9-supply = <&vreg_l2c_0p8>; vdda-1p2-supply = <&vreg_l1c_1p2>; status = "okay"; @@ -1506,13 +1502,6 @@ }; }; - cam_indicator_en: cam-indicator-en-state { - pins = "gpio110"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From 6b86aa6f448e09cc3511f9e05d5e79e424ac2f02 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 26 Mar 2026 10:27:48 +0000 Subject: [PATCH 0727/1330] FROMLIST: arm64: dts: qcom: x1e80100-dell-inspiron14-7441: Switch on CAMSS RGB sensor Inspiron14 has a ov02e10 sensor on CSIPHY4. Enable the list of dependencies now. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-11-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue (cherry picked from commit 644db5bdf9f97f17fef1fb37ff45477305392792) --- arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index 62cfe52ce614e..ebe53046750ca 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -847,7 +847,7 @@ }; &csiphy4 { - vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-0p9-supply = <&vreg_l2c_0p8>; vdda-1p2-supply = <&vreg_l1c_1p2>; status = "okay"; From 6b909901187c047f1237105b58006fb65efea380 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Fri, 10 Apr 2026 02:38:51 +0530 Subject: [PATCH 0728/1330] FROMLIST: arm64: dts: qcom: purwa: Fix GPU IOMMU property Purwa's GPU does not support SID 1, which is typically used for LPAC-related traffic. Remove SID 1 from the GPU node's iommus property to accurately describe the hardware. This fixes the splat below, seen with some versions of Gunyah hypervisor: Internal error: synchronous external abort: 0000000096000010 [#1] SMP CPU: 0 UID: 0 PID: 80 Comm: kworker/u33:2 Tainted: G M Tainted: [M]=MACHINE_CHECK Hardware name: Qualcomm Technologies, Inc. Purwa IoT EVK (DT) Workqueue: events_unbound deferred_probe_work_func pstate: 21400005 (nzCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--) pc : arm_smmu_write_s2cr+0x9c/0xbc lr : arm_smmu_master_install_s2crs+0x78/0xa4 sp : ffff80008039b570 x29: ffff80008039b570 x28: 0000000000000000 x27: ffffaddd62f1ab78 x26: ffff00080a4ff280 x25: 0000000000000018 x24: ffff00080b896480 x23: ffff00080ba9b7a0 x22: ffff00080bb05160 x21: 0000000000000000 x20: 0000000000000000 x19: 0000000000000001 x18: 00000000ffffffff x17: 0000000000000000 x16: 0000000000000000 x15: ffff80008039b1d0 x14: ffff80010039b37d x13: 00746c7561662d74 x12: 0000000000000000 x11: ffff00080b7fbd98 x10: ffffffffffffffc0 x9 : ffffffffffffffff x8 : 0000000000000228 x7 : 0000000000000e87 x6 : 0000000000000000 x5 : 0000000000000000 x4 : ffff00080a4ff280 x3 : 0000000000000000 x2 : ffff800082a40c04 x1 : 0000000000000000 x0 : ffff800082a40000 Call trace: arm_smmu_write_s2cr+0x9c/0xbc (P) arm_smmu_master_install_s2crs+0x78/0xa4 arm_smmu_attach_dev+0xb0/0x1d8 __iommu_device_set_domain+0x84/0x11c __iommu_group_set_domain_internal+0x60/0x120 __iommu_attach_group+0x88/0x9c iommu_attach_device+0x6c/0xa0 msm_iommu_new.part.0+0x84/0xe4 [msm] msm_iommu_gpu_new+0x3c/0x104 [msm] adreno_iommu_create_vm+0x24/0xc8 [msm] a6xx_create_vm+0x48/0x78 [msm] msm_gpu_init+0x2d8/0x508 [msm] adreno_gpu_init+0x208/0x324 [msm] a6xx_gpu_init+0x604/0x8cc [msm] adreno_bind+0xb4/0x124 [msm] component_bind_all+0x114/0x23c msm_drm_init+0x1b0/0x1ec [msm] msm_drm_bind+0x30/0x3c [msm] try_to_bring_up_aggregate_device+0x164/0x1d0 __component_add+0xa4/0x16c component_add+0x14/0x20 msm_dp_display_probe_tail+0x4c/0xac [msm] msm_dp_auxbus_done_probe+0x14/0x20 [msm] dp_aux_ep_probe+0x4c/0xf4 [drm_dp_aux_bus] really_probe+0xbc/0x29c __driver_probe_device+0x78/0x12c driver_probe_device+0x3c/0x15c __device_attach_driver+0xb8/0x134 bus_for_each_drv+0x88/0xe8 __device_attach+0xa0/0x190 device_initial_probe+0x50/0x54 bus_probe_device+0x38/0xa4 deferred_probe_work_func+0x88/0xc0 process_one_work+0x148/0x28c worker_thread+0x2cc/0x3d4 kthread+0x12c/0x204 ret_from_fork+0x10/0x20 ---[ end trace 0000000000000000 ]--- Fixes: 1aa0b4e36436 ("arm64: dts: qcom: x1p42100: Add GPU support") Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/20260410-purwa-gpu-dt-fix-v1-1-4637892156cf@oss.qualcomm.com (cherry picked from commit 8fc2339db1c4c4c1cc2fdcd1e78c7d94106b5850) --- arch/arm64/boot/dts/qcom/purwa.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 743eb12569f41..05e736a0f0935 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -55,6 +55,8 @@ &gpu { compatible = "qcom,adreno-43030c00", "qcom,adreno"; + iommus = <&adreno_smmu 0 0x0>; + nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; From 1c421ad8b19294379989c0da62d2ec911bef60e4 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 10 Apr 2026 12:25:33 +0800 Subject: [PATCH 0729/1330] FROMLIST: arm64: dts: qcom: purwa: Add camss node Add node for the X1P42100 camera subsystem. Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-3-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu (cherry picked from commit 10ec6e9d4ffa830675a3fa67b6d7949a1ed28fc9) --- arch/arm64/boot/dts/qcom/purwa.dtsi | 158 ++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 05e736a0f0935..7efefccf5547f 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -19,6 +19,8 @@ /delete-node/ &cpu_pd9; /delete-node/ &cpu_pd10; /delete-node/ &cpu_pd11; +/delete-node/ &csiphy1; +/delete-node/ &csiphy2; /delete-node/ &gpu_opp_table; /delete-node/ &gpu_speed_bin; /delete-node/ &pcie3_phy; @@ -36,6 +38,162 @@ /delete-node/ &cluster2_rep_2_3; /delete-node/ &apss_funnel_in2; +&camss { + compatible = "qcom,x1p42100-camss"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe_lite0", + "vfe_lite1"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy4", + "vfe0", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x19a0 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "top"; + + phys = <&csiphy0 PHY_TYPE_DPHY>, + <&csiphy4 PHY_TYPE_DPHY>; + phy-names = "csiphy0", + "csiphy4"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy0_inep0: endpoint@0 { + reg = <0>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy4_inep0: endpoint@0 { + reg = <0>; + }; + }; + }; +}; + &camcc { compatible = "qcom,x1p42100-camcc"; }; From 96395cc8f6f7f8cf7dc49743e61ea2876b73186c Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 10 Apr 2026 12:25:34 +0800 Subject: [PATCH 0730/1330] FROMLIST: arm64: dts: qcom: purwa-iot-evk: Add camss node enable camss node for purwa iot evk board camss tpg support. Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-4-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu (cherry picked from commit 64c4c26c934e2c3b9e7b278bd71aef08d3667fac) --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index ad503beec1d3d..eef03f1eb2a95 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -734,6 +734,10 @@ }; }; +&camss { + status = "okay"; +}; + &i2c3 { clock-frequency = <400000>; From cd81c54d01a1cc9b02d6f35687d46ccbec757971 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 27 Apr 2026 15:34:55 +0530 Subject: [PATCH 0731/1330] FROMLIST: arm64: dts: qcom: x1-crd: Add Embedded controller node Add embedded controller node for Hamoa/Purwa CRDs which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-4-702f74e495f7@oss.qualcomm.com/ Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P (cherry picked from commit 0e685bd843c1f024fe6970d2ff5b8ce7ca0a811d) --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index c3748124cd7ec..84b1860bc66a6 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1234,6 +1234,16 @@ #phy-cells = <0>; }; + + embedded-controller@76 { + compatible = "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; }; &i2c7 { @@ -1716,6 +1726,12 @@ }; }; + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From a74c7fb35b1e55da532d8e3e79df638abbea5577 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 27 Apr 2026 15:34:56 +0530 Subject: [PATCH 0732/1330] FROMLIST: arm64: dts: qcom: hamoa-iot-evk: Add Embedded controller node Add embedded controller node for Hamoa IOT EVK boards which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-5-702f74e495f7@oss.qualcomm.com/ Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Gaurav Kohli Tested-by: Gaurav Kohli Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P (cherry picked from commit 043244b06c8592ba2159538838acafdf964aa6fc) --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index e24858d5fadcc..53915dd10a02d 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -847,6 +847,16 @@ pinctrl-0 = <&eusb6_reset_n>; pinctrl-names = "default"; }; + + embedded-controller@76 { + compatible = "qcom,hamoa-iot-evk-ec", "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; }; &i2c7 { @@ -1356,6 +1366,12 @@ }; }; + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From 0582c783447628438dfc385cece30d5020d2078b Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Wed, 29 Apr 2026 15:43:55 +0800 Subject: [PATCH 0733/1330] FROMLIST: arm64: dts: qcom: purwa: Override Iris clocks and operating points The Iris block on X1P differs from SM8550/X1E in its clock configuration and requires a dedicated OPP table. The node inherited from the X1E cannot be reused directly, and the fallback compatible "qcom,sm8550-iris" cannot be applied. Override the inherited clocks, clock-names, and operating points, and replaces them with the X1P42100-specific definitions. A new OPP table is provided to support the correct performance levels on this platform. Link: https://lore.kernel.org/linux-arm-msm/20260429-enable_iris_on_purwa-v5-4-438fa96da248@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Reviewed-by: Dmitry Baryshkov Signed-off-by: Wangao Wang (cherry picked from commit 94e21a67ced5fa2f15c7b128b598f8a3e841a117) --- arch/arm64/boot/dts/qcom/purwa.dtsi | 50 +++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 7efefccf5547f..10d2207ce81e9 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -23,6 +23,7 @@ /delete-node/ &csiphy2; /delete-node/ &gpu_opp_table; /delete-node/ &gpu_speed_bin; +/delete-node/ &iris_opp_table; /delete-node/ &pcie3_phy; /delete-node/ &thermal_zones; /delete-node/ &etm8; @@ -325,6 +326,55 @@ compatible = "qcom,x1p42100-gpucc"; }; +&iris { + compatible = "qcom,x1p42100-iris"; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&videocc VIDEO_CC_MVS0_BSE_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "vcodec0_bse"; + + operating-points-v2 = <&iris_opp_table_x1p42100>; + + iris_opp_table_x1p42100: opp-table { + compatible = "operating-points-v2"; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000 105000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000 150000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_svs>; + }; + + opp-335000000 { + opp-hz = /bits/ 64 <335000000 167500000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-424000000 { + opp-hz = /bits/ 64 <424000000 212000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_nom>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000 250000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_turbo>; + }; + }; +}; + /* PCIe3 has half the lanes compared to X1E80100 */ &pcie3 { num-lanes = <4>; From 6e5770e4494921a4f7afc0322d9341ed660540aa Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Wed, 29 Apr 2026 15:43:56 +0800 Subject: [PATCH 0734/1330] FROMLIST: arm64: dts: qcom: purwa-iot-som: enable video Enable video nodes on the purwa-iot-som board. Link: https://lore.kernel.org/linux-arm-msm/20260429-enable_iris_on_purwa-v5-5-438fa96da248@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dikshita Agarwal Signed-off-by: Wangao Wang (cherry picked from commit af8dabacea61b5e9f7f7fadf821237072050849b) --- arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index 9ce86d3ff8cb5..cc30ad746df83 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -389,6 +389,10 @@ firmware-name = "qcom/x1p42100/gen71500_zap.mbn"; }; +&iris { + status = "okay"; +}; + &pcie3 { pinctrl-0 = <&pcie3_default>; pinctrl-names = "default"; From e870b3acc6d6a385a44398ff4499dd195cb2d624 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 7 Apr 2026 11:07:38 +0530 Subject: [PATCH 0735/1330] PENDING: arm64: dts: qcom: hamoa: switch iris iommus to iommu-map Switch the iris video codec node in hamoa from the legacy 'iommus' property to 'iommu-map', using IRIS_NON_PIXEL_VCODEC and IRIS_PIXEL function IDs to identify the non-pixel and pixel context bank SMMU stream mappings respectively. Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Signed-off-by: Gourav Kumar (cherry picked from commit 44a326540dfe51751783d132692d4cfedbe651b3) --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 221b6f149a62f..cf47fa4e7187a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -5763,8 +5764,8 @@ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names = "bus"; - iommus = <&apps_smmu 0x1940 0>, - <&apps_smmu 0x1947 0>; + iommu-map = , + ; dma-coherent; /* From 27469d9cb23ca96deb73a77140cb7f2ebd47b556 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Thu, 7 May 2026 12:43:58 +0530 Subject: [PATCH 0736/1330] PENDING: arm64: dts: qcom: glymur: removing iommu-map for iris video Removing iommu-map for iris video Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 6eb92b4fbbba1c7a64ca077670027f9b78b01dd5) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 6650c47d15449..5058be567c1f4 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5194,7 +5194,6 @@ <&apps_smmu 0x1944 0x0>, <&apps_smmu 0x19e0 0x0>; - iommu-map = ; memory-region = <&video_mem>; From 87b27ec51b3d4198c5c430a7f8d7d10048b6c664 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 15 Apr 2026 10:52:56 +0300 Subject: [PATCH 0737/1330] FROMLIST: arm64: dts: qcom: glymur: Mark USB SS1 and SS2 as role-switch capable Like USB SS0, the USB SS1 and SS2 controllers on Glymur also support USB role switching. Describe this by adding the 'usb-role-switch' property to both controllers. Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes") Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-1-409e1a257f1f@oss.qualcomm.com (cherry picked from commit 309a87e487a0e45c332781cf40c0c19524c9db7d) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 5058be567c1f4..d6584231dd497 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4920,6 +4920,8 @@ snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + usb-role-switch; + status = "disabled"; ports { @@ -4993,6 +4995,8 @@ snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + usb-role-switch; + status = "disabled"; ports { From cf38740966c43756e597b31d9bc2f04c69069416 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 7 May 2026 13:55:24 +0530 Subject: [PATCH 0738/1330] FROMLIST: arm64: dts: qcom: glymur-crd: Drop forced host mode for USB SS0 and SS1 The two USB Type-C ports on Glymur CRD are dual-role capable. Do not force their controllers into host mode. Drop the explicit 'dr_mode = "host"' properties so they can use their default OTG mode instead. Fixes: c8b63029455b ("arm64: dts: qcom: glymur-crd: Enable USB support") Signed-off-by: Abel Vesa (cherry picked from commit 2eecae5060c28770da64b96cc676941fbe7dc71e) --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index c23c95c862c7b..d35530ed09df5 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -1147,8 +1147,6 @@ }; &usb_0 { - dr_mode = "host"; - status = "okay"; }; @@ -1178,8 +1176,6 @@ }; &usb_1 { - dr_mode = "host"; - status = "okay"; }; From db5634d4eaded7d0dcf3c5986d2ee1328e293eec Mon Sep 17 00:00:00 2001 From: Kripalsinh Rana Date: Tue, 5 May 2026 16:24:45 +0530 Subject: [PATCH 0739/1330] QCLINUX: arm64: dts: qcom: Add kodiak lite camx overlay dts Add CAMX overlay dts file for kodiak lite boards. This change also enables the compilation of the CAMX overlay for kodiak lite boards. Signed-off-by: Kripalsinh Rana (cherry picked from commit 925a93ca00cdac30feb4f81d331b88ed5f94eded) --- arch/arm64/boot/dts/qcom/Makefile | 4 +++ .../arm64/boot/dts/qcom/qcs5430-fps-camx.dtso | 32 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs5430-fps-camx.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index da46dd5d124d7..e5296f0e36887 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -516,6 +516,10 @@ qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtbo +qcs5430-fps-camx-dtbs := qcs6490-rb3gen2.dtb qcs5430-fps-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs5430-fps-camx.dtb + qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.dtb \ qcs6490-rb3gen2-vision-mezzanine-camx.dtbo diff --git a/arch/arm64/boot/dts/qcom/qcs5430-fps-camx.dtso b/arch/arm64/boot/dts/qcom/qcs5430-fps-camx.dtso new file mode 100644 index 0000000000000..4255147f00ef9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs5430-fps-camx.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* +* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +*/ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "qcs6490-camera.dtsi" +#include "qcs6490-rb3gen2-camera-sensor.dtsi" + +&cam_csid2 { + status = "disabled"; +}; + +&cam_vfe2 { + status = "disabled"; +}; + +&camss { + status = "disabled"; +}; + +&cci1 { + status = "disabled"; +}; From 9a8d015cfe349fc4bc72b87dae328f0360910a75 Mon Sep 17 00:00:00 2001 From: Kripalsinh Rana Date: Tue, 5 May 2026 16:24:45 +0530 Subject: [PATCH 0740/1330] QCLINUX: arm64: dts: qcom: Add kodiak lite camx overlay dts Add CAMX overlay dts file for kodiak lite boards. This change also enables the compilation of the CAMX overlay for kodiak lite boards. Signed-off-by: Kripalsinh Rana (cherry picked from commit 2844d19748043c1ba35aaee14e7a2d12ab9d0f02) --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e5296f0e36887..9f346c111b778 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -511,6 +511,10 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo +qcs5430-fps-camx-dtbs := qcs6490-rb3gen2.dtb qcs5430-fps-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs5430-fps-camx.dtb + qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb From 6bbb6054d05ce8592abb6df6e8fbd6bc11a99486 Mon Sep 17 00:00:00 2001 From: Kripalsinh Rana Date: Tue, 5 May 2026 16:24:45 +0530 Subject: [PATCH 0741/1330] QCLINUX: arm64: dts: qcom: Add kodiak lite camx overlay dts Add CAMX overlay dts file for kodiak lite boards. This change also enables the compilation of the CAMX overlay for kodiak lite boards. Signed-off-by: Kripalsinh Rana (cherry picked from commit 675a11e3485adb2ef91e71b575a662ff320d4165) --- arch/arm64/boot/dts/qcom/Makefile | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 9f346c111b778..509236dcc6f65 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -520,10 +520,6 @@ qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtbo -qcs5430-fps-camx-dtbs := qcs6490-rb3gen2.dtb qcs5430-fps-camx.dtbo - -dtb-$(CONFIG_ARCH_QCOM) += qcs5430-fps-camx.dtb - qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.dtb \ qcs6490-rb3gen2-vision-mezzanine-camx.dtbo From a5881dd473b885f08f8a31d4e6a17e605df155ac Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 28 Apr 2026 09:24:07 +0530 Subject: [PATCH 0742/1330] FROMLIST: media: iris: Fix VM count passed to firmware On Glymur, firmware interprets the value written to CPU_CS_SCIACMDARG3 as the number of virtual machines (VMs) and internally adds 1 to it. Writing 1 causes firmware to treat it as 2 VMs. Since only one VM is required, remove this write to leave the register at its reset value of 0. This does not affect other platforms as only Glymur firmware uses this register, earlier platform firmwares ignore it. Link: https://lore.kernel.org/all/20260428-glymur-v3-1-8f28930f47d3@oss.qualcomm.com/ Fixes: abf5bac63f68a ("media: iris: implement the boot sequence of the firmware") Cc: stable@vger.kernel.org Reviewed-by: Vikash Garodia Signed-off-by: Vishnu Reddy (cherry picked from commit 40c3a5923549c7bdff079192cb898bb9de51b16b) --- drivers/media/platform/qcom/iris/iris_vpu_common.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index ca96e91222c67..663f2af2c8385 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -78,7 +78,6 @@ int iris_vpu_boot_firmware(struct iris_core *core) iris_vpu_setup_ucregion_memory_map(core); writel(ctrl_init, core->reg_base + CTRL_INIT); - writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); while (!ctrl_status && count < max_tries) { ctrl_status = readl(core->reg_base + CTRL_STATUS); From a17ac329045bc3a3cd8e5a2407e34885f5783e1f Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 28 Apr 2026 09:24:08 +0530 Subject: [PATCH 0743/1330] FROMLIST: dt-bindings: media: qcom,glymur-iris: Add glymur video codec Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur is a new generation of video IP that introduces a dual-core architecture. The second core brings its own power domain, clocks, and reset lines, requiring additional power domains and clocks in the power sequence. To accommodate glymur clock and power resources requirement, the maxItems constraints in qcom,venus-common.yaml are relaxed. This allows the glymur binding to inherit from the common venus schema without duplicating shared properties. Link: https://lore.kernel.org/all/20260428-glymur-v3-2-8f28930f47d3@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy (cherry picked from commit 468388966890ed5373ba6ddb7063fa14602e267e) --- .../bindings/media/qcom,glymur-iris.yaml | 211 ++++++++++++++++++ .../bindings/media/qcom,venus-common.yaml | 8 +- include/dt-bindings/media/qcom,glymur-iris.h | 11 + 3 files changed, 226 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml create mode 100644 include/dt-bindings/media/qcom,glymur-iris.h diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml new file mode 100644 index 0000000000000..3c5305b688ec7 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Glymur SoC Iris video encoder and decoder + +maintainers: + - Vishnu Reddy + +description: + The Iris video processing unit on Qualcomm Glymur SoC is a video encode and + decode accelerator. + +properties: + compatible: + const: qcom,glymur-iris + + clocks: + maxItems: 9 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + - const: iface1 + - const: core_freerun + - const: vcodec0_core_freerun + - const: iface2 + - const: vcodec1_core + - const: vcodec1_core_freerun + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + iommus: + maxItems: 4 + + iommu-map: + maxItems: 1 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 5 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + - const: vcodec1 + + resets: + maxItems: 6 + + reset-names: + items: + - const: bus0 + - const: bus1 + - const: core + - const: vcodec0_core + - const: bus2 + - const: vcodec1_core + +required: + - compatible + - reg + - clocks + - clock-names + - dma-coherent + - interconnects + - interconnect-names + - interrupts + - iommus + - memory-region + - power-domains + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + video-codec@aa00000 { + compatible = "qcom,glymur-iris"; + reg = <0x0aa00000 0xf0000>; + + clocks = <&gcc_video_axi0_clk>, + <&videocc_mvs0c_clk>, + <&videocc_mvs0_clk>, + <&gcc_video_axi0c_clk>, + <&videocc_mvs0c_freerun_clk>, + <&videocc_mvs0_freerun_clk>, + <&gcc_video_axi1_clk>, + <&videocc_mvs1_clk>, + <&videocc_mvs1_freerun_clk>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun", + "iface2", + "vcodec1_core", + "vcodec1_core_freerun"; + + dma-coherent; + + interconnects = <&hsc_noc_master_appss_proc &config_noc_slave_venus_cfg>, + <&mmss_noc_master_video &mc_virt_slave_ebi1>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = ; + + iommus = <&apps_smmu 0x1940 0x0>, + <&apps_smmu 0x1943 0x0>, + <&apps_smmu 0x1944 0x0>, + <&apps_smmu 0x19e0 0x0>; + + iommu-map = ; + + memory-region = <&video_mem>; + + operating-points-v2 = <&iris_opp_table>; + + power-domains = <&videocc_mvs0c_gdsc>, + <&videocc_mvs0_gdsc>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc_mvs1_gdsc>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx", + "vcodec1"; + + resets = <&gcc_video_axi0_clk_ares>, + <&gcc_video_axi0c_clk_ares>, + <&videocc_mvs0c_freerun_clk_ares>, + <&videocc_mvs0_freerun_clk_ares>, + <&gcc_video_axi1_clk_ares>, + <&videocc_mvs1_freerun_clk_ares>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core", + "bus2", + "vcodec1_core"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 240000000 360000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000 338000000 507000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000 366000000 549000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000 444000000 666000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334 533333334 800000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-655000000 { + opp-hz = /bits/ 64 <655000000 655000000 982000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml index 3153d91f9d18a..bf926c6020377 100644 --- a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml +++ b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml @@ -20,11 +20,11 @@ properties: clocks: minItems: 3 - maxItems: 7 + maxItems: 9 clock-names: minItems: 3 - maxItems: 7 + maxItems: 9 firmware-name: maxItems: 1 @@ -41,11 +41,11 @@ properties: power-domains: minItems: 1 - maxItems: 4 + maxItems: 5 power-domain-names: minItems: 1 - maxItems: 4 + maxItems: 5 video-firmware: type: object diff --git a/include/dt-bindings/media/qcom,glymur-iris.h b/include/dt-bindings/media/qcom,glymur-iris.h new file mode 100644 index 0000000000000..dcaa2bc21db56 --- /dev/null +++ b/include/dt-bindings/media/qcom,glymur-iris.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_ +#define _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_ + +#define IOMMU_FID_IRIS_FIRMWARE 0 + +#endif From 3368b874abbc9c85912c4dc8e57c5abc0492ff6b Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 28 Apr 2026 09:24:13 +0530 Subject: [PATCH 0744/1330] FROMLIST: media: iris: Rename clock and power domain macros to use vcodec prefix The current clock and power domain enum names are too generic. Rename them with a vcodec prefix to make the names more meaningful and to easily accommodate vcodec1 enums for the secondary core for glymur platform. No functional changes intended. Link: https://lore.kernel.org/all/20260428-glymur-v3-7-8f28930f47d3@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy (cherry picked from commit 5951ea504431cd344a94f11346f98ce11a84090a) --- .../platform/qcom/iris/iris_platform_common.h | 12 +++---- .../qcom/iris/iris_platform_kaanapali.h | 20 +++++------ .../platform/qcom/iris/iris_platform_sc7280.h | 10 +++--- .../platform/qcom/iris/iris_platform_sm8250.h | 6 ++-- .../platform/qcom/iris/iris_platform_sm8550.h | 6 ++-- .../platform/qcom/iris/iris_platform_sm8750.h | 12 +++---- .../qcom/iris/iris_platform_x1p42100.h | 8 ++--- drivers/media/platform/qcom/iris/iris_vpu3x.c | 30 +++++++++-------- drivers/media/platform/qcom/iris/iris_vpu4x.c | 30 +++++++++-------- .../platform/qcom/iris/iris_vpu_common.c | 33 ++++++++++--------- 10 files changed, 86 insertions(+), 81 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 4db1690cddbeb..fbcc74527a4f2 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -53,14 +53,14 @@ extern const struct iris_platform_data sm8750_data; extern const struct iris_platform_data x1p42100_data; enum platform_clk_type { - IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ + IRIS_AXI_VCODEC_CLK, IRIS_CTRL_CLK, IRIS_AHB_CLK, - IRIS_HW_CLK, - IRIS_HW_AHB_CLK, - IRIS_AXI1_CLK, + IRIS_VCODEC_CLK, + IRIS_VCODEC_AHB_CLK, + IRIS_AXI_CTRL_CLK, IRIS_CTRL_FREERUN_CLK, - IRIS_HW_FREERUN_CLK, + IRIS_VCODEC_FREERUN_CLK, IRIS_BSE_HW_CLK, IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, @@ -210,7 +210,7 @@ struct icc_vote_data { enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, - IRIS_HW_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h index 247fb9d7cb632..78c22be80f5c3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h @@ -25,16 +25,16 @@ static const char *const kaanapali_pmdomain_table[] = { }; static const struct platform_clk_data kaanapali_clk_table[] = { - { IRIS_AXI_CLK, "iface" }, - { IRIS_CTRL_CLK, "core" }, - { IRIS_HW_CLK, "vcodec0_core" }, - { IRIS_AXI1_CLK, "iface1" }, - { IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, - { IRIS_BSE_HW_CLK, "vcodec_bse" }, - { IRIS_VPP0_HW_CLK, "vcodec_vpp0" }, - { IRIS_VPP1_HW_CLK, "vcodec_vpp1" }, - { IRIS_APV_HW_CLK, "vcodec_apv" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_BSE_HW_CLK, "vcodec_bse" }, + {IRIS_VPP0_HW_CLK, "vcodec_vpp0" }, + {IRIS_VPP1_HW_CLK, "vcodec_vpp1" }, + {IRIS_APV_HW_CLK, "vcodec_apv" }, }; static const char *const kaanapali_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h index 0ec8f334df670..6b783e524b819 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -16,11 +16,11 @@ static const struct bw_info sc7280_bw_table_dec[] = { static const char * const sc7280_opp_pd_table[] = { "cx" }; static const struct platform_clk_data sc7280_clk_table[] = { - {IRIS_CTRL_CLK, "core" }, - {IRIS_AXI_CLK, "iface" }, - {IRIS_AHB_CLK, "bus" }, - {IRIS_HW_CLK, "vcodec_core" }, - {IRIS_HW_AHB_CLK, "vcodec_bus" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_VCODEC_CLK, "vcodec_core" }, + {IRIS_VCODEC_AHB_CLK, "vcodec_bus" }, }; static const char * const sc7280_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h index 50306043eb8ec..964e1cd920860 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -16,9 +16,9 @@ static const struct bw_info sm8250_bw_table_dec[] = { static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" }; static const struct platform_clk_data sm8250_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, }; static const char * const sm8250_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h index a9d9709c2e352..3b3f17b18707e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -9,9 +9,9 @@ static const char * const sm8550_clk_reset_table[] = { "bus" }; static const struct platform_clk_data sm8550_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, }; static struct platform_inst_caps platform_inst_cap_sm8550 = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h index 719056656a5ba..f843f13251c5c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h @@ -11,12 +11,12 @@ static const char * const sm8750_clk_reset_table[] = { }; static const struct platform_clk_data sm8750_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, - {IRIS_AXI1_CLK, "iface1" }, - {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - {IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, }; #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h index d89acfbc1233d..2c0b0644cd5aa 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h +++ b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h @@ -7,10 +7,10 @@ #define __IRIS_PLATFORM_X1P42100_H__ static const struct platform_clk_data x1p42100_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, - {IRIS_BSE_HW_CLK, "vcodec0_bse" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_BSE_HW_CLK, "vcodec0_bse" }, }; static const char *const x1p42100_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 5799e7e2aae2b..54aa079b2bd92 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -75,11 +75,12 @@ static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_power; @@ -90,9 +91,9 @@ static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) return 0; err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } @@ -241,7 +242,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core) disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); return 0; } @@ -250,30 +251,31 @@ static int iris_vpu35_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); if (ret) goto err_disable_axi_clk; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_hw_free_clk; return 0; err_disable_hw_free_clk: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); err_disable_axi_clk: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } @@ -282,8 +284,8 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) { iris_vpu33_power_off_hardware(core); - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } const struct vpu_ops iris_vpu3_ops = { diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c index 02e100a4045fc..92c0b06bbbff4 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -27,7 +27,8 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 { int ret; - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode); + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], + hw_mode); if (ret) return ret; @@ -63,7 +64,7 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN], !hw_mode); restore_hw_domain_mode: - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode); return ret; } @@ -162,15 +163,15 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v { int ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); if (ret) goto disable_axi_clock; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto disable_hw_free_run_clock; @@ -198,11 +199,11 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v disable_bse_hw_clock: iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); disable_hw_free_run_clock: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); return ret; } @@ -216,9 +217,9 @@ static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32 efuse iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } static int iris_vpu4x_power_on_hardware(struct iris_core *core) @@ -226,7 +227,8 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR); int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; @@ -267,7 +269,7 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs [IRIS_VPP0_HW_POWER_DOMAIN]); disable_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } @@ -345,7 +347,7 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs [IRIS_VPP0_HW_POWER_DOMAIN]); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); } static int iris_vpu4x_set_hwmode(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 663f2af2c8385..6b2e319a974a7 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -213,7 +213,7 @@ int iris_vpu_power_off_controller(struct iris_core *core) disable_power: iris_disable_unprepare_clock(core, IRIS_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); return 0; @@ -221,10 +221,10 @@ int iris_vpu_power_off_controller(struct iris_core *core) void iris_vpu_power_off_hw(struct iris_core *core) { - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); } void iris_vpu_power_off(struct iris_core *core) @@ -251,7 +251,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) goto err_disable_power; @@ -268,7 +268,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) err_disable_ctrl_clock: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); err_disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); @@ -279,31 +279,32 @@ int iris_vpu_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_AHB_CLK); if (ret && ret != -ENOENT) goto err_disable_hw_clock; return 0; err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } int iris_vpu_set_hwmode(struct iris_core *core) { - return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); + return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true); } int iris_vpu_switch_to_hwmode(struct iris_core *core) @@ -366,7 +367,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) disable_power: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); @@ -383,7 +384,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_CTRL_CLK); if (ret) goto err_disable_power; @@ -400,7 +401,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) err_disable_ctrl_free_clk: iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); err_disable_axi1_clk: - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); From 5589e66242b5689050a36611d091a21c9e3fa901 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 28 Apr 2026 09:24:14 +0530 Subject: [PATCH 0745/1330] FROMLIST: media: iris: Use power domain type to look up pd_devs index The pmdomain_tbl was a array of strings holding only the power domain names. Callers had to pass a pd_devs[] pointer indexed directly by the platform_pm_domain_type enum value to iris_enable_power_domains() and iris_disable_power_domains(). A future platform may need to introduce a new enum value that aliases an existing one (e.g. IRIS_VCODEC1_POWER_DOMAIN aliasing the IRIS_VPP0_HW_POWER_DOMAIN on Glymur), which would break the assumption that enum values map 1:1 to pd_devs[] indices. To fix this, replace the string array with a new struct platform_pd_data that pairs each power domain name with its platform_pm_domain_type. Add a helper iris_get_pd_index_by_type() that walks this table and returns the correct pd_devs[] index for a given type. Update iris_enable_power_domains() and iris_disable_power_domains() to accept a platform_pm_domain_type instead of a struct device pointer. They now call the helper internally to resolve the index, removing the need for callers to do the index lookup themselves. This prepares the driver for adding new platforms where power domain enum values cannot be used directly as pd_devs[] indices. Link: https://lore.kernel.org/all/20260428-glymur-v3-8-8f28930f47d3@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy (cherry picked from commit 0fab535e635f5773fbe5f63a4995ca5228f51b58) --- .../platform/qcom/iris/iris_platform_common.h | 9 +++- .../qcom/iris/iris_platform_kaanapali.h | 22 +++++--- .../platform/qcom/iris/iris_platform_vpu2.c | 18 +++++-- .../platform/qcom/iris/iris_platform_vpu3x.c | 27 ++++++---- .../platform/qcom/iris/iris_platform_vpu4x.c | 3 +- drivers/media/platform/qcom/iris/iris_probe.c | 4 +- .../media/platform/qcom/iris/iris_resources.c | 44 +++++++++++++++- .../media/platform/qcom/iris/iris_resources.h | 6 ++- drivers/media/platform/qcom/iris/iris_vpu3x.c | 12 ++--- drivers/media/platform/qcom/iris/iris_vpu4x.c | 52 +++++++------------ .../platform/qcom/iris/iris_vpu_common.c | 23 ++++---- 11 files changed, 136 insertions(+), 84 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index fbcc74527a4f2..52c09f29e81c1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -268,6 +268,12 @@ struct iris_firmware_desc { const char *fwname; }; +struct platform_pd_data { + enum platform_pm_domain_type *pd_types; + const char **pd_names; + u32 pd_count; +}; + struct iris_platform_data { /* * XXX: replace with gen1 / gen2 pointers once we have platforms @@ -283,8 +289,7 @@ struct iris_platform_data { unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; + const struct platform_pd_data *pmdomain_tbl; const char * const *opp_pd_tbl; unsigned int opp_pd_tbl_size; const struct platform_clk_data *clk_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h index 78c22be80f5c3..cade13ce1985b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h @@ -16,12 +16,22 @@ static const char *const kaanapali_clk_reset_table[] = { "vcodec0_core_freerun_reset", }; -static const char *const kaanapali_pmdomain_table[] = { - "venus", - "vcodec0", - "vpp0", - "vpp1", - "apv", +static const struct platform_pd_data kaanapali_pmdomain_table = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + IRIS_VPP0_HW_POWER_DOMAIN, + IRIS_VPP1_HW_POWER_DOMAIN, + IRIS_APV_HW_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + "vpp0", + "vpp1", + "apv", + }, + .pd_count = 5, }; static const struct platform_clk_data kaanapali_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index ff8ce078238a5..3c820c8ac9557 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -62,7 +62,17 @@ static const struct icc_info iris_icc_info_vpu2[] = { static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" }; -static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" }; +static const struct platform_pd_data iris_pmdomain_table_vpu2 = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + }, + .pd_count = 2, +}; static const struct tz_cp_config tz_cp_config_vpu2[] = { { @@ -80,8 +90,7 @@ const struct iris_platform_data sc7280_data = { .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), .bw_tbl_dec = sc7280_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl = iris_pmdomain_table_vpu2, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), + .pmdomain_tbl = &iris_pmdomain_table_vpu2, .opp_pd_tbl = sc7280_opp_pd_table, .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), .clk_tbl = sc7280_clk_table, @@ -111,8 +120,7 @@ const struct iris_platform_data sm8250_data = { .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2), .bw_tbl_dec = sm8250_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl = iris_pmdomain_table_vpu2, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), + .pmdomain_tbl = &iris_pmdomain_table_vpu2, .opp_pd_tbl = sm8250_opp_pd_table, .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), .clk_tbl = sm8250_clk_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index bb1df13563952..17dc95bef1847 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -73,7 +73,17 @@ static const struct bw_info iris_bw_table_dec_vpu3x[] = { { ((1920 * 1080) / 256) * 30, 294000 }, }; -static const char * const iris_pmdomain_table_vpu3x[] = { "venus", "vcodec0" }; +static const struct platform_pd_data iris_pmdomain_table_vpu3x = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + }, + .pd_count = 2, +}; static const char * const iris_opp_pd_table_vpu3x[] = { "mxc", "mmcx" }; @@ -155,8 +165,7 @@ const struct iris_platform_data qcs8300_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -187,8 +196,7 @@ const struct iris_platform_data sm8550_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -225,8 +233,7 @@ const struct iris_platform_data sm8650_data = { .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -255,8 +262,7 @@ const struct iris_platform_data sm8750_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8750_clk_table, @@ -287,8 +293,7 @@ const struct iris_platform_data x1p42100_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = x1p42100_clk_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c index cbd5af0e651db..29fd795c98418 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c @@ -86,8 +86,7 @@ const struct iris_platform_data kaanapali_data = { .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu4x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu4x), - .pmdomain_tbl = kaanapali_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), + .pmdomain_tbl = &kaanapali_pmdomain_table, .opp_pd_tbl = iris_opp_pd_table_vpu4x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu4x), .clk_tbl = kaanapali_clk_table, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 7fc9d2e7ff05c..d2838284b349d 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -43,8 +43,8 @@ static int iris_init_power_domains(struct iris_core *core) int ret; struct dev_pm_domain_attach_data iris_pd_data = { - .pd_names = core->iris_platform_data->pmdomain_tbl, - .num_pd_names = core->iris_platform_data->pmdomain_tbl_size, + .pd_names = core->iris_platform_data->pmdomain_tbl->pd_names, + .num_pd_names = core->iris_platform_data->pmdomain_tbl->pd_count, .pd_flags = PD_FLAG_NO_DEV_LINK, }; diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c index b10884eb3ac64..da783874cc1a4 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -72,10 +72,43 @@ int iris_opp_set_rate(struct device *dev, unsigned long freq) return dev_pm_opp_set_opp(dev, opp); } -int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev) +static int iris_get_pd_index_by_type(struct iris_core *core, enum platform_pm_domain_type pd_type) { + const struct platform_pd_data *pd_tbl; + u32 pd_count, i; + + pd_tbl = core->iris_platform_data->pmdomain_tbl; + pd_count = core->iris_platform_data->pmdomain_tbl->pd_count; + + for (i = 0; i < pd_count; i++) { + if (pd_tbl->pd_types[i] == pd_type) + return i; + } + + return -EINVAL; +} + +int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type, bool hwmode) +{ + int pd_index = iris_get_pd_index_by_type(core, pd_type); + + if (pd_index < 0) + return pd_index; + + return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[pd_index], hwmode); +} + +int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type) +{ + int pd_index = iris_get_pd_index_by_type(core, pd_type); + struct device *pd_dev; int ret; + if (pd_index < 0) + return pd_index; + + pd_dev = core->pmdomain_tbl->pd_devs[pd_index]; + ret = iris_opp_set_rate(core->dev, ULONG_MAX); if (ret) return ret; @@ -87,10 +120,17 @@ int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev) return ret; } -int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev) +int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type) { + int pd_index = iris_get_pd_index_by_type(core, pd_type); + struct device *pd_dev; int ret; + if (pd_index < 0) + return pd_index; + + pd_dev = core->pmdomain_tbl->pd_devs[pd_index]; + ret = iris_opp_set_rate(core->dev, 0); if (ret) return ret; diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h index e6a6dc24a7f12..8b46f036e9121 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -9,13 +9,15 @@ struct iris_core; int iris_opp_set_rate(struct device *dev, unsigned long freq); -int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev); -int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev); +int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type); +int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type); int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id); struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_type buffer_type); +int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type, + bool hwmode); #endif diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 54aa079b2bd92..91a9059941c1f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -75,8 +75,7 @@ static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); if (ret) return ret; @@ -93,7 +92,7 @@ static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); return ret; } @@ -241,7 +240,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); return 0; @@ -251,8 +250,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); if (ret) return ret; @@ -275,7 +273,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core) err_disable_axi_clk: iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); return ret; } diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c index 92c0b06bbbff4..bf7ad4e7cb8a4 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -27,28 +27,24 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 { int ret; - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], - hw_mode); + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, hw_mode); if (ret) return ret; if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode); + ret = iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, hw_mode); if (ret) goto restore_hw_domain_mode; } if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode); + ret = iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, hw_mode); if (ret) goto restore_vpp0_domain_mode; } if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_APV_HW_POWER_DOMAIN], hw_mode); + ret = iris_genpd_set_hwmode(core, IRIS_APV_HW_POWER_DOMAIN, hw_mode); if (ret) goto restore_vpp1_domain_mode; } @@ -57,14 +53,12 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 restore_vpp1_domain_mode: if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_DOMAIN], - !hw_mode); + iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, !hw_mode); restore_vpp0_domain_mode: if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN], - !hw_mode); + iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, !hw_mode); restore_hw_domain_mode: - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode); + iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, !hw_mode); return ret; } @@ -73,8 +67,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); if (ret) return ret; @@ -85,7 +78,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core) return 0; disable_apv_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); return ret; } @@ -140,7 +133,7 @@ static void iris_vpu4x_power_off_apv(struct iris_core *core) disable_clocks_and_power: iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); } static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core) @@ -227,21 +220,18 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR); int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); if (ret) return ret; if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); if (ret) goto disable_hw_power_domain; } if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); if (ret) goto disable_vpp0_power_domain; } @@ -262,14 +252,12 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) iris_vpu4x_disable_hardware_clocks(core, efuse_value); disable_vpp1_power_domain: if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); disable_vpp0_power_domain: if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); disable_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); return ret; } @@ -340,14 +328,12 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core) iris_vpu4x_disable_hardware_clocks(core, efuse_value); if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); } static int iris_vpu4x_set_hwmode(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 6b2e319a974a7..c96c02862aeec 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -214,15 +214,15 @@ int iris_vpu_power_off_controller(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); return 0; } void iris_vpu_power_off_hw(struct iris_core *core) { - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); } @@ -243,7 +243,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); if (ret) return ret; @@ -270,7 +270,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) err_disable_axi_clock: iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); return ret; } @@ -279,8 +279,7 @@ int iris_vpu_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); if (ret) return ret; @@ -297,14 +296,14 @@ int iris_vpu_power_on_hw(struct iris_core *core) err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); return ret; } int iris_vpu_set_hwmode(struct iris_core *core) { - return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true); + return iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); } int iris_vpu_switch_to_hwmode(struct iris_core *core) @@ -369,7 +368,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); reset_control_bulk_reset(clk_rst_tbl_size, core->resets); @@ -380,7 +379,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); if (ret) return ret; @@ -403,7 +402,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) err_disable_axi1_clk: iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); return ret; } From 1a91e1f976dc522d1d5bedb600764be42fba22af Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 28 Apr 2026 09:24:15 +0530 Subject: [PATCH 0746/1330] FROMLIST: media: iris: Add power sequence for Glymur Glymur has a secondary video codec core (vcodec1), equivalent to the primary core (vcodec0), but with independent power domains, clocks, and reset lines. Reuse the existing code wherever possible and add power sequence for vcodec1. Link: https://lore.kernel.org/all/20260428-glymur-v3-9-8f28930f47d3@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy (cherry picked from commit fa1539aa5268b67c704bd4fe22d5e5c276629d04) --- .../platform/qcom/iris/iris_platform_common.h | 4 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 137 ++++++++++++++++++ .../platform/qcom/iris/iris_vpu_common.h | 1 + .../qcom/iris/iris_vpu_register_defines.h | 7 + 4 files changed, 149 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 52c09f29e81c1..2171f2ae92b5c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -65,6 +65,9 @@ enum platform_clk_type { IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, IRIS_APV_HW_CLK, + IRIS_AXI_VCODEC1_CLK, + IRIS_VCODEC1_CLK, + IRIS_VCODEC1_FREERUN_CLK, }; struct platform_clk_data { @@ -214,6 +217,7 @@ enum platform_pm_domain_type { IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, + IRIS_VCODEC1_POWER_DOMAIN, }; struct iris_firmware_data { diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 91a9059941c1f..60359d45ed981 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -27,6 +27,16 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) return pwr_status ? false : true; } +static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) +{ + u32 value, pwr_status; + + value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); + pwr_status = value & BIT(4); + + return !pwr_status; +} + static void iris_vpu3_power_off_hardware(struct iris_core *core) { u32 reg_val = 0, value, i; @@ -286,6 +296,124 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } +static int iris_vpu36_power_on_hw1(struct iris_core *core) +{ + int ret; + + ret = iris_enable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); + if (ret) + return ret; + + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC1_CLK); + if (ret) + goto err_disable_hw1_power; + + ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_FREERUN_CLK); + if (ret) + goto err_disable_axi1_clk; + + ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_CLK); + if (ret) + goto err_disable_hw1_free_clk; + + return 0; + +err_disable_hw1_free_clk: + iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); +err_disable_axi1_clk: + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); +err_disable_hw1_power: + iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); + + return ret; +} + +static int iris_vpu36_power_on_hw(struct iris_core *core) +{ + int ret; + + ret = iris_vpu35_power_on_hw(core); + if (ret) + return ret; + + ret = iris_vpu36_power_on_hw1(core); + if (ret) + goto err_power_off_hw; + + return 0; + +err_power_off_hw: + iris_vpu35_power_off_hw(core); + + return ret; +} + +static void iris_vpu36_power_off_hw1(struct iris_core *core) +{ + u32 value, i; + int ret; + + if (iris_vpu36_hw1_power_collapsed(core)) + goto disable_power; + + value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret = readl_poll_timeout(core->reg_base + VCODEC1_SS_IDLE_STATUSN + 4 * i, + value, value & DMA_NOC_IDLE, 2000, 20000); + if (ret) + goto disable_power; + } + + writel(REQ_VCODEC1_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, + value, value & NOC_LPI_VCODEC1_STATUS_DONE, 2000, 20000); + if (ret) + goto disable_power; + + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + writel(VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_power: + iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, false); + iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); + iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); +} + +static void iris_vpu36_power_off_hw(struct iris_core *core) +{ + iris_vpu35_power_off_hw(core); + iris_vpu36_power_off_hw1(core); +} + +static int iris_vpu36_set_hwmode(struct iris_core *core) +{ + int ret; + + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); + if (ret) + return ret; + + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, true); + if (ret) + goto error_disable_hwmode; + + return 0; + +error_disable_hwmode: + iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false); + + return ret; +} + const struct vpu_ops iris_vpu3_ops = { .power_off_hw = iris_vpu3_power_off_hardware, .power_on_hw = iris_vpu_power_on_hw, @@ -322,3 +450,12 @@ const struct vpu_ops iris_vpu35_ops = { .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode = iris_vpu_set_hwmode, }; + +const struct vpu_ops iris_vpu36_ops = { + .power_off_hw = iris_vpu36_power_off_hw, + .power_on_hw = iris_vpu36_power_on_hw, + .power_off_controller = iris_vpu35_vpu4x_power_off_controller, + .power_on_controller = iris_vpu35_vpu4x_power_on_controller, + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode = iris_vpu36_set_hwmode, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index 9d531fd8c3cc6..c0b32ae9e1c6c 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu3_purwa_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; +extern const struct vpu_ops iris_vpu36_ops; extern const struct vpu_ops iris_vpu4x_ops; struct vpu_ops { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index 72168b9ffa738..37f234484f1b8 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -7,6 +7,7 @@ #define __IRIS_VPU_REGISTER_DEFINES_H__ #define VCODEC_BASE_OFFS 0x00000000 +#define VCODEC1_BASE_OFFS 0x00040000 #define AON_MVP_NOC_RESET 0x0001F000 #define CPU_BASE_OFFS 0x000A0000 #define WRAPPER_BASE_OFFS 0x000B0000 @@ -14,6 +15,8 @@ #define AON_BASE_OFFS 0x000E0000 #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) +#define VCODEC1_SS_IDLE_STATUSN (VCODEC1_BASE_OFFS + 0x70) +#define DMA_NOC_IDLE BIT(22) #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) @@ -35,6 +38,8 @@ #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) #define CORE_BRIDGE_SW_RESET BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) +#define VCODEC1_BRIDGE_SW_RESET BIT(2) +#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(3) #define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) #define MSK_SIGNAL_FROM_TENSILICA BIT(0) @@ -52,11 +57,13 @@ #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) #define REQ_POWER_DOWN_PREP BIT(0) +#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1) #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) #define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ #define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ #define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ +#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8) #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) From 064e5773b832ea12decab9e90f1366033f145863 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 28 Apr 2026 09:24:16 +0530 Subject: [PATCH 0747/1330] FROMLIST: media: iris: Add support to select core for dual core platforms On platforms with dual vcodec cores, select the hardware core for a session based on current load. Assign the session to vcodec0 if its MBPF/MBPS capacity allows it, otherwise assign to vcodec1. Communicate the selected core to firmware using the new HFI_PROP_CORE_ID property. Link: https://lore.kernel.org/all/20260428-glymur-v3-10-8f28930f47d3@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy (cherry picked from commit dc8b8f0667f2f30287d02dbe092913974dabb03e) --- .../media/platform/qcom/iris/iris_common.c | 10 ++ .../media/platform/qcom/iris/iris_common.h | 1 + drivers/media/platform/qcom/iris/iris_core.h | 5 + .../platform/qcom/iris/iris_hfi_common.h | 1 + .../qcom/iris/iris_hfi_gen2_command.c | 19 ++++ .../qcom/iris/iris_hfi_gen2_defines.h | 1 + .../media/platform/qcom/iris/iris_instance.h | 2 + .../platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_power.c | 11 ++- drivers/media/platform/qcom/iris/iris_utils.c | 91 +++++++++++++++---- drivers/media/platform/qcom/iris/iris_vb2.c | 4 + drivers/media/platform/qcom/iris/iris_vidc.c | 6 +- 12 files changed, 129 insertions(+), 23 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media/platform/qcom/iris/iris_common.c index 25836561bcf3e..dade0273717a2 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -46,6 +46,16 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) inst->metadata_idx++; } +int iris_set_core_id(struct iris_inst *inst) +{ + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + + if (!inst->core->iris_platform_data->dual_core) + return 0; + + return hfi_ops->session_set_core_id(inst, inst->core_id); +} + int iris_process_streamon_input(struct iris_inst *inst) { const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; diff --git a/drivers/media/platform/qcom/iris/iris_common.h b/drivers/media/platform/qcom/iris/iris_common.h index b2a27b781c9ac..34e32c60f7687 100644 --- a/drivers/media/platform/qcom/iris/iris_common.h +++ b/drivers/media/platform/qcom/iris/iris_common.h @@ -11,6 +11,7 @@ struct iris_buffer; int iris_vb2_buffer_to_driver(struct vb2_buffer *vb2, struct iris_buffer *buf); void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf); +int iris_set_core_id(struct iris_inst *inst); int iris_process_streamon_input(struct iris_inst *inst); int iris_process_streamon_output(struct iris_inst *inst); int iris_session_streamoff(struct iris_inst *inst, u32 plane); diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 2a47fb7001331..c15b375e37909 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -30,6 +30,11 @@ enum domain_type { DECODER = BIT(1), }; +enum iris_vcodec_core_id { + IRIS_VCODEC0 = 1, + IRIS_VCODEC1, +}; + /** * struct iris_core - holds core parameters valid for all instances * diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index a27447eb25199..47786529998d5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -131,6 +131,7 @@ struct iris_hfi_session_ops { int (*session_drain)(struct iris_inst *inst, u32 plane); int (*session_resume_drain)(struct iris_inst *inst, u32 plane); int (*session_close)(struct iris_inst *inst); + int (*session_set_core_id)(struct iris_inst *inst, u32 core_id); }; struct hfi_subscription_params { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index c90b22a75bc56..a3533a1450bb6 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1300,6 +1300,24 @@ static int iris_hfi_gen2_session_release_buffer(struct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } +static int iris_hfi_gen2_set_core_id(struct iris_inst *inst, u32 core_id) +{ + struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst); + u32 payload = core_id; + + iris_hfi_gen2_packet_session_command(inst, + HFI_PROP_CORE_ID, + HFI_HOST_FLAGS_NONE, + HFI_PORT_NONE, + inst->session_id, + HFI_PAYLOAD_U32, + &payload, + sizeof(u32)); + + return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet, + inst_hfi_gen2->packet->size); +} + static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_open = iris_hfi_gen2_session_open, .session_set_config_params = iris_hfi_gen2_session_set_config_params, @@ -1313,6 +1331,7 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_drain = iris_hfi_gen2_session_drain, .session_resume_drain = iris_hfi_gen2_session_resume_drain, .session_close = iris_hfi_gen2_session_close, + .session_set_core_id = iris_hfi_gen2_set_core_id, }; static struct iris_inst *iris_hfi_gen2_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index cecf771c55dd3..600e9dc076690 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -56,6 +56,7 @@ #define HFI_PROP_BUFFER_HOST_MAX_COUNT 0x03000123 #define HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT 0x03000124 #define HFI_PROP_PIC_ORDER_CNT_TYPE 0x03000128 +#define HFI_PROP_CORE_ID 0x030001a9 enum hfi_rate_control { HFI_RC_VBR_CFR = 0x00000000, diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h index 9fa635e27a28d..99491513ee0de 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -39,6 +39,7 @@ struct iris_fmt { * * @list: used for attach an instance to the core * @core: pointer to core structure + * @core_id: specifies the hardware core on which the session runs * @session_id: id of current video session * @hfi_session_ops: iris HFI session ops * @ctx_q_lock: lock to serialize queues related ioctls @@ -84,6 +85,7 @@ struct iris_fmt { struct iris_inst { struct list_head list; struct iris_core *core; + u32 core_id; u32 session_id; const struct iris_hfi_session_ops *hfi_session_ops; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 2171f2ae92b5c..a52942675deda 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -317,6 +317,7 @@ struct iris_platform_data { u32 max_core_mbpf; /* max number of macroblocks per second supported */ u32 max_core_mbps; + bool dual_core; }; #endif diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/platform/qcom/iris/iris_power.c index 91aa21d4070eb..0e116c63f529d 100644 --- a/drivers/media/platform/qcom/iris/iris_power.c +++ b/drivers/media/platform/qcom/iris/iris_power.c @@ -77,9 +77,9 @@ static int iris_vote_interconnects(struct iris_inst *inst) static int iris_set_clocks(struct iris_inst *inst) { + u64 vcodec0_freq = 0, vcodec1_freq = 0; struct iris_core *core = inst->core; struct iris_inst *instance; - u64 freq = 0; int ret; mutex_lock(&core->lock); @@ -87,11 +87,14 @@ static int iris_set_clocks(struct iris_inst *inst) if (!instance->max_input_data_size) continue; - freq += instance->power.min_freq; + if (instance->core_id == IRIS_VCODEC0) + vcodec0_freq += instance->power.min_freq; + else if (instance->core_id == IRIS_VCODEC1) + vcodec1_freq += instance->power.min_freq; } - core->power.clk_freq = freq; - ret = iris_opp_set_rate(core->dev, freq); + core->power.clk_freq = vcodec0_freq > vcodec1_freq ? vcodec0_freq : vcodec1_freq; + ret = iris_opp_set_rate(core->dev, core->power.clk_freq); mutex_unlock(&core->lock); return ret; diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/platform/qcom/iris/iris_utils.c index 29b07d88507eb..430b533078c3b 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -87,40 +87,95 @@ struct iris_inst *iris_get_instance(struct iris_core *core, u32 session_id) return NULL; } +static u32 iris_get_mbps(struct iris_inst *inst) +{ + u32 fps = max(inst->frame_rate, inst->operating_rate); + + return iris_get_mbpf(inst) * fps; +} + +static void iris_get_core_load(struct iris_core *core, u32 *core_load, u32 *core_session, bool mbpf) +{ + bool dual_core = core->iris_platform_data->dual_core; + struct iris_inst *inst; + u32 load; + + core_load[0] = 0; + core_load[1] = 0; + core_session[0] = 0; + core_session[1] = 0; + + list_for_each_entry(inst, &core->instances, list) { + if (mbpf) + load = iris_get_mbpf(inst); + else + load = iris_get_mbps(inst); + + if (inst->core_id == IRIS_VCODEC0) { + core_load[0] += load; + core_session[0]++; + } else if (dual_core && inst->core_id == IRIS_VCODEC1) { + core_load[1] += load; + core_session[1]++; + } + } +} + +static int iris_select_core_id(struct iris_inst *inst, u32 *core_load, u32 *core_session, + u32 max_load, u32 new_load) +{ + u32 max_session = inst->core->iris_platform_data->max_session_count; + bool dual_core = inst->core->iris_platform_data->dual_core; + u32 core_index; + + core_index = (core_load[0] > core_load[1] && dual_core) ? 1 : 0; + + if (core_session[core_index] >= max_session) + core_index = core_index == 0 && dual_core ? 1 : 0; + + if (core_session[core_index] >= max_session) + return -ENOMEM; + + if (core_load[core_index] + new_load <= max_load) + inst->core_id = core_index == 0 ? IRIS_VCODEC0 : IRIS_VCODEC1; + else + return -ENOMEM; + + return 0; +} + int iris_check_core_mbpf(struct iris_inst *inst) { + u32 max_core_mbpf = inst->core->iris_platform_data->max_core_mbpf; + u32 core_mbpf[2], core_session[2], new_mbpf; struct iris_core *core = inst->core; - struct iris_inst *instance; - u32 total_mbpf = 0; + int ret; mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) - total_mbpf += iris_get_mbpf(instance); + inst->core_id = 0; + iris_get_core_load(inst->core, core_mbpf, core_session, true); + new_mbpf = iris_get_mbpf(inst); + ret = iris_select_core_id(inst, core_mbpf, core_session, max_core_mbpf, new_mbpf); mutex_unlock(&core->lock); - if (total_mbpf > core->iris_platform_data->max_core_mbpf) - return -ENOMEM; - - return 0; + return ret; } int iris_check_core_mbps(struct iris_inst *inst) { + u32 max_core_mbps = inst->core->iris_platform_data->max_core_mbps; + u32 core_mbps[2] = {0, 0}, core_session[2], new_mbps; struct iris_core *core = inst->core; - struct iris_inst *instance; - u32 total_mbps = 0, fps = 0; + int ret; mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) { - fps = max(instance->frame_rate, instance->operating_rate); - total_mbps += iris_get_mbpf(instance) * fps; - } + inst->core_id = 0; + iris_get_core_load(inst->core, core_mbps, core_session, false); + new_mbps = iris_get_mbps(inst); + ret = iris_select_core_id(inst, core_mbps, core_session, max_core_mbps, new_mbps); mutex_unlock(&core->lock); - if (total_mbps > core->iris_platform_data->max_core_mbps) - return -ENOMEM; - - return 0; + return ret; } bool is_rotation_90_or_270(struct iris_inst *inst) diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/platform/qcom/iris/iris_vb2.c index a2ea2d67f60d0..dbb89396e6514 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -176,6 +176,10 @@ int iris_vb2_start_streaming(struct vb2_queue *q, unsigned int count) if (ret) goto error; + ret = iris_set_core_id(inst); + if (ret) + goto error; + if (V4L2_TYPE_IS_OUTPUT(q->type)) { if (inst->domain == DECODER) ret = iris_vdec_streamon_input(inst); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 26df872fb4fa1..735ec17290425 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -41,16 +41,20 @@ static void iris_v4l2_fh_deinit(struct iris_inst *inst, struct file *filp) static void iris_add_session(struct iris_inst *inst) { + u32 max_session_count = inst->core->iris_platform_data->max_session_count; struct iris_core *core = inst->core; struct iris_inst *iter; u32 count = 0; + if (inst->core->iris_platform_data->dual_core) + max_session_count *= 2; + mutex_lock(&core->lock); list_for_each_entry(iter, &core->instances, list) count++; - if (count < core->iris_platform_data->max_session_count) + if (count < max_session_count) list_add_tail(&inst->list, &core->instances); mutex_unlock(&core->lock); From da3e870bb2755a04f191f0b8c3e7d5c403995708 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 28 Apr 2026 09:24:17 +0530 Subject: [PATCH 0748/1330] FROMLIST: media: iris: Add platform data for glymur On glymur platform, the iris core shares most properties with the iris core on the SM8550 platform. The major difference is that glymur integrates two codec cores (vcodec0 and vcodec1), while SM8550 has only one. Add glymur specific platform data, reusing SM8550 definitions wherever applicable. Link: https://lore.kernel.org/all/20260428-glymur-v3-11-8f28930f47d3@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy (cherry picked from commit ae6052088e389437463712432a461564498379a8) --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 5 ++ .../platform/qcom/iris/iris_platform_glymur.c | 71 +++++++++++++++++++ .../platform/qcom/iris/iris_platform_glymur.h | 15 ++++ .../platform/qcom/iris/iris_platform_vpu3x.c | 37 ++++++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 ++ 6 files changed, 133 insertions(+) create mode 100644 drivers/media/platform/qcom/iris/iris_platform_glymur.c create mode 100644 drivers/media/platform/qcom/iris/iris_platform_glymur.h diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index f8a017d878d62..8cdea242f7fdb 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -12,6 +12,7 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ + iris_platform_glymur.o \ iris_platform_vpu2.o \ iris_platform_vpu3x.o \ iris_platform_vpu4x.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index a52942675deda..45c0ec69466ca 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -29,6 +29,10 @@ struct iris_inst; #define DEFAULT_QP 20 #define BITRATE_DEFAULT 20000000 +#define VIDEO_REGION_SECURE_FW_REGION_ID 0 +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + enum stage_type { STAGE_1 = 1, STAGE_2 = 2, @@ -43,6 +47,7 @@ enum pipe_type { extern const struct iris_firmware_data iris_hfi_gen1_data; extern const struct iris_firmware_data iris_hfi_gen2_data; +extern const struct iris_platform_data glymur_data; extern const struct iris_platform_data kaanapali_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/drivers/media/platform/qcom/iris/iris_platform_glymur.c new file mode 100644 index 0000000000000..194431665e077 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_platform_common.h" +#include "iris_platform_glymur.h" + +const struct platform_clk_data iris_glymur_clk_table[] = { + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_VCODEC1_CLK, "iface2" }, + {IRIS_VCODEC1_CLK, "vcodec1_core" }, + {IRIS_VCODEC1_FREERUN_CLK, "vcodec1_core_freerun" }, +}; + +const char * const iris_glymur_clk_reset_table[] = { + "bus0", + "bus1", + "core", + "vcodec0_core", + "bus2", + "vcodec1_core", +}; + +const char * const iris_glymur_opp_clk_table[] = { + "vcodec0_core", + "vcodec1_core", + "core", + NULL, +}; + +const struct platform_pd_data iris_glymur_pmdomain_table = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + IRIS_VCODEC1_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + "vcodec1", + }, + .pd_count = 3, +}; + +const struct tz_cp_config iris_glymur_tz_cp_config[] = { + { + .cp_start = VIDEO_REGION_SECURE_FW_REGION_ID, + .cp_size = 0, + .cp_nonpixel_start = 0, + .cp_nonpixel_size = 0x1000000, + }, + { + .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + }, + { + .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x25800000, + .cp_nonpixel_size = 0xda600000, + }, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/drivers/media/platform/qcom/iris/iris_platform_glymur.h new file mode 100644 index 0000000000000..875a3c65c58f1 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_GLYMUR_H__ +#define __IRIS_PLATFORM_GLYMUR_H__ + +extern const struct platform_clk_data iris_glymur_clk_table[9]; +extern const char * const iris_glymur_clk_reset_table[6]; +extern const char * const iris_glymur_opp_clk_table[4]; +extern const struct platform_pd_data iris_glymur_pmdomain_table; +extern const struct tz_cp_config iris_glymur_tz_cp_config[3]; + +#endif /* __IRIS_PLATFORM_GLYMUR_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index 17dc95bef1847..a6ad4cc6c0635 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -12,12 +12,19 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" +#include "iris_platform_glymur.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8550.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" #include "iris_platform_x1p42100.h" +const struct iris_firmware_desc iris_vpu36_p4_s7_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu36_p4_s7.mbn", +}; + const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, @@ -152,6 +159,36 @@ static void sm8550_deinit_cb_devs(struct iris_core *core) core->dev_p = NULL; } +const struct iris_platform_data glymur_data = { + .firmware_desc = &iris_vpu36_p4_s7_gen2_desc, + .vpu_ops = &iris_vpu36_ops, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = iris_glymur_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(iris_glymur_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = &iris_glymur_pmdomain_table, + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = iris_glymur_clk_table, + .clk_tbl_size = ARRAY_SIZE(iris_glymur_clk_table), + .opp_clk_tbl = iris_glymur_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xffe00000 - 1, + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = iris_glymur_tz_cp_config, + .tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config), + .ubwc_config = &iris_ubwc_config_vpu3x, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4320) / 256) * 60, + .dual_core = true, +}; + /* * Shares most of SM8550 data except: * - inst_caps to platform_inst_cap_qcs8300 diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index d2838284b349d..a8c8e8c07eb09 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -372,6 +372,10 @@ static const struct dev_pm_ops iris_pm_ops = { }; static const struct of_device_id iris_dt_match[] = { + { + .compatible = "qcom,glymur-iris", + .data = &glymur_data, + }, { .compatible = "qcom,kaanapali-iris", .data = &kaanapali_data, From c832d378913cd01903bfc1ec9b55dca195e4c81e Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 25 Aug 2025 22:15:47 +0800 Subject: [PATCH 0749/1330] FROMLIST: drm/msm/dp: remove cached drm_edid from panel The cached drm_edid seems unnecessary here. Use the drm_edid pointer directly in the plug stage instead of caching it. Remove the cached drm_edid and the corresponding oneliner to simplify the code. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-1-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 6989ab8e411c64892997fc88a7927acd49a6335a) --- drivers/gpu/drm/msm/dp/dp_display.c | 27 +++++++++----- drivers/gpu/drm/msm/dp/dp_panel.c | 57 +++-------------------------- drivers/gpu/drm/msm/dp/dp_panel.h | 13 ++----- 3 files changed, 26 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 7ac4b8dd372ae..d88a19757afee 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -269,6 +269,7 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) const struct drm_display_info *info = &connector->display_info; int rc = 0; u8 dpcd[DP_RECEIVER_CAP_SIZE]; + const struct drm_edid *drm_edid; rc = drm_dp_read_dpcd_caps(dp->aux, dpcd); if (rc) @@ -276,10 +277,20 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) dp->link->lttpr_count = msm_dp_display_lttpr_init(dp, dpcd); - rc = msm_dp_panel_read_sink_caps(dp->panel, connector); + rc = msm_dp_panel_read_link_caps(dp->panel, connector); if (rc) goto end; + drm_edid = drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); + + if (!drm_edid) { + DRM_ERROR("panel edid read failed\n"); + /* check edid read fail is due to unplug */ + if (!msm_dp_aux_is_link_connected(dp->aux)) + return -ETIMEDOUT; + } + msm_dp_link_process_request(dp->link); if (!dp->msm_dp_display.is_edp) @@ -291,7 +302,7 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) dp->msm_dp_display.psr_supported = dp->panel->psr_cap.version && psr_enabled; dp->audio_supported = info->has_audio; - msm_dp_panel_handle_sink_request(dp->panel); + msm_dp_panel_handle_sink_request(dp->panel, drm_edid); /* * set sink to normal operation mode -- D0 @@ -450,7 +461,7 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) /* Don't forget modes for eDP */ if (!dp->msm_dp_display.is_edp) - msm_dp_panel_unplugged(dp->panel, dp->msm_dp_display.connector); + drm_edid_connector_update(dp->msm_dp_display.connector, NULL); /* triggered by irq_hdp with sink_count = 0 */ if (dp->link->sink_count == 0) @@ -513,7 +524,6 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp) static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_private *dp) { msm_dp_audio_put(dp->audio); - msm_dp_panel_put(dp->panel); msm_dp_aux_put(dp->aux); } @@ -564,7 +574,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) rc = PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc); dp->ctrl = NULL; - goto error_ctrl; + goto error_link; } dp->audio = msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base); @@ -572,13 +582,11 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) rc = PTR_ERR(dp->audio); pr_err("failed to initialize audio, rc = %d\n", rc); dp->audio = NULL; - goto error_ctrl; + goto error_link; } return rc; -error_ctrl: - msm_dp_panel_put(dp->panel); error_link: msm_dp_aux_put(dp->aux); error: @@ -742,8 +750,7 @@ int msm_dp_display_get_modes(struct msm_dp *dp) msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); - return msm_dp_panel_get_modes(msm_dp_display->panel, - dp->connector); + return drm_edid_connector_add_modes(msm_dp_display->panel->connector); } bool msm_dp_display_check_video_test(struct msm_dp *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 6bb021820d7c5..bde4a772d22c0 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -232,8 +232,8 @@ static u32 msm_dp_panel_get_supported_bpp(struct msm_dp_panel *msm_dp_panel, return min_supported_bpp; } -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector) { int rc, bw_code; int count; @@ -271,36 +271,9 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, rc = drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, msm_dp_panel->downstream_ports); - if (rc) - return rc; - - drm_edid_free(msm_dp_panel->drm_edid); - - msm_dp_panel->drm_edid = drm_edid_read_ddc(connector, &panel->aux->ddc); - - drm_edid_connector_update(connector, msm_dp_panel->drm_edid); - - if (!msm_dp_panel->drm_edid) { - DRM_ERROR("panel edid read failed\n"); - /* check edid read fail is due to unplug */ - if (!msm_dp_aux_is_link_connected(panel->aux)) { - rc = -ETIMEDOUT; - goto end; - } - } - -end: return rc; } -void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - drm_edid_connector_update(connector, NULL); - drm_edid_free(msm_dp_panel->drm_edid); - msm_dp_panel->drm_edid = NULL; -} - u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_edid_bpp, u32 mode_pclk_khz) { @@ -324,20 +297,6 @@ u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, return bpp; } -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - if (!msm_dp_panel) { - DRM_ERROR("invalid input\n"); - return -EINVAL; - } - - if (msm_dp_panel->drm_edid) - return drm_edid_connector_add_modes(connector); - - return 0; -} - static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) { edid += edid->extensions; @@ -345,7 +304,8 @@ static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) return edid->checksum; } -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid) { struct msm_dp_panel_private *panel; @@ -358,7 +318,7 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { /* FIXME: get rid of drm_edid_raw() */ - const struct edid *edid = drm_edid_raw(msm_dp_panel->drm_edid); + const struct edid *edid = drm_edid_raw(drm_edid); u8 checksum; if (edid) @@ -755,10 +715,3 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux return msm_dp_panel; } -void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel) -{ - if (!msm_dp_panel) - return; - - drm_edid_free(msm_dp_panel->drm_edid); -} diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 9173e90a50530..53b7b4463551f 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -33,7 +33,6 @@ struct msm_dp_panel { u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; struct msm_dp_link_info link_info; - const struct drm_edid *drm_edid; struct drm_connector *connector; struct msm_dp_display_mode msm_dp_mode; struct msm_dp_panel_psr psr_cap; @@ -47,15 +46,12 @@ struct msm_dp_panel { int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en); -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); -void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector); u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_max_bpp, u32 mode_pclk_khz); -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid); void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable); void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel); @@ -94,5 +90,4 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux struct msm_dp_link *link, void __iomem *link_base, void __iomem *p0_base); -void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel); #endif /* _DP_PANEL_H_ */ From 95274ab128546744c819229233e7f8a304fc71ca Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Sat, 28 Mar 2026 16:24:35 +0800 Subject: [PATCH 0750/1330] FROMLIST: drm/msm/dp: drop deprecated .mode_set() and use .atomic_enable The bridge .mode_set() callback is deprecated. Remove it and move all mode setup logic to .atomic_enable(), where the adjusted_mode is available from the atomic CRTC state. Drop msm_dp_mode from msm_dp_display_private and store the mode directly in the panel, as it was only used as a temporary cache. Both changes are limited to msm_dp_display_set_mode and are kept in a single patch. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-2-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 98e1cb107ec1fc0ae616e14e6f9bbdc53c36fcc7) --- drivers/gpu/drm/msm/dp/dp_display.c | 81 +++++++++++------------------ drivers/gpu/drm/msm/dp/dp_drm.c | 2 - drivers/gpu/drm/msm/dp/dp_drm.h | 3 -- 3 files changed, 31 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index d88a19757afee..b17f1dc6187f7 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -63,7 +63,6 @@ struct msm_dp_display_private { struct msm_dp_panel *panel; struct msm_dp_ctrl *ctrl; - struct msm_dp_display_mode msm_dp_mode; struct msm_dp msm_dp_display; /* wait for audio signaling */ @@ -594,16 +593,33 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) } static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, - struct msm_dp_display_mode *mode) + const struct drm_display_mode *adjusted_mode, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *dp; + u32 bpp; dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - drm_mode_copy(&dp->panel->msm_dp_mode.drm_mode, &mode->drm_mode); - dp->panel->msm_dp_mode.bpp = mode->bpp; - dp->panel->msm_dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420; - msm_dp_panel_init_panel_info(dp->panel); + drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); + if (msm_dp_display_check_video_test(msm_dp_display)) + bpp = msm_dp_display_get_test_bpp(msm_dp_display); + else + bpp = msm_dp_panel->connector->display_info.bpc * 3; + + msm_dp_panel->msm_dp_mode.bpp = bpp ? bpp : 24; /* Default bpp */ + msm_dp_panel->msm_dp_mode.v_active_low = + !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); + msm_dp_panel->msm_dp_mode.h_active_low = + !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 = + drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mode) && + msm_dp_panel->vsc_sdp_supported; + msm_dp_panel_init_panel_info(msm_dp_panel); + + /* populate wide_bus_support to different layers */ + dp->ctrl->wide_bus_en = + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 ? false : dp->wide_bus_supported; return 0; } @@ -1306,7 +1322,7 @@ bool msm_dp_wide_bus_available(const struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - if (dp->msm_dp_mode.out_fmt_is_yuv_420) + if (dp->panel->msm_dp_mode.out_fmt_is_yuv_420) return false; return dp->wide_bus_supported; @@ -1362,15 +1378,19 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, { struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = msm_dp_bridge->msm_dp_display; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; int rc = 0; struct msm_dp_display_private *msm_dp_display; bool force_link_train = false; msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); - if (!msm_dp_display->msm_dp_mode.drm_mode.clock) { - DRM_ERROR("invalid params\n"); + + crtc = drm_atomic_get_new_crtc_for_encoder(state, + drm_bridge->encoder); + if (!crtc) return; - } + crtc_state = drm_atomic_get_new_crtc_state(state, crtc); if (dp->is_edp) msm_dp_hpd_plug_handle(msm_dp_display); @@ -1383,7 +1403,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, if (msm_dp_display->link->sink_count == 0) return; - rc = msm_dp_display_set_mode(dp, &msm_dp_display->msm_dp_mode); + rc = msm_dp_display_set_mode(dp, &crtc_state->adjusted_mode, msm_dp_display->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=%d\n", rc); return; @@ -1441,45 +1461,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, pm_runtime_put_sync(&dp->pdev->dev); } -void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); - struct msm_dp *dp = msm_dp_bridge->msm_dp_display; - struct msm_dp_display_private *msm_dp_display; - struct msm_dp_panel *msm_dp_panel; - - msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); - msm_dp_panel = msm_dp_display->panel; - - memset(&msm_dp_display->msm_dp_mode, 0x0, sizeof(struct msm_dp_display_mode)); - - if (msm_dp_display_check_video_test(dp)) - msm_dp_display->msm_dp_mode.bpp = msm_dp_display_get_test_bpp(dp); - else /* Default num_components per pixel = 3 */ - msm_dp_display->msm_dp_mode.bpp = dp->connector->display_info.bpc * 3; - - if (!msm_dp_display->msm_dp_mode.bpp) - msm_dp_display->msm_dp_mode.bpp = 24; /* Default bpp */ - - drm_mode_copy(&msm_dp_display->msm_dp_mode.drm_mode, adjusted_mode); - - msm_dp_display->msm_dp_mode.v_active_low = - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); - - msm_dp_display->msm_dp_mode.h_active_low = - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); - - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 = - drm_mode_is_420_only(&dp->connector->display_info, adjusted_mode) && - msm_dp_panel->vsc_sdp_supported; - - /* populate wide_bus_support to different layers */ - msm_dp_display->ctrl->wide_bus_en = - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display->wide_bus_supported; -} - void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) { struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(bridge); diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index 8dc0dabd275cd..af3d3e3a2d841 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -56,7 +56,6 @@ static const struct drm_bridge_funcs msm_dp_bridge_ops = { .atomic_enable = msm_dp_bridge_atomic_enable, .atomic_disable = msm_dp_bridge_atomic_disable, .atomic_post_disable = msm_dp_bridge_atomic_post_disable, - .mode_set = msm_dp_bridge_mode_set, .mode_valid = msm_dp_bridge_mode_valid, .get_modes = msm_dp_bridge_get_modes, .detect = msm_dp_bridge_detect, @@ -233,7 +232,6 @@ static const struct drm_bridge_funcs msm_edp_bridge_ops = { .atomic_enable = msm_edp_bridge_atomic_enable, .atomic_disable = msm_edp_bridge_atomic_disable, .atomic_post_disable = msm_edp_bridge_atomic_post_disable, - .mode_set = msm_dp_bridge_mode_set, .mode_valid = msm_edp_bridge_mode_valid, .atomic_reset = drm_atomic_helper_bridge_reset, .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h index 6c0426803d78c..6d4cbb9f39182 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -36,9 +36,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode); -void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode); void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge); void msm_dp_bridge_hpd_disable(struct drm_bridge *bridge); void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, From 9f0dcfb35afc32406d323c283a69a10d9e78bd5b Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:15:49 +0800 Subject: [PATCH 0751/1330] FROMLIST: drm/msm/dp: break up dp_display_enable into two parts dp_display_enable() currently re-trains the link if needed and then enables the pixel clock, programs the controller to start sending the pixel stream. Split these two parts into prepare/enable APIs, to support MST bridges_enable insert the MST payloads funcs between enable stream_clks and program register. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-3-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 31c47bca173a1e79d76e23f7f154faf23735e6a0) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 54 +++++++++----- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 105 ++++++++++++++++++---------- 3 files changed, 106 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index ef298c7d3e5ee..d2d3f414d5333 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2472,27 +2472,19 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train) +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train) { int ret = 0; - bool mainlink_ready = false; struct msm_dp_ctrl_private *ctrl; - unsigned long pixel_rate; - unsigned long pixel_rate_orig; if (!msm_dp_ctrl) return -EINVAL; ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - pixel_rate = pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; - - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) - pixel_rate >>= 1; - - drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", - ctrl->link->link_params.rate, - ctrl->link->link_params.num_lanes, pixel_rate); + drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d\n", + ctrl->link->link_params.rate, + ctrl->link->link_params.num_lanes); drm_dbg_dp(ctrl->drm_dev, "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", @@ -2502,10 +2494,40 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); if (ret) { DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); - goto end; + return ret; } } + if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) + msm_dp_ctrl_link_retrain(ctrl); + + /* stop txing train pattern to end link training */ + msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + + return ret; +} + +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +{ + int ret = 0; + bool mainlink_ready = false; + struct msm_dp_ctrl_private *ctrl; + unsigned long pixel_rate; + unsigned long pixel_rate_orig; + + if (!msm_dp_ctrl) + return -EINVAL; + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate = pixel_rate_orig; + + if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) + pixel_rate >>= 1; + + drm_dbg_dp(ctrl->drm_dev, "pixel_rate=%lu\n", pixel_rate); + ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); @@ -2523,12 +2545,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train ctrl->stream_clks_on = true; } - if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) - msm_dp_ctrl_link_retrain(ctrl); - - /* stop txing train pattern to end link training */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); - /* * Set up transfer unit values and set controller state to send * video. diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index f68bee62713f1..1497f1a8fc2f0 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index b17f1dc6187f7..f5c39d6f2bedd 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -623,7 +623,40 @@ static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, return 0; } -static int msm_dp_display_enable(struct msm_dp_display_private *dp, bool force_link_train) +static int msm_dp_display_prepare(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display = &dp->msm_dp_display; + int rc = 0; + bool force_link_train = false; + + drm_dbg_dp(dp->drm_dev, "sink_count=%d\n", dp->link->sink_count); + + if (msm_dp_display->is_edp) + msm_dp_hpd_plug_handle(dp); + + rc = pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); + if (rc) { + DRM_ERROR("failed to pm_runtime_resume\n"); + return rc; + } + + if (dp->link->sink_count == 0) + return rc; + + if (!msm_dp_display->power_on) { + msm_dp_display_host_phy_init(dp); + force_link_train = true; + } + + rc = msm_dp_ctrl_on_link(dp->ctrl); + if (rc) + DRM_ERROR("Failed link training (rc=%d)\n", rc); + // TODO: schedule drm_connector_set_link_status_property() + + return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); +} + +static int msm_dp_display_enable(struct msm_dp_display_private *dp) { int rc = 0; struct msm_dp *msm_dp_display = &dp->msm_dp_display; @@ -634,7 +667,7 @@ static int msm_dp_display_enable(struct msm_dp_display_private *dp, bool force_l return 0; } - rc = msm_dp_ctrl_on_stream(dp->ctrl, force_link_train); + rc = msm_dp_ctrl_on_stream(dp->ctrl); if (!rc) msm_dp_display->power_on = true; @@ -664,13 +697,10 @@ static int msm_dp_display_post_enable(struct msm_dp *msm_dp_display) return 0; } -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static void msm_dp_display_audio_notify_disable(struct msm_dp_display_private *dp) { struct msm_dp *msm_dp_display = &dp->msm_dp_display; - if (!msm_dp_display->power_on) - return 0; - /* wait only if audio was enabled */ if (msm_dp_display->audio_enabled) { /* signal the disconnect event */ @@ -681,6 +711,14 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) } msm_dp_display->audio_enabled = false; +} + +static int msm_dp_display_disable(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display = &dp->msm_dp_display; + + if (!msm_dp_display->power_on) + return 0; if (dp->link->sink_count == 0) { /* @@ -1377,14 +1415,13 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, struct drm_atomic_state *state) { struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); - struct msm_dp *dp = msm_dp_bridge->msm_dp_display; + struct msm_dp *msm_dp_display = msm_dp_bridge->msm_dp_display; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int rc = 0; - struct msm_dp_display_private *msm_dp_display; - bool force_link_train = false; + struct msm_dp_display_private *dp; - msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); crtc = drm_atomic_get_new_crtc_for_encoder(state, drm_bridge->encoder); @@ -1392,42 +1429,29 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, return; crtc_state = drm_atomic_get_new_crtc_state(state, crtc); - if (dp->is_edp) - msm_dp_hpd_plug_handle(msm_dp_display); - - if (pm_runtime_resume_and_get(&dp->pdev->dev)) { - DRM_ERROR("failed to pm_runtime_resume\n"); - return; - } - - if (msm_dp_display->link->sink_count == 0) - return; - - rc = msm_dp_display_set_mode(dp, &crtc_state->adjusted_mode, msm_dp_display->panel); + rc = msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode, dp->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=%d\n", rc); return; } - if (!dp->power_on) { - msm_dp_display_host_phy_init(msm_dp_display); - force_link_train = true; + rc = msm_dp_display_prepare(dp); + if (rc) { + DRM_ERROR("DP display prepare failed, rc=%d\n", rc); + return; } - rc = msm_dp_ctrl_on_link(msm_dp_display->ctrl); + rc = msm_dp_display_enable(dp); if (rc) - DRM_ERROR("Failed link training (rc=%d)\n", rc); - // TODO: schedule drm_connector_set_link_status_property() + DRM_ERROR("DP display enable failed, rc=%d\n", rc); - msm_dp_display_enable(msm_dp_display, force_link_train); - - rc = msm_dp_display_post_enable(dp); + rc = msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=%d\n", rc); - msm_dp_display_disable(msm_dp_display); + msm_dp_display_disable(dp); } - drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type); + drm_dbg_dp(msm_dp_display->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); } void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -1442,6 +1466,15 @@ void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, msm_dp_ctrl_push_idle(msm_dp_display->ctrl); } +static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display = &dp->msm_dp_display; + + pm_runtime_put_sync(&msm_dp_display->pdev->dev); + + drm_dbg_dp(dp->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); +} + void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, struct drm_atomic_state *state) { @@ -1454,11 +1487,11 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, if (dp->is_edp) msm_dp_hpd_unplug_handle(msm_dp_display); - msm_dp_display_disable(msm_dp_display); + msm_dp_display_audio_notify_disable(msm_dp_display); - drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type); + msm_dp_display_disable(msm_dp_display); - pm_runtime_put_sync(&dp->pdev->dev); + msm_dp_display_unprepare(msm_dp_display); } void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) From e923d02527d911b35f28eea3a2a21e3da6d4231f Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:15:50 +0800 Subject: [PATCH 0752/1330] FROMLIST: drm/msm/dp: re-arrange dp_display_disable() into functional parts dp_display_disable() handles special case of when monitor is disconnected from the dongle while the dongle stays connected thereby needing a separate function dp_ctrl_off_link_stream() for this. However with a slight rework this can still be handled by keeping common paths same for regular and special case. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-4-b20518dea8de@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov (cherry picked from commit cd4e6cdc31b91e5a9b2bc1e5c5856fe4ecc593f0) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 19 +------------------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 3 files changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index d2d3f414d5333..a49f90319a19e 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2576,7 +2576,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) return ret; } -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2584,23 +2584,6 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); phy = ctrl->phy; - msm_dp_panel_disable_vsc_sdp(ctrl->panel); - - /* set dongle to D3 (power off) mode */ - msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); - - msm_dp_ctrl_mainlink_disable(ctrl); - - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on = false; - } - - dev_pm_opp_set_rate(ctrl->dev, 0); - msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); - - phy_power_off(phy); - /* aux channel down, reinit phy */ phy_exit(phy); phy_init(phy); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 1497f1a8fc2f0..5d615f50d13bf 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,6 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); @@ -46,4 +45,5 @@ void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index f5c39d6f2bedd..0a375333aaa00 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -720,12 +720,20 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) if (!msm_dp_display->power_on) return 0; + msm_dp_panel_disable_vsc_sdp(dp->panel); + + /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count == 0) { /* * irq_hpd with sink_count = 0 * hdmi unplugged out of dongle */ - msm_dp_ctrl_off_link_stream(dp->ctrl); + + /* set dongle to D3 (power off) mode */ + msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + msm_dp_ctrl_off(dp->ctrl); + /* re-init the PHY so that we can listen to Dongle disconnect */ + msm_dp_ctrl_reinit_phy(dp->ctrl); } else { /* * unplugged interrupt From d1ea7df952f4fe212196ca3b98e702c18c71a7fa Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 25 Aug 2025 22:15:51 +0800 Subject: [PATCH 0753/1330] FROMLIST: drm/msm/dp: splite msm_dp_ctrl_config_ctrl() into link parts and stream parts The DP_CONFIGURATION_CTRL register contains both link-level and stream-specific fields. Currently, msm_dp_ctrl_config_ctrl() configures all of them together. Separates the configuration into link parts and streams part for support MST. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-5-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 6dc5de64e373ae005c0e502996666a4490999e3f) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 43 +++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index a49f90319a19e..fca210bebead9 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -388,26 +388,41 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); } -static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *msm_dp_panel) { u32 config = 0, tbd; + + config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) + config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ + + tbd = msm_dp_link_get_test_bits_depth(ctrl->link, + msm_dp_panel->msm_dp_mode.bpp); + + config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; + + if (msm_dp_panel->psr_cap.version) + config |= DP_CONFIGURATION_CTRL_SEND_VSC; + + drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); + + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); +} + +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) +{ + u32 config = 0; const u8 *dpcd = ctrl->panel->dpcd; /* Default-> LSCLK DIV: 1/4 LCLK */ config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) - config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ - /* Scrambler reset enable */ if (drm_dp_alternate_scrambler_reset_cap(dpcd)) config |= DP_CONFIGURATION_CTRL_ASSR; - tbd = msm_dp_link_get_test_bits_depth(ctrl->link, - ctrl->panel->msm_dp_mode.bpp); - - config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; - /* Num of Lanes */ config |= ((ctrl->link->link_params.num_lanes - 1) << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); @@ -421,10 +436,7 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; - if (ctrl->panel->psr_cap.version) - config |= DP_CONFIGURATION_CTRL_SEND_VSC; - - drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", config); + drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=0x%x\n", config); msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } @@ -450,7 +462,8 @@ static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); - msm_dp_ctrl_config_ctrl(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->panel->msm_dp_mode.bpp); colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); @@ -1628,7 +1641,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, u8 assr; struct msm_dp_link_info link_info = {0}; - msm_dp_ctrl_config_ctrl(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); link_info.num_lanes = ctrl->link->link_params.num_lanes; link_info.rate = ctrl->link->link_params.rate; From d9e672b6ab9b0b7b27e4f29caf41dd8c26816aa3 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 25 Aug 2025 22:15:52 +0800 Subject: [PATCH 0754/1330] FROMLIST: drm/msm/dp: extract MISC1_MISC0 configuration into a separate function Refactor the MISC1_MISC0 register configuration into a standalone helper function to support MST. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-6-b20518dea8de@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov (cherry picked from commit 50cb4636bf503473eabd1fa56aad9f5323276234) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index fca210bebead9..c03f2ba384c6d 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -455,17 +455,13 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) ln_mapping); } -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *msm_dp_panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl_link(ctrl); - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); - - test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->panel->msm_dp_mode.bpp); + test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, + msm_dp_panel->msm_dp_mode.bpp); colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); @@ -479,6 +475,17 @@ static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); +} + +static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) +{ + msm_dp_ctrl_lane_mapping(ctrl); + msm_dp_setup_peripheral_flush(ctrl); + + msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); + + msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); } From 8fa106150f61ee879fe4dda9e8eaf0577c9d4487 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Thu, 2 Apr 2026 19:01:09 +0800 Subject: [PATCH 0755/1330] FROMLIST: drm/msm/dp: split link setup from source params msm_dp_ctrl_configure_source_params() should only handle stream-related configuration. Move the link setup out of it so MST can program link and stream settings separately. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-7-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit b5bd798c5f70454548be3850d8c851648f1f0ae8) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index c03f2ba384c6d..8f1b4e8f0781b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -479,10 +479,6 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) { - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl_link(ctrl); msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); @@ -2571,6 +2567,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) */ reinit_completion(&ctrl->video_comp); + msm_dp_ctrl_lane_mapping(ctrl); + msm_dp_setup_peripheral_flush(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_configure_source_params(ctrl); msm_dp_ctrl_config_msa(ctrl, From 6fe70e31acf88773ea550cb0f947779b6402c4c5 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:15:53 +0800 Subject: [PATCH 0756/1330] FROMLIST: drm/msm/dp: allow dp_ctrl stream APIs to use any panel passed to it Currently, the dp_ctrl stream APIs operate on their own dp_panel which is stored inside the dp_ctrl's private struct. However with MST, the stored panel represents the fixed link and not the sinks which are hotplugged. Allow the stream related APIs to work on the panel which is passed to them rather than the stored one. For SST cases, this shall continue to use the stored dp_panel. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-8-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 4aed13058ab8723098306a07595d5862cd5672c9) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 21 +++++++++++---------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 8f1b4e8f0781b..cd226cfbf40ea 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -477,13 +477,14 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); } -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *msm_dp_panel) { - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); + msm_dp_ctrl_config_ctrl_streams(ctrl, msm_dp_panel); - msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); + msm_dp_ctrl_config_misc1_misc0(ctrl, msm_dp_panel); - msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); + msm_dp_panel_timing_cfg(msm_dp_panel, ctrl->msm_dp_ctrl.wide_bus_en); } /* @@ -2523,7 +2524,7 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_li return ret; } -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel) { int ret = 0; bool mainlink_ready = false; @@ -2536,10 +2537,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate_orig = msm_dp_panel->msm_dp_mode.drm_mode.clock; pixel_rate = pixel_rate_orig; - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) + if (msm_dp_ctrl->wide_bus_en || msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) pixel_rate >>= 1; drm_dbg_dp(ctrl->drm_dev, "pixel_rate=%lu\n", pixel_rate); @@ -2571,14 +2572,14 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) msm_dp_setup_peripheral_flush(ctrl); msm_dp_ctrl_config_ctrl_link(ctrl); - msm_dp_ctrl_configure_source_params(ctrl); + msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); msm_dp_ctrl_config_msa(ctrl, ctrl->link->link_params.rate, pixel_rate_orig, - ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420); - msm_dp_panel_clear_dsc_dto(ctrl->panel); + msm_dp_panel_clear_dsc_dto(msm_dp_panel); msm_dp_ctrl_setup_tr_unit(ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 5d615f50d13bf..32196e97cbe96 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,7 @@ struct msm_dp_ctrl { struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 0a375333aaa00..e3eef11e22407 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -667,7 +667,7 @@ static int msm_dp_display_enable(struct msm_dp_display_private *dp) return 0; } - rc = msm_dp_ctrl_on_stream(dp->ctrl); + rc = msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); if (!rc) msm_dp_display->power_on = true; From 58e4c58da7a7b1b7df86a029383ebf62284a1727 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 25 Aug 2025 22:15:54 +0800 Subject: [PATCH 0757/1330] FROMLIST: drm/msm/dp: move the pixel clock control to its own API Enable/Disable of DP pixel clock happens in multiple code paths leading to code duplication. Move it into individual helpers so that the helpers can be called wherever necessary. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-9-b20518dea8de@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov (cherry picked from commit a41663e9c3ea1a5571e1b926b6bc6e891c2fc6d3) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 79 +++++++++++++++++--------------- 1 file changed, 41 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index cd226cfbf40ea..db36c0401e114 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2176,6 +2176,42 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) return success; } +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate) +{ + int ret; + + ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + if (ret) { + DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); + return ret; + } + + if (ctrl->stream_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); + } else { + ret = clk_prepare_enable(ctrl->pixel_clk); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); + return ret; + } + ctrl->stream_clks_on = true; + } + + return ret; +} + +static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + if (ctrl->stream_clks_on) { + clk_disable_unprepare(ctrl->pixel_clk); + ctrl->stream_clks_on = false; + } +} + static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl) { int ret; @@ -2201,22 +2237,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl } pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; - ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); - return ret; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret = clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); - return ret; - } - ctrl->stream_clks_on = true; - } + ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); msm_dp_ctrl_send_phy_test_pattern(ctrl); @@ -2545,22 +2566,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * drm_dbg_dp(ctrl->drm_dev, "pixel_rate=%lu\n", pixel_rate); - ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); - goto end; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret = clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); - goto end; - } - ctrl->stream_clks_on = true; - } + ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + if (ret) + return ret; /* * Set up transfer unit values and set controller state to send @@ -2593,7 +2601,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * drm_dbg_dp(ctrl->drm_dev, "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); -end: return ret; } @@ -2649,11 +2656,7 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on = false; - } - + msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); From a6dfc38ba547a2636e3502597a8d4a9b5b34d321 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:15:55 +0800 Subject: [PATCH 0758/1330] FROMLIST: drm/msm/dp: split dp_ctrl_off() into stream and link parts Split dp_ctrl_off() into stream and link parts so that for MST cases we can control the link and pixel parts separately. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-10-b20518dea8de@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov (cherry picked from commit 21de468d0148357ee4fb963ba9bc11681972e0e0) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 8 ++++---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 ++- drivers/gpu/drm/msm/dp/dp_display.c | 6 ++++-- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index db36c0401e114..20d08259beaef 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2200,7 +2200,7 @@ static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned l return ret; } -static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -2228,7 +2228,8 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); if (ret) { @@ -2642,7 +2643,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) phy, phy->init_count, phy->power_count); } -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2656,7 +2657,6 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); - msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 32196e97cbe96..b83be2252a9bc 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,8 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index e3eef11e22407..d7b331470fa6d 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -731,7 +731,8 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_link(dp->ctrl); /* re-init the PHY so that we can listen to Dongle disconnect */ msm_dp_ctrl_reinit_phy(dp->ctrl); } else { @@ -739,7 +740,8 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) * unplugged interrupt * dongle unplugged out of DUT */ - msm_dp_ctrl_off(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_link(dp->ctrl); msm_dp_display_host_phy_exit(dp); } From ce7c73024138c83ce592bd03e452cc6128750194 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:15:56 +0800 Subject: [PATCH 0759/1330] FROMLIST: drm/msm/dp: make bridge helpers use dp_display to allow re-use dp_bridge helpers take drm_bridge as an input and extract the dp_display object to be used in the dp_display module. Rather than doing it in a roundabout way, directly pass the dp_display object to these helpers so that the MST bridge can also re-use the same helpers. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-11-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 6fafcda8ea97291d095ddf0453a113318b8ce4c3) --- drivers/gpu/drm/msm/dp/dp_display.c | 29 +++++++-------------- drivers/gpu/drm/msm/dp/dp_display.h | 7 ++++++ drivers/gpu/drm/msm/dp/dp_drm.c | 39 ++++++++++++++++++++++++++++- drivers/gpu/drm/msm/dp/dp_drm.h | 9 ------- 4 files changed, 54 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index d7b331470fa6d..b2b181d6bec15 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -753,24 +753,21 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) /** * msm_dp_bridge_mode_valid - callback to determine if specified mode is valid - * @bridge: Pointer to drm bridge structure + * @dp: Pointer to dp display structure * @info: display info * @mode: Pointer to drm mode structure * Returns: Validity status for specified mode */ -enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode) { const u32 num_components = 3, default_bpp = 24; struct msm_dp_display_private *msm_dp_display; struct msm_dp_link_info *link_info; u32 mode_rate_khz = 0, supported_rate_khz = 0, mode_bpp = 0; - struct msm_dp *dp; int mode_pclk_khz = mode->clock; - dp = to_dp_bridge(bridge)->msm_dp_display; - if (!dp || !mode_pclk_khz || !dp->connector) { DRM_ERROR("invalid params\n"); return -EINVAL; @@ -1421,11 +1418,9 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display, struct drm_device *dev, return 0; } -void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state) { - struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); - struct msm_dp *msm_dp_display = msm_dp_bridge->msm_dp_display; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int rc = 0; @@ -1434,7 +1429,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); crtc = drm_atomic_get_new_crtc_for_encoder(state, - drm_bridge->encoder); + msm_dp_display->bridge->encoder); if (!crtc) return; crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -1464,11 +1459,8 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, drm_dbg_dp(msm_dp_display->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); } -void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); - struct msm_dp *dp = msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); @@ -1485,11 +1477,8 @@ static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) drm_dbg_dp(dp->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); } -void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_post_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); - struct msm_dp *dp = msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 0b65e16c790da..1a697fb305a7d 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -33,5 +33,12 @@ void msm_dp_display_signal_audio_start(struct msm_dp *msm_dp_display); void msm_dp_display_signal_audio_complete(struct msm_dp *msm_dp_display); void msm_dp_display_set_psr(struct msm_dp *dp, bool enter); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct dentry *dentry, bool is_edp); +void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display, + struct drm_atomic_state *state); +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode); #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index af3d3e3a2d841..cb54d7e71f8e6 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -49,6 +49,43 @@ static void msm_dp_bridge_debugfs_init(struct drm_bridge *bridge, struct dentry msm_dp_display_debugfs_init(dp, root, false); } +static void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); + struct msm_dp *dp = dp_bridge->msm_dp_display; + + msm_dp_display_atomic_enable(dp, state); +} + +static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); + struct msm_dp *dp = dp_bridge->msm_dp_display; + + msm_dp_display_atomic_disable(dp); +} + +static void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); + struct msm_dp *dp = dp_bridge->msm_dp_display; + + msm_dp_display_atomic_post_disable(dp); +} + +static enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *drm_bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); + struct msm_dp *dp = dp_bridge->msm_dp_display; + + return msm_dp_display_mode_valid(dp, info, mode); +} + static const struct drm_bridge_funcs msm_dp_bridge_ops = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, @@ -115,7 +152,7 @@ static void msm_edp_bridge_atomic_enable(struct drm_bridge *drm_bridge, return; } - msm_dp_bridge_atomic_enable(drm_bridge, state); + msm_dp_display_atomic_enable(dp, state); } static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h index 6d4cbb9f39182..da412c788503c 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -27,15 +27,6 @@ int msm_dp_bridge_init(struct msm_dp *msm_dp_display, struct drm_device *dev, enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector); -void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state); -void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state); -void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state); -enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode); void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge); void msm_dp_bridge_hpd_disable(struct drm_bridge *bridge); void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, From d6f493dc021d6d1d406de5f8039031701a64ec92 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:15:57 +0800 Subject: [PATCH 0760/1330] FROMLIST: drm/msm/dp: separate dp_display_prepare() into its own API For MST, the link setup should only be done once when multiple sinks are enabled, while stream setup may run multiple times for each sink. Split the link-related preparation out of msm_dp_display_atomic_enable() so it can be called separately before the per-stream enable path. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-12-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit c35a36e5981fe0459178b1463576607ad0b800d1) --- drivers/gpu/drm/msm/dp/dp_display.c | 16 +++++++++++----- drivers/gpu/drm/msm/dp/dp_display.h | 5 +++-- drivers/gpu/drm/msm/dp/dp_drm.c | 6 ++++-- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index b2b181d6bec15..b707200f8fc97 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1418,8 +1418,8 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display, struct drm_device *dev, return 0; } -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, - struct drm_atomic_state *state) +void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -1441,10 +1441,16 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, } rc = msm_dp_display_prepare(dp); - if (rc) { + if (rc) DRM_ERROR("DP display prepare failed, rc=%d\n", rc); - return; - } +} + +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + int rc = 0; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); rc = msm_dp_display_enable(dp); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 1a697fb305a7d..295da7ae00478 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -35,8 +35,9 @@ void msm_dp_display_set_psr(struct msm_dp *dp, bool enter); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct dentry *dentry, bool is_edp); void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); void msm_dp_display_atomic_disable(struct msm_dp *dp_display); -void msm_dp_display_atomic_enable(struct msm_dp *dp_display, - struct drm_atomic_state *state); +void msm_dp_display_atomic_prepare(struct msm_dp *dp_display, + struct drm_atomic_state *state); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display); enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index cb54d7e71f8e6..0feb757e2db90 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -55,7 +55,8 @@ static void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = dp_bridge->msm_dp_display; - msm_dp_display_atomic_enable(dp, state); + msm_dp_display_atomic_prepare(dp, state); + msm_dp_display_atomic_enable(dp); } static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -152,7 +153,8 @@ static void msm_edp_bridge_atomic_enable(struct drm_bridge *drm_bridge, return; } - msm_dp_display_atomic_enable(dp, state); + msm_dp_display_atomic_prepare(dp, state); + msm_dp_display_atomic_enable(dp); } static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, From 734bb743fd3093db2af2611067e992e32ec81514 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Fri, 10 Apr 2026 11:18:58 +0800 Subject: [PATCH 0761/1330] FROMLIST: drm/msm/dp: introduce stream_id for each DP panel With MST, each DP controller can handle multiple streams. There shall be one dp_panel for each stream but the dp_display object shall be shared among them. To represent this abstraction, create a stream_id for each DP panel which shall be set by the MST stream. For SST, default this to stream 0. Use the stream ID to control the pixel clock of that respective stream by extending the clock handles and state tracking of the DP pixel clock to an array of max supported streams. The maximum streams currently is 4. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-13-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 1d1b03ba191218725a1b8ae49682271360b99cdf) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 57 ++++++++++++++++++----------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 24 +++++++++++- drivers/gpu/drm/msm/dp/dp_display.h | 2 + drivers/gpu/drm/msm/dp/dp_panel.h | 11 ++++++ 5 files changed, 71 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 20d08259beaef..76167627d9d17 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -127,7 +127,7 @@ struct msm_dp_ctrl_private { unsigned int num_link_clks; struct clk_bulk_data *link_clks; - struct clk *pixel_clk; + struct clk *pixel_clk[DP_STREAM_MAX]; union phy_configure_opts phy_opts; @@ -139,7 +139,7 @@ struct msm_dp_ctrl_private { bool core_clks_on; bool link_clks_on; - bool stream_clks_on; + bool stream_clks_on[DP_STREAM_MAX]; }; static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) @@ -2176,39 +2176,40 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) return success; } -static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate) +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate, + enum msm_dp_stream_id stream_id) { int ret; - ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + ret = clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); return ret; } - if (ctrl->stream_clks_on) { + if (ctrl->stream_clks_on[stream_id]) { drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); } else { - ret = clk_prepare_enable(ctrl->pixel_clk); + ret = clk_prepare_enable(ctrl->pixel_clk[stream_id]); if (ret) { DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); return ret; } - ctrl->stream_clks_on = true; + ctrl->stream_clks_on[stream_id] = true; } return ret; } -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id) { struct msm_dp_ctrl_private *ctrl; ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on = false; + if (ctrl->stream_clks_on[stream_id]) { + clk_disable_unprepare(ctrl->pixel_clk[stream_id]); + ctrl->stream_clks_on[stream_id] = false; } } @@ -2228,7 +2229,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id); msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); @@ -2238,7 +2239,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl } pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; - ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, ctrl->panel->stream_id); msm_dp_ctrl_send_phy_test_pattern(ctrl); @@ -2525,9 +2526,8 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_li ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes); - drm_dbg_dp(ctrl->drm_dev, - "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", - ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); + drm_dbg_dp(ctrl->drm_dev, "core_clk_on=%d link_clk_on=%d\n", + ctrl->core_clks_on, ctrl->link_clks_on); if (!ctrl->link_clks_on) { /* link clk is off */ ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); @@ -2567,7 +2567,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * drm_dbg_dp(ctrl->drm_dev, "pixel_rate=%lu\n", pixel_rate); - ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, msm_dp_panel->stream_id); if (ret) return ret; @@ -2651,8 +2651,6 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); phy = ctrl->phy; - msm_dp_panel_disable_vsc_sdp(ctrl->panel); - msm_dp_ctrl_mainlink_disable(ctrl); msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); @@ -2724,6 +2722,13 @@ static const char *ctrl_clks[] = { "ctrl_link_iface", }; +static const char * const pixel_clks[] = { + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel", +}; + static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -2757,9 +2762,17 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) if (rc) return rc; - ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); - if (IS_ERR(ctrl->pixel_clk)) - return PTR_ERR(ctrl->pixel_clk); + for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) { + ctrl->pixel_clk[i] = devm_clk_get(dev, pixel_clks[i]); + + if (i == 0 && IS_ERR(ctrl->pixel_clk[i])) + return PTR_ERR(ctrl->pixel_clk[i]); + + if (IS_ERR(ctrl->pixel_clk[i])) { + DRM_DEBUG_DP("stream %d pixel clock not exist", i); + break; + } + } return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index b83be2252a9bc..b9f0705b03ba5 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -20,7 +20,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index b707200f8fc97..4c154d8214683 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -731,7 +731,7 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); msm_dp_ctrl_off_link(dp->ctrl); /* re-init the PHY so that we can listen to Dongle disconnect */ msm_dp_ctrl_reinit_phy(dp->ctrl); @@ -740,7 +740,7 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) * unplugged interrupt * dongle unplugged out of DUT */ - msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); msm_dp_ctrl_off_link(dp->ctrl); msm_dp_display_host_phy_exit(dp); } @@ -751,6 +751,24 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) return 0; } +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, + struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id) +{ + int rc = 0; + struct msm_dp_display_private *dp; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + + if (!dp) { + DRM_ERROR("invalid input\n"); + return -EINVAL; + } + + panel->stream_id = stream_id; + + return rc; +} + /** * msm_dp_bridge_mode_valid - callback to determine if specified mode is valid * @dp: Pointer to dp display structure @@ -1452,6 +1470,8 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0); + rc = msm_dp_display_enable(dp); if (rc) DRM_ERROR("DP display enable failed, rc=%d\n", rc); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 295da7ae00478..a5c6ed5b18e42 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -41,5 +41,7 @@ void msm_dp_display_atomic_enable(struct msm_dp *dp_display); enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, + struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id); #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 53b7b4463551f..21f7f30e6dfd3 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -27,6 +27,15 @@ struct msm_dp_panel_psr { u8 capabilities; }; +/* stream id */ +enum msm_dp_stream_id { + DP_STREAM_0, + DP_STREAM_1, + DP_STREAM_2, + DP_STREAM_3, + DP_STREAM_MAX, +}; + struct msm_dp_panel { /* dpcd raw data */ u8 dpcd[DP_RECEIVER_CAP_SIZE]; @@ -40,6 +49,8 @@ struct msm_dp_panel { bool vsc_sdp_supported; u32 hw_revision; + enum msm_dp_stream_id stream_id; + u32 max_bw_code; }; From 6fd42d836255948406fa4ada5d236869930a0b55 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Fri, 10 Apr 2026 11:33:13 +0800 Subject: [PATCH 0762/1330] FROMLIST: drm/msm/dp: introduce max_streams for DP controller MST support Introduce the `mst_streams` field in each DP controller descriptor to specify the number of supported MST streams. Most platforms support 2 or 4 MST streams, while platforms without MST support default to a single stream (`DEFAULT_STREAM_COUNT = 1`). Also accounts for platforms with asymmetric stream support, e.g., DP0 supporting 4 streams and DP1 supporting 2. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-14-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 26d443b21c72856b5ebc87ece753e842cdd1205e) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 20 +++++++++++++++++--- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 ++ drivers/gpu/drm/msm/dp/dp_display.c | 20 +++++++++++++++++++- drivers/gpu/drm/msm/dp/dp_display.h | 1 + 4 files changed, 39 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 76167627d9d17..5fa1dd65af7bc 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -128,6 +128,7 @@ struct msm_dp_ctrl_private { struct clk_bulk_data *link_clks; struct clk *pixel_clk[DP_STREAM_MAX]; + unsigned int num_pixel_clks; union phy_configure_opts phy_opts; @@ -2729,7 +2730,7 @@ static const char * const pixel_clks[] = { "stream_3_pixel", }; -static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) +static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl, int max_stream) { struct msm_dp_ctrl_private *ctrl; struct device *dev; @@ -2762,7 +2763,8 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) if (rc) return rc; - for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) { + ctrl->num_pixel_clks = 0; + for (i = DP_STREAM_0; i < max_stream; i++) { ctrl->pixel_clk[i] = devm_clk_get(dev, pixel_clks[i]); if (i == 0 && IS_ERR(ctrl->pixel_clk[i])) @@ -2772,14 +2774,26 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) DRM_DEBUG_DP("stream %d pixel clock not exist", i); break; } + + ctrl->num_pixel_clks++; } return 0; } +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + return ctrl->num_pixel_clks; +} + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, + int max_stream, void __iomem *ahb_base, void __iomem *link_base) { @@ -2822,7 +2836,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link ctrl->ahb_base = ahb_base; ctrl->link_base = link_base; - ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); + ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { dev_err(dev, "failed to init clocks\n"); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index b9f0705b03ba5..6fed3ff3a72dc 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -29,6 +29,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, + int max_stream, void __iomem *ahb_base, void __iomem *link_base); @@ -47,4 +48,5 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 4c154d8214683..5d555953f7137 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -87,12 +87,15 @@ struct msm_dp_display_private { void __iomem *p0_base; size_t p0_len; + + int max_stream; }; struct msm_dp_desc { phys_addr_t io_start; unsigned int id; bool wide_bus_supported; + int mst_streams; }; static const struct msm_dp_desc msm_dp_desc_glymur[] = { @@ -568,13 +571,15 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) } dp->ctrl = msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - phy, dp->ahb_base, dp->link_base); + phy, dp->max_stream, dp->ahb_base, dp->link_base); if (IS_ERR(dp->ctrl)) { rc = PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc); dp->ctrl = NULL; goto error_link; } + if (dp->max_stream != msm_dp_ctrl_get_stream_cnt(dp->ctrl)) + dp->max_stream = 1; dp->audio = msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base); if (IS_ERR(dp->audio)) { @@ -1209,6 +1214,15 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) return 0; } +int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + + return dp->max_stream; +} + static int msm_dp_display_probe(struct platform_device *pdev) { int rc = 0; @@ -1235,6 +1249,10 @@ static int msm_dp_display_probe(struct platform_device *pdev) dp->msm_dp_display.is_edp = (dp->msm_dp_display.connector_type == DRM_MODE_CONNECTOR_eDP); dp->hpd_isr_status = 0; + dp->max_stream = 1; + + if (desc->mst_streams > 1) + dp->max_stream = desc->mst_streams; mutex_init(&dp->plugged_lock); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index a5c6ed5b18e42..b0cfdf2159704 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -26,6 +26,7 @@ struct msm_dp { bool psr_supported; }; +int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display); int msm_dp_display_get_modes(struct msm_dp *msm_dp_display); bool msm_dp_display_check_video_test(struct msm_dp *msm_dp_display); int msm_dp_display_get_test_bpp(struct msm_dp *msm_dp_display); From 71a25eb340e121eebdf80e8b7251ffcd727b44c0 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:00 +0800 Subject: [PATCH 0763/1330] FROMLIST: drm/msm/dp: Add support for programming p1/p2/p3 register blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for additional pixel register blocks (p1, p2, p3) to enable 4‑stream MST pixel clocks. Introduce the helper functions msm_dp_read_pn and msm_dp_write_pn for pixel register programming. All pixel clocks share the same register layout but use different base addresses. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-15-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 47eb662a82bf18db1311287b8abde25022886a0a) --- drivers/gpu/drm/msm/dp/dp_display.c | 34 +++++++---- drivers/gpu/drm/msm/dp/dp_panel.c | 89 ++++++++++++++++------------- drivers/gpu/drm/msm/dp/dp_panel.h | 3 +- 3 files changed, 73 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 5d555953f7137..3c8e0980d637b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -85,8 +85,8 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; - void __iomem *p0_base; - size_t p0_len; + void __iomem *pixel_base[DP_STREAM_MAX]; + size_t pixel_len; int max_stream; }; @@ -562,7 +562,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) goto error_link; } - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->p0_base); + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { rc = PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc = %d\n", rc); @@ -770,6 +770,7 @@ int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, } panel->stream_id = stream_id; + msm_dp_panel_set_pixel_base(panel, dp->pixel_base[stream_id]); return rc; } @@ -883,8 +884,8 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, - msm_dp_display->p0_base, "dp_p0"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, + msm_dp_display->pixel_base[0], "dp_p0"); } void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) @@ -1164,6 +1165,7 @@ static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx, size_ static int msm_dp_display_get_io(struct msm_dp_display_private *display) { struct platform_device *pdev = display->msm_dp_display.pdev; + int i; display->ahb_base = msm_dp_ioremap(pdev, 0, &display->ahb_len); if (IS_ERR(display->ahb_base)) @@ -1193,8 +1195,8 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) display->aux_len = DP_DEFAULT_AUX_SIZE; display->link_base = display->ahb_base + DP_DEFAULT_LINK_OFFSET; display->link_len = DP_DEFAULT_LINK_SIZE; - display->p0_base = display->ahb_base + DP_DEFAULT_P0_OFFSET; - display->p0_len = DP_DEFAULT_P0_SIZE; + display->pixel_base[0] = display->ahb_base + DP_DEFAULT_P0_OFFSET; + display->pixel_len = DP_DEFAULT_P0_SIZE; return 0; } @@ -1205,10 +1207,20 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) return PTR_ERR(display->link_base); } - display->p0_base = msm_dp_ioremap(pdev, 3, &display->p0_len); - if (IS_ERR(display->p0_base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); - return PTR_ERR(display->p0_base); + display->pixel_base[0] = msm_dp_ioremap(pdev, 3, &display->pixel_len); + if (IS_ERR(display->pixel_base[0])) { + DRM_ERROR("unable to remap p0 region: %pe\n", display->pixel_base[0]); + return PTR_ERR(display->pixel_base[0]); + } + + for (i = DP_STREAM_1; i < display->max_stream; i++) { + /* pixels clk reg index start from 3*/ + display->pixel_base[i] = msm_dp_ioremap(pdev, i + 3, &display->pixel_len); + if (IS_ERR(display->pixel_base[i])) { + DRM_DEBUG_DP("unable to remap p%d region: %pe\n", i, + display->pixel_base[i]); + break; + } } return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index bde4a772d22c0..c17b87353d1a6 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,7 +25,7 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; - void __iomem *p0_base; + void __iomem *pixel_base; bool panel_on; }; @@ -44,24 +44,24 @@ static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, writel(data, panel->link_base + offset); } -static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, - u32 offset, u32 data) +static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, + u32 offset, u32 data) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->p0_base + offset); + writel(data, panel->pixel_base + offset); } -static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, - u32 offset) +static inline u32 msm_dp_read_pn(struct msm_dp_panel_private *panel, + u32 offset) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(panel->p0_base + offset); + return readl_relaxed(panel->pixel_base + offset); } static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) @@ -367,34 +367,34 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, display_hctl = (hsync_end_x << 16) | hsync_start_x; - msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_pn(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, - DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, - DP_TPG_VIDEO_CONFIG_BPP_8BIT | - DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, - DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, - DP_TIMING_ENGINE_EN_EN); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, + DP_TPG_CHECKERED_RECT_PATTERN); + msm_dp_write_pn(panel, MMSS_DP_TPG_VIDEO_CONFIG, + DP_TPG_VIDEO_CONFIG_BPP_8BIT | + DP_TPG_VIDEO_CONFIG_RGB); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, + DP_BIST_ENABLE_DPBIST_EN); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, + DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); } @@ -403,9 +403,9 @@ static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); } void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) @@ -439,7 +439,7 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_pn(panel, MMSS_DP_DSC_DTO, 0x0); } static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) @@ -629,7 +629,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking); msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); - reg = msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); + reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) reg |= DP_INTF_CONFIG_DATABUS_WIDEN; else @@ -637,7 +637,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", wide_bus_en, reg); - msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_pn(panel, MMSS_DP_INTF_CONFIG, reg); if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); @@ -647,6 +647,13 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) return 0; } +void msm_dp_panel_set_pixel_base(struct msm_dp_panel *msm_dp_panel, void __iomem *pixel_base) +{ + struct msm_dp_panel_private *panel = + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + panel->pixel_base = pixel_base; +} + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) { struct drm_display_mode *drm_mode; @@ -689,7 +696,7 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base) + void __iomem *pixel_base) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; @@ -707,7 +714,7 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux panel->aux = aux; panel->link = link; panel->link_base = link_base; - panel->p0_base = p0_base; + panel->pixel_base = pixel_base; msm_dp_panel = &panel->msm_dp_panel; msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 21f7f30e6dfd3..fe4ac3e47e174 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -66,6 +66,7 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable); void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel); +void msm_dp_panel_set_pixel_base(struct msm_dp_panel *msm_dp_panel, void __iomem *pixel_base); void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp); void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel); @@ -100,5 +101,5 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base); + void __iomem *pixel_base); #endif /* _DP_PANEL_H_ */ From 54fa47a4ca742499a0600d3593d94827f27bfe83 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:01 +0800 Subject: [PATCH 0764/1330] FROMLIST: drm/msm/dp: use stream_id to change offsets in dp_catalog Use the dp_panel's stream_id to adjust the offsets for stream 1 which will be used for MST in the dp_catalog. Stream 1 share the same link clk with stream 0 with different reg offset. Also add additional register defines for stream 1. Streams 2 and 3 are not covered here, as they use separate link clocks and require separate handling. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-16-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 69601a26ddf3e83dd5939fe0423efaf0078202be) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 24 ++++++++--- drivers/gpu/drm/msm/dp/dp_panel.c | 72 ++++++++++++++++++++++--------- drivers/gpu/drm/msm/dp/dp_reg.h | 11 +++++ 3 files changed, 81 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 5fa1dd65af7bc..85dfc343185a0 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -393,6 +393,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, struct msm_dp_panel *msm_dp_panel) { u32 config = 0, tbd; + u32 reg_offset = 0; config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); @@ -409,7 +410,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); + if (msm_dp_panel->stream_id == DP_STREAM_1) + reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; } static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) @@ -460,12 +462,16 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, struct msm_dp_panel *msm_dp_panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; + u32 reg_offset = 0; test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, msm_dp_panel->msm_dp_mode.bpp); colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); - misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); + if (msm_dp_panel->stream_id == DP_STREAM_1) + reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + + misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); /* clear bpp bits */ misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -475,7 +481,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, misc_val |= DP_MISC0_SYNCHRONOUS_CLK; drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); } static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl, @@ -2446,6 +2452,7 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl) } static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *msm_dp_panel, u32 rate, u32 stream_rate_khz, bool is_ycbcr_420) { @@ -2455,6 +2462,12 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, u32 const link_rate_hbr2 = 540000; u32 const link_rate_hbr3 = 810000; unsigned long den, num; + u32 mvid_reg_off = 0, nvid_reg_off = 0; + + if (msm_dp_panel->stream_id == DP_STREAM_1) { + mvid_reg_off = REG_DP1_SOFTWARE_MVID - REG_DP_SOFTWARE_MVID; + nvid_reg_off = REG_DP1_SOFTWARE_NVID - REG_DP_SOFTWARE_NVID; + } switch (rate) { case link_rate_hbr3: @@ -2509,8 +2522,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, nvid *= 3; drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); } int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train) @@ -2585,6 +2598,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); msm_dp_ctrl_config_msa(ctrl, + msm_dp_panel, ctrl->link->link_params.rate, pixel_rate_orig, msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index c17b87353d1a6..6c88cc7e3037f 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -447,27 +447,35 @@ static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct u32 header[2]; u32 val; int i; + u32 offset = 0; + + if (panel->msm_dp_panel.stream_id == DP_STREAM_1) + offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0; msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); } } static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) { u32 hw_revision = panel->msm_dp_panel.hw_revision; + u32 offset = 0; + + if (panel->msm_dp_panel.stream_id == DP_STREAM_1) + offset = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; if (hw_revision >= DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); } } @@ -476,16 +484,25 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); u32 cfg, cfg2, misc; + u32 misc_reg_offset = 0; + u32 sdp_cfg_offset = 0; + u32 sdp_cfg2_offset = 0; + + if (msm_dp_panel->stream_id == DP_STREAM_1) { + misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; + sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; + } - cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG); - cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); - misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0); + cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); cfg |= GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); cfg2 |= GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); @@ -495,7 +512,7 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n"); pr_debug("misc settings = 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); msm_dp_panel_update_sdp(panel); } @@ -505,16 +522,25 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); u32 cfg, cfg2, misc; + u32 misc_reg_offset = 0; + u32 sdp_cfg_offset = 0; + u32 sdp_cfg2_offset = 0; + + if (msm_dp_panel->stream_id == DP_STREAM_1) { + misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; + sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; + } - cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG); - cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); - misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0); + cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); cfg &= ~GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); cfg2 &= ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); /* switch back to MSA */ misc &= ~DP_MISC1_VSC_SDP; @@ -522,7 +548,7 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n"); pr_debug("misc settings = 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); msm_dp_panel_update_sdp(panel); } @@ -580,6 +606,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) u32 msm_dp_active; u32 total; u32 reg; + u32 offset = 0; panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); drm_mode = &panel->msm_dp_panel.msm_dp_mode.drm_mode; @@ -594,6 +621,9 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) drm_mode->vsync_start - drm_mode->vdisplay, drm_mode->vsync_end - drm_mode->vsync_start); + if (msm_dp_panel->stream_id == DP_STREAM_1) + offset = REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER; + total_hor = drm_mode->htotal; total_ver = drm_mode->vtotal; @@ -624,10 +654,10 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) msm_dp_active = data; - msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); - msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking); - msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); + msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start); + msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); + msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 3689642b7fc06..295c1161e6b75 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -332,6 +332,17 @@ #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) +/* DP MST registers */ +#define REG_DP1_CONFIGURATION_CTRL (0x00000400) +#define REG_DP1_SOFTWARE_MVID (0x00000414) +#define REG_DP1_SOFTWARE_NVID (0x00000418) +#define REG_DP1_TOTAL_HOR_VER (0x0000041C) +#define REG_DP1_MISC1_MISC0 (0x0000042C) +#define MMSS_DP1_GENERIC0_0 (0x00000490) +#define MMSS_DP1_SDP_CFG (0x000004E0) +#define MMSS_DP1_SDP_CFG2 (0x000004E4) +#define MMSS_DP1_SDP_CFG3 (0x000004E8) + #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) From 44b3fd092007cd168506e33cc6c76ee9d05eafc3 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 25 Aug 2025 22:16:02 +0800 Subject: [PATCH 0765/1330] FROMLIST: drm/msm/dp: Add catalog support for 3rd/4th stream MST To support 4-stream MST, the link clocks for stream 3 and stream 4 are controlled by MST_2_LCLK and MST_3_LCLK which share the same register definitions but use different base addresses. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-17-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 77bb6ddd464666ffdb6eb897405ac4ddc64d3b03) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 225 +++++++++++++++++----------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 24 ++- drivers/gpu/drm/msm/dp/dp_panel.c | 135 +++++++++++++---- drivers/gpu/drm/msm/dp/dp_panel.h | 2 + drivers/gpu/drm/msm/dp/dp_reg.h | 16 +- 6 files changed, 283 insertions(+), 123 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 85dfc343185a0..93928a550ebdd 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -118,6 +118,8 @@ struct msm_dp_ctrl_private { struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; struct phy *phy; @@ -158,19 +160,45 @@ static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl, writel(data, ctrl->ahb_base + offset); } -static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 offset) +static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 offset) { - return readl_relaxed(ctrl->link_base + offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(ctrl->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(ctrl->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(ctrl->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } } static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, - u32 offset, u32 data) + enum msm_dp_stream_id stream_id, u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, ctrl->link_base + offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, ctrl->link_base + offset); + break; + case DP_STREAM_2: + writel(data, ctrl->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, ctrl->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } } static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, @@ -294,18 +322,18 @@ static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ctrl) { u32 val; - val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + val = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); val |= DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, val); } static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *ctrl) { u32 val; - val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + val = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); val &= ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, val); } static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) @@ -314,21 +342,21 @@ static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "enable\n"); - mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); mainlink_ctrl &= ~(DP_MAINLINK_CTRL_RESET | DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl |= DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl &= ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl |= (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) @@ -337,23 +365,23 @@ static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "disable\n"); - mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) { u32 mainlink_ctrl; - mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); if (ctrl->hw_revision >= DP_HW_VERSION_1_2) mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; else mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) @@ -380,7 +408,7 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); reinit_completion(&ctrl->idle_comp); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -395,7 +423,11 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, u32 config = 0, tbd; u32 reg_offset = 0; - config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + if (msm_dp_panel->stream_id == DP_STREAM_0) + config = msm_dp_read_link(ctrl, 0, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->stream_id == DP_STREAM_1) + reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ @@ -410,8 +442,10 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); - if (msm_dp_panel->stream_id == DP_STREAM_1) - reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_CONFIGURATION_CTRL : + REG_DP_CONFIGURATION_CTRL + reg_offset, config); + } static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) @@ -441,7 +475,7 @@ static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=0x%x\n", config); - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); + msm_dp_write_link(ctrl, 0, REG_DP_CONFIGURATION_CTRL, config); } static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) @@ -454,8 +488,8 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) ln_mapping |= lane_map[2] << LANE2_MAPPING_SHIFT; ln_mapping |= lane_map[3] << LANE3_MAPPING_SHIFT; - msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, - ln_mapping); + msm_dp_write_link(ctrl, 0, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + ln_mapping); } static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, @@ -471,7 +505,8 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, if (msm_dp_panel->stream_id == DP_STREAM_1) reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; - misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); + misc_val = msm_dp_read_link(ctrl, msm_dp_panel->stream_id, msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + reg_offset); /* clear bpp bits */ misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -481,7 +516,10 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, misc_val |= DP_MISC0_SYNCHRONOUS_CLK; drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + reg_offset, + misc_val); } static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl, @@ -1307,9 +1345,9 @@ static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", msm_dp_tu, valid_boundary, valid_boundary2); - msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2); + msm_dp_write_link(ctrl, 0, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(ctrl, 0, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(ctrl, 0, REG_DP_VALID_BOUNDARY_2, valid_boundary2); } static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) @@ -1426,7 +1464,7 @@ static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *ctrl, bit = BIT(state_bit - 1); drm_dbg_dp(ctrl->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, bit); bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; @@ -1453,7 +1491,7 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, delay_us = drm_dp_read_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); *training_step = DP_TRAINING_1; @@ -1577,7 +1615,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); *training_step = DP_TRAINING_2; @@ -1694,7 +1732,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, } end: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); return ret; } @@ -1840,34 +1878,34 @@ static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl) static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) { /* trigger sdp */ - msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(ctrl, 0, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(ctrl, 0, MMSS_DP_SDP_CFG3, 0x0); } static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) { u32 cmd; - cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); + cmd = msm_dp_read_link(ctrl, 0, REG_PSR_CMD); cmd &= ~(PSR_ENTER | PSR_EXIT); cmd |= PSR_ENTER; msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, 0, REG_PSR_CMD, cmd); } static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) { u32 cmd; - cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); + cmd = msm_dp_read_link(ctrl, 0, REG_PSR_CMD); cmd &= ~(PSR_ENTER | PSR_EXIT); cmd |= PSR_EXIT; msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, 0, REG_PSR_CMD, cmd); } void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) @@ -1880,9 +1918,9 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) return; /* enable PSR1 function */ - cfg = msm_dp_read_link(ctrl, REG_PSR_CONFIG); + cfg = msm_dp_read_link(ctrl, 0, REG_PSR_CONFIG); cfg |= PSR1_SUPPORTED; - msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg); + msm_dp_write_link(ctrl, 0, REG_PSR_CONFIG, cfg); msm_dp_ctrl_config_psr_interrupt(ctrl); msm_dp_ctrl_enable_sdp(ctrl); @@ -1921,16 +1959,16 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter) } msm_dp_ctrl_push_idle(msm_dp_ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); msm_dp_ctrl_psr_mainlink_disable(ctrl); } else { msm_dp_ctrl_psr_mainlink_enable(ctrl); msm_dp_ctrl_psr_exit(ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); msm_dp_ctrl_wait4video_ready(ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); } } @@ -2041,7 +2079,7 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); ret = msm_dp_ctrl_wait4video_ready(ctrl); end: @@ -2056,72 +2094,72 @@ static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, u32 value = 0x0; /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0x0); drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN1); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN1); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: value &= ~(1 << 16); - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); value |= SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); break; case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_PRBS7); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, - 0x3E0F83E0); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + 0x3E0F83E0); /* 00001111100000111110000011111000 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, - 0x0F83E0F8); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + 0x0F83E0F8); /* 1111100000111110 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, - 0x0000F83E); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + 0x0000F83E); break; case DP_PHY_TEST_PATTERN_CP2520: - value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + value = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); value &= ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, value); value = DP_HBR2_ERM_PATTERN; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); value |= SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + value = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); value |= DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, value); break; case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN4); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, + DP_MAINLINK_CTRL_ENABLE); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; default: @@ -2149,7 +2187,7 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); msm_dp_link_send_test_response(ctrl->link); - pattern_sent = msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY); + pattern_sent = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_READY); switch (pattern_sent) { case MR_LINK_TRAINING1: @@ -2522,8 +2560,14 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, nvid *= 3; drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_MSTLINK_SOFTWARE_MVID : REG_DP_SOFTWARE_MVID + mvid_reg_off, + mvid); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_MSTLINK_SOFTWARE_NVID : REG_DP_SOFTWARE_NVID + nvid_reg_off, + nvid); } int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train) @@ -2593,7 +2637,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); - msm_dp_ctrl_config_ctrl_link(ctrl); + if (msm_dp_panel->stream_id == DP_STREAM_0) + msm_dp_ctrl_config_ctrl_link(ctrl); msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); @@ -2607,7 +2652,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_ctrl_setup_tr_unit(ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); ret = msm_dp_ctrl_wait4video_ready(ctrl); if (ret) @@ -2809,7 +2854,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base) + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base) { struct msm_dp_ctrl_private *ctrl; int ret; @@ -2849,6 +2896,8 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link ctrl->phy = phy; ctrl->ahb_base = ahb_base; ctrl->link_base = link_base; + ctrl->mst2link_base = mst2link_base; + ctrl->mst3link_base = mst3link_base; ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 6fed3ff3a72dc..e72d501ac1ce8 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -31,7 +31,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base); + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base); void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 3c8e0980d637b..16f4f727dc466 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -85,6 +85,12 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; + void __iomem *mst2link_base; + size_t mst2link_len; + + void __iomem *mst3link_base; + size_t mst3link_len; + void __iomem *pixel_base[DP_STREAM_MAX]; size_t pixel_len; @@ -562,7 +568,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) goto error_link; } - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]); + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, + dp->mst2link_base, dp->mst3link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { rc = PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc = %d\n", rc); @@ -571,7 +578,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) } dp->ctrl = msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - phy, dp->max_stream, dp->ahb_base, dp->link_base); + phy, dp->max_stream, dp->ahb_base, + dp->link_base, dp->mst2link_base, dp->mst3link_base); if (IS_ERR(dp->ctrl)) { rc = PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc); @@ -884,6 +892,10 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst2link_len, + msm_dp_display->mst2link_base, "dp_mst2link"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst3link_len, + msm_dp_display->mst3link_base, "dp_mst3link"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, msm_dp_display->pixel_base[0], "dp_p0"); } @@ -1223,6 +1235,14 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) } } + display->mst2link_base = msm_dp_ioremap(pdev, 7, &display->mst2link_len); + if (IS_ERR(display->mst2link_base)) + DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst2link_base); + + display->mst3link_base = msm_dp_ioremap(pdev, 8, &display->mst3link_len); + if (IS_ERR(display->mst3link_base)) + DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst3link_base); + return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 6c88cc7e3037f..a8a6297b37e3e 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,23 +25,50 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; void __iomem *pixel_base; bool panel_on; }; static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32 offset) { - return readl_relaxed(panel->link_base + offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(panel->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(panel->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(panel->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } } static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, - u32 offset, u32 data) + u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->link_base + offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, panel->link_base + offset); + break; + case DP_STREAM_2: + writel(data, panel->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, panel->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } } static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, @@ -444,38 +471,51 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) { + u32 id = panel->msm_dp_panel.stream_id; u32 header[2]; u32 val; int i; u32 offset = 0; - if (panel->msm_dp_panel.stream_id == DP_STREAM_1) + if (id == DP_STREAM_1) offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0; msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_0 : MMSS_DP_GENERIC0_0 + offset, + header[0]); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_1 : MMSS_DP_GENERIC0_1 + offset, + header[1]); for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_2 + i : MMSS_DP_GENERIC0_2 + i + offset, + val); } } static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) { + u32 id = panel->msm_dp_panel.stream_id; u32 hw_revision = panel->msm_dp_panel.hw_revision; u32 offset = 0; - if (panel->msm_dp_panel.stream_id == DP_STREAM_1) + if (id == DP_STREAM_1) offset = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; if (hw_revision >= DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG3 : MMSS_DP_SDP_CFG3 + offset, + UPDATE_SDP); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG3 : MMSS_DP_SDP_CFG3 + offset, + 0x0); } } @@ -483,26 +523,34 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd { struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + u32 id = msm_dp_panel->stream_id; u32 cfg, cfg2, misc; u32 misc_reg_offset = 0; u32 sdp_cfg_offset = 0; u32 sdp_cfg2_offset = 0; - if (msm_dp_panel->stream_id == DP_STREAM_1) { + if (id == DP_STREAM_1) { misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } - cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + cfg = msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 = msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc = msm_dp_read_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset); cfg |= GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - cfg2 |= GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset, + cfg); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, + cfg2); msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); @@ -512,7 +560,9 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n"); pr_debug("misc settings = 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); + msm_dp_write_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset, + misc); msm_dp_panel_update_sdp(panel); } @@ -521,26 +571,34 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) { struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + u32 id = msm_dp_panel->stream_id; u32 cfg, cfg2, misc; u32 misc_reg_offset = 0; u32 sdp_cfg_offset = 0; u32 sdp_cfg2_offset = 0; - if (msm_dp_panel->stream_id == DP_STREAM_1) { + if (id == DP_STREAM_1) { misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } - cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + cfg = msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 = msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc = msm_dp_read_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset); cfg &= ~GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - cfg2 &= ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset, + cfg); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, + cfg2); /* switch back to MSA */ misc &= ~DP_MISC1_VSC_SDP; @@ -548,7 +606,9 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n"); pr_debug("misc settings = 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); + msm_dp_write_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset, + misc); msm_dp_panel_update_sdp(panel); } @@ -598,6 +658,7 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) { + u32 id = msm_dp_panel->stream_id; u32 data, total_ver, total_hor; struct msm_dp_panel_private *panel; struct drm_display_mode *drm_mode; @@ -621,7 +682,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) drm_mode->vsync_start - drm_mode->vdisplay, drm_mode->vsync_end - drm_mode->vsync_start); - if (msm_dp_panel->stream_id == DP_STREAM_1) + if (id == DP_STREAM_1) offset = REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER; total_hor = drm_mode->htotal; @@ -654,10 +715,18 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) msm_dp_active = data; - msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); - msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start); - msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); - msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_TOTAL_HOR_VER : + REG_DP_TOTAL_HOR_VER + offset, total); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC : + REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY : + REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_ACTIVE_HOR_VER : + REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) @@ -726,6 +795,8 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base, void __iomem *pixel_base) { struct msm_dp_panel_private *panel; @@ -745,6 +816,8 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux panel->link = link; panel->link_base = link_base; panel->pixel_base = pixel_base; + panel->mst2link_base = mst2link_base; + panel->mst3link_base = mst3link_base; msm_dp_panel = &panel->msm_dp_panel; msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index fe4ac3e47e174..4873c55bd6935 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -101,5 +101,7 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base, void __iomem *pixel_base); #endif /* _DP_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 295c1161e6b75..1c2d3d8d029d5 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -162,7 +162,6 @@ #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) #define REG_DP_ACTIVE_HOR_VER (0x00000028) - #define REG_DP_MISC1_MISC0 (0x0000002C) #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) @@ -343,6 +342,21 @@ #define MMSS_DP1_SDP_CFG2 (0x000004E4) #define MMSS_DP1_SDP_CFG3 (0x000004E8) +#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) +#define REG_MSTLINK_SOFTWARE_MVID (0x00000040) +#define REG_MSTLINK_SOFTWARE_NVID (0x00000044) +#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) +#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004C) +#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050) +#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054) +#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058) +#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000BC) +#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000C0) +#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000C4) +#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c) +#define MMSS_DP_MSTLINK_SDP_CFG2 (0x0000011c) +#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114) + #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) From 9660c4e77a740c8dddf8b2c019bfaa95e174e998 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:03 +0800 Subject: [PATCH 0766/1330] FROMLIST: drm/msm/dp: add support to send ACT packets for MST Whenever virtual channel slot allocation changes, the DP source must send the action control trigger sequence to notify the sink about the same. This would be applicable during the start and stop of the pixel stream. Add the infrastructure to be able to send ACT packets for the DP controller when operating in MST mode. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-18-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 091b8da2b696c09ff5ff059eaedae153b6e2e14c) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 43 +++++++++++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 3 +- drivers/gpu/drm/msm/dp/dp_display.h | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ 5 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 93928a550ebdd..7ab5853e3d1d1 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -143,6 +143,7 @@ struct msm_dp_ctrl_private { bool core_clks_on; bool link_clks_on; bool stream_clks_on[DP_STREAM_MAX]; + bool mst_active; }; static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) @@ -228,6 +229,32 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, return err; } +int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + bool act_complete; + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + if (!ctrl->mst_active) + return 0; + + msm_dp_write_link(ctrl, 0, REG_DP_MST_ACT, 0x1); + /* make sure ACT signal is performed */ + wmb(); + + msleep(20); /* needs 1 frame time */ + + act_complete = msm_dp_read_link(ctrl, 0, REG_DP_MST_ACT); + + if (!act_complete) { + drm_dbg_dp(ctrl->drm_dev, "MST ACT trigger complete failed\n"); + return 0; + } + + return 0; +} + /* * NOTE: resetting DP controller will also clear any pending HPD related interrupts */ @@ -2081,6 +2108,10 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + ret = msm_dp_ctrl_mst_send_act(&ctrl->msm_dp_ctrl); + if (ret) + return ret; + ret = msm_dp_ctrl_wait4video_ready(ctrl); end: return ret; @@ -2277,7 +2308,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id); msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); - ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); + ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, false); if (ret) { DRM_ERROR("failed to enable DP link controller\n"); return ret; @@ -2357,7 +2388,7 @@ static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_ctrl_private *ctrl) return drm_dp_channel_eq_ok(link_status, num_lanes); } -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active) { int rc = 0; struct msm_dp_ctrl_private *ctrl; @@ -2375,6 +2406,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl) rate = ctrl->panel->link_info.rate; pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; + ctrl->mst_active = mst_active; msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); @@ -2654,6 +2686,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + ret = msm_dp_ctrl_mst_send_act(msm_dp_ctrl); + if (ret) + return ret; + ret = msm_dp_ctrl_wait4video_ready(ctrl); if (ret) return ret; @@ -2715,6 +2751,8 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); + ctrl->mst_active = false; + dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); @@ -2898,6 +2936,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link ctrl->link_base = link_base; ctrl->mst2link_base = mst2link_base; ctrl->mst3link_base = mst3link_base; + ctrl->mst_active = false; ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index e72d501ac1ce8..f82fd96e412a7 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -16,7 +16,7 @@ struct msm_dp_ctrl { struct phy; -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); @@ -51,4 +51,5 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); +int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 16f4f727dc466..b16b9535d832a 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -661,7 +661,7 @@ static int msm_dp_display_prepare(struct msm_dp_display_private *dp) force_link_train = true; } - rc = msm_dp_ctrl_on_link(dp->ctrl); + rc = msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active); if (rc) DRM_ERROR("Failed link training (rc=%d)\n", rc); // TODO: schedule drm_connector_set_link_status_property() @@ -1542,6 +1542,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *dp) msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); msm_dp_ctrl_push_idle(msm_dp_display->ctrl); + msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl); } static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index b0cfdf2159704..fdbe6e4871d98 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -19,6 +19,7 @@ struct msm_dp { struct drm_bridge *bridge; bool audio_enabled; bool power_on; + bool mst_active; unsigned int connector_type; bool is_edp; diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 1c2d3d8d029d5..237325d52dbd2 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -156,6 +156,8 @@ #define DP_CONFIGURATION_CTRL_BPC_SHIFT (0x08) #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT (0x0D) +#define REG_DP_MST_ACT (0x00000500) + #define REG_DP_SOFTWARE_MVID (0x00000010) #define REG_DP_SOFTWARE_NVID (0x00000018) #define REG_DP_TOTAL_HOR_VER (0x0000001C) From 0356f670d40b5a1923ee0793ec37b9d5ab583f2c Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:04 +0800 Subject: [PATCH 0767/1330] FROMLIST: drm/msm/dp: Add support to enable MST in mainlink control Add support to program the MST enable bit in the mainlink control register when an MST session is active or being disabled. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-19-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 77209eeca75d25cf90f851b99795276196a7b311) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/dp/dp_reg.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 7ab5853e3d1d1..27fb5930d85d1 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -255,6 +255,19 @@ int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl) return 0; } +static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool enable) +{ + u32 mainlink_ctrl; + + mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + if (enable) + mainlink_ctrl |= DP_MAINLINK_CTRL_MST_EN; + else + mainlink_ctrl &= ~DP_MAINLINK_CTRL_MST_EN; + + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related interrupts */ @@ -2669,6 +2682,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); + if (ctrl->mst_active) + msm_dp_ctrl_mst_config(ctrl, true); + if (msm_dp_panel->stream_id == DP_STREAM_0) msm_dp_ctrl_config_ctrl_link(ctrl); @@ -2748,6 +2764,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) phy = ctrl->phy; msm_dp_ctrl_mainlink_disable(ctrl); + msm_dp_ctrl_mst_config(ctrl, false); msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 237325d52dbd2..87eaaefa014dd 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -128,6 +128,10 @@ #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1) #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) +#define DP_MAINLINK_CTRL_ECF_MODE BIT(26) +#define DP_MAINLINK_CTRL_MST_ACTIVE BIT(8) +#define DP_MAINLINK_CTRL_MST_EN (DP_MAINLINK_CTRL_ECF_MODE | \ + DP_MAINLINK_CTRL_MST_ACTIVE) #define REG_DP_STATE_CTRL (0x00000004) #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) From 2cf85e72c57a7b443584b60d19caef9addf10b86 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:05 +0800 Subject: [PATCH 0768/1330] FROMLIST: drm/msm/dp: no need to update tu calculation for mst DP stream is transmitted in transfer units only for SST case, there is no need to calculate and program TU parameters for MST case. Skip the TU programming for MST cases. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-20-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 74c4ce56c2c931ad4146c0e6fa1d3e027cfbd13b) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 27fb5930d85d1..8315aeb452229 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2698,7 +2698,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_panel_clear_dsc_dto(msm_dp_panel); - msm_dp_ctrl_setup_tr_unit(ctrl); + if (!ctrl->mst_active) + msm_dp_ctrl_setup_tr_unit(ctrl); msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); From 09ea3f863fb4d7e146e9b4f89f458b27f8c8b26e Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:06 +0800 Subject: [PATCH 0769/1330] FROMLIST: drm/msm/dp: Add support for MST channel slot allocation DP MST streams share 64 MTP slots in a time-multiplexed manner. This patch adds support for calculating the rate governor, slot allocation, and slot reservation in the DP controller. Each MST stream can reserve its slots by calling dp_display_set_stream_info() from its bridge callbacks. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-21-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit d98aec1f6504844e545b73c60577a0450ec91ff2) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 207 ++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 7 +- drivers/gpu/drm/msm/dp/dp_display.c | 28 ++-- drivers/gpu/drm/msm/dp/dp_display.h | 5 +- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 10 ++ 6 files changed, 247 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 8315aeb452229..167021595fa88 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -73,6 +73,7 @@ #define MR_LINK_PRBS7 0x100 #define MR_LINK_CUSTOM80 0x200 #define MR_LINK_TRAINING4 0x40 +#define DP_MAX_TIME_SLOTS 64 enum { DP_TRAINING_NONE, @@ -109,6 +110,11 @@ struct msm_dp_vc_tu_mapping_table { u8 tu_size_minus1; }; +struct msm_dp_mst_ch_slot_info { + u32 start_slot; + u32 tot_slots; +}; + struct msm_dp_ctrl_private { struct msm_dp_ctrl msm_dp_ctrl; struct drm_device *drm_dev; @@ -144,6 +150,8 @@ struct msm_dp_ctrl_private { bool link_clks_on; bool stream_clks_on[DP_STREAM_MAX]; bool mst_active; + + struct msm_dp_mst_ch_slot_info mst_ch_info[DP_STREAM_MAX]; }; static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) @@ -268,6 +276,73 @@ static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool enable msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } +static void msm_dp_ctrl_mst_channel_alloc(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 ch_start_slot, + u32 tot_slot_cnt) +{ + u32 i, slot; + u32 slot_reg_1, slot_reg_2; + u32 reg_off = 0; + int const num_slots_per_reg = 32; + + if (ch_start_slot > DP_MAX_TIME_SLOTS || + (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) { + DRM_ERROR("invalid slots start %d, tot %d\n", + ch_start_slot, tot_slot_cnt); + return; + } + + drm_dbg_dp(ctrl->drm_dev, "stream_id %d, start_slot %d, tot_slot %d\n", + stream_id, ch_start_slot, tot_slot_cnt); + + if (stream_id == DP_STREAM_1) + reg_off = REG_DP_DP1_TIMESLOT_1_32 - REG_DP_DP0_TIMESLOT_1_32; + + slot_reg_1 = 0; + slot_reg_2 = 0; + + if (ch_start_slot && tot_slot_cnt) { + ch_start_slot--; + for (i = 0; i < tot_slot_cnt; i++) { + if (ch_start_slot < num_slots_per_reg) { + slot_reg_1 |= BIT(ch_start_slot); + } else { + slot = ch_start_slot - num_slots_per_reg; + slot_reg_2 |= BIT(slot); + } + ch_start_slot++; + } + } + + drm_dbg_dp(ctrl->drm_dev, "stream_id:%d slot_reg_1:%d, slot_reg_2:%d\n", stream_id, + slot_reg_1, slot_reg_2); + + msm_dp_write_link(ctrl, stream_id, stream_id > DP_STREAM_1 ? + REG_DP_MSTLINK_TIMESLOT_1_32 : REG_DP_DP0_TIMESLOT_1_32 + reg_off, + slot_reg_1); + msm_dp_write_link(ctrl, stream_id, stream_id > DP_STREAM_1 ? + REG_DP_MSTLINK_TIMESLOT_33_63 : REG_DP_DP0_TIMESLOT_33_63 + reg_off, + slot_reg_2); +} + +static void msm_dp_ctrl_update_rg(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 x_int, u32 y_frac_enum) +{ + u32 rg, reg_off = 0; + + rg = y_frac_enum; + rg |= (x_int << 16); + + drm_dbg_dp(ctrl->drm_dev, "stream_id: %d x_int:%d y_frac_enum:%d rg:%d\n", + stream_id, x_int, y_frac_enum, rg); + + if (stream_id == DP_STREAM_1) + reg_off = REG_DP_DP1_RG - REG_DP_DP0_RG; + + msm_dp_write_link(ctrl, stream_id, stream_id > 1 ? + REG_DP_MSTLINK_DP_RG : REG_DP_DP0_RG + reg_off, rg); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related interrupts */ @@ -2615,6 +2690,103 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, nvid); } +/* TODO: comments here. */ +static void msm_dp_ctrl_mst_calculate_rg(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, + u32 *p_x_int, u32 *p_y_frac_enum) +{ + u64 min_slot_cnt, max_slot_cnt; + u64 raw_target_sc, target_sc_fixp; + u64 ts_denom, ts_enum, ts_int; + u64 pclk = panel->msm_dp_mode.drm_mode.clock; + u64 lclk = 0; + u64 lanes = ctrl->link->link_params.num_lanes; + u64 bpp = panel->msm_dp_mode.bpp; + u64 pbn = panel->pbn; + u64 numerator, denominator, temp, temp1, temp2; + u32 x_int = 0, y_frac_enum = 0; + u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp; + + lclk = ctrl->link->link_params.rate; + + /* min_slot_cnt */ + numerator = pclk * bpp * 64 * 1000; + denominator = lclk * lanes * 8 * 1000; + min_slot_cnt = drm_fixp_from_fraction(numerator, denominator); + + /* max_slot_cnt */ + numerator = pbn * 54 * 1000; + denominator = lclk * lanes; + max_slot_cnt = drm_fixp_from_fraction(numerator, denominator); + + /* raw_target_sc */ + numerator = max_slot_cnt + min_slot_cnt; + denominator = drm_fixp_from_fraction(2, 1); + raw_target_sc = drm_fixp_div(numerator, denominator); + + /* target_sc */ + temp = drm_fixp_from_fraction(256 * lanes, 1); + numerator = drm_fixp_mul(raw_target_sc, temp); + denominator = drm_fixp_from_fraction(256 * lanes, 1); + target_sc_fixp = drm_fixp_div(numerator, denominator); + + ts_enum = 256 * lanes; + ts_denom = drm_fixp_from_fraction(256 * lanes, 1); + ts_int = drm_fixp2int(target_sc_fixp); + + temp = drm_fixp2int_ceil(raw_target_sc); + if (temp != ts_int) { + temp = drm_fixp_from_fraction(ts_int, 1); + temp1 = raw_target_sc - temp; + temp2 = drm_fixp_mul(temp1, ts_denom); + ts_enum = drm_fixp2int(temp2); + } + + /* target_strm_sym */ + ts_int_fixp = drm_fixp_from_fraction(ts_int, 1); + ts_frac_fixp = drm_fixp_from_fraction(ts_enum, drm_fixp2int(ts_denom)); + temp = ts_int_fixp + ts_frac_fixp; + temp1 = drm_fixp_from_fraction(lanes, 1); + target_strm_sym = drm_fixp_mul(temp, temp1); + + /* x_int */ + x_int = drm_fixp2int(target_strm_sym); + + /* y_enum_frac */ + temp = drm_fixp_from_fraction(x_int, 1); + temp1 = target_strm_sym - temp; + temp2 = drm_fixp_from_fraction(256, 1); + y_frac_enum_fixp = drm_fixp_mul(temp1, temp2); + + temp1 = drm_fixp2int(y_frac_enum_fixp); + temp2 = drm_fixp2int_ceil(y_frac_enum_fixp); + + y_frac_enum = (u32)((temp1 == temp2) ? temp1 : temp1 + 1); + + *p_x_int = x_int; + *p_y_frac_enum = y_frac_enum; + + drm_dbg_dp(ctrl->drm_dev, "MST lane_cnt:%llu, rate:%llu x_int:%d, y_frac:%d\n", + lanes, lclk, x_int, y_frac_enum); +} + +static void msm_dp_ctrl_mst_stream_setup(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) +{ + u32 x_int, y_frac_enum; + + if (!ctrl->mst_active) + return; + + drm_dbg_dp(ctrl->drm_dev, "MST stream channel allocation\n"); + + msm_dp_ctrl_mst_stream_channel_slot_setup(&ctrl->msm_dp_ctrl); + + msm_dp_ctrl_mst_calculate_rg(ctrl, panel, &x_int, &y_frac_enum); + + msm_dp_ctrl_update_rg(ctrl, panel->stream_id, x_int, y_frac_enum); +} + int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train) { int ret = 0; @@ -2701,6 +2873,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * if (!ctrl->mst_active) msm_dp_ctrl_setup_tr_unit(ctrl); + msm_dp_ctrl_mst_stream_setup(ctrl, msm_dp_panel); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); ret = msm_dp_ctrl_mst_send_act(msm_dp_ctrl); @@ -2779,6 +2953,39 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) phy, phy->init_count, phy->power_count); } +void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 tot_slots) +{ + struct msm_dp_ctrl_private *ctrl; + + if (!msm_dp_ctrl || stream_id >= DP_STREAM_MAX) { + DRM_ERROR("invalid input\n"); + return; + } + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + ctrl->mst_ch_info[stream_id].start_slot = start_slot; + ctrl->mst_ch_info[stream_id].tot_slots = tot_slots; +} + +void msm_dp_ctrl_mst_stream_channel_slot_setup(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + int i; + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + if (!ctrl->mst_active) + return; + + for (i = DP_STREAM_0; i < ctrl->num_pixel_clks; i++) { + msm_dp_ctrl_mst_channel_alloc(ctrl, i, ctrl->mst_ch_info[i].start_slot, + ctrl->mst_ch_info[i].tot_slots); + } +} + irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index f82fd96e412a7..c59338199399c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id); @@ -52,4 +53,8 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_mst_stream_channel_slot_setup(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 tot_slots); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index b16b9535d832a..84915560bf1c3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -764,11 +764,13 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) return 0; } -int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, - struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id) +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct msm_dp_panel *panel, + enum msm_dp_stream_id stream_id, u32 start_slot, + u32 num_slots, u32 pbn) { int rc = 0; struct msm_dp_display_private *dp; + const int max_slots = 64; dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); @@ -777,7 +779,16 @@ int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, return -EINVAL; } + if (start_slot + num_slots > max_slots) { + DRM_ERROR("invalid channel info received. start:%d, slots:%d\n", + start_slot, num_slots); + return -EINVAL; + } + + msm_dp_ctrl_set_mst_channel_info(dp->ctrl, stream_id, start_slot, num_slots); + panel->stream_id = stream_id; + panel->pbn = pbn; msm_dp_panel_set_pixel_base(panel, dp->pixel_base[stream_id]); return rc; @@ -1520,7 +1531,7 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0); + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0); rc = msm_dp_display_enable(dp); if (rc) @@ -1535,14 +1546,15 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) drm_dbg_dp(msm_dp_display->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); } -void msm_dp_display_atomic_disable(struct msm_dp *dp) +void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) { - struct msm_dp_display_private *msm_dp_display; + struct msm_dp_display_private *dp; - msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - msm_dp_ctrl_push_idle(msm_dp_display->ctrl); - msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl); + msm_dp_ctrl_push_idle(dp->ctrl); + msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl); + msm_dp_ctrl_mst_send_act(dp->ctrl); } static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index fdbe6e4871d98..0ccdddb223c8e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -43,7 +43,8 @@ void msm_dp_display_atomic_enable(struct msm_dp *dp_display); enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); -int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, - struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id); +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct msm_dp_panel *panel, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 num_slots, u32 pbn); #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 4873c55bd6935..8e7374de90ebc 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,7 @@ struct msm_dp_panel { u32 hw_revision; enum msm_dp_stream_id stream_id; + u32 pbn; u32 max_bw_code; }; diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 87eaaefa014dd..835a55446868e 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -338,7 +338,13 @@ #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) /* DP MST registers */ + +#define REG_DP_MSTLINK_DP_RG (0X0000011C) #define REG_DP1_CONFIGURATION_CTRL (0x00000400) +#define REG_DP_DP0_TIMESLOT_1_32 (0x00000404) +#define REG_DP_DP0_TIMESLOT_33_63 (0x00000408) +#define REG_DP_DP1_TIMESLOT_1_32 (0x0000040C) +#define REG_DP_DP1_TIMESLOT_33_63 (0x00000410) #define REG_DP1_SOFTWARE_MVID (0x00000414) #define REG_DP1_SOFTWARE_NVID (0x00000418) #define REG_DP1_TOTAL_HOR_VER (0x0000041C) @@ -347,8 +353,12 @@ #define MMSS_DP1_SDP_CFG (0x000004E0) #define MMSS_DP1_SDP_CFG2 (0x000004E4) #define MMSS_DP1_SDP_CFG3 (0x000004E8) +#define REG_DP_DP0_RG (0x000004F8) +#define REG_DP_DP1_RG (0x000004FC) #define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) +#define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) +#define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003C) #define REG_MSTLINK_SOFTWARE_MVID (0x00000040) #define REG_MSTLINK_SOFTWARE_NVID (0x00000044) #define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) From 5745e6a3d9cf82722f394e1c41af5306f6b45f49 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:07 +0800 Subject: [PATCH 0770/1330] FROMLIST: drm/msm/dp: Add support for sending VCPF packets in DP controller The VC Payload Fill (VCPF) sequence is inserted by the DP controller when stream symbols are absent, typically before a stream is disabled. This patch adds support for triggering the VCPF sequence in the MSM DP controller. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-22-b20518dea8de@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov (cherry picked from commit 491646d2998807021b8535a8710d1894cd8dc256) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 55 ++++++++++++++++++++++++++--- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- drivers/gpu/drm/msm/dp/dp_reg.h | 5 +++ 4 files changed, 58 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 167021595fa88..0f756148abe0f 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -65,9 +65,18 @@ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) +#define DP_INTERRUPT_STATUS5 \ + (DP_INTR_DP0_VCPF_SENT | DP_INTR_DP1_VCPF_SENT) +#define DP_INTERRUPT_STATUS5_MASK \ + (DP_INTERRUPT_STATUS5 << DP_INTERRUPT_STATUS_MASK_SHIFT) + #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) +#define DP_DP0_PUSH_VCPF BIT(12) +#define DP_DP1_PUSH_VCPF BIT(14) +#define DP_MSTLINK_PUSH_VCPF BIT(12) + #define MR_LINK_TRAINING1 0x8 #define MR_LINK_SYMBOL_ERM 0x80 #define MR_LINK_PRBS7 0x100 @@ -405,6 +414,8 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl) DP_INTERRUPT_STATUS1_MASK); msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, DP_INTERRUPT_STATUS2_MASK); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, + DP_INTERRUPT_STATUS5_MASK); } void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl) @@ -414,6 +425,7 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl) msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00); msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, 0x00); } static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) @@ -433,6 +445,20 @@ static void msm_dp_ctrl_config_psr_interrupt(struct msm_dp_ctrl_private *ctrl) msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); } +static u32 msm_dp_ctrl_get_mst_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + u32 intr, intr_ack; + + intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS5); + intr &= ~DP_INTERRUPT_STATUS5_MASK; + intr_ack = (intr & DP_INTERRUPT_STATUS5) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, + intr_ack | DP_INTERRUPT_STATUS5_MASK); + + return intr; +} + static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ctrl) { u32 val; @@ -516,14 +542,28 @@ static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) return true; } -void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel) { struct msm_dp_ctrl_private *ctrl; + u32 state = 0x0; ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + if (!ctrl->mst_active) + state |= DP_STATE_CTRL_PUSH_IDLE; + else if (msm_dp_panel->stream_id == DP_STREAM_0) + state |= DP_DP0_PUSH_VCPF; + else if (msm_dp_panel->stream_id == DP_STREAM_1) + state |= DP_DP1_PUSH_VCPF; + else + state |= DP_MSTLINK_PUSH_VCPF; + reinit_completion(&ctrl->idle_comp); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); + + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_STATE_CTRL : REG_DP_STATE_CTRL, + state); if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -2073,7 +2113,7 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter) return; } - msm_dp_ctrl_push_idle(msm_dp_ctrl); + msm_dp_ctrl_push_idle(msm_dp_ctrl, ctrl->panel); msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); msm_dp_ctrl_psr_mainlink_disable(ctrl); @@ -2183,7 +2223,7 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) int ret = 0; int training_step = DP_TRAINING_NONE; - msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl, ctrl->panel); ctrl->link->phy_params.p_level = 0; ctrl->link->phy_params.v_level = 0; @@ -3027,6 +3067,13 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl) ret = IRQ_HANDLED; } + isr = msm_dp_ctrl_get_mst_interrupt(ctrl); + if (isr & (DP_INTR_DP0_VCPF_SENT | DP_INTR_DP1_VCPF_SENT)) { + drm_dbg_dp(ctrl->drm_dev, "vcpf sent\n"); + complete(&ctrl->idle_comp); + ret = IRQ_HANDLED; + } + /* DP aux isr */ isr = msm_dp_ctrl_get_aux_interrupt(ctrl); if (isr) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index c59338199399c..cfe7e44969437 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -22,7 +22,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id); -void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 84915560bf1c3..65b460b4a3ca7 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1552,7 +1552,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - msm_dp_ctrl_push_idle(dp->ctrl); + msm_dp_ctrl_push_idle(dp->ctrl, dp->panel); msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl); msm_dp_ctrl_mst_send_act(dp->ctrl); } diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 835a55446868e..65695fcb48d0f 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -42,9 +42,13 @@ #define DP_INTR_FRAME_END BIT(6) #define DP_INTR_CRC_UPDATED BIT(9) +#define DP_INTR_DP0_VCPF_SENT BIT(0) +#define DP_INTR_DP1_VCPF_SENT BIT(3) + #define REG_DP_INTR_STATUS3 (0x00000028) #define REG_DP_INTR_STATUS4 (0x0000002C) +#define REG_DP_INTR_STATUS5 (0x00000034) #define PSR_UPDATE_INT (0x00000001) #define PSR_CAPTURE_INT (0x00000004) #define PSR_EXIT_INT (0x00000010) @@ -356,6 +360,7 @@ #define REG_DP_DP0_RG (0x000004F8) #define REG_DP_DP1_RG (0x000004FC) +#define REG_DP_MSTLINK_STATE_CTRL (0x00000000) #define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) #define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) #define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003C) From 87310e883e26ce748dc63841327f87d260208a09 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:08 +0800 Subject: [PATCH 0771/1330] FROMLIST: drm/msm/dp: Always program MST_FIFO_CONSTANT_FILL for MST use cases As per the hardware programming guide, MST_FIFO_CONSTANT_FILL must always be programmed when operating in MST mode. This patch ensures the register is configured accordingly. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-23-b20518dea8de@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov (cherry picked from commit 6cf1bd2dbcb71f50b0a1172697eea79806f8c345) --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 12 ++++++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 0f756148abe0f..84238721ab548 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -685,6 +685,8 @@ static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl msm_dp_ctrl_config_misc1_misc0(ctrl, msm_dp_panel); msm_dp_panel_timing_cfg(msm_dp_panel, ctrl->msm_dp_ctrl.wide_bus_en); + + msm_dp_panel_mst_async_fifo(msm_dp_panel, ctrl->mst_active); } /* diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index a8a6297b37e3e..e05d96f33c433 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -753,6 +753,18 @@ void msm_dp_panel_set_pixel_base(struct msm_dp_panel *msm_dp_panel, void __iomem panel->pixel_base = pixel_base; } +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool mst_en) +{ + struct msm_dp_panel_private *panel; + + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + + if (mst_en) + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); + else + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); +} + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) { struct drm_display_mode *drm_mode; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 8e7374de90ebc..8bab27520439c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -72,6 +72,8 @@ void msm_dp_panel_set_pixel_base(struct msm_dp_panel *msm_dp_panel, void __iomem void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp); void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel); +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool mst_en); + /** * is_link_rate_valid() - validates the link rate * @bw_code: link rate requested by the sink From 0bde848a04adc6fa25e172b17402dbc49cfda78a Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Sat, 4 Apr 2026 15:00:08 +0800 Subject: [PATCH 0772/1330] FROMLIST: drm/msm/dp: simplify link and clock disable sequence Move the common disable steps out of the sink_count check to make the flow easier to follow. No functional change intended. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-24-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 6ce77512dacf736166537d59a93d858162a32f4f) --- drivers/gpu/drm/msm/dp/dp_display.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 65b460b4a3ca7..217db6a7fe898 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -735,28 +735,19 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp) msm_dp_panel_disable_vsc_sdp(dp->panel); - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count == 0) { - /* - * irq_hpd with sink_count = 0 - * hdmi unplugged out of dongle - */ + msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); - /* set dongle to D3 (power off) mode */ + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count == 0) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); - msm_dp_ctrl_off_link(dp->ctrl); + + msm_dp_ctrl_off_link(dp->ctrl); + + if (dp->link->sink_count == 0) /* re-init the PHY so that we can listen to Dongle disconnect */ msm_dp_ctrl_reinit_phy(dp->ctrl); - } else { - /* - * unplugged interrupt - * dongle unplugged out of DUT - */ - msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); - msm_dp_ctrl_off_link(dp->ctrl); + else msm_dp_display_host_phy_exit(dp); - } msm_dp_display->power_on = false; From 272ce8defb9a02044e42a107cf378685968772fd Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Sat, 4 Apr 2026 15:21:46 +0800 Subject: [PATCH 0773/1330] FROMLIST: drm/msm/dp: pass panel to display enable/disable helpers Pass struct msm_dp_panel to the display enable/disable helpers to make them easier to reuse for MST stream handling. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-25-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit d0d281a3e54ca59e8436a707f473a8ba30418cac) --- drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 217db6a7fe898..21d9aeaf5b0ee 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -669,7 +669,8 @@ static int msm_dp_display_prepare(struct msm_dp_display_private *dp) return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); } -static int msm_dp_display_enable(struct msm_dp_display_private *dp) +static int msm_dp_display_enable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { int rc = 0; struct msm_dp *msm_dp_display = &dp->msm_dp_display; @@ -726,20 +727,21 @@ static void msm_dp_display_audio_notify_disable(struct msm_dp_display_private *d msm_dp_display->audio_enabled = false; } -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static int msm_dp_display_disable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp *msm_dp_display = &dp->msm_dp_display; if (!msm_dp_display->power_on) return 0; - msm_dp_panel_disable_vsc_sdp(dp->panel); + msm_dp_panel_disable_vsc_sdp(msm_dp_panel); - msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count == 0) - msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + msm_dp_link_psm_config(dp->link, &msm_dp_panel->link_info, true); msm_dp_ctrl_off_link(dp->ctrl); @@ -1524,14 +1526,14 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0); - rc = msm_dp_display_enable(dp); + rc = msm_dp_display_enable(dp, dp->panel); if (rc) DRM_ERROR("DP display enable failed, rc=%d\n", rc); rc = msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=%d\n", rc); - msm_dp_display_disable(dp); + msm_dp_display_disable(dp, dp->panel); } drm_dbg_dp(msm_dp_display->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); @@ -1568,7 +1570,7 @@ void msm_dp_display_atomic_post_disable(struct msm_dp *dp) msm_dp_display_audio_notify_disable(msm_dp_display); - msm_dp_display_disable(msm_dp_display); + msm_dp_display_disable(msm_dp_display, msm_dp_display->panel); msm_dp_display_unprepare(msm_dp_display); } From 5f9ebfc936aabcde60db61f35667ee23eac74d0e Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:09 +0800 Subject: [PATCH 0774/1330] FROMLIST: drm/msm/dp: abstract out the dp_display stream helpers to accept a panel Currently the dp_display bridge helpers, in particular the dp_display_enable()/dp_display_disable() use the cached panel. To be able to re-use these helpers for MST use-case abstract the helpers to use the panel which is passed in to them. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-26-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit c51784e2d0dc687e1160c1892b654598d078967f) --- drivers/gpu/drm/msm/dp/dp_display.c | 117 +++++++++++++++++++--------- drivers/gpu/drm/msm/dp/dp_display.h | 12 +++ 2 files changed, 91 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 21d9aeaf5b0ee..6813103d6e084 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -636,12 +636,14 @@ static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, return 0; } -static int msm_dp_display_prepare(struct msm_dp_display_private *dp) +int msm_dp_display_prepare(struct msm_dp *msm_dp_display) { - struct msm_dp *msm_dp_display = &dp->msm_dp_display; + struct msm_dp_display_private *dp; int rc = 0; bool force_link_train = false; + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + drm_dbg_dp(dp->drm_dev, "sink_count=%d\n", dp->link->sink_count); if (msm_dp_display->is_edp) @@ -681,7 +683,7 @@ static int msm_dp_display_enable(struct msm_dp_display_private *dp, return 0; } - rc = msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); + rc = msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel); if (!rc) msm_dp_display->power_on = true; @@ -739,18 +741,6 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp, msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count == 0) - msm_dp_link_psm_config(dp->link, &msm_dp_panel->link_info, true); - - msm_dp_ctrl_off_link(dp->ctrl); - - if (dp->link->sink_count == 0) - /* re-init the PHY so that we can listen to Dongle disconnect */ - msm_dp_ctrl_reinit_phy(dp->ctrl); - else - msm_dp_display_host_phy_exit(dp); - msm_dp_display->power_on = false; drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); @@ -1490,76 +1480,116 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display, struct drm_device *dev, return 0; } -void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display, - struct drm_atomic_state *state) +int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state, + struct drm_encoder *drm_encoder, + struct msm_dp_panel *msm_dp_panel) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; + + crtc = drm_atomic_get_new_crtc_for_encoder(state, drm_encoder); + if (!crtc) + return 0; + crtc_state = drm_atomic_get_new_crtc_state(state, crtc); + + return msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode, msm_dp_panel); +} + +void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state) +{ int rc = 0; struct msm_dp_display_private *dp; dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - crtc = drm_atomic_get_new_crtc_for_encoder(state, - msm_dp_display->bridge->encoder); - if (!crtc) - return; - crtc_state = drm_atomic_get_new_crtc_state(state, crtc); - - rc = msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode, dp->panel); + rc = msm_dp_display_set_mode_helper(msm_dp_display, state, + msm_dp_display->bridge->encoder, dp->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=%d\n", rc); return; } - rc = msm_dp_display_prepare(dp); + rc = msm_dp_display_prepare(msm_dp_display); if (rc) DRM_ERROR("DP display prepare failed, rc=%d\n", rc); } -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +void msm_dp_display_enable_helper(struct msm_dp *msm_dp_display, struct msm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *dp; int rc = 0; dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0); - - rc = msm_dp_display_enable(dp, dp->panel); + rc = msm_dp_display_enable(dp, msm_dp_panel); if (rc) DRM_ERROR("DP display enable failed, rc=%d\n", rc); rc = msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=%d\n", rc); - msm_dp_display_disable(dp, dp->panel); + msm_dp_display_disable(dp, msm_dp_panel); } drm_dbg_dp(msm_dp_display->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); } -void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) { struct msm_dp_display_private *dp; dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - msm_dp_ctrl_push_idle(dp->ctrl, dp->panel); + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0); + + msm_dp_display_enable_helper(msm_dp_display, dp->panel); +} + +void msm_dp_display_disable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_display_private *dp; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + + msm_dp_ctrl_push_idle(dp->ctrl, msm_dp_panel); msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl); msm_dp_ctrl_mst_send_act(dp->ctrl); } -static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) { - struct msm_dp *msm_dp_display = &dp->msm_dp_display; + struct msm_dp_display_private *dp; - pm_runtime_put_sync(&msm_dp_display->pdev->dev); + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + + msm_dp_display_disable_helper(msm_dp_display, dp->panel); +} + +void msm_dp_display_unprepare(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - drm_dbg_dp(dp->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count == 0) + msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + + msm_dp_ctrl_off_link(dp->ctrl); + + /* re-init the PHY so that we can listen to Dongle disconnect */ + if (dp->link->sink_count == 0) + msm_dp_ctrl_reinit_phy(dp->ctrl); + else + msm_dp_display_host_phy_exit(dp); + + pm_runtime_put_sync(&msm_dp_display->pdev->dev); } -void msm_dp_display_atomic_post_disable(struct msm_dp *dp) +void msm_dp_display_atomic_post_disable_helper(struct msm_dp *dp, struct msm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *msm_dp_display; @@ -1570,7 +1600,18 @@ void msm_dp_display_atomic_post_disable(struct msm_dp *dp) msm_dp_display_audio_notify_disable(msm_dp_display); - msm_dp_display_disable(msm_dp_display, msm_dp_display->panel); + msm_dp_display_disable(msm_dp_display, msm_dp_panel); + + drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type); +} + +void msm_dp_display_atomic_post_disable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + + msm_dp_display_atomic_post_disable_helper(msm_dp_display, dp->panel); msm_dp_display_unprepare(msm_dp_display); } diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 0ccdddb223c8e..0ede5505be589 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -46,5 +46,17 @@ enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id, u32 start_slot, u32 num_slots, u32 pbn); +void msm_dp_display_enable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel); +void msm_dp_display_disable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel); +void msm_dp_display_atomic_post_disable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel); +int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, + struct drm_atomic_state *state, + struct drm_encoder *drm_encoder, + struct msm_dp_panel *msm_dp_panel); +int msm_dp_display_prepare(struct msm_dp *msm_dp_display); +void msm_dp_display_unprepare(struct msm_dp *dp); #endif /* _DP_DISPLAY_H_ */ From a03a69f1e44c8d7267905f5352f4c74b9d7ef4ca Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:10 +0800 Subject: [PATCH 0775/1330] FROMLIST: drm/msm/dp: replace power_on with active_stream_cnt for dp_display For DP MST, the link clock and power domain resources stay on until both streams have been disabled OR we receive hotplug. Introduce an active_stream_cnt to track the number of active streams and necessary state handling. Replace the power_on variable with active_stream_cnt as power_on boolean works only for a single stream. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-27-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 623aff0132670ee1629abc39144b8aae60db0991) --- drivers/gpu/drm/msm/dp/dp_audio.c | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 38 +++++++++++++++-------------- drivers/gpu/drm/msm/dp/dp_display.h | 2 +- 3 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_audio.c index 41018e82efa10..035e230201fd9 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -284,7 +284,7 @@ int msm_dp_audio_prepare(struct drm_bridge *bridge, * such cases check for connection status and bail out if not * connected. */ - if (!msm_dp_display->power_on) { + if (!msm_dp_display->active_stream_cnt) { rc = -EINVAL; goto end; } diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 6813103d6e084..25334349fb084 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -658,15 +658,15 @@ int msm_dp_display_prepare(struct msm_dp *msm_dp_display) if (dp->link->sink_count == 0) return rc; - if (!msm_dp_display->power_on) { + if (!msm_dp_display->active_stream_cnt) { msm_dp_display_host_phy_init(dp); force_link_train = true; - } - rc = msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active); - if (rc) - DRM_ERROR("Failed link training (rc=%d)\n", rc); - // TODO: schedule drm_connector_set_link_status_property() + rc = msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active); + if (rc) + DRM_ERROR("Failed link training (rc=%d)\n", rc); + // TODO: schedule drm_connector_set_link_status_property() + } return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); } @@ -675,18 +675,12 @@ static int msm_dp_display_enable(struct msm_dp_display_private *dp, struct msm_dp_panel *msm_dp_panel) { int rc = 0; - struct msm_dp *msm_dp_display = &dp->msm_dp_display; drm_dbg_dp(dp->drm_dev, "sink_count=%d\n", dp->link->sink_count); - if (msm_dp_display->power_on) { - drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); - return 0; - } rc = msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel); - if (!rc) - msm_dp_display->power_on = true; + dp->msm_dp_display.active_stream_cnt++; return rc; } @@ -732,16 +726,14 @@ static void msm_dp_display_audio_notify_disable(struct msm_dp_display_private *d static int msm_dp_display_disable(struct msm_dp_display_private *dp, struct msm_dp_panel *msm_dp_panel) { - struct msm_dp *msm_dp_display = &dp->msm_dp_display; - - if (!msm_dp_display->power_on) + if (!dp->msm_dp_display.active_stream_cnt) return 0; msm_dp_panel_disable_vsc_sdp(msm_dp_panel); msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); - msm_dp_display->power_on = false; + dp->msm_dp_display.active_stream_cnt--; drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); return 0; @@ -877,7 +869,7 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) * power_on status before dumping DP registers to avoid crash due * to unclocked access */ - if (!dp->power_on) + if (!dp->active_stream_cnt) return; msm_disp_snapshot_add_block(disp_state, msm_dp_display->ahb_len, @@ -1554,6 +1546,11 @@ void msm_dp_display_disable_helper(struct msm_dp *msm_dp_display, dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + if (!msm_dp_display->active_stream_cnt) { + drm_dbg_dp(dp->drm_dev, "no active streams\n"); + return; + } + msm_dp_ctrl_push_idle(dp->ctrl, msm_dp_panel); msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl); msm_dp_ctrl_mst_send_act(dp->ctrl); @@ -1574,6 +1571,11 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + if (msm_dp_display->active_stream_cnt) { + drm_dbg_dp(dp->drm_dev, "stream still active, return\n"); + return; + } + /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count == 0) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 0ede5505be589..2548f67cd441e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -18,7 +18,7 @@ struct msm_dp { struct drm_bridge *next_bridge; struct drm_bridge *bridge; bool audio_enabled; - bool power_on; + u32 active_stream_cnt; bool mst_active; unsigned int connector_type; bool is_edp; From e165d8dd547365c267e23e2230798e56da7d4b6a Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:11 +0800 Subject: [PATCH 0776/1330] FROMLIST: drm/msm/dp: Mark the SST bridge disconnected when mst is active The bridge detect function is only applicable for SST. In MST mode, connector detection is handled by MST bridges. This patch skips detection for the SST bridge when MST is active. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov (cherry picked from commit 40f8e5dc86fc734fd6b56e59a7a0852e9b8996d7) --- drivers/gpu/drm/msm/dp/dp_display.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 25334349fb084..1d98957424d22 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -921,6 +921,9 @@ enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, priv = container_of(dp, struct msm_dp_display_private, msm_dp_display); + if (dp->mst_active) + return status; + mutex_lock(&priv->plugged_lock); ret = pm_runtime_resume_and_get(&dp->pdev->dev); if (ret) { @@ -967,6 +970,8 @@ enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, status = connector_status_disconnected; } + if (priv->max_stream > 1 && drm_dp_read_mst_cap(priv->aux, dpcd)) + status = connector_status_disconnected; end: /* * If we detected the DPRX, leave the controller on so that it doesn't From 2bcabb842f84f38632d848cd97f810d13c52f674 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:12 +0800 Subject: [PATCH 0777/1330] FROMLIST: drm/msm/dp: add an API to initialize MST on sink side If the DP controller is capable of supporting multiple streams then initialize the DP sink in MST mode by programming the DP_MSTM_CTRL DPCD register to enable MST mode. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-29-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit ea8c3f4f4f644732066d028687c6453dced86e19) --- drivers/gpu/drm/msm/dp/dp_display.c | 57 +++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 1d98957424d22..3533b61435ba3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "msm_drv.h" @@ -271,6 +272,40 @@ static int msm_dp_display_lttpr_init(struct msm_dp_display_private *dp, u8 *dpcd return lttpr_count; } +static void msm_dp_display_mst_init(struct msm_dp_display_private *dp) +{ + const unsigned long clear_mstm_ctrl_timeout_us = 100000; + u8 old_mstm_ctrl; + struct msm_dp *msm_dp = &dp->msm_dp_display; + int ret; + + /* clear sink MST state */ + drm_dp_dpcd_read_byte(dp->aux, DP_MSTM_CTRL, &old_mstm_ctrl); + + ret = drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, 0); + if (ret < 0) { + DRM_ERROR("failed to clear DP_MSTM_CTRL, ret=%d\n", ret); + return; + } + + /* add extra delay if MST old state is on*/ + if (old_mstm_ctrl) { + drm_dbg_dp(dp->drm_dev, "wait %luus to set DP_MSTM_CTRL set 0\n", + clear_mstm_ctrl_timeout_us); + usleep_range(clear_mstm_ctrl_timeout_us, + clear_mstm_ctrl_timeout_us + 1000); + } + + ret = drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); + if (ret < 0) { + DRM_ERROR("sink MST enablement failed\n"); + return; + } + + msm_dp->mst_active = true; +} + static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) { struct drm_connector *connector = dp->msm_dp_display.connector; @@ -289,14 +324,19 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) if (rc) goto end; - drm_edid = drm_edid_read_ddc(connector, &dp->aux->ddc); - drm_edid_connector_update(connector, drm_edid); + if (!(dp->max_stream > 1) || !drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd)) { + drm_edid = drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); - if (!drm_edid) { - DRM_ERROR("panel edid read failed\n"); - /* check edid read fail is due to unplug */ - if (!msm_dp_aux_is_link_connected(dp->aux)) - return -ETIMEDOUT; + if (!drm_edid) { + DRM_ERROR("panel edid read failed\n"); + /* check edid read fail is due to unplug */ + if (!msm_dp_aux_is_link_connected(dp->aux)) + return -ETIMEDOUT; + } + + if (rc) + goto end; } msm_dp_link_process_request(dp->link); @@ -318,6 +358,9 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, false); + if (dp->max_stream > 1 && drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd)) + msm_dp_display_mst_init(dp); + msm_dp_link_reset_phy_params_vx_px(dp->link); end: From 7991087e8cffb36eca12e58116454964b9b56d21 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:13 +0800 Subject: [PATCH 0778/1330] FROMLIST: drm/msm/dp: add dp_display_get_panel() to initialize DP panel Add an API dp_display_get_panel() to initialize and return a DP panel to be used by DP MST module. Since some of the fields of DP panel are private, dp_display module needs to initialize these parts and return the panel back. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-30-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 1a002c01f97b09f7e1d320c8315259dee197c588) --- drivers/gpu/drm/msm/dp/dp_display.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 3533b61435ba3..ae3d2cb71b7be 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -572,6 +572,30 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp) return rc; } +struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + struct msm_dp_panel *dp_panel; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + + dp_panel = msm_dp_panel_get(&dp->msm_dp_display.pdev->dev, dp->aux, dp->link, + dp->link_base, dp->mst2link_base, dp->mst3link_base, + dp->pixel_base[0]); + + if (IS_ERR(dp->panel)) { + DRM_ERROR("failed to initialize panel\n"); + return NULL; + } + + /* FIXME: move out of panel */ + memcpy(dp_panel->dpcd, dp->panel->dpcd, DP_RECEIVER_CAP_SIZE); + memcpy(&dp_panel->link_info, &dp->panel->link_info, + sizeof(dp->panel->link_info)); + + return dp_panel; +} + static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_private *dp) { msm_dp_audio_put(dp->audio); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 2548f67cd441e..5f3ef295d7109 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -59,4 +59,5 @@ int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, int msm_dp_display_prepare(struct msm_dp *msm_dp_display); void msm_dp_display_unprepare(struct msm_dp *dp); +struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_display); #endif /* _DP_DISPLAY_H_ */ From 6a7cd16fcb80fce2e10c1958c9c8e611c82392f2 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Thu, 2 Apr 2026 12:02:11 +0800 Subject: [PATCH 0779/1330] FROMLIST: drm/msm/dp: add prepared to manage link-level operations In MST mode, multiple streams share the same DP link. Track a prepared state so msm_dp_display_prepare() runs only once per link and repeated calls are skipped. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-31-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit f6d1caa809e6ef60f2dbd5ea70db6ada887a1df0) --- drivers/gpu/drm/msm/dp/dp_display.c | 34 ++++++++++++++++++++++------- drivers/gpu/drm/msm/dp/dp_display.h | 1 + 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index ae3d2cb71b7be..0d3985e0da9f6 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -716,6 +716,11 @@ int msm_dp_display_prepare(struct msm_dp *msm_dp_display) if (msm_dp_display->is_edp) msm_dp_hpd_plug_handle(dp); + if (msm_dp_display->prepared) { + drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); + return 0; + } + rc = pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); if (rc) { DRM_ERROR("failed to pm_runtime_resume\n"); @@ -735,7 +740,11 @@ int msm_dp_display_prepare(struct msm_dp *msm_dp_display) // TODO: schedule drm_connector_set_link_status_property() } - return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); + rc = msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); + if (!rc) + msm_dp_display->prepared = true; + + return rc; } static int msm_dp_display_enable(struct msm_dp_display_private *dp, @@ -1587,14 +1596,16 @@ void msm_dp_display_enable_helper(struct msm_dp *msm_dp_display, struct msm_dp_p dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - rc = msm_dp_display_enable(dp, msm_dp_panel); - if (rc) - DRM_ERROR("DP display enable failed, rc=%d\n", rc); + if (msm_dp_display->prepared) { + rc = msm_dp_display_enable(dp, msm_dp_panel); + if (rc) + DRM_ERROR("DP display enable failed, rc=%d\n", rc); - rc = msm_dp_display_post_enable(msm_dp_display); - if (rc) { - DRM_ERROR("DP display post enable failed, rc=%d\n", rc); - msm_dp_display_disable(dp, msm_dp_panel); + rc = msm_dp_display_post_enable(msm_dp_display); + if (rc) { + DRM_ERROR("DP display post enable failed, rc=%d\n", rc); + msm_dp_display_disable(dp, msm_dp_panel); + } } drm_dbg_dp(msm_dp_display->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); @@ -1643,6 +1654,11 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + if (!msm_dp_display->prepared) { + drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); + return; + } + if (msm_dp_display->active_stream_cnt) { drm_dbg_dp(dp->drm_dev, "stream still active, return\n"); return; @@ -1661,6 +1677,8 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_display) msm_dp_display_host_phy_exit(dp); pm_runtime_put_sync(&msm_dp_display->pdev->dev); + + msm_dp_display->prepared = false; } void msm_dp_display_atomic_post_disable_helper(struct msm_dp *dp, struct msm_dp_panel *msm_dp_panel) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 5f3ef295d7109..bda76319c4596 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -22,6 +22,7 @@ struct msm_dp { bool mst_active; unsigned int connector_type; bool is_edp; + bool prepared; struct msm_dp_audio *msm_dp_audio; bool psr_supported; From 67119ec9e1ddd279bf0e4a0b1add4cc0e7cbfe6b Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Sun, 5 Apr 2026 18:07:11 +0800 Subject: [PATCH 0780/1330] FROMLIST: drm/msm/dpu: initialize encoders per stream for DP MST Simply initialize MST encoders for MST-capable DP controllers, and introduce msm_dp_get_mst_max_stream to query MST streams. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-32-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 3db9c62c0b848ffbdb7553483025444de853f367) --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 14 +++++++++++++- drivers/gpu/drm/msm/msm_drv.h | 7 ++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 014b2c504eda6..0346efd802340 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -653,7 +653,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, struct msm_display_info info; bool yuv_supported; int rc; - int i; + int i, stream_id, stream_cnt; for (i = 0; i < ARRAY_SIZE(priv->kms->dp); i++) { if (!priv->kms->dp[i]) @@ -676,6 +676,18 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); return rc; } + + stream_cnt = msm_dp_get_mst_max_stream(priv->kms->dp[i]); + + if (stream_cnt > 1) { + for (stream_id = 0; stream_id < stream_cnt; stream_id++) { + encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); + if (IS_ERR(encoder)) { + DPU_ERROR("encoder init failed for dp mst display\n"); + return PTR_ERR(encoder); + } + } + } } return 0; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 617b3c4b42c0c..9fac9e039c31c 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -355,7 +355,7 @@ bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); - +int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); #else static inline int __init msm_dp_register(void) { @@ -372,6 +372,11 @@ static inline int msm_dp_modeset_init(struct msm_dp *dp_display, return -EINVAL; } +static inline int msm_dp_get_mst_max_stream(struct msm_dp *dp_display) +{ + return -EINVAL; +} + static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) { } From 2d9d4d22b695077e774226c3a1365fdd841c1ed1 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:21 +0800 Subject: [PATCH 0781/1330] FROMLIST: drm/msm/dp: initialize dp_mst module for each DP MST controller For each MST capable DP controller, initialize a dp_mst module to manage its DP MST operations. The DP MST module for each controller is the central entity to manage its topology related operations as well as interfacing with the rest of the DP driver. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-33-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 34ef5deec98e549fd466f69fffdd84a46e81e002) --- drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 ++ drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++++ drivers/gpu/drm/msm/dp/dp_display.h | 2 + drivers/gpu/drm/msm/dp/dp_mst_drm.c | 73 +++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 13 +++++ drivers/gpu/drm/msm/msm_drv.h | 6 ++ 7 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/msm/dp/dp_mst_drm.c create mode 100644 drivers/gpu/drm/msm/dp/dp_mst_drm.h diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 8b94c5f1cb68e..1d8426876aa1c 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -144,7 +144,8 @@ msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ dp/dp_link.o \ dp/dp_panel.o \ dp/dp_audio.o \ - dp/dp_utils.o + dp/dp_utils.o \ + dp/dp_mst_drm.o msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 0346efd802340..1d45f2ebcf479 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -680,6 +680,12 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, stream_cnt = msm_dp_get_mst_max_stream(priv->kms->dp[i]); if (stream_cnt > 1) { + rc = msm_dp_mst_register(priv->kms->dp[i]); + if (rc) { + DPU_ERROR("dp_mst_init failed for DP, rc = %d\n", rc); + return rc; + } + for (stream_id = 0; stream_id < stream_cnt; stream_id++) { encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); if (IS_ERR(encoder)) { diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 0d3985e0da9f6..329938ac6439c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -28,6 +28,7 @@ #include "dp_drm.h" #include "dp_audio.h" #include "dp_debug.h" +#include "dp_mst_drm.h" static bool psr_enabled = false; module_param(psr_enabled, bool, 0); @@ -361,6 +362,9 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) if (dp->max_stream > 1 && drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd)) msm_dp_display_mst_init(dp); + if (dp->msm_dp_display.mst_active) + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, true); + msm_dp_link_reset_phy_params_vx_px(dp->link); end: @@ -528,6 +532,11 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) dp->panel->dpcd, dp->panel->downstream_ports); + if (dp->msm_dp_display.mst_active) { + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, false); + dp->msm_dp_display.mst_active = false; + } + /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); @@ -1553,6 +1562,15 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display, struct drm_device *dev, return 0; } +int msm_dp_mst_register(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + + return msm_dp_mst_init(msm_dp_display, dp->max_stream, dp->aux); +} + int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, struct drm_atomic_state *state, struct drm_encoder *drm_encoder, diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index bda76319c4596..55874daf41c44 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -24,6 +24,8 @@ struct msm_dp { bool is_edp; bool prepared; + void *msm_dp_mst; + struct msm_dp_audio *msm_dp_audio; bool psr_supported; }; diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/dp_mst_drm.c new file mode 100644 index 0000000000000..b6c7b82110251 --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "dp_mst_drm.h" +#include "dp_panel.h" + +#define MAX_DPCD_TRANSACTION_BYTES 16 + +struct msm_dp_mst { + struct drm_dp_mst_topology_mgr mst_mgr; + struct msm_dp *msm_dp; + struct drm_dp_aux *dp_aux; + u32 max_streams; + /* Protects MST bridge enable/disable handling. */ + struct mutex mst_lock; +}; + +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) +{ + struct msm_dp_mst *mst = dp_display->msm_dp_mst; + int rc; + + rc = drm_dp_mst_topology_mgr_set_mst(&mst->mst_mgr, state); + if (rc < 0) { + DRM_ERROR("failed to set topology mgr state to %d. rc %d\n", + state, rc); + } + + drm_dbg_dp(dp_display->drm_dev, "dp_mst_display_set_mgr_state state:%d\n", state); + return rc; +} + +int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_aux *drm_aux) +{ + struct drm_device *dev = dp_display->drm_dev; + int conn_base_id = 0; + int ret; + struct msm_dp_mst *msm_dp_mst; + + msm_dp_mst = devm_kzalloc(dev->dev, sizeof(*msm_dp_mst), GFP_KERNEL); + if (!msm_dp_mst) + return -ENOMEM; + + memset(&msm_dp_mst->mst_mgr, 0, sizeof(msm_dp_mst->mst_mgr)); + + conn_base_id = dp_display->connector->base.id; + msm_dp_mst->msm_dp = dp_display; + msm_dp_mst->max_streams = max_streams; + + msm_dp_mst->dp_aux = drm_aux; + + ret = drm_dp_mst_topology_mgr_init(&msm_dp_mst->mst_mgr, dev, + drm_aux, + MAX_DPCD_TRANSACTION_BYTES, + max_streams, + conn_base_id); + if (ret) { + DRM_ERROR("DP DRM MST topology manager init failed\n"); + return ret; + } + + dp_display->msm_dp_mst = msm_dp_mst; + + mutex_init(&msm_dp_mst->mst_lock); + return ret; +} diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/dp_mst_drm.h new file mode 100644 index 0000000000000..5d411529f6819 --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DP_MST_DRM_H_ +#define _DP_MST_DRM_H_ + +#include "dp_display.h" + +int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_aux *drm_aux); +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state); + +#endif /* _DP_MST_DRM_H_ */ diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 9fac9e039c31c..f347d683e9701 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -356,6 +356,7 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); +int msm_dp_mst_register(struct msm_dp *dp_display); #else static inline int __init msm_dp_register(void) { @@ -377,6 +378,11 @@ static inline int msm_dp_get_mst_max_stream(struct msm_dp *dp_display) return -EINVAL; } +static inline int msm_dp_mst_register(struct msm_dp *dp_display) +{ + return -EINVAL; +} + static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) { } From f7aaa20906de1477ddb42f4eec3f0ad01767d16a Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 22 Apr 2026 20:32:50 +0530 Subject: [PATCH 0782/1330] QCLINUX: arm64: dts: qcom: Add Purwa camx overlay dts Add CAMX overlay dts file for purwa boards. This change also enables the compilation of the CAMX overlay for purwa boards. Signed-off-by: Chandan Kumar Jha (cherry picked from commit 88293dfec01cf603c4c8e8d59fe2c37460a2672e) --- arch/arm64/boot/dts/qcom/Makefile | 4 + arch/arm64/boot/dts/qcom/purwa-camera.dtsi | 2056 ++++++++++++++++++ arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso | 25 + 3 files changed, 2085 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/purwa-camera.dtsi create mode 100644 arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 509236dcc6f65..ae7982b89bee9 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -511,6 +511,10 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo +purwa-evk-camx-dtbs := purwa-iot-evk.dtb purwa-evk-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += purwa-evk-camx.dtb + qcs5430-fps-camx-dtbs := qcs6490-rb3gen2.dtb qcs5430-fps-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs5430-fps-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/purwa-camera.dtsi b/arch/arm64/boot/dts/qcom/purwa-camera.dtsi new file mode 100644 index 0000000000000..5896e5759e22f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-camera.dtsi @@ -0,0 +1,2056 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +&soc { + cam_icp: qcom,icp@ac01000 { + compatible = "qcom,cam-icp_v2"; + icp-version = <0x0200>; + reg = <0x0 0xac01000 0x0 0x400>, + <0x0 0xac01800 0x0 0x400>, + <0x0 0x0ac04000 0x0 0x1000>; + reg-names = "icp_csr", "icp_cirq", "icp_wd0"; + reg-cam-base = <0x1000 0x1800 0x4000>; + interrupts = ; + interrupt-names = "icp"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + memory-region = <&camera_mem>; + clocks = <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + clock-names = "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + clock-rates = <0 300000000 0>, + <0 400000000 0>, + <0 480000000 0>, + <0 600000000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "nominal"; + nrt-device; + src-clock-name = "icp_clk_src"; + operating-points-v2 = <&icp_opp_table>; + clock-control-debugfs = "true"; + fw_name = "qcom/x1p4x100/CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x00000A0A>; + cam_hw_pid = <3>; + cell-index = <0>; + status = "okay"; + + icp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_cpas: qcom,cam-cpas@ac13000 { + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg = <0x0 0xac13000 0x0 0x1000>, + <0x0 0xac19000 0x0 0xC000>, + <0x0 0xbbf0000 0x0 0x1F00>; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg-cam-base = <0x13000 0x19000 0x0bbf0000>; + interrupts = ; + interrupt-names = "cpas_camnoc"; + camnoc-axi-min-ib-bw = <3000000000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names = "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk", + "camnoc_axi_nrt_clk", + "camcc_debug_clk"; + clock-rates = < 0 0 0 0 0 0 0 0 0 0 0 0>, + < 0 0 0 64000000 0 0 80000000 0 240000000 0 0 0>, + < 0 0 0 80000000 0 0 100000000 0 300000000 0 0 0>, + < 0 0 0 80000000 0 0 400000000 0 400000000 0 0 0>; + clock-cntl-level = "suspend", "lowsvsd1", "lowsvs", "nominal"; + clock-names-option = "cam_icp_clk"; + clocks-option = <&camcc CAM_CC_ICP_CLK>; + clock-rates-option = <400000000>; + src-clock-name = "camnoc_axi_clk_src"; + operating-points-v2 = <&cpas_opp_table>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + cam-icc-path-names = "cam_ahb"; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnects =<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_sf_0", + "cam_sf_icp"; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = <0 0>, <0 76800>, <0 76800>, <0 150000>, + <0 150000>, <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = "csiphy0", "csiphy4", "cci0", "cci1", "csid0", + "csid1", "csid2", "ife0", "ife1", "ife2", "ipe0", + "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", + "cam-cdm-intf0", "bps0", "icp0", "jpeg-dma0", + "jpeg-enc0", "tpg13", "tpg14", "tpg15"; + cell-index = <0>; + status = "okay"; + + camera-bus-nodes { + level0-nodes { + level-index = <0>; + + bps0_all_rd: bps0-all-rd { + cell-index = <0>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <1>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_wr>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <2>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt1_rd>; + }; + + ife0_linear_stats_wr: ife0-linear-stats-wr { + cell-index = <3>; + node-name = "ife0-linear-stats-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr3>; + }; + + ife0_pdaf_wr: ife0-pdaf-wr { + cell-index = <4>; + node-name = "ife0-pdaf-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_rt0_wr2>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <5>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <6>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr0>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <7>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level2_nrt0_wr>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <8>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <9>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <10>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <11>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_wr0>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <12>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <13>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_wr0>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <14>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + /* IFE Lite 0 */ + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <15>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + /* IFE Lite 1 */ + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <16>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <17>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <18>; + node-name = "level1-nrt0-rd1"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <19>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <20>; + node-name = "level1-ife-ubwc-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <21>; + node-name = "level1-ife-rdi-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <22>; + node-name = "level1-ife-pdaf"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr3: level1-rt0-wr3 { + cell-index = <23>; + node-name = "level1-ife01-linear-stats"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr4: level1-rt0-wr4 { + cell-index = <24>; + node-name = "level1-ifelite"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <25>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <26>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <27>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = ; + bus-width-factor = <4>; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <28>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_wr: level2-rt0-wr { + cell-index = <29>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + }; + + level3-nodes { + level-index = <3>; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <30>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <31>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_icp"; + }; + }; + + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <32>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0"; + }; + }; + }; + }; + + cpas_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_cci0: qcom,cci0@ac15000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac15000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupts = ; + interrupt-names = "cci0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + operating-points-v2 = <&cci0_opp_table>; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci0_active>; + pinctrl-1 = <&cci0_suspend>; + pinctrl-2 = <&cci1_active>; + pinctrl-3 = <&cci1_suspend>; + cell-index = <0>; + status = "okay"; + + cci0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci0: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_100Khz_cci0: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + }; + + cam_cci1: qcom,cci1@ac16000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac16000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupts = ; + interrupt-names = "cci1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + pinctrl-2 = <&cci3_active>; + pinctrl-3 = <&cci3_suspend>; + operating-points-v2 = <&cci1_opp_table>; + cell-index = <1>; + status = "okay"; + + cci1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci1: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_100Khz_cci1: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + }; + + qcom,rt-cdm0@ac25000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac25000 0x0 0x400>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupts = ; + interrupt-names = "rt-cdm0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <400000000 0>; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table0>; + nrt-device; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <0>; + status = "okay"; + + cdm_cpas_opp_table0: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_jpeg_enc: qcom,jpegenc@ac2a000 { + compatible = "qcom,cam_jpeg_enc_680"; + reg = <0x0 0xac2a000 0x0 0x1000>, + <0x0 0x0ac19000 0x0 0xc000>; + reg-names = "jpegenc_hw", "cam_camnoc"; + reg-cam-base = <0x2a000 0x19000>; + interrupts = ; + interrupt-names = "jpeg"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "jpegenc_clk_src", + "jpegenc_clk"; + clock-rates = <160000000 0>, + <200000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + operating-points-v2 = <&jpeg_enc_opp_table>; + nrt-device; + cam_hw_pid = <12 14>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + cell-index = <0>; + status = "okay"; + + jpeg_enc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-48000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_jpeg_dma: qcom,jpegdma@ac2b000 { + compatible = "qcom,cam_jpeg_dma_680"; + reg = <0x0 0xac2b000 0x0 0x1000>, + <0x0 0x0ac19000 0x0 0xc000>; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg-cam-base = <0x2b000 0x19000>; + interrupts = ; + interrupt-names = "jpegdma"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "jpegdma_clk_src", + "jpegdma_clk"; + clock-rates = <160000000 0>, + <200000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + operating-points-v2 = <&jpeg_dma_opp_table>; + nrt-device; + cam_hw_pid = <13 15>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + cell-index = <0>; + status = "okay"; + + jpeg_dma_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-48000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_bps: qcom,bps@ac2c000 { + compatible = "qcom,cam-bps680"; + reg = <0x0 0xac2c000 0x0 0xb000>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + power-domains = <&camcc CAM_CC_BPS_GDSC>; + clocks = <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_CPAS_BPS_CLK>; + clock-names = "bps_ahb_clk", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk", + "cam_cc_cpas_bps_clk"; + clock-rates = <0 0 160000000 0 0>, + <0 0 200000000 0 0>, + <0 0 400000000 0 0>, + <0 0 600000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "nominal"; + nrt-device; + src-clock-name = "bps_clk_src"; + operating-points-v2 = <&bps_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <6 7>; + cell-index = <0>; + status = "okay"; + + bps_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + compatible = "qcom,cam-ipe680"; + reg = <0x0 0xac42000 0x0 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + power-domains = <&camcc CAM_CC_IPE_0_GDSC>; + clocks = <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CPAS_IPE_NPS_CLK>; + clock-names = "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_cpas_ipe_nps_clk"; + clock-rates = <0 0 0 304000000 0 0 0>, + <0 0 0 364000000 0 0 0>, + <0 0 0 500000000 0 0 0>, + <0 0 0 600000000 0 0 0>, + <0 0 0 700000000 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + operating-points-v2 = <&ipe0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <22 23 30>; + cell-index = <0>; + status = "okay"; + + ipe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-304000000 { + opp-hz = /bits/ 64 <304000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-364000000 { + opp-hz = /bits/ 64 <364000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe0: qcom,ife0@ac62000 { + compatible = "qcom,vfe680"; + reg = <0x0 0xac62000 0x0 0xf000>, + <0x0 0xac19000 0x0 0xc000>; + reg-names = "ife", "cam_camnoc"; + reg-cam-base = <0x62000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "ife0"; + power-domains = <&camcc CAM_CC_IFE_0_GDSC>; + clocks = <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>; + clock-names = "ife_0_fast_ahb", + "ife_0_clk_src", + "ife_0_clk", + "cam_cc_cpas_ife_0_clk"; + clock-rates = <0 345600000 0 0>, + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_0_clk_src"; + operating-points-v2 = <&vfe0_opp_table>; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 4 20 8>; + cell-index = <0>; + status = "okay"; + + vfe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-727000000 { + opp-hz = /bits/ 64 <727000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid0: qcom,csid0@acb7000 { + compatible = "qcom,csid695"; + reg = <0x0 0xacb7000 0x0 0xd00>, + <0x0 0xacb6000 0x0 0x1000>; + reg-names = "csid", "csid_top"; + reg-cam-base = <0xb7000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "csid0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0 0>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clock-rates = <300000000 0 0>, + <400000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "csid_clk_src"; + operating-points-v2 = <&csid0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "okay"; + + csid0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite0: qcom,csid-lite0@acc6000 { + compatible = "qcom,csid-lite680"; + reg = <0x0 0xacc6000 0x0 0xa00>; + reg-names = "csid-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xc6000>; + interrupts = ; + interrupt-names = "csid-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 1 0 0 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "okay"; + + csid_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite0: qcom,ife-lite0@acc6000 { + compatible = "qcom,vfe-lite695"; + reg = <0x0 0xacc6000 0x0 0x4000>; + reg-names = "ife-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xc6000>; + interrupts = ; + interrupt-names = "ife-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 0 0 1 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <0>; + cell-index = <1>; + status = "okay"; + + vfe_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite1: qcom,csid-lite1@acca000 { + compatible = "qcom,csid-lite680"; + reg = <0x0 0xacca000 0x0 0xa00>; + reg-names = "csid-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xca000>; + interrupts = ; + interrupt-names = "csid-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 1 0 0 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <2>; + status = "okay"; + + csid_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite1: qcom,ife-lite1@acca000 { + compatible = "qcom,vfe-lite695"; + reg = <0x0 0xacca000 0x0 0x4000>; + reg-names = "ife-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xca000>; + interrupts = ; + interrupt-names = "ife-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 0 0 1 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite1_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <1>; + cell-index = <2>; + status = "okay"; + + vfe_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xace4000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupts = ; + interrupt-names = "CSIPHY0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l1c_1p2>; + csi-vdd-0p9-supply = <&vreg_l2c_0p8>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 920000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy0_opp_table>; + cell-index = <0>; + status = "okay"; + + csiphy0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xacec000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupts = ; + interrupt-names = "CSIPHY4"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l1c_1p2>; + csi-vdd-0p9-supply = <&vreg_l2c_0p8>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 880000>; + rgltr-max-voltage = <1200000 920000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy4_opp_table>; + cell-index = <4>; + status = "okay"; + + csiphy4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf6000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg0", "cam_cpas_top"; + reg-cam-base = <0xf6000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg0"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg0_opp_table>; + cell-index = <13>; + phy-id = <0>; + status = "okay"; + + csiphy_tpg0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf7000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg1", "cam_cpas_top"; + reg-cam-base = <0xf7000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg1"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg1_opp_table>; + cell-index = <14>; + phy-id = <1>; + status = "okay"; + + csiphy_tpg1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg15: qcom,tpg15@acf8000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf8000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg2", "cam_cpas_top"; + reg-cam-base = <0xf8000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg2"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg2_opp_table>; + cell-index = <15>; + phy-id = <2>; + status = "okay"; + + csiphy_tpg2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm2@acf9000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xacf9000 0x0 0x400>; + reg-names = "rt-cdm2"; + reg-cam-base = <0xf9000>; + interrupts = ; + interrupt-names = "rt-cdm2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_lite_ahb"; + clock-rates = <80000000 0>; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table2>; + nrt-device; + cdm-client-names = "ife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <2>; + status = "okay"; + + cdm_cpas_opp_table2: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm3@acfa000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xacfa000 0x0 0x400>; + reg-names = "rt-cdm3"; + reg-cam-base = <0xfa000>; + interrupts = ; + interrupt-names = "rt-cdm3"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_lite_ahb"; + clock-rates = <80000000 0>; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table3>; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <3>; + status = "okay"; + + cdm_cpas_opp_table3: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + cell-index = <0>; + status = "okay"; + }; + + cam_icp_firmware: qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "okay"; + icp_pc_en; + icp_use_pil; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "okay"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "okay"; + }; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "okay"; + }; + + cam_smmu: qcom,cam-smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "okay"; + force_cache_allocs; + need_shared_buffer_padding; + + msm-cam-smmu-cpas-cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x0000>; + cam-smmu-label = "rt-cdm"; + dma-coherent; + multiple-client-devices; + + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1800 0x0060>, + <&apps_smmu 0x1820 0x0060>, + <&apps_smmu 0x1840 0x0060>, + <&apps_smmu 0x1860 0x0060>, + <&apps_smmu 0x1900 0x0000>, + <&apps_smmu 0x1980 0x0020>, + <&apps_smmu 0x19A0 0x0020>; + cam-smmu-label = "icp"; + iova-region-discard = <0xe0000000 0x800000>; + dma-coherent; + + icp_iova_mem_map: iova-mem-map { + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "okay"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + iova-region-start = <0x10400000>; + iova-region-len = <0x700000>; + iova-region-id = <0x6>; + status = "okay"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.8 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xe0000000 0x800000>; + status = "okay"; + }; + + iova-mem-region-shared { + /* Shared region is ~250MB long */ + iova-region-name = "shared"; + iova-region-start = <0x800000>; + iova-region-len = <0xFC00000>; + iova-region-id = <0x1>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0800 0x0060>, + <&apps_smmu 0x0820 0x0060>, + <&apps_smmu 0x0840 0x0060>, + <&apps_smmu 0x0860 0x0060>; + dma-coherent; + cam-smmu-label = "ife"; + multiple-client-devices; + + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18E0 0x0000>; + cam-smmu-label = "jpeg"; + dma-coherent; + + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "okay"; + }; + + qcom,camera-main { + compatible = "qcom,camera_x1e80100"; + status = "okay"; + }; +}; + +&tlmm { + cam_sensor_active_int: cam-sensor-active-int { + /* CUSTOM */ + mux { + pins = "gpio19"; + function = "cam_pwe"; + }; + + config { + pins = "gpio19"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam-sensor-active-rst0 { + /* RESET REAR */ + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + pins = "gpio109"; + function = "gpio"; + }; + }; + + cam_sensor_active_rst1: cam-sensor-active-rst1 { + /* RESET */ + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst4: cam-sensor-active-rst4 { + /* RESET REAR */ + config { + pins = "gpio237"; + bias-disable; /* No PULL */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio237"; + function = "gpio"; + }; + }; + + cam_sensor_mclk0_active: cam-sensor-mclk0-active { + /* mclk0 */ + config { + pins = "gpio96"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk0_suspend: cam-sensor-mclk0-suspend { + /* mclk0 */ + config { + pins = "gpio96"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk1_active: cam-sensor-mclk1-active { + /* MCLK1 */ + mux { + pins = "gpio97"; + function = "cam_mclk"; + }; + + config { + pins = "gpio97"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam-sensor-mclk1-suspend { + /* MCLK1 */ + mux { + pins = "gpio97"; + function = "cam_mclk"; + }; + + config { + pins = "gpio97"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam-sensor-mclk4-active { + /* mclk4 */ + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio100"; + function = "cam_aon"; + }; + }; + + cam_sensor_mclk4_suspend: cam-sensor-mclk4-suspend { + /* mclk4 */ + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio100"; + function = "cam_aon"; + }; + }; + + cam_sensor_suspend_int: cam-sensor-suspend-int { + /* CUSTOM */ + mux { + pins = "gpio19"; + function = "cam_pwe"; + }; + + config { + pins = "gpio19"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam-sensor-suspend-rst0 { + /* RESET REAR */ + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + + mux { + pins = "gpio109"; + function = "gpio"; + }; + }; + + cam_sensor_suspend_rst1: cam-sensor-suspend-rst1 { + /* RESET */ + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_suspend_rst4: cam-sensor-suspend-rst4 { + /* RESET REAR */ + config { + pins = "gpio237"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <12>; /* 12 MA */ + output-low; + }; + + mux { + pins = "gpio237"; + function = "gpio"; + }; + }; + + cci0_active: cci0-active { + config { + /* DATA, CLK */ + pins = "gpio101","gpio102"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio101","gpio102"; // Only 2 + function = "cci_i2c"; + }; + }; + + cci0_suspend: cci0-suspend { + config { + /* DATA, CLK */ + pins = "gpio101","gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio101","gpio102"; + function = "cci_i2c"; + }; + }; + + cci1_active: cci1-active { + config { + /* DATA, CLK */ + pins = "gpio103","gpio104"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio103","gpio104"; // Only 2 + function = "cci_i2c"; + }; + }; + + cci1_suspend: cci1-suspend { + config { + /* DATA, CLK */ + pins = "gpio103","gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio103","gpio104"; + function = "cci_i2c"; + }; + }; + + cci2_active: cci2-active { + config { + /* DATA, CLK */ + pins = "gpio105","gpio106"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio105","gpio106"; // Only 2 + function = "cci_i2c"; + }; + }; + + cci2_suspend: cci2-suspend { + config { + /* DATA, CLK */ + pins = "gpio105","gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + }; + }; + + cci3_active: cci3-active { + config { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + }; + }; + + cci3_suspend: cci3-suspend { + config { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso b/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso new file mode 100644 index 0000000000000..26603aed4eafc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "purwa-camera.dtsi" + +&camss { + status = "disabled"; +}; From 89c7e8ffeff15746bab48ca7d30e0c6b4439395e Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 9 Apr 2026 01:52:24 -0700 Subject: [PATCH 0783/1330] FROMLIST: dt-bindings: remoteproc: qcom: cleanup qcom,adsp.yaml Items in qcom,adsp.yaml has common clock and interrupt properties, move these out of the allOf section to avoid list the compatible repeatly. Link: https://lore.kernel.org/lkml/20260409-knp-soccp-v5-1-805a492124da@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang (cherry picked from commit 46b29d2742bb3bc86c509f4b62081dfc8a1414c7) --- .../bindings/remoteproc/qcom,adsp.yaml | 64 ++++--------------- 1 file changed, 14 insertions(+), 50 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index 16a245fe2738d..a270834605da2 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -32,6 +32,14 @@ properties: reg: maxItems: 1 + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + cx-supply: true px-supply: @@ -49,6 +57,12 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + maxItems: 5 + + interrupt-names: + maxItems: 5 + required: - compatible - memory-region @@ -57,56 +71,6 @@ unevaluatedProperties: false allOf: - $ref: /schemas/remoteproc/qcom,pas-common.yaml# - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8226-adsp-pil - - qcom,msm8953-adsp-pil - - qcom,msm8974-adsp-pil - - qcom,msm8996-adsp-pil - - qcom,msm8996-slpi-pil - - qcom,msm8998-adsp-pas - - qcom,msm8998-slpi-pas - - qcom,sdm660-adsp-pas - - qcom,sdm660-cdsp-pas - - qcom,sdm845-adsp-pas - - qcom,sdm845-cdsp-pas - - qcom,sdm845-slpi-pas - then: - properties: - clocks: - items: - - description: XO clock - clock-names: - items: - - const: xo - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8226-adsp-pil - - qcom,msm8953-adsp-pil - - qcom,msm8974-adsp-pil - - qcom,msm8996-adsp-pil - - qcom,msm8996-slpi-pil - - qcom,msm8998-adsp-pas - - qcom,msm8998-slpi-pas - - qcom,sdm660-adsp-pas - - qcom,sdm660-cdsp-pas - - qcom,sdm845-adsp-pas - - qcom,sdm845-cdsp-pas - - qcom,sdm845-slpi-pas - then: - properties: - interrupts: - maxItems: 5 - interrupt-names: - maxItems: 5 - - if: properties: compatible: From 7479c71de5fb17460503dd9ab26a65a652bcf7d0 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 9 Apr 2026 01:52:25 -0700 Subject: [PATCH 0784/1330] FROMLIST: dt-bindings: remoteproc: qcom: move interrupts and interrupt-names list out of pas-common Move interrupts and interrupt-names list out of pas-common since they will be redefined differently for Kaanapali SoCCP. Link: https://lore.kernel.org/lkml/20260409-knp-soccp-v5-2-805a492124da@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang (cherry picked from commit 0e24ee43742483b2c7692d170671aa6cc291b27e) --- .../bindings/remoteproc/qcom,adsp.yaml | 14 +++++++++++-- .../bindings/remoteproc/qcom,milos-pas.yaml | 18 +++++++++++++---- .../bindings/remoteproc/qcom,pas-common.yaml | 16 ++------------- .../bindings/remoteproc/qcom,qcs404-pas.yaml | 14 +++++++++++-- .../bindings/remoteproc/qcom,sa8775p-pas.yaml | 14 +++++++++++-- .../bindings/remoteproc/qcom,sc7180-pas.yaml | 20 +++++++++++++++++++ .../remoteproc/qcom,sc8280xp-pas.yaml | 20 +++++++++++++++++++ .../bindings/remoteproc/qcom,sdx55-pas.yaml | 16 +++++++++++++-- .../bindings/remoteproc/qcom,sm6115-pas.yaml | 20 +++++++++++++++++++ .../bindings/remoteproc/qcom,sm6350-pas.yaml | 20 +++++++++++++++++++ .../bindings/remoteproc/qcom,sm6375-pas.yaml | 20 +++++++++++++++++++ .../bindings/remoteproc/qcom,sm8150-pas.yaml | 20 +++++++++++++++++++ .../bindings/remoteproc/qcom,sm8350-pas.yaml | 20 +++++++++++++++++++ .../bindings/remoteproc/qcom,sm8550-pas.yaml | 20 +++++++++++++++++++ 14 files changed, 226 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index a270834605da2..16c35e15ee1b4 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -58,10 +58,20 @@ properties: description: Firmware name for the Hexagon core interrupts: - maxItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt interrupt-names: - maxItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack required: - compatible diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml index c47d97004b330..f8e1b2b8e7828 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml @@ -33,12 +33,22 @@ properties: - const: xo interrupts: - minItems: 6 - maxItems: 6 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt interrupt-names: - minItems: 6 - maxItems: 6 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack qcom,qmp: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index 6a736161d5aed..ff7161af45339 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -26,23 +26,11 @@ properties: interrupts: minItems: 5 - items: - - description: Watchdog interrupt - - description: Fatal interrupt - - description: Ready interrupt - - description: Handover interrupt - - description: Stop acknowledge interrupt - - description: Shutdown acknowledge interrupt + maxItems: 6 interrupt-names: minItems: 5 - items: - - const: wdog - - const: fatal - - const: ready - - const: handover - - const: stop-ack - - const: shutdown-ack + maxItems: 6 iommus: maxItems: 1 diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml index ad45fd00ae346..5854b3d2041d5 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml @@ -32,10 +32,20 @@ properties: - const: xo interrupts: - maxItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt interrupt-names: - maxItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack power-domains: false power-domain-names: false diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml index 188a251940001..4c6d32b1031c7 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml @@ -60,10 +60,20 @@ properties: - description: Memory region for main Firmware authentication interrupts: - maxItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt interrupt-names: - maxItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack required: - compatible diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml index 66b455d0a8e32..cb0a61fc301df 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml @@ -48,6 +48,26 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml index 5dbda3a550477..c51010493bca3 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml @@ -45,6 +45,26 @@ properties: $ref: /schemas/types.yaml#/definitions/string description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml index 5d463272165fd..381ece510b0f0 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml @@ -30,10 +30,22 @@ properties: - const: xo interrupts: - minItems: 6 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt interrupt-names: - minItems: 6 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack power-domains: items: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml index eeb6a8aafeb92..987fac433fae5 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml @@ -51,6 +51,26 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml index c1a3cc308bdb2..53ffb1ccd1995 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml @@ -45,6 +45,26 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml index 7286b2baa19f2..6823a2a8d74e7 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml @@ -39,6 +39,26 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + smd-edge: false required: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml index a8cddf7e2fe1a..8a1fae095a3bd 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml @@ -61,6 +61,26 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml index 6d09823153fc8..4ea7518db5374 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -55,6 +55,26 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index b117c82b057b3..d93e17fb5e89f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -72,6 +72,26 @@ properties: - description: DSM Memory region 2 - description: Memory region for Qlink Logging + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + required: - compatible - reg From c8b45a53f9d5a863516a82226c38d499d8ba4dd6 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 9 Apr 2026 01:52:26 -0700 Subject: [PATCH 0785/1330] FROMLIST: dt-bindings: remoteproc: qcom: Document pas for SoCCP on Kaanapali and Glymur platforms Document the component used to boot SoCCP on Kaanapali SoC and add compatible for Glymur SoCCP which could fallback to Kaanapali. Extend the "qcom,smem-states", "qcom,smem-state-names" in the pas-common and add maxItems constraints for SMEM properties in the documents that reference to pas-common. Link: https://lore.kernel.org/lkml/20260409-knp-soccp-v5-3-805a492124da@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang (cherry picked from commit 6abb4da6bd3dac1abdd22928987be3424bc8daac) --- .../bindings/remoteproc/qcom,adsp.yaml | 8 + .../remoteproc/qcom,kaanapali-soccp-pas.yaml | 154 ++++++++++++++++++ .../bindings/remoteproc/qcom,milos-pas.yaml | 8 + .../bindings/remoteproc/qcom,pas-common.yaml | 6 +- .../bindings/remoteproc/qcom,qcs404-pas.yaml | 8 + .../bindings/remoteproc/qcom,sa8775p-pas.yaml | 8 + .../bindings/remoteproc/qcom,sc7180-pas.yaml | 8 + .../remoteproc/qcom,sc8280xp-pas.yaml | 8 + .../bindings/remoteproc/qcom,sdx55-pas.yaml | 8 + .../bindings/remoteproc/qcom,sm6115-pas.yaml | 8 + .../bindings/remoteproc/qcom,sm6350-pas.yaml | 8 + .../bindings/remoteproc/qcom,sm6375-pas.yaml | 8 + .../bindings/remoteproc/qcom,sm8150-pas.yaml | 8 + .../bindings/remoteproc/qcom,sm8350-pas.yaml | 8 + .../bindings/remoteproc/qcom,sm8550-pas.yaml | 8 + 15 files changed, 263 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,kaanapali-soccp-pas.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index 16c35e15ee1b4..7e8ecae8e6cb6 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -73,6 +73,14 @@ properties: - const: handover - const: stop-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - memory-region diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,kaanapali-soccp-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,kaanapali-soccp-pas.yaml new file mode 100644 index 0000000000000..ce18460a949fc --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,kaanapali-soccp-pas.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,kaanapali-soccp-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali SoCCP Peripheral Authentication Service + +maintainers: + - Jingyi Wang + +description: + The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls USB + Type-C, battery charging and various other functions on Qualcomm SoCs, somewhat + analogous to traditional PC Embedded Controllers. This document describes + the Peripheral Authentication Service that loads and boots firmware for SoCCP. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,glymur-soccp-pas + - const: qcom,kaanapali-soccp-pas + - enum: + - qcom,kaanapali-soccp-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + power-domains: + items: + - description: CX power domain + - description: MX power domain + + power-domain-names: + items: + - const: cx + - const: mx + + firmware-name: + items: + - description: Firmware name of the SoC Control Processor + - description: Firmware name of the SoCCP Devicetree + + memory-region: + items: + - description: Memory region for main Firmware authentication + - description: Memory region for Devicetree Firmware authentication + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Pong interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: pong + + qcom,smem-states: + minItems: 2 + description: States used by the AP to signal the SoC Control Processor + + qcom,smem-state-names: + minItems: 2 + description: The names of the state bits used for SMP2P output + +required: + - compatible + - reg + - memory-region + - power-domains + - power-domain-names + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #define IPCC_MPROC_SOCCP + + remoteproc@d00000 { + compatible = "qcom,kaanapali-soccp-pas"; + reg = <0x00d00000 0x200000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "pong"; + + memory-region = <&soccp_mem>, + <&soccp_dtb_mem_mem>; + + firmware-name = "qcom/kaanapali/soccp.mbn", + "qcom/kaanapali/soccp_dtb.mbn"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + qcom,smem-states = <&soccp_smp2p_out 0>, + <&soccp_smp2p_out 8>; + qcom,smem-state-names = "stop", + "ping"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "soccp"; + qcom,remote-pid = <19>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml index f8e1b2b8e7828..b24e6f6eaf373 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml @@ -68,6 +68,14 @@ properties: - description: Memory region for core Firmware authentication - description: Memory region for Devicetree Firmware authentication + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index ff7161af45339..682c73238169f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -46,13 +46,17 @@ properties: qcom,smem-states: $ref: /schemas/types.yaml#/definitions/phandle-array description: States used by the AP to signal the Hexagon core + minItems: 1 items: - - description: Stop the modem + - description: Stop the remoteproc + - description: ping the remoteproc qcom,smem-state-names: description: The names of the state bits used for SMP2P output + minItems: 1 items: - const: stop + - const: ping smd-edge: $ref: /schemas/remoteproc/qcom,smd-edge.yaml# diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml index 5854b3d2041d5..bf9bf1af9ff14 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml @@ -59,6 +59,14 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml index 4c6d32b1031c7..6cc2f4b700e0d 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml @@ -75,6 +75,14 @@ properties: - const: handover - const: stop-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml index cb0a61fc301df..b20780e5e26bd 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml @@ -68,6 +68,14 @@ properties: - const: stop-ack - const: shutdown-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml index c51010493bca3..86ae0ae4864be 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml @@ -65,6 +65,14 @@ properties: - const: stop-ack - const: shutdown-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml index 381ece510b0f0..0b38194c0781b 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml @@ -71,6 +71,14 @@ properties: $ref: /schemas/types.yaml#/definitions/string description: Firmware name for the Hexagon core + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml index 987fac433fae5..454ba82bd6f18 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml @@ -71,6 +71,14 @@ properties: - const: stop-ack - const: shutdown-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml index 53ffb1ccd1995..42e02c64347a0 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml @@ -65,6 +65,14 @@ properties: - const: stop-ack - const: shutdown-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml index 6823a2a8d74e7..274f87880e2e6 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml @@ -61,6 +61,14 @@ properties: smd-edge: false + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml index 8a1fae095a3bd..5a7c5f8c92d17 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml @@ -81,6 +81,14 @@ properties: - const: stop-ack - const: shutdown-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml index 4ea7518db5374..72d0db5698c5c 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -75,6 +75,14 @@ properties: - const: stop-ack - const: shutdown-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index d93e17fb5e89f..f4832c2930ee3 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -92,6 +92,14 @@ properties: - const: stop-ack - const: shutdown-ack + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg From 540e4e0d240b73d2faa6dd641c078b2e26b87e13 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 9 Apr 2026 01:52:27 -0700 Subject: [PATCH 0786/1330] FROMLIST: remoteproc: qcom: pas: Add late attach support for subsystems Subsystems can be brought out of reset by entities such as bootloaders. As the irq enablement could be later than subsystem bring up, the state of subsystem should be checked by reading SMP2P bits and performing ping test. A new qcom_pas_attach() function is introduced. if a crash state is detected for the subsystem, rproc_report_crash() is called. If the subsystem is ready and the ping is successful, it will be marked as "attached". If ready irq is not received, it could be the early boot feature is not supported by other entities. In this case, the state will be marked as RPROC_OFFLINE so that the PAS driver can load the firmware and start the remoteproc. Link: https://lore.kernel.org/lkml/20260409-knp-soccp-v5-4-805a492124da@oss.qualcomm.com/ Co-developed-by: Gokul Krishna Krishnakumar Signed-off-by: Gokul Krishna Krishnakumar Signed-off-by: Jingyi Wang (cherry picked from commit 69f19b62b1e31971422a5584acb92a17581a2104) --- drivers/remoteproc/qcom_q6v5.c | 69 ++++++++++++++++++++++++++ drivers/remoteproc/qcom_q6v5.h | 6 +++ drivers/remoteproc/qcom_q6v5_pas.c | 80 ++++++++++++++++++++++++++++-- 3 files changed, 152 insertions(+), 3 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index a02839c7ed8c2..96f4198c1a47c 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -21,6 +21,7 @@ #define Q6V5_LOAD_STATE_MSG_LEN 64 #define Q6V5_PANIC_DELAY_MS 200 +#define Q6V5_PING_TIMEOUT_MS 500 static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable) { @@ -235,6 +236,74 @@ unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5) } EXPORT_SYMBOL_GPL(qcom_q6v5_panic); +static irqreturn_t q6v5_pong_interrupt(int irq, void *data) +{ + struct qcom_q6v5 *q6v5 = data; + + complete(&q6v5->ping_done); + + return IRQ_HANDLED; +} + +int qcom_q6v5_ping_subsystem(struct qcom_q6v5 *q6v5) +{ + int ret; + int ping_failed = 0; + + reinit_completion(&q6v5->ping_done); + + /* Set master kernel Ping bit */ + ret = qcom_smem_state_update_bits(q6v5->ping_state, + BIT(q6v5->ping_bit), BIT(q6v5->ping_bit)); + if (ret) { + dev_err(q6v5->dev, "Failed to update ping bits\n"); + return ret; + } + + ret = wait_for_completion_timeout(&q6v5->ping_done, msecs_to_jiffies(Q6V5_PING_TIMEOUT_MS)); + if (!ret) { + ping_failed = -ETIMEDOUT; + dev_err(q6v5->dev, "Failed to get back pong\n"); + } + + /* Clear ping bit master kernel */ + ret = qcom_smem_state_update_bits(q6v5->ping_state, BIT(q6v5->ping_bit), 0); + if (ret) { + dev_err(q6v5->dev, "Failed to clear master kernel bits\n"); + return ret; + } + + return ping_failed; +} +EXPORT_SYMBOL_GPL(qcom_q6v5_ping_subsystem); + +int qcom_q6v5_ping_subsystem_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev) +{ + int ret = -ENODEV; + + q6v5->ping_state = devm_qcom_smem_state_get(&pdev->dev, "ping", &q6v5->ping_bit); + if (IS_ERR(q6v5->ping_state)) { + dev_err(&pdev->dev, "Failed to acquire smem state %ld\n", + PTR_ERR(q6v5->ping_state)); + return PTR_ERR(q6v5->ping_state); + } + + init_completion(&q6v5->ping_done); + + q6v5->pong_irq = platform_get_irq_byname(pdev, "pong"); + if (q6v5->pong_irq < 0) + return q6v5->pong_irq; + + ret = devm_request_threaded_irq(&pdev->dev, q6v5->pong_irq, NULL, + q6v5_pong_interrupt, IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "q6v5 pong", q6v5); + if (ret) + dev_err(&pdev->dev, "Failed to acquire pong IRQ\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_q6v5_ping_subsystem_init); + /** * qcom_q6v5_init() - initializer of the q6v5 common struct * @q6v5: handle to be initialized diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h index 5a859c41896e9..5025ffc4dbe80 100644 --- a/drivers/remoteproc/qcom_q6v5.h +++ b/drivers/remoteproc/qcom_q6v5.h @@ -17,22 +17,26 @@ struct qcom_q6v5 { struct rproc *rproc; struct qcom_smem_state *state; + struct qcom_smem_state *ping_state; struct qmp *qmp; struct icc_path *path; unsigned stop_bit; + unsigned int ping_bit; int wdog_irq; int fatal_irq; int ready_irq; int handover_irq; int stop_irq; + int pong_irq; bool handover_issued; struct completion start_done; struct completion stop_done; + struct completion ping_done; int crash_reason; @@ -52,5 +56,7 @@ int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5); int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon); int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout); unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5); +int qcom_q6v5_ping_subsystem(struct qcom_q6v5 *q6v5); +int qcom_q6v5_ping_subsystem_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev); #endif diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 40bc73f42b900..0aba90ee2c745 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -60,6 +60,7 @@ struct qcom_pas_data { int region_assign_count; bool region_assign_shared; int region_assign_vmid; + bool early_boot; }; struct qcom_pas { @@ -447,9 +448,15 @@ static int qcom_pas_stop(struct rproc *rproc) qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); - handover = qcom_q6v5_unprepare(&pas->q6v5); - if (handover) - qcom_pas_handover(&pas->q6v5); + /* + * qcom_q6v5_prepare is not called in qcom_pas_attach, skip unprepare to + * avoid mismatch. + */ + if (pas->rproc->state != RPROC_ATTACHED) { + handover = qcom_q6v5_unprepare(&pas->q6v5); + if (handover) + qcom_pas_handover(&pas->q6v5); + } if (pas->smem_host_id) ret = qcom_smem_bust_hwspin_lock_by_host(pas->smem_host_id); @@ -550,6 +557,63 @@ static void qcom_pas_coredump(struct rproc *rproc) pas->mem_region = NULL; } +static int qcom_pas_attach(struct rproc *rproc) +{ + int ret; + struct qcom_pas *pas = rproc->priv; + bool ready_state; + bool crash_state; + + pas->q6v5.running = true; + ret = irq_get_irqchip_state(pas->q6v5.fatal_irq, + IRQCHIP_STATE_LINE_LEVEL, &crash_state); + + if (ret) + goto disable_running; + + if (crash_state) { + dev_err(pas->dev, "Subsystem has crashed before driver probe\n"); + rproc_report_crash(rproc, RPROC_FATAL_ERROR); + ret = -EINVAL; + goto disable_running; + } + + ret = irq_get_irqchip_state(pas->q6v5.ready_irq, + IRQCHIP_STATE_LINE_LEVEL, &ready_state); + + if (ret) + goto disable_running; + + if (unlikely(!ready_state)) { + /* + * The bootloader may not support early boot, mark the state as + * RPROC_OFFLINE so that the PAS driver can load the firmware and + * start the remoteproc. + */ + dev_err(pas->dev, "Failed to get subsystem ready interrupt\n"); + pas->rproc->state = RPROC_OFFLINE; + ret = -EINVAL; + goto disable_running; + } + + ret = qcom_q6v5_ping_subsystem(&pas->q6v5); + + if (ret) { + dev_err(pas->dev, "Failed to ping subsystem, assuming device crashed\n"); + rproc_report_crash(rproc, RPROC_FATAL_ERROR); + goto disable_running; + } + + pas->q6v5.handover_issued = true; + + return 0; + +disable_running: + pas->q6v5.running = false; + + return ret; +} + static const struct rproc_ops qcom_pas_ops = { .unprepare = qcom_pas_unprepare, .start = qcom_pas_start, @@ -559,6 +623,7 @@ static const struct rproc_ops qcom_pas_ops = { .load = qcom_pas_load, .panic = qcom_pas_panic, .coredump = qcom_pas_coredump, + .attach = qcom_pas_attach, }; static const struct rproc_ops qcom_pas_minidump_ops = { @@ -901,6 +966,15 @@ static int qcom_pas_probe(struct platform_device *pdev) pas->pas_ctx->use_tzmem = rproc->has_iommu; pas->dtb_pas_ctx->use_tzmem = rproc->has_iommu; + + if (desc->early_boot) { + ret = qcom_q6v5_ping_subsystem_init(&pas->q6v5, pdev); + if (ret) + dev_warn(&pdev->dev, "Falling back to firmware load\n"); + else + pas->rproc->state = RPROC_DETACHED; + } + ret = rproc_add(rproc); if (ret) goto remove_ssr_sysmon; From 3c1921a18d6fc234f9da8c54378c3df78f3c9d31 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 9 Apr 2026 01:52:28 -0700 Subject: [PATCH 0787/1330] FROMLIST: remoteproc: qcom_q6v5_pas: Add SoCCP node on Kaanapali The SoC Control Processor (SoCCP) is small RISC-V MCU that controls USB Type-C, battery charging and various other functions on Qualcomm SoCs. It provides a solution for control-plane processing, reducing per-subsystem microcontroller reinvention. Add support for SoCCP PAS loader on Kaanapali platform. Link: https://lore.kernel.org/lkml/20260409-knp-soccp-v5-5-805a492124da@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang Reviewed-by: Bartosz Golaszewski (cherry picked from commit a7b9b6d8b0ef8713aea096ed6c6c0fa74db2ed25) --- drivers/remoteproc/qcom_q6v5_pas.c | 41 ++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 0aba90ee2c745..ee0544449ba78 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -1650,18 +1650,37 @@ static const struct qcom_pas_data sm8750_mpss_resource = { .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA, }; +static const struct qcom_pas_data kaanapali_soccp_resource = { + .crash_reason_smem = 656, + .firmware_name = "soccp.mbn", + .dtb_firmware_name = "soccp_dtb.mbn", + .pas_id = 51, + .dtb_pas_id = 0x41, + .proxy_pd_names = (char*[]){ + "cx", + "mx", + NULL + }, + .ssr_name = "soccp", + .sysmon_name = "soccp", + .auto_boot = true, + .early_boot = true, +}; + static const struct of_device_id qcom_pas_of_match[] = { - { .compatible = "qcom,milos-adsp-pas", .data = &sm8550_adsp_resource}, - { .compatible = "qcom,milos-cdsp-pas", .data = &milos_cdsp_resource}, - { .compatible = "qcom,milos-mpss-pas", .data = &sm8450_mpss_resource}, - { .compatible = "qcom,milos-wpss-pas", .data = &sc7280_wpss_resource}, - { .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource}, - { .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource}, - { .compatible = "qcom,msm8974-adsp-pil", .data = &msm8996_adsp_resource}, - { .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource}, - { .compatible = "qcom,msm8996-slpi-pil", .data = &msm8996_slpi_resource_init}, - { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8996_adsp_resource}, - { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8996_slpi_resource_init}, + { .compatible = "qcom,eliza-adsp-pas", .data = &sm8550_adsp_resource }, + { .compatible = "qcom,kaanapali-soccp-pas", .data = &kaanapali_soccp_resource }, + { .compatible = "qcom,milos-adsp-pas", .data = &sm8550_adsp_resource }, + { .compatible = "qcom,milos-cdsp-pas", .data = &milos_cdsp_resource }, + { .compatible = "qcom,milos-mpss-pas", .data = &sm8450_mpss_resource }, + { .compatible = "qcom,milos-wpss-pas", .data = &sc7280_wpss_resource }, + { .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource }, + { .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource }, + { .compatible = "qcom,msm8974-adsp-pil", .data = &msm8996_adsp_resource }, + { .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource }, + { .compatible = "qcom,msm8996-slpi-pil", .data = &msm8996_slpi_resource_init }, + { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8996_adsp_resource }, + { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8996_slpi_resource_init }, { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init }, { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init }, { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init }, From 7efd2a27eb94bc2786f1b232885b2f33621ae809 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Tue, 7 Apr 2026 11:07:38 +0530 Subject: [PATCH 0788/1330] PENDING: arm64: dts: qcom: lemans: switch iris iommus to iommu-map Switch the iris video codec node in sa8775p (lemans) from the legacy 'iommus' property to 'iommu-map', using IRIS_NON_PIXEL_VCODEC and IRIS_PIXEL function IDs to identify the non-pixel and pixel context bank SMMU stream mappings respectively. Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Signed-off-by: Gourav Kumar (cherry picked from commit abe2b59eafa53a4ef5ce772495b33349c8a73501) --- arch/arm64/boot/dts/qcom/lemans.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 948f9f1c65db9..16f4e4b388da3 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -4624,8 +4625,8 @@ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names = "bus"; - iommus = <&apps_smmu 0x0880 0x0400>, - <&apps_smmu 0x0887 0x0400>; + iommu-map = , + ; dma-coherent; status = "disabled"; From 691c9c420887eaba6a81d00f1b9d5b7e5cf8ee31 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Fri, 10 Apr 2026 22:37:06 +0530 Subject: [PATCH 0789/1330] PENDING: arm64: dts: qcom: lemans-ride: Drop video firmware from common As per memory map, video firmware memory region is 7MB for sa8775* variants while it is 16MB for qcs9100* variants. Keeping the 7MB variant of video firmware in ride common DTS does not allow qcs9100* to pick the 16MB variant. Drop it from common and define in respective variant DTS. Signed-off-by: Gourav Kumar Signed-off-by: Vikash Garodia Signed-off-by: Venkata Siva Pavan KumarVenkatapatigari (cherry picked from commit 8599257b5b6f00e34cefb1f74e6b684b83ffa5e2) --- arch/arm64/boot/dts/qcom/lemans-auto.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 2 -- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi index 8db958d60fd1d..07fa9cb148ae6 100644 --- a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi @@ -102,3 +102,7 @@ }; }; }; + +&iris { + firmware-name = "qcom/vpu/vpu30_p4_s6.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index c72a01fdc75de..68f8d5b432ec5 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -580,8 +580,6 @@ }; &iris { - firmware-name = "qcom/vpu/vpu30_p4_s6.mbn"; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 16f4e4b388da3..23a97ed059946 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4622,6 +4622,8 @@ memory-region = <&pil_video_mem>; + firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn"; + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names = "bus"; From c9eec5c40cf0ed9fb4cdb25f8ec52c7dd73ea05d Mon Sep 17 00:00:00 2001 From: Jianping Li Date: Wed, 22 Apr 2026 17:36:55 +0800 Subject: [PATCH 0790/1330] WORKAROUND: arm64: dts: qcom: sc7280: avoid EFI overlap for ADSP remote heap On KODIAK platforms boot can fail when the DT "adsp-rpc-remote-heap" reserved-memory region overlaps with firmware allocations (UEFI/EFI runtime). The kernel then reports failure to reserve the region and subsequent EFI runtime activity may trigger aborts. The remote heap node was described as a fixed "no-map" region, which turns it into a hard carveout. Replace it with a "shared-dma-pool" reserved memory region with reusable CMA-backed allocation, specifying alignment and size. This avoids hard carveouts and reduces the chance of conflicting with firmware memory maps while keeping an explicit pool for ADSP remote heap usage. Signed-off-by: Jianping Li (cherry picked from commit 147846a90b4db45dcf09a6f25ba23938bc24d0f6) --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index cea8581d291ef..cc61b1d89363a 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -191,9 +191,12 @@ qcom,vmid = ; }; - adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 { - reg = <0x0 0x9cb80000 0x0 0x800000>; - no-map; + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; }; }; From ea82c788f00f8f1606de7a73673bdff61ee06be7 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 27 Apr 2026 15:25:49 +0530 Subject: [PATCH 0791/1330] arm64: dts: qcom: kodiak: Add EL2 overlay All the existing variants Kodiak boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Kodiak IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Signed-off-by: Mukesh Ojha [SG: watchdog fixup] Signed-off-by: Sumit Garg Link: https://lore.kernel.org/r/20260427095603.1157963-2-sumit.garg@kernel.org (cherry picked from commit dd9a4b8355449dd5de2ffa91ba42e7452db231db) --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/kodiak-el2.dtso | 35 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kodiak-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ae7982b89bee9..5b77b11127cb3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -178,6 +178,8 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb +qcs6490-rb3gen2-el2-dtbs := qcs6490-rb3gen2.dtb kodiak-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-el2.dtb qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/kodiak-el2.dtso b/arch/arm64/boot/dts/qcom/kodiak-el2.dtso new file mode 100644 index 0000000000000..0b3a69a0d7654 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kodiak-el2.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Kodiak specific modifications required to boot in EL2. + */ + + +/dts-v1/; +/plugin/; + +&gpu_zap_shader { + status = "disabled"; +}; + +&remoteproc_adsp { + iommus = <&apps_smmu 0x1800 0x0>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x11a0 0x0400>; +}; + +&remoteproc_wpss { + iommus = <&apps_smmu 0x1c03 0x1>, + <&apps_smmu 0x1c83 0x1>; +}; + +&venus { + status = "disabled"; +}; + +&watchdog { + status = "okay"; +}; From 3c19ba7427f3c00c41f0a424355e6af693a4726f Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Fri, 3 Apr 2026 12:10:34 +0530 Subject: [PATCH 0792/1330] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform. The controller is connected via SPI3 and uses a 40 MHz oscillator. Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260403-can-spi-kodiak-dtsi-v1-1-4055e67dd3fc@oss.qualcomm.com (cherry picked from commit d86129381ec0ade1667f9c11d8bedaeedbeaa6f1) --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 86eb67639c3dc..52095082bf876 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1173,17 +1173,9 @@ reg = <0>; interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>; clocks = <&mcp2518fd_osc>; - spi-max-frequency = <10000000>; + spi-max-frequency = <14000000>; vdd-supply = <&vreg_l11c_2p8>; - gpio-controller; - #gpio-cells = <2>; - - gpio0-hog { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - output-high; - line-name = "mcp251xfd-gpio0"; - }; + microchip,xstbyen; }; }; From 0c6d96dd9bc1821fd31f1012d17955c1c108ea79 Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Mon, 27 Apr 2026 23:04:46 +0530 Subject: [PATCH 0793/1330] dt-bindings: arm: Document reboot mode magic Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Reviewed-by: Rob Herring (Arm) Signed-off-by: Shivendra Pratap Link: https://lore.kernel.org/r/20260427-arm-psci-system_reset2-vendor-reboots-v21-6-dcf937775e73@oss.qualcomm.com (cherry picked from commit 5828ac79f9793009a4c522f6653cd3a005c5e18c) --- Documentation/devicetree/bindings/arm/psci.yaml | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 5d4368d77d07e..5fdcbf331ea56 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -113,11 +113,10 @@ properties: Describes a vendor-specific reset type. The string after "mode-" maps a reboot mode to the parameters in the PSCI SYSTEM_RESET2 call. - Parameters are named mode-xxx = , where xxx - is the name of the magic reboot mode, type is the lower 31 bits - of the reset_type, and, optionally, the cookie value. If the cookie - is not provided, it is defaulted to zero. - The 31st bit (vendor-resets) will be implicitly set by the driver. + Parameters are named mode-xxx = , where xxx is the + name of the magic reboot mode, type corresponds to the reset_type + and the values should be provided as per the PSCI SYSTEM_RESET2 + specs. The cookie value is optional and defaulted to zero. patternProperties: "^power-domain-": @@ -299,8 +298,8 @@ examples: method = "smc"; reboot-mode { - mode-edl = <0>; - mode-bootloader = <1 2>; + mode-edl = <0x80000000 1>; + mode-bootloader = <0x80010001 2>; }; }; ... From 5286795d8b17b18afa6d1ce6f2306a8301824553 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:20 +0800 Subject: [PATCH 0794/1330] FROMLIST: drm/msm/dp: add dp_mst_drm to manage DP MST bridge operations Add dp_mst_drm to manage the DP MST bridge operations similar to the dp_drm file which manages the SST bridge operations. Each MST encoder creates one bridge and each bridge is bound to its own dp_panel abstraction to manage the operations of its pipeline. Keep the connector/panel association in bridge private state for atomic assignment and release, and mirror it in the bridge object for runtime bridge callbacks. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-34-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit b4c8ea94ee64986e4b4d5aff7823e5abd6a9aeef) --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 + drivers/gpu/drm/msm/dp/dp_mst_drm.c | 466 +++++++++++++++++++++++- drivers/gpu/drm/msm/msm_drv.h | 7 + 3 files changed, 478 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 1d45f2ebcf479..1f00fa2eb6ea1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -692,6 +692,12 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, DPU_ERROR("encoder init failed for dp mst display\n"); return PTR_ERR(encoder); } + + rc = msm_dp_mst_attach_encoder(priv->kms->dp[i], encoder); + if (rc) { + DPU_ERROR("DP MST init failed, %d\n", rc); + continue; + } } } } diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/dp_mst_drm.c index b6c7b82110251..69f8faa03a98f 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -13,8 +13,47 @@ #define MAX_DPCD_TRANSACTION_BYTES 16 +#define to_dp_mst_bridge(x) container_of((x), struct msm_dp_mst_bridge, base) +#define to_dp_mst_bridge_state_priv(x) \ + container_of((x), struct msm_dp_mst_bridge_state, base) +#define to_dp_mst_bridge_state(x) \ + to_dp_mst_bridge_state_priv((x)->obj.state) +#define to_dp_mst_connector(x) \ + container_of((x), struct msm_dp_mst_connector, connector) + +#define DP_MST_CONN_ID(x) ((x)->connector ? \ + (x)->connector->base.id : 0) + +struct msm_dp_mst_bridge { + struct drm_bridge base; + struct drm_private_obj obj; + u32 id; + + bool initialized; + + struct msm_dp *display; + struct drm_encoder *encoder; + + struct drm_connector *connector; + struct msm_dp_panel *msm_dp_panel; +}; + +struct msm_dp_mst_bridge_state { + struct drm_private_state base; + struct drm_connector *connector; + struct msm_dp_panel *msm_dp_panel; +}; + +struct msm_dp_mst_connector { + struct drm_connector connector; + struct drm_dp_mst_port *mst_port; + struct msm_dp_mst *dp_mst; + struct msm_dp_panel *dp_panel; +}; + struct msm_dp_mst { struct drm_dp_mst_topology_mgr mst_mgr; + struct msm_dp_mst_bridge *mst_bridge[DP_STREAM_MAX]; struct msm_dp *msm_dp; struct drm_dp_aux *dp_aux; u32 max_streams; @@ -22,6 +61,426 @@ struct msm_dp_mst { struct mutex mst_lock; }; +static struct drm_private_state *msm_dp_mst_duplicate_bridge_state(struct drm_private_obj *obj) +{ + struct msm_dp_mst_bridge_state *mst_bridge_state; + + mst_bridge_state = kmemdup(obj->state, sizeof(*mst_bridge_state), GFP_KERNEL); + if (!mst_bridge_state) + return NULL; + + __drm_atomic_helper_private_obj_duplicate_state(obj, &mst_bridge_state->base); + + return &mst_bridge_state->base; +} + +static void msm_dp_mst_destroy_bridge_state(struct drm_private_obj *obj, + struct drm_private_state *state) +{ + struct msm_dp_mst_bridge_state *mst_bridge_state = + to_dp_mst_bridge_state_priv(state); + + kfree(mst_bridge_state); +} + +static struct drm_private_state * +msm_dp_mst_create_bridge_state(struct drm_private_obj *obj) +{ + struct msm_dp_mst_bridge_state *mst_bridge_state; + + mst_bridge_state = kzalloc_obj(*mst_bridge_state); + if (!mst_bridge_state) + return ERR_PTR(-ENOMEM); + + __drm_atomic_helper_private_obj_create_state(obj, &mst_bridge_state->base); + + return &mst_bridge_state->base; +} + +static const struct drm_private_state_funcs msm_dp_mst_bridge_state_funcs = { + .atomic_create_state = msm_dp_mst_create_bridge_state, + .atomic_duplicate_state = msm_dp_mst_duplicate_bridge_state, + .atomic_destroy_state = msm_dp_mst_destroy_bridge_state, +}; + +static struct msm_dp_mst_bridge_state *msm_dp_mst_br_priv_state(struct drm_atomic_state *st, + struct msm_dp_mst_bridge *bridge) +{ + struct drm_device *dev = bridge->base.dev; + struct drm_private_state *obj_state = drm_atomic_get_private_obj_state(st, &bridge->obj); + + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + + return to_dp_mst_bridge_state_priv(obj_state); +} + +static void msm_dp_mst_update_timeslots(struct msm_dp_mst *mst, + struct msm_dp_mst_bridge *mst_bridge, + struct drm_atomic_state *state, + struct drm_dp_mst_port *port) +{ + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + + mst_state = to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + payload = drm_atomic_get_mst_payload_state(mst_state, port); + + if (!payload) { + DRM_ERROR("MST bridge [%d] update_timeslots failed, null payload\n", + mst_bridge->id); + return; + } + + if (payload->vc_start_slot < 0) + msm_dp_display_set_stream_info(mst->msm_dp, mst_bridge->msm_dp_panel, + mst_bridge->id, 1, 0, 0); + else + msm_dp_display_set_stream_info(mst->msm_dp, mst_bridge->msm_dp_panel, + mst_bridge->id, payload->vc_start_slot, + payload->time_slots, payload->pbn); +} + +static int msm_dp_mst_bridge_pre_enable_part1(struct msm_dp_mst_bridge *dp_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display = dp_bridge->display; + struct msm_dp_mst *mst = dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn = to_dp_mst_connector(dp_bridge->connector); + struct drm_dp_mst_port *port = mst_conn->mst_port; + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + struct msm_dp_panel *dp_panel = mst_conn->dp_panel; + int pbn; + int rc = 0; + + mst_state = drm_atomic_get_new_mst_topology_state(state, &mst->mst_mgr); + + pbn = drm_dp_calc_pbn_mode(dp_panel->msm_dp_mode.drm_mode.clock, + (mst_conn->connector.display_info.bpc * 3) << 4); + + payload = drm_atomic_get_mst_payload_state(mst_state, port); + if (!payload || payload->time_slots <= 0) { + DRM_ERROR("time slots not allocated for conn:%d\n", DP_MST_CONN_ID(dp_bridge)); + rc = -EINVAL; + return rc; + } + + drm_dbg_dp(dp_display->drm_dev, "conn:%d pbn:%d, slots:%d\n", DP_MST_CONN_ID(dp_bridge), + pbn, payload->time_slots); + + drm_dp_mst_update_slots(mst_state, DP_CAP_ANSI_8B10B); + + rc = drm_dp_add_payload_part1(&mst->mst_mgr, mst_state, payload); + if (rc) { + DRM_ERROR("payload allocation failure for conn:%d\n", DP_MST_CONN_ID(dp_bridge)); + return rc; + } + + msm_dp_mst_update_timeslots(mst, dp_bridge, state, port); + + return rc; +} + +static void _msm_dp_mst_bridge_pre_enable_part2(struct msm_dp_mst_bridge *dp_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display = dp_bridge->display; + struct msm_dp_mst *mst = dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn = to_dp_mst_connector(dp_bridge->connector); + struct drm_dp_mst_port *port = mst_conn->mst_port; + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + + drm_dp_check_act_status(&mst->mst_mgr); + + mst_state = to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + payload = drm_atomic_get_mst_payload_state(mst_state, port); + + drm_dp_add_payload_part2(&mst->mst_mgr, payload); + + drm_dbg_dp(dp_display->drm_dev, "MST bridge [%d] _pre enable part-2 complete\n", + dp_bridge->id); +} + +static void msm_dp_mst_bridge_pre_disable_part1(struct msm_dp_mst_bridge *dp_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display = dp_bridge->display; + struct msm_dp_mst *mst = dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn = to_dp_mst_connector(dp_bridge->connector); + struct drm_dp_mst_port *port = mst_conn->mst_port; + struct drm_dp_mst_topology_state *old_mst_state; + struct drm_dp_mst_topology_state *new_mst_state; + const struct drm_dp_mst_atomic_payload *old_payload; + struct drm_dp_mst_atomic_payload *new_payload; + + old_mst_state = drm_atomic_get_old_mst_topology_state(state, &mst->mst_mgr); + new_mst_state = drm_atomic_get_new_mst_topology_state(state, &mst->mst_mgr); + + old_payload = drm_atomic_get_mst_payload_state(old_mst_state, port); + new_payload = drm_atomic_get_mst_payload_state(new_mst_state, port); + + if (!old_payload || !new_payload) { + DRM_ERROR("MST bridge [%d] _pre disable part-1 failed, null payload\n", + dp_bridge->id); + return; + } + + drm_dp_remove_payload_part1(&mst->mst_mgr, new_mst_state, new_payload); + drm_dp_remove_payload_part2(&mst->mst_mgr, new_mst_state, old_payload, new_payload); + + msm_dp_mst_update_timeslots(mst, dp_bridge, state, port); + + drm_dbg_dp(dp_display->drm_dev, "MST bridge [%d] _pre disable part-1 complete\n", + dp_bridge->id); +} + +static void msm_dp_mst_bridge_atomic_pre_enable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + int rc = 0; + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst_bridge_state *mst_bridge_state; + struct msm_dp_mst *dp_mst; + struct msm_dp_panel *msm_dp_panel; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge = to_dp_mst_bridge(drm_bridge); + mst_bridge_state = to_dp_mst_bridge_state(bridge); + dp_display = bridge->display; + dp_mst = dp_display->msm_dp_mst; + + /* to cover cases of bridge_disable/bridge_enable without modeset */ + bridge->connector = mst_bridge_state->connector; + bridge->msm_dp_panel = mst_bridge_state->msm_dp_panel; + + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + msm_dp_panel = bridge->msm_dp_panel; + mutex_lock(&dp_mst->mst_lock); + + rc = msm_dp_display_set_mode_helper(dp_display, state, drm_bridge->encoder, msm_dp_panel); + if (rc) { + DRM_ERROR("Failed to perform a mode set, rc=%d\n", rc); + mutex_unlock(&dp_mst->mst_lock); + return; + } + msm_dp_panel->pbn = drm_dp_calc_pbn_mode(msm_dp_panel->msm_dp_mode.drm_mode.clock, + msm_dp_panel->msm_dp_mode.bpp << 4); + rc = msm_dp_display_prepare(dp_display); + if (rc) { + DRM_ERROR("[%d] DP display pre-enable failed, rc=%d\n", bridge->id, rc); + msm_dp_display_unprepare(dp_display); + mutex_unlock(&dp_mst->mst_lock); + return; + } + + rc = msm_dp_mst_bridge_pre_enable_part1(bridge, state); + if (rc) { + DRM_ERROR("[%d] DP display pre-enable failed, rc=%d\n", bridge->id, rc); + mutex_unlock(&dp_mst->mst_lock); + return; + } + + msm_dp_display_enable_helper(dp_display, bridge->msm_dp_panel); + + _msm_dp_mst_bridge_pre_enable_part2(bridge, state); + + mutex_unlock(&dp_mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "conn:%d mode:%s pre enable done\n", + DP_MST_CONN_ID(bridge), bridge->msm_dp_panel->msm_dp_mode.drm_mode.name); +} + +static void msm_dp_mst_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst *mst; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge = to_dp_mst_bridge(drm_bridge); + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + dp_display = bridge->display; + mst = dp_display->msm_dp_mst; + + mutex_lock(&mst->mst_lock); + + msm_dp_mst_bridge_pre_disable_part1(bridge, state); + + msm_dp_display_disable_helper(dp_display, bridge->msm_dp_panel); + + drm_dp_check_act_status(&mst->mst_mgr); + + mutex_unlock(&mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "MST bridge:%d disable complete\n", bridge->id); +} + +static void msm_dp_mst_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst *mst; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge = to_dp_mst_bridge(drm_bridge); + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + dp_display = bridge->display; + mst = dp_display->msm_dp_mst; + + mutex_lock(&mst->mst_lock); + + msm_dp_display_atomic_post_disable_helper(dp_display, bridge->msm_dp_panel); + + if (!dp_display->mst_active) + msm_dp_display_unprepare(dp_display); + + bridge->connector = NULL; + bridge->msm_dp_panel = NULL; + + mutex_unlock(&mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "MST bridge:%d conn:%d post disable complete\n", + bridge->id, DP_MST_CONN_ID(bridge)); +} + +static int msm_dp_mst_bridge_atomic_check(struct drm_bridge *drm_bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_atomic_state *state = crtc_state->state; + struct drm_connector *connector = conn_state->connector; + struct drm_dp_mst_topology_state *mst_state; + struct msm_dp_mst_connector *mst_conn; + struct msm_dp_mst *mst; + int rc = 0, pbn, slots; + struct msm_dp_mst_bridge_state *mst_bridge_state; + u32 bpp; + + if (!drm_atomic_crtc_needs_modeset(crtc_state) || !crtc_state->enable) + return 0; + + mst_conn = to_dp_mst_connector(connector); + mst = mst_conn->dp_mst; + + bpp = connector->display_info.bpc * 3; + + if (!bpp) + bpp = 24; + + pbn = drm_dp_calc_pbn_mode(crtc_state->mode.clock, bpp << 4); + + mst_state = to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + if (IS_ERR(mst_state)) + return PTR_ERR(mst_state); + + if (!dfixed_trunc(mst_state->pbn_div)) { + mst_state->pbn_div = + drm_dp_get_vc_payload_bw(mst_conn->dp_panel->link_info.rate, + mst_conn->dp_panel->link_info.num_lanes); + } + + slots = drm_dp_atomic_find_time_slots(state, &mst->mst_mgr, mst_conn->mst_port, pbn); + + drm_dbg_dp(drm_bridge->dev, "add slots, conn:%d pbn:%d slots:%d rc:%d\n", + connector->base.id, pbn, slots, rc); + + if (!conn_state->crtc) { + mst_bridge_state = msm_dp_mst_br_priv_state(state, to_dp_mst_bridge(drm_bridge)); + mst_bridge_state->connector = NULL; + mst_bridge_state->msm_dp_panel = NULL; + } + + return 0; +} + +/* DP MST Bridge APIs */ +static const struct drm_bridge_funcs msm_dp_mst_bridge_ops = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_pre_enable = msm_dp_mst_bridge_atomic_pre_enable, + .atomic_disable = msm_dp_mst_bridge_atomic_disable, + .atomic_post_disable = msm_dp_mst_bridge_atomic_post_disable, + .atomic_check = msm_dp_mst_bridge_atomic_check, +}; + +int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, struct drm_encoder *encoder) +{ + int rc = 0; + struct msm_dp_mst_bridge *bridge = NULL; + struct drm_device *dev; + struct msm_dp_mst *mst = dp_display->msm_dp_mst; + int i; + + for (i = 0; i < mst->max_streams; i++) { + if (!mst->mst_bridge[i]->initialized) { + bridge = mst->mst_bridge[i]; + bridge->encoder = encoder; + bridge->initialized = true; + bridge->id = i; + break; + } + } + + if (i == mst->max_streams) { + DRM_ERROR("MST supports only %d bridges\n", mst->max_streams); + rc = -EACCES; + goto end; + } + + dev = dp_display->drm_dev; + bridge->display = dp_display; + bridge->base.encoder = encoder; + bridge->base.type = dp_display->connector_type; + bridge->base.ops = DRM_BRIDGE_OP_MODES; + drm_bridge_add(&bridge->base); + + rc = drm_bridge_attach(encoder, &bridge->base, NULL, 0); + if (rc) { + DRM_ERROR("failed to attach bridge, rc=%d\n", rc); + goto end; + } + + drm_atomic_private_obj_init(dev, &bridge->obj, + &msm_dp_mst_bridge_state_funcs); + + drm_dbg_dp(dp_display->drm_dev, "MST drm bridge init. bridge id:%d\n", i); + + return 0; + +end: + return rc; +} + int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) { struct msm_dp_mst *mst = dp_display->msm_dp_mst; @@ -49,11 +508,16 @@ int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_au return -ENOMEM; memset(&msm_dp_mst->mst_mgr, 0, sizeof(msm_dp_mst->mst_mgr)); - conn_base_id = dp_display->connector->base.id; msm_dp_mst->msm_dp = dp_display; msm_dp_mst->max_streams = max_streams; + for (int i = 0; i < DP_STREAM_MAX; i++) { + msm_dp_mst->mst_bridge[i] = + devm_drm_bridge_alloc(dev->dev, struct msm_dp_mst_bridge, base, + &msm_dp_mst_bridge_ops); + } + msm_dp_mst->dp_aux = drm_aux; ret = drm_dp_mst_topology_mgr_init(&msm_dp_mst->mst_mgr, dev, diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index f347d683e9701..37aa9c350b436 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -357,6 +357,8 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); int msm_dp_mst_register(struct msm_dp *dp_display); +int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, struct drm_encoder *encoder); + #else static inline int __init msm_dp_register(void) { @@ -383,6 +385,11 @@ static inline int msm_dp_mst_register(struct msm_dp *dp_display) return -EINVAL; } +static inline int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, struct drm_encoder *encoder) +{ + return -EINVAL; +} + static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) { } From adbf151af65570fc4ce9afe78262b71bcde38ad0 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 25 Aug 2025 22:16:15 +0800 Subject: [PATCH 0795/1330] FROMLIST: drm/msm/dp: wire MST helpers into atomic check and commit paths Call drm_dp_mst_atomic_check() from msm_atomic_check() so MST-specific state, such as connector and topology changes, is validated as part of the atomic check. Hook the MST helpers into atomic_commit_setup() and atomic_commit_tail() to support non-blocking atomic commits for DisplayPort MST, and ensure MST commits properly wait for dependencies. For SST, non-blocking commits are already handled via commit_tail(), which waits for dependencies in the DRM core. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-35-b20518dea8de@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov (cherry picked from commit 362ac4e780ebdea33ef6e3e6a39bb0d2fb84960b) --- drivers/gpu/drm/msm/msm_atomic.c | 9 ++++++++- drivers/gpu/drm/msm/msm_kms.c | 2 ++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 87a91148a731d..ea064aa6d8fc1 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -4,6 +4,7 @@ * Author: Rob Clark */ +#include #include #include @@ -207,7 +208,11 @@ int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) if (ret) return ret; - return drm_atomic_helper_check(dev, state); + ret = drm_atomic_helper_check(dev, state); + if (ret) + return ret; + + return drm_dp_mst_atomic_check(state); } void msm_atomic_commit_tail(struct drm_atomic_state *state) @@ -221,6 +226,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state) trace_msm_atomic_commit_tail_start(async, crtc_mask); + drm_dp_mst_atomic_wait_for_dependencies(state); + kms->funcs->enable_commit(kms); /* diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index e5d0ea6294484..a8f5fbb3239d1 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -29,6 +30,7 @@ static const struct drm_mode_config_funcs mode_config_funcs = { static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { .atomic_commit_tail = msm_atomic_commit_tail, + .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, }; static irqreturn_t msm_irq(int irq, void *arg) From 3c572a5ff2b2be1a1e3922ce716fb96a01d47f6c Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:16 +0800 Subject: [PATCH 0796/1330] FROMLIST: drm/msm/dp: add connector abstraction for DP MST Introduce an MST connector abstraction for DP MST, with each MST connector associated with a DP panel and connected through a DRM bridge to an MST encoder. The connector is only used for MST helper callbacks, such as detect, get_modes, and get_encoder. Display enable/disable, hotplug handling, and modeset sequencing continue to be handled by the bridge path. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-36-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 44240affae534ea1baa0a38225481e4b06feb426) --- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 305 ++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/dp_mst_drm.c index 69f8faa03a98f..f6c2d6281bca7 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "dp_mst_drm.h" #include "dp_panel.h" @@ -496,6 +497,309 @@ int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) return rc; } +/* DP MST Connector OPs */ +static int +msm_dp_mst_connector_detect(struct drm_connector *connector, + struct drm_modeset_acquire_ctx *ctx, + bool force) +{ + struct msm_dp_mst_connector *mst_conn = to_dp_mst_connector(connector); + struct msm_dp_mst *mst = mst_conn->dp_mst; + struct msm_dp *dp_display = mst->msm_dp; + struct device *dev = dp_display->drm_dev->dev; + enum drm_connector_status status = connector_status_disconnected; + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + return status; + + if (dp_display->mst_active) + status = drm_dp_mst_detect_port(connector, + ctx, &mst->mst_mgr, mst_conn->mst_port); + + pm_runtime_put_autosuspend(dev); + + return status; +} + +static int msm_dp_mst_connector_get_modes(struct drm_connector *connector) +{ + struct msm_dp_mst_connector *mst_conn = to_dp_mst_connector(connector); + struct msm_dp_mst *mst = mst_conn->dp_mst; + const struct drm_edid *drm_edid; + + drm_edid = drm_dp_mst_edid_read(connector, &mst->mst_mgr, mst_conn->mst_port); + drm_edid_connector_update(connector, drm_edid); + + return drm_edid_connector_add_modes(connector); +} + +static enum drm_mode_status msm_dp_mst_connector_mode_valid(struct drm_connector *connector, + const struct drm_display_mode *mode) +{ + struct msm_dp_mst_connector *mst_conn; + struct drm_dp_mst_port *mst_port; + struct msm_dp *dp_display; + int required_pbn; + + if (drm_connector_is_unregistered(connector)) + return 0; + + mst_conn = to_dp_mst_connector(connector); + mst_port = mst_conn->mst_port; + dp_display = mst_conn->dp_mst->msm_dp; + + if (!mst_port) + return MODE_ERROR; + + required_pbn = drm_dp_calc_pbn_mode(mode->clock, (6 * 3) << 4); + + if (required_pbn > mst_port->full_pbn) { + drm_dbg_dp(dp_display->drm_dev, "mode:%s not supported.\n", mode->name); + return MODE_CLOCK_HIGH; + } + + return msm_dp_display_mode_valid(dp_display, &connector->display_info, mode); +} + +static struct drm_encoder * +msm_dp_mst_atomic_best_encoder(struct drm_connector *connector, struct drm_atomic_state *state) +{ + struct msm_dp_mst_connector *mst_conn = to_dp_mst_connector(connector); + struct msm_dp_mst *mst = mst_conn->dp_mst; + struct msm_dp *dp_display = mst->msm_dp; + struct drm_encoder *enc = NULL; + struct msm_dp_mst_bridge_state *mst_bridge_state; + u32 i; + struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state, + connector); + + if (conn_state && conn_state->best_encoder) + return conn_state->best_encoder; + + for (i = 0; i < mst->max_streams; i++) { + mst_bridge_state = msm_dp_mst_br_priv_state(state, mst->mst_bridge[i]); + if (IS_ERR(mst_bridge_state)) + goto end; + + if (mst_bridge_state->connector == connector) { + enc = mst->mst_bridge[i]->encoder; + goto end; + } + } + + for (i = 0; i < mst->max_streams; i++) { + mst_bridge_state = msm_dp_mst_br_priv_state(state, mst->mst_bridge[i]); + + if (!mst_bridge_state->connector) { + mst_bridge_state->connector = connector; + mst_bridge_state->msm_dp_panel = mst_conn->dp_panel; + enc = mst->mst_bridge[i]->encoder; + break; + } + } + +end: + if (enc) + drm_dbg_dp(dp_display->drm_dev, "MST connector:%d atomic best encoder:%d\n", + connector->base.id, i); + else + drm_dbg_dp(dp_display->drm_dev, "MST connector:%d atomic best encoder failed\n", + connector->base.id); + + return enc; +} + +static int msm_dp_mst_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + int rc = 0, slots; + struct drm_connector_state *old_conn_state; + struct drm_connector_state *new_conn_state; + struct drm_crtc *old_crtc; + struct drm_crtc_state *crtc_state; + struct msm_dp_mst_bridge *bridge; + struct msm_dp_mst_bridge_state *mst_bridge_state; + struct drm_bridge *drm_bridge; + struct msm_dp_mst_connector *mst_conn = to_dp_mst_connector(connector); + struct msm_dp_mst *mst = mst_conn->dp_mst; + struct msm_dp *dp_display = mst->msm_dp; + struct drm_dp_mst_atomic_payload *payload; + struct drm_dp_mst_topology_state *mst_state; + + if (!state) + return rc; + + new_conn_state = drm_atomic_get_new_connector_state(state, connector); + if (!new_conn_state) + return rc; + + old_conn_state = drm_atomic_get_old_connector_state(state, connector); + if (!old_conn_state) + goto end; + + old_crtc = old_conn_state->crtc; + if (!old_crtc) + goto end; + + crtc_state = drm_atomic_get_new_crtc_state(state, old_crtc); + + /* attempt to release vcpi slots on a modeset change for crtc state */ + if (drm_atomic_crtc_needs_modeset(crtc_state)) { + if (WARN_ON(!old_conn_state->best_encoder)) { + rc = -EINVAL; + goto end; + } + + drm_bridge = drm_bridge_chain_get_first_bridge(old_conn_state->best_encoder); + if (WARN_ON(!drm_bridge)) { + rc = -EINVAL; + goto end; + } + bridge = to_dp_mst_bridge(drm_bridge); + + mst_bridge_state = msm_dp_mst_br_priv_state(state, bridge); + + mst_state = to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + + payload = drm_atomic_get_mst_payload_state(mst_state, mst_conn->mst_port); + + slots = payload->time_slots; + if (slots > 0) { + rc = drm_dp_atomic_release_time_slots(state, + &mst->mst_mgr, + mst_conn->mst_port); + if (rc) { + DRM_ERROR("failed releasing %d vcpi slots %d\n", slots, rc); + goto end; + } + } + + if (!new_conn_state->crtc) { + /* for cases where crtc is not disabled the slots are not + * freed by drm_dp_atomic_release_time_slots. this results + * in subsequent atomic_check failing since internal slots + * were freed but not the DP MST mgr's + */ + mst_bridge_state->connector = NULL; + mst_bridge_state->msm_dp_panel = NULL; + drm_dbg_dp(dp_display->drm_dev, "clear best encoder: %d\n", bridge->id); + } + } + +end: + drm_dbg_dp(dp_display->drm_dev, "mst connector:%d atomic check ret %d\n", + connector->base.id, rc); + return rc; +} + +static void dp_mst_connector_destroy(struct drm_connector *connector) +{ + struct msm_dp_mst_connector *mst_conn = to_dp_mst_connector(connector); + + drm_connector_cleanup(connector); + drm_dp_mst_put_port_malloc(mst_conn->mst_port); + kfree(mst_conn); +} + +/* DRM MST callbacks */ +static const struct drm_connector_helper_funcs msm_dp_drm_mst_connector_helper_funcs = { + .get_modes = msm_dp_mst_connector_get_modes, + .detect_ctx = msm_dp_mst_connector_detect, + .mode_valid = msm_dp_mst_connector_mode_valid, + .atomic_best_encoder = msm_dp_mst_atomic_best_encoder, + .atomic_check = msm_dp_mst_connector_atomic_check, +}; + +static const struct drm_connector_funcs msm_dp_drm_mst_connector_funcs = { + .reset = drm_atomic_helper_connector_reset, + .destroy = dp_mst_connector_destroy, + .fill_modes = drm_helper_probe_single_connector_modes, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static struct drm_connector * +msm_dp_mst_add_connector(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, const char *pathprop) +{ + struct msm_dp_mst *dp_mst; + struct drm_device *dev; + struct msm_dp *dp_display; + struct msm_dp_mst_connector *mst_conn; + struct drm_connector *connector; + int rc, i; + + dp_mst = container_of(mgr, struct msm_dp_mst, mst_mgr); + + dp_display = dp_mst->msm_dp; + dev = dp_display->drm_dev; + + mst_conn = kzalloc_obj(*mst_conn); + + if (!mst_conn) + return NULL; + + drm_modeset_lock_all(dev); + + connector = &mst_conn->connector; + rc = drm_connector_dynamic_init(dev, connector, + &msm_dp_drm_mst_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort, NULL); + if (rc) { + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + + mst_conn->dp_panel = msm_dp_display_get_panel(dp_display); + if (!mst_conn->dp_panel) { + DRM_ERROR("failed to get dp_panel for connector\n"); + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + + mst_conn->dp_panel->connector = connector; + mst_conn->dp_mst = dp_mst; + + drm_connector_helper_add(connector, &msm_dp_drm_mst_connector_helper_funcs); + + if (connector->funcs->reset) + connector->funcs->reset(connector); + + /* add all encoders as possible encoders */ + for (i = 0; i < dp_mst->max_streams; i++) { + rc = drm_connector_attach_encoder(connector, dp_mst->mst_bridge[i]->encoder); + + if (rc) { + DRM_ERROR("failed to attach encoder to connector, %d\n", rc); + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + } + + mst_conn->mst_port = port; + drm_dp_mst_get_port_malloc(mst_conn->mst_port); + + drm_object_attach_property(&connector->base, + dev->mode_config.path_property, 0); + drm_object_attach_property(&connector->base, + dev->mode_config.tile_property, 0); + drm_connector_set_path_property(connector, pathprop); + drm_modeset_unlock_all(dev); + + drm_dbg_dp(dp_display->drm_dev, "add MST connector id:%d\n", connector->base.id); + + return connector; +} + +static const struct drm_dp_mst_topology_cbs msm_dp_mst_drm_cbs = { + .add_connector = msm_dp_mst_add_connector, +}; + int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_aux *drm_aux) { struct drm_device *dev = dp_display->drm_dev; @@ -508,6 +812,7 @@ int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_au return -ENOMEM; memset(&msm_dp_mst->mst_mgr, 0, sizeof(msm_dp_mst->mst_mgr)); + msm_dp_mst->mst_mgr.cbs = &msm_dp_mst_drm_cbs; conn_base_id = dp_display->connector->base.id; msm_dp_mst->msm_dp = dp_display; msm_dp_mst->max_streams = max_streams; From 57df788bc58194a03146b49f82e1941daba57706 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:17 +0800 Subject: [PATCH 0797/1330] FROMLIST: drm/msm/dp: add HPD callback for dp MST Add HPD callback for the MST module which shall be invoked from the dp_display's HPD handler to perform MST specific operations in case of HPD. In MST case, route the HPD messages to MST module. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-37-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 9115cc691ea7293fd68e0a8a2cbb8d785f420dae) --- drivers/gpu/drm/msm/dp/dp_display.c | 23 +++++++++++++++---- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 34 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 1 + 3 files changed, 54 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 329938ac6439c..a440c067568d4 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -455,6 +455,9 @@ static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp) dp->msm_dp_display.connector_type, dp->link->sink_count); + if (dp->plugged && dp->msm_dp_display.mst_active) + return 0; + mutex_lock(&dp->plugged_lock); ret = pm_runtime_resume_and_get(&pdev->dev); @@ -557,12 +560,19 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp) { u32 sink_request; int rc = 0; + struct msm_dp *msm_dp_display = &dp->msm_dp_display; /* irq_hpd can happen at either connected or disconnected state */ drm_dbg_dp(dp->drm_dev, "Before, type=%d, sink_count=%d\n", dp->msm_dp_display.connector_type, dp->link->sink_count); + if (msm_dp_display->mst_active) { + if (msm_dp_aux_is_link_connected(dp->aux) != ISR_DISCONNECTED) + msm_dp_mst_display_hpd_irq(&dp->msm_dp_display); + return 0; + } + /* check for any test request issued by sink */ rc = msm_dp_link_process_request(dp->link); if (!rc) { @@ -1122,9 +1132,13 @@ static irqreturn_t msm_dp_display_irq_thread(int irq, void *dev_id) connector_status_connected); /* Send HPD as connected and distinguish it in the notifier */ - if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) - drm_bridge_hpd_notify(dp->msm_dp_display.bridge, - connector_status_connected); + if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) { + if (dp->msm_dp_display.mst_active) + msm_dp_irq_hpd_handle(dp); + else + drm_bridge_hpd_notify(dp->msm_dp_display.bridge, + connector_status_connected); + } ret = IRQ_HANDLED; @@ -1790,7 +1804,8 @@ void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, msm_dp_hpd_plug_handle(dp); } } else { - msm_dp_hpd_unplug_handle(dp); + if (hpd_link_status == ISR_DISCONNECTED) + msm_dp_hpd_unplug_handle(dp); } pm_runtime_put_sync(&msm_dp_display->pdev->dev); diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/dp_mst_drm.c index f6c2d6281bca7..a6cf700378f1d 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -497,6 +497,40 @@ int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) return rc; } +/* DP MST HPD IRQ callback */ +void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display) +{ + int rc; + struct msm_dp_mst *mst = dp_display->msm_dp_mst; + u8 ack[8] = {}; + u8 esi[4]; + unsigned int esi_res = DP_SINK_COUNT_ESI + 1; + bool handled; + + rc = drm_dp_dpcd_read_data(mst->dp_aux, DP_SINK_COUNT_ESI, esi, 4); + if (rc < 0) { + DRM_ERROR("DPCD sink status read failed, rlen=%d\n", rc); + return; + } + + drm_dbg_dp(dp_display->drm_dev, "MST irq: esi1[0x%x] esi2[0x%x] esi3[%x]\n", + esi[1], esi[2], esi[3]); + + rc = drm_dp_mst_hpd_irq_handle_event(&mst->mst_mgr, esi, ack, &handled); + + /* ack the request */ + if (handled) { + rc = drm_dp_dpcd_write_byte(mst->dp_aux, esi_res, ack[1]); + if (rc < 0) { + DRM_ERROR("DPCD esi_res failed. rc=%d\n", rc); + return; + } + + drm_dp_mst_hpd_irq_send_new_request(&mst->mst_mgr); + } + drm_dbg_dp(dp_display->drm_dev, "MST display hpd_irq handled:%d rc:%d\n", handled, rc); +} + /* DP MST Connector OPs */ static int msm_dp_mst_connector_detect(struct drm_connector *connector, diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/dp_mst_drm.h index 5d411529f6819..08e145399cfc7 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -9,5 +9,6 @@ int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_aux *drm_aux); int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state); +void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display); #endif /* _DP_MST_DRM_H_ */ From 39da6685d20c24e3aaeba90ea57ad344ebc4082a Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 25 Aug 2025 22:16:22 +0800 Subject: [PATCH 0798/1330] FROMLIST: drm/msm/dpu: use msm_dp_get_mst_intf_id() to get the intf id Use msm_dp_get_mst_intf_id() to get the interface ID for the DP MST controller as the intf_id is unique for each MST stream of each DP controller. For DSI/eDP/DP SST, the stream_id is always 0, so existing behavior remains unchanged. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260410-msm-dp-mst-v4-38-b20518dea8de@oss.qualcomm.com/ (cherry picked from commit 2b42252f7d560af98eff354867de94a5085a0155) --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +++++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 ++++ 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index eba1d52211f68..d6813107a27df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1438,18 +1438,21 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, struct dpu_rm *dpu_rm, - enum dpu_intf_type type, u32 controller_id) + struct msm_display_info *disp_info, u32 controller_id) { - int i = 0; + int i = 0, cnt = 0; + int stream_id = disp_info->stream_id; - if (type == INTF_WB) + if (disp_info->intf_type == INTF_WB) return NULL; + DPU_DEBUG("intf_type 0x%x controller_id %d stream_id %d\n", + disp_info->intf_type, controller_id, stream_id); for (i = 0; i < catalog->intf_count; i++) { - if (catalog->intf[i].type == type - && catalog->intf[i].controller_id == controller_id) { - return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); - } + if (catalog->intf[i].type == disp_info->intf_type && + controller_id == catalog->intf[i].controller_id) + if (cnt++ == stream_id) + return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); } return NULL; @@ -2675,8 +2678,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, i, controller_id, phys_params.split_role); phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, - disp_info->intf_type, - controller_id); + disp_info, controller_id); if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index ca1ca2e51d7ea..2eb4c39b111c1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -28,6 +28,7 @@ * @h_tile_instance: Controller instance used per tile. Number of elements is * based on num_of_h_tiles * @is_cmd_mode Boolean to indicate if the CMD mode is requested + * @stream_id stream id for which the interface needs to be acquired * @vsync_source: Source of the TE signal for DSI CMD devices */ struct msm_display_info { @@ -35,6 +36,7 @@ struct msm_display_info { uint32_t num_of_h_tiles; uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; bool is_cmd_mode; + int stream_id; enum dpu_vsync_source vsync_source; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 1f00fa2eb6ea1..c557430e0dfb1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -612,6 +612,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, info.h_tile_instance[info.num_of_h_tiles++] = other; info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->kms->dsi[i]); + info.stream_id = 0; rc = dpu_kms_dsi_set_te_source(&info, priv->kms->dsi[i]); if (rc) { @@ -687,6 +688,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, } for (stream_id = 0; stream_id < stream_cnt; stream_id++) { + info.stream_id = stream_id; encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); if (IS_ERR(encoder)) { DPU_ERROR("encoder init failed for dp mst display\n"); @@ -720,6 +722,7 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *dev, info.num_of_h_tiles = 1; info.h_tile_instance[0] = 0; info.intf_type = INTF_HDMI; + info.stream_id = 0; encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info); if (IS_ERR(encoder)) { @@ -752,6 +755,7 @@ static int _dpu_kms_initialize_writeback(struct drm_device *dev, /* use only WB idx 2 instance for DPU */ info.h_tile_instance[0] = wb_idx; info.intf_type = INTF_WB; + info.stream_id = 0; maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth; From bbc32b22e698e5c82aaba5af8d84c10a8067a0f1 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 25 Aug 2025 22:16:24 +0800 Subject: [PATCH 0799/1330] FROMLIST: drm/msm/dp: Add MST stream support for SA8775P DP controller 0 and 1 This change enables SA8775P support for Multi-Stream Transport (MST), allowing each controller to handle up to two or four DisplayPort streams. As all necessary code for MST support was already implemented in the previous series of patches. Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20250825-msm-dp-mst-v3-38-01faacfcdedd@oss.qualcomm.com/ (cherry picked from commit 2fbdd74ad152cbed32ae7fb4d4be2bec77f2f192) --- drivers/gpu/drm/msm/dp/dp_display.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index a440c067568d4..a9f781a6c7431 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -115,8 +115,10 @@ static const struct msm_dp_desc msm_dp_desc_glymur[] = { }; static const struct msm_dp_desc msm_dp_desc_sa8775p[] = { - { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, - { .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true }, + { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true, + .mst_streams = 4}, + { .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true, + .mst_streams = 2}, { .io_start = 0x22154000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, { .io_start = 0x2215c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true }, {} From 9eeb1c0b9eff1dfd27026bc0eb67cef137db17b6 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Fri, 8 May 2026 09:36:34 +0530 Subject: [PATCH 0800/1330] WORKAROUND: power: reset: reboot-mode: fix NULL deref when dev is not set reboot_mode_create_device() and reboot_mode_unregister_device() unconditionally dereference reboot->dev->driver->name to name the sysfs device. psci_init_vendor_reset() allocates a reboot_mode_driver with kzalloc (so reboot->dev == NULL) and never sets reboot->dev, causing a NULL pointer dereference at boot: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000068 pc : reboot_mode_register+0x334/0x3b8 psci_init_vendor_reset+0xdc/0x128 Kernel panic - not syncing: Oops: Fatal exception The offset 0x68 is the 'driver' pointer inside struct device on arm64, confirming that reboot->dev itself is NULL. Fix this by adding a 'name' field to struct reboot_mode_driver. reboot_mode_create_device() and reboot_mode_unregister_device() now prefer reboot->name; they fall back to reboot->dev->driver->name only when reboot->name is NULL, and return -EINVAL / return early if neither source is available. Set reboot->name = "psci" in psci_init_vendor_reset() so the sysfs device is correctly named. Existing device-based callers (nvmem-reboot-mode, syscon-reboot-mode, qcom-pon) are unaffected: they set reboot->dev before calling devm_reboot_mode_register(), so the fallback path is taken as before. Fixes: cfaf0a90789a ("power: reset: reboot-mode: Expose sysfs for registered reboot_modes") Fixes: 614b17a3ce6e ("firmware: psci: Implement vendor-specific resets as reboot-mode") Reported-by: LAVA job 91409 Signed-off-by: Salendarsingh Gaud (cherry picked from commit 2d42c35af66ed0db002e2d2d8481719dd05b804b) --- drivers/firmware/psci/psci.c | 2 +- drivers/power/reset/reboot-mode.c | 73 ++++++++++++++++++++++++------- include/linux/reboot-mode.h | 3 +- 3 files changed, 59 insertions(+), 19 deletions(-) diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c index ff82e7f4c27d1..bbed7f8dca170 100644 --- a/drivers/firmware/psci/psci.c +++ b/drivers/firmware/psci/psci.c @@ -616,7 +616,7 @@ static int __init psci_init_vendor_reset(void) } reboot->write = psci_set_vendor_sys_reset2; - reboot->driver_name = "psci"; + reboot->name = "psci"; ret = reboot_mode_register(reboot, of_fwnode_handle(np)); if (ret) diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c index 582aa7f8ed7fa..d1e3b81f889b7 100644 --- a/drivers/power/reset/reboot-mode.c +++ b/drivers/power/reset/reboot-mode.c @@ -72,11 +72,19 @@ static ssize_t reboot_modes_show(struct device *dev, struct device_attribute *at { struct reboot_mode_driver *reboot; struct mode_info *info; - ssize_t size = 0; + const char *dev_name; + int ret; + + dev_name = reboot->name; + if (!dev_name) { + if (!reboot->dev || !reboot->dev->driver) + return -EINVAL; + dev_name = reboot->dev->driver->name; + } - reboot = (struct reboot_mode_driver *)dev_get_drvdata(dev); - if (!reboot) - return -ENODATA; + priv = kzalloc_obj(*priv, GFP_KERNEL); + if (!priv) + return -ENOMEM; list_for_each_entry(info, &reboot->head, list) size += sysfs_emit_at(buf, size, "%s ", info->mode); @@ -86,18 +94,12 @@ static ssize_t reboot_modes_show(struct device *dev, struct device_attribute *at return size; } - return -ENODATA; -} -static DEVICE_ATTR_RO(reboot_modes); - -static int create_reboot_mode_device(struct reboot_mode_driver *reboot) -{ - int ret = 0; - - if (!rb_class) { - rb_class = class_create("reboot-mode"); - if (IS_ERR(rb_class)) - return PTR_ERR(rb_class); + priv->reboot_mode_device = device_create(&reboot_mode_class, NULL, 0, + (void *)priv, "%s", + dev_name); + if (IS_ERR(priv->reboot_mode_device)) { + ret = PTR_ERR(priv->reboot_mode_device); + goto error; } reboot->reboot_dev = device_create(rb_class, NULL, 0, (void *)reboot, reboot->driver_name); @@ -200,6 +202,45 @@ int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle } EXPORT_SYMBOL_GPL(reboot_mode_register); +static int reboot_mode_match_by_name(struct device *dev, const void *data) +{ + const char *name = data; + + if (!dev || !data) + return 0; + + return dev_name(dev) && strcmp(dev_name(dev), name) == 0; +} + +static inline void reboot_mode_unregister_device(struct reboot_mode_driver *reboot) +{ + struct reboot_mode_sysfs_data *priv; + struct device *reboot_mode_device; + const char *dev_name; + + dev_name = reboot->name; + if (!dev_name) { + if (!reboot->dev || !reboot->dev->driver) + return; + dev_name = reboot->dev->driver->name; + } + + reboot_mode_device = class_find_device(&reboot_mode_class, NULL, dev_name, + reboot_mode_match_by_name); + + if (!reboot_mode_device) + return; + + priv = dev_get_drvdata(reboot_mode_device); + device_unregister(reboot_mode_device); + + if (!priv) + return; + + reboot_mode_release_list(priv); + kfree(priv); +} + /** * reboot_mode_unregister - unregister a reboot mode driver * @reboot: reboot mode driver diff --git a/include/linux/reboot-mode.h b/include/linux/reboot-mode.h index 81c149edf40fb..56581199af234 100644 --- a/include/linux/reboot-mode.h +++ b/include/linux/reboot-mode.h @@ -7,8 +7,7 @@ struct reboot_mode_driver { struct device *dev; - struct device *reboot_dev; - const char *driver_name; + const char *name; struct list_head head; int (*write)(struct reboot_mode_driver *reboot, u64 magic); struct notifier_block reboot_notifier; From 027b2d37012086e396fa25aac78584f95fa1670e Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Tue, 7 Apr 2026 09:01:05 +0530 Subject: [PATCH 0801/1330] FROMLIST: wifi: ath12k: add channel 177 to the 5 GHz channel list Add support for 5 GHz channel 177 with a center frequency of 5885 MHz and Operating Class 125 per IEEE Std 802.11-2024 Table E-4. Channels 169, 173, and 177 are in the 5.9 GHz band and must be disabled when 5.9 GHz service bit is not supported. The 5.9 GHz band is only permitted for WLAN operation under FCC regulations. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Link: https://lore.kernel.org/ath12k/20260415063857.2462256-1-yintang@qti.qualcomm.com Signed-off-by: Yingying Tang (cherry picked from commit ea4373ad8c68734d030589028bec154f49f70ec7) --- drivers/net/wireless/ath/ath12k/core.h | 4 ++-- drivers/net/wireless/ath/ath12k/dp_rx.c | 11 +++++++++-- drivers/net/wireless/ath/ath12k/mac.c | 26 +++++++++++++++++++++++++ drivers/net/wireless/ath/ath12k/wmi.h | 1 + 4 files changed, 38 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h index 490c8a20028fa..f3fe9565d4767 100644 --- a/drivers/net/wireless/ath/ath12k/core.h +++ b/drivers/net/wireless/ath/ath12k/core.h @@ -541,8 +541,8 @@ struct ath12k_sta { #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) -#define ATH12K_NUM_CHANS 101 -#define ATH12K_MAX_5GHZ_CHAN 173 +#define ATH12K_NUM_CHANS 102 +#define ATH12K_MAX_5GHZ_CHAN 177 static inline bool ath12k_is_2ghz_channel_freq(u32 freq) { diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.c b/drivers/net/wireless/ath/ath12k/dp_rx.c index 40d85d1689750..de16bff6e0c1c 100644 --- a/drivers/net/wireless/ath/ath12k/dp_rx.c +++ b/drivers/net/wireless/ath/ath12k/dp_rx.c @@ -17,6 +17,11 @@ #include "dp_mon.h" #include "debugfs_htt_stats.h" +#define ATH12K_2GHZ_MIN_CHAN_NUM 1 +#define ATH12K_2GHZ_MAX_CHAN_NUM 14 +#define ATH12K_5GHZ_MIN_CHAN_NUM 36 +#define ATH12K_5GHZ_MAX_CHAN_NUM 177 + static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, struct ath12k_dp_rx_tid_rxq *rx_tid); @@ -1290,9 +1295,11 @@ void ath12k_dp_rx_h_ppdu(struct ath12k_pdev_dp *dp_pdev, center_freq <= ATH12K_MAX_6GHZ_FREQ) { rx_status->band = NL80211_BAND_6GHZ; rx_status->freq = center_freq; - } else if (channel_num >= 1 && channel_num <= 14) { + } else if (channel_num >= ATH12K_2GHZ_MIN_CHAN_NUM && + channel_num <= ATH12K_2GHZ_MAX_CHAN_NUM) { rx_status->band = NL80211_BAND_2GHZ; - } else if (channel_num >= 36 && channel_num <= 173) { + } else if (channel_num >= ATH12K_5GHZ_MIN_CHAN_NUM && + channel_num <= ATH12K_5GHZ_MAX_CHAN_NUM) { rx_status->band = NL80211_BAND_5GHZ; } diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c index dd9a7ddb66e68..6c5890637cf53 100644 --- a/drivers/net/wireless/ath/ath12k/mac.c +++ b/drivers/net/wireless/ath/ath12k/mac.c @@ -51,6 +51,9 @@ .max_power = 30, \ } +#define ATH12K_5_9_GHZ_MIN_FREQ 5845 +#define ATH12K_5_9_GHZ_MAX_FREQ 5885 + static const struct ieee80211_channel ath12k_2ghz_channels[] = { CHAN2G(1, 2412, 0), CHAN2G(2, 2417, 0), @@ -96,6 +99,7 @@ static const struct ieee80211_channel ath12k_5ghz_channels[] = { CHAN5G(165, 5825, 0), CHAN5G(169, 5845, 0), CHAN5G(173, 5865, 0), + CHAN5G(177, 5885, 0), }; static const struct ieee80211_channel ath12k_6ghz_channels[] = { @@ -13891,6 +13895,26 @@ static int ath12k_mac_update_band(struct ath12k *ar, return 0; } +static void ath12k_mac_update_5_9_ghz_ch_list(struct ath12k *ar, + struct ieee80211_supported_band *band) +{ + int i; + + if (test_bit(WMI_TLV_SERVICE_5_9GHZ_SUPPORT, + ar->ab->wmi_ab.svc_map)) + return; + + guard(spinlock_bh)(&ar->ab->base_lock); + if (ar->ab->dfs_region != ATH12K_DFS_REG_FCC) + return; + + for (i = 0; i < band->n_channels; i++) { + if (band->channels[i].center_freq >= ATH12K_5_9_GHZ_MIN_FREQ && + band->channels[i].center_freq <= ATH12K_5_9_GHZ_MAX_FREQ) + band->channels[i].flags |= IEEE80211_CHAN_DISABLED; + } +} + static int ath12k_mac_setup_channels_rates(struct ath12k *ar, u32 supported_bands, struct ieee80211_supported_band *bands[]) @@ -14024,6 +14048,8 @@ static int ath12k_mac_setup_channels_rates(struct ath12k *ar, band->n_bitrates = ath12k_a_rates_size; band->bitrates = ath12k_a_rates; + ath12k_mac_update_5_9_ghz_ch_list(ar, band); + if (ab->hw_params->single_pdev_only) { phy_id = ath12k_get_phy_id(ar, WMI_HOST_WLAN_5GHZ_CAP); reg_cap = &ab->hal_reg_cap[phy_id]; diff --git a/drivers/net/wireless/ath/ath12k/wmi.h b/drivers/net/wireless/ath/ath12k/wmi.h index 0bf0a7941cd3c..0d78eb204d8eb 100644 --- a/drivers/net/wireless/ath/ath12k/wmi.h +++ b/drivers/net/wireless/ath/ath12k/wmi.h @@ -2259,6 +2259,7 @@ enum wmi_tlv_service { WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, WMI_TLV_SERVICE_EXT2_MSG = 220, WMI_TLV_SERVICE_BEACON_PROTECTION_SUPPORT = 244, + WMI_TLV_SERVICE_5_9GHZ_SUPPORT = 247, WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, From e6f5de905823c305841202689417c84124a8f1a4 Mon Sep 17 00:00:00 2001 From: Baochen Qiang Date: Mon, 27 Apr 2026 13:51:41 +0800 Subject: [PATCH 0802/1330] FROMLIST: wifi: ath12k: fix peer_id usage in normal RX path ath12k_dp_rx_deliver_msdu() currently uses hal_rx_desc_data::peer_id parsed from mpdu_start descriptor to do peer lookup. However In an A-MSDU aggregation scenario, hardware only populates mpdu_start descriptor for the first sub-msdu, but not the following ones. In that case peer_id could be invalid, leading to peer lookup failure: ath12k_wifi7_pci 0000:06:00.0: rx skb 00000000c391c041 len 1532 peer (null) 0 ucast sn 0 eht320 rate_idx 12 vht_nss 2 freq 6105 band 3 flag 0x40d1a fcs-err 0 mic-err 0 amsdu-more 0 As a result pubsta is NULL and parts of ieee80211_rx_status structure are left uninitialized, which may cause unexpected behavior. Fix it by switching the normal RX path to use ath12k_skb_rxcb::peer_id which is parsed from REO ring's rx_mpdu_desc and is always valid. hal_rx_desc_data::peer_id is still used in ath12k_wifi7_dp_rx_frag_h_mpdu(), which is safe since A-MSDU aggregation does not occur for fragmented frames. Similarly, ath12k_skb_rxcb::peer_id may be overwritten by hal_rx_desc_data::peer_id in ath12k_wifi7_dp_rx_h_mpdu(), which only handles non-aggregated multicast/broadcast traffic. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Link: https://lore.kernel.org/all/20260427-ath12k-fix-peer-id-source-v1-1-b5f701fb8e88@oss.qualcomm.com Fixes: 11157e0910fd ("wifi: ath12k: Use ath12k_dp_peer in per packet Tx & Rx paths") Signed-off-by: Baochen Qiang (cherry picked from commit 2fef133500b06af9fc65011c52948a8fd51a50ce) --- drivers/net/wireless/ath/ath12k/dp_rx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.c b/drivers/net/wireless/ath/ath12k/dp_rx.c index de16bff6e0c1c..2f987f76612c9 100644 --- a/drivers/net/wireless/ath/ath12k/dp_rx.c +++ b/drivers/net/wireless/ath/ath12k/dp_rx.c @@ -1348,7 +1348,7 @@ void ath12k_dp_rx_deliver_msdu(struct ath12k_pdev_dp *dp_pdev, struct napi_struc bool is_mcbc = rxcb->is_mcbc; bool is_eapol = rxcb->is_eapol; - peer = ath12k_dp_peer_find_by_peerid(dp_pdev, rx_info->peer_id); + peer = ath12k_dp_peer_find_by_peerid(dp_pdev, rxcb->peer_id); pubsta = peer ? peer->sta : NULL; From 011e0cbc7bd376672f9f1009f655f5098928c253 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Sun, 12 Apr 2026 21:23:17 +0800 Subject: [PATCH 0803/1330] FROMLIST: wifi: ath12k: fix TLV32 length mask HAL_TLV_HDR_LEN was using the wrong bitmask; fix it to cover bits [21:10]. Also drop HAL_SRNG_TLV_HDR_{TAG,LEN} and use the generic TLV header bit definitions for TLV32/TLV64 encode/decode to avoid redundant macros. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0.c2-00068-QCACOLSWPL_V1_TO_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: d889913205cf ("wifi: ath12k: driver for Qualcomm Wi-Fi 7 devices") Signed-off-by: Miaoqing Pan Link: https://lore.kernel.org/linux-wireless/20260509025819.1641630-2-miaoqing.pan@oss.qualcomm.com/ (cherry picked from commit fcd7afbccd1e2444a0a02441053c81cf2397c494) --- drivers/net/wireless/ath/ath12k/hal.c | 8 ++++---- drivers/net/wireless/ath/ath12k/hal.h | 5 +---- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/hal.c b/drivers/net/wireless/ath/ath12k/hal.c index a164563fff289..f03817b2fbc52 100644 --- a/drivers/net/wireless/ath/ath12k/hal.c +++ b/drivers/net/wireless/ath/ath12k/hal.c @@ -828,8 +828,8 @@ void *ath12k_hal_encode_tlv64_hdr(void *tlv, u64 tag, u64 len) { struct hal_tlv_64_hdr *tlv64 = tlv; - tlv64->tl = le64_encode_bits(tag, HAL_TLV_HDR_TAG) | - le64_encode_bits(len, HAL_TLV_HDR_LEN); + tlv64->tl = le64_encode_bits(tag, HAL_TLV_64_HDR_TAG) | + le64_encode_bits(len, HAL_TLV_64_HDR_LEN); return tlv64->value; } @@ -851,7 +851,7 @@ u16 ath12k_hal_decode_tlv64_hdr(void *tlv, void **desc) struct hal_tlv_64_hdr *tlv64 = tlv; u16 tag; - tag = le64_get_bits(tlv64->tl, HAL_SRNG_TLV_HDR_TAG); + tag = le64_get_bits(tlv64->tl, HAL_TLV_64_HDR_TAG); *desc = tlv64->value; return tag; @@ -863,7 +863,7 @@ u16 ath12k_hal_decode_tlv32_hdr(void *tlv, void **desc) struct hal_tlv_hdr *tlv32 = tlv; u16 tag; - tag = le32_get_bits(tlv32->tl, HAL_SRNG_TLV_HDR_TAG); + tag = le32_get_bits(tlv32->tl, HAL_TLV_HDR_TAG); *desc = tlv32->value; return tag; diff --git a/drivers/net/wireless/ath/ath12k/hal.h b/drivers/net/wireless/ath/ath12k/hal.h index bf4f7dbae8669..b3a89ace5a978 100644 --- a/drivers/net/wireless/ath/ath12k/hal.h +++ b/drivers/net/wireless/ath/ath12k/hal.h @@ -1442,7 +1442,7 @@ struct hal_ops { }; #define HAL_TLV_HDR_TAG GENMASK(9, 1) -#define HAL_TLV_HDR_LEN GENMASK(25, 10) +#define HAL_TLV_HDR_LEN GENMASK(21, 10) #define HAL_TLV_USR_ID GENMASK(31, 26) #define HAL_TLV_ALIGN 4 @@ -1462,9 +1462,6 @@ struct hal_tlv_64_hdr { u8 value[]; } __packed; -#define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) -#define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) - dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab, struct hal_srng *srng); dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab, From d3b51652f386b6b9c1ccf56930f67eb03b57fcfe Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Fri, 17 Apr 2026 15:25:55 +0800 Subject: [PATCH 0804/1330] FROMLIST: wifi: ath12k: refactor HAL TLV32/64 decode helpers Change TLV decode helpers to return the TLV value pointer and optionally decode tag/len/usrid via out parameters. This allows reusing the helpers for DP monitor RX status header TLV parsing and avoids duplicated header decoding in callers. No functional change intended. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0.c2-00068-QCACOLSWPL_V1_TO_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Miaoqing Pan Link: https://lore.kernel.org/linux-wireless/20260509025819.1641630-3-miaoqing.pan@oss.qualcomm.com/ (cherry picked from commit 79e4ddc0ddf29bab210d927010affbd656b9eb7c) --- drivers/net/wireless/ath/ath12k/hal.c | 26 ++++++++++++------- drivers/net/wireless/ath/ath12k/hal.h | 4 +-- .../wireless/ath/ath12k/wifi7/hal_qcc2072.c | 2 +- .../wireless/ath/ath12k/wifi7/hal_qcn9274.c | 11 +++++++- .../wireless/ath/ath12k/wifi7/hal_wcn7850.c | 11 +++++++- 5 files changed, 39 insertions(+), 15 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/hal.c b/drivers/net/wireless/ath/ath12k/hal.c index f03817b2fbc52..d940f83cd92fb 100644 --- a/drivers/net/wireless/ath/ath12k/hal.c +++ b/drivers/net/wireless/ath/ath12k/hal.c @@ -846,26 +846,32 @@ void *ath12k_hal_encode_tlv32_hdr(void *tlv, u64 tag, u64 len) } EXPORT_SYMBOL(ath12k_hal_encode_tlv32_hdr); -u16 ath12k_hal_decode_tlv64_hdr(void *tlv, void **desc) +void *ath12k_hal_decode_tlv64_hdr(void *tlv, u16 *tag, u16 *len, u16 *usrid) { struct hal_tlv_64_hdr *tlv64 = tlv; - u16 tag; - tag = le64_get_bits(tlv64->tl, HAL_TLV_64_HDR_TAG); - *desc = tlv64->value; + if (tag) + *tag = le64_get_bits(tlv64->tl, HAL_TLV_64_HDR_TAG); + if (len) + *len = le64_get_bits(tlv64->tl, HAL_TLV_64_HDR_LEN); + if (usrid) + *usrid = le64_get_bits(tlv64->tl, HAL_TLV_64_USR_ID); - return tag; + return tlv64->value; } EXPORT_SYMBOL(ath12k_hal_decode_tlv64_hdr); -u16 ath12k_hal_decode_tlv32_hdr(void *tlv, void **desc) +void *ath12k_hal_decode_tlv32_hdr(void *tlv, u16 *tag, u16 *len, u16 *usrid) { struct hal_tlv_hdr *tlv32 = tlv; - u16 tag; - tag = le32_get_bits(tlv32->tl, HAL_TLV_HDR_TAG); - *desc = tlv32->value; + if (tag) + *tag = le32_get_bits(tlv32->tl, HAL_TLV_HDR_TAG); + if (len) + *len = le32_get_bits(tlv32->tl, HAL_TLV_HDR_LEN); + if (usrid) + *usrid = le32_get_bits(tlv32->tl, HAL_TLV_USR_ID); - return tag; + return tlv32->value; } EXPORT_SYMBOL(ath12k_hal_decode_tlv32_hdr); diff --git a/drivers/net/wireless/ath/ath12k/hal.h b/drivers/net/wireless/ath/ath12k/hal.h index b3a89ace5a978..3158c1881c767 100644 --- a/drivers/net/wireless/ath/ath12k/hal.h +++ b/drivers/net/wireless/ath/ath12k/hal.h @@ -1551,6 +1551,6 @@ void ath12k_hal_rx_reo_ent_buf_paddr_get(struct ath12k_hal *hal, void *rx_desc, u8 *rbm, u32 *msdu_cnt); void *ath12k_hal_encode_tlv64_hdr(void *tlv, u64 tag, u64 len); void *ath12k_hal_encode_tlv32_hdr(void *tlv, u64 tag, u64 len); -u16 ath12k_hal_decode_tlv64_hdr(void *tlv, void **desc); -u16 ath12k_hal_decode_tlv32_hdr(void *tlv, void **desc); +void *ath12k_hal_decode_tlv64_hdr(void *tlv, u16 *tag, u16 *len, u16 *usrid); +void *ath12k_hal_decode_tlv32_hdr(void *tlv, u16 *tag, u16 *len, u16 *usrid); #endif diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c index 1eefb931a853e..c0583c3a21916 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c @@ -439,7 +439,7 @@ static u16 ath12k_hal_reo_status_dec_tlv_hdr_qcc2072(void *tlv, void **desc) struct hal_reo_get_queue_stats_status_qcc2072 *status_tlv; u16 tag; - tag = ath12k_hal_decode_tlv32_hdr(tlv, (void **)&status_tlv); + status_tlv = ath12k_hal_decode_tlv32_hdr(tlv, &tag, NULL, NULL); /* * actual desc of REO status entry starts after tlv32_padding, * see hal_reo_get_queue_stats_status_qcc2072 diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c index 41c918eb17673..6410f764ae5e4 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c @@ -846,6 +846,15 @@ void ath12k_hal_extract_rx_desc_data_qcn9274(struct hal_rx_desc_data *rx_desc_da rx_desc_data->err_bitmap = ath12k_hal_rx_h_mpdu_err_qcn9274(rx_desc); } +static u16 ath12k_hal_reo_status_dec_tlv_hdr_qcn9274(void *tlv, void **desc) +{ + u16 tag; + + *desc = ath12k_hal_decode_tlv64_hdr(tlv, &tag, NULL, NULL); + + return tag; +} + const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = { .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | @@ -1034,5 +1043,5 @@ const struct hal_ops hal_qcn9274_ops = { .rx_msdu_list_get = ath12k_wifi7_hal_rx_msdu_list_get, .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get, .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv64_hdr, - .reo_status_dec_tlv_hdr = ath12k_hal_decode_tlv64_hdr, + .reo_status_dec_tlv_hdr = ath12k_hal_reo_status_dec_tlv_hdr_qcn9274, }; diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c b/drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c index e64e512cac7df..4bef64ac91500 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c @@ -740,6 +740,15 @@ int ath12k_hal_srng_create_config_wcn7850(struct ath12k_hal *hal) return 0; } +static u16 ath12k_hal_reo_status_dec_tlv_hdr_wcn7850(void *tlv, void **desc) +{ + u16 tag; + + *desc = ath12k_hal_decode_tlv64_hdr(tlv, &tag, NULL, NULL); + + return tag; +} + const struct ath12k_hal_tcl_to_wbm_rbm_map ath12k_hal_tcl_to_wbm_rbm_map_wcn7850[DP_TCL_NUM_RING_MAX] = { { @@ -805,5 +814,5 @@ const struct hal_ops hal_wcn7850_ops = { .rx_msdu_list_get = ath12k_wifi7_hal_rx_msdu_list_get, .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get, .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv64_hdr, - .reo_status_dec_tlv_hdr = ath12k_hal_decode_tlv64_hdr, + .reo_status_dec_tlv_hdr = ath12k_hal_reo_status_dec_tlv_hdr_wcn7850, }; From 74b6ac15f36fcea229a4bd11716fc7ae562cbd4c Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Fri, 17 Apr 2026 16:25:09 +0800 Subject: [PATCH 0805/1330] FROMLIST: wifi: ath12k: add HAL ops for monitor TLV header decode and alignment Wi-Fi 7 monitor RX status TLV parsing needs to decode TLV headers and advance the pointer with the correct header alignment. Different targets use different TLV header layouts (32-bit vs 64-bit), but the HAL ops for dp_mon RX status header decode and header alignment were not populated for all wifi7 targets. Add dp_mon RX status TLV header decode callbacks and TLV header alignment helpers to the wifi7 HAL ops for QCC2072, QCN9274 and WCN7850. Export helpers to query the required TLV header alignment for 32-bit and 64-bit TLV headers so the caller can align the TLV walk correctly across targets. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0.c2-00068-QCACOLSWPL_V1_TO_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Miaoqing Pan Link: https://lore.kernel.org/linux-wireless/20260509025819.1641630-4-miaoqing.pan@oss.qualcomm.com/ (cherry picked from commit c87780b09593544fee282291fa5d3adf546e32c3) --- drivers/net/wireless/ath/ath12k/hal.c | 12 ++++++++++++ drivers/net/wireless/ath/ath12k/hal.h | 4 ++++ drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c | 2 ++ drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c | 2 ++ drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c | 2 ++ 5 files changed, 22 insertions(+) diff --git a/drivers/net/wireless/ath/ath12k/hal.c b/drivers/net/wireless/ath/ath12k/hal.c index d940f83cd92fb..c0c3d2f047ef0 100644 --- a/drivers/net/wireless/ath/ath12k/hal.c +++ b/drivers/net/wireless/ath/ath12k/hal.c @@ -875,3 +875,15 @@ void *ath12k_hal_decode_tlv32_hdr(void *tlv, u16 *tag, u16 *len, u16 *usrid) return tlv32->value; } EXPORT_SYMBOL(ath12k_hal_decode_tlv32_hdr); + +u32 ath12k_hal_get_tlv64_hdr_align(void) +{ + return HAL_TLV_64_ALIGN; +} +EXPORT_SYMBOL(ath12k_hal_get_tlv64_hdr_align); + +u32 ath12k_hal_get_tlv32_hdr_align(void) +{ + return HAL_TLV_ALIGN; +} +EXPORT_SYMBOL(ath12k_hal_get_tlv32_hdr_align); diff --git a/drivers/net/wireless/ath/ath12k/hal.h b/drivers/net/wireless/ath/ath12k/hal.h index 3158c1881c767..312993d3d5d4b 100644 --- a/drivers/net/wireless/ath/ath12k/hal.h +++ b/drivers/net/wireless/ath/ath12k/hal.h @@ -1439,6 +1439,8 @@ struct hal_ops { u8 *rbm, u32 *msdu_cnt); void *(*reo_cmd_enc_tlv_hdr)(void *tlv, u64 tag, u64 len); u16 (*reo_status_dec_tlv_hdr)(void *tlv, void **desc); + void *(*mon_rx_status_dec_tlv_hdr)(void *tlv, u16 *tag, u16 *len, u16 *usrid); + u32 (*get_tlv_hdr_align)(void); }; #define HAL_TLV_HDR_TAG GENMASK(9, 1) @@ -1553,4 +1555,6 @@ void *ath12k_hal_encode_tlv64_hdr(void *tlv, u64 tag, u64 len); void *ath12k_hal_encode_tlv32_hdr(void *tlv, u64 tag, u64 len); void *ath12k_hal_decode_tlv64_hdr(void *tlv, u16 *tag, u16 *len, u16 *usrid); void *ath12k_hal_decode_tlv32_hdr(void *tlv, u16 *tag, u16 *len, u16 *usrid); +u32 ath12k_hal_get_tlv64_hdr_align(void); +u32 ath12k_hal_get_tlv32_hdr_align(void); #endif diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c index c0583c3a21916..80ffadc47d48c 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c @@ -490,6 +490,8 @@ const struct hal_ops hal_qcc2072_ops = { .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get, .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv32_hdr, .reo_status_dec_tlv_hdr = ath12k_hal_reo_status_dec_tlv_hdr_qcc2072, + .mon_rx_status_dec_tlv_hdr = ath12k_hal_decode_tlv32_hdr, + .get_tlv_hdr_align = ath12k_hal_get_tlv32_hdr_align, }; u32 ath12k_hal_rx_desc_get_mpdu_start_offset_qcc2072(void) diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c index 6410f764ae5e4..e51b6f2afffc6 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c @@ -1044,4 +1044,6 @@ const struct hal_ops hal_qcn9274_ops = { .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get, .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv64_hdr, .reo_status_dec_tlv_hdr = ath12k_hal_reo_status_dec_tlv_hdr_qcn9274, + .mon_rx_status_dec_tlv_hdr = ath12k_hal_decode_tlv64_hdr, + .get_tlv_hdr_align = ath12k_hal_get_tlv64_hdr_align, }; diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c b/drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c index 4bef64ac91500..8819860755489 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c @@ -815,4 +815,6 @@ const struct hal_ops hal_wcn7850_ops = { .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get, .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv64_hdr, .reo_status_dec_tlv_hdr = ath12k_hal_reo_status_dec_tlv_hdr_wcn7850, + .mon_rx_status_dec_tlv_hdr = ath12k_hal_decode_tlv64_hdr, + .get_tlv_hdr_align = ath12k_hal_get_tlv64_hdr_align, }; From c361b12d8069c6d6fb62d26d8030f6644f98bd52 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Fri, 17 Apr 2026 20:19:00 +0800 Subject: [PATCH 0806/1330] FROMLIST: wifi: ath12k: add dp_mon support 32-bit TLV headers Wi-Fi 7 monitor status parsing in dp_mon currently assumes a 64-bit TLV header and directly decodes tag/len/userid from struct hal_tlv_64_hdr. On chips using a 32-bit TLV header (e.g. QCC2072), this causes monitor RX status packets to be dropped during TLV parsing. Introduce HAL helpers to decode TLV header fields (tag/len/userid/value) for both 32-bit and 64-bit header layouts. Without changing the actual TLV parsing logic. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0.c2-00068-QCACOLSWPL_V1_TO_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Miaoqing Pan Link: https://lore.kernel.org/linux-wireless/20260509025819.1641630-5-miaoqing.pan@oss.qualcomm.com/ (cherry picked from commit f3fc0c636335daa7cb06a522934241c86f87b67d) --- .../net/wireless/ath/ath12k/wifi7/dp_mon.c | 57 ++++++++++--------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c b/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c index 77f5d23be78d6..4266bd1d0d3d7 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c @@ -1565,16 +1565,17 @@ ath12k_wifi7_dp_mon_parse_status_msdu_end(struct ath12k_mon_data *pmon, static enum hal_rx_mon_status ath12k_wifi7_dp_mon_rx_parse_status_tlv(struct ath12k_pdev_dp *dp_pdev, struct ath12k_mon_data *pmon, - const struct hal_tlv_64_hdr *tlv) + const void *tlv) { struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; - const void *tlv_data = tlv->value; - u32 info[7], userid; - u16 tlv_tag, tlv_len; + struct ath12k *ar = ath12k_pdev_dp_to_ar(dp_pdev); + struct ath12k_hal *hal = &ar->ab->hal; + u16 tlv_tag, tlv_len, userid; + void *tlv_data; + u32 info[7]; - tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG); - tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN); - userid = le64_get_bits(tlv->tl, HAL_TLV_64_USR_ID); + tlv_data = hal->ops->mon_rx_status_dec_tlv_hdr((void *)tlv, &tlv_tag, + &tlv_len, &userid); if (ppdu_info->tlv_aggr.in_progress && ppdu_info->tlv_aggr.tlv_tag != tlv_tag) { ath12k_wifi7_dp_mon_parse_eht_sig_hdr(ppdu_info, @@ -2931,11 +2932,12 @@ static enum dp_mon_status_buf_state ath12k_wifi7_dp_rx_mon_buf_done(struct ath12k_base *ab, struct hal_srng *srng, struct dp_rxdma_mon_ring *rx_ring) { + struct ath12k_hal *hal = &ab->hal; struct ath12k_skb_rxcb *rxcb; - struct hal_tlv_64_hdr *tlv; struct sk_buff *skb; void *status_desc; dma_addr_t paddr; + u16 tlv_tag; u32 cookie; int buf_id; u8 rbm; @@ -2960,8 +2962,8 @@ ath12k_wifi7_dp_rx_mon_buf_done(struct ath12k_base *ab, struct hal_srng *srng, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); - tlv = (struct hal_tlv_64_hdr *)skb->data; - if (le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG) != HAL_RX_STATUS_BUFFER_DONE) + hal->ops->mon_rx_status_dec_tlv_hdr(skb->data, &tlv_tag, NULL, NULL); + if (tlv_tag != HAL_RX_STATUS_BUFFER_DONE) return DP_MON_STATUS_NO_DMA; return DP_MON_STATUS_REPLINISH; @@ -2973,39 +2975,38 @@ ath12k_wifi7_dp_mon_parse_rx_dest(struct ath12k_pdev_dp *dp_pdev, struct sk_buff *skb) { struct ath12k *ar = ath12k_pdev_dp_to_ar(dp_pdev); - struct hal_tlv_64_hdr *tlv; + struct ath12k_hal *hal = &ar->ab->hal; + u8 *tlv_value, *tlv = skb->data; struct ath12k_skb_rxcb *rxcb; enum hal_rx_mon_status hal_status; u16 tlv_tag, tlv_len; - u8 *ptr = skb->data; + u32 tlv_hdr_len; + + tlv_hdr_len = hal->ops->get_tlv_hdr_align(); do { - tlv = (struct hal_tlv_64_hdr *)ptr; - tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG); + tlv_value = hal->ops->mon_rx_status_dec_tlv_hdr(tlv, &tlv_tag, + &tlv_len, NULL); /* The actual length of PPDU_END is the combined length of many PHY * TLVs that follow. Skip the TLV header and * rx_rxpcu_classification_overview that follows the header to get to * next TLV. */ - if (tlv_tag == HAL_RX_PPDU_END) tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); - else - tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN); hal_status = ath12k_wifi7_dp_mon_rx_parse_status_tlv(dp_pdev, pmon, tlv); if (ar->monitor_started && ar->ab->hw_params->rxdma1_enable && ath12k_wifi7_dp_mon_parse_rx_dest_tlv(dp_pdev, pmon, hal_status, - tlv->value)) + tlv_value)) return HAL_RX_MON_STATUS_PPDU_DONE; - ptr += sizeof(*tlv) + tlv_len; - ptr = PTR_ALIGN(ptr, HAL_TLV_64_ALIGN); + tlv = PTR_ALIGN(tlv + tlv_len + tlv_hdr_len, tlv_hdr_len); - if ((ptr - skb->data) > skb->len) + if ((tlv - skb->data) > skb->len) break; } while ((hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE) || @@ -3057,15 +3058,16 @@ ath12k_wifi7_dp_rx_reap_mon_status_ring(struct ath12k_base *ab, int mac_id, int buf_id, srng_id, num_buffs_reaped = 0; enum dp_mon_status_buf_state reap_status; struct dp_rxdma_mon_ring *rx_ring; + struct ath12k_hal *hal = &ab->hal; struct ath12k_mon_data *pmon; struct ath12k_skb_rxcb *rxcb; - struct hal_tlv_64_hdr *tlv; void *rx_mon_status_desc; struct hal_srng *srng; struct ath12k_dp *dp; struct sk_buff *skb; struct ath12k *ar; dma_addr_t paddr; + u16 tlv_tag; u32 cookie; u8 rbm; @@ -3110,14 +3112,13 @@ ath12k_wifi7_dp_rx_reap_mon_status_ring(struct ath12k_base *ab, int mac_id, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); - tlv = (struct hal_tlv_64_hdr *)skb->data; - if (le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG) != - HAL_RX_STATUS_BUFFER_DONE) { + hal->ops->mon_rx_status_dec_tlv_hdr(skb->data, &tlv_tag, + NULL, NULL); + if (tlv_tag != HAL_RX_STATUS_BUFFER_DONE) { pmon->buf_state = DP_MON_STATUS_NO_DMA; ath12k_warn(ab, - "mon status DONE not set %llx, buf_id %d\n", - le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG), - buf_id); + "mon status DONE not set %x, buf_id %d\n", + tlv_tag, buf_id); /* RxDMA status done bit might not be set even * though tp is moved by HW. */ From b5f0750100ff981baa5ad2b34ad61d849ba49502 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Sun, 12 Apr 2026 21:21:46 +0800 Subject: [PATCH 0807/1330] FROMLIST: wifi: ath12k: tighten RX monitor TLV bounds check Validate the pointer to the next RX monitor TLV more strictly by ensuring that at least a full TLV header is available within the status buffer before continuing TLV parsing. Prevent potential out-of-bounds access when handling malformed or truncated RX monitor status data. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0.c2-00068-QCACOLSWPL_V1_TO_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Miaoqing Pan Link: https://lore.kernel.org/linux-wireless/20260509025819.1641630-6-miaoqing.pan@oss.qualcomm.com/ (cherry picked from commit bd4458e2deb5ea1264ca23d4a7f92e323945fb64) --- drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c b/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c index 4266bd1d0d3d7..23ba0cc824a77 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c @@ -3006,9 +3006,9 @@ ath12k_wifi7_dp_mon_parse_rx_dest(struct ath12k_pdev_dp *dp_pdev, tlv = PTR_ALIGN(tlv + tlv_len + tlv_hdr_len, tlv_hdr_len); - if ((tlv - skb->data) > skb->len) + if (unlikely(tlv - skb->data > skb->len || + skb->len - (tlv - skb->data) < tlv_hdr_len)) break; - } while ((hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE) || (hal_status == HAL_RX_MON_STATUS_BUF_ADDR) || (hal_status == HAL_RX_MON_STATUS_MPDU_START) || From 5503f91673ac229ca8aaa2a57067aa493270e6eb Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 3 Apr 2026 19:14:59 +0530 Subject: [PATCH 0808/1330] arm64: dts: qcom: shikra: Add TCSR mutex hwlock support Describe the TCSR mutex hwlock controller and reference it from the SMEM node to enable proper hardware locking on Shikra. Signed-off-by: Komal Bajaj (cherry picked from commit f59686a529c118bc73eb9c423a9fabbeafb0aae6) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 0cdf3f0c9f6dd..385298df34cba 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -223,6 +223,14 @@ no-map; }; + smem_mem: smem_region@86000000 { + compatible = "qcom,smem"; + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + }; + audio_heap_mem: audio-heap@86200000 { reg = <0x0 0x86200000 0x0 0x100000>; no-map; @@ -321,6 +329,12 @@ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + tcsr_mutex: syscon@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,shikra-tlmm"; reg = <0x0 0x00500000 0x0 0x800000>; From 2904824bd6f9fdd48d17519744bb9b1ea9f9ea36 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 1 Apr 2026 16:27:25 +0530 Subject: [PATCH 0809/1330] arm64: dts: msm: add interconnect devices for Shikra Add interconnect devices for config_noc, system_noc, mc_virt, clk_virt, mem_noc, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Signed-off-by: Raviteja Laggyshetty (cherry picked from commit cf53904cf90e38dcddd4fe198136f6604e86b202) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 52 +++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 385298df34cba..76916cd36d256 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include / { @@ -358,6 +360,14 @@ }; }; + mem_noc: interconnect@d00000 { + compatible = "qcom,shikra-mem-noc-core"; + reg = <0x0 0x00d00000 0x0 0x43080>; + clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; + clock-names = "gpu_axi"; + #interconnect-cells = <2>; + }; + gcc: clock-controller@1400000 { compatible = "qcom,shikra-gcc"; reg = <0x0 0x01400000 0x0 0x1f0000>; @@ -374,7 +384,47 @@ #power-domain-cells = <1>; }; - qfprom: efuse@1b44000 { + system_noc: interconnect@1880000 { + compatible = "qcom,shikra-sys-noc"; + reg = <0x0 0x01880000 0x0 0x6a080>; + clocks = <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>, + <&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>, + <&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; + clock-names = "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi"; + #interconnect-cells = <2>; + + clk_virt: interconnect-clk { + compatible = "qcom,shikra-clk-virt"; + #interconnect-cells = <2>; + }; + + mc_virt: interconnect-mc { + compatible = "qcom,shikra-mc-virt"; + #interconnect-cells = <2>; + }; + + mmrt_virt: interconnect-mmrt { + compatible = "qcom,shikra-mmrt-virt"; + #interconnect-cells = <2>; + }; + + mmnrt_virt: interconnect-mmnrt { + compatible = "qcom,shikra-mmnrt-virt"; + #interconnect-cells = <2>; + }; + }; + + config_noc: interconnect@1900000 { + compatible = "qcom,shikra-config-noc"; + reg = <0x0 0x01900000 0x0 0x8080>; + #interconnect-cells = <2>; + }; + + qfprom: efuse@1b40000 { compatible = "qcom,shikra-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; #address-cells = <1>; From f7546547828b979f8bc343a99edb4e1e0d647741 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 3 Apr 2026 19:36:11 +0530 Subject: [PATCH 0810/1330] arm64: dts: qcom: shikra: Add download mode support Add the SCM firmware node and TCSR syscon required to support download mode on Shikra. Signed-off-by: Komal Bajaj (cherry picked from commit e48efb44aac4da3596cc39ca1e5df5ac70af6425) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 76916cd36d256..d7f4f44b9d0be 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -96,17 +96,12 @@ }; }; - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - clock-frequency = <38400000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - #clock-cells = <0>; + firmware { + scm { + compatible = "qcom,scm-shikra", "qcom,scm"; + qcom,dload-mode = <&tcsr_regs 0x13000>; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; }; }; @@ -337,6 +332,11 @@ #hwlock-cells = <1>; }; + tcsr_regs: syscon@3c0000 { + compatible = "qcom,shikra-tcsr", "syscon"; + reg = <0x0 0x003c0000 0x0 0x40000>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,shikra-tlmm"; reg = <0x0 0x00500000 0x0 0x800000>; From bc154193ff2e1a10206623dc185de93c71a937cb Mon Sep 17 00:00:00 2001 From: Xueyao An Date: Thu, 26 Mar 2026 10:44:58 +0800 Subject: [PATCH 0811/1330] arm64: dts: qcom: Add QUPv3 UART console node for shikra Enable console support for shikra. Signed-off-by: Xueyao An (cherry picked from commit 92ddbe8d5cd58fd060a5d5da335dba9e2a0f2c70) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 5 +++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 5 +++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 5 +++ arch/arm64/boot/dts/qcom/shikra.dtsi | 38 ++++++++++++++++++++- 4 files changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 1bd1717a9d1f0..e3619bfd80e03 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -13,9 +13,14 @@ chassis-type = "embedded"; aliases { + serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 89fd8d0ccdc56..57191d29ce5f3 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -13,9 +13,14 @@ chassis-type = "embedded"; aliases { + serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index f0e9da31909dd..fecc676e4cd26 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -13,9 +13,14 @@ chassis-type = "embedded"; aliases { + serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index d7f4f44b9d0be..f7a33ff6bc68f 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -354,7 +354,7 @@ qup_uart0_default: qup-uart0-default-state { pins = "gpio0", "gpio1"; - function = "qup0_se1"; + function = "qup0_se0"; drive-strength = <2>; bias-disable; }; @@ -671,6 +671,42 @@ status = "disabled"; }; }; + + qupv3_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@4a80000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x04a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; }; timer { From 83018a08c9b0c8f0fb325ca1943ec7bbe384f820 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Tue, 7 Apr 2026 18:55:41 +0530 Subject: [PATCH 0812/1330] arm64: dts: qcom: Add eMMC support for shikra SoC Add support for eMMC on shikra SoC and enable the required pinctrl configurations. Signed-off-by: Monish Chunara (cherry picked from commit 1e57f69c7bb86c3c14e563d687a58ebe6f877682) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 116 +++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index f7a33ff6bc68f..cffd860056b9a 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -358,6 +359,56 @@ drive-strength = <2>; bias-disable; }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <6>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <6>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-bus-hold; + }; + }; }; mem_noc: interconnect@d00000 { @@ -476,6 +527,71 @@ reg = <0x0 0x04690000 0x0 0x14000>; }; + sdhc_1: mmc@4744000 { + compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; + + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + iommus = <&apps_smmu 0xc0 0x0>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + + bus-width = <8>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + resets = <&gcc GCC_SDCC1_BCR>; + + status = "disabled"; + + sdhc1_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <250000 133320>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <800000 300000>; + opp-avg-kBps = <400000 0>; + }; + }; + }; + adreno_smmu: iommu@59a0000 { compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x059a0000 0x0 0x10000>; From 79358c018adb9b22c39e754cea4f95b54d13a7e3 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Tue, 7 Apr 2026 18:58:23 +0530 Subject: [PATCH 0813/1330] arm64: dts: qcom: Enable eMMC for shikra EVK Enable eMMC for shikra CQS, CQM and IQS EVK variants. Signed-off-by: Monish Chunara (cherry picked from commit cc260b3e2eec5e39e67abcd26b17d2c985b6e199) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 17 +++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index e3619bfd80e03..14c0456db27bc 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -13,6 +13,7 @@ chassis-type = "embedded"; aliases { + mmc0 = &sdhc_1; serial0 = &uart0; }; @@ -21,6 +22,22 @@ }; }; +&sdhc_1 { + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 57191d29ce5f3..3795455c36112 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -13,6 +13,7 @@ chassis-type = "embedded"; aliases { + mmc0 = &sdhc_1; serial0 = &uart0; }; @@ -21,6 +22,22 @@ }; }; +&sdhc_1 { + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index fecc676e4cd26..b374258946582 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -13,6 +13,7 @@ chassis-type = "embedded"; aliases { + mmc0 = &sdhc_1; serial0 = &uart0; }; @@ -21,6 +22,22 @@ }; }; +&sdhc_1 { + vmmc-supply = <&pm8150_l17>; + vqmmc-supply = <&pm8150_s4>; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; + &uart0 { status = "okay"; }; From be48f6b7572fe3b37023e44c612a8b50c5dbde20 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Tue, 7 Apr 2026 20:42:20 +0530 Subject: [PATCH 0814/1330] arm64: dts: qcom: Add SD Card support for shikra SoC Add support for SD card on shikra SoC and enable the required pinctrl configurations. Signed-off-by: Monish Chunara (cherry picked from commit 2db4f0bcc7e65936fddc3b03616fadd243a2b60f) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++ arch/arm64/boot/dts/qcom/shikra.dtsi | 91 +++++++++++++++++++++ 4 files changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 14c0456db27bc..2b7e2f236c465 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "shikra-cqm-som.dtsi" +#include "shikra-evk.dtsi" +#include / { model = "Qualcomm Technologies, Inc. Shikra CQM EVK"; @@ -14,6 +16,7 @@ aliases { mmc0 = &sdhc_1; + mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &uart0; }; @@ -38,6 +41,22 @@ status = "okay"; }; +&sdhc_2 { + vmmc-supply = <&pm4125_l21>; + vqmmc-supply = <&pm4125_l4>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 3795455c36112..3022ab4ccffeb 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "shikra-cqs-som.dtsi" +#include "shikra-evk.dtsi" +#include / { model = "Qualcomm Technologies, Inc. Shikra CQS EVK"; @@ -14,6 +16,7 @@ aliases { mmc0 = &sdhc_1; + mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &uart0; }; @@ -38,6 +41,22 @@ status = "okay"; }; +&sdhc_2 { + vmmc-supply = <&pm4125_l21>; + vqmmc-supply = <&pm4125_l4>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index b374258946582..60951524844b2 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "shikra-iqs-som.dtsi" +#include "shikra-evk.dtsi" +#include / { model = "Qualcomm Technologies, Inc. Shikra IQS EVK"; @@ -14,6 +16,7 @@ aliases { mmc0 = &sdhc_1; + mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &uart0; }; @@ -38,6 +41,22 @@ status = "okay"; }; +&sdhc_2 { + vmmc-supply = <&pm8150_l10>; + vqmmc-supply = <&pm8150_l2>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index cffd860056b9a..9761f4af0a272 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -409,6 +409,53 @@ bias-bus-hold; }; }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <14>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <14>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <14>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; mem_noc: interconnect@d00000 { @@ -592,6 +639,50 @@ }; }; + sdhc_2: mmc@4784000 { + compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x4784000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x0a0 0x0>; + + interconnects = <&system_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + status = "disabled"; + + sdhc2_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + adreno_smmu: iommu@59a0000 { compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x059a0000 0x0 0x10000>; From ee0aac6060cd1c84e03657eee4757496893f9049 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Wed, 8 Apr 2026 19:20:05 +0530 Subject: [PATCH 0815/1330] arm64: dts: qcom: Add USB changes for Shikra Add usb related changes on Shikra specifically: a) Primary controller node b) Primary high speed phy c) QMP Phy for super speed operation Enable USB controller and phys in device mode on CQS and CQM variants. Add the regulators for the phys accordingly. Signed-off-by: Krishna Kurapati (cherry picked from commit 64f81a14b323a8e87832f343f55c4b537b2e3b73) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 21 +++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 21 +++ arch/arm64/boot/dts/qcom/shikra.dtsi | 146 +++++++++++++++++++- 3 files changed, 186 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 2b7e2f236c465..d65110aa6b93e 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -60,3 +60,24 @@ &uart0 { status = "okay"; }; + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + vdda-phy-dpdm-supply = <&pm4125_l21>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l8>; + vdda-pll-supply = <&pm4125_l13>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 3022ab4ccffeb..8552841508e9c 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -60,3 +60,24 @@ &uart0 { status = "okay"; }; + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + vdda-phy-dpdm-supply = <&pm4125_l21>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l8>; + vdda-pll-supply = <&pm4125_l13>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 9761f4af0a272..429fecce4e3c2 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -482,6 +482,70 @@ #power-domain-cells = <1>; }; + usb_1_hsphy: phy@1613000 { + compatible = "qcom,shikra-qusb2-phy"; + reg = <0x0 0x01613000 0x0 0x180>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim_1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_qmpphy: phy@1615000 { + compatible = "qcom,shikra-qmp-usb3-phy"; + reg = <0x0 0x01615000 0x0 0x1000>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "cfg_ahb", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb3_phy_pipe_clk_src"; + + #phy-cells = <0>; + orientation-switch; + + qcom,tcsr-reg = <&tcsr_regs 0xb244>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + system_noc: interconnect@1880000 { compatible = "qcom,shikra-sys-noc"; reg = <0x0 0x01880000 0x0 0x6a080>; @@ -528,8 +592,13 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu-speed-bin@2006 { - reg = <0x2006 0x2>; + qusb2_hstx_trim_1: hstx-trim@258 { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + + gpu_speed_bin: gpu-speed-bin@6006 { + reg = <0x6006 0x2>; bits = <5 8>; }; }; @@ -683,6 +752,79 @@ }; }; + usb_1: usb@4e00000 { + compatible = "qcom,shikra-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x04e00000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + + iommus = <&apps_smmu 0x120 0x0>; + + phys = <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + snps,parkmode-disable-ss-quirk; + + usb-role-switch; + + wakeup-source; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; + }; + }; + }; + }; + adreno_smmu: iommu@59a0000 { compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x059a0000 0x0 0x10000>; From 4ce69610fff322e048a7a18d1e4f3166e17f4b11 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 10 Apr 2026 11:39:45 +0530 Subject: [PATCH 0816/1330] arm64: dts: qcom: shikra: Add cpufreq scaling node Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik (cherry picked from commit f72e965fb98ffb7e8d46732b925182fa5b930e69) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 429fecce4e3c2..a73705cc77a46 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -29,6 +29,7 @@ next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0>; }; cpu1: cpu@100 { @@ -39,6 +40,7 @@ next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0>; }; cpu2: cpu@200 { @@ -49,6 +51,7 @@ next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0>; }; cpu3: cpu@300 { @@ -59,6 +62,7 @@ next-level-cache = <&l2_3>; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <486>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_3: l2-cache { compatible = "cache"; @@ -1056,6 +1060,24 @@ status = "disabled"; }; }; + + cpufreq_hw: cpufreq@fd91000 { + compatible = "qcom,shikra-cpufreq-rimps", "qcom,cpufreq-rimps"; + reg = <0x0 0x0fd91000 0x0 0x1000>, + <0x0 0x0fd92000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1"; + + #freq-domain-cells = <1>; + }; }; timer { From ff9df3b3cdd6af15255c95dde4a3aaab2849a9d2 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Tue, 7 Apr 2026 15:44:34 +0530 Subject: [PATCH 0817/1330] arm64: dts: qcom: shikra: Add SMP2P nodes Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable inter-processor signalling for remoteproc state management. Signed-off-by: Vishnu Santhosh (cherry picked from commit 56790ced18fd8257f6c8341d42f49f5176cd3fe7) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a73705cc77a46..91ba8ea57ea44 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -323,6 +323,75 @@ }; }; + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = ; + + mboxes = <&apcs_glb 6>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-lmcu { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + + interrupts = ; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <26>; + + lmcu_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + lmcu_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; From e3492ed12215dd78fb7bef9a4cce3014dca58545 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 16 Apr 2026 20:03:01 +0530 Subject: [PATCH 0818/1330] arm64: dts: qcom: Enable primary usb controller on IQS platform Enable primary usb controller on IQS platform in peripheral mode. Signed-off-by: Krishna Kurapati (cherry picked from commit 382e7c7a0476b564613a9969efb884bd44da8158) --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 60951524844b2..ef64908d41986 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -60,3 +60,24 @@ &uart0 { status = "okay"; }; + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&pm8150_l4>; + vdda-pll-supply = <&pm8150_l12>; + vdda-phy-dpdm-supply = <&pm8150_l13>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&pm8150_l6>; + vdda-pll-supply = <&pm8150_l12>; + + status = "okay"; +}; From d8d5beb0447e370e8b4944faa50134e7d4ae8bc1 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Fri, 10 Apr 2026 17:26:00 +0530 Subject: [PATCH 0819/1330] arm64: dts: qcom: shikra: Enable TSENS and thermal zones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The shikra includes one TSENS instance, with a total of 14 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 120°C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 110°C and critical trip at 115°C. Signed-off-by: Gaurav Kohli (cherry picked from commit d173d9c4ddd7ff7fa26f43c705f86759b1400a9f) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 268 +++++++++++++++++++++++++++ 1 file changed, 268 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 91ba8ea57ea44..1955dbe43cea2 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -10,6 +10,8 @@ #include #include #include +#include +#include / { interrupt-parent = <&intc>; @@ -698,6 +700,18 @@ qcom,ee = <0>; }; + tsens0: thermal-sensor@4411000 { + compatible = "qcom,shikra-tsens", "qcom,tsens-v2"; + reg = <0x0 0x04411000 0x0 0x1000>, + <0x0 0x04410000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <14>; + #thermal-sensor-cells = <1>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x0 0x045f0000 0x0 0x7000>; @@ -1149,6 +1163,260 @@ }; }; + thermal_zones: thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu00-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu01-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu10-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu11-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsp-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss0-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss1-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + video-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu02-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; From 8ed97e7bd169871911fa7639e991e68d7c5c4ad5 Mon Sep 17 00:00:00 2001 From: Xueyao An Date: Fri, 17 Apr 2026 16:24:54 +0800 Subject: [PATCH 0820/1330] arm64: dts: qcom: shikra: Add firmware-name to QUPv3 nodes Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Xueyao An (cherry picked from commit 6d170bd1306b33874fa32b15df55fe859ede3711) --- arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi index cf7460e1125d6..10a57da6bc2f3 100644 --- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -12,3 +12,8 @@ * Sensor DC * NFC DC */ + +&qupv3_0 { + firmware-name = "qcom/shikra/qupv3fw.elf"; + status = "okay"; +}; From c9f82d2a67a4bf3d14cc5480e1f1fb3a20ad014f Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 6 Apr 2026 18:27:05 +0530 Subject: [PATCH 0821/1330] arm64: dts: qcom: shikra: Add PMIC thermal and ADC support Add PMIC topic overlay changes for Shikra SOM variants (CQM, CQS, IQS): - Add pm4125 temp-alarm and VADC channel nodes - Add pm8005 temp-alarm node - Add thermal zones for PMIC and system thermistors - Add GPIO key (volume up) bindings - Add ADC thermal bridge nodes for pa/quiet/msm thermistors - Disable pm8005 regulators across SOM variants - Switch SPMI interrupt to MPM edge-triggered Signed-off-by: Rakesh Kota (cherry picked from commit 8aaefc4cf5fac564431c7c29297650fd6d368636) --- arch/arm64/boot/dts/qcom/pm4125.dtsi | 77 +++++++ arch/arm64/boot/dts/qcom/pm8005.dtsi | 7 + arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 223 ++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi | 224 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 158 +++++++++++++ arch/arm64/boot/dts/qcom/shikra.dtsi | 2 +- 6 files changed, 690 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm4125.dtsi b/arch/arm64/boot/dts/qcom/pm4125.dtsi index cf8c822e80ce8..ad410b8c4f6be 100644 --- a/arch/arm64/boot/dts/qcom/pm4125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm4125.dtsi @@ -66,6 +66,83 @@ status = "disabled"; }; + pm4125_tz: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm4125_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + + pm4125_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + + /* Channel nodes */ + channel@0 { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + channel@1 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@6 { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@7 { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + channel@8 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + channel@9 { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@4b { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@83 { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@84 { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi index 0f0ab2da83055..2867ace2fa1ce 100644 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -11,6 +11,13 @@ #address-cells = <1>; #size-cells = <0>; + pm8005_tz: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm8005_gpios: gpio@c000 { compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 79ea476c7c4a6..42f0b29330dcc 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -3,9 +3,136 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include +#include +#include + #include "shikra.dtsi" +#include "pm4125.dtsi" +#include "pm8005.dtsi" /* Modem, Cocos + Kunlun PMIC */ +/ { + gpio-key { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm4125_gpios 9 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + pm4125_msm_therm_bridge: pm4125-msm-therm-bridge { + compatible = "generic-adc-thermal"; + io-channels = <&pm4125_adc ADC5_AMUX_THM3_100K_PU>; + io-channel-names = "sensor-channel"; + #thermal-sensor-cells = <0>; + }; + + pm4125_pa_therm_bridge: pm4125-pa-therm-bridge { + compatible = "generic-adc-thermal"; + io-channels = <&pm4125_adc ADC5_AMUX_THM1_100K_PU>; + io-channel-names = "sensor-channel"; + #thermal-sensor-cells = <0>; + }; + + pm4125_quiet_therm_bridge: pm4125-quiet-therm-bridge { + compatible = "generic-adc-thermal"; + io-channels = <&pm4125_adc ADC5_AMUX_THM2_100K_PU>; + io-channel-names = "sensor-channel"; + #thermal-sensor-cells = <0>; + }; +}; + +&pm4125_adc { + pinctrl-0 = <&pm4125_adc_gpio5_default>, <&pm4125_adc_gpio6_default>; + pinctrl-names = "default"; + status = "okay"; + + channel@4d { + reg = ; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@4e { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@4f { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@54 { + reg = ; + label = "chgr_skin"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@55 { + reg = ; + label = "gnss_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm4125_gpios { + pm4125_adc_gpio5_default: pm4125-adc-gpio5-state { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + pm4125_adc_gpio6_default: pm4125-adc-gpio6-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + vol_up_n: vol-up-n-state { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + +&pm4125_resin { + linux,code = ; + status = "okay"; +}; + +&pm4125_tz { + status = "okay"; +}; + +&pm8005_regulators { + status = "disabled"; +}; &rpm_requests { regulators { @@ -137,3 +264,99 @@ }; }; }; + +&thermal_zones { + pm4125-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm4125_tz>; + + trips { + pm4125_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm4125_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "hot"; + }; + + pm4125_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8005-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8005_tz>; + + trips { + pm8005_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8005_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8005_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + sys-1-thermal { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-sensors = <&pm4125_pa_therm_bridge>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-2-thermal { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-sensors = <&pm4125_quiet_therm_bridge>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-3-thermal { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-sensors = <&pm4125_msm_therm_bridge>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi index 2434c997173e2..14100f35c9383 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi @@ -3,10 +3,138 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include +#include +#include + #include "shikra.dtsi" +#include "pm4125.dtsi" +#include "pm8005.dtsi" /* APQ (No Modem), Cocos + Kunlun PMIC */ +/ { + gpio-key { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm4125_gpios 9 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + pm4125_msm_therm_bridge: pm4125-msm-therm-bridge { + compatible = "generic-adc-thermal"; + io-channels = <&pm4125_adc ADC5_AMUX_THM3_100K_PU>; + io-channel-names = "sensor-channel"; + #thermal-sensor-cells = <0>; + }; + + pm4125_pa_therm_bridge: pm4125-pa-therm-bridge { + compatible = "generic-adc-thermal"; + io-channels = <&pm4125_adc ADC5_AMUX_THM1_100K_PU>; + io-channel-names = "sensor-channel"; + #thermal-sensor-cells = <0>; + }; + + pm4125_quiet_therm_bridge: pm4125-quiet-therm-bridge { + compatible = "generic-adc-thermal"; + io-channels = <&pm4125_adc ADC5_AMUX_THM2_100K_PU>; + io-channel-names = "sensor-channel"; + #thermal-sensor-cells = <0>; + }; +}; + +&pm4125_adc { + pinctrl-0 = <&pm4125_adc_gpio5_default>, <&pm4125_adc_gpio6_default>; + pinctrl-names = "default"; + status = "okay"; + + channel@4d { + reg = ; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@4e { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@4f { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@54 { + reg = ; + label = "chgr_skin"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@55 { + reg = ; + label = "gnss_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm4125_gpios { + pm4125_adc_gpio5_default: pm4125-adc-gpio5-state { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + pm4125_adc_gpio6_default: pm4125-adc-gpio6-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + vol_up_n: vol-up-n-state { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + +&pm4125_resin { + linux,code = ; + status = "okay"; +}; + +&pm4125_tz { + status = "okay"; +}; + +&pm8005_regulators { + status = "disabled"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-pm2250-regulators"; @@ -137,3 +265,99 @@ }; }; }; + +&thermal_zones { + pm4125-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm4125_tz>; + + trips { + pm4125_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm4125_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "hot"; + }; + + pm4125_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8005-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8005_tz>; + + trips { + pm8005_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8005_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8005_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + sys-1-thermal { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-sensors = <&pm4125_pa_therm_bridge>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-2-thermal { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-sensors = <&pm4125_quiet_therm_bridge>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-3-thermal { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-sensors = <&pm4125_msm_therm_bridge>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi index 9581f98b7d08e..88b1472cf87cc 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -3,9 +3,129 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include +#include +#include + #include "shikra.dtsi" +#include "pm8150.dtsi" /* APQ (No Modem), Wailua PMIC */ + +/ { + gpio-key { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pm8150_adc { + pinctrl-0 = <&pm8150_adc_gpio2_default>, <&pm8150_adc_gpio3_default>; + pinctrl-names = "default"; + + channel@4d { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@4e { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@52 { + reg = ; + label = "gnss_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@55 { + reg = ; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150_adc_tm { + status = "okay"; + + pa-therm@0 { + reg = <0>; + io-channels = <&pm8150_adc ADC5_GPIO4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + msm-therm@2 { + reg = <2>; + io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8150_gpios { + pm8150_adc_gpio2_default: pm8150-adc-gpio2-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + pm8150_adc_gpio3_default: pm8150-adc-gpio3-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source = <0>; + }; + +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-pm8150-regulators"; @@ -126,3 +246,41 @@ }; }; }; + +&thermal_zones { + sys-1-thermal { + thermal-sensors = <&pm8150_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-2-thermal { + thermal-sensors = <&pm8150_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-3-thermal { + thermal-sensors = <&pm8150_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 1955dbe43cea2..7aa94d29d11c4 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -690,7 +690,7 @@ "obsrvr", "intr", "cnfg"; - interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&mpm 86 IRQ_TYPE_EDGE_RISING>; interrupt-names = "periph_irq"; interrupt-controller; #interrupt-cells = <4>; From cd04ada5bba1575057afb0bc7fded0f97868cab0 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 16 Apr 2026 23:09:19 +0530 Subject: [PATCH 0822/1330] arm64: dts: qcom: Add DISPCC and GPUCC nodes support Add support for DISPCC and GPUCC nodes on Qualcomm Shikra platforms. Signed-off-by: Imran Shaik (cherry picked from commit ad36dde772bf16ad7de804d3f73f1bec22525832) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 29 +++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 7aa94d29d11c4..6c3ebbb3a0477 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -4,8 +4,9 @@ */ #include -#include +#include #include +#include #include #include #include @@ -912,6 +913,17 @@ }; }; + gpucc: clock-controller@5990000 { + compatible = "qcom,shikra-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + adreno_smmu: iommu@59a0000 { compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x059a0000 0x0 0x10000>; @@ -929,6 +941,21 @@ ; }; + dispcc: clock-controller@5f00000 { + compatible = "qcom,shikra-dispcc"; + reg = <0x0 0x05f00000 0x0 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + sram@c11e000 { compatible = "qcom,shikra-imem", "syscon", "simple-mfd"; reg = <0x0 0x0c11e000 0x0 0x1000>; From 26c7d3f590da86ef5c69c25f6451c6e65a45d4f7 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Wed, 15 Apr 2026 18:41:44 +0530 Subject: [PATCH 0823/1330] arm64: dts: qcom: Add clock nodes for adreno smmu Add clock entries for adreno smmu node in Shikra. Signed-off-by: Bibek Kumar Patro (cherry picked from commit 4a1e45b75d7e91dcbaa592b45785ba1cb973aa76) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 6c3ebbb3a0477..138fa360ef85c 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -939,6 +939,17 @@ , , ; + + clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "mem", + "iface", + "ahb"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>; }; dispcc: clock-controller@5f00000 { From 4d2737bdd40ecbeb3f42b2df00a6e30433abc8e8 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Thu, 16 Apr 2026 15:18:05 +0800 Subject: [PATCH 0824/1330] arm64: dts: qcom: shikra: add WiFi node support Introduce the WiFi hardware description in shikra.dtsi, including register space, interrupts, IOMMU configuration and reserved memory. The node is kept disabled by default and is intended to be enabled by board-specific device trees. Signed-off-by: Miaoqing Pan (cherry picked from commit 1a6e08356bae467d7f6fe2a95be47020de8766e8) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 138fa360ef85c..baa32d570eed6 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1055,6 +1055,29 @@ ; }; + wifi: wifi@c800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x0 0x0c800000 0x0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x1a0 0x1>; + qcom,msa-fixed-perm; + + status = "disabled"; + }; + intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf200000 0x0 0x10000>, /* GICD */ From 1908a2cadf91f1532b75992786cfb035e28fbad1 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Mon, 20 Apr 2026 10:11:12 +0800 Subject: [PATCH 0825/1330] arm64: dts: qcom: shikra: enable WiFi on EVK boards Enable WiFi support on Shikra CQS, CQM and IQS EVK variants. Provide board-specific WiFi configuration, including power supply connections and calibration variant selection. The WiFi node is enabled on each EVK according to the corresponding PMIC and board design. Signed-off-by: Miaoqing Pan (cherry picked from commit 2ebfd3bd0b7af5a69f71476e4d84442bb658a35c) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 11 +++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 11 +++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 21 +++++++++++++++++++++ 3 files changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index d65110aa6b93e..6cb829f25e0f9 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -81,3 +81,14 @@ status = "okay"; }; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm4125_l7>; + vdd-1.8-xo-supply = <&pm4125_l13>; + vdd-1.3-rfa-supply = <&pm4125_l10>; + vdd-3.3-ch0-supply = <&pm4125_l22>; + qcom,calibration-variant = "Shikra_EVK"; + firmware-name = "cq2390"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 8552841508e9c..1d207eb5607b7 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -81,3 +81,14 @@ status = "okay"; }; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm4125_l7>; + vdd-1.8-xo-supply = <&pm4125_l13>; + vdd-1.3-rfa-supply = <&pm4125_l10>; + vdd-3.3-ch0-supply = <&pm4125_l22>; + qcom,calibration-variant = "Shikra_EVK"; + firmware-name = "cq2390"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index ef64908d41986..5ccdea654d16c 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -23,6 +23,16 @@ chosen { stdout-path = "serial0:115200n8"; }; + + regulators { + vreg_wlan_3p3_dummy: regulator-wlan-3p3-dummy { + compatible = "regulator-fixed"; + regulator-name = "wlan_3p3_dummy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; }; &sdhc_1 { @@ -81,3 +91,14 @@ status = "okay"; }; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm8150_s4>; + vdd-1.8-xo-supply = <&pm8150_l12>; + vdd-1.3-rfa-supply = <&pm8150_l8>; + vdd-3.3-ch0-supply = <&vreg_wlan_3p3_dummy>; + qcom,calibration-variant = "Shikra_EVK"; + firmware-name = "cq2390"; + + status = "okay"; +}; From 18ad8d345e26ec5636574cb4ff49f51b92bfa64f Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Mon, 20 Apr 2026 19:32:46 +0530 Subject: [PATCH 0826/1330] arm64: dts: qcom: shikra: Add Iris video codec node Add the Iris video codec device tree node for the Shikra platform. Shikra reuses the QCM2290-class video hardware and programming model. The video node is added to describe the Iris based video decoder encoder block, allowing the media driver to probe and initialize the hardware. Signed-off-by: Dikshita Agarwal (cherry picked from commit 839ada4bd899a08bf078b4b8409211258501b1ac) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 61 ++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index baa32d570eed6..1b20ae4d81c78 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -952,6 +952,67 @@ power-domains = <&gpucc GPU_CC_CX_GDSC>; }; + iris: video-codec@5a00000 { + compatible = "qcom,shikra-iris", "qcom,qcm2290-venus"; + reg = <0 0x5a00000 0 0x200000>; + interrupts = ; + + power-domains = <&gcc GCC_VENUS_GDSC>, + <&gcc GCC_VCODEC0_GDSC>, + <&rpmpd QCM2290_VDDCX>; + power-domain-names = "venus", + "vcodec0", + "cx"; + operating-points-v2 = <&venus_opp_table>; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>; + clock-names = "core", + "iface", + "bus", + "throttle", + "vcodec0_core", + "vcodec0_bus"; + + memory-region = <&video_mem>; + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_VENUS_CFG RPM_ALWAYS_TAG>; + interconnect-names = "video-mem", + "cpu-cfg"; + + iommus = <&apps_smmu 0x780 0x0020>; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133333333 { + opp-hz = /bits/ 64 <133333333>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + dispcc: clock-controller@5f00000 { compatible = "qcom,shikra-dispcc"; reg = <0x0 0x05f00000 0x0 0x20000>; From 2c12d6c9e495030bd3c5b8399e4ea8e1faa07ca5 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Mon, 20 Apr 2026 19:33:38 +0530 Subject: [PATCH 0827/1330] arm64: dts: qcom: shikra-evk: Enable Iris core Enable video en/decoder on the Shikra EVK board. Signed-off-by: Dikshita Agarwal (cherry picked from commit f8b6d80889c637855d64c583da53b289fdbf696e) --- arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi index 10a57da6bc2f3..e69499f77c682 100644 --- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -13,6 +13,10 @@ * NFC DC */ +&iris { + status = "okay"; +}; + &qupv3_0 { firmware-name = "qcom/shikra/qupv3fw.elf"; status = "okay"; From 30e15cab7ee231f6d4f74f5802a3fdffd5a3f754 Mon Sep 17 00:00:00 2001 From: Xueyao An Date: Thu, 16 Apr 2026 12:34:14 +0800 Subject: [PATCH 0828/1330] arm64: dts: qcom: Add QUPv3 configuration for Shikra Add device tree support for QUPv3 serial engine protocols on Shikra. Shikra has 10 QUP serial engines under a single QUP wrapper, all with support of GPI DMA engines. Signed-off-by: Xueyao An (cherry picked from commit 4a32f233e580adffd812db41c0fa1a21769743f9) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++ 1 file changed, 951 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 1b20ae4d81c78..73de1ce9ec6f8 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -429,6 +430,161 @@ gpio-ranges = <&tlmm 0 0 185>; wakeup-parent = <&mpm>; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio2", "gpio3"; + function = "qup0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup0_se1_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio6", "gpio7"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio10", "gpio11"; + function = "qup0_se3_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup0_se4_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio14", "gpio15"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio18", "gpio19"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup0_se7_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio22", "gpio23"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio27", "gpio26"; + function = "qup0_se9_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio1"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio2", "gpio3", "gpio0"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio9"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio6", "gpio7", "gpio8"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio17"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio14", "gpio15", "gpio16"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio29"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio18", "gpio19", "gpio28"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio25"; + function = "qup0_se8"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio22", "gpio23", "gpio24"; + function = "qup0_se8"; + drive-strength = <6>; + bias-disable; + }; + qup_uart0_default: qup-uart0-default-state { pins = "gpio0", "gpio1"; function = "qup0_se0"; @@ -436,6 +592,105 @@ bias-disable; }; + qup_uart1_default: qup-uart1-default-state { + pins = "gpio4", "gpio5"; + function = "qup0_se1_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + /* TX, RX */ + pins = "gpio8", "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart2_cts_rts: qup-uart2-cts-rts-state { + /* CTS, RTS */ + pins = "gpio6", "gpio7"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart3_default: qup-uart3-default-state { + pins = "gpio10", "gpio11"; + function = "qup0_se3_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins = "gpio12", "gpio13"; + function = "qup0_se4_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins = "gpio16", "gpio17"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart5_cts_rts: qup-uart5-cts-rts-state { + /* CTS, RTS */ + pins = "gpio14", "gpio15"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart6_default: qup-uart6-default-state { + /* TX, RX */ + pins = "gpio28", "gpio29"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart6_cts_rts: qup-uart6-cts-rts-state { + /* CTS, RTS */ + pins = "gpio18", "gpio19"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart7_default: qup-uart7-default-state { + pins = "gpio20", "gpio21"; + function = "qup0_se7_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default-state { + /* TX, RX */ + pins = "gpio24", "gpio25"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart8_cts_rts: qup-uart8-cts-rts-state { + /* CTS, RTS */ + pins = "gpio22", "gpio23"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart9_default: qup-uart9-default-state { + pins = "gpio26", "gpio27"; + function = "qup0_se9_23"; + drive-strength = <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -1230,6 +1485,34 @@ }; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x04a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <16>; + dma-channel-mask = <0xff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xf6 0x0>; + }; + qupv3_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x04ac0000 0x0 0x2000>; @@ -1239,10 +1522,75 @@ clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; #size-cells = <2>; ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart0: serial@4a80000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x04a80000 0x0 0x4000>; @@ -1264,6 +1612,609 @@ status = "disabled"; }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart1: serial@4a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart2: serial@4a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a88000 0x0 0x4000>; + + interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart3: serial@4a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart4: serial@4a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart5: serial@4a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c6: i2c@4a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@4a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart6: serial@4a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c7: i2c@4a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart7: serial@4a9c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c8: i2c@4aa0000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>, + <&gpi_dma0 1 8 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@4aa0000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>, + <&gpi_dma0 1 8 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart8: serial@4aa0000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c9: i2c@4aa4000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4aa4000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>, + <&gpi_dma0 1 9 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart9: serial@4aa4000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04aa4000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart9_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; }; cpufreq_hw: cpufreq@fd91000 { From 2708ff529912987fce85e1158c3f8941576f410d Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 20 Apr 2026 18:16:57 +0530 Subject: [PATCH 0829/1330] arm64: dts: qcom: shikra: enable USB-C port handling Enable USB role switching and USB-C orientation handling for the Qualcomm shikra board. Signed-off-by: Rakesh Kota (cherry picked from commit 1a9ac0de4669f9ec31ddd5b3ff458986c4f70c88) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 18 +++++++++- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 38 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 18 +++++++++- arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi | 38 ++++++++++++++++++++ 4 files changed, 110 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 6cb829f25e0f9..63128d33cc973 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -25,6 +25,14 @@ }; }; +&pm4125_hs_in { + remote-endpoint = <&usb_1_dwc3_hs>; +}; + +&pm4125_ss_in { + remote-endpoint = <&usb_qmpphy_out>; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; @@ -62,11 +70,15 @@ }; &usb_1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pm4125_hs_in>; +}; + &usb_1_hsphy { vdd-supply = <&pm4125_l12>; vdda-pll-supply = <&pm4125_l13>; @@ -92,3 +104,7 @@ status = "okay"; }; + +&usb_qmpphy_out { + remote-endpoint = <&pm4125_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 42f0b29330dcc..26cf4b0f31a48 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -126,10 +126,48 @@ status = "okay"; }; +&pm4125_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm4125_hs_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + pm4125_ss_in: endpoint { + }; + }; + }; + }; +}; + &pm4125_tz { status = "okay"; }; +&pm4125_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <500000>; + status = "okay"; +}; + &pm8005_regulators { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 1d207eb5607b7..c6d5337d9bf15 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -25,6 +25,14 @@ }; }; +&pm4125_hs_in { + remote-endpoint = <&usb_1_dwc3_hs>; +}; + +&pm4125_ss_in { + remote-endpoint = <&usb_qmpphy_out>; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; @@ -62,11 +70,15 @@ }; &usb_1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pm4125_hs_in>; +}; + &usb_1_hsphy { vdd-supply = <&pm4125_l12>; vdda-pll-supply = <&pm4125_l13>; @@ -92,3 +104,7 @@ status = "okay"; }; + +&usb_qmpphy_out { + remote-endpoint = <&pm4125_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi index 14100f35c9383..e9f5469768010 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi @@ -127,10 +127,48 @@ status = "okay"; }; +&pm4125_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm4125_hs_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + pm4125_ss_in: endpoint { + }; + }; + }; + }; +}; + &pm4125_tz { status = "okay"; }; +&pm4125_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <500000>; + status = "okay"; +}; + &pm8005_regulators { status = "disabled"; }; From ec0a8fb7bf4b6c9c14652a8021f6e4777b76c23f Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Wed, 22 Apr 2026 17:01:38 +0530 Subject: [PATCH 0830/1330] arm64: dts: qcom: shikra: correct RPM tags for iris interconnects Flip RPMh tags so CPU configuration paths use RPM_ACTIVE_TAG and video memory paths use RPM_ALWAYS_TAG, matching intended power management behavior. Signed-off-by: Dikshita Agarwal (cherry picked from commit bd077acd9c9bea16b8909dd81b4647d350aeb341) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 73de1ce9ec6f8..4d37f475743e9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1234,10 +1234,10 @@ "vcodec0_bus"; memory-region = <&video_mem>; - interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ACTIVE_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_VENUS_CFG RPM_ALWAYS_TAG>; + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; interconnect-names = "video-mem", "cpu-cfg"; From daa7f1c3bd71c0be07688c1bb67a23638e393a7f Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 24 Apr 2026 16:38:09 +0530 Subject: [PATCH 0831/1330] arm64: dts: qcom: shikra: Add LLCC node Add a DT node for the Last Level Cache Controller (LLCC) on the Shikra SoC. Signed-off-by: Komal Bajaj (cherry picked from commit 0eee8c33f7bd422a62aacb600cda78ab65471d1d) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 4d37f475743e9..a1b9ea44f5369 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -797,6 +797,15 @@ #interconnect-cells = <2>; }; + llcc: system-cache-controller@e00000 { + compatible = "qcom,shikra-llcc"; + reg = <0x0 0x00e00000 0x0 0x80000>, + <0x0 0x0f00000 0x0 0x80000>, + <0x0 0x1000000 0x0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; + interrupts = ; + }; + gcc: clock-controller@1400000 { compatible = "qcom,shikra-gcc"; reg = <0x0 0x01400000 0x0 0x1f0000>; From fd74b5f417a4f6bfa494e70724fda1a5ebb7438c Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Mon, 20 Apr 2026 14:28:10 +0530 Subject: [PATCH 0832/1330] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem. Signed-off-by: Bibek Kumar Patro (cherry picked from commit 05b222bf242464f5b71cb2a7c1e2fe12b90ab54d) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 169 +++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a1b9ea44f5369..4c2104401fb56 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -2226,6 +2226,174 @@ }; }; + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,shikra-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + + memory-region = <&mpss_wlan_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 12>; + qcom,remote-pid = <1>; + label = "mpss"; + }; + }; + + remoteproc_cdsp: remoteproc@b300000 { + compatible = "qcom,shikra-cdsp-pas"; + reg = <0x0 0x0b300000 0x0 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 4>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,fastrpc"; + #address-cells = <1>; + #size-cells = <0>; + label = "cdsp"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0201 0x0000>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0202 0x0000>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0203 0x0000>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0204 0x0000>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0205 0x0000>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0206 0x0000>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x0209 0x0000>; + }; + }; + }; + }; + + remoteproc_lpaicp: remoteproc@b800000 { + compatible = "qcom,shikra-lpaicp-pas"; + reg = <0x0 0x0b800000 0x0 0x200000>; + + interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, + <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>; + + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&lmcu_mem &lmcu_dtb_mem>; + + qcom,smem-states = <&lmcu_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 9>; + qcom,remote-pid = <26>; + label = "lpaicp"; + }; + }; + cpufreq_hw: cpufreq@fd91000 { compatible = "qcom,shikra-cpufreq-rimps", "qcom,cpufreq-rimps"; reg = <0x0 0x0fd91000 0x0 0x1000>, @@ -2243,6 +2411,7 @@ #freq-domain-cells = <1>; }; + }; thermal_zones: thermal-zones { From 286ae5eb2b4b417d745317ae7c61554c20e1aa00 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Thu, 30 Apr 2026 17:27:49 +0530 Subject: [PATCH 0833/1330] arm64: dts: qcom: shikra-cqm: Enable CDSP, LPAICP and MPSS Enable CDSP, LPAICP and MPSS for Qualcomm's shikra-cqm board. Signed-off-by: Bibek Kumar Patro (cherry picked from commit c73620ad552622304b07ee421660f1ab62aa27b9) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 63128d33cc973..e864b995443ef 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -33,6 +33,25 @@ remote-endpoint = <&usb_qmpphy_out>; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/shikra/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; From 78fa9c62817dc67514d84166471b5066d0527dd0 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Thu, 30 Apr 2026 17:37:31 +0530 Subject: [PATCH 0834/1330] arm64: dts: qcom: shikra-cqs: Enable CDSP and LPAICP Enable CDSP and LPAICP for Qualcomm's shikra-cqs board. Signed-off-by: Bibek Kumar Patro (cherry picked from commit 5f438c122e30816054ce6f4fc81277f795331fe0) --- arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index c6d5337d9bf15..47f0dfeb6b627 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -33,6 +33,19 @@ remote-endpoint = <&usb_qmpphy_out>; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; From 77746fcff85fef045e4b267937b741f6863e55af Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Thu, 30 Apr 2026 17:38:39 +0530 Subject: [PATCH 0835/1330] arm64: dts: qcom: shikra-iqs: Enable CDSP and LPAICP Enable CDSP and LPAICP for Qualcomm's shikra-iqs board. Signed-off-by: Bibek Kumar Patro (cherry picked from commit d3c0a1085e463840903cf26adddf131993bd34c2) --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 5ccdea654d16c..52862e4e2f57d 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -35,6 +35,19 @@ }; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm8150_l17>; vqmmc-supply = <&pm8150_s4>; From cb3f1d2496cedf37911708f75e9e9238bfba4357 Mon Sep 17 00:00:00 2001 From: Aastha Pandey Date: Thu, 7 May 2026 15:59:40 +0530 Subject: [PATCH 0836/1330] arm64: dts: qcom: shikra: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Aastha Pandey (cherry picked from commit bbaa962dc46958e5ae4e3e935673090280a6b7a3) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 4c2104401fb56..28f9135b1ed9b 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -34,6 +34,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; }; cpu1: cpu@100 { @@ -45,6 +46,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -56,6 +58,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -67,6 +70,7 @@ capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <486>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; l2_3: l2-cache { compatible = "cache"; From a7366bd5f02514bb1a1fb12493b644b081f627fe Mon Sep 17 00:00:00 2001 From: Xueyao An Date: Thu, 26 Mar 2026 10:42:33 +0800 Subject: [PATCH 0837/1330] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC Document the GPI DMA engine on Shikra platform. Signed-off-by: Xueyao An Signed-off-by: Komal Bajaj (cherry picked from commit dd2d77509d6a24f8e0bc94865395ec18fb927b02) --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index fde1df035ad12..9a376265d8718 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -35,6 +35,7 @@ properties: - qcom,sc7280-gpi-dma - qcom,sc8280xp-gpi-dma - qcom,sdx75-gpi-dma + - qcom,shikra-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma From 4005bc5d61c7a0fb488f2b891fd3812c6ae77949 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Sat, 21 Mar 2026 22:42:58 +0530 Subject: [PATCH 0838/1330] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for Shikra Update dt-bindings to add Shikra to QMP Phy list. Signed-off-by: Krishna Kurapati (cherry picked from commit 588a1808736f1402bde5c6e4c2402fbb19afcaaa) --- .../devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml index 1636285fbe535..8402fe4a96e03 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -20,6 +20,7 @@ properties: - qcom,qcm2290-qmp-usb3-phy - qcom,qcs615-qmp-usb3-phy - qcom,sdm660-qmp-usb3-phy + - qcom,shikra-qmp-usb3-phy - qcom,sm6115-qmp-usb3-phy reg: @@ -116,6 +117,7 @@ allOf: contains: enum: - qcom,qcm2290-qmp-usb3-phy + - qcom,shikra-qmp-usb3-phy - qcom,sm6115-qmp-usb3-phy then: properties: From 1d37ad98d4c0fe93ed7d78a91bab227e429cb8fa Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Sat, 21 Mar 2026 22:43:45 +0530 Subject: [PATCH 0839/1330] dt-bindings: phy: qcom,qusb2: Add bindings for Shikra Update dt-bindings to add Shikra to QUSB2 Phy list. Signed-off-by: Krishna Kurapati (cherry picked from commit 11e223ccc7532eeafd4f54ac90c347fb0acce67d) --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 39851ba9de436..ddbddeec6fb16 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -28,6 +28,7 @@ properties: - qcom,qcm2290-qusb2-phy - qcom,qcs615-qusb2-phy - qcom,sdm660-qusb2-phy + - qcom,shikra-qusb2-phy - qcom,sm4250-qusb2-phy - qcom,sm6115-qusb2-phy - items: From 79632feb247bf433c92427b478501a7c6d8d5dc7 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Sat, 21 Mar 2026 22:45:05 +0530 Subject: [PATCH 0840/1330] dt-bindings: usb: qcom,snps-dwc3: Add Shikra compatible Introduce the compatible definition for Shikra QCOM SNPS DWC3. Signed-off-by: Krishna Kurapati (cherry picked from commit d3a76a6773166a28221ab5083100796420bbacb0) --- Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml index 7d784a648b7d9..ed0268d16567a 100644 --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml @@ -59,6 +59,7 @@ properties: - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 + - qcom,shikra-dwc3 - qcom,sm4250-dwc3 - qcom,sm6115-dwc3 - qcom,sm6125-dwc3 @@ -352,6 +353,8 @@ allOf: - qcom,sar2130p-dwc3 - qcom,sc8180x-dwc3 - qcom,sc8180x-dwc3-mp + - qcom,shikra-dwc3 + - qcom,sm4250-dwc3 - qcom,sm6115-dwc3 - qcom,sm6125-dwc3 - qcom,sm8150-dwc3 @@ -424,6 +427,7 @@ allOf: - qcom,ipq8074-dwc3 - qcom,msm8953-dwc3 - qcom,msm8998-dwc3 + - qcom,shikra-dwc3 then: properties: interrupts: From aee4f0174be45ea4f82cd955e39800ea176659ef Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Sat, 21 Mar 2026 22:47:32 +0530 Subject: [PATCH 0841/1330] phy: qcom-qusb2: Add support for Shikra Add init sequence and phy configuration for Shikra. Signed-off-by: Krishna Kurapati (cherry picked from commit 11e34e80ea71a20af56566607ff1b9d288a429c5) --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index eb93015be841f..8014141e92f2a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -381,6 +381,19 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = { .autoresume_en = BIT(3), }; +static const struct qusb2_phy_cfg shikra_phy_cfg = { + .tbl = qcs615_init_tbl, + .tbl_num = ARRAY_SIZE(qcs615_init_tbl), + .regs = ipq6018_regs_layout, + + .has_pll_test = true, + .se_clk_scheme_default = true, + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), + .mask_core_ready = PLL_LOCKED, + .autoresume_en = BIT(3), + .update_tune1_with_efuse = false, +}; + static const struct qusb2_phy_cfg sm6115_phy_cfg = { .tbl = sm6115_init_tbl, .tbl_num = ARRAY_SIZE(sm6115_init_tbl), @@ -958,6 +971,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = { }, { .compatible = "qcom,sdm660-qusb2-phy", .data = &sdm660_phy_cfg, + }, { + .compatible = "qcom,shikra-qusb2-phy", + .data = &shikra_phy_cfg, }, { .compatible = "qcom,sm4250-qusb2-phy", .data = &sm6115_phy_cfg, From a8e71b98f710eacaeaaa78bd40bd00970fd54027 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Sat, 21 Mar 2026 22:48:49 +0530 Subject: [PATCH 0842/1330] phy: qcom: qmp-usbc: Add qmp configuration for Shikra Provide PHY configuration for the USB QMP PHY for Shikra Platform. Signed-off-by: Krishna Kurapati (cherry picked from commit 36fde32c1b5570075ea9c26fb7e3a6c3c20e7d64) --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c index 0dd7000614f44..634b4da116595 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -2019,6 +2019,9 @@ static const struct of_device_id qmp_usbc_of_match_table[] = { }, { .compatible = "qcom,sdm660-qmp-usb3-phy", .data = &sdm660_usb3phy_cfg, + }, { + .compatible = "qcom,shikra-qmp-usb3-phy", + .data = &qcs615_usb3phy_cfg, }, { .compatible = "qcom,sm6115-qmp-usb3-phy", .data = &qcm2290_usb3phy_cfg, From 228d7cc1fd3dc443dd400240bfc71de3facb8054 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 1 Apr 2026 11:39:17 +0530 Subject: [PATCH 0843/1330] dt-bindings: interconnect: document the RPM Network-On-Chip interconnect in Shikra SoC Document the RPM Network-On-Chip Interconnect for the Qualcomm Shikra platform. Signed-off-by: Raviteja Laggyshetty (cherry picked from commit ada9ccf8cbe9c3b41564d60a7794ca389ba5eb30) --- .../bindings/interconnect/qcom,shikra.yaml | 165 ++++++++++++++++++ .../dt-bindings/interconnect/qcom,shikra.h | 121 +++++++++++++ 2 files changed, 286 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml create mode 100644 include/dt-bindings/interconnect/qcom,shikra.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml new file mode 100644 index 0000000000000..f48fd25d6a33f --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,shikra.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra Network-On-Chip interconnect + +maintainers: + - Raviteja Laggyshetty + +description: | + The Qualcomm Shikra interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,shikra-config-noc + - qcom,shikra-mem-noc-core + - qcom,shikra-sys-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + allOf: + - $ref: qcom,rpm-common.yaml# + + properties: + compatible: + enum: + - qcom,shikra-clk-virt + - qcom,shikra-mc-virt + - qcom,shikra-mmrt-virt + - qcom,shikra-mmnrt-virt + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: qcom,rpm-common.yaml# + - if: + properties: + compatible: + const: qcom,shikra-mem-noc-core + + then: + properties: + clocks: + items: + - description: GPU-NoC AXI clock + + clock-names: + items: + - const: gpu_axi + + - if: + properties: + compatible: + const: qcom,shikra-sys-noc + + then: + properties: + clocks: + items: + - description: EMAC0-NoC AXI clock. + - description: EMAC1-NoC AXI clock. + - description: USB2-NoC AXI clock. + - description: USB3-NoC AXI clock. + + clock-names: + items: + - const: emac0_axi + - const: emac1_axi + - const: usb2_axi + - const: usb3_axi + + - if: + properties: + compatible: + enum: + - qcom,sm6115-clk-virt + - qcom,sm6115-config-noc + - qcom,sm6115-mc-virt + - qcom,sm6115-mmrt-virt + - qcom,sm6115-mmnrt-virt + + then: + properties: + clocks: false + clock-names: false + +unevaluatedProperties: false + +examples: + - | + system_noc: interconnect@1880000 { + compatible = "qcom,shikra-sys-noc"; + reg = <0x01880000 0x6a080>; + #interconnect-cells = <2>; + clocks = <&gcc_emac0_axi_sys_noc_clk>, + <&gcc_emac1_axi_sys_noc_clk>, + <&gcc_sys_noc_usb2_prim_axi_clk>, + <&gcc_sys_noc_usb3_prim_axi_clk>; + clock-names = "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi"; + + clk_virt: interconnect-clk { + compatible = "qcom,shikra-clk-virt"; + #interconnect-cells = <2>; + }; + + mc_virt: interconnect-mc { + compatible = "qcom,shikra-mc-virt"; + #interconnect-cells = <2>; + }; + + mmnrt_virt: interconnect-mmnrt { + compatible = "qcom,shikra-mmnrt-virt"; + #interconnect-cells = <2>; + }; + + mmrt_virt: interconnect-mmrt { + compatible = "qcom,shikra-mmrt-virt"; + #interconnect-cells = <2>; + }; + }; + + config_noc: interconnect@1900000 { + compatible = "qcom,shikra-config-noc"; + reg = <0x01900000 0x8080>; + #interconnect-cells = <2>; + }; + + mem_noc: interconnect@d00000 { + compatible = "qcom,shikra-mem-noc-core"; + reg = <0x00d00000 0x43080>; + #interconnect-cells = <2>; + clocks = <&gcc_ddrss_gpu_axi_clk>; + clock-names = "gpu_axi"; + }; diff --git a/include/dt-bindings/interconnect/qcom,shikra.h b/include/dt-bindings/interconnect/qcom,shikra.h new file mode 100644 index 0000000000000..a42ea22ee162c --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,shikra.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H + +#define MASTER_QUP_CORE_0 0 +#define SLAVE_QUP_CORE_0 1 + +#define SNOC_CNOC_MAS 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_AHB2PHY_USB 2 +#define SLAVE_APSS_THROTTLE_CFG 3 +#define SLAVE_AUDIO 4 +#define SLAVE_BOOT_ROM 5 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6 +#define SLAVE_CAMERA_CFG 7 +#define SLAVE_CDSP_THROTTLE_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_DSP_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_RBCPR_MX_CFG 12 +#define SLAVE_CRYPTO_0_CFG 13 +#define SLAVE_DDR_SS_CFG 14 +#define SLAVE_DISPLAY_CFG 15 +#define SLAVE_EMAC0_CFG 16 +#define SLAVE_EMAC1_CFG 17 +#define SLAVE_GPU_CFG 18 +#define SLAVE_GPU_THROTTLE_CFG 19 +#define SLAVE_HWKM 20 +#define SLAVE_IMEM_CFG 21 +#define SLAVE_MAPSS 22 +#define SLAVE_MDSP_MPU_CFG 23 +#define SLAVE_MESSAGE_RAM 24 +#define SLAVE_MSS 25 +#define SLAVE_PCIE_CFG 26 +#define SLAVE_PDM 27 +#define SLAVE_PIMEM_CFG 28 +#define SLAVE_PKA_WRAPPER_CFG 29 +#define SLAVE_PMIC_ARB 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QM_CFG 32 +#define SLAVE_QM_MPU_CFG 33 +#define SLAVE_QPIC 34 +#define SLAVE_QUP_0 35 +#define SLAVE_RPM 36 +#define SLAVE_SDCC_1 37 +#define SLAVE_SDCC_2 38 +#define SLAVE_SECURITY 39 +#define SLAVE_SNOC_CFG 40 +#define SNOC_SF_THROTTLE_CFG 41 +#define SLAVE_TLMM 42 +#define SLAVE_TSCSS 43 +#define SLAVE_USB2 44 +#define SLAVE_USB3 45 +#define SLAVE_VENUS_CFG 46 +#define SLAVE_VENUS_THROTTLE_CFG 47 +#define SLAVE_VSENSE_CTRL_CFG 48 +#define SLAVE_SERVICE_CNOC 49 + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_GRAPHICS_3D 0 +#define MASTER_MNOC_HF_MEM_NOC 1 +#define MASTER_ANOC_PCIE_MEM_NOC 2 +#define MASTER_SNOC_SF_MEM_NOC 3 +#define MASTER_AMPSS_M0 4 +#define MASTER_SYS_TCU 5 +#define SLAVE_LLCC 6 +#define SLAVE_MEMNOC_SNOC 7 +#define SLAVE_MEM_NOC_PCIE_SNOC 8 + +#define MASTER_CAMNOC_SF 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define SLAVE_MMNRT_VIRT 3 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_MDP_PORT0 1 +#define MASTER_MMRT_VIRT 2 +#define SLAVE_MM_MEMNOC 3 + +#define MASTER_SNOC_CFG 0 +#define MASTER_TIC 1 +#define MASTER_ANOC_SNOC 2 +#define MASTER_MEMNOC_PCIE 3 +#define MASTER_MEMNOC_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_PCIE2_0 6 +#define MASTER_QDSS_BAM 7 +#define MASTER_QPIC 8 +#define MASTER_QUP_0 9 +#define CNOC_SNOC_MAS 10 +#define MASTER_AUDIO 11 +#define MASTER_EMAC_0 12 +#define MASTER_EMAC_1 13 +#define MASTER_QDSS_ETR 14 +#define MASTER_SDCC_1 15 +#define MASTER_SDCC_2 16 +#define MASTER_USB2_0 17 +#define MASTER_USB3 18 +#define MASTER_CRYPTO_CORE0 19 +#define SLAVE_APPSS 20 +#define SLAVE_MCUSS 21 +#define SLAVE_WCSS 22 +#define SLAVE_MEMNOC_SF 23 +#define SNOC_CNOC_SLV 24 +#define SLAVE_BOOTIMEM 25 +#define SLAVE_OCIMEM 26 +#define SLAVE_PIMEM 27 +#define SLAVE_SERVICE_SNOC 28 +#define SLAVE_PCIE2_0 29 +#define SLAVE_QDSS_STM 30 +#define SLAVE_TCU 31 +#define SLAVE_PCIE_MEMNOC 32 +#define SLAVE_ANOC_SNOC 33 + +#endif From 9e730ea640ce40237ceaaca5053946fe5bc1e050 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 1 Apr 2026 11:44:52 +0530 Subject: [PATCH 0844/1330] interconnect: qcom: add Shikra interconnect provider driver Add driver for the Qualcomm interconnect buses found in Shikra based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Signed-off-by: Raviteja Laggyshetty (cherry picked from commit 0f43d105a7ebc48c42c80b49aee6e9b1dd3dc564) --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/shikra.c | 1810 ++++++++++++++++++++++++++++ 3 files changed, 1821 insertions(+) create mode 100644 drivers/interconnect/qcom/shikra.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index bb1cb8a640c17..aa2b14420b055 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -274,6 +274,15 @@ config INTERCONNECT_QCOM_SDX75 This is a driver for the Qualcomm Network-on-Chip on sdx75-based platforms. +config INTERCONNECT_QCOM_SHIKRA + tristate "Qualcomm SHIKRA interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on shikra-based + platforms. + config INTERCONNECT_QCOM_SM6115 tristate "Qualcomm SM6115 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 6eedff043b412..52540dfbc3488 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -34,6 +34,7 @@ qnoc-sdm845-objs := sdm845.o qnoc-sdx55-objs := sdx55.o qnoc-sdx65-objs := sdx65.o qnoc-sdx75-objs := sdx75.o +qnoc-shikra-objs := shikra.o qnoc-sm6115-objs := sm6115.o qnoc-sm6350-objs := sm6350.o qnoc-sm7150-objs := sm7150.o @@ -78,6 +79,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o +obj-$(CONFIG_INTERCONNECT_QCOM_SHIKRA) += qnoc-shikra.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) += qnoc-sm6115.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM7150) += qnoc-sm7150.o diff --git a/drivers/interconnect/qcom/shikra.c b/drivers/interconnect/qcom/shikra.c new file mode 100644 index 0000000000000..30a9a5b10db86 --- /dev/null +++ b/drivers/interconnect/qcom/shikra.c @@ -0,0 +1,1810 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "icc-rpm.h" + +static const char * const sys_noc_intf_clocks[] = { + "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi", +}; + +static const char * const memnoc_intf_clocks[] = { + "gpu_axi", +}; + +enum { + SHIKRA_MASTER_QUP_CORE_0 = 1, + SHIKRA_SNOC_CNOC_MAS, + SHIKRA_MASTER_QDSS_DAP, + SHIKRA_MASTER_LLCC, + SHIKRA_MASTER_GRAPHICS_3D, + SHIKRA_MASTER_MNOC_HF_MEM_NOC, + SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, + SHIKRA_MASTER_SNOC_SF_MEM_NOC, + SHIKRA_MASTER_AMPSS_M0, + SHIKRA_MASTER_SYS_TCU, + SHIKRA_MASTER_CAMNOC_SF, + SHIKRA_MASTER_VIDEO_P0, + SHIKRA_MASTER_VIDEO_PROC, + SHIKRA_MASTER_CAMNOC_HF, + SHIKRA_MASTER_MDP_PORT0, + SHIKRA_MASTER_MMRT_VIRT, + SHIKRA_MASTER_SNOC_CFG, + SHIKRA_MASTER_TIC, + SHIKRA_MASTER_ANOC_SNOC, + SHIKRA_MASTER_MEMNOC_PCIE, + SHIKRA_MASTER_MEMNOC_SNOC, + SHIKRA_MASTER_PIMEM, + SHIKRA_MASTER_PCIE2_0, + SHIKRA_MASTER_QDSS_BAM, + SHIKRA_MASTER_QPIC, + SHIKRA_MASTER_QUP_0, + SHIKRA_CNOC_SNOC_MAS, + SHIKRA_MASTER_AUDIO, + SHIKRA_MASTER_EMAC_0, + SHIKRA_MASTER_EMAC_1, + SHIKRA_MASTER_QDSS_ETR, + SHIKRA_MASTER_SDCC_1, + SHIKRA_MASTER_SDCC_2, + SHIKRA_MASTER_USB2_0, + SHIKRA_MASTER_USB3, + SHIKRA_MASTER_CRYPTO_CORE0, + + SHIKRA_SLAVE_QUP_CORE_0, + SHIKRA_SLAVE_AHB2PHY_USB, + SHIKRA_SLAVE_APSS_THROTTLE_CFG, + SHIKRA_SLAVE_AUDIO, + SHIKRA_SLAVE_BOOT_ROM, + SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SHIKRA_SLAVE_CAMERA_CFG, + SHIKRA_SLAVE_CDSP_THROTTLE_CFG, + SHIKRA_SLAVE_CLK_CTL, + SHIKRA_SLAVE_DSP_CFG, + SHIKRA_SLAVE_RBCPR_CX_CFG, + SHIKRA_SLAVE_RBCPR_MX_CFG, + SHIKRA_SLAVE_CRYPTO_0_CFG, + SHIKRA_SLAVE_DDR_SS_CFG, + SHIKRA_SLAVE_DISPLAY_CFG, + SHIKRA_SLAVE_EMAC0_CFG, + SHIKRA_SLAVE_EMAC1_CFG, + SHIKRA_SLAVE_GPU_CFG, + SHIKRA_SLAVE_GPU_THROTTLE_CFG, + SHIKRA_SLAVE_HWKM, + SHIKRA_SLAVE_IMEM_CFG, + SHIKRA_SLAVE_MAPSS, + SHIKRA_SLAVE_MDSP_MPU_CFG, + SHIKRA_SLAVE_MESSAGE_RAM, + SHIKRA_SLAVE_MSS, + SHIKRA_SLAVE_PCIE_CFG, + SHIKRA_SLAVE_PDM, + SHIKRA_SLAVE_PIMEM_CFG, + SHIKRA_SLAVE_PKA_WRAPPER_CFG, + SHIKRA_SLAVE_PMIC_ARB, + SHIKRA_SLAVE_QDSS_CFG, + SHIKRA_SLAVE_QM_CFG, + SHIKRA_SLAVE_QM_MPU_CFG, + SHIKRA_SLAVE_QPIC, + SHIKRA_SLAVE_QUP_0, + SHIKRA_SLAVE_RPM, + SHIKRA_SLAVE_SDCC_1, + SHIKRA_SLAVE_SDCC_2, + SHIKRA_SLAVE_SECURITY, + SHIKRA_SLAVE_SNOC_CFG, + SHIKRA_SNOC_SF_THROTTLE_CFG, + SHIKRA_SLAVE_TLMM, + SHIKRA_SLAVE_TSCSS, + SHIKRA_SLAVE_USB2, + SHIKRA_SLAVE_USB3, + SHIKRA_SLAVE_VENUS_CFG, + SHIKRA_SLAVE_VENUS_THROTTLE_CFG, + SHIKRA_SLAVE_VSENSE_CTRL_CFG, + SHIKRA_SLAVE_SERVICE_CNOC, + SHIKRA_SLAVE_EBI_CH0, + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, + SHIKRA_SLAVE_MMNRT_VIRT, + SHIKRA_SLAVE_MM_MEMNOC, + SHIKRA_SLAVE_APPSS, + SHIKRA_SLAVE_MCUSS, + SHIKRA_SLAVE_WCSS, + SHIKRA_SLAVE_MEMNOC_SF, + SHIKRA_SNOC_CNOC_SLV, + SHIKRA_SLAVE_BOOTIMEM, + SHIKRA_SLAVE_OCIMEM, + SHIKRA_SLAVE_PIMEM, + SHIKRA_SLAVE_SERVICE_SNOC, + SHIKRA_SLAVE_PCIE2_0, + SHIKRA_SLAVE_QDSS_STM, + SHIKRA_SLAVE_TCU, + SHIKRA_SLAVE_PCIE_MEMNOC, + SHIKRA_SLAVE_ANOC_SNOC, +}; + +/* Master nodes */ +static const u16 qup0_core_master_links[] = { + SHIKRA_SLAVE_QUP_CORE_0, +}; + +static struct qcom_icc_node qup0_core_master = { + .id = SHIKRA_MASTER_QUP_CORE_0, + .name = "qup0_core_master", + .buswidth = 4, + .mas_rpm_id = 170, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qup0_core_master_links), + .links = qup0_core_master_links, +}; + +static const u16 qnm_snoc_cnoc_links[] = { + SHIKRA_SLAVE_AHB2PHY_USB, + SHIKRA_SLAVE_APSS_THROTTLE_CFG, + SHIKRA_SLAVE_AUDIO, + SHIKRA_SLAVE_BOOT_ROM, + SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SHIKRA_SLAVE_CAMERA_CFG, + SHIKRA_SLAVE_CDSP_THROTTLE_CFG, + SHIKRA_SLAVE_CLK_CTL, + SHIKRA_SLAVE_DSP_CFG, + SHIKRA_SLAVE_RBCPR_CX_CFG, + SHIKRA_SLAVE_RBCPR_MX_CFG, + SHIKRA_SLAVE_CRYPTO_0_CFG, + SHIKRA_SLAVE_DDR_SS_CFG, + SHIKRA_SLAVE_DISPLAY_CFG, + SHIKRA_SLAVE_EMAC0_CFG, + SHIKRA_SLAVE_EMAC1_CFG, + SHIKRA_SLAVE_GPU_CFG, + SHIKRA_SLAVE_GPU_THROTTLE_CFG, + SHIKRA_SLAVE_HWKM, + SHIKRA_SLAVE_IMEM_CFG, + SHIKRA_SLAVE_MAPSS, + SHIKRA_SLAVE_MDSP_MPU_CFG, + SHIKRA_SLAVE_MESSAGE_RAM, + SHIKRA_SLAVE_MSS, + SHIKRA_SLAVE_PCIE_CFG, + SHIKRA_SLAVE_PDM, + SHIKRA_SLAVE_PIMEM_CFG, + SHIKRA_SLAVE_PKA_WRAPPER_CFG, + SHIKRA_SLAVE_PMIC_ARB, + SHIKRA_SLAVE_QDSS_CFG, + SHIKRA_SLAVE_QM_CFG, + SHIKRA_SLAVE_QM_MPU_CFG, + SHIKRA_SLAVE_QPIC, + SHIKRA_SLAVE_QUP_0, + SHIKRA_SLAVE_RPM, + SHIKRA_SLAVE_SDCC_1, + SHIKRA_SLAVE_SDCC_2, + SHIKRA_SLAVE_SECURITY, + SHIKRA_SLAVE_SNOC_CFG, + SHIKRA_SNOC_SF_THROTTLE_CFG, + SHIKRA_SLAVE_TLMM, + SHIKRA_SLAVE_TSCSS, + SHIKRA_SLAVE_USB2, + SHIKRA_SLAVE_USB3, + SHIKRA_SLAVE_VENUS_CFG, + SHIKRA_SLAVE_VENUS_THROTTLE_CFG, + SHIKRA_SLAVE_VSENSE_CTRL_CFG, + SHIKRA_SLAVE_SERVICE_CNOC, +}; + +static struct qcom_icc_node qnm_snoc_cnoc = { + .id = SHIKRA_SNOC_CNOC_MAS, + .name = "qnm_snoc_cnoc", + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_snoc_cnoc_links), + .links = qnm_snoc_cnoc_links, +}; + +static const u16 xm_dap_links[] = { + SHIKRA_SLAVE_AHB2PHY_USB, + SHIKRA_SLAVE_APSS_THROTTLE_CFG, + SHIKRA_SLAVE_AUDIO, + SHIKRA_SLAVE_BOOT_ROM, + SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SHIKRA_SLAVE_CAMERA_CFG, + SHIKRA_SLAVE_CDSP_THROTTLE_CFG, + SHIKRA_SLAVE_CLK_CTL, + SHIKRA_SLAVE_DSP_CFG, + SHIKRA_SLAVE_RBCPR_CX_CFG, + SHIKRA_SLAVE_RBCPR_MX_CFG, + SHIKRA_SLAVE_CRYPTO_0_CFG, + SHIKRA_SLAVE_DDR_SS_CFG, + SHIKRA_SLAVE_DISPLAY_CFG, + SHIKRA_SLAVE_EMAC0_CFG, + SHIKRA_SLAVE_EMAC1_CFG, + SHIKRA_SLAVE_GPU_CFG, + SHIKRA_SLAVE_GPU_THROTTLE_CFG, + SHIKRA_SLAVE_HWKM, + SHIKRA_SLAVE_IMEM_CFG, + SHIKRA_SLAVE_MAPSS, + SHIKRA_SLAVE_MDSP_MPU_CFG, + SHIKRA_SLAVE_MESSAGE_RAM, + SHIKRA_SLAVE_MSS, + SHIKRA_SLAVE_PCIE_CFG, + SHIKRA_SLAVE_PDM, + SHIKRA_SLAVE_PIMEM_CFG, + SHIKRA_SLAVE_PKA_WRAPPER_CFG, + SHIKRA_SLAVE_PMIC_ARB, + SHIKRA_SLAVE_QDSS_CFG, + SHIKRA_SLAVE_QM_CFG, + SHIKRA_SLAVE_QM_MPU_CFG, + SHIKRA_SLAVE_QPIC, + SHIKRA_SLAVE_QUP_0, + SHIKRA_SLAVE_RPM, + SHIKRA_SLAVE_SDCC_1, + SHIKRA_SLAVE_SDCC_2, + SHIKRA_SLAVE_SECURITY, + SHIKRA_SLAVE_SNOC_CFG, + SHIKRA_SNOC_SF_THROTTLE_CFG, + SHIKRA_SLAVE_TLMM, + SHIKRA_SLAVE_TSCSS, + SHIKRA_SLAVE_USB2, + SHIKRA_SLAVE_USB3, + SHIKRA_SLAVE_VENUS_CFG, + SHIKRA_SLAVE_VENUS_THROTTLE_CFG, + SHIKRA_SLAVE_VSENSE_CTRL_CFG, + SHIKRA_SLAVE_SERVICE_CNOC, +}; + +static struct qcom_icc_node xm_dap = { + .id = SHIKRA_MASTER_QDSS_DAP, + .name = "xm_dap", + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_dap_links), + .links = xm_dap_links, +}; + +static const u16 llcc_mc_links[] = { + SHIKRA_SLAVE_EBI_CH0, +}; + +static struct qcom_icc_node llcc_mc = { + .id = SHIKRA_MASTER_LLCC, + .name = "llcc_mc", + .buswidth = 4, + .channels = 2, + .mas_rpm_id = 190, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(llcc_mc_links), + .links = llcc_mc_links, +}; + +static const u16 qnm_gpu_links[] = { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, +}; + +static struct qcom_icc_node qnm_gpu = { + .id = SHIKRA_MASTER_GRAPHICS_3D, + .name = "qnm_gpu", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 6, + .qos.urg_fwd_en = false, + .qos.areq_prio = 0, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_gpu_links), + .links = qnm_gpu_links, +}; + +static const u16 qnm_mnoc_hf_links[] = { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .id = SHIKRA_MASTER_MNOC_HF_MEM_NOC, + .name = "qnm_mnoc_hf", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 7, + .qos.urg_fwd_en = true, + .qos.areq_prio = 0, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_mnoc_hf_links), + .links = qnm_mnoc_hf_links, +}; + +static const u16 qnm_pcie_links[] = { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, +}; + +static struct qcom_icc_node qnm_pcie = { + .id = SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, + .name = "qnm_pcie", + .buswidth = 8, + .qos.qos_port = 4, + .qos.urg_fwd_en = true, + .qos.areq_prio = 0, + .mas_rpm_id = 185, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_pcie_links), + .links = qnm_pcie_links, +}; + +static const u16 qnm_snoc_sf_links[] = { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .id = SHIKRA_MASTER_SNOC_SF_MEM_NOC, + .name = "qnm_snoc_sf", + .buswidth = 16, + .qos.qos_port = 3, + .qos.urg_fwd_en = true, + .qos.areq_prio = 0, + .mas_rpm_id = 76, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_snoc_sf_links), + .links = qnm_snoc_sf_links, +}; + +static const u16 xm_apps_links[] = { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, +}; + +static struct qcom_icc_node xm_apps = { + .id = SHIKRA_MASTER_AMPSS_M0, + .name = "xm_apps", + .buswidth = 16, + .qos.qos_port = 5, + .qos.urg_fwd_en = false, + .qos.areq_prio = 0, + .mas_rpm_id = 0, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_apps_links), + .links = xm_apps_links, +}; + +static const u16 xm_tcu_links[] = { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, +}; + +static struct qcom_icc_node xm_tcu = { + .id = SHIKRA_MASTER_SYS_TCU, + .name = "xm_tcu", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 2, + .qos.urg_fwd_en = false, + .qos.areq_prio = 6, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_tcu_links), + .links = xm_tcu_links, +}; + +static const u16 qnm_camera_nrt_links[] = { + SHIKRA_SLAVE_MMNRT_VIRT, +}; + +static struct qcom_icc_node qnm_camera_nrt = { + .id = SHIKRA_MASTER_CAMNOC_SF, + .name = "qnm_camera_nrt", + .buswidth = 32, + .qos.ap_owned = true, + .qos.qos_port = 3, + .qos.urg_fwd_en = false, + .qos.areq_prio = 3, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_camera_nrt_links), + .links = qnm_camera_nrt_links, +}; + +static const u16 qxm_venus0_links[] = { + SHIKRA_SLAVE_MMNRT_VIRT, +}; + +static struct qcom_icc_node qxm_venus0 = { + .id = SHIKRA_MASTER_VIDEO_P0, + .name = "qxm_venus0", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 8, + .qos.urg_fwd_en = true, + .qos.areq_prio = 0, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qxm_venus0_links), + .links = qxm_venus0_links, +}; + +static const u16 qxm_venus_cpu_links[] = { + SHIKRA_SLAVE_MMNRT_VIRT, +}; + +static struct qcom_icc_node qxm_venus_cpu = { + .id = SHIKRA_MASTER_VIDEO_PROC, + .name = "qxm_venus_cpu", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 12, + .qos.urg_fwd_en = false, + .qos.areq_prio = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qxm_venus_cpu_links), + .links = qxm_venus_cpu_links, +}; + +static const u16 qnm_camera_rt_links[] = { + SHIKRA_SLAVE_MM_MEMNOC, +}; + +static struct qcom_icc_node qnm_camera_rt = { + .id = SHIKRA_MASTER_CAMNOC_HF, + .name = "qnm_camera_rt", + .buswidth = 32, + .qos.ap_owned = true, + .qos.qos_port = 9, + .qos.urg_fwd_en = true, + .qos.areq_prio = 0, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_camera_rt_links), + .links = qnm_camera_rt_links, +}; + +static const u16 qxm_mdp0_links[] = { + SHIKRA_SLAVE_MM_MEMNOC, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .id = SHIKRA_MASTER_MDP_PORT0, + .name = "qxm_mdp0", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 4, + .qos.urg_fwd_en = true, + .qos.areq_prio = 0, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qxm_mdp0_links), + .links = qxm_mdp0_links, +}; + +static const u16 mmrt_virt_master_links[] = { + SHIKRA_SLAVE_MM_MEMNOC, +}; + +static struct qcom_icc_node mmrt_virt_master = { + .id = SHIKRA_MASTER_MMRT_VIRT, + .name = "mmrt_virt_master", + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mmrt_virt_master_links), + .links = mmrt_virt_master_links, +}; + +static const u16 qhm_snoc_cfg_links[] = { + SHIKRA_SLAVE_SERVICE_SNOC, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .id = SHIKRA_MASTER_SNOC_CFG, + .name = "qhm_snoc_cfg", + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qhm_snoc_cfg_links), + .links = qhm_snoc_cfg_links, +}; + +static const u16 qhm_tic_links[] = { + SHIKRA_SLAVE_APPSS, + SHIKRA_SLAVE_MCUSS, + SHIKRA_SLAVE_WCSS, + SHIKRA_SLAVE_MEMNOC_SF, + SHIKRA_SNOC_CNOC_SLV, + SHIKRA_SLAVE_BOOTIMEM, + SHIKRA_SLAVE_OCIMEM, + SHIKRA_SLAVE_PIMEM, + SHIKRA_SLAVE_QDSS_STM, + SHIKRA_SLAVE_TCU, +}; + +static struct qcom_icc_node qhm_tic = { + .id = SHIKRA_MASTER_TIC, + .name = "qhm_tic", + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qhm_tic_links), + .links = qhm_tic_links, +}; + +static const u16 qnm_anoc_snoc_links[] = { + SHIKRA_SLAVE_MEMNOC_SF, +}; + +static struct qcom_icc_node qnm_anoc_snoc = { + .id = SHIKRA_MASTER_ANOC_SNOC, + .name = "qnm_anoc_snoc", + .buswidth = 16, + .mas_rpm_id = 110, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_anoc_snoc_links), + .links = qnm_anoc_snoc_links, +}; + +static const u16 qnm_memnoc_pcie_links[] = { + SHIKRA_SLAVE_PCIE2_0, +}; + +static struct qcom_icc_node qnm_memnoc_pcie = { + .id = SHIKRA_MASTER_MEMNOC_PCIE, + .name = "qnm_memnoc_pcie", + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_memnoc_pcie_links), + .links = qnm_memnoc_pcie_links, +}; + +static const u16 qnm_memnoc_snoc_links[] = { + SHIKRA_SLAVE_APPSS, + SHIKRA_SLAVE_MCUSS, + SHIKRA_SLAVE_WCSS, + SHIKRA_SNOC_CNOC_SLV, + SHIKRA_SLAVE_BOOTIMEM, + SHIKRA_SLAVE_OCIMEM, + SHIKRA_SLAVE_PIMEM, + SHIKRA_SLAVE_QDSS_STM, + SHIKRA_SLAVE_TCU, +}; + +static struct qcom_icc_node qnm_memnoc_snoc = { + .id = SHIKRA_MASTER_MEMNOC_SNOC, + .name = "qnm_memnoc_snoc", + .buswidth = 8, + .mas_rpm_id = 184, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_memnoc_snoc_links), + .links = qnm_memnoc_snoc_links, +}; + +static const u16 qxm_pimem_links[] = { + SHIKRA_SLAVE_MEMNOC_SF, + SHIKRA_SLAVE_OCIMEM, +}; + +static struct qcom_icc_node qxm_pimem = { + .id = SHIKRA_MASTER_PIMEM, + .name = "qxm_pimem", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 14, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qxm_pimem_links), + .links = qxm_pimem_links, +}; + +static const u16 xm_pcie2_0_links[] = { + SHIKRA_SLAVE_PCIE_MEMNOC, +}; + +static struct qcom_icc_node xm_pcie2_0 = { + .id = SHIKRA_MASTER_PCIE2_0, + .name = "xm_pcie2_0", + .buswidth = 8, + .qos.qos_port = 21, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = 186, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_pcie2_0_links), + .links = xm_pcie2_0_links, +}; + +static const u16 qhm_qdss_bam_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .id = SHIKRA_MASTER_QDSS_BAM, + .name = "qhm_qdss_bam", + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_port = 2, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qhm_qdss_bam_links), + .links = qhm_qdss_bam_links, +}; + +static const u16 qhm_qpic_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qhm_qpic = { + .id = SHIKRA_MASTER_QPIC, + .name = "qhm_qpic", + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_port = 1, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qhm_qpic_links), + .links = qhm_qpic_links, +}; + +static const u16 qhm_qup0_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qhm_qup0 = { + .id = SHIKRA_MASTER_QUP_0, + .name = "qhm_qup0", + .buswidth = 4, + .qos.qos_port = 0, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = 166, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qhm_qup0_links), + .links = qhm_qup0_links, +}; + +static const u16 qnm_cnoc_snoc_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qnm_cnoc_snoc = { + .id = SHIKRA_CNOC_SNOC_MAS, + .name = "qnm_cnoc_snoc", + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_port = 7, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qnm_cnoc_snoc_links), + .links = qnm_cnoc_snoc_links, +}; + +static const u16 qxm_audio_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qxm_audio = { + .id = SHIKRA_MASTER_AUDIO, + .name = "qxm_audio", + .buswidth = 8, + .qos.qos_port = 22, + .qos.urg_fwd_en = false, + .qos.areq_prio = 3, + .mas_rpm_id = 78, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qxm_audio_links), + .links = qxm_audio_links, +}; + +static const u16 xm_emac_0_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_emac_0 = { + .id = SHIKRA_MASTER_EMAC_0, + .name = "xm_emac_0", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 19, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_emac_0_links), + .links = xm_emac_0_links, +}; + +static const u16 xm_emac_1_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_emac_1 = { + .id = SHIKRA_MASTER_EMAC_1, + .name = "xm_emac_1", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 20, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_emac_1_links), + .links = xm_emac_1_links, +}; + +static const u16 xm_qdss_etr_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .id = SHIKRA_MASTER_QDSS_ETR, + .name = "xm_qdss_etr", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 11, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_qdss_etr_links), + .links = xm_qdss_etr_links, +}; + +static const u16 xm_sdc1_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_sdc1 = { + .id = SHIKRA_MASTER_SDCC_1, + .name = "xm_sdc1", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 13, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_sdc1_links), + .links = xm_sdc1_links, +}; + +static const u16 xm_sdc2_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_sdc2 = { + .id = SHIKRA_MASTER_SDCC_2, + .name = "xm_sdc2", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 17, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_sdc2_links), + .links = xm_sdc2_links, +}; + +static const u16 xm_usb2_0_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_usb2_0 = { + .id = SHIKRA_MASTER_USB2_0, + .name = "xm_usb2_0", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 24, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_usb2_0_links), + .links = xm_usb2_0_links, +}; + +static const u16 xm_usb3_0_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .id = SHIKRA_MASTER_USB3, + .name = "xm_usb3_0", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 18, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(xm_usb3_0_links), + .links = xm_usb3_0_links, +}; + +static const u16 crypto_c0_links[] = { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node crypto_c0 = { + .id = SHIKRA_MASTER_CRYPTO_CORE0, + .name = "crypto_c0", + .buswidth = 8, + .qos.qos_port = 16, + .qos.urg_fwd_en = false, + .qos.areq_prio = 2, + .mas_rpm_id = 23, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(crypto_c0_links), + .links = crypto_c0_links, +}; + +/* Slave nodes */ +static struct qcom_icc_node qup0_core_slave = { + .id = SHIKRA_SLAVE_QUP_CORE_0, + .name = "qup0_core_slave", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 264, +}; + +static struct qcom_icc_node qhs_ahb2phy_usb = { + .id = SHIKRA_SLAVE_AHB2PHY_USB, + .name = "qhs_ahb2phy_usb", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_apss_throttle_cfg = { + .id = SHIKRA_SLAVE_APSS_THROTTLE_CFG, + .name = "qhs_apss_throttle_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_audio = { + .id = SHIKRA_SLAVE_AUDIO, + .name = "qhs_audio", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_boot_rom = { + .id = SHIKRA_SLAVE_BOOT_ROM, + .name = "qhs_boot_rom", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { + .id = SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .name = "qhs_camera_nrt_throttle_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_camera_ss_cfg = { + .id = SHIKRA_SLAVE_CAMERA_CFG, + .name = "qhs_camera_ss_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_cdsp_throttle_cfg = { + .id = SHIKRA_SLAVE_CDSP_THROTTLE_CFG, + .name = "qhs_cdsp_throttle_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .id = SHIKRA_SLAVE_CLK_CTL, + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_compute_dsp_cfg = { + .id = SHIKRA_SLAVE_DSP_CFG, + .name = "qhs_compute_dsp_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .id = SHIKRA_SLAVE_RBCPR_CX_CFG, + .name = "qhs_cpr_cx", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .id = SHIKRA_SLAVE_RBCPR_MX_CFG, + .name = "qhs_cpr_mx", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .id = SHIKRA_SLAVE_CRYPTO_0_CFG, + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_ddr_ss_cfg = { + .id = SHIKRA_SLAVE_DDR_SS_CFG, + .name = "qhs_ddr_ss_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_disp_ss_cfg = { + .id = SHIKRA_SLAVE_DISPLAY_CFG, + .name = "qhs_disp_ss_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_emac0_cfg = { + .id = SHIKRA_SLAVE_EMAC0_CFG, + .name = "qhs_emac0_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_emac1_cfg = { + .id = SHIKRA_SLAVE_EMAC1_CFG, + .name = "qhs_emac1_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_gpu_cfg = { + .id = SHIKRA_SLAVE_GPU_CFG, + .name = "qhs_gpu_cfg", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_gpu_throttle_cfg = { + .id = SHIKRA_SLAVE_GPU_THROTTLE_CFG, + .name = "qhs_gpu_throttle_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_hwkm = { + .id = SHIKRA_SLAVE_HWKM, + .name = "qhs_hwkm", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .id = SHIKRA_SLAVE_IMEM_CFG, + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_mapss = { + .id = SHIKRA_SLAVE_MAPSS, + .name = "qhs_mapss", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_mdsp_mpu_cfg = { + .id = SHIKRA_SLAVE_MDSP_MPU_CFG, + .name = "qhs_mdsp_mpu_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_mesg_ram = { + .id = SHIKRA_SLAVE_MESSAGE_RAM, + .name = "qhs_mesg_ram", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_mss = { + .id = SHIKRA_SLAVE_MSS, + .name = "qhs_mss", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_pcie_cfg = { + .id = SHIKRA_SLAVE_PCIE_CFG, + .name = "qhs_pcie_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_pdm = { + .id = SHIKRA_SLAVE_PDM, + .name = "qhs_pdm", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .id = SHIKRA_SLAVE_PIMEM_CFG, + .name = "qhs_pimem_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_pka_wrapper = { + .id = SHIKRA_SLAVE_PKA_WRAPPER_CFG, + .name = "qhs_pka_wrapper", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_pmic_arb = { + .id = SHIKRA_SLAVE_PMIC_ARB, + .name = "qhs_pmic_arb", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .id = SHIKRA_SLAVE_QDSS_CFG, + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_qm_cfg = { + .id = SHIKRA_SLAVE_QM_CFG, + .name = "qhs_qm_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg = { + .id = SHIKRA_SLAVE_QM_MPU_CFG, + .name = "qhs_qm_mpu_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_qpic = { + .id = SHIKRA_SLAVE_QPIC, + .name = "qhs_qpic", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_qup0 = { + .id = SHIKRA_SLAVE_QUP_0, + .name = "qhs_qup0", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_rpm = { + .id = SHIKRA_SLAVE_RPM, + .name = "qhs_rpm", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .id = SHIKRA_SLAVE_SDCC_1, + .name = "qhs_sdc1", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .id = SHIKRA_SLAVE_SDCC_2, + .name = "qhs_sdc2", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_security = { + .id = SHIKRA_SLAVE_SECURITY, + .name = "qhs_security", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static const u16 qhs_snoc_cfg_links[] = { + SHIKRA_MASTER_SNOC_CFG, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .id = SHIKRA_SLAVE_SNOC_CFG, + .name = "qhs_snoc_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = 1, + .links = qhs_snoc_cfg_links, +}; + +static struct qcom_icc_node qhs_snoc_sf_throttle_cfg = { + .id = SHIKRA_SNOC_SF_THROTTLE_CFG, + .name = "qhs_snoc_sf_throttle_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_tlmm = { + .id = SHIKRA_SLAVE_TLMM, + .name = "qhs_tlmm", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_tscss = { + .id = SHIKRA_SLAVE_TSCSS, + .name = "qhs_tscss", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_usb2 = { + .id = SHIKRA_SLAVE_USB2, + .name = "qhs_usb2", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_usb3 = { + .id = SHIKRA_SLAVE_USB3, + .name = "qhs_usb3", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .id = SHIKRA_SLAVE_VENUS_CFG, + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg = { + .id = SHIKRA_SLAVE_VENUS_THROTTLE_CFG, + .name = "qhs_venus_throttle_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .id = SHIKRA_SLAVE_VSENSE_CTRL_CFG, + .name = "qhs_vsense_ctrl_cfg", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node srvc_cnoc = { + .id = SHIKRA_SLAVE_SERVICE_CNOC, + .name = "srvc_cnoc", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node ebi = { + .id = SHIKRA_SLAVE_EBI_CH0, + .name = "ebi", + .channels = 2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 0, +}; + +static const u16 qns_llcc_links[] = { + SHIKRA_MASTER_LLCC, +}; + +static struct qcom_icc_node qns_llcc = { + .id = SHIKRA_SLAVE_LLCC, + .name = "qns_llcc", + .channels = 2, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 312, + .num_links = 1, + .links = qns_llcc_links, +}; + +static const u16 qns_memnoc_snoc_links[] = { + SHIKRA_MASTER_MEMNOC_SNOC, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .id = SHIKRA_SLAVE_MEMNOC_SNOC, + .name = "qns_memnoc_snoc", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 314, + .num_links = 1, + .links = qns_memnoc_snoc_links, +}; + +static const u16 qns_pcie_links[] = { + SHIKRA_MASTER_MEMNOC_PCIE, +}; + +static struct qcom_icc_node qns_pcie = { + .id = SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, + .name = "qns_pcie", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = 1, + .links = qns_pcie_links, +}; + +static const u16 mmnrt_virt_slave_links[] = { + SHIKRA_MASTER_MMRT_VIRT, +}; + +static struct qcom_icc_node mmnrt_virt_slave = { + .id = SHIKRA_SLAVE_MMNRT_VIRT, + .name = "mmnrt_virt_slave", + .channels = 1, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = 1, + .links = mmnrt_virt_slave_links, +}; + +static const u16 qns_mm_memnoc_links[] = { + SHIKRA_MASTER_MNOC_HF_MEM_NOC, +}; + +static struct qcom_icc_node qns_mm_memnoc = { + .id = SHIKRA_SLAVE_MM_MEMNOC, + .name = "qns_mm_memnoc", + .channels = 1, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = 1, + .links = qns_mm_memnoc_links, +}; + +static struct qcom_icc_node qhs_apss = { + .id = SHIKRA_SLAVE_APPSS, + .name = "qhs_apss", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qhs_mcuss = { + .id = SHIKRA_SLAVE_MCUSS, + .name = "qhs_mcuss", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 319, +}; + +static struct qcom_icc_node qhs_wcss = { + .id = SHIKRA_SLAVE_WCSS, + .name = "qhs_wcss", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 23, +}; + +static const u16 qns_memnoc_sf_links[] = { + SHIKRA_MASTER_SNOC_SF_MEM_NOC, +}; + +static struct qcom_icc_node qns_memnoc_sf = { + .id = SHIKRA_SLAVE_MEMNOC_SF, + .name = "qns_memnoc_sf", + .channels = 1, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 313, + .num_links = 1, + .links = qns_memnoc_sf_links, +}; + +static const u16 qns_snoc_cnoc_links[] = { + SHIKRA_SNOC_CNOC_MAS, +}; + +static struct qcom_icc_node qns_snoc_cnoc = { + .id = SHIKRA_SNOC_CNOC_SLV, + .name = "qns_snoc_cnoc", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 25, + .num_links = 1, + .links = qns_snoc_cnoc_links, +}; + +static struct qcom_icc_node qxs_bootimem = { + .id = SHIKRA_SLAVE_BOOTIMEM, + .name = "qxs_bootimem", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node qxs_imem = { + .id = SHIKRA_SLAVE_OCIMEM, + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 26, +}; + +static struct qcom_icc_node qxs_pimem = { + .id = SHIKRA_SLAVE_PIMEM, + .name = "qxs_pimem", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node srvc_snoc = { + .id = SHIKRA_SLAVE_SERVICE_SNOC, + .name = "srvc_snoc", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node xs_pcie2_0 = { + .id = SHIKRA_SLAVE_PCIE2_0, + .name = "xs_pcie2_0", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .id = SHIKRA_SLAVE_QDSS_STM, + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 30, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .id = SHIKRA_SLAVE_TCU, + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static const u16 qns_pcie_memnoc_links[] = { + SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, +}; + +static struct qcom_icc_node qns_pcie_memnoc = { + .id = SHIKRA_SLAVE_PCIE_MEMNOC, + .name = "qns_pcie_memnoc", + .channels = 1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 317, + .num_links = 1, + .links = qns_pcie_memnoc_links, +}; + +static const u16 qns_anoc_snoc_links[] = { + SHIKRA_MASTER_ANOC_SNOC, +}; + +static struct qcom_icc_node qns_anoc_snoc = { + .id = SHIKRA_SLAVE_ANOC_SNOC, + .name = "qns_anoc_snoc", + .channels = 1, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 141, + .num_links = 1, + .links = qns_anoc_snoc_links, +}; + +/* NoC descriptors */ +static struct qcom_icc_node * const shikra_clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, +}; + +static const struct qcom_icc_desc shikra_clk_virt = { + .type = QCOM_ICC_QNOC, + .nodes = shikra_clk_virt_nodes, + .num_nodes = ARRAY_SIZE(shikra_clk_virt_nodes), + .bus_clk_desc = &qup_clk, + .keep_alive = true, +}; + +static struct qcom_icc_node * const shikra_config_noc_nodes[] = { + [SNOC_CNOC_MAS] = &qnm_snoc_cnoc, + [MASTER_QDSS_DAP] = &xm_dap, + [SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb, + [SLAVE_APSS_THROTTLE_CFG] = &qhs_apss_throttle_cfg, + [SLAVE_AUDIO] = &qhs_audio, + [SLAVE_BOOT_ROM] = &qhs_boot_rom, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, + [SLAVE_CAMERA_CFG] = &qhs_camera_ss_cfg, + [SLAVE_CDSP_THROTTLE_CFG] = &qhs_cdsp_throttle_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_DSP_CFG] = &qhs_compute_dsp_cfg, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_DDR_SS_CFG] = &qhs_ddr_ss_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_disp_ss_cfg, + [SLAVE_EMAC0_CFG] = &qhs_emac0_cfg, + [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, + [SLAVE_GPU_CFG] = &qhs_gpu_cfg, + [SLAVE_GPU_THROTTLE_CFG] = &qhs_gpu_throttle_cfg, + [SLAVE_HWKM] = &qhs_hwkm, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_MAPSS] = &qhs_mapss, + [SLAVE_MDSP_MPU_CFG] = &qhs_mdsp_mpu_cfg, + [SLAVE_MESSAGE_RAM] = &qhs_mesg_ram, + [SLAVE_MSS] = &qhs_mss, + [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper, + [SLAVE_PMIC_ARB] = &qhs_pmic_arb, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QM_CFG] = &qhs_qm_cfg, + [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, + [SLAVE_QPIC] = &qhs_qpic, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_RPM] = &qhs_rpm, + [SLAVE_SDCC_1] = &qhs_sdc1, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SECURITY] = &qhs_security, + [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, + [SNOC_SF_THROTTLE_CFG] = &qhs_snoc_sf_throttle_cfg, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_TSCSS] = &qhs_tscss, + [SLAVE_USB2] = &qhs_usb2, + [SLAVE_USB3] = &qhs_usb3, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, +}; + +static const struct regmap_config shikra_config_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x8080, + .fast_io = true, +}; + +static const struct qcom_icc_desc shikra_config_noc = { + .type = QCOM_ICC_QNOC, + .nodes = shikra_config_noc_nodes, + .num_nodes = ARRAY_SIZE(shikra_config_noc_nodes), + .bus_clk_desc = &bus_1_clk, + .keep_alive = true, +}; + +static struct qcom_icc_node * const shikra_mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI_CH0] = &ebi, +}; + +static const struct qcom_icc_desc shikra_mc_virt = { + .type = QCOM_ICC_QNOC, + .nodes = shikra_mc_virt_nodes, + .num_nodes = ARRAY_SIZE(shikra_mc_virt_nodes), + .bus_clk_desc = &bimc_clk, + .keep_alive = true, + .ab_coeff = 152, +}; + +static struct qcom_icc_node * const shikra_mem_noc_core_nodes[] = { + [MASTER_GRAPHICS_3D] = &qnm_gpu, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_ANOC_PCIE_MEM_NOC] = &qnm_pcie, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_AMPSS_M0] = &xm_apps, + [MASTER_SYS_TCU] = &xm_tcu, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEMNOC_SNOC] = &qns_memnoc_snoc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, +}; + +static const struct regmap_config shikra_mem_noc_core_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x43080, + .fast_io = true, +}; + +static const struct qcom_icc_desc shikra_mem_noc_core = { + .type = QCOM_ICC_QNOC, + .nodes = shikra_mem_noc_core_nodes, + .num_nodes = ARRAY_SIZE(shikra_mem_noc_core_nodes), + .bus_clk_desc = &mem_1_clk, + .regmap_cfg = &shikra_mem_noc_core_regmap_config, + .intf_clocks = memnoc_intf_clocks, + .num_intf_clocks = ARRAY_SIZE(memnoc_intf_clocks), + .qos_offset = 0x28000, + .keep_alive = true, + .ab_coeff = 142, +}; + +static struct qcom_icc_node * const shikra_mmnrt_virt_nodes[] = { + [MASTER_CAMNOC_SF] = &qnm_camera_nrt, + [MASTER_VIDEO_P0] = &qxm_venus0, + [MASTER_VIDEO_PROC] = &qxm_venus_cpu, + [SLAVE_MMNRT_VIRT] = &mmnrt_virt_slave, +}; + +static const struct regmap_config shikra_sys_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x6a080, + .fast_io = true, +}; + +static const struct qcom_icc_desc shikra_mmnrt_virt = { + .type = QCOM_ICC_QNOC, + .nodes = shikra_mmnrt_virt_nodes, + .num_nodes = ARRAY_SIZE(shikra_mmnrt_virt_nodes), + .bus_clk_desc = &mmaxi_0_clk, + .regmap_cfg = &shikra_sys_noc_regmap_config, + .qos_offset = 0x51000, + .keep_alive = true, + .ab_coeff = 142, +}; + +static struct qcom_icc_node * const shikra_mmrt_virt_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camera_rt, + [MASTER_MDP_PORT0] = &qxm_mdp0, + [MASTER_MMRT_VIRT] = &mmrt_virt_master, + [SLAVE_MM_MEMNOC] = &qns_mm_memnoc, +}; + +static const struct qcom_icc_desc shikra_mmrt_virt = { + .type = QCOM_ICC_QNOC, + .nodes = shikra_mmrt_virt_nodes, + .num_nodes = ARRAY_SIZE(shikra_mmrt_virt_nodes), + .bus_clk_desc = &mmaxi_1_clk, + .regmap_cfg = &shikra_sys_noc_regmap_config, + .qos_offset = 0x51000, + .keep_alive = true, + .ab_coeff = 142, +}; + +static struct qcom_icc_node * const shikra_sys_noc_nodes[] = { + [MASTER_SNOC_CFG] = &qhm_snoc_cfg, + [MASTER_TIC] = &qhm_tic, + [MASTER_ANOC_SNOC] = &qnm_anoc_snoc, + [MASTER_MEMNOC_PCIE] = &qnm_memnoc_pcie, + [MASTER_MEMNOC_SNOC] = &qnm_memnoc_snoc, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_PCIE2_0] = &xm_pcie2_0, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QPIC] = &qhm_qpic, + [MASTER_QUP_0] = &qhm_qup0, + [CNOC_SNOC_MAS] = &qnm_cnoc_snoc, + [MASTER_AUDIO] = &qxm_audio, + [MASTER_EMAC_0] = &xm_emac_0, + [MASTER_EMAC_1] = &xm_emac_1, + [MASTER_QDSS_ETR] = &xm_qdss_etr, + [MASTER_SDCC_1] = &xm_sdc1, + [MASTER_SDCC_2] = &xm_sdc2, + [MASTER_USB2_0] = &xm_usb2_0, + [MASTER_USB3] = &xm_usb3_0, + [MASTER_CRYPTO_CORE0] = &crypto_c0, + [SLAVE_APPSS] = &qhs_apss, + [SLAVE_MCUSS] = &qhs_mcuss, + [SLAVE_WCSS] = &qhs_wcss, + [SLAVE_MEMNOC_SF] = &qns_memnoc_sf, + [SNOC_CNOC_SLV] = &qns_snoc_cnoc, + [SLAVE_BOOTIMEM] = &qxs_bootimem, + [SLAVE_OCIMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, + [SLAVE_PCIE2_0] = &xs_pcie2_0, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, + [SLAVE_PCIE_MEMNOC] = &qns_pcie_memnoc, + [SLAVE_ANOC_SNOC] = &qns_anoc_snoc, +}; + +static const struct qcom_icc_desc shikra_sys_noc = { + .type = QCOM_ICC_QNOC, + .nodes = shikra_sys_noc_nodes, + .num_nodes = ARRAY_SIZE(shikra_sys_noc_nodes), + .bus_clk_desc = &bus_2_clk, + .regmap_cfg = &shikra_sys_noc_regmap_config, + .intf_clocks = sys_noc_intf_clocks, + .num_intf_clocks = ARRAY_SIZE(sys_noc_intf_clocks), + .qos_offset = 0x51000, + .keep_alive = true, +}; + +static const struct of_device_id shikra_qnoc_of_match[] = { + { .compatible = "qcom,shikra-clk-virt", + .data = &shikra_clk_virt }, + { .compatible = "qcom,shikra-config-noc", + .data = &shikra_config_noc }, + { .compatible = "qcom,shikra-mc-virt", + .data = &shikra_mc_virt }, + { .compatible = "qcom,shikra-mem-noc-core", + .data = &shikra_mem_noc_core }, + { .compatible = "qcom,shikra-mmnrt-virt", + .data = &shikra_mmnrt_virt }, + { .compatible = "qcom,shikra-mmrt-virt", + .data = &shikra_mmrt_virt }, + { .compatible = "qcom,shikra-sys-noc", + .data = &shikra_sys_noc }, + { }, +}; +MODULE_DEVICE_TABLE(of, shikra_qnoc_of_match); + +static struct platform_driver shikra_qnoc_driver = { + .probe = qnoc_probe, + .remove = qnoc_remove, + .driver = { + .name = "qnoc-shikra", + .of_match_table = shikra_qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&shikra_qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&shikra_qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm SHIKRA NoC driver"); +MODULE_LICENSE("GPL"); From 984f3b6ff8f87de2a6c6e542d343822ec4370d53 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 1 Apr 2026 11:52:10 +0530 Subject: [PATCH 0845/1330] arm64: defconfig: Enable interconnect driver for Shikra Enable the shikra interconnect driver so that consumers are able to obtain their path handles properly. Signed-off-by: Raviteja Laggyshetty (cherry picked from commit f41ab11c727905ea92754495561f81bf98418ecf) --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f43c30fecc318..e7bdde46a6d82 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1888,6 +1888,7 @@ CONFIG_INTERCONNECT_QCOM_SC8180X=y CONFIG_INTERCONNECT_QCOM_SC8280XP=y CONFIG_INTERCONNECT_QCOM_SDM845=y CONFIG_INTERCONNECT_QCOM_SDX75=y +CONFIG_INTERCONNECT_QCOM_SHIKRA=y CONFIG_INTERCONNECT_QCOM_SM6115=y CONFIG_INTERCONNECT_QCOM_SM6350=y CONFIG_INTERCONNECT_QCOM_MILOS=y From cc3367af6390467294218f38f84519900dd139be Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 7 Apr 2026 11:00:02 +0530 Subject: [PATCH 0846/1330] dt-bindings: mfd: qcom,tcsr: Add compatible for Shikra Document the qcom,shikra-tcsr compatible. Signed-off-by: Komal Bajaj (cherry picked from commit 65bc551344ba457e2da4b180c9f5258d9bae83d9) --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 14ae3f00ef7e0..51d0dcab57064 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -33,6 +33,7 @@ properties: - qcom,sdx55-tcsr - qcom,sdx65-tcsr - qcom,sdx75-tcsr + - qcom,shikra-tcsr - qcom,sm4450-tcsr - qcom,sm6115-tcsr - qcom,sm8150-tcsr From f3edac1dc6cfd234785d0241403b0bf895b0e56e Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Tue, 7 Apr 2026 23:00:01 +0530 Subject: [PATCH 0847/1330] dt-bindings: mmc: sdhci-msm: Add compatible for shikra Document the qcom,shikra-sdhci compatible Signed-off-by: Monish Chunara (cherry picked from commit 9976645c67ea70d3628d5b45c3c3482a20ced344) --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index cc9f7724bdf0e..1d4a04281f6d2 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -60,6 +60,7 @@ properties: - qcom,sdx55-sdhci - qcom,sdx65-sdhci - qcom,sdx75-sdhci + - qcom,shikra-sdhci - qcom,sm6115-sdhci - qcom,sm6125-sdhci - qcom,sm6350-sdhci From 63b089216fdaa3bea3c038d2258afe320dd9a167 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 10 Apr 2026 10:20:03 +0530 Subject: [PATCH 0848/1330] dt-bindings: cpufreq: qcom-hw: Document Shikra CPUFREQ Hardware The Qualcomm Shikra SoCs use RIMPS (RISC V based Integrated Manager for Power States) hardware for cpufreq scaling, which is functionally similar to EPSS, but supports only up to 12 frequency lookup table (LUT) entries. Signed-off-by: Imran Shaik (cherry picked from commit 54810373726d0c5386488ba0404a18d09d2f9dbc) --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 22eeaef14f557..2162110183de8 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -53,6 +53,12 @@ properties: - qcom,sm8650-cpufreq-epss - const: qcom,cpufreq-epss + - description: RIMPS CPUFREQ HW + items: + - enum: + - qcom,shikra-cpufreq-rimps + - const: qcom,cpufreq-rimps + reg: minItems: 1 items: @@ -143,6 +149,7 @@ allOf: - qcom,sc8280xp-cpufreq-epss - qcom,sdm670-cpufreq-hw - qcom,sdm845-cpufreq-hw + - qcom,shikra-cpufreq-rimps - qcom,sm4450-cpufreq-epss - qcom,sm6115-cpufreq-hw - qcom,sm6350-cpufreq-hw From 15ce4e0e1af2cf0e6d7c0a5a19864b27b4e87624 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 23 Feb 2024 15:52:25 +0530 Subject: [PATCH 0849/1330] cpufreq: qcom-cpufreq-hw: Add RIMPS based cpufreq support for Shikra SoC The Qualcomm Shikra SoCs uses the RIMPS based hardware for cpufreq scaling. Introduce rimps_soc_data, which reuses the existing EPSS configurations, and accounts for the maximum LUT entries to 12 as per RIMPS hardware. Signed-off-by: Taniya Das (cherry picked from commit a9eab59ec39a4f584ad8dcad96e312feb89c1fdc) --- drivers/cpufreq/qcom-cpufreq-hw.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index ea9a20d27b8fd..1fad60e3a627e 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -40,6 +41,7 @@ struct qcom_cpufreq_soc_data { u32 reg_intr_clr; u32 reg_current_vote; u32 reg_perf_state; + u32 lut_max_entries; u8 lut_row_size; }; @@ -156,7 +158,7 @@ static unsigned int qcom_cpufreq_get_freq(struct cpufreq_policy *policy) soc_data = qcom_cpufreq.soc_data; index = readl_relaxed(data->base + soc_data->reg_perf_state); - index = min(index, LUT_MAX_ENTRIES - 1); + index = min(index, soc_data->lut_max_entries - 1); return policy->freq_table[index].frequency; } @@ -211,7 +213,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, struct qcom_cpufreq_data *drv_data = policy->driver_data; const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; - table = kzalloc_objs(*table, LUT_MAX_ENTRIES + 1); + table = kzalloc_objs(*table, soc_data->lut_max_entries + 1); if (!table) return -ENOMEM; @@ -236,7 +238,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, icc_scaling_enabled = false; } - for (i = 0; i < LUT_MAX_ENTRIES; i++) { + for (i = 0; i < soc_data->lut_max_entries; i++) { data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + i * soc_data->lut_row_size); src = FIELD_GET(LUT_SRC, data); @@ -405,6 +407,7 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_current_vote = 0x704, .reg_perf_state = 0x920, .lut_row_size = 32, + .lut_max_entries = LUT_MAX_ENTRIES, }; static const struct qcom_cpufreq_soc_data epss_soc_data = { @@ -416,11 +419,25 @@ static const struct qcom_cpufreq_soc_data epss_soc_data = { .reg_intr_clr = 0x308, .reg_perf_state = 0x320, .lut_row_size = 4, + .lut_max_entries = LUT_MAX_ENTRIES, +}; + +static const struct qcom_cpufreq_soc_data rimps_soc_data = { + .reg_enable = 0x0, + .reg_domain_state = 0x20, + .reg_dcvs_ctrl = 0xb0, + .reg_freq_lut = 0x100, + .reg_volt_lut = 0x200, + .reg_intr_clr = 0x308, + .reg_perf_state = 0x320, + .lut_row_size = 4, + .lut_max_entries = 12, }; static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, + { .compatible = "qcom,cpufreq-rimps", .data = &rimps_soc_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); From 651eb845378d886fadb0d02887369a985ecc64f9 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 14 Apr 2026 17:31:31 +0530 Subject: [PATCH 0850/1330] arm64: defconfig: Enable Pinctrl on Shikra EVK boards Enable the pinctrl driver on the Qualcomm Shikra EVK boards. Signed-off-by: Komal Bajaj (cherry picked from commit 0b65824c15db43795a4e34647549f36af97560cf) --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e7bdde46a6d82..297b7456c5040 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -677,6 +677,7 @@ CONFIG_PINCTRL_SDM660=y CONFIG_PINCTRL_SDM670=y CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SDX75=y +CONFIG_PINCTRL_SHIKRA=y CONFIG_PINCTRL_SM4450=y CONFIG_PINCTRL_SM6115=y CONFIG_PINCTRL_SM6125=y From e09d4762b60f4d33bcd16fe47507cc037020718e Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Thu, 9 Apr 2026 23:37:40 +0530 Subject: [PATCH 0851/1330] dt-bindings: thermal: qcom-tsens: Document the Shikra Temperature Sensor Document the Temperature Sensor (TSENS) on the Shikra SoC. Signed-off-by: Gaurav Kohli (cherry picked from commit d8ececd04d1c05d9147cd90c1816412b741ff97b) --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 57f1cbb4c188e..abaa1e639ac0f 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -72,6 +72,7 @@ properties: - qcom,sc8280xp-tsens - qcom,sdm630-tsens - qcom,sdm845-tsens + - qcom,shikra-tsens - qcom,sm6115-tsens - qcom,sm6350-tsens - qcom,sm6375-tsens From 9c7d7ea9b185811e4ad347677d417db17407177d Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Mon, 11 May 2026 10:47:11 +0530 Subject: [PATCH 0852/1330] WORKAROUND:arm64: dts: glymur: Q6APM SID fixed Q6APM SID fixed Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 549515ae0ab880a1e0eb17b1d082de62cee5c341) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index d6584231dd497..361ddfec97481 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4460,7 +4460,7 @@ q6apmdai: dais { compatible = "qcom,q6apm-dais"; - iommus = <&apps_smmu 0x1004 0x80>, + iommus = <&apps_smmu 0x1001 0x80>, <&apps_smmu 0x1061 0x20>; }; }; From a0a70cb2690aa4fd11a6d15a9929d4cf8247cfca Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 7 May 2026 11:52:30 +0530 Subject: [PATCH 0853/1330] FROMLIST: firmware: arm_scmi: Add QCOM Generic Vendor Protocol documentation Add QCOM System Control Management Interface (SCMI) Generic Vendor Extensions Protocol documentation. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/lkml/20260507062237.78051-2-sibi.sankar@oss.qualcomm.com/ (cherry picked from commit a79ab85eca9b9674e34fa3350fb9e35f5e5e247d) --- .../arm_scmi/vendors/qcom/qcom_generic.rst | 211 ++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst b/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst new file mode 100644 index 0000000000000..141bc932e30ff --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst @@ -0,0 +1,211 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +=============================================================================== +QCOM System Control and Management Interface(SCMI) Vendor Protocols Extension +=============================================================================== + +:Copyright: |copy| 2024, Qualcomm Innovation Center, Inc. All rights reserved. + +:Author: Sibi Sankar + +SCMI_GENERIC: System Control and Management Interface QCOM Generic Vendor Protocol +================================================================================== + +This protocol is intended as a generic way of exposing a number of Qualcomm +SoC specific features through a mixture of pre-determined algorithm string and +param_id pairs hosted on the SCMI controller. It implements an interface compliant +with the Arm SCMI Specification with additional vendor specific commands as +detailed below. + +Commands: +_________ + +PROTOCOL_VERSION +~~~~~~~~~~~~~~~~ + +message_id: 0x0 +protocol_id: 0x80 + ++---------------+--------------------------------------------------------------+ +|Return values | ++---------------+--------------------------------------------------------------+ +|Name |Description | ++---------------+--------------------------------------------------------------+ +|int32 status |See ARM SCMI Specification for status code definitions. | ++---------------+--------------------------------------------------------------+ +|uint32 version |For this revision of the specification, this value must be | +| |0x10000. | ++---------------+--------------------------------------------------------------+ + +PROTOCOL_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x1 +protocol_id: 0x80 + ++---------------+--------------------------------------------------------------+ +|Return values | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|int32 status |See ARM SCMI Specification for status code definitions. | ++------------------+-----------------------------------------------------------+ +|uint32 attributes |Bits[31:16] Reserved, must be to 0. | +| |Bits[15:8] Number of agents in the system | +| |Bits[7:0] Number of vendor protocols in the system | ++------------------+-----------------------------------------------------------+ + +PROTOCOL_MESSAGE_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x2 +protocol_id: 0x80 + ++---------------+--------------------------------------------------------------+ +|Return values | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|int32 status |See ARM SCMI Specification for status code definitions. | ++------------------+-----------------------------------------------------------+ +|uint32 attributes |For all message id's the parameter has a value of 0. | ++------------------+-----------------------------------------------------------+ + +QCOM_SCMI_SET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x10 +protocol_id: 0x80 + ++------------------+-----------------------------------------------------------+ +|Parameters | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|uint32 ext_id |Reserved, must be zero. | ++------------------+-----------------------------------------------------------+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 param_id |Serves as the token message id for the algorithm string | +| |and is used to set various parameters supported by it. | ++------------------+-----------------------------------------------------------+ +|uint32 buf[] |Serves as the payload for the specified param_id and | +| |algorithm string pair. | ++------------------+-----------------------------------------------------------+ +|Return values | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfully | +| |by the chosen algorithm string. | +| |NOT_SUPPORTED: if the algorithm string does not have any | +| |matches. | +| |INVALID_PARAMETERS: if the param_id and the buf[] passed | +| |is rejected by the algorithm string. | ++------------------+-----------------------------------------------------------+ + +QCOM_SCMI_GET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x11 +protocol_id: 0x80 + ++------------------+-----------------------------------------------------------+ +|Parameters | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|uint32 ext_id |Reserved, must be zero. | ++------------------+-----------------------------------------------------------+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 param_id |Serves as the token message id for the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 buf[] |Serves as the payload and store of value for the specified | +| |param_id and algorithm string pair. | ++------------------+-----------------------------------------------------------+ +|Return values | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfully | +| |by the chosen algorithm string and the result is copied | +| |into buf[]. | +| |NOT_SUPPORTED: if the algorithm string does not have any | +| |matches. | +| |INVALID_PARAMETERS: if the param_id and the buf[] passed | +| |is rejected by the algorithm string. | ++------------------+-----------------------------------------------------------+ + +QCOM_SCMI_START_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x12 +protocol_id: 0x80 + ++------------------+-----------------------------------------------------------+ +|Parameters | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|uint32 ext_id |Reserved, must be zero. | ++------------------+-----------------------------------------------------------+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 param_id |Serves as the token message id for the algorithm string | +| |and is generally used to start the activity performed by | +| |the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 buf[] |Serves as the payload for the specified param_id and | +| |algorithm string pair. | ++------------------+-----------------------------------------------------------+ +|Return values | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|int32 status |SUCCESS: if the activity performed by the algorithm string | +| |starts successfully. | +| |NOT_SUPPORTED: if the algorithm string does not have any. | +| |matches or if the activity is already running. | ++------------------+-----------------------------------------------------------+ + +QCOM_SCMI_STOP_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x13 +protocol_id: 0x80 + ++------------------+-----------------------------------------------------------+ +|Parameters | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|uint32 ext_id |Reserved, must be zero. | ++------------------+-----------------------------------------------------------+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 param_id |Serves as the token message id for the algorithm string | +| |and is generally used to stop the activity performed by | +| |the algorithm string. | ++------------------+-----------------------------------------------------------+ +|uint32 buf[] |Serves as the payload for the specified param_id and | +| |algorithm string pair. | ++------------------+-----------------------------------------------------------+ +|Return values | ++------------------+-----------------------------------------------------------+ +|Name |Description | ++------------------+-----------------------------------------------------------+ +|int32 status |SUCCESS: if the activity performed by the algorithm string | +| |stops successfully. | +| |NOT_SUPPORTED: if the algorithm string does not have any | +| |matches or if the activity isn't running. | ++------------------+-----------------------------------------------------------+ From 1410ab40510b87e2e6f2ad7d40708e187cbdb350 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 7 May 2026 11:52:31 +0530 Subject: [PATCH 0854/1330] FROMLIST: firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions The QCOM SCMI Generic Extensions Protocol provides a generic way of exposing a number of Qualcomm SoC specific features (like memory bus scaling) through a mixture of pre-determined algorithm strings and param_id pairs hosted on the SCMI controller. Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/lkml/20260507062237.78051-3-sibi.sankar@oss.qualcomm.com/ (cherry picked from commit 22d8168f823e4db2d37abf0e4c2fd32cdff74c68) --- drivers/firmware/arm_scmi/Kconfig | 1 + drivers/firmware/arm_scmi/Makefile | 1 + .../firmware/arm_scmi/vendors/qcom/Kconfig | 15 ++ .../firmware/arm_scmi/vendors/qcom/Makefile | 2 + .../arm_scmi/vendors/qcom/qcom-generic-ext.c | 135 ++++++++++++++++++ include/linux/scmi_qcom_protocol.h | 37 +++++ 6 files changed, 191 insertions(+) create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/Kconfig create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/Makefile create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c create mode 100644 include/linux/scmi_qcom_protocol.h diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/Kconfig index e3fb36825978e..a52f4d1b8b2c8 100644 --- a/drivers/firmware/arm_scmi/Kconfig +++ b/drivers/firmware/arm_scmi/Kconfig @@ -84,6 +84,7 @@ config ARM_SCMI_QUIRKS source "drivers/firmware/arm_scmi/transports/Kconfig" source "drivers/firmware/arm_scmi/vendors/imx/Kconfig" +source "drivers/firmware/arm_scmi/vendors/qcom/Kconfig" endif #ARM_SCMI_PROTOCOL diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index 780cd62b2f78a..5a0e003c2477a 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -13,6 +13,7 @@ scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y) $(scmi-transport-y) obj-$(CONFIG_ARM_SCMI_PROTOCOL) += transports/ obj-$(CONFIG_ARM_SCMI_PROTOCOL) += vendors/imx/ +obj-$(CONFIG_ARM_SCMI_PROTOCOL) += vendors/qcom/ obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-core.o obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-module.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Kconfig b/drivers/firmware/arm_scmi/vendors/qcom/Kconfig new file mode 100644 index 0000000000000..5dd9e8a6b75f0 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "ARM SCMI QCOM Vendor Protocols" + +config QCOM_SCMI_GENERIC_EXT + tristate "Qualcomm Technologies, Inc. Qcom SCMI vendor Protocol" + depends on ARM_SCMI_PROTOCOL || COMPILE_TEST + help + The QCOM SCMI vendor protocol provides a generic way of exposing + a number of Qualcomm SoC specific features (like memory bus scaling) + through a mixture of pre-determined algorithm strings and param_id + pairs hosted on the SCMI controller. + + This driver defines/documents the message ID's used for this + communication and also exposes the operations used by the clients. +endmenu diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Makefile b/drivers/firmware/arm_scmi/vendors/qcom/Makefile new file mode 100644 index 0000000000000..6b98fabbebb86 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_QCOM_SCMI_GENERIC_EXT) += qcom-generic-ext.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c b/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c new file mode 100644 index 0000000000000..4f9eba8ff4bd4 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +#include "../../common.h" + +/** + * enum qcom_generic_ext_protocol_cmd - vendor specific commands supported by SCMI Qualcomm + * generic vendor protocol. + * + * This protocol is intended as a generic way of exposing a number of Qualcomm SoC + * specific features through a mixture of pre-determined algorithm string and param_id + * pairs hosted on the SCMI controller. + * + * The QCOM SCMI Vendor Protocol has the protocol id as 0x80 and vendor id set to + * Qualcomm and the supported version is set to 0x10000. The PROTOCOL_VERSION command + * returns version 1.0. + * + * @QCOM_SCMI_SET_PARAM: is used to set the parameter of a specific algo_str hosted on + * QCOM SCMI Vendor Protocol. The tx len depends on the algo_str used. + * @QCOM_SCMI_GET_PARAM: is used to get parameter information of a specific algo_str + * hosted on QCOM SCMI Vendor Protocol. The tx and rx len depends + * on the algo_str used. + * @QCOM_SCMI_START_ACTIVITY: is used to start the activity performed by the algo_str. + * @QCOM_SCMI_STOP_ACTIVITY: is used to stop a pre-existing activity performed by the algo_str. + */ +enum qcom_generic_ext_protocol_cmd { + QCOM_SCMI_SET_PARAM = 0x10, + QCOM_SCMI_GET_PARAM = 0x11, + QCOM_SCMI_START_ACTIVITY = 0x12, + QCOM_SCMI_STOP_ACTIVITY = 0x13, +}; + +/** + * struct qcom_scmi_msg - represents the various parameters to be populated + * for using the QCOM SCMI Vendor Protocol + * + * @ext_id: reserved, must be zero + * @algo_low: lower 32 bits of the algo_str + * @algo_high: upper 32 bits of the algo_str + * @param_id: serves as token message id to the specific algo_str + * @buf: serves as the payload to the specified param_id and algo_str pair + */ +struct qcom_scmi_msg { + __le32 ext_id; + __le32 algo_low; + __le32 algo_high; + __le32 param_id; + __le32 buf[]; +}; + +static int qcom_scmi_common_xfer(const struct scmi_protocol_handle *ph, + enum qcom_generic_ext_protocol_cmd cmd_id, void *buf, + size_t buf_len, u64 algo_str, u32 param_id, size_t rx_size) +{ + struct scmi_xfer *t; + struct qcom_scmi_msg *msg; + int ret; + + ret = ph->xops->xfer_get_init(ph, cmd_id, buf_len + sizeof(*msg), rx_size, &t); + if (ret) + return ret; + + msg = t->tx.buf; + msg->algo_low = cpu_to_le32(lower_32_bits(algo_str)); + msg->algo_high = cpu_to_le32(upper_32_bits(algo_str)); + msg->param_id = cpu_to_le32(param_id); + memcpy(msg->buf, buf, buf_len); + + ret = ph->xops->do_xfer(ph, t); + if (!ret && rx_size) + memcpy(buf, t->rx.buf, t->rx.len); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int qcom_scmi_set_param(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len, + u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_SET_PARAM, buf, buf_len, algo_str, + param_id, 0); +} + +static int qcom_scmi_get_param(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len, + u64 algo_str, u32 param_id, size_t rx_size) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_GET_PARAM, buf, buf_len, algo_str, + param_id, rx_size); +} + +static int qcom_scmi_start_activity(const struct scmi_protocol_handle *ph, void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_START_ACTIVITY, buf, buf_len, algo_str, + param_id, 0); +} + +static int qcom_scmi_stop_activity(const struct scmi_protocol_handle *ph, void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_STOP_ACTIVITY, buf, buf_len, algo_str, + param_id, 0); +} + +static struct qcom_generic_ext_ops qcom_proto_ops = { + .set_param = qcom_scmi_set_param, + .get_param = qcom_scmi_get_param, + .start_activity = qcom_scmi_start_activity, + .stop_activity = qcom_scmi_stop_activity, +}; + +static int qcom_generic_ext_protocol_init(const struct scmi_protocol_handle *ph) +{ + dev_dbg(ph->dev, "QCOM Generic Vendor Version %d.%d\n", + PROTOCOL_REV_MAJOR(ph->version), PROTOCOL_REV_MINOR(ph->version)); + + return 0; +} + +static const struct scmi_protocol qcom_generic_ext = { + .id = SCMI_PROTOCOL_QCOM_GENERIC, + .owner = THIS_MODULE, + .instance_init = &qcom_generic_ext_protocol_init, + .ops = &qcom_proto_ops, + .vendor_id = "Qualcomm", + .supported_version = 0x10000, +}; +module_scmi_protocol(qcom_generic_ext); + +MODULE_DESCRIPTION("QCOM SCMI Generic Vendor protocol"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/scmi_qcom_protocol.h b/include/linux/scmi_qcom_protocol.h new file mode 100644 index 0000000000000..465b2522ca29d --- /dev/null +++ b/include/linux/scmi_qcom_protocol.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SCMI Message Protocol driver QCOM extension header + * + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _LINUX_SCMI_QCOM_PROTOCOL_H +#define _LINUX_SCMI_QCOM_PROTOCOL_H + +#include + +#define SCMI_PROTOCOL_QCOM_GENERIC 0x80 + +struct scmi_protocol_handle; + +/** + * struct qcom_generic_ext_ops - represents the various operations provided + * by QCOM Generic Vendor Protocol + * + * @set_param: set parameter specified by param_id and algo_str pair. + * @get_param: retrieve parameter specified by param_id and algo_str pair. + * @start_activity: initiate a specific activity defined by algo_str. + * @stop_activity: halt previously initiated activity defined by algo_str. + */ +struct qcom_generic_ext_ops { + int (*set_param)(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len, + u64 algo_str, u32 param_id); + int (*get_param)(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len, + u64 algo_str, u32 param_id, size_t rx_size); + int (*start_activity)(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len, + u64 algo_str, u32 param_id); + int (*stop_activity)(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len, + u64 algo_str, u32 param_id); +}; + +#endif /* _LINUX_SCMI_QCOM_PROTOCOL_H */ From f92dd82022c06a18319cae3a84ec5436c8bfb6ac Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 7 May 2026 11:52:32 +0530 Subject: [PATCH 0855/1330] FROMLIST: PM / devfreq: Add new target_freq attribute flag for governors Introduce the target_freq attribute flag as a pre-cursor to adding support for devfreq governors who do not explicitly allow for a method to get/set target frequency. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/lkml/20260507062237.78051-4-sibi.sankar@oss.qualcomm.com/ (cherry picked from commit d20cabd2e12e6671a4a55c9b338014e643011a3b) --- drivers/devfreq/devfreq.c | 4 ++++ drivers/devfreq/governor_passive.c | 1 + drivers/devfreq/governor_performance.c | 1 + drivers/devfreq/governor_powersave.c | 1 + drivers/devfreq/governor_simpleondemand.c | 1 + drivers/devfreq/governor_userspace.c | 1 + drivers/devfreq/hisi_uncore_freq.c | 1 + drivers/devfreq/tegra30-devfreq.c | 3 ++- include/linux/devfreq-governor.h | 3 +++ 9 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index c0a74091b9041..a7814b316240d 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -1568,6 +1568,10 @@ static ssize_t target_freq_show(struct device *dev, { struct devfreq *df = to_devfreq(dev); + if (!df->profile || !df->governor || + !IS_SUPPORTED_ATTR(df->governor->attrs, TARGET_FREQ)) + return -EINVAL; + return sprintf(buf, "%lu\n", df->previous_freq); } static DEVICE_ATTR_RO(target_freq); diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c index d7feecd900f1d..b75e4bbee4b13 100644 --- a/drivers/devfreq/governor_passive.c +++ b/drivers/devfreq/governor_passive.c @@ -448,6 +448,7 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq, static struct devfreq_governor devfreq_passive = { .name = DEVFREQ_GOV_PASSIVE, + .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags = DEVFREQ_GOV_FLAG_IMMUTABLE, .get_target_freq = devfreq_passive_get_target_freq, .event_handler = devfreq_passive_event_handler, diff --git a/drivers/devfreq/governor_performance.c b/drivers/devfreq/governor_performance.c index fdb22bf512cf1..b9ec587f582cc 100644 --- a/drivers/devfreq/governor_performance.c +++ b/drivers/devfreq/governor_performance.c @@ -37,6 +37,7 @@ static int devfreq_performance_handler(struct devfreq *devfreq, static struct devfreq_governor devfreq_performance = { .name = DEVFREQ_GOV_PERFORMANCE, + .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq = devfreq_performance_func, .event_handler = devfreq_performance_handler, }; diff --git a/drivers/devfreq/governor_powersave.c b/drivers/devfreq/governor_powersave.c index ee2d6ec8a5122..69eab1d0a7fcc 100644 --- a/drivers/devfreq/governor_powersave.c +++ b/drivers/devfreq/governor_powersave.c @@ -37,6 +37,7 @@ static int devfreq_powersave_handler(struct devfreq *devfreq, static struct devfreq_governor devfreq_powersave = { .name = DEVFREQ_GOV_POWERSAVE, + .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq = devfreq_powersave_func, .event_handler = devfreq_powersave_handler, }; diff --git a/drivers/devfreq/governor_simpleondemand.c b/drivers/devfreq/governor_simpleondemand.c index ac9c5e9e51a49..65ff9d912ef9c 100644 --- a/drivers/devfreq/governor_simpleondemand.c +++ b/drivers/devfreq/governor_simpleondemand.c @@ -118,6 +118,7 @@ static int devfreq_simple_ondemand_handler(struct devfreq *devfreq, static struct devfreq_governor devfreq_simple_ondemand = { .name = DEVFREQ_GOV_SIMPLE_ONDEMAND, .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TARGET_FREQ | DEVFREQ_GOV_ATTR_TIMER, .get_target_freq = devfreq_simple_ondemand_func, .event_handler = devfreq_simple_ondemand_handler, diff --git a/drivers/devfreq/governor_userspace.c b/drivers/devfreq/governor_userspace.c index 3906ebedbae84..d1b765a7b8e56 100644 --- a/drivers/devfreq/governor_userspace.c +++ b/drivers/devfreq/governor_userspace.c @@ -135,6 +135,7 @@ static int devfreq_userspace_handler(struct devfreq *devfreq, static struct devfreq_governor devfreq_userspace = { .name = DEVFREQ_GOV_USERSPACE, + .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq = devfreq_userspace_func, .event_handler = devfreq_userspace_handler, }; diff --git a/drivers/devfreq/hisi_uncore_freq.c b/drivers/devfreq/hisi_uncore_freq.c index 4d00d813c8ac6..0800116e33343 100644 --- a/drivers/devfreq/hisi_uncore_freq.c +++ b/drivers/devfreq/hisi_uncore_freq.c @@ -399,6 +399,7 @@ static struct devfreq_governor hisi_platform_governor = { * Set interrupt_driven to skip the devfreq monitor mechanism, though * this governor is not interrupt-driven. */ + .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags = DEVFREQ_GOV_FLAG_IRQ_DRIVEN, .get_target_freq = hisi_platform_gov_func, .event_handler = hisi_platform_gov_handler, diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c index 8b57194ac6984..12709a9f59085 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -776,7 +776,8 @@ static int tegra_governor_event_handler(struct devfreq *devfreq, static struct devfreq_governor tegra_devfreq_governor = { .name = "tegra_actmon", - .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL, + .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags = DEVFREQ_GOV_FLAG_IMMUTABLE | DEVFREQ_GOV_FLAG_IRQ_DRIVEN, .get_target_freq = tegra_governor_get_target, diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-governor.h index dfdd0160a29f3..2853f571dfdf7 100644 --- a/include/linux/devfreq-governor.h +++ b/include/linux/devfreq-governor.h @@ -43,9 +43,12 @@ * : Indicate polling_interval sysfs attribute * - DEVFREQ_GOV_ATTR_TIMER * : Indicate timer sysfs attribute + * - DEVFREQ_GOV_ATTR_TARGET_FREQ + * : Indicate the target freq sysfs attribute */ #define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0) #define DEVFREQ_GOV_ATTR_TIMER BIT(1) +#define DEVFREQ_GOV_ATTR_TARGET_FREQ BIT(2) /** * struct devfreq_governor - Devfreq policy governor From 0d1eac9333f192985a3a019700e9fd2922175a30 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 7 May 2026 11:52:33 +0530 Subject: [PATCH 0856/1330] FROMLIST: PM / devfreq: Add new track_remote flag for governors Add a new track_remote flag for devfreq governors as a pre-curor to adding the devfreq governors that is responsible for tracking frequency changes on remote devices. This new governor flag provides for a way track the remote device's frequency and keep the trans_stat data updated and skip the frequency update sequency for the device. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/lkml/20260507062237.78051-5-sibi.sankar@oss.qualcomm.com/ (cherry picked from commit c9e516957736a5bc873832ba85d3cbdc681f1903) --- drivers/devfreq/devfreq.c | 5 +++++ include/linux/devfreq-governor.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index a7814b316240d..18f3392594578 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -348,6 +348,10 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq, unsigned long cur_freq; int err = 0; + /* Frequency already updated, update trans-stat info */ + if (IS_SUPPORTED_FLAG(devfreq->governor->flags, TRACK_REMOTE)) + goto update_status; + if (devfreq->profile->get_cur_freq) devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq); else @@ -375,6 +379,7 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq, freqs.new = new_freq; devfreq_notify_transition(devfreq, &freqs, DEVFREQ_POSTCHANGE); +update_status: if (devfreq_update_status(devfreq, new_freq)) dev_warn(&devfreq->dev, "Couldn't update frequency transition information.\n"); diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-governor.h index 2853f571dfdf7..83aa82c4a9b65 100644 --- a/include/linux/devfreq-governor.h +++ b/include/linux/devfreq-governor.h @@ -36,6 +36,7 @@ */ #define DEVFREQ_GOV_FLAG_IMMUTABLE BIT(0) #define DEVFREQ_GOV_FLAG_IRQ_DRIVEN BIT(1) +#define DEVFREQ_GOV_FLAG_TRACK_REMOTE BIT(2) /* * Definition of governor attribute flags except for common sysfs attributes From 8c0e79e361a5af9de23fcf9ef71f26a84a3c5732 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 7 May 2026 11:52:34 +0530 Subject: [PATCH 0857/1330] FROMLIST: PM / devfreq: Add a governor for tracking remote device frequencies On SoCs, where the governor and the mechanism to control the frequency for devices like caches is hosted on the System Control Processor (SCP), there exists a need track the frequency changes in a reliable way and provide ways to tweaking parameters on the remote governor. To address this introduce the new remote devfreq governor that provides for a way to track the frequency changes on remote devices. It uses the newly introduced target_freq attribute flag and track_remote flag to achieve this. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/lkml/20260507062237.78051-6-sibi.sankar@oss.qualcomm.com/ (cherry picked from commit fea394756fa189f12d56cd583bdb2fed3f4f22bd) --- drivers/devfreq/Kconfig | 8 ++++ drivers/devfreq/Makefile | 1 + drivers/devfreq/governor_remote.c | 80 +++++++++++++++++++++++++++++++ include/linux/devfreq.h | 1 + 4 files changed, 90 insertions(+) create mode 100644 drivers/devfreq/governor_remote.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index c999c4a1e5675..2caa875549141 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -56,6 +56,14 @@ config DEVFREQ_GOV_POWERSAVE the DEVFREQ framework returns the lowest frequency available at any time. +config DEVFREQ_GOV_REMOTE + tristate "Remote" + help + A simple governor to track the frequency of devices whose + dvfs control lies outside the kernel. This governor acts + as an observer and provides for ways to track frequency and + set/get information related to the remote dvfs device. + config DEVFREQ_GOV_USERSPACE tristate "Userspace" help diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 404179d79a9db..cde57c8cda764 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PM_DEVFREQ_EVENT) += devfreq-event.o obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) += governor_simpleondemand.o obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o +obj-$(CONFIG_DEVFREQ_GOV_REMOTE) += governor_remote.o obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o diff --git a/drivers/devfreq/governor_remote.c b/drivers/devfreq/governor_remote.c new file mode 100644 index 0000000000000..6bff3cdaf1e50 --- /dev/null +++ b/drivers/devfreq/governor_remote.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +static int devfreq_remote_track_func(struct devfreq *devfreq, unsigned long *freq) +{ + unsigned long cur_freq = 0; + + if (devfreq->profile->get_cur_freq) + devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq); + + *freq = cur_freq; + + return 0; +} + +static int devfreq_remote_track_handler(struct devfreq *devfreq, unsigned int event, void *data) +{ + switch (event) { + case DEVFREQ_GOV_START: + devfreq_monitor_start(devfreq); + break; + + case DEVFREQ_GOV_STOP: + devfreq_monitor_stop(devfreq); + break; + + case DEVFREQ_GOV_UPDATE_INTERVAL: + devfreq_update_interval(devfreq, (unsigned int *)data); + break; + + case DEVFREQ_GOV_SUSPEND: + devfreq_monitor_suspend(devfreq); + break; + + case DEVFREQ_GOV_RESUME: + devfreq_monitor_resume(devfreq); + break; + + default: + break; + } + + return 0; +} + +static struct devfreq_governor devfreq_remote_track = { + .name = DEVFREQ_GOV_REMOTE, + .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TIMER, + .flags = DEVFREQ_GOV_FLAG_IMMUTABLE + | DEVFREQ_GOV_FLAG_TRACK_REMOTE, + .get_target_freq = devfreq_remote_track_func, + .event_handler = devfreq_remote_track_handler, +}; + +static int __init devfreq_remote_track_init(void) +{ + return devfreq_add_governor(&devfreq_remote_track); +} +subsys_initcall(devfreq_remote_track_init); + +static void __exit devfreq_remote_track_exit(void) +{ + int ret; + + ret = devfreq_remove_governor(&devfreq_remote_track); + if (ret) + pr_err("%s: failed remove governor %d\n", __func__, ret); +} +module_exit(devfreq_remote_track_exit); + +MODULE_DESCRIPTION("DEVFREQ Remote Tracking governor"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h index dc1075dc34460..4d50cf2309504 100644 --- a/include/linux/devfreq.h +++ b/include/linux/devfreq.h @@ -21,6 +21,7 @@ #define DEVFREQ_GOV_POWERSAVE "powersave" #define DEVFREQ_GOV_USERSPACE "userspace" #define DEVFREQ_GOV_PASSIVE "passive" +#define DEVFREQ_GOV_REMOTE "remote" /* DEVFREQ notifier interface */ #define DEVFREQ_TRANSITION_NOTIFIER (0) From ce0c52651a3c880eb8232664b1bca4c0a44abe23 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 7 May 2026 11:52:35 +0530 Subject: [PATCH 0858/1330] FROMLIST: PM / devfreq: Introduce the QCOM SCMI Memlat devfreq device On Qualcomm Glymur and Hamoa SoCs, the memlat governor and the mechanism to control the various caches and ram is hosted on the CPU Control Processor (CPUCP) and the method to tweak and start the governor is exposed through the QCOM SCMI Generic Extension Protocol. Introduce the devfreq scmi client driver that uses the memlat algorithm string hosted on QCOM SCMI Generic Extension Protocol to detect memory latency workloads and control frequency/level of the various memory buses (DDR/LLCC/DDR_QOS). The DDR/LLCC/DDR_QOS are modelled as devfreq devices, with the governor set to remote devfreq governor. This serves as a way to get a basic insight into the device operation through trans_stat and provides for ways to further tweak the parameters of the remote governor. Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/lkml/20260507062237.78051-7-sibi.sankar@oss.qualcomm.com/ (cherry picked from commit 6ebf719c35b8661be830d69b2ea595473cced6d0) --- drivers/devfreq/Kconfig | 13 + drivers/devfreq/Makefile | 1 + drivers/devfreq/scmi-qcom-memlat-cfg.h | 473 +++++++++++++++++ drivers/devfreq/scmi-qcom-memlat-devfreq.c | 582 +++++++++++++++++++++ 4 files changed, 1069 insertions(+) create mode 100644 drivers/devfreq/scmi-qcom-memlat-cfg.h create mode 100644 drivers/devfreq/scmi-qcom-memlat-devfreq.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 2caa875549141..98b5a50d31896 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -169,6 +169,19 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ This adds the DEVFREQ driver for the MBUS controller in some Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs. +config SCMI_QCOM_MEMLAT_DEVFREQ + tristate "Qualcomm Technologies Inc. SCMI client driver" + depends on QCOM_SCMI_GENERIC_EXT || COMPILE_TEST + select DEVFREQ_GOV_REMOTE + help + This driver uses the MEMLAT (memory latency) algorithm string + hosted on QCOM SCMI Vendor Protocol to detect memory latency + workloads and control frequency/level of the various memory + buses (DDR/LLCC/DDR_QOS). + + This driver defines/documents the parameter IDs used while configuring + the memory buses. + source "drivers/devfreq/event/Kconfig" endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index cde57c8cda764..b11f94e2f4855 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o +obj-$(CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ) += scmi-qcom-memlat-devfreq.o # DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff --git a/drivers/devfreq/scmi-qcom-memlat-cfg.h b/drivers/devfreq/scmi-qcom-memlat-cfg.h new file mode 100644 index 0000000000000..e56899489db45 --- /dev/null +++ b/drivers/devfreq/scmi-qcom-memlat-cfg.h @@ -0,0 +1,473 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_DEVFREQ_SCMI_QCOM_MEMLAT_CONFIG_H__ +#define __DRIVERS_DEVFREQ_SCMI_QCOM_MEMLAT_CONFIG_H__ + +/* + * Memlat Effective Frequency Calculation Method + * CPUCP_EFFECTIVE_FREQ_METHOD_0 - Uses CPU Cycles and CONST Cycles to calculate + * CPUCP_EFFECTIVE_FREQ_METHOD_1 - Uses CPU Cycles and time period + */ +#define CPUCP_EFFECTIVE_FREQ_CALC_METHOD_0 0 +#define CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1 1 + +#define EV_CPU_CYCLES 0 +#define EV_CNT_CYCLES 1 +#define EV_INST_RETIRED 2 +#define EV_STALL_BACKEND_MEM 3 +#define EV_L2_D_RFILL 5 +#define INVALID_IDX 0xff + +#define MEMLAT_ALGO_STR 0x4D454D4C4154 /* MEMLAT */ + +struct scmi_qcom_map_table { + unsigned int cpu_freq; + unsigned int mem_freq; +}; + +struct scmi_qcom_opp_data { + unsigned long freq; + unsigned int level; +}; + +struct scmi_qcom_memory_range { + unsigned int min_freq; + unsigned int max_freq; +}; + +struct scmi_qcom_monitor_cfg { + const struct scmi_qcom_map_table *table; + const char *name; + u32 be_stall_floor; + u32 cpu_mask; + u32 ipm_ceil; + int table_len; +}; + +struct scmi_qcom_memory_cfg { + const struct scmi_qcom_monitor_cfg *monitor_cfg; + const struct scmi_qcom_opp_data *mem_table; + struct scmi_qcom_memory_range memory_range; + const char *name; + u32 memory_type; + int monitor_cnt; + int num_opps; +}; + +struct scmi_qcom_memlat_cfg_data { + const struct scmi_qcom_memory_cfg *memory_cfg; + u32 cpucp_freq_method; + u32 cpucp_sample_ms; + int memory_cnt; +}; + +static const struct scmi_qcom_opp_data glymur_llcc_table[] = { + { .freq = 315000000 }, + { .freq = 479000000 }, + { .freq = 545000000 }, + { .freq = 725000000 }, + { .freq = 840000000 }, + { .freq = 959000000 }, + { .freq = 1090000000 }, + { .freq = 1211000000 }, +}; + +static const struct scmi_qcom_opp_data hamoa_llcc_table[] = { + { .freq = 300000000 }, + { .freq = 466000000 }, + { .freq = 600000000 }, + { .freq = 806000000 }, + { .freq = 933000000 }, + { .freq = 1066000000 }, +}; + +static const struct scmi_qcom_opp_data glymur_ddr_table[] = { + { .freq = 200000000 }, + { .freq = 547000000 }, + { .freq = 1353000000 }, + { .freq = 1555000000 }, + { .freq = 1708000000 }, + { .freq = 2092000000 }, + { .freq = 2736000000 }, + { .freq = 3187000000 }, + { .freq = 3686000000 }, + { .freq = 4224000000 }, + { .freq = 4761000000 }, +}; + +static const struct scmi_qcom_opp_data hamoa_ddr_table[] = { + { .freq = 200000000 }, + { .freq = 547000000 }, + { .freq = 768000000 }, + { .freq = 1555000000 }, + { .freq = 1708000000 }, + { .freq = 2092000000 }, + { .freq = 2736000000 }, + { .freq = 3187000000 }, + { .freq = 3686000000 }, + { .freq = 4224000000 }, +}; + +static const struct scmi_qcom_opp_data glymur_ddr_qos_table[] = { + { .freq = 1, .level = 0 }, + { .freq = 100, .level = 1 }, +}; + +static const struct scmi_qcom_memory_cfg glymur_memory_cfg[] = { + { + .memory_type = 0, + .name = "ddr", + .mem_table = glymur_ddr_table, + .num_opps = ARRAY_SIZE(glymur_ddr_table), + .monitor_cnt = 4, + .memory_range = { .min_freq = 547000, .max_freq = 4761000}, + .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) { + { + .name = "mon_0", + .cpu_mask = 0x3f, + .ipm_ceil = 60000000, + .be_stall_floor = 1, + .table_len = 8, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 960, .mem_freq = 547000 }, + { .cpu_freq = 1133, .mem_freq = 1353000 }, + { .cpu_freq = 1594, .mem_freq = 1555000 }, + { .cpu_freq = 1920, .mem_freq = 1708000 }, + { .cpu_freq = 2228, .mem_freq = 2736000 }, + { .cpu_freq = 2362, .mem_freq = 3187000 }, + { .cpu_freq = 2650, .mem_freq = 3686000 }, + { .cpu_freq = 2938, .mem_freq = 4761000 }, + } + }, + { + .name = "mon_1", + .cpu_mask = 0xfc0, + .ipm_ceil = 60000000, + .be_stall_floor = 1, + .table_len = 8, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 356, .mem_freq = 547000 }, + { .cpu_freq = 1018, .mem_freq = 1353000 }, + { .cpu_freq = 1536, .mem_freq = 1555000 }, + { .cpu_freq = 1748, .mem_freq = 1708800 }, + { .cpu_freq = 2324, .mem_freq = 2736000 }, + { .cpu_freq = 2496, .mem_freq = 3187000 }, + { .cpu_freq = 2900, .mem_freq = 3686000 }, + { .cpu_freq = 3514, .mem_freq = 4761000 }, + } + }, + { + .name = "mon_2", + .cpu_mask = 0x3f000, + .ipm_ceil = 60000000, + .be_stall_floor = 1, + .table_len = 8, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 356, .mem_freq = 547000 }, + { .cpu_freq = 1018, .mem_freq = 1353000 }, + { .cpu_freq = 1536, .mem_freq = 1555000 }, + { .cpu_freq = 1748, .mem_freq = 1708800 }, + { .cpu_freq = 2324, .mem_freq = 2736000 }, + { .cpu_freq = 2496, .mem_freq = 3187000 }, + { .cpu_freq = 2900, .mem_freq = 3686000 }, + { .cpu_freq = 3514, .mem_freq = 4761000 }, + } + }, + { + .name = "mon_3", + .cpu_mask = 0x3ffff, + .table_len = 4, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 2823, .mem_freq = 547000 }, + { .cpu_freq = 3034, .mem_freq = 1555000 }, + { .cpu_freq = 3226, .mem_freq = 1708000 }, + { .cpu_freq = 5012, .mem_freq = 2092000 }, + } + }, + }, + }, + { + .memory_type = 1, + .name = "llcc", + .mem_table = glymur_llcc_table, + .num_opps = ARRAY_SIZE(glymur_llcc_table), + .monitor_cnt = 3, + .memory_range = { .min_freq = 315000, .max_freq = 1211000}, + .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) { + { + .name = "mon_0", + .cpu_mask = 0x3f, + .ipm_ceil = 60000000, + .be_stall_floor = 1, + .table_len = 7, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 960, .mem_freq = 315000 }, + { .cpu_freq = 1113, .mem_freq = 479000 }, + { .cpu_freq = 1594, .mem_freq = 545000 }, + { .cpu_freq = 1920, .mem_freq = 725000 }, + { .cpu_freq = 2362, .mem_freq = 840000 }, + { .cpu_freq = 2650, .mem_freq = 959000 }, + { .cpu_freq = 2938, .mem_freq = 1211000 }, + } + }, + { + .name = "mon_1", + .cpu_mask = 0xfc0, + .ipm_ceil = 60000000, + .be_stall_floor = 1, + .table_len = 7, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 356, .mem_freq = 315000 }, + { .cpu_freq = 1018, .mem_freq = 479000 }, + { .cpu_freq = 1536, .mem_freq = 545000 }, + { .cpu_freq = 1748, .mem_freq = 725000 }, + { .cpu_freq = 2496, .mem_freq = 840000 }, + { .cpu_freq = 2900, .mem_freq = 959000 }, + { .cpu_freq = 3514, .mem_freq = 1211000 }, + } + }, + { + .name = "mon_2", + .cpu_mask = 0x3f000, + .ipm_ceil = 60000000, + .be_stall_floor = 1, + .table_len = 7, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 356, .mem_freq = 315000 }, + { .cpu_freq = 1018, .mem_freq = 479000 }, + { .cpu_freq = 1536, .mem_freq = 545000 }, + { .cpu_freq = 1748, .mem_freq = 725000 }, + { .cpu_freq = 2496, .mem_freq = 840000 }, + { .cpu_freq = 2900, .mem_freq = 959000 }, + { .cpu_freq = 3514, .mem_freq = 1211000 }, + } + }, + }, + }, + { + .memory_type = 2, + .name = "ddr-qos", + .monitor_cnt = 3, + .mem_table = glymur_ddr_qos_table, + .num_opps = ARRAY_SIZE(glymur_ddr_qos_table), + .memory_range = { .min_freq = 0, .max_freq = 1}, + .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) { + { + .name = "mon_0", + .cpu_mask = 0x3f, + .ipm_ceil = 80000000, + .be_stall_floor = 1, + .table_len = 2, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 2362, .mem_freq = 0 }, + { .cpu_freq = 2938, .mem_freq = 1 }, + } + }, + { + .name = "mon_1", + .cpu_mask = 0xfc0, + .ipm_ceil = 80000000, + .be_stall_floor = 1, + .table_len = 2, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 2496, .mem_freq = 0 }, + { .cpu_freq = 3514, .mem_freq = 1 }, + } + }, + { + .name = "mon_2", + .cpu_mask = 0x3f000, + .ipm_ceil = 80000000, + .be_stall_floor = 1, + .table_len = 2, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 2496, .mem_freq = 0 }, + { .cpu_freq = 3514, .mem_freq = 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memory_cfg hamoa_memory_cfg[] = { + { + .memory_type = 0, + .name = "ddr", + .mem_table = hamoa_ddr_table, + .num_opps = ARRAY_SIZE(hamoa_ddr_table), + .monitor_cnt = 4, + .memory_range = { .min_freq = 200000, .max_freq = 4224000}, + .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) { + { + .name = "mon_0", + .cpu_mask = 0xf, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 6, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 999, .mem_freq = 547000 }, + { .cpu_freq = 1440, .mem_freq = 768000 }, + { .cpu_freq = 1671, .mem_freq = 1555000 }, + { .cpu_freq = 2189, .mem_freq = 2092000 }, + { .cpu_freq = 2516, .mem_freq = 3187000 }, + { .cpu_freq = 3860, .mem_freq = 4224000 }, + } + }, + { + .name = "mon_1", + .cpu_mask = 0xf0, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 6, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 999, .mem_freq = 547000 }, + { .cpu_freq = 1440, .mem_freq = 768000 }, + { .cpu_freq = 1671, .mem_freq = 1555000 }, + { .cpu_freq = 2189, .mem_freq = 2092000 }, + { .cpu_freq = 2516, .mem_freq = 3187000 }, + { .cpu_freq = 3860, .mem_freq = 4224000 }, + } + }, + { + .name = "mon_2", + .cpu_mask = 0xf00, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 6, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 999, .mem_freq = 547000 }, + { .cpu_freq = 1440, .mem_freq = 768000 }, + { .cpu_freq = 1671, .mem_freq = 1555000 }, + { .cpu_freq = 2189, .mem_freq = 2092000 }, + { .cpu_freq = 2516, .mem_freq = 3187000 }, + { .cpu_freq = 3860, .mem_freq = 4224000 }, + } + }, + { + .name = "mon_3", + .cpu_mask = 0xfff, + .table_len = 4, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 1440, .mem_freq = 547000 }, + { .cpu_freq = 2189, .mem_freq = 768000 }, + { .cpu_freq = 2516, .mem_freq = 1555000 }, + { .cpu_freq = 3860, .mem_freq = 2092000 }, + } + }, + }, + }, + { + .memory_type = 1, + .name = "llcc", + .mem_table = hamoa_llcc_table, + .num_opps = ARRAY_SIZE(hamoa_llcc_table), + .monitor_cnt = 3, + .memory_range = { .min_freq = 300000, .max_freq = 1067000}, + .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) { + { + .name = "mon_0", + .cpu_mask = 0xf, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 6, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 999, .mem_freq = 300000 }, + { .cpu_freq = 1440, .mem_freq = 466000 }, + { .cpu_freq = 1671, .mem_freq = 600000 }, + { .cpu_freq = 2189, .mem_freq = 806000 }, + { .cpu_freq = 2516, .mem_freq = 933000 }, + { .cpu_freq = 3860, .mem_freq = 1066000 }, + } + }, + { + .name = "mon_1", + .cpu_mask = 0xf0, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 6, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 999, .mem_freq = 300000 }, + { .cpu_freq = 1440, .mem_freq = 466000 }, + { .cpu_freq = 1671, .mem_freq = 600000 }, + { .cpu_freq = 2189, .mem_freq = 806000 }, + { .cpu_freq = 2516, .mem_freq = 933000 }, + { .cpu_freq = 3860, .mem_freq = 1066000 }, + } + }, + { + .name = "mon_2", + .cpu_mask = 0xf00, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 6, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 999, .mem_freq = 300000 }, + { .cpu_freq = 1440, .mem_freq = 466000 }, + { .cpu_freq = 1671, .mem_freq = 600000 }, + { .cpu_freq = 2189, .mem_freq = 806000 }, + { .cpu_freq = 2516, .mem_freq = 933000 }, + { .cpu_freq = 3860, .mem_freq = 1066000 }, + } + }, + }, + }, + { + .memory_type = 2, + .name = "ddr-qos", + .monitor_cnt = 3, + .mem_table = glymur_ddr_qos_table, + .num_opps = ARRAY_SIZE(glymur_ddr_qos_table), + .memory_range = { .min_freq = 0, .max_freq = 1}, + .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) { + { + .name = "mon_0", + .cpu_mask = 0xf, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 2, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 2189, .mem_freq = 0 }, + { .cpu_freq = 3860, .mem_freq = 1 }, + } + }, + { + .name = "mon_1", + .cpu_mask = 0xf0, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 2, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 2189, .mem_freq = 0 }, + { .cpu_freq = 3860, .mem_freq = 1 }, + } + }, + { + .name = "mon_2", + .cpu_mask = 0xf00, + .ipm_ceil = 20000000, + .be_stall_floor = 1, + .table_len = 2, + .table = (const struct scmi_qcom_map_table[]) { + { .cpu_freq = 2189, .mem_freq = 0 }, + { .cpu_freq = 3860, .mem_freq = 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memlat_cfg_data glymur_memlat_data = { + .memory_cfg = glymur_memory_cfg, + .cpucp_freq_method = CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1, + .cpucp_sample_ms = 4, + .memory_cnt = ARRAY_SIZE(glymur_memory_cfg), +}; + +static const struct scmi_qcom_memlat_cfg_data hamoa_memlat_data = { + .memory_cfg = hamoa_memory_cfg, + .cpucp_freq_method = CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1, + .cpucp_sample_ms = 4, + .memory_cnt = ARRAY_SIZE(hamoa_memory_cfg), +}; + +#endif diff --git a/drivers/devfreq/scmi-qcom-memlat-devfreq.c b/drivers/devfreq/scmi-qcom-memlat-devfreq.c new file mode 100644 index 0000000000000..c75bfb16bb2b9 --- /dev/null +++ b/drivers/devfreq/scmi-qcom-memlat-devfreq.c @@ -0,0 +1,582 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_MEMORY_TYPES 4 +#define MAX_MONITOR_CNT 5 +#define MAX_NAME_LEN 20 +#define MAX_MAP_ENTRIES 10 + +#include "scmi-qcom-memlat-cfg.h" + +/** + * enum scmi_memlat_protocol_cmd - parameter_ids supported by the "MEMLAT" algo_str hosted + * by the Qualcomm Generic Vendor Protocol on the SCMI controller. + * + * MEMLAT (Memory Latency) monitors the counters to detect memory latency bound workloads + * and scales the frequency/levels of the memory buses accordingly. + * + * @MEMLAT_SET_MEM_GROUP: initializes the frequency/level scaling functions for the memory bus. + * @MEMLAT_SET_MONITOR: configures the monitor to work on a specific memory bus. + * @MEMLAT_SET_COMMON_EV_MAP: set up common counters used to monitor the cpu frequency. + * @MEMLAT_SET_GRP_EV_MAP: set up any specific counters used to monitor the memory bus. + * @MEMLAT_IPM_CEIL: set the IPM (Instruction Per Misses) ceiling per monitor. + * @MEMLAT_SAMPLE_MS: set the sampling period for all the monitors. + * @MEMLAT_MON_FREQ_MAP: setup the cpufreq to memfreq map. + * @MEMLAT_SET_MIN_FREQ: set the max frequency of the memory bus. + * @MEMLAT_SET_MAX_FREQ: set the min frequency of the memory bus. + * @MEMLAT_START_TIMER: start all the monitors with the requested sampling period. + * @MEMLAT_STOP_TIMER: stop all the running monitors. + * @MEMLAT_SET_EFFECTIVE_FREQ_METHOD: set the method used to determine cpu frequency. + */ +enum scmi_memlat_protocol_cmd { + MEMLAT_SET_MEM_GROUP = 16, + MEMLAT_SET_MONITOR, + MEMLAT_SET_COMMON_EV_MAP, + MEMLAT_SET_GRP_EV_MAP, + MEMLAT_IPM_CEIL = 23, + MEMLAT_BE_STALL_FLOOR = 25, + MEMLAT_SAMPLE_MS = 31, + MEMLAT_MON_FREQ_MAP, + MEMLAT_SET_MIN_FREQ, + MEMLAT_SET_MAX_FREQ, + MEMLAT_GET_CUR_FREQ, + MEMLAT_START_TIMER = 36, + MEMLAT_STOP_TIMER, + MEMLAT_SET_EFFECTIVE_FREQ_METHOD = 39, +}; + +struct cpucp_map_table { + u16 v1; + u16 v2; +}; + +struct map_param_msg { + u32 hw_type; + u32 mon_idx; + u32 nr_rows; + struct cpucp_map_table tbl[MAX_MAP_ENTRIES]; +} __packed; + +struct node_msg { + u32 cpumask; + u32 hw_type; + u32 mon_type; + u32 mon_idx; + char mon_name[MAX_NAME_LEN]; +}; + +struct scalar_param_msg { + u32 hw_type; + u32 mon_idx; + u32 val; +}; + +enum common_ev_idx { + INST_IDX, + CYC_IDX, + CONST_CYC_IDX, + FE_STALL_IDX, + BE_STALL_IDX, + NUM_COMMON_EVS +}; + +enum grp_ev_idx { + MISS_IDX, + WB_IDX, + ACC_IDX, + NUM_GRP_EVS +}; + +struct ev_map_msg { + u32 num_evs; + u32 hw_type; + u32 cid[NUM_COMMON_EVS]; +}; + +struct scmi_qcom_memlat_map { + unsigned int cpufreq_mhz; + unsigned int memfreq_khz; +}; + +struct scmi_qcom_monitor_info { + struct scmi_qcom_memlat_map *freq_map; + char name[MAX_NAME_LEN]; + u32 mon_idx; + u32 mon_type; + u32 ipm_ceil; + u32 be_stall_floor; + u32 mask; + u32 freq_map_len; +}; + +struct scmi_qcom_memory_info { + struct scmi_qcom_monitor_info *monitor[MAX_MONITOR_CNT]; + u32 hw_type; + int monitor_cnt; + u32 min_freq; + u32 max_freq; + struct devfreq_dev_profile profile; + struct devfreq *devfreq; + struct platform_device *pdev; + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; +}; + +struct scmi_qcom_memlat_info { + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; + struct scmi_qcom_memory_info *memory[MAX_MEMORY_TYPES]; + u32 cpucp_freq_method; + u32 cpucp_sample_ms; + int memory_cnt; +}; + +static int configure_cpucp_common_events(struct scmi_qcom_memlat_info *info) +{ + const struct qcom_generic_ext_ops *ops = info->ops; + u8 ev_map[NUM_COMMON_EVS]; + struct ev_map_msg msg; + + memset(ev_map, 0xFF, NUM_COMMON_EVS); + + msg.num_evs = NUM_COMMON_EVS; + msg.cid[INST_IDX] = EV_INST_RETIRED; + msg.cid[CYC_IDX] = EV_CPU_CYCLES; + msg.cid[CONST_CYC_IDX] = EV_CNT_CYCLES; + msg.cid[FE_STALL_IDX] = INVALID_IDX; + msg.cid[BE_STALL_IDX] = EV_STALL_BACKEND_MEM; + + return ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, + MEMLAT_SET_COMMON_EV_MAP); +} + +static int configure_cpucp_grp(struct device *dev, struct scmi_qcom_memlat_info *info, + int memory_index) +{ + struct scmi_qcom_memory_info *memory = info->memory[memory_index]; + const struct qcom_generic_ext_ops *ops = info->ops; + struct ev_map_msg ev_msg; + u8 ev_map[NUM_GRP_EVS]; + struct node_msg msg; + int ret; + + msg.cpumask = 0; + msg.hw_type = memory->hw_type; + msg.mon_type = 0; + msg.mon_idx = 0; + ret = ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEMLAT_SET_MEM_GROUP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure mem type %d\n", + memory->hw_type); + + memset(ev_map, 0xFF, NUM_GRP_EVS); + ev_msg.num_evs = NUM_GRP_EVS; + ev_msg.hw_type = memory->hw_type; + ev_msg.cid[MISS_IDX] = EV_L2_D_RFILL; + ev_msg.cid[WB_IDX] = INVALID_IDX; + ev_msg.cid[ACC_IDX] = INVALID_IDX; + ret = ops->set_param(info->ph, &ev_msg, sizeof(ev_msg), MEMLAT_ALGO_STR, + MEMLAT_SET_GRP_EV_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure event map for mem type %d\n", + memory->hw_type); + + return ret; +} + +static int configure_cpucp_mon(struct device *dev, struct scmi_qcom_memlat_info *info, + int memory_index, int monitor_index) +{ + const struct qcom_generic_ext_ops *ops = info->ops; + struct scmi_qcom_memory_info *memory = info->memory[memory_index]; + struct scmi_qcom_monitor_info *monitor = memory->monitor[monitor_index]; + struct scalar_param_msg scalar_msg; + struct map_param_msg map_msg; + struct node_msg msg; + int ret; + int i; + + msg.cpumask = monitor->mask; + msg.hw_type = memory->hw_type; + msg.mon_type = monitor->mon_type; + msg.mon_idx = monitor->mon_idx; + strscpy(msg.mon_name, monitor->name, sizeof(msg.mon_name)); + ret = ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEMLAT_SET_MONITOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure monitor %s\n", + monitor->name); + + scalar_msg.hw_type = memory->hw_type; + scalar_msg.mon_idx = monitor->mon_idx; + scalar_msg.val = monitor->ipm_ceil; + ret = ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR, + MEMLAT_IPM_CEIL); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set ipm ceil for %s\n", + monitor->name); + + scalar_msg.hw_type = memory->hw_type; + scalar_msg.mon_idx = monitor->mon_idx; + scalar_msg.val = monitor->be_stall_floor; + ret = ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR, + MEMLAT_BE_STALL_FLOOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set ipm ceil for %s\n", monitor->name); + + map_msg.hw_type = memory->hw_type; + map_msg.mon_idx = monitor->mon_idx; + map_msg.nr_rows = monitor->freq_map_len; + for (i = 0; i < monitor->freq_map_len; i++) { + map_msg.tbl[i].v1 = monitor->freq_map[i].cpufreq_mhz; + + if (monitor->freq_map[i].memfreq_khz > 1) + map_msg.tbl[i].v2 = monitor->freq_map[i].memfreq_khz / 1000; + else + map_msg.tbl[i].v2 = monitor->freq_map[i].memfreq_khz; + } + ret = ops->set_param(info->ph, &map_msg, sizeof(map_msg), MEMLAT_ALGO_STR, + MEMLAT_MON_FREQ_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure freq_map for %s\n", + monitor->name); + + scalar_msg.hw_type = memory->hw_type; + scalar_msg.mon_idx = monitor->mon_idx; + scalar_msg.val = memory->min_freq; + ret = ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR, + MEMLAT_SET_MIN_FREQ); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set min_freq for %s\n", + monitor->name); + + scalar_msg.hw_type = memory->hw_type; + scalar_msg.mon_idx = monitor->mon_idx; + scalar_msg.val = memory->max_freq; + ret = ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR, + MEMLAT_SET_MAX_FREQ); + if (ret < 0) + dev_err_probe(dev, ret, "failed to set max_freq for %s\n", monitor->name); + + return ret; +} + +static int scmi_qcom_devfreq_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct scmi_qcom_memory_info *memory = dev_get_drvdata(dev); + const struct qcom_generic_ext_ops *ops; + struct scalar_param_msg scalar_msg; + int ret; + + ops = memory->ops; + + scalar_msg.hw_type = memory->hw_type; + scalar_msg.mon_idx = 0; + u32 cur_freq; + + ret = ops->get_param(memory->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR, + MEMLAT_GET_CUR_FREQ, sizeof(cur_freq)); + if (ret < 0) { + pr_err("failed to get mon current frequency\n"); + return ret; + } + + memcpy(&cur_freq, (void *)&scalar_msg, sizeof(cur_freq)); + + if (memory->hw_type == 2) + *freq = le32_to_cpu(cur_freq) ? 100 : 1; + else + *freq = le32_to_cpu(cur_freq) * 1000UL; + + return 0; +} + +static int scmi_qcom_memlat_configure_events(struct scmi_device *sdev, + struct scmi_qcom_memlat_info *info) +{ + const struct qcom_generic_ext_ops *ops = info->ops; + struct scmi_protocol_handle *ph = info->ph; + int i, j, ret; + + /* Configure common events ids */ + ret = configure_cpucp_common_events(info); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to configure common events\n"); + + for (i = 0; i < info->memory_cnt; i++) { + /* Configure per group parameters */ + ret = configure_cpucp_grp(&sdev->dev, info, i); + if (ret < 0) + return ret; + + for (j = 0; j < info->memory[i]->monitor_cnt; j++) { + /* Configure per monitor parameters */ + ret = configure_cpucp_mon(&sdev->dev, info, i, j); + if (ret < 0) + return ret; + } + } + + /* Set loop sampling time */ + ret = ops->set_param(ph, &info->cpucp_sample_ms, sizeof(info->cpucp_sample_ms), + MEMLAT_ALGO_STR, MEMLAT_SAMPLE_MS); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to set sample_ms\n"); + + /* Set the effective cpu frequency calculation method */ + ret = ops->set_param(ph, &info->cpucp_freq_method, sizeof(info->cpucp_freq_method), + MEMLAT_ALGO_STR, MEMLAT_SET_EFFECTIVE_FREQ_METHOD); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, + "failed to set effective frequency calc method\n"); + + /* Start sampling and voting timer */ + ret = ops->start_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_START_TIMER); + if (ret < 0) + dev_err_probe(&sdev->dev, ret, "failed to start memory group timer\n"); + + for (i = 0; i < info->memory_cnt; i++) { + struct scmi_qcom_memory_info *memory = info->memory[i]; + struct platform_device *pdev = memory->pdev; + struct devfreq_dev_profile *profile = &memory->profile; + + profile->polling_ms = info->cpucp_sample_ms; + profile->get_cur_freq = scmi_qcom_devfreq_get_cur_freq; + profile->initial_freq = memory->min_freq > 1 ? + (memory->min_freq * 1000UL) : memory->min_freq; + + memory->ops = info->ops; + memory->ph = info->ph; + + platform_set_drvdata(pdev, memory); + + memory->devfreq = devm_devfreq_add_device(&pdev->dev, profile, + DEVFREQ_GOV_REMOTE, NULL); + if (IS_ERR(memory->devfreq)) { + dev_err(&sdev->dev, "failed to add devfreq device\n"); + /* Start sampling and voting timer */ + ret = ops->start_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_STOP_TIMER); + if (ret < 0) + dev_err_probe(&sdev->dev, ret, + "failed to stop memory group timer\n"); + return -EINVAL; + } + } + + return 0; +} + +static struct scmi_qcom_memlat_map *scmi_qcom_parse_memlat_map(struct device *dev, + const struct scmi_qcom_monitor_cfg *mon_cfg) +{ + struct scmi_qcom_memlat_map *map_table; + const struct scmi_qcom_map_table *table; + + map_table = devm_kzalloc(dev, MAX_MAP_ENTRIES * sizeof(struct scmi_qcom_memlat_map), + GFP_KERNEL); + if (!map_table) + return ERR_PTR(-ENOMEM); + + for (int i = 0; i < mon_cfg->table_len; i++) { + table = &mon_cfg->table[i]; + + map_table[i].cpufreq_mhz = table->cpu_freq; + map_table[i].memfreq_khz = table->mem_freq; + } + + return map_table; +} + +static const struct of_device_id scmi_qcom_memlat_configs[] __maybe_unused = { + { .compatible = "qcom,glymur", .data = &glymur_memlat_data}, + { .compatible = "qcom,mahua", .data = &glymur_memlat_data}, + { .compatible = "qcom,x1e80100", .data = &hamoa_memlat_data}, + { .compatible = "qcom,x1p42100", .data = &hamoa_memlat_data}, + { } +}; + +static int scmi_qcom_memlat_parse_cfg(struct scmi_device *sdev, struct scmi_qcom_memlat_info *info) +{ + const struct scmi_qcom_memlat_cfg_data *cfg_data; + struct scmi_qcom_monitor_info *monitor; + struct scmi_qcom_memory_info *memory; + int ret, i, j; + + cfg_data = of_machine_get_match_data(scmi_qcom_memlat_configs); + if (!cfg_data) { + return dev_err_probe(&sdev->dev, PTR_ERR(cfg_data), + "Couldn't find config data for this platform\n"); + } + + for (i = 0; i < cfg_data->memory_cnt; i++) { + const struct scmi_qcom_memory_cfg *memory_cfg = &cfg_data->memory_cfg[i]; + struct platform_device_info pdevinfo = { 0 }; + + pdevinfo.parent = &sdev->dev; + pdevinfo.name = memory_cfg->name; + pdevinfo.id = PLATFORM_DEVID_NONE; + + memory = devm_kzalloc(&sdev->dev, sizeof(*memory), GFP_KERNEL); + if (!memory) { + ret = -ENOMEM; + goto out; + } + + memory->ops = info->ops; + memory->ph = info->ph; + memory->hw_type = memory_cfg->memory_type; + memory->monitor_cnt = memory_cfg->monitor_cnt; + memory->min_freq = memory_cfg->memory_range.min_freq; + memory->max_freq = memory_cfg->memory_range.max_freq; + + memory->pdev = platform_device_register_full(&pdevinfo); + if (IS_ERR(memory->pdev)) { + dev_err_probe(&sdev->dev, PTR_ERR(memory->pdev), + "failed to register platform device\n"); + ret = PTR_ERR(memory->pdev); + goto out; + } + + info->memory[i] = memory; + + for (j = 0; j < memory_cfg->num_opps; j++) { + const struct scmi_qcom_opp_data *table = &memory_cfg->mem_table[j]; + struct platform_device *pdev = memory->pdev; + struct dev_pm_opp_data data; + + data.freq = table->freq; + data.level = table->level; + + ret = dev_pm_opp_add_dynamic(&pdev->dev, &data); + if (ret) { + dev_err_probe(&sdev->dev, ret, "failed to add OPP\n"); + dev_pm_opp_remove_all_dynamic(&pdev->dev); + goto out; + } + } + + for (j = 0; j < memory_cfg->monitor_cnt; j++) { + const struct scmi_qcom_monitor_cfg *monitor_cfg = &memory_cfg->monitor_cfg[j]; + + monitor = devm_kzalloc(&sdev->dev, sizeof(*monitor), GFP_KERNEL); + if (!monitor) + return -ENOMEM; + + monitor->ipm_ceil = monitor_cfg->ipm_ceil; + monitor->mon_type = monitor->ipm_ceil ? 0 : 1; + monitor->be_stall_floor = monitor_cfg->be_stall_floor; + monitor->mask = monitor_cfg->cpu_mask; + monitor->freq_map_len = monitor_cfg->table_len; + + monitor->freq_map = scmi_qcom_parse_memlat_map(&sdev->dev, monitor_cfg); + if (IS_ERR(monitor->freq_map)) { + dev_err_probe(&sdev->dev, PTR_ERR(monitor->freq_map), + "failed to populate cpufreq-memfreq map\n"); + ret = -EINVAL; + goto out; + } + + strscpy(monitor->name, monitor_cfg->name, sizeof(monitor->name)); + monitor->mon_idx = j; + memory->monitor[j] = monitor; + } + } + + info->cpucp_freq_method = cfg_data->cpucp_freq_method; + info->cpucp_sample_ms = cfg_data->cpucp_sample_ms; + info->memory_cnt = cfg_data->memory_cnt; + + return 0; + +out: + for (i = 0; i < cfg_data->memory_cnt; i++) { + if (IS_ERR_OR_NULL(info->memory[i])) + break; + + memory = info->memory[i]; + if (!IS_ERR(memory->pdev)) + platform_device_unregister(memory->pdev); + } + + return ret; +} + +static int scmi_qcom_devfreq_memlat_probe(struct scmi_device *sdev) +{ + const struct scmi_handle *handle = sdev->handle; + const struct qcom_generic_ext_ops *ops; + struct scmi_qcom_memlat_info *info; + struct scmi_protocol_handle *ph; + int ret; + + if (!handle) + return -ENODEV; + + info = devm_kzalloc(&sdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_QCOM_GENERIC, &ph); + if (IS_ERR(ops)) + return PTR_ERR(ops); + + info->ops = ops; + info->ph = ph; + + ret = scmi_qcom_memlat_parse_cfg(sdev, info); + if (ret) + return ret; + + ret = scmi_qcom_memlat_configure_events(sdev, info); + if (ret) + return ret; + + dev_set_drvdata(&sdev->dev, info); + + return ret; +} + +static void scmi_qcom_devfreq_memlat_remove(struct scmi_device *sdev) +{ + struct scmi_qcom_memlat_info *info = dev_get_drvdata(&sdev->dev); + + for (int i = 0; i < info->memory_cnt; i++) { + struct scmi_qcom_memory_info *memory = info->memory[i]; + + if (!IS_ERR(memory->pdev)) + platform_device_unregister(memory->pdev); + } +} + +static const struct scmi_device_id scmi_id_table[] = { + { SCMI_PROTOCOL_QCOM_GENERIC, "qcom-generic-ext" }, + { }, +}; +MODULE_DEVICE_TABLE(scmi, scmi_id_table); + +static struct scmi_driver scmi_qcom_devfreq_memlat_driver = { + .name = "scmi-qcom-devfreq-memlat", + .probe = scmi_qcom_devfreq_memlat_probe, + .remove = scmi_qcom_devfreq_memlat_remove, + .id_table = scmi_id_table, +}; +module_scmi_driver(scmi_qcom_devfreq_memlat_driver); + +MODULE_AUTHOR("Sibi Sankar "); +MODULE_DESCRIPTION("SCMI QCOM DEVFREQ MEMLAT driver"); +MODULE_LICENSE("GPL"); From 27b90bba7cb27e3132518f159b9ad9db2e4e36af Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Thu, 16 Apr 2026 22:42:00 -0700 Subject: [PATCH 0859/1330] FROMLIST: arm64: dts: qcom: purwa: Add EL2 overlay for purwa-iot-evk Add support for building an EL2 combined DTB for the purwa-iot-evk in the Qualcomm DTS Makefile. The new purwa-iot-evk-el2.dtb is generated by combining the base purwa-iot-evk.dtb with the x1-el2.dtbo overlay, enabling EL2-specific configurations required by the platform. Signed-off-by: Xin Liu Link: https://lore.kernel.org/all/20260417054200.2402281-1-xin.liu@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov (cherry picked from commit a0521166c4d7d0cf502a55528474cdcd3c8897e6) --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5b77b11127cb3..7880dbf7a35ef 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -164,6 +164,10 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk.dtb + +purwa-iot-evk-el2-dtbs := purwa-iot-evk.dtb x1-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb From 26c6495ae41ad670457ae1c520c798a10c2be826 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 13:40:52 +0530 Subject: [PATCH 0860/1330] FROMLIST: arm64: dts: qcom: glymur: add TRNG node Glymur has a True Random Number Generator, add the node with the correct compatible set. Link: https://lore.kernel.org/all/20260424-glymur_trng_enablement-v2-2-0603cbe68440@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev (cherry picked from commit 0dfe39e8b3670772ef55355a77d1e09e8a0b0752) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 361ddfec97481..b1eb5cfa64184 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4046,6 +4046,11 @@ status = "disabled"; }; + rng: rng@10c3000 { + compatible = "qcom,glymur-trng", "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From b3642588ce31750ed10e8c88b47da560e28faa65 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 18:15:49 +0530 Subject: [PATCH 0861/1330] FROMLIST: arm64: dts: qcom: glymur: Add crypto engine and BAM On almost all Qualcomm platforms, including Glymur, there is a Crypto engine IP block to which the CPU can off-load cryptographic computations for achieving acceleration. The engine is also DMA capable due to the presence of an associated Bus Access Manager (BAM) module. Describe the Crypto engine and its BAM. Link: https://lore.kernel.org/all/20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.com/ Signed-off-by: Harshal Dev (cherry picked from commit 457196c06429c0cbb32b936e90b2a8ca753157f6) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index b1eb5cfa64184..eaca3b1c404ac 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4051,6 +4051,32 @@ reg = <0x0 0x010c3000 0x0 0x1000>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu 0x80 0x0>, + <&apps_smmu 0x81 0x0>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <20>; + qcom,num-ees = <4>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", + "tx"; + iommus = <&apps_smmu 0x80 0x0>, + <&apps_smmu 0x81 0x0>; + interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From ae24074fea5f23b34cab6e433073b2def35647ed Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 13:34:21 +0530 Subject: [PATCH 0862/1330] FROMLIST: dt-bindings: crypto: qcom,prng: Document Glymur TRNG Document glymur compatible for the True Random Number Generator. Link: https://lore.kernel.org/all/20260424-glymur_trng_enablement-v2-1-0603cbe68440@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Harshal Dev (cherry picked from commit 380a518d34e3fe5d13c85214eb83cb7a39ff87cf) --- Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml index 41402599e9ab8..498d6914135e8 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -17,6 +17,7 @@ properties: - qcom,prng-ee # 8996 and later using EE - items: - enum: + - qcom,glymur-trng - qcom,ipq5332-trng - qcom,ipq5424-trng - qcom,ipq9574-trng From 28ea4d0bff3a724a61d4bafa9d25345b380f7298 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 13:57:20 +0530 Subject: [PATCH 0863/1330] FROMLIST: dt-bindings: crypto: qcom-qce: Document the Glymur crypto engine Document the crypto engine on Glymur platform. Link: https://lore.kernel.org/all/20260505-glymur_crypto_enablement-v2-1-bf115aeb1459@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Harshal Dev (cherry picked from commit f030676615c0917a3bb04a3d0f4ca63d7561371b) --- Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index 79d5be2548bc5..0b62271f8bfe5 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -45,6 +45,7 @@ properties: - items: - enum: + - qcom,glymur-qce - qcom,kaanapali-qce - qcom,qcs615-qce - qcom,qcs8300-qce From 6bfc263208134be566dbdac19a646a8aff360b5f Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 7 May 2026 11:52:36 +0530 Subject: [PATCH 0864/1330] FROMLIST: arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS dvfs On Qualcomm Glymur SoCs, the memlat governor and the mechanism to control the LLCC and DDR/DDR_QOS is hosted on the CPU Control Processor (CPUCP). Enable the nodes required to get QCOM SCMI Generic Extension protocol to probe on Glymur and Mahua SoCs. Link: https://lore.kernel.org/lkml/20260507062237.78051-8-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar (cherry picked from commit 5fd19005ccfd07a5370eb75ee9979d5ca15c297e) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index eaca3b1c404ac..185f57d6127b7 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -366,6 +366,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; + cpucp_scmi { + compatible = "arm,scmi"; + mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; + + mbox-names = "tx", "rx"; + shmem = <&cpucp_scp_lpri0>, <&cpucp_scp_lpri1>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_vendor: protocol@80 { + reg = <0x80>; + }; + }; + scmi { compatible = "arm,scmi"; mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; @@ -7829,6 +7844,13 @@ #mbox-cells = <1>; }; + cpucp_mbox: mailbox@17620000 { + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0 0x17620000 0 0x8000>, <0 0x18830000 0 0x8000>; + interrupts = ; + #mbox-cells = <1>; + }; + timer@17810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17810000 0x0 0x1000>; @@ -8013,6 +8035,26 @@ }; }; + cpucp_sram: sram@18b4e000 { + compatible = "mmio-sram"; + reg = <0x0 0x18b4e000 0x0 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x18b4e000 0x400>; + + cpucp_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpucp_scp_lpri1: scp-sram-section@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x200>; + }; + }; + nsi_noc: interconnect@1d600000 { compatible = "qcom,glymur-nsinoc"; reg = <0x0 0x1d600000 0x0 0x14080>; From ab9869289e0c822d508ee74b62cf680cb913ebd7 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 27 Apr 2026 12:08:55 +0530 Subject: [PATCH 0865/1330] FROMLIST: clk: qcom: gdsc: Add custom disable callback for GX GDSC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GX GDSC is a special power domain that should only be disabled by OS during GMU recovery. In all other scenarios, the GMU firmware is responsible for handling its disable sequence, and OS must not interfere. During the resume_noirq() phase of system resume, the GenPD framework enables all power domains and later disables them in the complete() phase if there are no active votes from OS. This behavior can incorrectly disable the GX GDSC while the GMU firmware is still using it. To prevent this, implement a custom disable callback for GX GDSC that relies on GenPD’s synced_poweroff flag. The GMU driver sets this flag only during recovery, allowing OS to explicitly disable GX GDSC in hardware in that case. In all other situations, the disable callback will avoid touching GX GDSC hardware. Signed-off-by: Jagadeesh Kona Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-1-797e54b3d464@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit 13610c9b09b946e07b2b55518962f6c498a844f3) --- drivers/clk/qcom/gdsc.c | 22 ++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 95aa071202455..ab5d741a2e235 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -675,3 +675,25 @@ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) return ret; } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); + +/* + * GX GDSC is a special power domain. Normally, its disable sequence + * is managed by the GMU firmware, and high level OS must not attempt + * to disable it. The only exception is during GMU recovery, where the + * GMU driver can set GenPD’s synced_poweroff flag to allow explicitly + * disable GX GDSC in hardware. + */ +int gdsc_gx_disable(struct generic_pm_domain *domain) +{ + struct gdsc *sc = domain_to_gdsc(domain); + + if (domain->synced_poweroff) + return gdsc_disable(domain); + + /* Remove parent-supply placed in enable */ + if (sc->rsupply) + return regulator_disable(sc->rsupply); + + return 0; +} +EXPORT_SYMBOL_GPL(gdsc_gx_disable); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index dd843e86c05b2..495daebaf9951 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -88,6 +88,7 @@ int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, struct regmap *); void gdsc_unregister(struct gdsc_desc *desc); int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain); +int gdsc_gx_disable(struct generic_pm_domain *domain); #else static inline int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *rcdev, From 1924538483c13bc4e0a1c2f60cc8d8dd5d46b723 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 27 Apr 2026 12:08:56 +0530 Subject: [PATCH 0866/1330] FROMLIST: clk: qcom: gxclkctl: Use custom disable callback for gx_gdsc The GX GDSC represents a special GPU power domain that must not be disabled during normal runtime PM flows. As per the GMU architecture, GX GDSC should only be force-disabled during GMU/GPU recovery, where the OS explicitly resets the GX power domain. However, when managed by the generic GDSC runtime PM path, GX GDSC may be disabled during GMU runtime suspend, resulting in warnings such as: gx_clkctl_gx_gdsc status stuck at 'on' and failures in gdsc_toggle_logic() during rpm suspend. Use the newly added custom disable callback for gx_gdsc to ensure the GDSC is toggled only in recovery scenarios, while preventing unintended disable attempts during normal GMU runtime PM operations. Reported-by: Pengyu Luo Closes: https://lore.kernel.org/all/CAH2e8h4Vp9fJYAUUbOmoHSKB25wakPBvmpwa62BTRqgRQbMWuw@mail.gmail.com/ Reported-by: Alexander Koskovich Closes: https://lore.kernel.org/all/gwVAH2mJerU4dBInw8pKmOs5aQK55Q7W6q_UQAlLFCsEgX6eyvSgXAWbNNMqAX4WmPlYCKUSMhfkr5Jry4Ps5EqnxYZqEEDd3Whwv7ZXGlc=@pm.me/ Fixes: 5af11acae660 ("clk: qcom: Add a driver for SM8750 GPU clocks") Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-2-797e54b3d464@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit a44ce308e141d7cbadf5ed61c791366ffb35d82c) --- drivers/clk/qcom/gxclkctl-kaanapali.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclkctl-kaanapali.c index b45ab0ac46c77..7f62392637f6c 100644 --- a/drivers/clk/qcom/gxclkctl-kaanapali.c +++ b/drivers/clk/qcom/gxclkctl-kaanapali.c @@ -27,6 +27,7 @@ static struct gdsc gx_clkctl_gx_gdsc = { .pd = { .name = "gx_clkctl_gx_gdsc", .power_on = gdsc_gx_do_nothing_enable, + .power_off = gdsc_gx_disable, }, .pwrsts = PWRSTS_OFF_ON, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, From 98dc0e4956dfb0a9f9af00e14989b7f2a3d55f62 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 27 Apr 2026 12:08:57 +0530 Subject: [PATCH 0867/1330] FROMLIST: clk: qcom: common: ensure runtime PM suspend completes on probe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the clock controller is probed with 'use_rpm' enabled, the runtime PM reference is currently released using pm_runtime_put(), which may return before the runtime suspend has completed. When the clock controller device is registered through this function, calling pm_runtime_disable() immediately after pm_runtime_put() prevents the runtime suspend from completing, leaving the clock controller active and the HW rails in the ON state. Use pm_runtime_put_sync() instead to ensure the runtime PM “putV completes synchronously during probe. This does not have any functional impact, but it guarantees that the device is fully runtime-suspended before returning. Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-3-797e54b3d464@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit 0f287b8555a738553cc284eb0fb728e1c40eb269) --- drivers/clk/qcom/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index eec369d2173b5..2c09abaf1d2a1 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -428,7 +428,7 @@ int qcom_cc_really_probe(struct device *dev, put_rpm: if (desc->use_rpm) - pm_runtime_put(dev); + pm_runtime_put_sync(dev); return ret; } From 1497823aac3fc3624707dcb41a749de6ef1fc5b3 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 27 Apr 2026 12:08:58 +0530 Subject: [PATCH 0868/1330] FROMLIST: clk: qcom: gxclkctl: Remove GX/GMxC rail votes to align with IFPC The GX GDSC control is handled through a dedicated clock controller, and the enable/disable sequencing depends on correct rail voting. The driver votes for the GX/GMxC rails and CX GDSC before toggling the GX GDSC. Currently, during GMU runtime PM resume, rails remain enabled due to upstream votes propagated via RPM-enabled devlinks and explicit pm_runtime votes on GX GDSC. This is not an expected behaviour of IFPC(Inter Frame Power Collapse) requirements of GPU as GMU firmware is expected to control these rails, except during the GPU/GMU recovery via the OS and that is where the GX GDSC should be voting for the rails (GX/GMxC and CX GDSC) before toggling the GX GDSC. Thus, disable runtime PM after successfully registering the clock controller. Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-4-797e54b3d464@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit eea3e9858db5f675261967f5b88b78727049bf98) --- drivers/clk/qcom/gxclkctl-kaanapali.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclkctl-kaanapali.c index 7f62392637f6c..dafc39232c841 100644 --- a/drivers/clk/qcom/gxclkctl-kaanapali.c +++ b/drivers/clk/qcom/gxclkctl-kaanapali.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -62,7 +63,15 @@ MODULE_DEVICE_TABLE(of, gx_clkctl_kaanapali_match_table); static int gx_clkctl_kaanapali_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gx_clkctl_kaanapali_desc); + int ret; + + ret = qcom_cc_probe(pdev, &gx_clkctl_kaanapali_desc); + if (ret) + return ret; + + pm_runtime_disable(&pdev->dev); + + return ret; } static struct platform_driver gx_clkctl_kaanapali_driver = { From 4f1de4943c05690500abac1b738b7653e10d0193 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 7 May 2026 11:52:37 +0530 Subject: [PATCH 0869/1330] FROMLIST: arm64: dts: qcom: hamoa: Enable LLCC/DDR/DDR_QOS dvfs On Qualcomm Hamoa SoCs, the memlat governor and the mechanism to control the LLCC and DDR/DDR_QOS is hosted on the CPU Control Processor (CPUCP). Add the vendor protocol node to the existing SCMI transport to enable QCOM SCMI Generic Extension protocol on Hamoa SoCs. Link: https://lore.kernel.org/lkml/20260507062237.78051-9-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar (cherry picked from commit 670d0021452a91a99d66fcef03c0af876b85469f) --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index cf47fa4e7187a..cbd06b794c317 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -552,6 +552,10 @@ reg = <0x13>; #power-domain-cells = <1>; }; + + scmi_vendor: protocol@80 { + reg = <0x80>; + }; }; }; From 7879006cf497fc757507473a4c481a2bc91cd094 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Sun, 10 May 2026 02:21:51 +0530 Subject: [PATCH 0870/1330] arm64: dts: qcom: shikra: update reserved memory regions Update reserved memory regions for Shikra aligning with new set of no-map regions. Signed-off-by: Bibek Kumar Patro (cherry picked from commit 84088d1e352a40634cda41000339b9935c3a7127) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 28f9135b1ed9b..b99516599a26d 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -246,12 +246,6 @@ no-map; }; - pvm_fw_mem: pvm-fw@86300000 { - reg = <0x0 0x86300000 0x0 0x100000>; - no-map; - }; - - /* UEFI region at 0x9F400000 is reclaimed by Linux */ tz_stat_mem: tz-stat@a0000000 { reg = <0x0 0xa0000000 0x0 0x100000>; no-map; @@ -315,20 +309,6 @@ no-map; }; - /* Linux kernel image is loaded at 0xB5000000 */ - trust_ui_vm_mem: trust-ui-vm@f3800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0xf3800000 0x0 0x4000000>; - alignment = <0x0 0x400000>; - reusable; - }; - - oem_vm_mem: oem-vm@f7c00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0xf7c00000 0x0 0x4c00000>; - alignment = <0x0 0x400000>; - reusable; - }; }; smp2p-cdsp { From 6b12c0182a7cdbbd314a3b3c54d52399e61742be Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Sun, 10 May 2026 02:32:46 +0530 Subject: [PATCH 0871/1330] arm64: dts: qcom: shikra: fix compatible field for iommu nodes Fix compatible entries for apps_smmu and adreno_smmu nodes, add missing "qcom,adreno-smmu" compatible entry for adreno_smmu node. Signed-off-by: Bibek Kumar Patro (cherry picked from commit 4bd608f82405c5475ff7170bb4dc43854909696c) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index b99516599a26d..7bb086e02135f 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1173,7 +1173,8 @@ }; adreno_smmu: iommu@59a0000 { - compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + compatible = "qcom,shikra-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x059a0000 0x0 0x10000>; #iommu-cells = <2>; #global-interrupts = <1>; @@ -1291,8 +1292,7 @@ }; apps_smmu: iommu@c600000 { - compatible = "qcom,shikra-smmu-500", "qcom,adreno-smmu", - "qcom,smmu-500", "arm,mmu-500"; + compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x0c600000 0x0 0x80000>; #iommu-cells = <2>; #global-interrupts = <1>; From 6c09cb13019812be1aa3ae80b68a70d09b898bd7 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Mon, 11 May 2026 16:19:12 +0530 Subject: [PATCH 0872/1330] arm64: dts: qcom: Modify MPM pin count for shikra Modify MPM pin count to incorporate all MPM interrupts that can be configured. Signed-off-by: Sneh Mankad (cherry picked from commit 34e225b5147bc37364aaa3d8bb180dd65be37298) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 7bb086e02135f..84d7f85bb233d 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -202,7 +202,7 @@ #interrupt-cells = <2>; #power-domain-cells = <0>; interrupt-parent = <&intc>; - qcom,mpm-pin-count = <95>; + qcom,mpm-pin-count = <96>; qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ <12 422>, /* DWC3 ss_phy_irq */ <58 272>, /* QUSB2_PHY dmse_hv_vddmx */ From 48e00653bc04926d174d24eadf11a3668e78b02e Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 11 May 2026 15:58:56 +0530 Subject: [PATCH 0873/1330] arm64: dts: qcom: Update Min and max Voltages for Shikra Retail Remove unused regulators (s1, s4, l1, l2, l11) and tighten min/max voltage ranges for remaining rails to match actual operating voltages derived from PGA report analysis. Signed-off-by: Rakesh Kota (cherry picked from commit aad592cb9d2ef66381d60414c0c3b024342ba0d6) --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 73 +++++++------------- arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi | 73 +++++++------------- 2 files changed, 48 insertions(+), 98 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 26cf4b0f31a48..107dcb442f0d8 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -176,43 +176,23 @@ regulators { compatible = "qcom,rpm-pm2250-regulators"; - pm4125_s1: s1 { - regulator-min-microvolt = <1396000>; - regulator-max-microvolt = <1950000>; - }; - pm4125_s2: s2 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; }; - pm4125_s4: s4 { - regulator-min-microvolt = <640000>; - regulator-max-microvolt = <1414000>; - }; - - pm4125_l1: l1 { - regulator-min-microvolt = <312000>; - regulator-max-microvolt = <1304000>; - }; - - pm4125_l2: l2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - }; - pm4125_l3: l3 { - regulator-min-microvolt = <570000>; + regulator-min-microvolt = <624000>; regulator-max-microvolt = <650000>; }; pm4125_l4: l4 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; }; pm4125_l5: l5 { - regulator-min-microvolt = <1100000>; + regulator-min-microvolt = <1232000>; regulator-max-microvolt = <1304000>; }; @@ -227,7 +207,7 @@ }; pm4125_l8: l8 { - regulator-min-microvolt = <875000>; + regulator-min-microvolt = <928000>; regulator-max-microvolt = <1000000>; }; @@ -237,68 +217,63 @@ }; pm4125_l10: l10 { - regulator-min-microvolt = <1150000>; + regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; }; - pm4125_l11: l11 { - regulator-min-microvolt = <970000>; - regulator-max-microvolt = <1150000>; - }; - pm4125_l12: l12 { - regulator-min-microvolt = <875000>; + regulator-min-microvolt = <928000>; regulator-max-microvolt = <975000>; }; pm4125_l13: l13 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1950000>; + regulator-max-microvolt = <1800000>; }; pm4125_l14: l14 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; pm4125_l15: l15 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2000000>; + regulator-max-microvolt = <1800000>; }; pm4125_l16: l16 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; pm4125_l17: l17 { - regulator-min-microvolt = <2900000>; + regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; }; pm4125_l18: l18 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; }; pm4125_l19: l19 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; }; pm4125_l20: l20 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <3544000>; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; }; pm4125_l21: l21 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3056000>; }; pm4125_l22: l22 { - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi index e9f5469768010..8094df7e607e1 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi @@ -177,43 +177,23 @@ regulators { compatible = "qcom,rpm-pm2250-regulators"; - pm4125_s1: s1 { - regulator-min-microvolt = <1396000>; - regulator-max-microvolt = <1950000>; - }; - pm4125_s2: s2 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; }; - pm4125_s4: s4 { - regulator-min-microvolt = <640000>; - regulator-max-microvolt = <1414000>; - }; - - pm4125_l1: l1 { - regulator-min-microvolt = <312000>; - regulator-max-microvolt = <1304000>; - }; - - pm4125_l2: l2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - }; - pm4125_l3: l3 { - regulator-min-microvolt = <570000>; + regulator-min-microvolt = <624000>; regulator-max-microvolt = <650000>; }; pm4125_l4: l4 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; }; pm4125_l5: l5 { - regulator-min-microvolt = <1100000>; + regulator-min-microvolt = <1232000>; regulator-max-microvolt = <1304000>; }; @@ -228,7 +208,7 @@ }; pm4125_l8: l8 { - regulator-min-microvolt = <875000>; + regulator-min-microvolt = <928000>; regulator-max-microvolt = <1000000>; }; @@ -238,68 +218,63 @@ }; pm4125_l10: l10 { - regulator-min-microvolt = <1150000>; + regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; }; - pm4125_l11: l11 { - regulator-min-microvolt = <970000>; - regulator-max-microvolt = <1150000>; - }; - pm4125_l12: l12 { - regulator-min-microvolt = <875000>; + regulator-min-microvolt = <928000>; regulator-max-microvolt = <975000>; }; pm4125_l13: l13 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1950000>; + regulator-max-microvolt = <1800000>; }; pm4125_l14: l14 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; pm4125_l15: l15 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2000000>; + regulator-max-microvolt = <1800000>; }; pm4125_l16: l16 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; pm4125_l17: l17 { - regulator-min-microvolt = <2900000>; + regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; }; pm4125_l18: l18 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; }; pm4125_l19: l19 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; }; pm4125_l20: l20 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <3544000>; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; }; pm4125_l21: l21 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3056000>; }; pm4125_l22: l22 { - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; }; }; }; From 218eed83609f0f59ef34fda1cd20a446ccd587b7 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 16 Apr 2026 16:22:49 +0530 Subject: [PATCH 0874/1330] dt-bindings: clock: qcom: Add Shikra Display clock controller Add device tree bindings for the Display clock controller on the Qualcomm Shikra SoC. Signed-off-by: Imran Shaik (cherry picked from commit 8ad47c91269fa92fc156a1e72b3946b3e1f26a0d) --- .../bindings/clock/qcom,shikra-dispcc.yaml | 62 +++++++++++++++++++ .../dt-bindings/clock/qcom,shikra-dispcc.h | 39 ++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,shikra-dispcc.yaml create mode 100644 include/dt-bindings/clock/qcom,shikra-dispcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-dispcc.yaml new file mode 100644 index 0000000000000..dbaecdd3e0b4b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-dispcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Display Clock & Reset Controller for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + +description: | + Display clock control module provides the clocks, resets and power + domains on Qualcomm Shikra SoC platform. + + See also: + - include/dt-bindings/clock/qcom,shikra-dispcc.h + +properties: + compatible: + enum: + - qcom,shikra-dispcc + + clocks: + items: + - description: Board XO source + - description: Board sleep clock + - description: GPLL0 DISP DIV clock from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + clock-controller@5f00000 { + compatible = "qcom,shikra-dispcc"; + reg = <0x5f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,shikra-dispcc.h b/include/dt-bindings/clock/qcom,shikra-dispcc.h new file mode 100644 index 0000000000000..088a7c692ad5d --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-dispcc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SHIKRA_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_ESC0_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK_SRC 8 +#define DISP_CC_MDSS_MDP_CLK 9 +#define DISP_CC_MDSS_MDP_CLK_SRC 10 +#define DISP_CC_MDSS_MDP_LUT_CLK 11 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12 +#define DISP_CC_MDSS_PCLK0_CLK 13 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 14 +#define DISP_CC_MDSS_VSYNC_CLK 15 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 16 +#define DISP_CC_SLEEP_CLK 17 +#define DISP_CC_SLEEP_CLK_SRC 18 +#define DISP_CC_XO_CLK 19 +#define DISP_CC_XO_CLK_SRC 20 + +/* DISP_CC power domains */ +#define DISP_CC_MDSS_CORE_GDSC 0 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +#endif From 609e153cfc30b7403f5515212f77d701d192e02d Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 16 Apr 2026 12:04:44 +0530 Subject: [PATCH 0875/1330] dt-bindings: clock: qcom: Add Shikra GPU clock controller Add device tree bindings for the GPU clock controller on the Qualcomm Shikra SoC. Signed-off-by: Imran Shaik (cherry picked from commit 5f8274b1be316c4ce6598f5aeffc7b01cca87ef5) --- .../bindings/clock/qcom,sm6115-gpucc.yaml | 6 ++- include/dt-bindings/clock/qcom,shikra-gpucc.h | 37 +++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,shikra-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml index 104ba10ca5737..1f6b5cec4642a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -8,16 +8,20 @@ title: Qualcomm Graphics Clock & Reset Controller on SM6115 maintainers: - Konrad Dybcio + - Imran Shaik description: | Qualcomm graphics clock control module provides clocks, resets and power domains on Qualcomm SoCs. - See also: include/dt-bindings/clock/qcom,sm6115-gpucc.h + See also: + include/dt-bindings/clock/qcom,shikra-gpucc.h + include/dt-bindings/clock/qcom,sm6115-gpucc.h properties: compatible: enum: + - qcom,shikra-gpucc - qcom,sm6115-gpucc clocks: diff --git a/include/dt-bindings/clock/qcom,shikra-gpucc.h b/include/dt-bindings/clock/qcom,shikra-gpucc.h new file mode 100644 index 0000000000000..60714f6cc6cd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-gpucc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SHIKRA_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_AHB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GPU_SMMU_VOTE_CLK 10 +#define GPU_CC_GX_CXO_CLK 11 +#define GPU_CC_GX_GFX3D_CLK 12 +#define GPU_CC_GX_GFX3D_CLK_SRC 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_CX_BCR 0 +#define GPU_CC_GFX3D_AON_BCR 1 +#define GPU_CC_GMU_BCR 2 +#define GPU_CC_GX_BCR 3 +#define GPU_CC_XO_BCR 4 + +#endif From 124d398c8613115e2610924e16a0257a7a46ad98 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 16 Apr 2026 21:38:06 +0530 Subject: [PATCH 0876/1330] clk: qcom: Add support for Display Clock Controller on Shikra Add a driver for the Display clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik (cherry picked from commit cc03e796a7813d484d6c1032e0754c2215dcba12) --- drivers/clk/qcom/Kconfig | 20 ++ drivers/clk/qcom/Makefile | 3 + drivers/clk/qcom/dispcc-shikra.c | 565 +++++++++++++++++++++++++++++++ 3 files changed, 588 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-shikra.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index dbe88d8da3841..b0b73641be21c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -155,6 +155,26 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. +config CLK_NORD_GCC + tristate "Nord Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on Nord devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination + of GCC, SE_GCC, NE_GCC and NW_GCC. + +config CLK_SHIKRA_DISPCC + tristate "Shikra Display Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_SHIKRA_GCC + help + Support for the display clock controller on Qualcomm Technologies, Inc + Shikra devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config CLK_SHIKRA_GCC tristate "Shikra Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 21ade4469588c..f2d21805b1631 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -33,6 +33,9 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o +obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o +obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o +obj-$(CONFIG_CLK_SHIKRA_DISPCC) += dispcc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o diff --git a/drivers/clk/qcom/dispcc-shikra.c b/drivers/clk/qcom/dispcc-shikra.c new file mode 100644 index 0000000000000..f4ae20f190465 --- /dev/null +++ b/drivers/clk/qcom/dispcc-shikra.c @@ -0,0 +1,565 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_GPLL0, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, +}; + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco spark_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +/* 768.0 MHz Configuration */ +static const struct alpha_pll_config disp_cc_pll0_config = { + .l = 0x28, + .alpha = 0x0, + .alpha_en_mask = BIT(24), + .vco_val = BIT(21), + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .config = &disp_cc_pll0_config, + .vco_table = spark_vco, + .num_vco = ARRAY_SIZE(spark_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GPLL0 }, +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .index = DT_GPLL0 }, +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, +}; + +static const struct parent_map disp_cc_parent_map_5[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_ahb_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x20a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_byte0_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .flags = CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x20c0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_esc0_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x2074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x205c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .flags = CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT, + .ops = &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x208c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_vsync_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { + F(32764, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_sleep_clk_src = { + .cmd_rcgr = 0x6050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .freq_tbl = ftbl_disp_cc_sleep_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_sleep_clk_src", + .parent_data = disp_cc_parent_data_5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_xo_clk_src = { + .cmd_rcgr = 0x6034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_xo_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { + .reg = 0x20bc, + .shift = 0, + .width = 2, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_byte0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x2044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x201c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x201c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_byte0_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x2020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x2024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_esc0_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_mdp_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x2010, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x2010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x4004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x4004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_pclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x2018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "disp_cc_mdss_vsync_clk", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc disp_cc_mdss_core_gdsc = { + .gdscr = 0x3000, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "disp_cc_mdss_core_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *disp_cc_shikra_clocks[] = { + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, + [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, + [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, +}; + +static struct gdsc *disp_cc_shikra_gdscs[] = { + [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc, +}; + +static const struct qcom_reset_map disp_cc_shikra_resets[] = { + [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, + [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, +}; + +static struct clk_alpha_pll *disp_cc_shikra_plls[] = { + &disp_cc_pll0, +}; + +static u32 disp_cc_shikra_critical_cbcrs[] = { + 0x6068, /* DISP_CC_SLEEP_CLK */ + 0x604c, /* DISP_CC_XO_CLK */ +}; + +static const struct regmap_config disp_cc_shikra_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static struct qcom_cc_driver_data disp_cc_shikra_driver_data = { + .alpha_plls = disp_cc_shikra_plls, + .num_alpha_plls = ARRAY_SIZE(disp_cc_shikra_plls), + .clk_cbcrs = disp_cc_shikra_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(disp_cc_shikra_critical_cbcrs), +}; + +static const struct qcom_cc_desc disp_cc_shikra_desc = { + .config = &disp_cc_shikra_regmap_config, + .clks = disp_cc_shikra_clocks, + .num_clks = ARRAY_SIZE(disp_cc_shikra_clocks), + .resets = disp_cc_shikra_resets, + .num_resets = ARRAY_SIZE(disp_cc_shikra_resets), + .gdscs = disp_cc_shikra_gdscs, + .num_gdscs = ARRAY_SIZE(disp_cc_shikra_gdscs), + .driver_data = &disp_cc_shikra_driver_data, +}; + +static const struct of_device_id disp_cc_shikra_match_table[] = { + { .compatible = "qcom,shikra-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_shikra_match_table); + +static int disp_cc_shikra_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &disp_cc_shikra_desc); +} + +static struct platform_driver disp_cc_shikra_driver = { + .probe = disp_cc_shikra_probe, + .driver = { + .name = "dispcc-shikra", + .of_match_table = disp_cc_shikra_match_table, + }, +}; + +module_platform_driver(disp_cc_shikra_driver); + +MODULE_DESCRIPTION("QTI DISPCC Shikra Driver"); +MODULE_LICENSE("GPL"); From 3342ae9fa0976e2fe85a744fa84b3f178bf5c927 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 16 Apr 2026 11:45:15 +0530 Subject: [PATCH 0877/1330] clk: qcom: Add support for GPU Clock Controller on Shikra Add a driver for the GPU clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik (cherry picked from commit f977be22c5df7144de2aebf21071415e55f16bc4) --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-shikra.c | 408 ++++++++++++++++++++++++++++++++ 3 files changed, 418 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-shikra.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b0b73641be21c..f6ac47a88f21f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -184,6 +184,15 @@ config CLK_SHIKRA_GCC Say Y if you want to use multimedia devices or peripheral devices such as Camera, Video, UART, SPI, I2C, USB, SD/eMMC etc. +config CLK_SHIKRA_GPUCC + tristate "Shikra Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_SHIKRA_GCC + help + Support for the graphics clock controller on Shikra devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f2d21805b1631..412b87dac32e7 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o obj-$(CONFIG_CLK_SHIKRA_DISPCC) += dispcc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o +obj-$(CONFIG_CLK_SHIKRA_GPUCC) += gpucc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o diff --git a/drivers/clk/qcom/gpucc-shikra.c b/drivers/clk/qcom/gpucc-shikra.c new file mode 100644 index 0000000000000..19a938a14d68d --- /dev/null +++ b/drivers/clk/qcom/gpucc-shikra.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_2X_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_AUX, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco huayra_vco[] = { + { 600000000, 3300000000, 0 }, + { 600000000, 2200000000, 1 }, +}; + +/* 710.4 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x25, + .cal_l = 0x4e, + .alpha = 0x0, + .config_ctl_val = 0x200d4828, + .config_ctl_hi_val = 0x6, + .config_ctl_hi1_val = 0x00000000, + .test_ctl_val = 0x1c000000, + .test_ctl_hi_val = 0x00004000, + .test_ctl_hi1_val = 0x00000000, + .user_ctl_val = 0xf, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .config = &gpu_cc_pll0_config, + .vco_table = huayra_vco, + .num_vco = ARRAY_SIZE(huayra_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL0_OUT_AUX, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(537600000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1142400000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = { + .halt_reg = 0x10a8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_gfx3d_slv_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gpu_smmu_vote_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gpu_smmu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gpu_cc_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gpu_cc_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_CC_GX_BCR }, + .reset_count = 1, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gpu_cc_gx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | SW_RESET | CLAMP_IO | AON_RESET, +}; + +static struct clk_regmap *gpu_cc_shikra_clocks[] = { + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GPU_SMMU_VOTE_CLK] = &gpu_cc_gpu_smmu_vote_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, +}; + +static struct gdsc *gpu_cc_shikra_gdscs[] = { + [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, + [GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_shikra_resets[] = { + [GPU_CC_CX_BCR] = { 0x1068 }, + [GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, + [GPU_CC_GMU_BCR] = { 0x111c }, + [GPU_CC_GX_BCR] = { 0x1008 }, + [GPU_CC_XO_BCR] = { 0x1000 }, +}; + +static struct clk_alpha_pll *gpu_cc_shikra_plls[] = { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_shikra_critical_cbcrs[] = { + 0x1078, /* GPU_CC_AHB_CLK */ + 0x1004, /* GPU_CC_CXO_AON_CLK */ + 0x1060, /* GPU_CC_GX_CXO_CLK */ +}; + +static const struct regmap_config gpu_cc_shikra_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x7008, + .fast_io = true, +}; + +static struct qcom_cc_driver_data gpu_cc_shikra_driver_data = { + .alpha_plls = gpu_cc_shikra_plls, + .num_alpha_plls = ARRAY_SIZE(gpu_cc_shikra_plls), + .clk_cbcrs = gpu_cc_shikra_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_shikra_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_shikra_desc = { + .config = &gpu_cc_shikra_regmap_config, + .clks = gpu_cc_shikra_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_shikra_clocks), + .resets = gpu_cc_shikra_resets, + .num_resets = ARRAY_SIZE(gpu_cc_shikra_resets), + .gdscs = gpu_cc_shikra_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_shikra_gdscs), + .driver_data = &gpu_cc_shikra_driver_data, +}; + +static const struct of_device_id gpu_cc_shikra_match_table[] = { + { .compatible = "qcom,shikra-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_shikra_match_table); + +static int gpu_cc_shikra_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_shikra_desc); +} + +static struct platform_driver gpu_cc_shikra_driver = { + .probe = gpu_cc_shikra_probe, + .driver = { + .name = "gpucc-shikra", + .of_match_table = gpu_cc_shikra_match_table, + }, +}; + +module_platform_driver(gpu_cc_shikra_driver); + +MODULE_DESCRIPTION("QTI GPUCC Shikra Driver"); +MODULE_LICENSE("GPL"); From 240e3a58f06746e072e4439c0ea101e1ac50a890 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 16 Apr 2026 13:31:00 +0530 Subject: [PATCH 0878/1330] arm64: defconfig: Enable DISPCC and GPUCC on Shikra EVK boards Enable the DISPCC and GPUCC drivers on the Qualcomm Shikra EVK boards. Signed-off-by: Imran Shaik (cherry picked from commit a8f9b0ac5e5adaefa3d2c11deed4d012acabb507) --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 297b7456c5040..1eb25e4b3cf92 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1448,7 +1448,9 @@ CONFIG_CLK_IMX8QXP=y CONFIG_CLK_IMX8ULP=y CONFIG_CLK_IMX93=y CONFIG_CLK_IMX95_BLK_CTL=y +CONFIG_CLK_SHIKRA_DISPCC=y CONFIG_CLK_SHIKRA_GCC=y +CONFIG_CLK_SHIKRA_GPUCC=y CONFIG_TI_SCI_CLK=y CONFIG_COMMON_CLK_MT8192_AUDSYS=y CONFIG_COMMON_CLK_MT8192_CAMSYS=y From cce2dd13313f7db34b63fe61b1d58c3fbb46452c Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 15 Apr 2026 14:48:27 +0530 Subject: [PATCH 0879/1330] pinctrl: qcom: Add GPIO-MPM map for shikra Map the wakeup capable GPIOs to respective MPM pins for shikra. Signed-off-by: Sneh Mankad (cherry picked from commit 049c32f28ba81d7545f2b873712e6cb0a82eaccf) --- drivers/pinctrl/qcom/pinctrl-shikra.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c index d1ea0bb0dc41f..b9253b0f0755e 100644 --- a/drivers/pinctrl/qcom/pinctrl-shikra.c +++ b/drivers/pinctrl/qcom/pinctrl-shikra.c @@ -1724,8 +1724,19 @@ static const struct msm_pingroup shikra_groups[] = { [168] = SDC_QDSD_PINGROUP(sdc2_data, 0x1AA000, 9, 0), }; -static const struct msm_gpio_wakeirq_map shikra_pdc_map[] = { - +static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = { + {1, 9}, {2, 31}, {5, 49}, {6, 53}, {9, 72}, {10, 10}, + {12, 22}, {14, 26}, {17, 29}, {18, 24}, {20, 32}, {22, 33}, + {25, 34}, {27, 35}, {28, 36}, {29, 37}, {30, 38}, {31, 39}, + {32, 40}, {33, 41}, {38, 42}, {40, 43}, {43, 44}, {44, 45}, + {45, 46}, {46, 47}, {47, 48}, {48, 60}, {50, 50}, {51, 51}, + {52, 61}, {53, 62}, {57, 52}, {58, 63}, {60, 54}, {63, 64}, + {73, 55}, {74, 56}, {75, 57}, {77, 3}, {80, 4}, {84, 5}, + {85, 67}, {86, 69}, {88, 70}, {89, 71}, {90, 73}, {91, 74}, + {92, 75}, {93, 76}, {94, 77}, {95, 78}, {97, 79}, {99, 80}, + {100, 11}, {101, 13}, {102, 14}, {103, 15}, {106, 16}, {108, 17}, + {112, 18}, {116, 19}, {117, 20}, {119, 21}, {120, 23}, {136, 25}, + {159, 27}, {161, 28}, }; static const struct msm_pinctrl_soc_data shikra_tlmm = { @@ -1736,8 +1747,8 @@ static const struct msm_pinctrl_soc_data shikra_tlmm = { .groups = shikra_groups, .ngroups = ARRAY_SIZE(shikra_groups), .ngpios = 166, - .wakeirq_map = shikra_pdc_map, - .nwakeirq_map = ARRAY_SIZE(shikra_pdc_map), + .wakeirq_map = shikra_mpm_map, + .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map), .egpio_func = 11, }; From 6c2acdbefc314c84af4cf4ebf663ec291c9e6c7c Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 22 Apr 2026 16:34:16 +0530 Subject: [PATCH 0880/1330] interconnect: qcom: shikra: program QoS mode for ICC masters Set `qos_mode` on Shikra interconnect master nodes and mark ap-owned masters with `ap_owned` where missing. This enables correct QoS register programming (fixed or bypass mode) for the defined QoS ports. Signed-off-by: Raviteja Laggyshetty (cherry picked from commit bfd73186712f4242c75676cf0ce3296786cf0e46) --- drivers/interconnect/qcom/shikra.c | 33 ++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/interconnect/qcom/shikra.c b/drivers/interconnect/qcom/shikra.c index 30a9a5b10db86..5bf796100904f 100644 --- a/drivers/interconnect/qcom/shikra.c +++ b/drivers/interconnect/qcom/shikra.c @@ -300,6 +300,7 @@ static struct qcom_icc_node qnm_gpu = { .qos.ap_owned = true, .qos.qos_port = 6, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 0, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -320,6 +321,7 @@ static struct qcom_icc_node qnm_mnoc_hf = { .qos.ap_owned = true, .qos.qos_port = 7, .qos.urg_fwd_en = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, .qos.areq_prio = 0, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -336,8 +338,10 @@ static struct qcom_icc_node qnm_pcie = { .id = SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, .name = "qnm_pcie", .buswidth = 8, + .qos.ap_owned = true, .qos.qos_port = 4, .qos.urg_fwd_en = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, .qos.areq_prio = 0, .mas_rpm_id = 185, .slv_rpm_id = -1, @@ -355,8 +359,10 @@ static struct qcom_icc_node qnm_snoc_sf = { .id = SHIKRA_MASTER_SNOC_SF_MEM_NOC, .name = "qnm_snoc_sf", .buswidth = 16, + .qos.ap_owned = true, .qos.qos_port = 3, .qos.urg_fwd_en = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, .qos.areq_prio = 0, .mas_rpm_id = 76, .slv_rpm_id = -1, @@ -374,8 +380,10 @@ static struct qcom_icc_node xm_apps = { .id = SHIKRA_MASTER_AMPSS_M0, .name = "xm_apps", .buswidth = 16, + .qos.ap_owned = true, .qos.qos_port = 5, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 0, .mas_rpm_id = 0, .slv_rpm_id = -1, @@ -395,6 +403,7 @@ static struct qcom_icc_node xm_tcu = { .qos.ap_owned = true, .qos.qos_port = 2, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 6, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -413,6 +422,7 @@ static struct qcom_icc_node qnm_camera_nrt = { .qos.ap_owned = true, .qos.qos_port = 3, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 3, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -431,6 +441,7 @@ static struct qcom_icc_node qxm_venus0 = { .qos.ap_owned = true, .qos.qos_port = 8, .qos.urg_fwd_en = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, .qos.areq_prio = 0, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -449,6 +460,7 @@ static struct qcom_icc_node qxm_venus_cpu = { .qos.ap_owned = true, .qos.qos_port = 12, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 4, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -467,6 +479,7 @@ static struct qcom_icc_node qnm_camera_rt = { .qos.ap_owned = true, .qos.qos_port = 9, .qos.urg_fwd_en = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, .qos.areq_prio = 0, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -485,6 +498,7 @@ static struct qcom_icc_node qxm_mdp0 = { .qos.ap_owned = true, .qos.qos_port = 4, .qos.urg_fwd_en = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, .qos.areq_prio = 0, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -605,6 +619,7 @@ static struct qcom_icc_node qxm_pimem = { .qos.ap_owned = true, .qos.qos_port = 14, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -620,8 +635,10 @@ static struct qcom_icc_node xm_pcie2_0 = { .id = SHIKRA_MASTER_PCIE2_0, .name = "xm_pcie2_0", .buswidth = 8, + .qos.ap_owned = true, .qos.qos_port = 21, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = 186, .slv_rpm_id = -1, @@ -640,6 +657,7 @@ static struct qcom_icc_node qhm_qdss_bam = { .qos.ap_owned = true, .qos.qos_port = 2, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -658,6 +676,7 @@ static struct qcom_icc_node qhm_qpic = { .qos.ap_owned = true, .qos.qos_port = 1, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -673,8 +692,10 @@ static struct qcom_icc_node qhm_qup0 = { .id = SHIKRA_MASTER_QUP_0, .name = "qhm_qup0", .buswidth = 4, + .qos.ap_owned = true, .qos.qos_port = 0, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = 166, .slv_rpm_id = -1, @@ -693,6 +714,7 @@ static struct qcom_icc_node qnm_cnoc_snoc = { .qos.ap_owned = true, .qos.qos_port = 7, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -708,8 +730,10 @@ static struct qcom_icc_node qxm_audio = { .id = SHIKRA_MASTER_AUDIO, .name = "qxm_audio", .buswidth = 8, + .qos.ap_owned = true, .qos.qos_port = 22, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 3, .mas_rpm_id = 78, .slv_rpm_id = -1, @@ -728,6 +752,7 @@ static struct qcom_icc_node xm_emac_0 = { .qos.ap_owned = true, .qos.qos_port = 19, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -746,6 +771,7 @@ static struct qcom_icc_node xm_emac_1 = { .qos.ap_owned = true, .qos.qos_port = 20, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -764,6 +790,7 @@ static struct qcom_icc_node xm_qdss_etr = { .qos.ap_owned = true, .qos.qos_port = 11, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -782,6 +809,7 @@ static struct qcom_icc_node xm_sdc1 = { .qos.ap_owned = true, .qos.qos_port = 13, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -800,6 +828,7 @@ static struct qcom_icc_node xm_sdc2 = { .qos.ap_owned = true, .qos.qos_port = 17, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -818,6 +847,7 @@ static struct qcom_icc_node xm_usb2_0 = { .qos.ap_owned = true, .qos.qos_port = 24, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -836,6 +866,7 @@ static struct qcom_icc_node xm_usb3_0 = { .qos.ap_owned = true, .qos.qos_port = 18, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = -1, .slv_rpm_id = -1, @@ -851,8 +882,10 @@ static struct qcom_icc_node crypto_c0 = { .id = SHIKRA_MASTER_CRYPTO_CORE0, .name = "crypto_c0", .buswidth = 8, + .qos.ap_owned = true, .qos.qos_port = 16, .qos.urg_fwd_en = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.areq_prio = 2, .mas_rpm_id = 23, .slv_rpm_id = -1, From 8d37b45870d95cd314a27c4ac60d051cfc619a73 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 24 Apr 2026 16:18:11 +0530 Subject: [PATCH 0881/1330] dt-bindings: cache: qcom,llcc: Document Qualcomm Shikra LLCC Document the Last Level Cache Controller on Shikra SoC. Signed-off-by: Komal Bajaj (cherry picked from commit d9b91090fc568028ced20e33cb8d514882ffb91b) --- Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 6671e461e34ab..69a75e180a24d 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -34,6 +34,7 @@ properties: - qcom,sc8180x-llcc - qcom,sc8280xp-llcc - qcom,sdm845-llcc + - qcom,shikra-llcc - qcom,sm6350-llcc - qcom,sm7150-llcc - qcom,sm8150-llcc @@ -204,6 +205,8 @@ allOf: contains: enum: - qcom,sc7280-llcc + - qcom,sdm670-llcc + - qcom,shikra-llcc then: properties: reg: From f17dc240019502cdc7c6af930a83a2dce73ef32d Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 23 Apr 2026 16:25:41 +0530 Subject: [PATCH 0882/1330] FROMLIST: soc: qcom: smem: Switch partitions to xarray The partitions array is currently statically sized and uses the remote host ID as an index. Future protocol improvements to allow for more than two hosts in a partition will require hostIDs to be bitwise significant integers. This will result in large, sparse host IDs that generally exceed the current static limit. Switch to using xarray to efficiently handle these sparse indices and allow for dynamic growth. Signed-off-by: Tony Truong Tested-by: Shawn Guo # On Nord Tested-by: Konrad Dybcio # Glymur CRD Reviewed-by: Konrad Dybcio Signed-off-by: Pranav Mahesh Phansalkar Link: https://lore.kernel.org/r/20260423-smem-v3-1-582befff289a@oss.qualcomm.com (cherry picked from commit 373936195553e4a9262982bf6a70346ea3407d35) --- drivers/soc/qcom/smem.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 4315512d3a1d4..95afeaa00066e 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -284,8 +284,6 @@ struct qcom_smem { struct smem_partition global_partition; struct xarray partitions; - struct dentry *debugfs_dir; - unsigned num_regions; struct smem_region regions[] __counted_by(num_regions); }; From 7aa3eb137a6641c67008187a875a97a103c32107 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Thu, 30 Apr 2026 14:50:07 +0530 Subject: [PATCH 0883/1330] FROMLIST: pinctrl: qcom: Unconditionally mark gpio as wakeup enable The wakeup enable bit needs to be set irrespective of the SoC using PDC or MPM as wakeup capable irqchip to allow the GPIO interrupts to be forwarded to parent irqchip. This is set only for PDC irqchip using additional check skip_wake_irqs making it impossible for MPM irqchip to detect the GPIO interrupt during SoC low power mode since for MPM irqchip the skip_wake_irqs is always false. Remove skip_wake_irqs condition when setting wakeup enable bit to allow forwarding GPIO interrupts for SoCs using MPM irqchip too. Fixes: 76b446f5b86e ("pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits") Signed-off-by: Sneh Mankad Reviewed-by: Maulik Shah Link: https://lore.kernel.org/r/20260430-enable_wakeup_capable_gpios-v2-1-8c26ac795318@oss.qualcomm.com (cherry picked from commit cbc9c348528193cd2c445e75ed2429d83c50e7b5) --- drivers/pinctrl/qcom/pinctrl-msm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index e99871b90ab9c..424b14bc29e96 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1226,12 +1226,12 @@ static int msm_gpio_irq_reqres(struct irq_data *d) /* * If the wakeup_enable bit is present and marked as available for the * requested GPIO, it should be enabled when the GPIO is marked as - * wake irq in order to allow the interrupt event to be transfered to - * the PDC HW. + * wake irq in order to allow the interrupt event to be transferred to + * the PDC/MPM HW. * While the name implies only the wakeup event, it's also required for * the interrupt event. */ - if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { + if (g->intr_wakeup_present_bit) { u32 intr_cfg; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -1259,7 +1259,7 @@ static void msm_gpio_irq_relres(struct irq_data *d) unsigned long flags; /* Disable the wakeup_enable bit if it has been set in msm_gpio_irq_reqres() */ - if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { + if (g->intr_wakeup_present_bit) { u32 intr_cfg; raw_spin_lock_irqsave(&pctrl->lock, flags); From f2e501b2f5d4f9bb5e2e3edd4798b406805a9f53 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 21 Apr 2026 02:07:25 +0530 Subject: [PATCH 0884/1330] remoteproc: qcom: pas: Add Shikra remoteproc support Add DSP and lpaicp Peripheral Authentication Service support for the Shikra platform. Signed-off-by: Bibek Kumar Patro (cherry picked from commit 310e46fea2aacf0508e0458d0c6b96d8a35fa1f1) --- drivers/remoteproc/qcom_q6v5_pas.c | 76 +++++++++++++++++++++++++----- 1 file changed, 63 insertions(+), 13 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index ee0544449ba78..d6ab12e456725 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -1577,6 +1577,55 @@ static const struct qcom_pas_data sc7280_wpss_resource = { .ssctl_id = 0x19, }; +static const struct qcom_pas_data shikra_cdsp_resource = { + .crash_reason_smem = 601, + .firmware_name = "cdsp.mbn", + .pas_id = 18, + .minidump_id = 7, + .auto_boot = false, + .proxy_pd_names = (char *[]){ + "cx", + NULL + }, + .load_state = "cdsp", + .ssr_name = "cdsp", + .sysmon_name = "cdsp", + .ssctl_id = 0x17, + .smem_host_id = 5, + .region_assign_vmid = QCOM_SCM_VMID_CDSP, +}; + +static const struct qcom_pas_data shikra_lpaicp_resource = { + .crash_reason_smem = 682, + .firmware_name = "lpaicp.mbn", + .dtb_firmware_name = "lpaicp_dtb.mbn", + .pas_id = 0x56, + .dtb_pas_id = 0x57, + /* placeholder for lpaicp subsystem dump collection id to be added */ + .minidump_id = 0, + .auto_boot = true, + .ssr_name = "lpaicp", + .sysmon_name = "lpaicp", +}; + +static const struct qcom_pas_data shikra_mpss_resource = { + .crash_reason_smem = 421, + .firmware_name = "qdsp6sw.mbn", + .pas_id = 4, + .minidump_id = 3, + .auto_boot = false, + .decrypt_shutdown = true, + .proxy_pd_names = (char *[]){ + "cx", + NULL + }, + .load_state = "modem", + .ssr_name = "mpss", + .sysmon_name = "modem", + .ssctl_id = 0x12, + .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA, +}; + static const struct qcom_pas_data sm8650_cdsp_resource = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", @@ -1668,19 +1717,17 @@ static const struct qcom_pas_data kaanapali_soccp_resource = { }; static const struct of_device_id qcom_pas_of_match[] = { - { .compatible = "qcom,eliza-adsp-pas", .data = &sm8550_adsp_resource }, - { .compatible = "qcom,kaanapali-soccp-pas", .data = &kaanapali_soccp_resource }, - { .compatible = "qcom,milos-adsp-pas", .data = &sm8550_adsp_resource }, - { .compatible = "qcom,milos-cdsp-pas", .data = &milos_cdsp_resource }, - { .compatible = "qcom,milos-mpss-pas", .data = &sm8450_mpss_resource }, - { .compatible = "qcom,milos-wpss-pas", .data = &sc7280_wpss_resource }, - { .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource }, - { .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource }, - { .compatible = "qcom,msm8974-adsp-pil", .data = &msm8996_adsp_resource }, - { .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource }, - { .compatible = "qcom,msm8996-slpi-pil", .data = &msm8996_slpi_resource_init }, - { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8996_adsp_resource }, - { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8996_slpi_resource_init }, + { .compatible = "qcom,milos-adsp-pas", .data = &sm8550_adsp_resource}, + { .compatible = "qcom,milos-cdsp-pas", .data = &milos_cdsp_resource}, + { .compatible = "qcom,milos-mpss-pas", .data = &sm8450_mpss_resource}, + { .compatible = "qcom,milos-wpss-pas", .data = &sc7280_wpss_resource}, + { .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource}, + { .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource}, + { .compatible = "qcom,msm8974-adsp-pil", .data = &msm8996_adsp_resource}, + { .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource}, + { .compatible = "qcom,msm8996-slpi-pil", .data = &msm8996_slpi_resource_init}, + { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8996_adsp_resource}, + { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8996_slpi_resource_init}, { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init }, { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init }, { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init }, @@ -1709,6 +1756,9 @@ static const struct of_device_id qcom_pas_of_match[] = { { .compatible = "qcom,sdm845-slpi-pas", .data = &sdm845_slpi_resource_init}, { .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource}, { .compatible = "qcom,sdx75-mpss-pas", .data = &sm8650_mpss_resource}, + { .compatible = "qcom,shikra-cdsp-pas", .data = &shikra_cdsp_resource }, + { .compatible = "qcom,shikra-lpaicp-pas", .data = &shikra_lpaicp_resource }, + { .compatible = "qcom,shikra-mpss-pas", .data = &shikra_mpss_resource }, { .compatible = "qcom,sm6115-adsp-pas", .data = &adsp_resource_init}, { .compatible = "qcom,sm6115-cdsp-pas", .data = &cdsp_resource_init}, { .compatible = "qcom,sm6115-mpss-pas", .data = &sc8180x_mpss_resource}, From 72910dc5de889dc16c99360e521c264992af3505 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Mon, 20 Apr 2026 14:28:10 +0530 Subject: [PATCH 0885/1330] dt-bindings: remoteproc: qcom: Add Shikra PAS binding Add devicetree binding documentation for the Qualcomm Shikra SoC Peripheral Authentication Service (PAS) remoteproc nodes. Signed-off-by: Bibek Kumar Patro (cherry picked from commit 527e287025beab1ce61f54346fd2926639d7174f) --- .../bindings/remoteproc/qcom,shikra-pas.yaml | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml new file mode 100644 index 0000000000000..f4ec101a35894 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,shikra-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra SoC Peripheral Authentication Service + +maintainers: + - Bibek Kumar Patro + - Komal Bajaj + +description: + Qualcomm Shikra SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,shikra-cdsp-pas + - qcom,shikra-lpaicp-pas + - qcom,shikra-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + memory-region: + minItems: 1 + maxItems: 2 + + smd-edge: false + + firmware-name: + minItems: 1 + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + +required: + - compatible + - reg + - memory-region + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + + - if: + properties: + compatible: + enum: + - qcom,shikra-cdsp-pas + - qcom,shikra-mpss-pas + then: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + maxItems: 1 + firmware-name: + maxItems: 1 + power-domains: + items: + - description: CX power domain + power-domain-names: + items: + - const: cx + + - if: + properties: + compatible: + enum: + - qcom,shikra-lpaicp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + minItems: 2 + firmware-name: + minItems: 2 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + remoteproc@b300000 { + compatible = "qcom,shikra-cdsp-pas"; + reg = <0x0b300000 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + power-domain-names = "cx"; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 4>; + qcom,remote-pid = <5>; + label = "cdsp"; + }; + }; From cd5efa6e3ce1be1b2e7370ccf847177d3d5f3885 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Tue, 5 May 2026 16:22:30 +0530 Subject: [PATCH 0886/1330] dt-bindings: clock: qcom: Add GCC_QUSB2PHY_SEC_BCR support for Shikra Add GCC_QUSB2PHY_SEC_BCR reset support for Shikra platform. Signed-off-by: Imran Shaik (cherry picked from commit e3fe14f5aa88bd1c4df778c3563c71802bd3986a) --- include/dt-bindings/clock/qcom,shikra-gcc.h | 23 +++++++++++---------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/include/dt-bindings/clock/qcom,shikra-gcc.h b/include/dt-bindings/clock/qcom,shikra-gcc.h index 77c6159755ce9..2e88a9cd9f535 100644 --- a/include/dt-bindings/clock/qcom,shikra-gcc.h +++ b/include/dt-bindings/clock/qcom,shikra-gcc.h @@ -243,16 +243,17 @@ #define GCC_PDM_BCR 9 #define GCC_QUPV3_WRAPPER_0_BCR 10 #define GCC_QUSB2PHY_PRIM_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_TSCSS_BCR 14 -#define GCC_USB20_BCR 15 -#define GCC_USB30_PRIM_BCR 16 -#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 17 -#define GCC_USB3_PHY_PRIM_SP0_BCR 18 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 19 -#define GCC_VCODEC0_BCR 20 -#define GCC_VENUS_BCR 21 -#define GCC_VIDEO_INTERFACE_BCR 22 +#define GCC_QUSB2PHY_SEC_BCR 12 +#define GCC_SDCC1_BCR 13 +#define GCC_SDCC2_BCR 14 +#define GCC_TSCSS_BCR 15 +#define GCC_USB20_BCR 16 +#define GCC_USB30_PRIM_BCR 17 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 18 +#define GCC_USB3_PHY_PRIM_SP0_BCR 19 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 20 +#define GCC_VCODEC0_BCR 21 +#define GCC_VENUS_BCR 22 +#define GCC_VIDEO_INTERFACE_BCR 23 #endif From 4ae4e7f35bcb3fa9ecdf83daa72a500d73b6029c Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Tue, 5 May 2026 16:24:13 +0530 Subject: [PATCH 0887/1330] clk: qcom: gcc-shikra: Update GCC driver for Shikra Add GCC_QUSB2PHY_SEC_BCR reset support for Shikra. While at it, drop the flags which are not required for the fixed parent clocks. Signed-off-by: Imran Shaik (cherry picked from commit c786641163b7a58d9666eecd16aec8e0b1961198) --- drivers/clk/qcom/gcc-shikra.c | 114 +++++++++------------------------- 1 file changed, 29 insertions(+), 85 deletions(-) diff --git a/drivers/clk/qcom/gcc-shikra.c b/drivers/clk/qcom/gcc-shikra.c index 3ca5ed7cd48a1..8834618354882 100644 --- a/drivers/clk/qcom/gcc-shikra.c +++ b/drivers/clk/qcom/gcc-shikra.c @@ -68,9 +68,12 @@ static const struct pll_vco brammo_vco[] = { { 500000000, 1250000000, 0 }, }; +static const struct pll_vco default_vco[] = { + { 500000000, 1000000000, 2 }, +}; + static const struct pll_vco spark_vco[] = { { 750000000, 1500000000, 1 }, - { 500000000, 1000000000, 2 }, }; static struct clk_alpha_pll gpll0 = { @@ -112,23 +115,6 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { }, }; -static struct clk_alpha_pll gpll1 = { - .offset = 0x1000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], - .clkr = { - .enable_reg = 0x79000, - .enable_mask = BIT(1), - .hw.init = &(const struct clk_init_data) { - .name = "gpll1", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_ops, - }, - }, -}; - /* 1152.0 MHz Configuration */ static const struct alpha_pll_config gpll10_config = { .l = 0x3c, @@ -176,9 +162,10 @@ static const struct alpha_pll_config gpll11_config = { static struct clk_alpha_pll gpll11 = { .offset = 0xb000, .config = &gpll11_config, - .vco_table = spark_vco, - .num_vco = ARRAY_SIZE(spark_vco), + .vco_table = default_vco, + .num_vco = ARRAY_SIZE(default_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .flags = SUPPORTS_DYNAMIC_UPDATE, .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(11), @@ -380,9 +367,10 @@ static const struct alpha_pll_config gpll8_config = { static struct clk_alpha_pll gpll8 = { .offset = 0x8000, .config = &gpll8_config, - .vco_table = spark_vco, - .num_vco = ARRAY_SIZE(spark_vco), + .vco_table = default_vco, + .num_vco = ARRAY_SIZE(default_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .flags = SUPPORTS_DYNAMIC_UPDATE, .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(8), @@ -464,9 +452,9 @@ static struct clk_alpha_pll_postdiv gpll9_out_main = { .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), .width = 2, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], - .clkr.hw.init = &(const struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll9_out_main", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll9.clkr.hw, }, .num_parents = 1, @@ -529,7 +517,7 @@ static const struct clk_parent_data gcc_parent_data_3[] = { { .hw = &gpll0.clkr.hw }, { .hw = &gpll9.clkr.hw }, { .hw = &gpll10.clkr.hw }, - { .hw = &gpll9.clkr.hw }, + { .hw = &gpll9_out_main.clkr.hw }, { .hw = &gpll3_out_main.clkr.hw }, }; @@ -874,7 +862,6 @@ static struct clk_rcg2 gcc_camss_axi_clk_src = { .name = "gcc_camss_axi_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -896,7 +883,6 @@ static struct clk_rcg2 gcc_camss_cci_clk_src = { .name = "gcc_camss_cci_clk_src", .parent_data = gcc_parent_data_14, .num_parents = ARRAY_SIZE(gcc_parent_data_14), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -920,7 +906,6 @@ static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { .name = "gcc_camss_csi0phytimer_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -936,7 +921,6 @@ static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { .name = "gcc_camss_csi1phytimer_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1030,7 +1014,6 @@ static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { .name = "gcc_camss_ope_ahb_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1117,7 +1100,6 @@ static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { .name = "gcc_camss_tfe_0_csid_clk_src", .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1133,7 +1115,6 @@ static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { .name = "gcc_camss_tfe_1_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1149,7 +1130,6 @@ static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { .name = "gcc_camss_tfe_1_csid_clk_src", .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1173,7 +1153,6 @@ static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { .name = "gcc_camss_tfe_cphy_rx_clk_src", .parent_data = gcc_parent_data_15, .num_parents = ARRAY_SIZE(gcc_parent_data_15), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1196,7 +1175,6 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { .name = "gcc_camss_top_ahb_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1221,7 +1199,6 @@ static struct clk_rcg2 gcc_emac0_axi_clk_src = { .name = "gcc_emac0_axi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1242,7 +1219,6 @@ static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = { .name = "gcc_emac0_phy_aux_clk_src", .parent_data = gcc_parent_data_10, .num_parents = ARRAY_SIZE(gcc_parent_data_10), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1263,7 +1239,6 @@ static struct clk_rcg2 gcc_emac0_ptp_clk_src = { .name = "gcc_emac0_ptp_clk_src", .parent_data = gcc_parent_data_11, .num_parents = ARRAY_SIZE(gcc_parent_data_11), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1286,7 +1261,6 @@ static struct clk_rcg2 gcc_emac0_rgmii_clk_src = { .name = "gcc_emac0_rgmii_clk_src", .parent_data = gcc_parent_data_12, .num_parents = ARRAY_SIZE(gcc_parent_data_12), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1302,7 +1276,6 @@ static struct clk_rcg2 gcc_emac1_axi_clk_src = { .name = "gcc_emac1_axi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1318,7 +1291,6 @@ static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = { .name = "gcc_emac1_phy_aux_clk_src", .parent_data = gcc_parent_data_10, .num_parents = ARRAY_SIZE(gcc_parent_data_10), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1334,7 +1306,6 @@ static struct clk_rcg2 gcc_emac1_ptp_clk_src = { .name = "gcc_emac1_ptp_clk_src", .parent_data = gcc_parent_data_11, .num_parents = ARRAY_SIZE(gcc_parent_data_11), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1350,7 +1321,6 @@ static struct clk_rcg2 gcc_emac1_rgmii_clk_src = { .name = "gcc_emac1_rgmii_clk_src", .parent_data = gcc_parent_data_12, .num_parents = ARRAY_SIZE(gcc_parent_data_12), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1374,7 +1344,6 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1390,7 +1359,6 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1406,7 +1374,6 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1422,7 +1389,6 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = { .name = "gcc_pcie_aux_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1438,7 +1404,6 @@ static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { .name = "gcc_pcie_aux_phy_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1459,7 +1424,6 @@ static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = { .name = "gcc_pcie_rchng_phy_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1481,7 +1445,6 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1510,7 +1473,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1528,7 +1490,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1546,7 +1507,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1564,7 +1524,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1582,7 +1541,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1600,7 +1558,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1618,7 +1575,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1636,7 +1592,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1654,7 +1609,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s8_clk_src_init = { .name = "gcc_qupv3_wrap0_s8_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1672,7 +1626,6 @@ static struct clk_init_data gcc_qupv3_wrap0_s9_clk_src_init = { .name = "gcc_qupv3_wrap0_s9_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }; @@ -1709,7 +1662,6 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_floor_ops, }, }; @@ -1734,7 +1686,6 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_floor_ops, }, }; @@ -1760,7 +1711,6 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_21, .num_parents = ARRAY_SIZE(gcc_parent_data_21), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_floor_ops, }, }; @@ -1776,7 +1726,6 @@ static struct clk_rcg2 gcc_tscss_clk_src = { .name = "gcc_tscss_clk_src", .parent_data = gcc_parent_data_22, .num_parents = ARRAY_SIZE(gcc_parent_data_22), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1798,7 +1747,6 @@ static struct clk_rcg2 gcc_usb20_master_clk_src = { .name = "gcc_usb20_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1814,7 +1762,6 @@ static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { .name = "gcc_usb20_mock_utmi_clk_src", .parent_data = gcc_parent_data_13, .num_parents = ARRAY_SIZE(gcc_parent_data_13), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1838,7 +1785,6 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1854,7 +1800,6 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1870,7 +1815,6 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, }; @@ -1899,6 +1843,20 @@ static struct clk_rcg2 gcc_video_venus_clk_src = { }, }; +static struct clk_regmap_div gcc_disp_gpll0_clk_src = { + .reg = 0x17058, + .shift = 0, + .width = 2, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_disp_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { .reg = 0xb0038, .shift = 0, @@ -2487,20 +2445,6 @@ static struct clk_branch gcc_ddrss_memnoc_pcie_sf_clk = { }, }; -static struct clk_regmap_div gcc_disp_gpll0_clk_src = { - .reg = 0x17058, - .shift = 0, - .width = 2, - .clkr.hw.init = &(struct clk_init_data) { - .name = "gcc_disp_gpll0_clk_src", - .parent_hws = (const struct clk_hw*[]){ - &gpll0.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - }, -}; - static struct clk_branch gcc_disp_gpll0_div_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -4334,7 +4278,6 @@ static struct clk_regmap *gcc_shikra_clocks[] = { [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, [GPLL0] = &gpll0.clkr, [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, - [GPLL1] = &gpll1.clkr, [GPLL10] = &gpll10.clkr, [GPLL11] = &gpll11.clkr, [GPLL12] = &gpll12.clkr, @@ -4376,6 +4319,7 @@ static const struct qcom_reset_map gcc_shikra_resets[] = { [GCC_PDM_BCR] = { 0x20000 }, [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, [GCC_SDCC1_BCR] = { 0x38000 }, [GCC_SDCC2_BCR] = { 0x1e000 }, [GCC_TSCSS_BCR] = { 0xac000 }, @@ -4480,5 +4424,5 @@ static void __exit gcc_shikra_exit(void) } module_exit(gcc_shikra_exit); -MODULE_DESCRIPTION("QTI GCC SHIKRA Driver"); +MODULE_DESCRIPTION("QTI GCC Shikra Driver"); MODULE_LICENSE("GPL"); From 072b7261f12baed4dd3ace7525ccbe2cfd2d22a2 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Tue, 5 May 2026 16:31:00 +0530 Subject: [PATCH 0888/1330] clk: qcom: gpucc-shikra: Drop unused DT_BI_TCXO_AO index Remove the unused enum entry to keep the binding indices aligned with device tree. Signed-off-by: Imran Shaik (cherry picked from commit 7d82c0719756d380a87761fe4c190b0001c6ca02) --- drivers/clk/qcom/gpucc-shikra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-shikra.c b/drivers/clk/qcom/gpucc-shikra.c index 19a938a14d68d..4ad4fc0b6703a 100644 --- a/drivers/clk/qcom/gpucc-shikra.c +++ b/drivers/clk/qcom/gpucc-shikra.c @@ -24,7 +24,6 @@ enum { DT_BI_TCXO, - DT_BI_TCXO_AO, DT_GPLL0_OUT_MAIN, DT_GPLL0_OUT_MAIN_DIV, }; From 2bd74dffc7d40c772126465e14c55eaca3ccd5ed Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Wed, 22 Apr 2026 15:01:50 +0800 Subject: [PATCH 0889/1330] FROMLIST: wifi: ath12k: fix memory leak in ath12k_wifi7_dp_rx_h_verify_tkip_mic() In ath12k_wifi7_dp_rx_h_verify_tkip_mic(), the call to ath12k_dp_rx_check_nwifi_hdr_len_valid() may return false when the NWIFI header length is invalid, causing the function to abort early with -EINVAL. When this happens, the error propagates to ath12k_wifi7_dp_rx_h_defrag(), which clears first_frag by setting it to NULL. As a result, the corresponding MSDU is no longer referenced by the defragmentation path and is never freed. This leads to a memory leak for the affected MSDU on this error path. Proper cleanup is required to ensure the MSDU is released when header validation fails during TKIP MIC verification. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: 9a0dddfb30f1 ("wifi: ath12k: Fix invalid data access in ath12k_dp_rx_h_undecap_nwifi") Signed-off-by: Miaoqing Pan Link: https://lore.kernel.org/linux-wireless/20260512021108.2031651-1-miaoqing.pan@oss.qualcomm.com/ (cherry picked from commit f5b9e96d3c301935f7387e5ae2edb95e29ad203b) --- drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c b/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c index 038e339e8fb1c..0407536c92cd5 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c @@ -1030,9 +1030,11 @@ static int ath12k_wifi7_dp_rx_h_verify_tkip_mic(struct ath12k_pdev_dp *dp_pdev, RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; skb_pull(msdu, hal_rx_desc_sz); - if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(dp, rx_desc, msdu, - rx_info))) + if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(dp, msdu, + rx_info))) { + dev_kfree_skb_any(msdu); return -EINVAL; + } ath12k_dp_rx_h_ppdu(dp_pdev, rx_info); ath12k_dp_rx_h_undecap(dp_pdev, msdu, rx_desc, From 38d78bd8a662753de200a19b8dd568146beb8ab3 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Mon, 13 Apr 2026 14:31:35 +0800 Subject: [PATCH 0890/1330] FROMLIST: wifi: ath11k: fix invalid data access in ath11k_dp_rx_h_undecap_nwifi In certain cases, hardware might provide packets with a length greater than the maximum native Wi-Fi header length. This can lead to accessing and modifying fields in the header within the ath11k_dp_rx_h_undecap_nwifi() function for the DP_RX_DECAP_TYPE_NATIVE_WIFI decap type and potentially result in invalid data access and memory corruption. Kernel stack is corrupted in: ath11k_dp_rx_h_undecap+0x6b0/0x6b0 [ath11k] Call trace: ath11k_dp_rx_h_mpdu+0x0/0x2e8 [ath11k] ath11k_dp_rx_h_mpdu+0x1e0/0x2e8 [ath11k] ath11k_dp_rx_wbm_err+0x1e0/0x450 [ath11k] ath11k_dp_rx_process_wbm_err+0x2fc/0x460 [ath11k] ath11k_dp_service_srng+0x2e0/0x348 [ath11k] Add a sanity check before processing the SKB to prevent invalid data access in the undecap native Wi-Fi function for the DP_RX_DECAP_TYPE_NATIVE_WIFI decap type. This adapted from the discussion/patch of the ath12k driver [1]. Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Link: https://lore.kernel.org/linux-wireless/20250211090302.4105141-1-tamizh.raja@oss.qualcomm.com/ # [1] Signed-off-by: Miaoqing Pan Link: https://lore.kernel.org/linux-wireless/20260512022351.2033155-2-miaoqing.pan@oss.qualcomm.com/ (cherry picked from commit b2599e03b60fa727eb11d3d4f9abb8b5ec6edf12) --- drivers/net/wireless/ath/ath11k/dp_rx.c | 50 +++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/ath/ath11k/dp_rx.c b/drivers/net/wireless/ath/ath11k/dp_rx.c index 9bbafbd696e6b..33c8e4ccf00a2 100644 --- a/drivers/net/wireless/ath/ath11k/dp_rx.c +++ b/drivers/net/wireless/ath/ath11k/dp_rx.c @@ -2501,6 +2501,29 @@ static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *nap ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); } +static bool ath11k_dp_rx_check_nwifi_hdr_len_valid(struct ath11k_base *ab, + struct hal_rx_desc *rx_desc, + struct sk_buff *msdu) +{ + struct ieee80211_hdr *hdr; + u8 decap_type; + u32 hdr_len; + + decap_type = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc); + if (decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI) + return true; + + hdr = (struct ieee80211_hdr *)msdu->data; + hdr_len = ieee80211_hdrlen(hdr->frame_control); + + if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN))) + return true; + + ab->soc_stats.invalid_rbm++; + WARN_ON_ONCE(1); + return false; +} + static int ath11k_dp_rx_process_msdu(struct ath11k *ar, struct sk_buff *msdu, struct sk_buff_head *msdu_list, @@ -2571,6 +2594,11 @@ static int ath11k_dp_rx_process_msdu(struct ath11k *ar, } } + if (unlikely(!ath11k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) { + ret = -EINVAL; + goto free_out; + } + ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status); ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); @@ -3306,6 +3334,12 @@ static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; skb_pull(msdu, hal_rx_desc_sz); + if (unlikely(!ath11k_dp_rx_check_nwifi_hdr_len_valid(ar->ab, rx_desc, + msdu))) { + dev_kfree_skb_any(msdu); + return -EINVAL; + } + ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); @@ -3998,6 +4032,10 @@ static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu, skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); } + + if (unlikely(!ath11k_dp_rx_check_nwifi_hdr_len_valid(ar->ab, desc, msdu))) + return -EINVAL; + ath11k_dp_rx_h_ppdu(ar, desc, status); ath11k_dp_rx_h_mpdu(ar, msdu, desc, status); @@ -4042,7 +4080,7 @@ static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu, return drop; } -static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, +static bool ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, struct ieee80211_rx_status *status) { u16 msdu_len; @@ -4050,6 +4088,7 @@ static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, u8 l3pad_bytes; struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; + struct ath11k_base *ab = ar->ab; rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); @@ -4059,6 +4098,9 @@ static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); + if (unlikely(!ath11k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu))) + return true; + ath11k_dp_rx_h_ppdu(ar, desc, status); status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | @@ -4066,19 +4108,21 @@ static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, ath11k_dp_rx_h_undecap(ar, msdu, desc, HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); + + return false; } static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu, struct ieee80211_rx_status *status) { struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); - bool drop = false; + bool drop; ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; switch (rxcb->err_code) { case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: - ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status); + drop = ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status); break; default: /* TODO: Review other rxdma error code to check if anything is From d9c3289f323d8b3b609eed5e28b7136301d344d6 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Mon, 13 Apr 2026 14:47:15 +0800 Subject: [PATCH 0891/1330] FROMLIST: wifi: ath11k: add MSDU length validation for TKIP MIC error In the WBM error path, while processing TKIP MIC errors, MSDU length is fetched from the hal_rx_desc's msdu_end. This MSDU length is directly passed to skb_put() without validation. In stress test scenarios, the WBM error ring may receive invalid descriptors, which could lead to an invalid MSDU length. To fix this, add a check to drop the skb when the calculated MSDU length is greater than the skb size. This is adapted from the discussion/patch of the ath12k driver [1]. Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Link: https://lore.kernel.org/linux-wireless/20250416021903.3178962-1-nithyanantham.paramasivam@oss.qualcomm.com/ # [1] Signed-off-by: Miaoqing Pan Link: https://lore.kernel.org/linux-wireless/20260512022351.2033155-3-miaoqing.pan@oss.qualcomm.com/ (cherry picked from commit a7780373c84ebe7855c5b7e9162ffeac4e74d2c4) --- drivers/net/wireless/ath/ath11k/dp_rx.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/wireless/ath/ath11k/dp_rx.c b/drivers/net/wireless/ath/ath11k/dp_rx.c index 33c8e4ccf00a2..73344509c7b65 100644 --- a/drivers/net/wireless/ath/ath11k/dp_rx.c +++ b/drivers/net/wireless/ath/ath11k/dp_rx.c @@ -4095,6 +4095,15 @@ static bool ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); + + if (unlikely(hal_rx_desc_sz + l3pad_bytes + msdu_len > DP_RX_BUFFER_SIZE)) { + ath11k_dbg(ab, ATH11K_DBG_DATA, + "invalid msdu len in tkip mic err %u\n", msdu_len); + ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", desc, + sizeof(*desc)); + return true; + } + skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); From f83ff565738782d95d494fd2ce51debb17f6f2df Mon Sep 17 00:00:00 2001 From: Hangtian Zhu Date: Fri, 10 Apr 2026 11:56:52 +0800 Subject: [PATCH 0892/1330] FROMLIST: wifi: ath12k: allow peer_id 0 in dp peer lookup For some chipsets, firmware can report HTT_T2H_MSG_TYPE_PEER_MAP2 with peer_id 0 as a valid value for mapping ath12k_dp_link_peer to ath12k_dp_peer. ath12k_dp_peer_find_by_peerid() currently treats peer_id 0 as invalid. When firmware assigns peer_id 0, peer lookup fails. As a result, DHCP OFFER packets are dropped in __ieee80211_rx_handle_packet() because pubsta is NULL. ath12k_dp_rx_deliver_msdu() <- rx_info->peer_id 0 ath12k_dp_peer_find_by_peerid -> peer NULL ieee80211_rx_napi <- pubsta NULL ieee80211_rx_list __ieee80211_rx_handle_packet <- pubsta NULL, skb undelivered The following error in the TX completion path is caused by the same issue: ath12k_wifi7_pci 0000:04:00.0: dp_tx: failed to find the peer with peer_id 0 The error message is triggered by: ath12k_wifi7_dp_tx_complete_msdu ath12k_dp_link_peer_find_by_peerid <- ts->peer_id 0 ath12k_dp_peer_find_by_peerid -> peer NULL ath12k_dp_tx_htt_tx_complete_buf ath12k_dp_link_peer_find_by_peerid <- peer_id 0 ath12k_dp_peer_find_by_peerid -> peer NULL Fix this by allowing peer_id 0 in ath12k_dp_peer_find_by_peerid() and rejecting only values >= ATH12K_DP_PEER_ID_INVALID. Also update peer_id 0 handling in monitor path: Always call ath12k_dp_link_peer_find_by_peerid() in ath12k_dp_rx_h_find_link_peer() to fetch the peer, including when peer_id is 0. Always store peer_id in ppdu_info->peer_id in ath12k_wifi7_dp_mon_rx_parse_status_tlv(), including peer_id 0. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0.c2-00074-QCACOLSWPL_V1_TO_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c7-00108-QCAHMTSWPL_V1.0_V2.0_SILICONZ_UPSTREAM-3 Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1 Signed-off-by: Hangtian Zhu Link: https://lore.kernel.org/all/20260512025732.1297849-1-hangtian.zhu@oss.qualcomm.com/ (cherry picked from commit 3623de023fc23c916a464f2bc9768875d595bbbc) --- drivers/net/wireless/ath/ath12k/dp_peer.c | 2 +- drivers/net/wireless/ath/ath12k/dp_rx.c | 3 +-- drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c | 3 +-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/dp_peer.c b/drivers/net/wireless/ath/ath12k/dp_peer.c index a1100782d45e6..47d009a0d61fe 100644 --- a/drivers/net/wireless/ath/ath12k/dp_peer.c +++ b/drivers/net/wireless/ath/ath12k/dp_peer.c @@ -419,7 +419,7 @@ struct ath12k_dp_peer *ath12k_dp_peer_find_by_peerid(struct ath12k_pdev_dp *dp_p RCU_LOCKDEP_WARN(!rcu_read_lock_held(), "ath12k dp peer find by peerid index called without rcu lock"); - if (!peer_id || peer_id >= ATH12K_DP_PEER_ID_INVALID) + if (peer_id >= ATH12K_DP_PEER_ID_INVALID) return NULL; index = ath12k_dp_peer_get_peerid_index(dp, peer_id); diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.c b/drivers/net/wireless/ath/ath12k/dp_rx.c index 2f987f76612c9..01a45ec88b4b8 100644 --- a/drivers/net/wireless/ath/ath12k/dp_rx.c +++ b/drivers/net/wireless/ath/ath12k/dp_rx.c @@ -1175,8 +1175,7 @@ ath12k_dp_rx_h_find_link_peer(struct ath12k_pdev_dp *dp_pdev, struct sk_buff *ms lockdep_assert_held(&dp->dp_lock); - if (rxcb->peer_id) - peer = ath12k_dp_link_peer_find_by_peerid(dp_pdev, rxcb->peer_id); + peer = ath12k_dp_link_peer_find_by_peerid(dp_pdev, rxcb->peer_id); if (peer) return peer; diff --git a/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c b/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c index 23ba0cc824a77..c84c42a3d3774 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c @@ -1780,8 +1780,7 @@ ath12k_wifi7_dp_mon_rx_parse_status_tlv(struct ath12k_pdev_dp *dp_pdev, info[1] = __le32_to_cpu(mpdu_start->info1); peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID); - if (peer_id) - ppdu_info->peer_id = peer_id; + ppdu_info->peer_id = peer_id; ppdu_info->mpdu_len += u32_get_bits(info[1], HAL_RX_MPDU_START_INFO2_MPDU_LEN); From 3acba9df44cf8b254b41c55d2f6f88f22014fd6a Mon Sep 17 00:00:00 2001 From: Pragnesh Papaniya Date: Tue, 12 May 2026 14:08:03 +0530 Subject: [PATCH 0893/1330] QCLINUX: qcom.config: Enable QCOM SCMI memlat bus scaling Enable the QCOM SCMI Generic Vendor Extension protocol (=y), the remote devfreq governor (=y), and the QCOM SCMI memlat devfreq device driver (=m) for LLCC/DDR/DDR_QOS bus scaling on Glymur and Hamoa SoCs. SCMI_QCOM_MEMLAT_DEVFREQ follows QCOM_CPUCP_MBOX at =m since it depends on that mailbox transport. Link: https://lore.kernel.org/lkml/20260507062237.78051-1-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar (cherry picked from commit f19fa91d95c822f87dc8d30b854f0660e95b9928) --- arch/arm64/configs/qcom.config | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 72f860a6dec2c..9de3118a8f584 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -105,3 +105,8 @@ CONFIG_FS_ENCRYPTION=y # Support performance profiling CONFIG_FTRACE=y + +# QCOM SCMI memlat bus scaling +CONFIG_QCOM_SCMI_GENERIC_EXT=y +CONFIG_DEVFREQ_GOV_REMOTE=y +CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ=m From 96e167eaccc64aac838d20da57abebbad766209a Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Thu, 7 May 2026 12:53:20 +0530 Subject: [PATCH 0894/1330] WORKAROUND: arm64: dts: qcom: purwa-iot-evk: support Bluetooth over both USB and UART On Purwa boards, a single M.2 slot may host either a UART-based or a USB-based Bluetooth device. As a result, the UART controller node is always present in DT, while the USB path is hot-pluggable. When Bluetooth operates over USB, the presence of the UART DT node still causes the hci_qca UART driver to probe. During probe or power sequencing, the driver may deassert BT_EN, cutting power to the shared Bluetooth device and disconnecting the USB interface. Model BT_EN as an always-on fixed regulator so it cannot be toggled by the UART probe. This prevents the UART driver from interfering with Bluetooth operation when the device is connected over USB. Workaround will be reverted once the M.2 solutionis available upstream. Signed-off-by: Wei Deng (cherry picked from commit d15f5a17f8be4c6116c1a398ab5e6c3a25852ef1) --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 34 ++++++++++++++++------ 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index eef03f1eb2a95..dca57f2db1fe1 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -514,6 +514,23 @@ regulator-boot-on; }; + vreg_wcn_bt_en: regulator-wcn-bt-en { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_BT_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 116 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_bt_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -628,10 +645,9 @@ vddrfa1p2-supply = <&vreg_wcn_1p9>; vddrfa1p8-supply = <&vreg_wcn_1p9>; - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-0 = <&wcn_wlan_en>; pinctrl-names = "default"; regulators { @@ -1508,13 +1524,13 @@ compatible = "qcom,wcn7850-bt"; max-speed = <3200000>; - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddaon-supply = <&vreg_wcn_3p3>; + vddwlcx-supply = <&vreg_wcn_3p3>; + vddwlmx-supply = <&vreg_wcn_3p3>; + vddrfacmn-supply = <&vreg_wcn_3p3>; + vddrfa0p8-supply = <&vreg_wcn_3p3>; + vddrfa1p2-supply = <&vreg_wcn_3p3>; + vddrfa1p8-supply = <&vreg_wcn_3p3>; }; }; From fc7b18236b0f418adbd22f89b8c8321a9c218c9f Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 11 May 2026 16:08:57 +0530 Subject: [PATCH 0895/1330] FROMLIST: arm64: defconfig: Enable CAMCC driver on Qualcomm Glymur SoC Enable camera clock controller driver for camera functionality on Qualcomm Glymur-CRD and similar other platforms with Glymur SoC. Link: https://lore.kernel.org/r/20260429-glymur_camcc-v2-4-0c3fd1977869@oss.qualcomm.com Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jagadeesh Kona Signed-off-by: Taniya Das (cherry picked from commit ff67f6a055a339d05f0386c7e3bcbfbe3cc472a9) --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1eb25e4b3cf92..789233c2ad831 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1465,6 +1465,7 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y CONFIG_COMMON_CLK_MT8192_VDECSYS=y CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_CLK_GLYMUR_CAMCC=m CONFIG_CLK_GLYMUR_DISPCC=m CONFIG_CLK_GLYMUR_GCC=y CONFIG_CLK_GLYMUR_GPUCC=m From a314a1ff67c90fe79065a709776e140499fcb790 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 8 May 2026 10:42:17 +0530 Subject: [PATCH 0896/1330] dt-bindings: clock: qcom: shikra-gcc: Add power-domains property Document the power-domains property in order to propagate the votes on GDSC to CX raill. Signed-off-by: Imran Shaik (cherry picked from commit 116cd1ac6dd212043dac826243540b7439c1cfe6) --- .../bindings/clock/qcom,shikra-gcc.yaml | 33 +++++++++++-------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml index 39cf7383df8bc..da6eebfa84c22 100644 --- a/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml @@ -4,15 +4,15 @@ $id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller on Shikra +title: Global Clock & Reset Controller on Qualcomm Shikra SoC maintainers: - Imran Shaik - Taniya Das description: | - Qualcomm global clock control module provides the clocks, resets and power - domains on Shikra. + Global clock control module provides the clocks, resets and power + domains on Qualcomm Shikra SoC platform. See also: include/dt-bindings/clock/qcom,shikra-gcc.h @@ -31,9 +31,14 @@ properties: - description: PCIE Pipe clock source - description: USB3 phy wrapper pipe clock source + power-domains: + items: + - description: CX domain + required: - compatible - clocks + - power-domains - '#power-domain-cells' allOf: @@ -44,20 +49,22 @@ unevaluatedProperties: false examples: - | #include + #include clock-controller@1400000 { compatible = "qcom,shikra-gcc"; reg = <0x01400000 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&sleep_clk>, - <&emac0_sgmiiphy_rclk>, - <&emac0_sgmiiphy_tclk>, - <&emac1_sgmiiphy_rclk>, - <&emac1_sgmiiphy_tclk>, - <&pcie_pipe_clk>, - <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; + <&sleep_clk>, + <&emac0_sgmiiphy_rclk>, + <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, + <&pcie_pipe_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; }; ... From c1f9a121f21d141046b7345625d598a74b695aef Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Fri, 27 Mar 2026 18:14:37 +0530 Subject: [PATCH 0897/1330] dt-bindings: mailbox: qcom: Modify Shikra APCS compatible Mention compatible for the Qualcomm Shikra APCS block in the same block as sdm845-apss-shared since they share the same data. Signed-off-by: Sneh Mankad (cherry picked from commit 0ae26ead9a5dd6281aa25b399d903f02b8a1932c) --- .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index a6d4fe840ea5d..f5c54639930aa 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -49,6 +49,7 @@ properties: - qcom,qcs615-apss-shared - qcom,sc7180-apss-shared - qcom,sc8180x-apss-shared + - qcom,shikra-apss-shared - qcom,sm7150-apss-shared - qcom,sm8150-apss-shared - const: qcom,sdm845-apss-shared @@ -66,7 +67,6 @@ properties: - qcom,qcm2290-apcs-hmss-global - qcom,shikra-apcs-hmss-global - qcom,sdm845-apss-shared - - qcom,shikra-apcs-hmss-global reg: maxItems: 1 @@ -241,7 +241,6 @@ allOf: - qcom,qcm2290-apcs-hmss-global - qcom,shikra-apcs-hmss-global - qcom,sdm845-apss-shared - - qcom,shikra-apcs-hmss-global then: properties: clocks: false From 559b3802ae2427708175e748ee86249247fff68c Mon Sep 17 00:00:00 2001 From: Anandu Krishnan E Date: Tue, 12 May 2026 13:54:49 +0530 Subject: [PATCH 0898/1330] misc: fastrpc: Introduce cache maintenance operations Introduce cache maintenance operations for remote arguments in fastrpc driver for non-dma coherent targets. Upstream-Status: Pending Signed-off-by: Abhinav Parihar Signed-off-by: Anandu Krishnan E (cherry picked from commit c7d8100749c6e861041c8b37ff314be46be923eb) --- drivers/misc/fastrpc.c | 105 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 102 insertions(+), 3 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 5e596ed65e09d..5a67b60f7d9a5 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -196,6 +196,7 @@ struct fastrpc_buf_overlap { u64 mstart; u64 mend; u64 offset; + bool do_cmo; }; struct fastrpc_buf { @@ -271,7 +272,7 @@ struct fastrpc_session_ctx { int sid; bool used; bool valid; - struct mutex mutex; + bool coherent; }; struct fastrpc_soc_data { @@ -351,6 +352,18 @@ static inline u64 fastrpc_sid_offset(struct fastrpc_channel_ctx *cctx, return (u64)sctx->sid << cctx->soc_data->sid_pos; } +/* + * Align buffer size to kernel page granularity for dma-buf cache maintenance. + */ +static inline uint64_t buf_page_size(uint64_t size) +{ + int cache_align = dma_get_cache_alignment(); + uint64_t sz = ALIGN(size, cache_align); + + return max_t(uint64_t, sz, (uint64_t)cache_align); +} + + static void fastrpc_free_map(struct kref *ref) { struct fastrpc_map *map; @@ -625,7 +638,9 @@ static int olaps_cmp(const void *a, const void *b) static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) { u64 max_end = 0; + int max_raix = -1; int i; + int inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); for (i = 0; i < ctx->nbufs; ++i) { ctx->olaps[i].start = ctx->args[i].ptr; @@ -645,6 +660,9 @@ static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) if (ctx->olaps[i].end > max_end) { max_end = ctx->olaps[i].end; } else { + if ((max_raix < inbufs && ctx->olaps[i].raix + 1 > inbufs) || + (ctx->olaps[i].raix < inbufs && max_raix + 1 > inbufs)) + ctx->olaps[i].do_cmo = true; ctx->olaps[i].mend = 0; ctx->olaps[i].mstart = 0; } @@ -654,6 +672,7 @@ static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) ctx->olaps[i].mstart = ctx->olaps[i].start; ctx->olaps[i].offset = 0; max_end = ctx->olaps[i].end; + max_raix = ctx->olaps[i].raix; } } } @@ -884,7 +903,7 @@ static int fastrpc_map_attach(struct fastrpc_user *fl, int fd, mutex_unlock(&fl->sctx->mutex); goto attach_err; } - + if (!sess->coherent) table = dma_buf_map_attachment_unlocked(map->attach, DMA_BIDIRECTIONAL); if (IS_ERR(table)) { err = PTR_ERR(table); @@ -1054,6 +1073,70 @@ static int fastrpc_create_maps(struct fastrpc_invoke_ctx *ctx) return 0; } +static int fastrpc_flush_args(struct fastrpc_invoke_ctx *ctx, + union fastrpc_remote_arg *rpra) +{ + int oix, inbufs, outbufs; + struct device *dev = ctx->fl->sctx->dev; + + inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); + outbufs = REMOTE_SCALARS_OUTBUFS(ctx->sc); + for (oix = 0; oix < inbufs+outbufs; ++oix) { + int i = ctx->olaps[oix].raix; + struct fastrpc_map *map = ctx->maps[i]; + + if (i+1 > inbufs) + continue; + if (!map) + continue; + if (rpra[i].buf.len && ctx->olaps[oix].mstart) { + if (map->buf) { + if ((buf_page_size(ctx->olaps[oix].mend - + ctx->olaps[oix].mstart)) == map->size ) { + dma_buf_begin_cpu_access(map->buf, DMA_TO_DEVICE); + dma_buf_end_cpu_access(map->buf, DMA_TO_DEVICE); + } + } + } + } + return 0; +} + +static int fastrpc_inv_args(struct fastrpc_invoke_ctx *ctx) +{ + int i, inbufs, outbufs; + uint32_t sc = ctx->sc; + union fastrpc_remote_arg *rpra = ctx->rpra; + struct device *dev = ctx->fl->sctx->dev; + + inbufs = REMOTE_SCALARS_INBUFS(sc); + outbufs = REMOTE_SCALARS_OUTBUFS(sc); + for (i = 0; i < inbufs+outbufs; ++i) { + int over = ctx->olaps[i].raix; + struct fastrpc_map *map = ctx->maps[over]; + + if (over + 1 <= inbufs) + continue; + if (!rpra[over].buf.len) + continue; + if (!map) + continue; + if (((uintptr_t)rpra & PAGE_MASK) == + ((uintptr_t)rpra[over].buf.pv & PAGE_MASK)) + continue; + if (ctx->olaps[i].mstart) { + if (map->buf) { + if (((buf_page_size(ctx->olaps[i].mend - + ctx->olaps[i].mstart)) == map->size)) { + dma_buf_begin_cpu_access(map->buf, DMA_FROM_DEVICE); + dma_buf_end_cpu_access(map->buf, DMA_TO_DEVICE); + } + } + } + } + return 0; +} + static struct fastrpc_invoke_buf *fastrpc_invoke_buf_start(union fastrpc_remote_arg *pra, int len) { return (struct fastrpc_invoke_buf *)(&pra[len]); @@ -1178,6 +1261,12 @@ static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) } } + if (!ctx->fl->sctx->coherent) { + err = fastrpc_flush_args(ctx, rpra); + if (err) + goto bail; + } + for (i = ctx->nbufs; i < ctx->nscalars; ++i) { list[i].num = ctx->args[i].length ? 1 : 0; list[i].pgidx = i; @@ -1366,6 +1455,11 @@ static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, if (err) goto bail; + if (!fl->sctx->coherent) { + err = fastrpc_inv_args(ctx); + if (err) + goto bail; + } /* make sure that all CPU memory writes are seen by DSP */ dma_wmb(); /* Send invoke buffer to remote dsp */ @@ -1395,6 +1489,11 @@ static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, /* make sure that all memory writes by DSP are seen by CPU */ dma_rmb(); + if (!fl->sctx->coherent) { + err = fastrpc_inv_args(ctx); + if (err) + goto bail; + } /* populate all the output buffers with results */ err = fastrpc_put_args(ctx, kernel); if (err) @@ -2399,7 +2498,7 @@ static int fastrpc_cb_probe(struct platform_device *pdev) sess->used = false; sess->valid = true; sess->dev = dev; - mutex_init(&sess->mutex); + sess->coherent = of_property_read_bool(dev->of_node, "dma-coherent"); dev_set_drvdata(dev, sess); if (cctx->domain_id == CDSP_DOMAIN_ID) From adbf77485361019c73657527fe529f94b2c509db Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 8 May 2026 10:52:40 +0530 Subject: [PATCH 0899/1330] arm64: dts: qcom: shikra: Add CX power domain to GCC Add CX power domain support to GCC node on Shikra platform. Signed-off-by: Imran Shaik (cherry picked from commit 0acc9b4201513f150dec91af82a6b21538d02486) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 84d7f85bb233d..a85c647d68c02 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -801,6 +801,7 @@ <0>, <0>, <0>; + power-domains = <&rpmpd RPMPD_VDDCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From e0ad2745adbe1a1c4d683ab4e5caf49c9131a393 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Fri, 8 May 2026 14:48:36 +0530 Subject: [PATCH 0900/1330] arm64: dts: qcom: Modify compatible for Shikra APCS device Modify compatible for Shikra mailbox APCS device and add fallback compatible string. Signed-off-by: Sneh Mankad (cherry picked from commit 21152b664bf13c3a13f70c7a49992d480ce9e432) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a85c647d68c02..649e9f87c7b6e 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1407,7 +1407,7 @@ }; apcs_glb: mailbox@f400000 { - compatible = "qcom,shikra-apcs-hmss-global"; + compatible = "qcom,shikra-apss-shared", "qcom,sdm845-apss-shared"; reg = <0x0 0x0f400000 0x0 0x1000>; #mbox-cells = <1>; }; From aaf7331763d8a39e423209cbb11daecfae29a2aa Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Tue, 17 Mar 2026 18:05:45 +0800 Subject: [PATCH 0901/1330] FROMLIST: media: qcom: camss: Add common TPG support Introduce a new common Test Pattern Generator (TPG) implementation for Qualcomm CAMSS. This module provides a generic interface for pattern generation that can be reused by multiple platforms. Unlike CSID-integrated TPG, this TPG acts as a standalone block that emulates both CSIPHY and sensor behavior, enabling flexible test patterns without external hardware. Link: https://lore.kernel.org/all/20260317-camss_tpg-v10-1-b4cfa85c2e1b@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # Dell Inpsiron14p Signed-off-by: Wenmeng Liu (cherry picked from commit 115eae8fc88d86b9ba24af230f44f45f35a492ba) --- drivers/media/platform/qcom/camss/Makefile | 11 +- drivers/media/platform/qcom/camss/camss-tpg.c | 519 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss-tpg.h | 118 ++++ drivers/media/platform/qcom/camss/camss.h | 5 + 4 files changed, 648 insertions(+), 5 deletions(-) create mode 100644 drivers/media/platform/qcom/camss/camss-tpg.c create mode 100644 drivers/media/platform/qcom/camss/camss-tpg.h diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index ed8001ef90a68..8e4611d7fa652 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -11,10 +11,13 @@ qcom-camss-objs += \ camss-csid-gen2.o \ camss-csid-gen3.o \ camss-csid-gen4.o \ + camss-csiphy.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ - camss-csiphy.o \ + camss-format.o \ camss-ispif.o \ + camss-tpg.o \ + camss-vfe.o \ camss-vfe-4-1.o \ camss-vfe-4-7.o \ camss-vfe-4-8.o \ @@ -22,12 +25,10 @@ qcom-camss-objs += \ camss-vfe-340.o \ camss-vfe-480.o \ camss-vfe-680.o \ + camss-vfe-gen1.o \ camss-vfe-gen3.o \ camss-vfe-gen4.o \ - camss-vfe-gen1.o \ camss-vfe-vbif.o \ - camss-vfe.o \ - camss-video.o \ - camss-format.o \ + camss-video.o obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-tpg.c b/drivers/media/platform/qcom/camss/camss-tpg.c new file mode 100644 index 0000000000000..c5b75132add44 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.c @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +static const struct tpg_format_info formats_gen1[] = { + { + MEDIA_BUS_FMT_SBGGR8_1X8, + MIPI_CSI2_DT_RAW8, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SGBRG8_1X8, + MIPI_CSI2_DT_RAW8, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SGRBG8_1X8, + MIPI_CSI2_DT_RAW8, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SRGGB8_1X8, + MIPI_CSI2_DT_RAW8, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SBGGR10_1X10, + MIPI_CSI2_DT_RAW10, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SGBRG10_1X10, + MIPI_CSI2_DT_RAW10, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SGRBG10_1X10, + MIPI_CSI2_DT_RAW10, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SRGGB10_1X10, + MIPI_CSI2_DT_RAW10, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SBGGR12_1X12, + MIPI_CSI2_DT_RAW12, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SGBRG12_1X12, + MIPI_CSI2_DT_RAW12, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SGRBG12_1X12, + MIPI_CSI2_DT_RAW12, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SRGGB12_1X12, + MIPI_CSI2_DT_RAW12, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_Y8_1X8, + MIPI_CSI2_DT_RAW8, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_Y10_1X10, + MIPI_CSI2_DT_RAW10, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, +}; + +const struct tpg_formats tpg_formats_gen1 = { + .nformats = ARRAY_SIZE(formats_gen1), + .formats = formats_gen1 +}; + +const struct tpg_format_info *tpg_get_fmt_entry(const struct tpg_format_info *formats, + unsigned int nformats, + u32 code) +{ + unsigned int i; + + for (i = 0; i < nformats; i++) + if (code == formats[i].code) + return &formats[i]; + + return ERR_PTR(-EINVAL); +} + +static int tpg_set_clock_rates(struct tpg_device *tpg) +{ + struct device *dev = tpg->camss->dev; + int i, ret; + + for (i = 0; i < tpg->nclocks; i++) { + struct camss_clock *clock = &tpg->clock[i]; + long round_rate; + + if (clock->freq) { + round_rate = clk_round_rate(clock->clk, clock->freq[0]); + if (round_rate < 0) { + dev_err(dev, "clk round rate failed: %ld\n", + round_rate); + return -EINVAL; + } + + ret = clk_set_rate(clock->clk, round_rate); + if (ret < 0) { + dev_err(dev, "clk set rate failed: %d\n", ret); + return ret; + } + } + } + + return 0; +} + +static int tpg_set_power(struct v4l2_subdev *sd, int on) +{ + struct tpg_device *tpg = v4l2_get_subdevdata(sd); + struct device *dev = tpg->camss->dev; + + if (on) { + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + ret = tpg_set_clock_rates(tpg); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + ret = camss_enable_clocks(tpg->nclocks, tpg->clock, dev); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + tpg->res->hw_ops->reset(tpg); + + tpg->res->hw_ops->hw_version(tpg); + } else { + camss_disable_clocks(tpg->nclocks, tpg->clock); + + pm_runtime_put_sync(dev); + } + + return 0; +} + +static int tpg_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct tpg_device *tpg = v4l2_get_subdevdata(sd); + int ret; + + if (enable) { + ret = v4l2_ctrl_handler_setup(&tpg->ctrls); + if (ret < 0) { + dev_err(tpg->camss->dev, + "could not sync v4l2 controls: %d\n", ret); + return ret; + } + } + + return tpg->res->hw_ops->configure_stream(tpg, enable); +} + +static struct v4l2_mbus_framefmt * +__tpg_get_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + enum v4l2_subdev_format_whence which) +{ + if (which == V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_state_get_format(sd_state, + pad); + + return &tpg->fmt; +} + +static void tpg_try_format(struct tpg_device *tpg, + struct v4l2_mbus_framefmt *fmt) +{ + unsigned int i; + + for (i = 0; i < tpg->res->formats->nformats; i++) + if (tpg->res->formats->formats[i].code == fmt->code) + break; + + if (i >= tpg->res->formats->nformats) + fmt->code = MEDIA_BUS_FMT_SBGGR8_1X8; + + fmt->width = clamp_t(u32, fmt->width, TPG_MIN_WIDTH, TPG_MAX_WIDTH); + fmt->height = clamp_t(u32, fmt->height, TPG_MIN_HEIGHT, TPG_MAX_HEIGHT); + fmt->field = V4L2_FIELD_NONE; + fmt->colorspace = V4L2_COLORSPACE_SRGB; +} + +static int tpg_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct tpg_device *tpg = v4l2_get_subdevdata(sd); + + if (code->index >= tpg->res->formats->nformats) + return -EINVAL; + + code->code = tpg->res->formats->formats[code->index].code; + + return 0; +} + +static int tpg_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct tpg_device *tpg = v4l2_get_subdevdata(sd); + unsigned int i; + + if (fse->index != 0) + return -EINVAL; + + for (i = 0; i < tpg->res->formats->nformats; i++) + if (tpg->res->formats->formats[i].code == fse->code) + break; + + if (i >= tpg->res->formats->nformats) + return -EINVAL; + + fse->min_width = TPG_MIN_WIDTH; + fse->min_height = TPG_MIN_HEIGHT; + fse->max_width = TPG_MAX_WIDTH; + fse->max_height = TPG_MAX_HEIGHT; + + return 0; +} + +static int tpg_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg = v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format = __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + fmt->format = *format; + + return 0; +} + +static int tpg_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg = v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format = __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + tpg_try_format(tpg, &fmt->format); + *format = fmt->format; + + return 0; +} + +static int tpg_init_formats(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct v4l2_subdev_format format = { + .pad = MSM_TPG_PAD_SRC, + .which = fh ? V4L2_SUBDEV_FORMAT_TRY : + V4L2_SUBDEV_FORMAT_ACTIVE, + .format = { + .code = MEDIA_BUS_FMT_SBGGR8_1X8, + .width = 1920, + .height = 1080, + } + }; + + return tpg_set_format(sd, fh ? fh->state : NULL, &format); +} + +static int tpg_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct tpg_device *tpg = container_of(ctrl->handler, + struct tpg_device, ctrls); + int ret = -EINVAL; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + ret = tpg->res->hw_ops->configure_testgen_pattern(tpg, ctrl->val); + break; + } + + return ret; +} + +static const struct v4l2_ctrl_ops tpg_ctrl_ops = { + .s_ctrl = tpg_s_ctrl, +}; + +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id) +{ + struct platform_device *pdev; + struct device *dev; + int i, j; + + dev = camss->dev; + pdev = to_platform_device(dev); + + tpg->camss = camss; + tpg->id = id; + tpg->res = &res->tpg; + tpg->res->hw_ops->subdev_init(tpg); + + tpg->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]); + if (IS_ERR(tpg->base)) + return PTR_ERR(tpg->base); + + tpg->nclocks = 0; + while (res->clock[tpg->nclocks]) + tpg->nclocks++; + + if (!tpg->nclocks) + return 0; + + tpg->clock = devm_kcalloc(dev, tpg->nclocks, + sizeof(*tpg->clock), GFP_KERNEL); + if (!tpg->clock) + return -ENOMEM; + + for (i = 0; i < tpg->nclocks; i++) { + struct camss_clock *clock = &tpg->clock[i]; + + clock->clk = devm_clk_get(dev, res->clock[i]); + if (IS_ERR(clock->clk)) + return PTR_ERR(clock->clk); + + clock->name = res->clock[i]; + + clock->nfreqs = 0; + while (res->clock_rate[i][clock->nfreqs]) + clock->nfreqs++; + + if (!clock->nfreqs) { + clock->freq = NULL; + continue; + } + + clock->freq = devm_kcalloc(dev, clock->nfreqs, + sizeof(*clock->freq), GFP_KERNEL); + if (!clock->freq) + return -ENOMEM; + + for (j = 0; j < clock->nfreqs; j++) + clock->freq[j] = res->clock_rate[i][j]; + } + + return 0; +} + +static int tpg_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + if (flags & MEDIA_LNK_FL_ENABLED) + if (media_pad_remote_pad_first(local)) + return -EBUSY; + + return 0; +} + +static const struct v4l2_subdev_core_ops tpg_core_ops = { + .s_power = tpg_set_power, +}; + +static const struct v4l2_subdev_video_ops tpg_video_ops = { + .s_stream = tpg_set_stream, +}; + +static const struct v4l2_subdev_pad_ops tpg_pad_ops = { + .enum_mbus_code = tpg_enum_mbus_code, + .enum_frame_size = tpg_enum_frame_size, + .get_fmt = tpg_get_format, + .set_fmt = tpg_set_format, +}; + +static const struct v4l2_subdev_ops tpg_v4l2_ops = { + .core = &tpg_core_ops, + .video = &tpg_video_ops, + .pad = &tpg_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops tpg_v4l2_internal_ops = { + .open = tpg_init_formats, +}; + +static const struct media_entity_operations tpg_media_ops = { + .link_setup = tpg_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev) +{ + struct v4l2_subdev *sd = &tpg->subdev; + struct device *dev = tpg->camss->dev; + int ret; + + v4l2_subdev_init(sd, &tpg_v4l2_ops); + sd->internal_ops = &tpg_v4l2_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; + snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", + "msm_tpg", tpg->id); + sd->grp_id = TPG_GRP_ID; + v4l2_set_subdevdata(sd, tpg); + + ret = v4l2_ctrl_handler_init(&tpg->ctrls, 1); + if (ret < 0) { + dev_err(dev, "Failed to init ctrl handler: %d\n", ret); + return ret; + } + + tpg->testgen_mode = v4l2_ctrl_new_std_menu_items(&tpg->ctrls, + &tpg_ctrl_ops, V4L2_CID_TEST_PATTERN, + tpg->testgen.nmodes, 0, 0, + tpg->testgen.modes); + if (tpg->ctrls.error) { + dev_err(dev, "Failed to init ctrl: %d\n", tpg->ctrls.error); + ret = tpg->ctrls.error; + goto free_ctrl; + } + + tpg->subdev.ctrl_handler = &tpg->ctrls; + + ret = tpg_init_formats(sd, NULL); + if (ret < 0) { + dev_err(dev, "Failed to init format: %d\n", ret); + goto free_ctrl; + } + + tpg->pad.flags = MEDIA_PAD_FL_SOURCE; + + sd->entity.ops = &tpg_media_ops; + ret = media_entity_pads_init(&sd->entity, 1, &tpg->pad); + if (ret < 0) { + dev_err(dev, "Failed to init media entity: %d\n", ret); + goto free_ctrl; + } + + ret = v4l2_device_register_subdev(v4l2_dev, sd); + if (ret < 0) { + dev_err(dev, "Failed to register subdev: %d\n", ret); + media_entity_cleanup(&sd->entity); + goto free_ctrl; + } + + return 0; + +free_ctrl: + v4l2_ctrl_handler_free(&tpg->ctrls); + + return ret; +} + +void msm_tpg_unregister_entity(struct tpg_device *tpg) +{ + v4l2_device_unregister_subdev(&tpg->subdev); + media_entity_cleanup(&tpg->subdev.entity); + v4l2_ctrl_handler_free(&tpg->ctrls); +} diff --git a/drivers/media/platform/qcom/camss/camss-tpg.h b/drivers/media/platform/qcom/camss/camss-tpg.h new file mode 100644 index 0000000000000..7fb35a97dd068 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * camss-tpg.h + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef QC_MSM_CAMSS_TPG_H +#define QC_MSM_CAMSS_TPG_H + +#include +#include +#include +#include +#include +#include +#include + +#define ENCODE_FORMAT_UNCOMPRESSED_8_BIT 0x1 +#define ENCODE_FORMAT_UNCOMPRESSED_10_BIT 0x2 +#define ENCODE_FORMAT_UNCOMPRESSED_12_BIT 0x3 +#define ENCODE_FORMAT_UNCOMPRESSED_14_BIT 0x4 +#define ENCODE_FORMAT_UNCOMPRESSED_16_BIT 0x5 +#define ENCODE_FORMAT_UNCOMPRESSED_20_BIT 0x6 +#define ENCODE_FORMAT_UNCOMPRESSED_24_BIT 0x7 + +#define MSM_TPG_PAD_SRC 0 +#define MSM_TPG_ACTIVE_VC 0 +#define MSM_TPG_ACTIVE_DT 0 + +#define TPG_MIN_WIDTH 1 +#define TPG_MIN_HEIGHT 1 +#define TPG_MAX_WIDTH 8191 +#define TPG_MAX_HEIGHT 8191 + +#define TPG_GRP_ID 0 + +enum tpg_testgen_mode { + TPG_PAYLOAD_MODE_DISABLED = 0, + TPG_PAYLOAD_MODE_INCREMENTING = 1, + TPG_PAYLOAD_MODE_ALTERNATING_55_AA = 2, + TPG_PAYLOAD_MODE_RANDOM = 5, + TPG_PAYLOAD_MODE_USER_SPECIFIED = 6, + TPG_PAYLOAD_MODE_COLOR_BARS = 9, + TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1 = 9, +}; + +struct tpg_testgen_config { + enum tpg_testgen_mode mode; + const char * const*modes; + u8 nmodes; +}; + +struct tpg_format_info { + u32 code; + u8 data_type; + u8 encode_format; + u8 bpp; +}; + +struct tpg_formats { + unsigned int nformats; + const struct tpg_format_info *formats; +}; + +struct tpg_device; + +struct tpg_hw_ops { + int (*configure_stream)(struct tpg_device *tpg, u8 enable); + int (*configure_testgen_pattern)(struct tpg_device *tpg, s32 val); + u32 (*hw_version)(struct tpg_device *tpg); + int (*reset)(struct tpg_device *tpg); + void (*subdev_init)(struct tpg_device *tpg); +}; + +struct tpg_subdev_resources { + u8 lane_cnt; + const struct tpg_formats *formats; + const struct tpg_hw_ops *hw_ops; +}; + +struct tpg_device { + struct camss *camss; + u8 id; + struct v4l2_subdev subdev; + struct media_pad pad; + void __iomem *base; + struct camss_clock *clock; + int nclocks; + struct tpg_testgen_config testgen; + struct v4l2_mbus_framefmt fmt; + struct v4l2_ctrl_handler ctrls; + struct v4l2_ctrl *testgen_mode; + const struct tpg_subdev_resources *res; + u32 hw_version; +}; + +struct camss_subdev_resources; + +const struct tpg_format_info *tpg_get_fmt_entry(const struct tpg_format_info *formats, + unsigned int nformats, + u32 code); + +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id); + +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev); + +void msm_tpg_unregister_entity(struct tpg_device *tpg); + +extern const struct tpg_formats tpg_formats_gen1; + +extern const struct tpg_hw_ops tpg_ops_gen1; + +#endif /* QC_MSM_CAMSS_TPG_H */ diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index ddc1eabc06c3c..bfe45d8f01eaa 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -21,6 +21,7 @@ #include "camss-csid.h" #include "camss-csiphy.h" #include "camss-ispif.h" +#include "camss-tpg.h" #include "camss-vfe.h" #include "camss-format.h" @@ -52,6 +53,7 @@ struct camss_subdev_resources { char *interrupt[CAMSS_RES_MAX]; union { struct csiphy_subdev_resources csiphy; + struct tpg_subdev_resources tpg; struct csid_subdev_resources csid; struct vfe_subdev_resources vfe; }; @@ -107,6 +109,7 @@ struct camss_resources { const char *pd_name; const bool legacy_phy; const struct camss_subdev_resources *csiphy_res; + const struct camss_subdev_resources *tpg_res; const struct camss_subdev_resources *csid_res; const struct camss_subdev_resources *ispif_res; const struct camss_subdev_resources *vfe_res; @@ -114,6 +117,7 @@ struct camss_resources { const struct resources_icc *icc_res; const unsigned int icc_path_num; const unsigned int csiphy_num; + const unsigned int tpg_num; const unsigned int csid_num; const unsigned int vfe_num; }; @@ -124,6 +128,7 @@ struct camss { struct media_device media_dev; struct device *dev; struct csiphy_device *csiphy; + struct tpg_device *tpg; struct csid_device *csid; struct ispif_device *ispif; struct vfe_device *vfe; From f8498cb16e9d91ef726ac86c5c745b9e7345eb56 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Tue, 17 Mar 2026 18:05:46 +0800 Subject: [PATCH 0902/1330] FROMLIST: media: qcom: camss: Add link support for TPG TPG is connected to the csid as an entity, the link needs to be adapted. Link: https://lore.kernel.org/all/20260317-camss_tpg-v10-2-b4cfa85c2e1b@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # Dell Inpsiron14p Signed-off-by: Wenmeng Liu (cherry picked from commit e960ece065fd17ff02a4c4757c24c72d3c26f766) --- .../media/platform/qcom/camss/camss-csid.c | 45 ++++++++++----- .../media/platform/qcom/camss/camss-csid.h | 1 + .../media/platform/qcom/camss/camss-csiphy.c | 1 + .../media/platform/qcom/camss/camss-csiphy.h | 2 + drivers/media/platform/qcom/camss/camss.c | 55 +++++++++++++++++++ 5 files changed, 90 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index ed1820488c987..48459b46a981b 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -35,6 +35,8 @@ #define HW_VERSION_REVISION 16 #define HW_VERSION_GENERATION 28 +#define LANE_CFG_BITWIDTH 4 + #define MSM_CSID_NAME "msm_csid" const char * const csid_testgen_modes[] = { @@ -1215,18 +1217,22 @@ void msm_csid_get_csid_id(struct media_entity *entity, u8 *id) } /* - * csid_get_lane_assign - Calculate CSI2 lane assign configuration parameter - * @lane_cfg - CSI2 lane configuration + * csid_get_lane_assign - Calculate lane assign by csiphy/tpg lane num + * @lane_cfg: CSI2 lane configuration + * @num_lanes: lane num * * Return lane assign */ -static u32 csid_get_lane_assign(struct csiphy_lanes_cfg *lane_cfg) +static u32 csid_get_lane_assign(struct csiphy_lanes_cfg *lane_cfg, int num_lanes) { u32 lane_assign = 0; + int pos; int i; - for (i = 0; i < lane_cfg->num_data; i++) - lane_assign |= lane_cfg->data[i].pos << (i * 4); + for (i = 0; i < num_lanes; i++) { + pos = lane_cfg ? lane_cfg->data[i].pos : i; + lane_assign |= pos << (i * LANE_CFG_BITWIDTH); + } return lane_assign; } @@ -1251,6 +1257,7 @@ static int csid_link_setup(struct media_entity *entity, if ((local->flags & MEDIA_PAD_FL_SINK) && (flags & MEDIA_LNK_FL_ENABLED)) { struct v4l2_subdev *sd; + struct tpg_device *tpg; struct csid_device *csid; struct csiphy_device *csiphy; struct csiphy_lanes_cfg *lane_cfg; @@ -1265,18 +1272,28 @@ static int csid_link_setup(struct media_entity *entity, return -EBUSY; sd = media_entity_to_v4l2_subdev(remote->entity); - csiphy = v4l2_get_subdevdata(sd); + if (sd->grp_id == TPG_GRP_ID) { + tpg = v4l2_get_subdevdata(sd); - /* If a sensor is not linked to CSIPHY */ - /* do no allow a link from CSIPHY to CSID */ - if (!csiphy->cfg.csi2) - return -EPERM; + csid->phy.lane_cnt = tpg->res->lane_cnt; + csid->phy.csiphy_id = tpg->id; + csid->phy.lane_assign = csid_get_lane_assign(NULL, csid->phy.lane_cnt); + csid->tpg_linked = true; + } else { + csiphy = v4l2_get_subdevdata(sd); - csid->phy.csiphy_id = csiphy->id; + /* If a sensor is not linked to CSIPHY */ + /* do no allow a link from CSIPHY to CSID */ + if (!csiphy->cfg.csi2) + return -EPERM; - lane_cfg = &csiphy->cfg.csi2->lane_cfg; - csid->phy.lane_cnt = lane_cfg->num_data; - csid->phy.lane_assign = csid_get_lane_assign(lane_cfg); + csid->phy.csiphy_id = csiphy->id; + + lane_cfg = &csiphy->cfg.csi2->lane_cfg; + csid->phy.lane_cnt = lane_cfg->num_data; + csid->phy.lane_assign = csid_get_lane_assign(lane_cfg, lane_cfg->num_data); + csid->tpg_linked = false; + } } /* Decide which virtual channels to enable based on which source pads are enabled */ if (local->flags & MEDIA_PAD_FL_SOURCE) { diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index 75a113050eb1a..e6590b2bd8be5 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -169,6 +169,7 @@ struct csid_device { int num_supplies; struct completion reset_complete; struct csid_testgen_config testgen; + bool tpg_linked; struct csid_phy_config phy; struct v4l2_mbus_framefmt fmt[MSM_CSID_PADS_NUM]; struct v4l2_ctrl_handler ctrls; diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index b8bfbf2fef8fa..886ea61c9ea7b 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -942,6 +942,7 @@ int msm_csiphy_register_entity(struct csiphy_device *csiphy, sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", MSM_CSIPHY_NAME, csiphy->id); + sd->grp_id = CSIPHY_GRP_ID; v4l2_set_subdevdata(sd, csiphy); ret = csiphy_init_formats(sd, NULL); diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h index 25b803c06e8bf..1879826034aac 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -22,6 +22,8 @@ #define MSM_CSIPHY_PAD_SRC 1 #define MSM_CSIPHY_PADS_NUM 2 +#define CSIPHY_GRP_ID 1 + struct csiphy_lane { u8 pos; u8 pol; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 47da76dd87f7e..520a4c905e7d2 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4854,6 +4854,19 @@ static int camss_init_subdevices(struct camss *camss) } } + if (camss->tpg) { + for (i = 0; i < camss->res->tpg_num; i++) { + ret = msm_tpg_subdev_init(camss, &camss->tpg[i], + &res->tpg_res[i], i); + if (ret < 0) { + dev_err(camss->dev, + "Failed to init tpg%d sub-device: %d\n", + i, ret); + return ret; + } + } + } + /* note: SM8250 requires VFE to be initialized before CSID */ for (i = 0; i < camss->res->vfe_num; i++) { ret = msm_vfe_subdev_init(camss, &camss->vfe[i], @@ -4945,6 +4958,23 @@ static int camss_link_entities(struct camss *camss) } } + for (i = 0; i < camss->res->tpg_num; i++) { + for (j = 0; j < camss->res->csid_num; j++) { + ret = media_create_pad_link(&camss->tpg[i].subdev.entity, + MSM_TPG_PAD_SRC, + &camss->csid[j].subdev.entity, + MSM_CSID_PAD_SINK, + 0); + if (ret < 0) { + camss_link_err(camss, + camss->tpg[i].subdev.entity.name, + camss->csid[j].subdev.entity.name, + ret); + return ret; + } + } + } + if (camss->ispif) { for (i = 0; i < camss->res->csid_num; i++) { for (j = 0; j < camss->ispif->line_num; j++) { @@ -5052,6 +5082,19 @@ static int camss_register_entities(struct camss *camss) } } + if (camss->tpg) { + for (i = 0; i < camss->res->tpg_num; i++) { + ret = msm_tpg_register_entity(&camss->tpg[i], + &camss->v4l2_dev); + if (ret < 0) { + dev_err(camss->dev, + "Failed to register tpg%d entity: %d\n", + i, ret); + goto err_reg_tpg; + } + } + } + for (i = 0; i < camss->res->csid_num; i++) { ret = msm_csid_register_entity(&camss->csid[i], &camss->v4l2_dev); @@ -5095,6 +5138,13 @@ static int camss_register_entities(struct camss *camss) for (i--; i >= 0; i--) msm_csid_unregister_entity(&camss->csid[i]); + i = camss->res->tpg_num; +err_reg_tpg: + if (camss->tpg) { + for (i--; i >= 0; i--) + msm_tpg_unregister_entity(&camss->tpg[i]); + } + i = camss->res->csiphy_num; err_reg_csiphy: for (i--; i >= 0; i--) { @@ -5120,6 +5170,11 @@ static void camss_unregister_entities(struct camss *camss) msm_csiphy_unregister_entity(&camss->csiphy[i]); } + if (camss->tpg) { + for (i = 0; i < camss->res->tpg_num; i++) + msm_tpg_unregister_entity(&camss->tpg[i]); + } + for (i = 0; i < camss->res->csid_num; i++) msm_csid_unregister_entity(&camss->csid[i]); From 77298ee858b91b92cf786c840a77780f1ef96aad Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Tue, 17 Mar 2026 18:05:47 +0800 Subject: [PATCH 0903/1330] FROMLIST: media: qcom: camss: tpg: Add TPG support for multiple targets Add support for TPG found on LeMans, Monaco, Hamoa. Link: https://lore.kernel.org/all/20260317-camss_tpg-v10-3-b4cfa85c2e1b@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # Dell Inpsiron14p Signed-off-by: Wenmeng Liu (cherry picked from commit 110a0016ea905690b5a71a3c9dd627910c20dfb3) --- drivers/media/platform/qcom/camss/Makefile | 1 + .../platform/qcom/camss/camss-csid-680.c | 14 +- .../platform/qcom/camss/camss-csid-gen3.c | 14 +- .../platform/qcom/camss/camss-tpg-gen1.c | 231 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss.c | 117 ++++++++- 5 files changed, 371 insertions(+), 6 deletions(-) create mode 100644 drivers/media/platform/qcom/camss/camss-tpg-gen1.c diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 8e4611d7fa652..b114ca37e36e2 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -17,6 +17,7 @@ qcom-camss-objs += \ camss-format.o \ camss-ispif.o \ camss-tpg.o \ + camss-tpg-gen1.o \ camss-vfe.o \ camss-vfe-4-1.o \ camss-vfe-4-7.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/media/platform/qcom/camss/camss-csid-680.c index 86134a23cd4e9..aed911d4d6df0 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-680.c +++ b/drivers/media/platform/qcom/camss/camss-csid-680.c @@ -102,6 +102,8 @@ #define CSI2_RX_CFG0_DL3_INPUT_SEL 16 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 #define CSI2_RX_CFG0_PHY_TYPE_SEL 24 +#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27) +#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28) #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN BIT(0) @@ -184,10 +186,20 @@ static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy, int vc) { u32 val; + struct camss *camss; + camss = csid->camss; val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; - val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL; + + if (camss->tpg && csid->tpg_linked && + camss->tpg[phy->csiphy_id].testgen.mode != TPG_PAYLOAD_MODE_DISABLED) { + val |= FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1); + val |= CSI2_RX_CFG0_TPG_MUX_EN; + } else { + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + } writel(val, csid->base + CSID_CSI2_RX_CFG0); diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c index 76a4b62eca1b8..0040109d7b850 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -66,6 +66,8 @@ #define CSI2_RX_CFG0_VC_MODE 3 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27) +#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28) #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -108,10 +110,20 @@ static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy, int vc) { int val; + struct camss *camss; + camss = csid->camss; val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; - val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL; + + if (camss->tpg && csid->tpg_linked && + camss->tpg[phy->csiphy_id].testgen.mode != TPG_PAYLOAD_MODE_DISABLED) { + val |= FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1); + val |= CSI2_RX_CFG0_TPG_MUX_EN; + } else { + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + } writel(val, csid->base + CSID_CSI2_RX_CFG0); diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c new file mode 100644 index 0000000000000..d29de5f93c18e --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG (Test Pattern Generator) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +/* TPG global registers */ +#define TPG_HW_VERSION 0x0 +# define HW_VERSION_STEPPING GENMASK(15, 0) +# define HW_VERSION_REVISION GENMASK(27, 16) +# define HW_VERSION_GENERATION GENMASK(31, 28) + +#define TPG_HW_VER(gen, rev, step) \ + (((u32)(gen) << 28) | ((u32)(rev) << 16) | (u32)(step)) + +#define TPG_HW_VER_2_0_0 TPG_HW_VER(2, 0, 0) +#define TPG_HW_VER_2_1_0 TPG_HW_VER(2, 1, 0) + +#define TPG_HW_STATUS 0x4 + +#define TPG_CTRL 0x64 +# define TPG_CTRL_TEST_EN BIT(0) +# define TPG_CTRL_PHY_SEL BIT(3) +# define TPG_CTRL_NUM_ACTIVE_LANES GENMASK(5, 4) +# define TPG_CTRL_VC_DT_PATTERN_ID GENMASK(8, 6) +# define TPG_CTRL_OVERLAP_SHDR_EN BIT(10) +# define TPG_CTRL_NUM_ACTIVE_VC GENMASK(31, 30) + +#define TPG_CLEAR 0x1F4 + +/* TPG VC-based registers */ +#define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) + +#define TPG_VC_n_CFG0(n) (0x68 + (n) * 0x60) +# define TPG_VC_n_CFG0_VC_NUM GENMASK(4, 0) +# define TPG_VC_n_CFG0_NUM_ACTIVE_DT GENMASK(9, 8) +# define TPG_VC_n_CFG0_NUM_BATCH GENMASK(15, 12) +# define TPG_VC_n_CFG0_NUM_FRAMES GENMASK(31, 16) + +#define TPG_VC_n_LSFR_SEED(n) (0x6C + (n) * 0x60) +#define TPG_VC_n_HBI_CFG(n) (0x70 + (n) * 0x60) +#define TPG_VC_n_VBI_CFG(n) (0x74 + (n) * 0x60) + +#define TPG_VC_n_COLOR_BARS_CFG(n) (0x78 + (n) * 0x60) +# define TPG_VC_n_COLOR_BARS_CFG_PIX_PATTERN GENMASK(2, 0) +# define TPG_VC_n_COLOR_BARS_CFG_QCFA_EN BIT(3) +# define TPG_VC_n_COLOR_BARS_CFG_SPLIT_EN BIT(4) +# define TPG_VC_n_COLOR_BARS_CFG_NOISE_EN BIT(5) +# define TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD GENMASK(13, 8) +# define TPG_VC_n_COLOR_BARS_CFG_XCFA_EN BIT(16) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_X GENMASK(26, 24) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_Y GENMASK(30, 28) + +/* TPG DT-based registers */ +#define TPG_VC_m_DT_n_CFG_0(m, n) (0x7C + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT GENMASK(15, 0) +# define TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_1(m, n) (0x80 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_1_DATA_TYPE GENMASK(5, 0) +# define TPG_VC_m_DT_n_CFG_1_ECC_XOR_MASK GENMASK(13, 8) +# define TPG_VC_m_DT_n_CFG_1_CRC_XOR_MASK GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_2(m, n) (0x84 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE GENMASK(3, 0) +/* v2.0.0: USER[19:4], ENC[23:20] */ +# define TPG_V2_0_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(19, 4) +# define TPG_V2_0_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(23, 20) +/* v2.1.0: USER[27:4], ENC[31:28] */ +# define TPG_V2_1_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(27, 4) +# define TPG_V2_1_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(31, 28) + +#define TPG_HBI_PCT_DEFAULT 545 /* 545% */ +#define TPG_VBI_PCT_DEFAULT 10 /* 10% */ +#define PERCENT_BASE 100 + +/* Default user-specified payload for TPG test generator. + * Keep consistent with CSID TPG default: 0xBE. + */ +#define TPG_USER_SPECIFIED_PAYLOAD_DEFAULT 0xBE +#define TPG_LFSR_SEED_DEFAULT 0x12345678 +#define TPG_COLOR_BARS_CFG_STANDARD \ + FIELD_PREP(TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD, 0xA) + +static const char * const testgen_payload_modes[] = { + [TPG_PAYLOAD_MODE_DISABLED] = "Disabled", + [TPG_PAYLOAD_MODE_INCREMENTING] = "Incrementing", + [TPG_PAYLOAD_MODE_ALTERNATING_55_AA] = "Alternating 0x55/0xAA", + [TPG_PAYLOAD_MODE_RANDOM] = "Pseudo-random Data", + [TPG_PAYLOAD_MODE_USER_SPECIFIED] = "User Specified", + [TPG_PAYLOAD_MODE_COLOR_BARS] = "Color bars", +}; + +static int tpg_stream_on(struct tpg_device *tpg) +{ + struct tpg_testgen_config *tg = &tpg->testgen; + struct v4l2_mbus_framefmt *input_format; + const struct tpg_format_info *format; + u8 payload_mode = (tg->mode > TPG_PAYLOAD_MODE_DISABLED) ? + tg->mode - 1 : 0; + u8 lane_cnt = tpg->res->lane_cnt; + u8 vc, dt, last_vc = 0; + u32 val; + + for (vc = 0; vc <= MSM_TPG_ACTIVE_VC; vc++) { + last_vc = vc; + + input_format = &tpg->fmt; + format = tpg_get_fmt_entry(tpg->res->formats->formats, + tpg->res->formats->nformats, + input_format->code); + if (IS_ERR(format)) + return -EINVAL; + + /* VC configuration */ + val = FIELD_PREP(TPG_VC_n_CFG0_NUM_ACTIVE_DT, MSM_TPG_ACTIVE_DT) | + FIELD_PREP(TPG_VC_n_CFG0_NUM_FRAMES, 0); + writel(val, tpg->base + TPG_VC_n_CFG0(vc)); + + writel(TPG_LFSR_SEED_DEFAULT, tpg->base + TPG_VC_n_LSFR_SEED(vc)); + + val = DIV_ROUND_UP(input_format->width * format->bpp * TPG_HBI_PCT_DEFAULT, + BITS_PER_BYTE * lane_cnt * PERCENT_BASE); + writel(val, tpg->base + TPG_VC_n_HBI_CFG(vc)); + + val = input_format->height * TPG_VBI_PCT_DEFAULT / PERCENT_BASE; + writel(val, tpg->base + TPG_VC_n_VBI_CFG(vc)); + + writel(TPG_COLOR_BARS_CFG_STANDARD, tpg->base + TPG_VC_n_COLOR_BARS_CFG(vc)); + + /* DT configuration */ + for (dt = 0; dt <= MSM_TPG_ACTIVE_DT; dt++) { + val = FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT, + input_format->height & 0xffff) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH, + input_format->width & 0xffff); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_0(vc, dt)); + + val = FIELD_PREP(TPG_VC_m_DT_n_CFG_1_DATA_TYPE, format->data_type); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_1(vc, dt)); + + if (tpg->hw_version == TPG_HW_VER_2_0_0) { + val = FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, payload_mode) | + FIELD_PREP(TPG_V2_0_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, + TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | + FIELD_PREP(TPG_V2_0_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT, + format->encode_format); + } else if (tpg->hw_version >= TPG_HW_VER_2_1_0) { + val = FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, payload_mode) | + FIELD_PREP(TPG_V2_1_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, + TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | + FIELD_PREP(TPG_V2_1_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT, + format->encode_format); + } + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_2(vc, dt)); + } + } + + /* Global TPG control */ + val = FIELD_PREP(TPG_CTRL_TEST_EN, 1) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, last_vc); + writel(val, tpg->base + TPG_CTRL); + + return 0; +} + +static int tpg_reset(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); + + return 0; +} + +static void tpg_stream_off(struct tpg_device *tpg) +{ + tpg_reset(tpg); +} + +static int tpg_configure_stream(struct tpg_device *tpg, u8 enable) +{ + if (enable) + return tpg_stream_on(tpg); + + tpg_stream_off(tpg); + + return 0; +} + +static int tpg_configure_testgen_pattern(struct tpg_device *tpg, s32 val) +{ + if (val >= 0 && val <= TPG_PAYLOAD_MODE_COLOR_BARS) + tpg->testgen.mode = val; + + return 0; +} + +static u32 tpg_hw_version(struct tpg_device *tpg) +{ + u32 hw_version = readl(tpg->base + TPG_HW_VERSION); + + tpg->hw_version = hw_version; + dev_dbg(tpg->camss->dev, "tpg HW Version = %u.%u.%u\n", + (u32)FIELD_GET(HW_VERSION_GENERATION, hw_version), + (u32)FIELD_GET(HW_VERSION_REVISION, hw_version), + (u32)FIELD_GET(HW_VERSION_STEPPING, hw_version)); + + return hw_version; +} + +static void tpg_subdev_init(struct tpg_device *tpg) +{ + tpg->testgen.modes = testgen_payload_modes; + tpg->testgen.nmodes = TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; +} + +const struct tpg_hw_ops tpg_ops_gen1 = { + .configure_stream = tpg_configure_stream, + .configure_testgen_pattern = tpg_configure_testgen_pattern, + .hw_version = tpg_hw_version, + .reset = tpg_reset, + .subdev_init = tpg_subdev_init, +}; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 520a4c905e7d2..675f4dee6a7e5 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3916,6 +3916,54 @@ static const struct camss_subdev_resources csiphy_res_8775p[] = { }, }; +static const struct camss_subdev_resources tpg_res_8775p[] = { + /* TPG0 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "tpg0" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, + /* TPG1 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "tpg1" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, + /* TPG2 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "tpg2" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_8775p[] = { /* CSID0 */ { @@ -4284,6 +4332,54 @@ static const struct camss_subdev_resources csiphy_res_x1e80100[] = { }, }; +static const struct camss_subdev_resources tpg_res_x1e80100[] = { + /* TPG0 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csid_csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "csitpg0" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, + /* TPG1 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csid_csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "csitpg1" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, + /* TPG2 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csid_csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "csitpg2" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_x1e80100[] = { /* CSID0 */ { @@ -4397,7 +4493,7 @@ static const struct camss_subdev_resources vfe_res_x1e80100[] = { .clock = {"camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", "cpas_fast_ahb", "cpas_vfe0", "vfe0_fast_ahb", "vfe0" }, - .clock_rate = { { 0 }, + .clock_rate = { { 400000000 }, { 0 }, { 0 }, { 0 }, @@ -4421,7 +4517,7 @@ static const struct camss_subdev_resources vfe_res_x1e80100[] = { .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", "cpas_fast_ahb", "cpas_vfe1", "vfe1_fast_ahb", "vfe1" }, - .clock_rate = { { 0 }, + .clock_rate = { { 400000000 }, { 0 }, { 0 }, { 0 }, @@ -4445,7 +4541,7 @@ static const struct camss_subdev_resources vfe_res_x1e80100[] = { .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite", "vfe_lite_csid" }, - .clock_rate = { { 0 }, + .clock_rate = { { 400000000 }, { 0 }, { 0 }, { 0 }, @@ -4468,7 +4564,7 @@ static const struct camss_subdev_resources vfe_res_x1e80100[] = { .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite", "vfe_lite_csid" }, - .clock_rate = { { 0 }, + .clock_rate = { { 400000000 }, { 0 }, { 0 }, { 0 }, @@ -5395,6 +5491,13 @@ static int camss_probe(struct platform_device *pdev) if (!camss->csiphy) return -ENOMEM; + if (camss->res->tpg_num > 0) { + camss->tpg = devm_kcalloc(dev, camss->res->tpg_num, + sizeof(*camss->tpg), GFP_KERNEL); + if (!camss->tpg) + return -ENOMEM; + } + camss->csid = devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->csid), GFP_KERNEL); if (!camss->csid) @@ -5603,11 +5706,13 @@ static const struct camss_resources qcs8300_resources = { .pd_name = "top", .legacy_phy = true, .csiphy_res = csiphy_res_8300, + .tpg_res = tpg_res_8775p, .csid_res = csid_res_8775p, .csid_wrapper_res = &csid_wrapper_res_sm8550, .vfe_res = vfe_res_8775p, .icc_res = icc_res_qcs8300, .csiphy_num = ARRAY_SIZE(csiphy_res_8300), + .tpg_num = ARRAY_SIZE(tpg_res_8775p), .csid_num = ARRAY_SIZE(csid_res_8775p), .vfe_num = ARRAY_SIZE(vfe_res_8775p), .icc_path_num = ARRAY_SIZE(icc_res_qcs8300), @@ -5618,11 +5723,13 @@ static const struct camss_resources sa8775p_resources = { .pd_name = "top", .legacy_phy = true, .csiphy_res = csiphy_res_8775p, + .tpg_res = tpg_res_8775p, .csid_res = csid_res_8775p, .csid_wrapper_res = &csid_wrapper_res_sm8550, .vfe_res = vfe_res_8775p, .icc_res = icc_res_sa8775p, .csiphy_num = ARRAY_SIZE(csiphy_res_8775p), + .tpg_num = ARRAY_SIZE(tpg_res_8775p), .csid_num = ARRAY_SIZE(csid_res_8775p), .vfe_num = ARRAY_SIZE(vfe_res_8775p), .icc_path_num = ARRAY_SIZE(icc_res_sa8775p), @@ -5754,12 +5861,14 @@ static const struct camss_resources x1e80100_resources = { .version = CAMSS_X1E80100, .pd_name = "top", .csiphy_res = csiphy_res_x1e80100, + .tpg_res = tpg_res_x1e80100, .csid_res = csid_res_x1e80100, .vfe_res = vfe_res_x1e80100, .csid_wrapper_res = &csid_wrapper_res_x1e80100, .icc_res = icc_res_x1e80100, .icc_path_num = ARRAY_SIZE(icc_res_x1e80100), .csiphy_num = ARRAY_SIZE(csiphy_res_x1e80100), + .tpg_num = ARRAY_SIZE(tpg_res_x1e80100), .csid_num = ARRAY_SIZE(csid_res_x1e80100), .vfe_num = ARRAY_SIZE(vfe_res_x1e80100), }; From cd1c8b7aed716695be4411cef27254593bfe1773 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 10 Apr 2026 12:25:31 +0800 Subject: [PATCH 0904/1330] FROMLIST: dt-bindings: media: Add bindings for qcom,x1p42100-camss Add bindings for the Camera Subsystem for X1P42100. The X1P42100 platform provides: - 2 x CSIPHY - 3 x TPG - 3 x CSID - 2 x CSID Lite - 1 x IFE - 2 x IFE Lite Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-1-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu (cherry picked from commit dfee7c2902974d8e1dc81f11d0c92297f0cadd54) --- .../bindings/media/qcom,x1p42100-camss.yaml | 424 ++++++++++++++++++ 1 file changed, 424 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml new file mode 100644 index 0000000000000..8bfa7e616c3b6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml @@ -0,0 +1,424 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,x1p42100-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1P42100 Camera Subsystem (CAMSS) + +maintainers: + - Wenmeng Liu + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,x1p42100-camss + + reg: + maxItems: 14 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy4 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe0 + - const: vfe_lite0 + - const: vfe_lite1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + ranges: true + + clocks: + maxItems: 22 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe_lite + - const: cphy_rx_clk_src + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy4 + - const: csiphy4_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 10 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy4 + - const: vfe0 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + oneOf: + - items: + - description: S1 HLOS IFE and IFE_LITE non-protected read + - description: S1 HLOS IFE and IFE_LITE non-protected write + - description: S1 HLOS SFE non-protected read + - description: S1 HLOS SFE non-protected write + - description: S1 HLOS CDM IFE non-protected + - description: Legacy slot 0 - do not use + - description: Legacy slot 1 - do not use + - description: Legacy slot 2 - do not use + - items: + - description: S1 HLOS IFE and IFE_LITE non-protected read + - description: S1 HLOS IFE and IFE_LITE non-protected write + - description: S1 HLOS SFE non-protected read + - description: S1 HLOS SFE non-protected write + - description: S1 HLOS CDM IFE non-protected + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: top + + vdd-csiphy-0p8-supply: + description: + 0.8V supply to a PHY. + + vdd-csiphy-1p2-supply: + description: + 1.2V supply to a PHY. + + phys: + maxItems: 2 + + phy-names: + items: + - const: csiphy0 + - const: csiphy4 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. Supports either standard single sensor mode or + Qualcomm's combo mode with one sensor in 2x1 + 1x1 data-lane, clock-lane mode. + + patternProperties: + "^port@[0-3]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data. + + properties: + endpoint@0: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + description: + Endpoint for receiving a single sensor input (or first leg of combo). + + properties: + data-lanes: + minItems: 1 + maxItems: 4 # Base max allows 4 (for D-PHY) + + clock-lanes: + maxItems: 1 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + endpoint@1: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + description: + Endpoint for receiving the second leg of a combo sensor input. + + properties: + data-lanes: + maxItems: 1 + + clock-lanes: + maxItems: 1 + + bus-type: + const: 4 # Combo is D-PHY specific + + required: + - data-lanes + + allOf: + # Case 1: Combo Mode (endpoint@1 is present) + # If endpoint@1 exists, we restrict endpoint@0 to 2 lanes (D-PHY split) + - if: + required: + - endpoint@1 + then: + properties: + endpoint@0: + properties: + data-lanes: + minItems: 2 + maxItems: 2 + bus-type: + const: 4 + endpoint@1: + properties: + data-lanes: + minItems: 1 + maxItems: 1 + bus-type: + const: 4 + + # Case 2: Single Mode (endpoint@1 is missing) + # We explicitly allow up to 4 lanes here to cover the D-PHY use case. + - if: + not: + required: + - endpoint@1 + then: + properties: + endpoint@0: + properties: + data-lanes: + minItems: 1 + maxItems: 4 + +patternProperties: + "^phy@[0-9a-f]+$": + $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml + unevaluatedProperties: false + + "^opp-table(-.*)?$": + type: object + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: isp@acb7000 { + compatible = "qcom,x1p42100-camss"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe_lite0", + "vfe_lite1"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy4", + "vfe0", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x820 0x60>, + <&apps_smmu 0x840 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x18a0 0x0>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domain-names = "ife0", + "top"; + + vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; + vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csiphy_ep0: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; From 40427a7afc59fd8c3fe5ec9aca8615356221e871 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 10 Apr 2026 12:25:32 +0800 Subject: [PATCH 0905/1330] FROMLIST: media: qcom: camss: add support for X1P42100 camss The Purwa camera subsystem is a cut-down variant of the Hamoa CAMSS. Compared to Hamoa, Purwa provides only two CSIPHY instances and does not include the VFE1. Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-2-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu (cherry picked from commit aac9b784879aa69c88d34d43102e9e558e5b24fb) --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 2 + drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 109 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 4 files changed, 114 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index c51ffcd93ce18..ed1f6b6f2f953 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1138,6 +1138,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: + case CAMSS_X1P42100: ret = true; break; } @@ -1233,6 +1234,7 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp); break; case CAMSS_X1E80100: + case CAMSS_X1P42100: regs->lane_regs = &lane_regs_x1e80100[0]; regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100); regs->offset = 0x1000; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 99630ffa1db57..ad2aa93bd8000 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -354,6 +354,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: + case CAMSS_X1P42100: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -2017,6 +2018,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: + case CAMSS_X1P42100: ret = 16; break; default: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 675f4dee6a7e5..4df05fb2d685b 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4610,6 +4610,98 @@ static const struct resources_wrapper csid_wrapper_res_x1e80100 = { .reg = "csid_wrapper", }; +static const struct camss_subdev_resources csiphy_res_x1p42100[] = { + /* CSIPHY0 */ + { + .csiphy = { + .id = 0, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + }, + }, + /* CSIPHY4 */ + { + .csiphy = { + .id = 4, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + }, + }, +}; + +static const struct camss_subdev_resources vfe_res_x1p42100[] = { + /* IFE0 */ + { + .regulators = {}, + .clock = {"camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", + "cpas_fast_ahb", "cpas_vfe0", "vfe0_fast_ahb", + "vfe0" }, + .clock_rate = { { 400000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 345600000, 432000000, 594000000, 675000000, + 727000000 }, }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 4, + .pd_name = "ife0", + .hw_ops = &vfe_ops_680, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + }, + }, + /* IFE_LITE_0 */ + { + .regulators = {}, + .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", + "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite", + "vfe_lite_csid" }, + .clock_rate = { { 400000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 266666667, 400000000, 480000000 }, }, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" }, + .vfe = { + .is_lite = true, + .line_num = 4, + .hw_ops = &vfe_ops_680, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + }, + }, + /* IFE_LITE_1 */ + { + .regulators = {}, + .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", + "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite", + "vfe_lite_csid" }, + .clock_rate = { { 400000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 266666667, 400000000, 480000000 }, }, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" }, + .vfe = { + .is_lite = true, + .line_num = 4, + .hw_ops = &vfe_ops_680, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + }, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -5873,6 +5965,22 @@ static const struct camss_resources x1e80100_resources = { .vfe_num = ARRAY_SIZE(vfe_res_x1e80100), }; +static const struct camss_resources x1p42100_resources = { + .version = CAMSS_X1P42100, + .pd_name = "top", + .csiphy_res = csiphy_res_x1p42100, + .tpg_res = tpg_res_x1e80100, + .csid_res = csid_res_x1e80100, + .vfe_res = vfe_res_x1p42100, + .csid_wrapper_res = &csid_wrapper_res_x1e80100, + .icc_res = icc_res_x1e80100, + .icc_path_num = ARRAY_SIZE(icc_res_x1e80100), + .csiphy_num = ARRAY_SIZE(csiphy_res_x1p42100), + .tpg_num = ARRAY_SIZE(tpg_res_x1e80100), + .csid_num = ARRAY_SIZE(csid_res_x1e80100), + .vfe_num = ARRAY_SIZE(vfe_res_x1p42100), +}; + static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,kaanapali-camss", .data = &kaanapali_resources }, { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, @@ -5892,6 +6000,7 @@ static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources }, { .compatible = "qcom,sm8650-camss", .data = &sm8650_resources }, { .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources }, + { .compatible = "qcom,x1p42100-camss", .data = &x1p42100_resources }, { } }; diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index bfe45d8f01eaa..ff318b334eec8 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -97,6 +97,7 @@ enum camss_version { CAMSS_8775P, CAMSS_KAANAPALI, CAMSS_X1E80100, + CAMSS_X1P42100, }; enum icc_count { From c01d2eda8cf6d41be4fb8c7d5ef1c48a3722e09d Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 29 Apr 2026 19:44:58 +0530 Subject: [PATCH 0906/1330] FROMLIST: arm64: dts: qcom: glymur: Add camera clock controller support Add support for camera clock controller for camera clients to be able to request for camera clocks on Glymur SoC's. Link: https://lore.kernel.org/r/20260429-glymur_camcc-v2-3-0c3fd1977869@oss.qualcomm.com Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Signed-off-by: Taniya Das (cherry picked from commit 9251e2445a53df7f065cd6b016a67800b66ca2d4) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 185f57d6127b7..560c2d2287b81 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3,6 +3,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include #include #include #include @@ -5321,6 +5322,22 @@ }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,glymur-camcc"; + reg = <0x0 0x0ade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,glymur-mdss"; reg = <0x0 0x0ae00000 0x0 0x1000>; From cca0fe6d0e923bea733eed292c3246ce6304307a Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Thu, 9 Apr 2026 16:11:55 +0530 Subject: [PATCH 0907/1330] dt-bindings: media: qcom,qcm2290-venus: document shikra Iris compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the Iris video accelerator used on Shikra platforms by adding the qcom,shikra-iris compatible. Although QCM2290 and Shikra share the same video hardware and overall integration, their SMMU programming differs. QCM2290 exposes separate Stream IDs for the video hardware and the Xtensa path, requiring two explicit IOMMU entries, whereas Shikra uses a masked SMR to collapse equivalent Stream IDs into a single mapping. Due to QCM2290’s SID layout and Xtensa isolation requirements, such SMR masking is not applicable on QCM2290 platforms. Since Shikra uses the same video hardware as QCM2290 and shares the same programming model and capabilities, it is added as a fallback compatible to qcom,qcm2290-venus, with conditional handling to allow either one or two IOMMU entries. Signed-off-by: Dikshita Agarwal (cherry picked from commit c3b3cbe560d7424b604cc37f25222bbda727aafd) --- .../bindings/media/qcom,qcm2290-venus.yaml | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml index 7e6dc410c2d2b..10713164c2d80 100644 --- a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml @@ -15,10 +15,27 @@ description: allOf: - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + contains: + const: qcom,shikra-iris + then: + properties: + iommus: + maxItems: 1 + else: + properties: + iommus: + maxItems: 2 properties: compatible: - const: qcom,qcm2290-venus + oneOf: + - items: + - const: qcom,shikra-iris + - const: qcom,qcm2290-venus + - const: qcom,qcm2290-venus power-domains: maxItems: 3 @@ -41,9 +58,6 @@ properties: - const: vcodec0_core - const: vcodec0_bus - iommus: - maxItems: 2 - interconnects: maxItems: 2 From 0d28d14719d32d6ea4f86219de28bb7e77609a5b Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 8 May 2026 21:56:00 +0800 Subject: [PATCH 0908/1330] arm64: dts: qcom: shikra: Add coresight nodes Add DT nodes for the CoreSight debug and trace subsystem on Qualcomm Shikra SoC. Signed-off-by: Jie Gan (cherry picked from commit 177649904d9b464e6f174486755993994c4b83c6) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 1490 ++++++++++++++++++++++++-- 1 file changed, 1388 insertions(+), 102 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 649e9f87c7b6e..d17a1bbd41cd9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -109,6 +109,20 @@ }; }; + dummy-eud { + compatible = "arm,coresight-dummy-sink"; + + label = "eud"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = <&replicator_eud_out1>; + }; + }; + }; + }; + firmware { scm { compatible = "qcom,scm-shikra", "qcom,scm"; @@ -124,6 +138,21 @@ reg = <0x0 0xa0000000 0x0 0x0>; }; + modem-etm0 { + compatible = "arm,coresight-dummy-source"; + + label = "modem_etm0"; + arm,static-trace-id = <36>; + + out-ports { + port { + modem_etm0_out: endpoint { + remote-endpoint = <&funnel_in1_in4>; + }; + }; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2253,150 +2282,1407 @@ }; }; - remoteproc_cdsp: remoteproc@b300000 { - compatible = "qcom,shikra-cdsp-pas"; - reg = <0x0 0x0b300000 0x0 0x100000>; + ctcu@8001000 { + compatible = "qcom,shikra-ctcu","qcom,sa8775p-ctcu"; + reg = <0x0 0x08001000 0x0 0x1000>; - interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack", - "shutdown-ack"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb"; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; + in-ports { + port { + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + }; + }; - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + stm@8002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x08002000 0x0 0x1000>, + <0x0 0x0e280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; - power-domains = <&rpmpd RPMHPD_CX>; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; - memory-region = <&cdsp_mem>; + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in7>; + }; + }; + }; + }; - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; + tpdm@8003000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08003000 0x0 0x1000>; - status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; - glink-edge { - interrupts = ; - mboxes = <&apcs_glb 4>; - qcom,remote-pid = <5>; - label = "cdsp"; + label = "tpdm_dcc"; + qcom,cmb-element-bits = <32>; - fastrpc { - compatible = "qcom,fastrpc"; - #address-cells = <1>; - #size-cells = <0>; - label = "cdsp"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; + out-ports { + port { + tpdm_dcc_out: endpoint { + remote-endpoint = <&tpda_qdss_in0>; + }; + }; + }; + }; - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0201 0x0000>; + tpda@8004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x08004000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_qdss_in0: endpoint { + remote-endpoint = <&tpdm_dcc_out>; }; + }; - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0202 0x0000>; + port@1 { + reg = <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint = <&tpdm_spdm_out>; }; + }; + }; - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0203 0x0000>; + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint = <&funnel_in0_in6>; }; + }; + }; + }; - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x0204 0x0000>; + tpdm@800f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x0800f000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_spdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint = <&tpda_qdss_in1>; }; + }; + }; + }; - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x0205 0x0000>; + funnel@8041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08041000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + + funnel_in0_in5: endpoint { + remote-endpoint = <&snoc_out>; }; + }; - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x0206 0x0000>; + port@6 { + reg = <6>; + + funnel_in0_in6: endpoint { + remote-endpoint = <&tpda_qdss_out>; }; + }; - compute-cb@9 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <9>; - iommus = <&apps_smmu 0x0209 0x0000>; + port@7 { + reg = <7>; + + funnel_in0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&funnel_merg_in0>; }; }; }; }; - remoteproc_lpaicp: remoteproc@b800000 { - compatible = "qcom,shikra-lpaicp-pas"; - reg = <0x0 0x0b800000 0x0 0x200000>; + funnel@8042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08042000 0x0 0x1000>; - interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, - <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, - <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, - <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, - <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; + in-ports { + #address-cells = <1>; + #size-cells = <0>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; + port@1 { + reg = <1>; - memory-region = <&lmcu_mem &lmcu_dtb_mem>; + funnel_in1_in1: endpoint { + remote-endpoint = <&tpda_aodbg_out>; + }; + }; - qcom,smem-states = <&lmcu_smp2p_out 0>; - qcom,smem-state-names = "stop"; + port@4 { + reg = <4>; - status = "disabled"; + funnel_in1_in4: endpoint { + remote-endpoint = <&modem_etm0_out>; + }; + }; - glink-edge { - interrupts = ; - mboxes = <&apcs_glb 9>; - qcom,remote-pid = <26>; - label = "lpaicp"; + port@6 { + reg = <6>; + + funnel_in1_in6: endpoint { + remote-endpoint = <&funnel_cpuss1_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_in1_in7: endpoint { + remote-endpoint = <&funnel_center_out>; + }; + }; + }; + + out-ports { + port { + funnel_in1_out: endpoint { + remote-endpoint = <&funnel_merg_in1>; + }; + }; }; }; - cpufreq_hw: cpufreq@fd91000 { - compatible = "qcom,shikra-cpufreq-rimps", "qcom,cpufreq-rimps"; - reg = <0x0 0x0fd91000 0x0 0x1000>, - <0x0 0x0fd92000 0x0 0x1000>; - reg-names = "freq-domain0", - "freq-domain1"; + funnel@8045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08045000 0x0 0x1000>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; - interrupts = , - ; - interrupt-names = "dcvsh-irq-0", - "dcvsh-irq-1"; + in-ports { + #address-cells = <1>; + #size-cells = <0>; - #freq-domain-cells = <1>; + port@0 { + reg = <0>; + + funnel_merg_in0: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + port@1 { + reg = <1>; + + funnel_merg_in1: endpoint { + remote-endpoint = <&funnel_in1_out>; + }; + }; + }; + + out-ports { + port { + funnel_merg_out: endpoint { + remote-endpoint = <&tmc_etf_in>; + }; + }; + }; + }; + + replicator@8046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x08046000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_qdss_in: endpoint { + remote-endpoint = <&tmc_etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + replicator_qdss_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + replicator_qdss_out1: endpoint { + remote-endpoint = <&replicator_eud_in>; + }; + }; + }; + }; + + tmc@8047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x08047000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint = <&funnel_merg_out>; + }; + }; + }; + + out-ports { + port { + tmc_etf_out: endpoint { + remote-endpoint = <&replicator_qdss_in>; + }; + }; + }; + }; + + tmc@8048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x08048000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x0160 0x0>; + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&replicator_qdss_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; }; + replicator@804a000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x0804a000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_eud_in: endpoint { + remote-endpoint = <&replicator_qdss_out1>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + replicator_eud_out1: endpoint { + remote-endpoint = <&eud_in>; + }; + }; + }; + }; + + tpdm@8800000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08800000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_cdsp"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <4>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint = <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@8801000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08801000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint = <&tpdm_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out0: endpoint { + remote-endpoint = <&tpda_center_in3>; + }; + }; + }; + }; + + cti@8807000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08807000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_turing_q6"; + }; + + cti@8833000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08833000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_mss_q6"; + }; + + tpdm@8840000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08840000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_vsense"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_vsense_out: endpoint { + remote-endpoint = <&tpda_center_in6>; + }; + }; + }; + }; + + tpdm@8844000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08844000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_dlct_1"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_dlct_1_out: endpoint { + remote-endpoint = <&tpda_center_in13>; + }; + }; + }; + }; + + tpda@8845000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x08845000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_center_in0: endpoint { + remote-endpoint = <&funnel_mcu_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_center_in2: endpoint { + remote-endpoint = <&tpdm_dlct_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_center_in3: endpoint { + remote-endpoint = <&funnel_cdsp_out0>; + }; + }; + + port@4 { + reg = <4>; + + tpda_center_in4: endpoint { + remote-endpoint = <&funnel_ddr_out0>; + }; + }; + + port@6 { + reg = <6>; + + tpda_center_in6: endpoint { + remote-endpoint = <&tpdm_vsense_out>; + }; + }; + + port@7 { + reg = <7>; + + tpda_center_in7: endpoint { + remote-endpoint = <&tpdm_prng_out>; + }; + }; + + port@8 { + reg = <8>; + + tpda_center_in8: endpoint { + remote-endpoint = <&tpdm_west_out>; + }; + }; + + port@9 { + reg = <9>; + + tpda_center_in9: endpoint { + remote-endpoint = <&tpdm_qm_out>; + }; + }; + + port@a { + reg = <0xa>; + + tpda_center_in10: endpoint { + remote-endpoint = <&tpdm_pimem_out>; + }; + }; + + port@d { + reg = <0xd>; + + tpda_center_in13: endpoint { + remote-endpoint = <&tpdm_dlct_1_out>; + }; + }; + }; + + out-ports { + port { + tpda_center_out: endpoint { + remote-endpoint = <&funnel_center_in0>; + }; + }; + }; + }; + + funnel@8846000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08846000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_center_in0: endpoint { + remote-endpoint = <&tpda_center_out>; + }; + }; + }; + + out-ports { + port { + funnel_center_out: endpoint { + remote-endpoint = <&funnel_in1_in7>; + }; + }; + }; + }; + + tpdm@884c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x0884c000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_prng"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_prng_out: endpoint { + remote-endpoint = <&tpda_center_in7>; + }; + }; + }; + }; + + tpdm@8850000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08850000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_pimem"; + qcom,cmb-element-bits = <64>; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + tpdm_pimem_out: endpoint { + remote-endpoint = <&tpda_center_in10>; + }; + }; + }; + }; + + tpdm@8980000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08980000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_mcu"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <16>; + + out-ports { + port { + tpdm_mcu_out: endpoint { + remote-endpoint = <&funnel_mcu_in0>; + }; + }; + }; + }; + + funnel@8982000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08982000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_mcu_in0: endpoint { + remote-endpoint = <&tpdm_mcu_out>; + }; + }; + }; + + out-ports { + port { + funnel_mcu_out: endpoint { + remote-endpoint = <&tpda_center_in0>; + }; + }; + }; + }; + + tpdm@89d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x089d0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_qm"; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint = <&tpda_center_in9>; + }; + }; + }; + }; + + tpdm@8a01000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08a01000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_mapss"; + qcom,cmb-element-bits = <32>; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <16>; + + out-ports { + port { + tpdm_mapss_out: endpoint { + remote-endpoint = <&tpda_aodbg_in>; + }; + }; + }; + }; + + cti@8a02000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08a02000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_mapss"; + }; + + tpda@8a04000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x08a04000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tpda_aodbg_in: endpoint { + remote-endpoint = <&tpdm_mapss_out>; + }; + }; + }; + + out-ports { + port { + tpda_aodbg_out: endpoint { + remote-endpoint = <&funnel_in1_in1>; + }; + }; + }; + }; + + tpdm@8a58000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08a58000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_west"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <16>; + + out-ports { + port { + tpdm_west_out: endpoint { + remote-endpoint = <&tpda_center_in8>; + }; + }; + }; + }; + + cti@8b30000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b30000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_cortex_m3"; + }; + + tpdm@8b58000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08b58000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_dlct"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <16>; + + out-ports { + port { + tpdm_dlct_out: endpoint { + remote-endpoint = <&tpda_center_in2>; + }; + }; + }; + }; + + cti@8b59000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b59000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_dlct_0"; + }; + + cti@8b5a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b5a000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_dlct_1"; + }; + + cti@8b5b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b5b000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_dlct_2"; + }; + + cti@8b5c000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b5c000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_dlct_3"; + }; + + tpdm@8b60000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08b60000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_ddr"; + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <1>; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_ddr_out: endpoint { + remote-endpoint = <&funnel_ddr_in0>; + }; + }; + }; + }; + + cti@8b62000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b62000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_ddr_dl_0"; + }; + + funnel@8b65000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08b65000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_ddr_in0: endpoint { + remote-endpoint = <&tpdm_ddr_out>; + }; + }; + }; + + out-ports { + port { + funnel_ddr_out0: endpoint { + remote-endpoint = <&tpda_center_in4>; + }; + }; + }; + }; + + cti@8b70000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b70000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_ddr_dl_0_1"; + }; + + cti@8b71000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b71000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_ddr_dl_1_1"; + }; + + cti@9020000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09020000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_pe0"; + }; + + etm@9040000 { + compatible = "arm,coresight-etm4x-sysreg"; + reg = <0x0 0x09040000 0x0 0x1000>; + cpu = <&cpu0>; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_cpuss0_in0>; + }; + }; + }; + }; + + cti@90e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x090e0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_cluster"; + }; + + cti@9120000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09120000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_pe1"; + }; + + etm@9140000 { + compatible = "arm,coresight-etm4x-sysreg"; + reg = <0x0 0x09140000 0x0 0x1000>; + cpu = <&cpu1>; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_cpuss0_in1>; + }; + }; + }; + }; + + cti@9220000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09220000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_pe2"; + }; + + etm@9240000 { + compatible = "arm,coresight-etm4x-sysreg"; + reg = <0x0 0x09240000 0x0 0x1000>; + cpu = <&cpu2>; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_cpuss0_in2>; + }; + }; + }; + }; + + cti@9320000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09320000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_pe3"; + }; + + etm@9340000 { + compatible = "arm,coresight-etm4x-sysreg"; + reg = <0x0 0x09340000 0x0 0x1000>; + cpu = <&cpu3>; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_cpuss0_in3>; + }; + }; + }; + }; + + funnel@9800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x09800000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_cpuss0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + + funnel_cpuss0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + + funnel_cpuss0_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + + funnel_cpuss0_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + funnel_cpuss0_out: endpoint { + remote-endpoint = <&funnel_cpuss1_in0>; + }; + }; + }; + }; + + funnel@9810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x09810000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_cpuss1_in0: endpoint { + remote-endpoint = <&funnel_cpuss0_out>; + }; + }; + + port@3 { + reg = <3>; + + funnel_cpuss1_in3: endpoint { + remote-endpoint = <&tpda_apss_out>; + }; + }; + }; + + out-ports { + port { + funnel_cpuss1_out: endpoint { + remote-endpoint = <&funnel_in1_in6>; + }; + }; + }; + }; + + cti@982b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x0982b000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_riscv"; + }; + + tpdm@9860000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x09860000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_actpm"; + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <1>; + + out-ports { + port { + tpdm_actpm_out: endpoint { + remote-endpoint = <&tpda_apss_in2>; + }; + }; + }; + }; + + tpdm@9861000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x09861000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_hwe"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_hwe_out: endpoint { + remote-endpoint = <&tpda_apss_in3>; + }; + }; + }; + }; + + tpda@9863000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x09863000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_apss_in0: endpoint { + remote-endpoint = <&tpdm_llm_silver_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_apss_in2: endpoint { + remote-endpoint = <&tpdm_actpm_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_apss_in3: endpoint { + remote-endpoint = <&tpdm_hwe_out>; + }; + }; + }; + + out-ports { + port { + tpda_apss_out: endpoint { + remote-endpoint = <&funnel_cpuss1_in3>; + }; + }; + }; + }; + + tpdm@98a0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x098a0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_llm_silver"; + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <12>; + + out-ports { + port { + tpdm_llm_silver_out: endpoint { + remote-endpoint = <&tpda_apss_in0>; + }; + }; + }; + }; + + cti@98e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x098e0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_0"; + }; + + cti@98f0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x098f0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_1"; + }; + + cti@9900000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09900000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_2"; + }; + + remoteproc_cdsp: remoteproc@b300000 { + compatible = "qcom,shikra-cdsp-pas"; + reg = <0x0 0x0b300000 0x0 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 4>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,fastrpc"; + #address-cells = <1>; + #size-cells = <0>; + label = "cdsp"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0201 0x0000>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0202 0x0000>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0203 0x0000>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0204 0x0000>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0205 0x0000>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0206 0x0000>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x0209 0x0000>; + }; + }; + }; + }; + + remoteproc_lpaicp: remoteproc@b800000 { + compatible = "qcom,shikra-lpaicp-pas"; + reg = <0x0 0x0b800000 0x0 0x200000>; + + interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, + <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>; + + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&lmcu_mem &lmcu_dtb_mem>; + + qcom,smem-states = <&lmcu_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 9>; + qcom,remote-pid = <26>; + label = "lpaicp"; + }; + }; + + cpufreq_hw: cpufreq@fd91000 { + compatible = "qcom,shikra-cpufreq-rimps", "qcom,cpufreq-rimps"; + reg = <0x0 0x0fd91000 0x0 0x1000>, + <0x0 0x0fd92000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1"; + + #freq-domain-cells = <1>; + }; + }; + + snoc { + compatible = "arm,coresight-dummy-source"; + arm,static-trace-id = <18>; + + label = "snoc"; + + out-ports { + port { + snoc_out: endpoint { + remote-endpoint = <&funnel_in0_in5>; + }; + }; + }; }; thermal_zones: thermal-zones { From 081fa05a4d22b45e721158339e7d9601630d3dd7 Mon Sep 17 00:00:00 2001 From: Yepuri Siddu Date: Wed, 13 May 2026 12:17:18 +0530 Subject: [PATCH 0909/1330] arm64: dts: qcom: shikra: Enable BT support on EVK boards. Enable uart8 and add WCN3988 Bluetooth node with board-specific regulator supplies across CQM, CQS and IQS Shikra EVK variants. Signed-off-by: Yepuri Siddu (cherry picked from commit a635c96813435159d424646500e4abbee0f3061a) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 12 ++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 12 ++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 12 ++++++++++++ arch/arm64/boot/dts/qcom/shikra.dtsi | 8 ++++++++ 4 files changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index e864b995443ef..05b450bd2acdf 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -18,6 +18,7 @@ mmc0 = &sdhc_1; mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &uart0; + serial1 = &uart8; }; chosen { @@ -88,6 +89,17 @@ status = "okay"; }; +&uart8 { + status = "okay"; + + bluetooth { + vddio-supply = <&pm4125_l7>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + }; +}; + &usb_1 { dr_mode = "otg"; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 47f0dfeb6b627..d12c897a9e71f 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -18,6 +18,7 @@ mmc0 = &sdhc_1; mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &uart0; + serial1 = &uart8; }; chosen { @@ -82,6 +83,17 @@ status = "okay"; }; +&uart8 { + status = "okay"; + + bluetooth { + vddio-supply = <&pm4125_l7>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + }; +}; + &usb_1 { dr_mode = "otg"; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 52862e4e2f57d..fb60b0a5ba0ab 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -18,6 +18,7 @@ mmc0 = &sdhc_1; mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &uart0; + serial1 = &uart8; }; chosen { @@ -84,6 +85,17 @@ status = "okay"; }; +&uart8 { + status = "okay"; + + bluetooth { + vddio-supply = <&pm8150_s4>; + vddxo-supply = <&pm8150_l12>; + vddrf-supply = <&pm8150_l8>; + vddch0-supply = <&vreg_wlan_3p3_dummy>; + }; +}; + &usb_1 { dr_mode = "peripheral"; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index d17a1bbd41cd9..993945305da91 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -2183,6 +2183,14 @@ pinctrl-names = "default"; status = "disabled"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + + enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + max-speed = <3200000>; + }; + }; i2c9: i2c@4aa4000 { From bf58b184c1af3372bee9e14f8d878dfe624a6f74 Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Mon, 11 May 2026 16:00:01 +0530 Subject: [PATCH 0910/1330] arm64: dts: qcom: shikra: Add MDSS display subsystem Add the SoC-level display subsystem nodes for Shikra: MDSS wrapper, DPU display controller, DSI host controller, and 14nm DSI PHY. Shikra uses DPU 6.5 hardware (same as QCM2290), with platform-specific compatibles qcom,shikra-dpu and qcom,shikra-dsi-ctrl. The dispcc clock inputs for the DSI byte and pixel PLLs are wired from mdss_dsi0_phy. Signed-off-by: Mahadevan P (cherry picked from commit ec9dcf0c48a68b2d5d20812331f8956a42679520) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 202 ++++++++++++++++++++++++++- 1 file changed, 200 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 993945305da91..441d1f510a269 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -1292,14 +1293,211 @@ }; }; + mdss: display-subsystem@5e00000 { + compatible = "qcom,shikra-mdss"; + reg = <0x0 0x05e00000 0x0 0x1000>; + reg-names = "mdss"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x420 0x2>; + interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdp: display-controller@5e01000 { + compatible = "qcom,shikra-dpu"; + reg = <0x0 0x05e01000 0x0 0x8f000>, + <0x0 0x05eb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "core", + "lut", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@5e94000 { + compatible = "qcom,shikra-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x05e94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-164000000 { + opp-hz = /bits/ 64 <164000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x0 0x05e94400 0x0 0x100>, + <0x0 0x05e94500 0x0 0x300>, + <0x0 0x05e94800 0x0 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + power-domains = <&rpmpd QCM2290_VDDMX>; + required-opps = <&rpmpd_opp_nom>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + dispcc: clock-controller@5f00000 { compatible = "qcom,shikra-dispcc"; reg = <0x0 0x05f00000 0x0 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>; #clock-cells = <1>; From f7cd4364e6ba207a4b39ec1e37ca63457662d340 Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Mon, 11 May 2026 16:00:45 +0530 Subject: [PATCH 0911/1330] arm64: dts: qcom: shikra-cqm-evk: Enable display and add DLC0697 panel Enable the Shikra MDSS display subsystem on the CQM EVK board and add the DLC0697 panel node. Pin pm4125_l5 to 1.232V with regulator-allow-set-load for DSI PHY PLL stability. Signed-off-by: Mahadevan P (cherry picked from commit 8f7e16e4d0ed7a8e661c67589c02f9987abf29dc) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 90 +++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 05b450bd2acdf..a8f6d64ea57df 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -24,6 +24,65 @@ chosen { stdout-path = "serial0:115200n8"; }; + + lcd_bias: regulator-lcd-bias { + compatible = "regulator-fixed"; + regulator-name = "lcd_bias"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pm4125_l17>; + gpio = <&tlmm 151 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_bias_en>; + pinctrl-names = "default"; + }; + +}; + +&mdss { + status = "okay"; +}; + +&pm4125_l5 { + /* DSI VDDA - must be at NOM voltage for PHY PLL lock */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + regulator-allow-set-load; +}; + +&mdss_dsi0 { + vdda-supply = <&pm4125_l5>; + status = "okay"; + + panel@0 { + compatible = "dlc,dlc0697"; + reg = <0>; + + reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&pm4125_l15>; + bias-supply = <&lcd_bias>; + + pinctrl-0 = <&panel_rst_n &panel_te_pin>; + pinctrl-1 = <&panel_rst_n_suspend>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; }; &pm4125_hs_in { @@ -85,6 +144,37 @@ status = "okay"; }; +&tlmm { + lcd_bias_en: lcd-bias-en-state { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + panel_rst_n: panel-rst-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_rst_n_suspend: panel-rst-n-suspend-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + panel_te_pin: panel-te-pin-state { + pins = "gpio86"; + function = "mdp_vsync_p"; + drive-strength = <2>; + bias-pull-down; + }; + +}; + &uart0 { status = "okay"; }; From 5a71e936ba1288acdb8583f55a3224e346ea76d5 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 12 May 2026 17:00:31 +0530 Subject: [PATCH 0912/1330] iommu/arm-smmu: Add ACTLR settings for missing MDSS devices for new Shikra platform Shikra being a new platform has a different target specific compatible for mdss device. Add ACTLR configuration for corresponding compatible to apply the required QoS settings. Signed-off-by: Bibek Kumar Patro (cherry picked from commit e606a118cd6132960cfb7e2fce33dfa449ba1482) --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 2d006049dd610..69931b458561c 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -53,6 +53,8 @@ static const struct of_device_id qcom_smmu_actlr_client_of_match[] = { .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, { .compatible = "qcom,sc8280xp-mdss", .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible = "qcom,shikra-mdss", + .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, { .compatible = "qcom,sm6115-mdss", .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, { .compatible = "qcom,sm6125-mdss", From 4684237f1eeeaac58b720fed4c774f9c7082a19c Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Tue, 5 May 2026 20:12:30 +0530 Subject: [PATCH 0913/1330] dt-bindings: display: msm: qcm2290: Add Shikra MDSS Shikra SoC uses the same MDSS/DPU/DSI hardware as QCM2290 (DPU 6.5), sharing the same register layout, DSI controller and 14nm DSI PHY. Add qcom,shikra-mdss to the qcm2290-mdss binding compatible enum rather than introducing a separate binding file. Register qcom,shikra-dsi-ctrl in dsi-controller-main.yaml alongside qcom,qcm2290-dsi-ctrl, and update the qcm2290-mdss patternProperties to accept both SoC-specific DPU and DSI controller compatibles. Signed-off-by: Mahadevan P (cherry picked from commit 89c98e36bd908e503021067fcd0388b3e44a15b5) --- .../display/msm/dsi-controller-main.yaml | 1 + .../display/msm/qcom,qcm2290-dpu.yaml | 4 ++- .../display/msm/qcom,qcm2290-mdss.yaml | 34 +++++++++++++++---- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index eb6d38dabb08e..3190b2526c341 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -32,6 +32,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl + - qcom,shikra-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl - qcom,sm6150-dsi-ctrl diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml index be6cd8adb3b67..cc1f227ade2d3 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,qcm2290-dpu + enum: + - qcom,qcm2290-dpu + - qcom,shikra-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml index 2772cdec7e42a..72d763482ef34 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -4,21 +4,35 @@ $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm QCM220 Display MDSS +title: Qualcomm QCM2290 and Shikra Display MDSS maintainers: - Loic Poulain + - Mahadevan P description: Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS - are mentioned for QCM2290 target. + are mentioned for QCM2290 and Shikra targets. Shikra uses the same MDSS/DPU/DSI + hardware as QCM2290 (DPU 6.5) and shares the same register layout. $ref: /schemas/display/msm/mdss-common.yaml# +select: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-mdss + - qcom,shikra-mdss + required: + - compatible + properties: compatible: - const: qcom,qcm2290-mdss + enum: + - qcom,qcm2290-mdss + - qcom,shikra-mdss clocks: items: @@ -52,7 +66,9 @@ patternProperties: properties: compatible: - const: qcom,qcm2290-dpu + enum: + - qcom,qcm2290-dpu + - qcom,shikra-dpu "^dsi@[0-9a-f]+$": type: object @@ -60,9 +76,13 @@ patternProperties: properties: compatible: - items: - - const: qcom,qcm2290-dsi-ctrl - - const: qcom,mdss-dsi-ctrl + oneOf: + - items: + - const: qcom,qcm2290-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + - items: + - const: qcom,shikra-dsi-ctrl + - const: qcom,mdss-dsi-ctrl "^phy@[0-9a-f]+$": type: object From d38979ee2069d23a10c25f405afb3cfa08b00650 Mon Sep 17 00:00:00 2001 From: Arpit Saini Date: Tue, 12 May 2026 16:57:57 +0530 Subject: [PATCH 0914/1330] dt-bindings: display: panel: Add DLC0697 DSI panel binding Add Device Tree binding documentation for the DLC DLC0697 1080x1920 video-mode MIPI DSI panel. Add a MAINTAINERS entry covering the binding and the panel driver. Signed-off-by: Arpit Saini Signed-off-by: Mahadevan P (cherry picked from commit ba489cbcba7a852d2eb7016a8672757e257c49b0) --- .../bindings/display/panel/dlc,dlc0697.yaml | 66 +++++++++++++++++++ MAINTAINERS | 7 ++ 2 files changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/dlc,dlc0697.yaml diff --git a/Documentation/devicetree/bindings/display/panel/dlc,dlc0697.yaml b/Documentation/devicetree/bindings/display/panel/dlc,dlc0697.yaml new file mode 100644 index 0000000000000..8ae72a8265e61 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/dlc,dlc0697.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/dlc,dlc0697.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DLC DLC0697 1080x1920 video-mode DSI panel + +maintainers: + - Arpit Saini + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: dlc,dlc0697 + + reg: + maxItems: 1 + description: DSI virtual channel + + reset-gpios: true + + enable-gpios: true + + vddio-supply: + description: I/O voltage supply (1.8V) + + bias-supply: + description: LCD bias supply (3.3V), typically a GPIO-controlled fixed regulator + + port: true + +required: + - compatible + - reg + - reset-gpios + - vddio-supply + - port + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "dlc,dlc0697"; + reg = <0>; + + reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>; + vddio-supply = <&vreg_l15>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 33746655481d1..b532de78a5aeb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7965,6 +7965,13 @@ S: Maintained F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml F: drivers/gpu/drm/bridge/chipone-icn6211.c +DRM DRIVER FOR DLC DLC0697 DSI PANEL +M: Arpit Saini +S: Maintained +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: Documentation/devicetree/bindings/display/panel/dlc,dlc0697.yaml +F: drivers/gpu/drm/panel/panel-dlc0697.c + DRM DRIVER FOR EBBG FT8719 PANEL M: Joel Selvaraj S: Maintained From d38c03736899ab8900b91202c8b907ae9f14f432 Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Tue, 5 May 2026 19:57:34 +0530 Subject: [PATCH 0915/1330] drm/msm/mdss: Add Shikra support Add Mobile Display Subsystem (MDSS) support for the Shikra platform. Shikra uses the same MDSS and DPU 6.5 hardware as QCM2290, so it reuses the same AHB clock rate configuration (data_76k8) and DPU catalog. Register qcom,shikra-dpu in the DPU KMS match table pointing to dpu_qcm2290_cfg. Signed-off-by: Mahadevan P (cherry picked from commit 9f37c5afe0cefd8eac0ed581c10ff9a833d78d7b) --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index c557430e0dfb1..5a9794d2c4446 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1545,6 +1545,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, }, { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, }, { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, + { .compatible = "qcom,shikra-dpu", .data = &dpu_qcm2290_cfg, }, { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, }, { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, }, diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 9047e8d9ee89b..b44bbc5dcb491 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -569,6 +569,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sar2130p-mdss", .data = &data_74k }, { .compatible = "qcom,sdm670-mdss", .data = &data_76k8 }, { .compatible = "qcom,sdm845-mdss", .data = &data_76k8 }, + { .compatible = "qcom,shikra-mdss", .data = &data_76k8 }, { .compatible = "qcom,sc7180-mdss", .data = &data_76k8 }, { .compatible = "qcom,sc7280-mdss", .data = &data_74k }, { .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 }, From 56a04f5763ef8765dbfaabae2d010c410eea50b3 Mon Sep 17 00:00:00 2001 From: Arpit Saini Date: Tue, 12 May 2026 17:01:53 +0530 Subject: [PATCH 0916/1330] drm/panel: Add driver for DLC0697 FHD video-mode DSI panel Add a DRM panel driver for the DLC0697 1080x1920@60Hz MIPI DSI panel. The driver implements the panel init/exit sequence, power and reset handling, a fixed display mode, and DCS backlight control. The panel operates in video burst mode with four data lanes using RGB888 pixel format. Backlight enable GPIO is toggled directly in enable/disable; backlight brightness is managed via the DRM backlight framework using the 16-bit DCS brightness API. Signed-off-by: Arpit Saini Signed-off-by: Mahadevan P (cherry picked from commit c58c64e5438d7cc7325a12bda02ee7c1289ea0b8) --- drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-dlc0697.c | 339 ++++++++++++++++++++++++++ 3 files changed, 351 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-dlc0697.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 79264f7bbd0e2..6bdcbf610bcab 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -105,6 +105,17 @@ config DRM_PANEL_BOE_TV101WUM_LL2 Say Y here if you want to support for BOE TV101WUM-LL2 WUXGA PANEL DSI Video Mode panel +config DRM_PANEL_DLC0697 + tristate "DLC0697 1080x1920 video mode DSI panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for the DLC DLC0697 + 1080x1920 60Hz MIPI-DSI video mode panel found on Qualcomm + Shikra (QCM2290-based) EVK boards. The panel supports hardware + backlight control via the MIPI DCS brightness command. + config DRM_PANEL_EBBG_FT8719 tristate "EBBG FT8719 panel driver" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index aeffaa95666d6..8d72f238bde42 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A) += panel-boe-th101mb31ig002-28a. obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_LL2) += panel-boe-tv101wum-ll2.o obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o +obj-$(CONFIG_DRM_PANEL_DLC0697) += panel-dlc0697.o obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o diff --git a/drivers/gpu/drm/panel/panel-dlc0697.c b/drivers/gpu/drm/panel/panel-dlc0697.c new file mode 100644 index 0000000000000..f0ef07cb0160f --- /dev/null +++ b/drivers/gpu/drm/panel/panel-dlc0697.c @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +/* + * DRM panel driver for DLC0697 1080x1920 60Hz video-mode DSI panel + * + * Derived from downstream Qualcomm panel DT data. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct dlc0697 { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + + struct regulator_bulk_data *supplies; + struct gpio_desc *reset_gpio; + struct gpio_desc *enable_gpio; + + struct pinctrl *pinctrl; + struct pinctrl_state *state_active; + struct pinctrl_state *state_suspend; +}; + +static const struct regulator_bulk_data dlc0697_supplies[] = { + { .supply = "vddio" }, + { .supply = "bias" }, +}; + +static inline struct dlc0697 *to_dlc0697(struct drm_panel *panel) +{ + return container_of(panel, struct dlc0697, panel); +} + +static const struct drm_display_mode dlc0697_mode = { + .clock = 131911, + + .hdisplay = 1080, + .hsync_start = 1080 + 18, + .hsync_end = 1080 + 18 + 2, + .htotal = 1080 + 18 + 2 + 16, + + .vdisplay = 1920, + .vsync_start = 1920 + 26, + .vsync_end = 1920 + 26 + 4, + .vtotal = 1920 + 26 + 4 + 20, + + .width_mm = 0, + .height_mm = 0, +}; + +static void dlc0697_reset(struct dlc0697 *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); +} + +static int dlc0697_on(struct dlc0697 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_soft_reset_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x78, 0x07, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x09, 0x99); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x3f, 0xff); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); + + ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + if (dsi_ctx.accum_err) + dev_err(&ctx->dsi->dev, "panel on sequence failed: %d\n", dsi_ctx.accum_err); + + return dsi_ctx.accum_err; +} + +static int dlc0697_off(struct dlc0697 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); + + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); + + ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + if (dsi_ctx.accum_err) + dev_err(&ctx->dsi->dev, "panel off sequence failed: %d\n", dsi_ctx.accum_err); + + return dsi_ctx.accum_err; +} + +static int dlc0697_enable(struct drm_panel *panel) +{ + struct dlc0697 *ctx = to_dlc0697(panel); + + if (ctx->enable_gpio) + gpiod_set_value_cansleep(ctx->enable_gpio, 1); + + return 0; +} + +static int dlc0697_disable(struct drm_panel *panel) +{ + struct dlc0697 *ctx = to_dlc0697(panel); + + if (ctx->enable_gpio) + gpiod_set_value_cansleep(ctx->enable_gpio, 0); + + return 0; +} + +static int dlc0697_prepare(struct drm_panel *panel) +{ + struct dlc0697 *ctx = to_dlc0697(panel); + int ret; + + if (ctx->pinctrl && ctx->state_active) { + ret = pinctrl_select_state(ctx->pinctrl, ctx->state_active); + if (ret < 0) + return ret; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(dlc0697_supplies), ctx->supplies); + if (ret < 0) { + dev_err(ctx->panel.dev, "failed to enable regulators: %d\n", ret); + return ret; + } + + /* qcom,supply-post-on-sleep = <20> */ + msleep(20); + + dlc0697_reset(ctx); + + ret = dlc0697_on(ctx); + if (ret < 0) + goto err; + + return 0; + +err: + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + + if (ctx->pinctrl && ctx->state_suspend) + pinctrl_select_state(ctx->pinctrl, ctx->state_suspend); + + regulator_bulk_disable(ARRAY_SIZE(dlc0697_supplies), ctx->supplies); + + return ret; +} + +static int dlc0697_unprepare(struct drm_panel *panel) +{ + struct dlc0697 *ctx = to_dlc0697(panel); + + dlc0697_off(ctx); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + + if (ctx->pinctrl && ctx->state_suspend) + pinctrl_select_state(ctx->pinctrl, ctx->state_suspend); + + regulator_bulk_disable(ARRAY_SIZE(dlc0697_supplies), ctx->supplies); + + return 0; +} + +static int dlc0697_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + return drm_connector_helper_get_modes_fixed(connector, &dlc0697_mode); +} + +static const struct drm_panel_funcs dlc0697_panel_funcs = { + .prepare = dlc0697_prepare, + .unprepare = dlc0697_unprepare, + .enable = dlc0697_enable, + .disable = dlc0697_disable, + .get_modes = dlc0697_get_modes, +}; + +static int dlc0697_bl_update_status(struct backlight_device *bl) +{ + struct mipi_dsi_device *dsi = bl_get_data(bl); + u16 brightness = backlight_get_brightness(bl); + int ret; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness); + if (ret < 0) + return ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + return 0; +} + +static const struct backlight_ops dlc0697_bl_ops = { + .update_status = dlc0697_bl_update_status, +}; + +static struct backlight_device *dlc0697_create_backlight(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + const struct backlight_properties props = { + .type = BACKLIGHT_RAW, + .brightness = 4095, + .max_brightness = 4095, + }; + + return devm_backlight_device_register(dev, dev_name(dev), dev, dsi, + &dlc0697_bl_ops, &props); +} + +static int dlc0697_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct dlc0697 *ctx; + int ret; + + ctx = devm_drm_panel_alloc(dev, struct dlc0697, panel, + &dlc0697_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + if (IS_ERR(ctx)) + return PTR_ERR(ctx); + + ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(dlc0697_supplies), + dlc0697_supplies, &ctx->supplies); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get regulators\n"); + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "failed to get reset gpio\n"); + + ctx->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(ctx->enable_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), + "failed to get enable gpio\n"); + + ctx->pinctrl = devm_pinctrl_get(dev); + if (IS_ERR(ctx->pinctrl)) { + if (PTR_ERR(ctx->pinctrl) == -ENODEV) { + ctx->pinctrl = NULL; + } else { + return dev_err_probe(dev, PTR_ERR(ctx->pinctrl), + "failed to get pinctrl\n"); + } + } + + if (ctx->pinctrl) { + ctx->state_active = pinctrl_lookup_state(ctx->pinctrl, "default"); + if (IS_ERR(ctx->state_active)) + ctx->state_active = NULL; + + ctx->state_suspend = pinctrl_lookup_state(ctx->pinctrl, "sleep"); + if (IS_ERR(ctx->state_suspend)) + ctx->state_suspend = NULL; + } + + ctx->dsi = dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST; + + ctx->panel.prepare_prev_first = true; + + ctx->panel.backlight = dlc0697_create_backlight(dsi); + if (IS_ERR(ctx->panel.backlight)) + return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight), + "failed to create backlight\n"); + + drm_panel_add(&ctx->panel); + + ret = devm_mipi_dsi_attach(dev, dsi); + if (ret < 0) { + drm_panel_remove(&ctx->panel); + return dev_err_probe(dev, ret, "failed to attach dsi\n"); + } + + return 0; +} + +static void dlc0697_remove(struct mipi_dsi_device *dsi) +{ + drm_panel_remove(mipi_dsi_get_drvdata(dsi)); +} + +static const struct of_device_id dlc0697_of_match[] = { + { .compatible = "dlc,dlc0697" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dlc0697_of_match); + +static struct mipi_dsi_driver dlc0697_driver = { + .probe = dlc0697_probe, + .remove = dlc0697_remove, + .driver = { + .name = "panel-dlc0697", + .of_match_table = dlc0697_of_match, + }, +}; +module_mipi_dsi_driver(dlc0697_driver); + +MODULE_AUTHOR("Arpit Saini "); +MODULE_DESCRIPTION("DLC0697 1080x1920 video mode DSI panel"); +MODULE_LICENSE("GPL"); From 48f0d112403c59f385a34f95790e5704f256312a Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Wed, 6 May 2026 10:17:26 +0530 Subject: [PATCH 0917/1330] arm64: defconfig: Enable DLC0697 DSI panel driver Enable the DLC0697 1080x1920 video-mode DSI panel driver as a module, used on the Shikra CQM EVK board. Signed-off-by: Mahadevan P (cherry picked from commit 65d343878c5e222a3680767851708893ecfd1e82) --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 789233c2ad831..c2dde76d6b08f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -980,6 +980,7 @@ CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_DLC0697=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_SUMMIT=m From 9beb7fdeaef167735916f58ce3afd30bb5c494b5 Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Mon, 11 May 2026 15:58:52 +0530 Subject: [PATCH 0918/1330] soc: qcom: ubwc: Add Shikra UBWC config Add UBWC configuration for the Shikra platform. Shikra has no UBWC support and no highest_bank_bit setting, so use no_ubwc_data. Signed-off-by: Mahadevan P (cherry picked from commit 96a38f617c1f4707073c77b3a1c747aa9fff0545) --- drivers/soc/qcom/ubwc_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 8304463f238a6..708b24f16608c 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -276,6 +276,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,sdm660", .data = &msm8937_data }, { .compatible = "qcom,sdm670", .data = &sdm670_data, }, { .compatible = "qcom,sdm845", .data = &sdm845_data, }, + { .compatible = "qcom,shikra", .data = &no_ubwc_data, }, { .compatible = "qcom,sm4250", .data = &sm6115_data, }, { .compatible = "qcom,sm6115", .data = &sm6115_data, }, { .compatible = "qcom,sm6125", .data = &sm6125_data, }, From 92c147f4b9f4b00c92b22ca33caea3426e00f2ba Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Thu, 9 Apr 2026 14:52:06 +0530 Subject: [PATCH 0919/1330] ASoC: dt-bindings: Add schema for qcom,wsa885x-i2c Add a devicetree binding schema for Qualcomm WSA885X smart speaker amplifier on I2C. Document the device compatible, supplies, GPIOs, DAI cell count and initialization table property used by the driver. Keep a single init table property (wsa885x-init-table) as currently supported. Signed-off-by: Prasad Kumpatla (cherry picked from commit 4dae440b358bd921f650d90340289ba330fffda9) --- .../bindings/sound/qcom,wsa885x-i2c.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/qcom,wsa885x-i2c.yaml diff --git a/Documentation/devicetree/bindings/sound/qcom,wsa885x-i2c.yaml b/Documentation/devicetree/bindings/sound/qcom,wsa885x-i2c.yaml new file mode 100644 index 0000000000000..6bc742b0aacf8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,wsa885x-i2c.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wsa885x-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm WSA885X I2C smart speaker amplifier + +maintainers: + - Srinivas Kandagatla + +allOf: + - $ref: dai-common.yaml# + +description: | + WSA885X is a Qualcomm smart speaker amplifier codec. + This binding describes the I2C control interface and + board-level resources required by the codec. + +properties: + compatible: + const: qcom,wsa885x-i2c + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + powerdown-gpios: + description: GPIO spec for the codec shutdown/powerdown pin. + maxItems: 1 + + interrupt-gpios: + description: GPIO spec for the codec interrupt pin. + maxItems: 1 + + vdd-io-supply: + description: 1.8V I/O supply. + + vdd-1p8-supply: + description: 1.8V analog/digital core supply. + + qcom,battery_config: + description: Battery topology configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + wsa885x-init-table: + description: Register/value initialization table as pairs. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 512 + +required: + - compatible + - reg + - '#sound-dai-cells' + - vdd-io-supply + - vdd-1p8-supply + - wsa885x-init-table + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + speaker-codec@c { + compatible = "qcom,wsa885x-i2c"; + reg = <0x0c>; + #sound-dai-cells = <0>; + + qcom,battery_config = <1>; + + powerdown-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + interrupt-gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>; + + vdd-io-supply = <&vreg_l15a_1p8>; + vdd-1p8-supply = <&vreg_l10a_1p8>; + + wsa885x-init-table = < + 0x800d 0x1c + 0x8090 0x1f + >; + }; + }; + +... From 34fffbeb87a47feea46b34fa4b544456abb62a88 Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Thu, 9 Apr 2026 16:22:47 +0530 Subject: [PATCH 0920/1330] ASoC: codecs: add Qualcomm WSA885X I2C codec driver Add a new ASoC codec driver for Qualcomm WSA885X over I2C. Signed-off-by: Prasad Kumpatla (cherry picked from commit e2a212affd7eb967ec8e53b8304e987881e8db09) --- sound/soc/codecs/Kconfig | 9 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/wsa885x-i2c.c | 1359 ++++++++++++++++++++++++++++++++ 3 files changed, 1370 insertions(+) create mode 100644 sound/soc/codecs/wsa885x-i2c.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index adb3fb923be39..20191fe9259d0 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -363,6 +363,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_WSA881X imply SND_SOC_WSA883X imply SND_SOC_WSA884X + imply SND_SOC_WSA885X_I2C imply SND_SOC_ZL38060 help Normally ASoC codec drivers are only built if a machine driver which @@ -2721,6 +2722,14 @@ config SND_SOC_WSA884X This enables support for Qualcomm WSA8840/WSA8845/WSA8845H Class-D Smart Speaker Amplifier. +config SND_SOC_WSA885X_I2C + tristate "WSA885X I2C Codec" + depends on I2C + select REGMAP_I2C + help + This enables support for Qualcomm WSA885X Smart Speaker + Amplifier over I2C. + config SND_SOC_ZL38060 tristate "Microsemi ZL38060 Connected Home Audio Processor" depends on SPI_MASTER diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 3ddee52987219..9ebef3856e4f8 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -421,6 +421,7 @@ snd-soc-wm-hubs-y := wm_hubs.o snd-soc-wsa881x-y := wsa881x.o snd-soc-wsa883x-y := wsa883x.o snd-soc-wsa884x-y := wsa884x.o +snd-soc-wsa885x-i2c-y := wsa885x-i2c.o snd-soc-zl38060-y := zl38060.o # Amp snd-soc-max9877-y := max9877.o @@ -866,6 +867,7 @@ obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o obj-$(CONFIG_SND_SOC_WSA881X) += snd-soc-wsa881x.o obj-$(CONFIG_SND_SOC_WSA883X) += snd-soc-wsa883x.o obj-$(CONFIG_SND_SOC_WSA884X) += snd-soc-wsa884x.o +obj-$(CONFIG_SND_SOC_WSA885X_I2C) += snd-soc-wsa885x-i2c.o obj-$(CONFIG_SND_SOC_ZL38060) += snd-soc-zl38060.o # Amp diff --git a/sound/soc/codecs/wsa885x-i2c.c b/sound/soc/codecs/wsa885x-i2c.c new file mode 100644 index 0000000000000..2ace3a0956b25 --- /dev/null +++ b/sound/soc/codecs/wsa885x-i2c.c @@ -0,0 +1,1359 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* WSA885X I2C codec driver */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Driver Constants */ +#define CLK_RATE_FIXED 73728000 +#define SUPPLIES_NUM 2 +#define SLAVE_ADDR 0x00c +#define NUM_REGS 0x03 + +/* Interrupt Registers */ +#define WSA885X_INTR_STATUS0 0x8584 /* Base address of the status register */ +#define WSA885X_INTR_MASK0 0x8581 /* Base address of the mask register */ +#define WSA885X_INTR_CLEAR0 0x8587 /* Base address of the acknowledge register */ +#define WSA885X_INTR_LEVEL0 0x858A /* Base address of the acknowledge register */ + +/* Power and PA FSM Control Registers */ +#define WSA885X_POWER_FSM_CTL0 0x8423 +#define WSA885X_PA0_FSM_CTL0 0x842A +#define WSA885X_PA1_FSM_CTL0 0x8434 + +/* Digital Control GPIO and Interrupt Registers */ +#define DIG_CTRL1_PIN_CT 0x8510 +#define DIG_CTRL1_SPMI_PAD_GPIO2_CTL 0x8518 +#define DIG_CTRL1_INTR_MODE 0x8580 + +/* Control Registers - Audio Processing */ +#define SMP_AMP_CTRL_STEREO_STEREO_SMP_AMP_CTRL_I2S 0x0000 +#define SMP_AMP_CTRL_STEREO_CMT_GRP_MASK 0x0004 +#define SMP_AMP_CTRL_STEREO_IT21_CLUSERINDEX 0x0140 +#define SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID 0x0208 +#define SMP_AMP_CTRL_STEREO_CS21_SAMPLERATEINDEX 0x0240 +#define SMP_AMP_CTRL_STEREO_PPU21_POSTURENUMBER 0x0340 +#define SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X0 0x4405 +#define SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X1 0x4406 +#define SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_LSB 0x4409 +#define SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_MSB 0x6409 +#define SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_LSB 0x440a +#define SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_MSB 0x640a +#define SMP_AMP_CTRL_STEREO_PDE23_REQ_PS 0x0a04 +#define SMP_AMP_CTRL_STEREO_PDE23_ACT_PS 0x0a40 +#define SMP_AMP_CTRL_STEREO_OT23_USAGE 0x0b10 +#define SMP_AMP_CTRL_STEREO_CS24_SAMPLERATEINDEX 0x0e40 + +/* Analog Top Registers - Power and Clock Control */ +#define ANA_TOP_PON_CKSK_CTL_0 0x800d +#define ANA_TOP_BG_TVP_UVLO1_PROG 0x8024 +#define ANA_TOP_BG_TVP_UVLO2_PROG 0x8025 +#define ANA_TOP_BG_TVP_OVRD_CTL 0x8034 + +/* Analog PLL Registers */ +#define ANA_PLL_DIV_CTL_0 0x8090 +#define ANA_PLL_DIV_CTL_1 0x8091 +#define ANA_TOP_PLL_VCO_CTL 0x8092 +#define ANA_TOP_PLL_LOOPFILT_0 0x8093 +#define ANA_TOP_PLL_OVRD_CTL 0x8098 +#define ANA_TOP_PLL_STATUS_0 0x809a +#define ANA_TOP_PLL_STATUS_1 0x809b + +/* Analog Boost Control Registers */ +#define ANA_TOP_BOOST_STB_CTRL2 0x805b +#define ANA_TOP_BOOST_STB_CTRL3 0x805c +#define ANA_TOP_BOOST_BYP_CTRL2 0x805e +#define ANA_TOP_BOOST_BYP_CTRL3 0x805f +#define ANA_TOP_BOOST_MISC 0x8063 +#define ANA_TOP_BOOST_PWRSTAGE_CTRL2 0x8065 +#define ANA_TOP_BOOST_PWRSTAGE_CTRL4 0x8067 + +/* Analog IV Sense ADC Registers */ +#define ANA_TOP_IVSENSE_ADC_MODE_CTL2 0x80ca +#define ANA_TOP_IVSENSE_ADC_MODE_CTL3 0x80cb +#define ANA_TOP_IVSENSE_ADC_REF_CTL 0x80cc +#define ANA_TOP_IVSENSE_ADC_CDAC_CAL_CTL2 0x80d0 + +/* Analog Speaker Power Stage Registers */ +#define ANA_TOP_SPK_TOP_PWRSTG_CH1_CTRL3 0x8108 +#define ANA_TOP_SPK_TOP_PWRSTG_CH1_TUNE3 0x810b +#define ANA_TOP_SPK_TOP_PWRSTG_CH2_CTRL3 0x810e +#define ANA_TOP_SPK_TOP_PWRSTG_CH2_TUNE3 0x8111 +#define ANA_TOP_SPK_TOP_SPARE3 0x813c +#define SPK_TOP_LF_CH1_CTRL11 0x811c +#define SPK_TOP_LF_CH1_TUNE1 0x811d +#define SPK_TOP_LF_CH2_TUNE1 0x8129 +#define SPK_TOP_LF_CH1_CTRL9 0x811a +#define SPK_TOP_LF_CH2_CTRL9 0x8126 +#define SPK_TOP_LF_CH2_CTRL11 0x8128 +#define SPK_TOP_COMMON_CTRL2 0x8102 +#define SPK_TOP_COMMON_TUNE1 0x8103 +#define IVSENSE_VSNS_ISNS_CTL_CH1 0x80ba +#define DIG_CTRL0_CDC_CLK_CTL 0x841c +#define PON_CKSK_CTL_0 0x800d +#define DIG_CTRL0_TOP_CLK_CFG 0x8418 +#define DIG_CTRL0_SDCA_COMMIT 0x8419 +#define DIG_CTRL0_CLK_SOURCE_ENABLE 0x841a +#define DIG_CTRL0_SYS_CLK_SEL 0x841b +#define DIG_CTRL0_CDC_CLK_CTL 0x841c +#define DIG_CTRL0_PA_FSM_CTL 0x8420 +#define DIG_CTRL0_POWER_FSM_CTL0 0x8423 +#define DIG_CTRL0_POWER_FSM_CTL1 0x8424 +#define DIG_CTRL0_PA0_FSM_CTL1 0x842b +#define DIG_CTRL0_PA1_FSM_CTL1 0x8435 +#define DIG_CTRL0_VBAT_THRM_FLT_CTL 0x8458 +#define DIG_CTRL0_CDC_RXTX_FSCNT_CTL 0x8470 +#define DIG_CTRL0_GAIN_RAMP0_CTL1 0x84b4 +#define DIG_CTRL0_GAIN_RAMP1_CTL1 0x84b7 + +/* Digital Control 1 Registers - I2S/TDM Interface */ +#define DIG_CTRL1_I2S_CTL0 0x85A0 +#define DIG_CTRL1_I2S_CFG0_TDM_TX 0x85A2 +#define DIG_CTRL1_I2S_CFG1_TDM_TX 0x85A3 +#define DIG_CTRL1_I2S_TDM_CTL0 0x85A7 +#define DIG_CTRL1_I2S_TDM_CTL1 0x85A9 +#define DIG_CTRL1_I2S_TDM_CH_RX 0x85AA +#define DIG_CTRL1_I2S_TDM_CH_TX 0x85AB +#define DIG_CTRL1_I2S_RESET_CTL 0x85AE + +/* CDC RX Path Registers - Audio Data Path */ +#define CDC_RX0_RX_PATH_CFG0 0x8601 +#define CDC_RX0_RX_PATH_CFG1 0x8602 +#define CDC_RX0_RX_PATH_CTL 0x8606 +#define RX0_RX_PATH_DSMDEM_CTL 0x8613 +#define CDC_RX1_RX_PATH_CFG0 0x8621 +#define CDC_RX1_RX_PATH_CFG1 0x8622 +#define CDC_RX1_RX_PATH_CTL 0x8626 +#define RX1_RX_PATH_DSMDEM_CTL 0x8633 + +/* CDC Compander Registers - Dynamic Range Control */ +#define CDC_COMPANDER0_CTL0 0x8640 +#define CDC_COMPANDER0_CTL7 0x8647 +#define CDC_COMPANDER1_CTL0 0x8660 +#define CDC_COMPANDER1_CTL7 0x8667 + +/* CDC Speaker Protection Registers - IV Sense */ +#define CDC_VSENSE0_SPKR_PROT_PATH_CTL 0x86A1 +#define CDC_VSENSE1_SPKR_PROT_PATH_CTL 0x86B1 +#define CDC_ISENSE0_SPKR_PROT_PATH_CTL 0x86A9 +#define CDC_ISENSE1_SPKR_PROT_PATH_CTL 0x86B9 + +/* CDC Class-H Registers - Headroom Control */ +#define CDC_CLSH_V1P8_BP_CTL1 0x86CD +#define CDC_CLSH_V1P8_BP_CTL0 0x86CC +#define CDC_CLSH_CLSH_SIG_DP_CTL0 0x86C7 +#define CDC_CLSH_CLSH_V_HD_PA 0x86C3 +#define CDC_CLSH_V1P8_BP_CTL2 0x86CE + +/* RX Sample Rate Index Values - Audio Playback Path */ +#define WSA885X_RX_RATE_8000HZ 0x00 /* 8 kHz sample rate */ +#define WSA885X_RX_RATE_16000HZ 0x01 /* 16 kHz sample rate */ +#define WSA885X_RX_RATE_32000HZ 0x02 /* 32 kHz sample rate */ +#define WSA885X_RX_RATE_44100HZ 0x03 /* 44.1 kHz sample rate */ +#define WSA885X_RX_RATE_48000HZ 0x04 /* 48 kHz sample rate */ +#define WSA885X_RX_RATE_96000HZ 0x05 /* 96 kHz sample rate */ +#define WSA885X_RX_RATE_192000HZ 0x06 /* 192 kHz sample rate */ +#define WSA885X_RX_RATE_384000HZ 0x07 /* 384 kHz sample rate */ + +/* VI Sample Rate Index Values - Voltage/Current Sensing Path */ +#define WSA885X_VI_RATE_8000HZ 0x00 /* 8 kHz sample rate for VI sensing */ +#define WSA885X_VI_RATE_16000HZ 0x01 /* 16 kHz sample rate for VI sensing */ +#define WSA885X_VI_RATE_44100HZ 0x02 /* 44.1 kHz sample rate for VI sensing */ +#define WSA885X_VI_RATE_48000HZ 0x03 /* 48 kHz sample rate for VI sensing */ +#define WSA885X_VI_RATE_96000HZ 0x04 /* 96 kHz sample rate for VI sensing */ +#define WSA885X_VI_RATE_22050HZ 0x05 /* 22.05 kHz sample rate for VI sensing */ +#define WSA885X_VI_RATE_24000HZ 0x06 /* 24 kHz sample rate for VI sensing */ +#define WSA885X_VI_RATE_192000HZ 0x07 /* 192 kHz sample rate for VI sensing */ +#define WSA885X_VI_RATE_384000HZ 0x08 /* 384 kHz sample rate for VI sensing */ + +/* Channel Configuration Masks */ +#define WSA885X_CHANNEL_STEREO 0x03 /* Both left and right channels (0b11) */ +#define WSA885X_CHANNEL_MONO_LEFT 0x01 /* Left channel only (0b01) */ +#define WSA885X_CHANNEL_MONO_RIGHT 0x02 /* Right channel only (0b10) */ + +/* PLL Status Register Bits */ +#define WSA885X_PLL_LOCK_BIT 0x01 /* PLL lock status bit (bit 0) */ + +/* FU21 volume support */ +#define FU21_VOL_STEPS 124 +static const DECLARE_TLV_DB_SCALE(fu21_digital_gain, -8400, 100, 0); + +static const char *const supply_name[] = { + "vdd-io", + "vdd-1p8", +}; + +enum { + batt_1s = 1, + batt_2s, +}; + +enum { + WSA885X_IRQ_INT_SAF2WAR = 0, + WSA885X_IRQ_INT_WAR2SAF, + WSA885X_IRQ_INT_DISABLE, + WSA885X_IRQ_INT_PA0_OCP, + WSA885X_IRQ_INT_PA1_OCP, + WSA885X_IRQ_INT_CLIP0, + WSA885X_IRQ_INT_CLIP1, + WSA885X_IRQ_INT_CLK_WD, + WSA885X_IRQ_INT_INTR_GPIO1_PIN, + WSA885X_IRQ_INT_INTR_GPIO2_PIN, + WSA885X_IRQ_INT_UVLO, + WSA885X_IRQ_INT_BOP, + WSA885X_IRQ_INT_PA0_FSM_ERR, + WSA885X_IRQ_INT_PA1_FSM_ERR, + WSA885X_IRQ_INT_MAIN_FSM_ERR, + WSA885X_IRQ_INT_PCM_DATA0_WD, + WSA885X_IRQ_INT_PCM_DATA1_WD, + WSA885X_IRQ_INT_PCM_DATA0_DC, + WSA885X_IRQ_INT_PCM_DATA1_DC, + WSA885X_IRQ_INT_PLL_UNLOCKED, + WSA885X_IRQ_INT_PROT_MODE_CHANGE, + WSA885X_IRQ_INT_PB_CLOCK_VALID, + WSA885X_IRQ_INT_SENSE_CLOCK_VALID, + WSA885X_IRQ_MAX, +}; + +static const char *wsa885x_irq_names[WSA885X_IRQ_MAX] = { + "WSA885X_IRQ_INT_SAF2WAR", + "WSA885X_IRQ_INT_WAR2SAF", + "WSA885X_IRQ_INT_DISABLE", + "WSA885X_IRQ_INT_PA0_OCP", + "WSA885X_IRQ_INT_PA1_OCP", + "WSA885X_IRQ_INT_CLIP0", + "WSA885X_IRQ_INT_CLIP1", + "WSA885X_IRQ_INT_CLK_WD", + "WSA885X_IRQ_INT_INTR_GPIO1_PIN", + "WSA885X_IRQ_INT_INTR_GPIO2_PIN", + "WSA885X_IRQ_INT_UVLO", + "WSA885X_IRQ_INT_BOP", + "WSA885X_IRQ_INT_PA0_FSM_ERR", + "WSA885X_IRQ_INT_PA1_FSM_ERR", + "WSA885X_IRQ_INT_MAIN_FSM_ERR", + "WSA885X_IRQ_INT_PCM_DATA0_WD", + "WSA885X_IRQ_INT_PCM_DATA1_WD", + "WSA885X_IRQ_INT_PCM_DATA0_DC", + "WSA885X_IRQ_INT_PCM_DATA1_DC", + "WSA885X_IRQ_INT_PLL_UNLOCKED", + "WSA885X_IRQ_INT_PROT_MODE_CHANGE", + "WSA885X_IRQ_INT_PB_CLOCK_VALID", + "WSA885X_IRQ_INT_SENSE_CLOCK_VALID"}; + +struct wsa885x_i2c_priv { + struct i2c_client *client; + struct regmap *regmap; + struct device *dev; + struct snd_soc_component *component; + struct regulator_bulk_data supplies[SUPPLIES_NUM]; + struct gpio_desc *sd_n; + uint32_t sample_rate; + uint32_t *init_table; + uint32_t init_table_size; + uint32_t usage_mode; + uint32_t rx_slot_mask; + struct gpio_desc *intr_pin; + atomic_t open_count; + uint32_t batt_conf; + int stereo_voldB; /* in dB, -84..+40, encoded as signed 8-bit in MSB register */ +}; + +static const struct regmap_range_cfg regmap_ranges[] = { + { + .range_min = 0, + .range_max = 0x88ff, + .selector_reg = 0x0, + .selector_mask = 0xFF, + .selector_shift = 0, + .window_start = 0, + .window_len = 0x100, + }, +}; + +static const struct reg_default codec_reg_defaults[] = { + {SMP_AMP_CTRL_STEREO_STEREO_SMP_AMP_CTRL_I2S, 0x00}, + {SMP_AMP_CTRL_STEREO_IT21_CLUSERINDEX, 0x01}, + {SMP_AMP_CTRL_STEREO_CMT_GRP_MASK, 0x00}, + {SMP_AMP_CTRL_STEREO_OT23_USAGE, 0x00}, + {SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID, 0x00}, + {SMP_AMP_CTRL_STEREO_CS21_SAMPLERATEINDEX, 0x04}, + {SMP_AMP_CTRL_STEREO_PPU21_POSTURENUMBER, 0x01}, + {SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X0, 0x01}, + {SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X1, 0x01}, + {SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_MSB, 0xac}, + {SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_LSB, 0x00}, + {SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_MSB, 0xac}, + {SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_LSB, 0x00}, + {SMP_AMP_CTRL_STEREO_PDE23_REQ_PS, 0x03}, + {SMP_AMP_CTRL_STEREO_PDE23_ACT_PS, 0x03}, + {SMP_AMP_CTRL_STEREO_OT23_USAGE, 0x00}, + {SMP_AMP_CTRL_STEREO_CS24_SAMPLERATEINDEX, 0x03}, + {SMP_AMP_CTRL_STEREO_CS24_SAMPLERATEINDEX, 0x03}, + {ANA_TOP_PON_CKSK_CTL_0, 0x00}, + {ANA_TOP_BG_TVP_UVLO1_PROG, 0x19}, + {ANA_TOP_BG_TVP_UVLO2_PROG, 0x22}, + {ANA_PLL_DIV_CTL_0, 0x0c}, + {ANA_PLL_DIV_CTL_1, 0x50}, + {ANA_TOP_PLL_VCO_CTL, 0x00}, + {ANA_TOP_PLL_LOOPFILT_0, 0xb4}, + {ANA_TOP_PLL_OVRD_CTL, 0x00}, + {ANA_TOP_BG_TVP_OVRD_CTL, 0x00}, + {ANA_TOP_BOOST_STB_CTRL2, 0x03}, + {ANA_TOP_BOOST_STB_CTRL3, 0x3c}, + {ANA_TOP_BOOST_BYP_CTRL2, 0xc5}, + {ANA_TOP_BOOST_BYP_CTRL3, 0x13}, + {ANA_TOP_BOOST_MISC, 0x79}, + {ANA_TOP_SPK_TOP_SPARE3, 0x00}, + {SPK_TOP_COMMON_CTRL2, 0x08}, + {SPK_TOP_LF_CH1_CTRL11, 0x09}, + {SPK_TOP_LF_CH1_TUNE1, 0x00}, + {SPK_TOP_LF_CH2_TUNE1, 0x00}, + {SPK_TOP_LF_CH1_CTRL9, 0x00}, + {SPK_TOP_LF_CH2_CTRL9, 0x00}, + {SPK_TOP_LF_CH2_CTRL11, 0x09}, + {SPK_TOP_COMMON_TUNE1, 0x08}, + {SPK_TOP_COMMON_TUNE1, 0x03}, + {IVSENSE_VSNS_ISNS_CTL_CH1, 0x00}, + {DIG_CTRL0_CDC_CLK_CTL, 0x0e}, + {PON_CKSK_CTL_0, 0x00}, + {ANA_TOP_BOOST_PWRSTAGE_CTRL2, 0x40}, + {ANA_TOP_BOOST_PWRSTAGE_CTRL4, 0xff}, + {ANA_TOP_PLL_STATUS_0, 0x00}, + {ANA_TOP_PLL_STATUS_1, 0x00}, + {ANA_TOP_IVSENSE_ADC_MODE_CTL2, 0x84}, + {ANA_TOP_IVSENSE_ADC_MODE_CTL3, 0x02}, + {ANA_TOP_IVSENSE_ADC_REF_CTL, 0x00}, + {ANA_TOP_IVSENSE_ADC_CDAC_CAL_CTL2, 0xe0}, + {ANA_TOP_SPK_TOP_PWRSTG_CH1_CTRL3, 0xa4}, + {ANA_TOP_SPK_TOP_PWRSTG_CH1_TUNE3, 0xc9}, + {ANA_TOP_SPK_TOP_PWRSTG_CH2_CTRL3, 0xa4}, + {ANA_TOP_SPK_TOP_PWRSTG_CH2_TUNE3, 0xc5}, + {ANA_TOP_SPK_TOP_PWRSTG_CH2_TUNE3, 0xc9}, + {DIG_CTRL0_TOP_CLK_CFG, 0x00}, + {DIG_CTRL0_SDCA_COMMIT, 0x00}, + {DIG_CTRL0_CLK_SOURCE_ENABLE, 0x00}, + {DIG_CTRL0_SYS_CLK_SEL, 0x00}, + {DIG_CTRL0_CDC_CLK_CTL, 0x0e}, + {DIG_CTRL0_PA_FSM_CTL, 0x00}, + {DIG_CTRL0_POWER_FSM_CTL0, 0x05}, + {DIG_CTRL0_POWER_FSM_CTL1, 0x00}, + {DIG_CTRL0_PA0_FSM_CTL1, 0x45}, + {DIG_CTRL0_PA1_FSM_CTL1, 0x45}, + {DIG_CTRL0_VBAT_THRM_FLT_CTL, 0x7f}, + {DIG_CTRL0_CDC_RXTX_FSCNT_CTL, 0x00}, + {DIG_CTRL0_GAIN_RAMP0_CTL1, 0x01}, + {DIG_CTRL0_GAIN_RAMP1_CTL1, 0x01}, + {DIG_CTRL1_I2S_CTL0, 0x06}, + {DIG_CTRL1_I2S_CFG0_TDM_TX, 0x00}, + {DIG_CTRL1_I2S_CFG1_TDM_TX, 0x00}, + {DIG_CTRL1_I2S_TDM_CTL0, 0x00}, + {DIG_CTRL1_I2S_TDM_CTL1, 0x05}, + {DIG_CTRL1_I2S_TDM_CH_TX, 0x00}, + {DIG_CTRL1_I2S_RESET_CTL, 0x00}, + {DIG_CTRL1_I2S_TDM_CH_RX, 0x08}, + {CDC_RX0_RX_PATH_CFG0, 0x89}, + {CDC_RX0_RX_PATH_CFG1, 0x64}, + {CDC_RX0_RX_PATH_CTL, 0x24}, + {RX0_RX_PATH_DSMDEM_CTL, 0x01}, + {CDC_RX1_RX_PATH_CFG0, 0x89}, + {CDC_RX1_RX_PATH_CFG1, 0x64}, + {CDC_RX1_RX_PATH_CTL, 0x04}, + {RX1_RX_PATH_DSMDEM_CTL, 0x01}, + {CDC_COMPANDER0_CTL0, 0x01}, + {CDC_COMPANDER0_CTL7, 0x2a}, + {CDC_COMPANDER1_CTL0, 0x01}, + {CDC_COMPANDER1_CTL7, 0x2a}, + {CDC_VSENSE0_SPKR_PROT_PATH_CTL, 0x14}, + {CDC_VSENSE1_SPKR_PROT_PATH_CTL, 0x14}, + {CDC_ISENSE0_SPKR_PROT_PATH_CTL, 0x14}, + {CDC_ISENSE1_SPKR_PROT_PATH_CTL, 0x14}, + {CDC_CLSH_V1P8_BP_CTL1, 0x50}, + {CDC_CLSH_V1P8_BP_CTL0, 0x6c}, + {CDC_CLSH_CLSH_SIG_DP_CTL0, 0x0d}, + {CDC_CLSH_CLSH_V_HD_PA, 0x03}, + {CDC_CLSH_V1P8_BP_CTL2, 0x05}, +}; + +static int wsa885x_gpio_set(struct wsa885x_i2c_priv *wsa885x, bool val) +{ + int ret = 0; + + if (val) + ret = gpiod_direction_output(wsa885x->sd_n, 1); + else + ret = gpiod_direction_output(wsa885x->sd_n, 0); + + if (ret < 0) { + dev_err_ratelimited(wsa885x->dev, "%s: failed to set GPIO: %d\n", __func__, + ret); + } + return ret; +} + +static void reg_update_sequence(struct regmap *regmap) +{ + regmap_write(regmap, DIG_CTRL1_I2S_TDM_CTL1, 0x15); + regmap_write(regmap, DIG_CTRL1_I2S_TDM_CTL1, 0x11); + + /* Configure TDM control register 0 */ + regmap_write(regmap, DIG_CTRL1_I2S_TDM_CTL0, 0x04); + regmap_update_bits(regmap, DIG_CTRL1_I2S_TDM_CTL0, 0x01, 0x01); + + /* Configure TDM transmit channel settings */ + regmap_write(regmap, DIG_CTRL1_I2S_TDM_CH_TX, 0x01); + regmap_update_bits(regmap, DIG_CTRL1_I2S_TDM_CH_TX, 0x02, 0x02); +} + +static int wait_for_pll_lock(struct wsa885x_i2c_priv *wsa885x) +{ + unsigned int status; + int cnt = 0; + int ret = 0; + + do { + usleep_range(1000, 1100); + ret = regmap_read(wsa885x->regmap, ANA_TOP_PLL_STATUS_0, &status); + + /* Check if PLL is locked (bit 0 set) */ + if (ret == 0 && (status & WSA885X_PLL_LOCK_BIT)) { + dev_dbg(wsa885x->component->dev, "PLL locked successfully after %d ms\n", + cnt + 1); + return 0; + } + } while (++cnt < 20); /* Maximum 20ms timeout */ + + /* PLL lock timeout */ + dev_warn(wsa885x->component->dev, "PLL lock timeout after 20ms, status=0x%x\n", status); + return -ETIMEDOUT; +} + +static void wsa885x_2s_conf(struct wsa885x_i2c_priv *wsa885x) +{ + regmap_write(wsa885x->regmap, SPK_TOP_COMMON_TUNE1, 0x03); + regmap_write(wsa885x->regmap, SPK_TOP_LF_CH1_CTRL11, 0x0d); + regmap_write(wsa885x->regmap, SPK_TOP_LF_CH2_CTRL11, 0x0d); + regmap_write(wsa885x->regmap, CDC_CLSH_V1P8_BP_CTL1, 0x71); + regmap_write(wsa885x->regmap, CDC_CLSH_V1P8_BP_CTL0, 0xAA); +} + +static int wait_for_pde_state(struct wsa885x_i2c_priv *wsa885x, + int ps, int reg) +{ + int act_ps, cnt = 0, clock_valid; + int rc = 0; + + /* Poll for power state transition with timeout */ + do { + usleep_range(1000, 1500); + + /* Read actual power state from PDE register */ + rc = regmap_read(wsa885x->regmap, + SMP_AMP_CTRL_STEREO_PDE23_ACT_PS, + &act_ps); + + /* Check if desired power state is reached */ + if (rc == 0 && act_ps == ps) + return 0; + } while (++cnt < 5); + + /* Read clock validity status for debugging */ + regmap_read(wsa885x->regmap, + SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID, + &clock_valid); + + dev_err(wsa885x->component->dev, + "PDE power state %d request failed, actual_ps %d, clock_valid:%d\n", + ps, act_ps, clock_valid); + + return -ETIMEDOUT; +} + +static int codec_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct wsa885x_i2c_priv *wsa885x = snd_soc_component_get_drvdata(component); + uint8_t value, cs21_sample_rate_idx, cs24_sample_rate_idx; + int open_count = 0; + + dev_dbg(wsa885x->dev, "%s: HW Params called with sampling rate as %d\n", __func__, + params_rate(params)); + + /* Check if multiple streams are open - only configure on first stream */ + open_count = atomic_read(&wsa885x->open_count); + if (open_count > 1) + return 0; + + /* Extract sample rate from ALSA parameters */ + wsa885x->sample_rate = params_rate(params); + + /* Map sample rate to codec-specific rate indices */ + switch (wsa885x->sample_rate) { + case 8000: + value = 0x00; + cs21_sample_rate_idx = WSA885X_RX_RATE_8000HZ; + cs24_sample_rate_idx = WSA885X_VI_RATE_8000HZ; + break; + case 16000: + value = 0x01; + cs21_sample_rate_idx = WSA885X_RX_RATE_16000HZ; + cs24_sample_rate_idx = WSA885X_VI_RATE_16000HZ; + break; + case 32000: + value = 0x02; + cs21_sample_rate_idx = WSA885X_RX_RATE_32000HZ; + cs24_sample_rate_idx = WSA885X_VI_RATE_48000HZ; + break; + case 44100: + value = 0x03; + cs21_sample_rate_idx = WSA885X_RX_RATE_44100HZ; + cs24_sample_rate_idx = WSA885X_VI_RATE_44100HZ; + break; + case 48000: + value = 0x03; + cs21_sample_rate_idx = WSA885X_RX_RATE_48000HZ; + cs24_sample_rate_idx = WSA885X_VI_RATE_48000HZ; + break; + case 88200: + case 96000: + value = 0x04; + cs21_sample_rate_idx = WSA885X_RX_RATE_96000HZ; + cs24_sample_rate_idx = WSA885X_VI_RATE_96000HZ; + break; + case 176400: + case 192000: + value = 0x05; + cs21_sample_rate_idx = WSA885X_RX_RATE_192000HZ; + cs24_sample_rate_idx = WSA885X_VI_RATE_192000HZ; + break; + case 352800: + case 384000: + value = 0x06; + cs21_sample_rate_idx = WSA885X_RX_RATE_384000HZ; + cs24_sample_rate_idx = WSA885X_VI_RATE_384000HZ; + break; + default: + dev_err(component->dev, "sampling rate %d is not supported\n", + params_rate(params)); + return -EINVAL; + } + + /* Configure I2S control register with sample rate (bits 1:4) and enable bit */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CTL0, 0x1f, + (value << 1) + 1); + + /* Reset I2S interface */ + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_RESET_CTL, 0x00); + + /* Set RX (playback) sample rate index */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_CS21_SAMPLERATEINDEX, + cs21_sample_rate_idx); + + /* Set VI (voltage/current sensing) sample rate index */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_CS24_SAMPLERATEINDEX, + cs24_sample_rate_idx); + + /* Program FU21 volume with current dB value (MSB) and zero LSB, then commit */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_MSB, wsa885x->stereo_voldB); + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_LSB, 0x00); + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_MSB, wsa885x->stereo_voldB); + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_LSB, 0x00); + regmap_write(wsa885x->regmap, DIG_CTRL0_SDCA_COMMIT, 0x01); + + return 0; +} + +static int codec_set_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_slot_mask, + unsigned int rx_slot_mask, int slots, + int slot_width) +{ + struct snd_soc_component *component = dai->component; + struct wsa885x_i2c_priv *wsa885x = + snd_soc_component_get_drvdata(component); + + dev_dbg(wsa885x->dev, "%s: TDM num_slots configured as %d\n", __func__, slots); + + /* Increment open count atomically - only configure on first call */ + if (atomic_inc_return(&wsa885x->open_count) > 1) + return 0; + + /* Reset I2S interface before configuration */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_RESET_CTL, 0x01, 0x01); + + /* Configure TDM slots based on channel mask */ + if (wsa885x->rx_slot_mask == WSA885X_CHANNEL_STEREO) { + /* Stereo configuration - both channels active */ + /* Configure slot0 for I-sense channel 0 */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CFG0_TDM_TX, + 0x01, 0x01); + /* Configure slot1 for I-sense channel 1 */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CFG0_TDM_TX, + 0x20, 0x20); + /* Configure slot3 for current protection sense 0 */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CFG1_TDM_TX, + 0x05, 0x05); + /* Configure slot4 for current protection sense 1 */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CFG1_TDM_TX, + 0x60, 0x60); + /* Apply TDM control sequence */ + reg_update_sequence(wsa885x->regmap); + /* Enable transmit channels */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_TDM_CH_TX, + 0x04, 0x04); + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_TDM_CH_TX, + 0x08, 0x08); + } else if (wsa885x->rx_slot_mask == WSA885X_CHANNEL_MONO_LEFT) { + /* Mono left channel configuration */ + /* Configure slot0 for I-sense channel 0 */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CFG0_TDM_TX, + 0x01, 0x01); + /* Configure slot1 for current protection sense 0 */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CFG0_TDM_TX, + 0x50, 0x50); + reg_update_sequence(wsa885x->regmap); + } else if (wsa885x->rx_slot_mask == WSA885X_CHANNEL_MONO_RIGHT) { + /* Mono right channel configuration */ + /* Configure slot0 for I-sense channel 1 */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CFG0_TDM_TX, + 0x02, 0x02); + /* Configure slot1 for current protection sense 1 */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CFG0_TDM_TX, + 0x60, 0x60); + reg_update_sequence(wsa885x->regmap); + } + + /* Enable I2S control */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_CTL0, 0x01, 0x01); + + /* Release I2S reset */ + regmap_update_bits(wsa885x->regmap, DIG_CTRL1_I2S_RESET_CTL, 0x01, 0x00); + + return 0; +} + +static int codec_set_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct snd_soc_component *component = dai->component; + struct wsa885x_i2c_priv *wsa885x = + snd_soc_component_get_drvdata(component); + uint8_t pll_div; + int i, open_count = 0, ret = 0; + + dev_dbg(wsa885x->dev, "%s: Freq: %d\n", __func__, freq); + + /* Check if multiple streams are open - only configure on first stream */ + open_count = atomic_read(&wsa885x->open_count); + if (open_count > 1) + return 0; + + /* Calculate PLL divider: Fixed rate / target frequency */ + pll_div = CLK_RATE_FIXED / freq; + + /* Configure analog bias and thermal/voltage protection override */ + regmap_write(wsa885x->regmap, ANA_TOP_BG_TVP_OVRD_CTL, 0x03); + + /* Select internal system clock source */ + regmap_write(wsa885x->regmap, DIG_CTRL0_SYS_CLK_SEL, 0x04); + + /* Configure PLL loop filter for stability */ + regmap_write(wsa885x->regmap, ANA_TOP_PLL_LOOPFILT_0, 0xB4); + + /* Configure VCO (Voltage Controlled Oscillator) */ + regmap_write(wsa885x->regmap, ANA_TOP_PLL_VCO_CTL, 0x00); + + /* Disable PLL override mode */ + regmap_write(wsa885x->regmap, ANA_TOP_PLL_OVRD_CTL, 0x00); + + /* Set calculated PLL divider */ + regmap_write(wsa885x->regmap, ANA_PLL_DIV_CTL_0, pll_div); + + /* Enable PLL clock source */ + regmap_write(wsa885x->regmap, DIG_CTRL0_CLK_SOURCE_ENABLE, 0x02); + + /* Wait for PLL to lock with intelligent polling */ + ret = wait_for_pll_lock(wsa885x); + if (ret) { + dev_err(wsa885x->component->dev, "PLL lock failed, aborting sysclk configuration\n"); + return ret; + } + + /* Switch to PLL as system clock source */ + regmap_write(wsa885x->regmap, DIG_CTRL0_SYS_CLK_SEL, 0x00); + + /* Enable power FSM control */ + regmap_write(wsa885x->regmap, DIG_CTRL0_POWER_FSM_CTL1, 0x01); + + /* Apply codec-specific initialization table from device tree */ + for (i = 0; i < wsa885x->init_table_size / 2; i++) { + if (wsa885x->batt_conf == batt_2s && wsa885x->init_table[2 * i] == + SPK_TOP_LF_CH1_CTRL11) + wsa885x_2s_conf(wsa885x); + else if (wsa885x->batt_conf == batt_2s && + wsa885x->init_table[2 * i] == SPK_TOP_COMMON_TUNE1) + regmap_write(wsa885x->regmap, SPK_TOP_COMMON_TUNE1, 0x26); + else + regmap_write(wsa885x->regmap, wsa885x->init_table[2 * i], + wsa885x->init_table[2 * i + 1]); + } + return 0; +} + +static int codec_mute_stream(struct snd_soc_dai *dai, int mute, int stream) +{ + struct wsa885x_i2c_priv *wsa885x = snd_soc_dai_get_drvdata(dai); + int ret = 0, ps0 = 0, ps3 = 3, open_count = 0; + + dev_dbg(wsa885x->dev, "%s: Stream is %s\n", __func__, mute ? "muted" : "unmuted"); + + if (mute) { + open_count = atomic_dec_return(&wsa885x->open_count); + if (open_count > 0) + return 0; + regmap_write(wsa885x->regmap, DIG_CTRL0_PA_FSM_CTL, 0x00); + /* Request power state 3 (low power/standby mode) */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_PDE23_REQ_PS, 0x03); + ret = wait_for_pde_state(wsa885x, ps3, SMP_AMP_CTRL_STEREO_PDE23_ACT_PS); + if (!ret) { + dev_dbg(wsa885x->component->dev, + "Successfully transitioned to power state %d\n", ps3); + } + } else { + open_count = atomic_read(&wsa885x->open_count); + if (open_count > 1) + return 0; + /* Disable power amplifier FSM before configuration */ + regmap_write(wsa885x->regmap, DIG_CTRL0_PA_FSM_CTL, 0x00); + + /* Configure usage mode for thermal/speaker protection */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_OT23_USAGE, + wsa885x->usage_mode); + + /* Set cluster index for audio processing */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_IT21_CLUSERINDEX, 0x01); + + /* Set posture number for speaker configuration */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_PPU21_POSTURENUMBER, 0x01); + + /* Apply requested volume */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_MSB, wsa885x->stereo_voldB); + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_LSB, 0x00); + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_MSB, wsa885x->stereo_voldB); + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_LSB, 0x00); + + regmap_write(wsa885x->regmap, DIG_CTRL0_SDCA_COMMIT, 0x01); + + /* Request power state 0 (active mode) */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_PDE23_REQ_PS, 0x00); + ret = wait_for_pde_state(wsa885x, ps0, SMP_AMP_CTRL_STEREO_PDE23_ACT_PS); + if (!ret) { + dev_dbg(wsa885x->component->dev, + "Successfully transitioned to power state %d\n", ps0); + } else { + dev_err(wsa885x->component->dev, "PS0 request failed\n"); + goto exit; + } + + /* Configure power amplifier based on channel configuration */ + if (wsa885x->rx_slot_mask == 0b11) { + /* Stereo mode - enable both PA channels */ + regmap_write(wsa885x->regmap, DIG_CTRL0_PA_FSM_CTL, 0x03); + } else if (wsa885x->rx_slot_mask == 0b01) { + /* Mono left channel */ + regmap_write(wsa885x->regmap, DIG_CTRL0_PA_FSM_CTL, 0x01); + } else if (wsa885x->rx_slot_mask == 0b10) { + /* Mono right channel */ + regmap_write(wsa885x->regmap, DIG_CTRL0_PA_FSM_CTL, 0b10); + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_TDM_CH_RX, 0b01); + } + + /* Unmute both channels */ + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X0, 0x00); + regmap_write(wsa885x->regmap, SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X1, 0x00); + + /* Commit all changes */ + regmap_write(wsa885x->regmap, DIG_CTRL0_SDCA_COMMIT, 0x01); + } +exit: + return ret; +} + +static int codec_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct wsa885x_i2c_priv *wsa885x = + snd_soc_component_get_drvdata(component); + int open_count = 0; + + dev_dbg(wsa885x->dev, "%s: HW Free, resetting I2S registers\n", __func__); + + open_count = atomic_read(&wsa885x->open_count); + if (open_count > 0) + return 0; + + /* Reset I2S register in any case */ + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_RESET_CTL, 0x00); + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_CFG0_TDM_TX, 0x00); + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_CFG1_TDM_TX, 0x00); + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_TDM_CTL1, 0x05); + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_TDM_CTL0, 0x00); + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_TDM_CH_TX, 0x00); + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_CTL0, 0x06); + regmap_write(wsa885x->regmap, DIG_CTRL1_I2S_TDM_CH_RX, 0x08); + + /* Reset Clock */ + regmap_write(wsa885x->regmap, DIG_CTRL0_CLK_SOURCE_ENABLE, 0x00); + regmap_write(wsa885x->regmap, ANA_TOP_BG_TVP_OVRD_CTL, 0x00); + + return 0; +} + +static const struct snd_soc_dai_ops wsa885x_i2c_dai_ops = { + .hw_params = codec_hw_params, + .set_tdm_slot = codec_set_tdm_slot, + .set_sysclk = codec_set_sysclk, + .mute_stream = codec_mute_stream, + .hw_free = codec_hw_free, +}; + +static struct snd_soc_dai_driver wsa885x_i2c_dai[] = { + { + .name = "wsa885x_dai_drv", + .playback = { + .stream_name = "WSA885X I2C TDM Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .ops = &wsa885x_i2c_dai_ops, + }, +}; + +static void wsa885x_gpio_powerdown(void *data) +{ + gpiod_direction_output(data, 1); +} + +static bool wsa885x_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ANA_TOP_PLL_STATUS_0: + case ANA_TOP_PLL_STATUS_1: + case SMP_AMP_CTRL_STEREO_PDE23_ACT_PS: + case SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID: + case WSA885X_INTR_STATUS0: + case WSA885X_INTR_STATUS0 + 1: + case WSA885X_INTR_STATUS0 + 2: + case WSA885X_INTR_CLEAR0: + case WSA885X_INTR_CLEAR0 + 1: + case WSA885X_INTR_CLEAR0 + 2: + return true; + default: + return false; + } +} + +static bool wsa885x_readable_register(struct device *dev, unsigned int reg) +{ + if (reg >= 0 && reg <= 0x88ff) + return true; + return false; +} + +static bool wsa885x_writeable_register(struct device *dev, unsigned int reg) +{ + if (reg >= 0 && reg <= 0x88ff) { + /* Read-only status registers */ + if (reg == ANA_TOP_PLL_STATUS_0 || + reg == WSA885X_INTR_STATUS0 || + reg == WSA885X_INTR_STATUS0 + 1 || + reg == WSA885X_INTR_STATUS0 + 2 || + reg == SMP_AMP_CTRL_STEREO_PDE23_ACT_PS || + reg == SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID) + return false; + return true; + } + return false; +} + +static const struct regmap_config regmap_cfg = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0x88FF, + .ranges = regmap_ranges, + .num_ranges = ARRAY_SIZE(regmap_ranges), + .reg_defaults = codec_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(codec_reg_defaults), + .volatile_reg = wsa885x_volatile_register, + .writeable_reg = wsa885x_writeable_register, + .readable_reg = wsa885x_readable_register, + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static int wsa885x_component_probe(struct snd_soc_component *component) +{ + struct wsa885x_i2c_priv *wsa885x = + snd_soc_component_get_drvdata(component); + wsa885x->component = component; + snd_soc_component_init_regmap(component, wsa885x->regmap); + /* Enable interrupts */ + regmap_write(wsa885x->regmap, DIG_CTRL1_SPMI_PAD_GPIO2_CTL, 0x2e); + regmap_write(wsa885x->regmap, DIG_CTRL1_INTR_MODE, 0x01); + regmap_write(wsa885x->regmap, DIG_CTRL1_PIN_CT, 0x04); + regmap_write(wsa885x->regmap, WSA885X_INTR_MASK0, 0x00); + regmap_write(wsa885x->regmap, WSA885X_INTR_MASK0 + 1, 0x00); + regmap_write(wsa885x->regmap, WSA885X_INTR_MASK0 + 2, 0xf8); + + return 0; +} + +static void wsa885x_component_remove(struct snd_soc_component *component) +{ + struct wsa885x_i2c_priv *wsa885x = + snd_soc_component_get_drvdata(component); + + if (!wsa885x) + return; + + snd_soc_component_exit_regmap(component); +} + +static void wsa885x_regulator_disable(void *data) +{ + regulator_bulk_disable(SUPPLIES_NUM, data); +} + +static int wsa885x_stereo_gain_offset_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct wsa885x_i2c_priv *wsa885x = + snd_soc_component_get_drvdata(component); + + /* UI range 0..124 maps to dB = value - 84; return slider value */ + ucontrol->value.integer.value[0] = wsa885x->stereo_voldB + 84; + return 0; +} + +static int wsa885x_stereo_gain_offset_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct wsa885x_i2c_priv *wsa885x = + snd_soc_component_get_drvdata(component); + long val = ucontrol->value.integer.value[0]; + + if (val < 0 || val > FU21_VOL_STEPS) { + dev_err(component->dev, "%s: Invalid range, Val: %ld\n", __func__, val); + return -EINVAL; + } + wsa885x->stereo_voldB = (int)val - 84; + dev_dbg(component->dev, "%s: Volume dB: %d\n", __func__, wsa885x->stereo_voldB); + return 0; +} + +static int wsa885x_i2c_usage_modes_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct wsa885x_i2c_priv *wsa885x_i2c = + snd_soc_component_get_drvdata(component); + + if (!wsa885x_i2c) + return -EINVAL; + + ucontrol->value.integer.value[0] = wsa885x_i2c->usage_mode; + + return 0; +} + +static int wsa885x_i2c_usage_modes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct wsa885x_i2c_priv *wsa885x_i2c = + snd_soc_component_get_drvdata(component); + + if (!wsa885x_i2c) + return -EINVAL; + + wsa885x_i2c->usage_mode = ucontrol->value.integer.value[0]; + + dev_dbg(component->dev, "%s: Usage mode:%d\n", __func__, + wsa885x_i2c->usage_mode); + + return 0; +} + +static int wsa885x_i2c_rx_slot_mask_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct wsa885x_i2c_priv *wsa885x_i2c = + snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = wsa885x_i2c->rx_slot_mask; + + return 0; +} + +static int wsa885x_i2c_rx_slot_mask_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct wsa885x_i2c_priv *wsa885x_i2c = + snd_soc_component_get_drvdata(component); + + wsa885x_i2c->rx_slot_mask = ucontrol->value.enumerated.item[0]; + + dev_dbg(component->dev, "%s: Rx channel:%d select\n", __func__, + wsa885x_i2c->rx_slot_mask); + return 0; +} + +static const struct snd_kcontrol_new wsa885x_snd_controls[] = { + SOC_SINGLE_EXT("OT23 Usage Mode", SND_SOC_NOPM, 0, 8, 0, + wsa885x_i2c_usage_modes_get, + wsa885x_i2c_usage_modes_put), + + SOC_SINGLE_EXT_TLV("SA1 FU21 Stereo Gain Offset dB", SND_SOC_NOPM, + 0, FU21_VOL_STEPS, 0, + wsa885x_stereo_gain_offset_get, + wsa885x_stereo_gain_offset_put, + fu21_digital_gain), + + SOC_SINGLE_EXT("Rx Slot Mask", SND_SOC_NOPM, 0, 4, 0, + wsa885x_i2c_rx_slot_mask_get, + wsa885x_i2c_rx_slot_mask_put), +}; + +static const struct snd_soc_component_driver wsa885x_i2c_component = { + .name = "wsa885x-i2c", + .probe = wsa885x_component_probe, + .remove = wsa885x_component_remove, + .controls = wsa885x_snd_controls, + .num_controls = ARRAY_SIZE(wsa885x_snd_controls), + .dapm_widgets = NULL, + .num_dapm_widgets = 0, + .dapm_routes = NULL, + .num_dapm_routes = 0, +}; + +static irqreturn_t handle_wsa885x_i2c_irq(int irq, void *data) +{ + struct wsa885x_i2c_priv *wsa885x = data; + + /* Handle the interrupt based on the IRQ number */ + switch (irq) { + case WSA885X_IRQ_INT_SAF2WAR: + case WSA885X_IRQ_INT_WAR2SAF: + case WSA885X_IRQ_INT_PA0_OCP: + case WSA885X_IRQ_INT_PA1_OCP: + case WSA885X_IRQ_INT_CLIP0: + case WSA885X_IRQ_INT_CLIP1: + case WSA885X_IRQ_INT_CLK_WD: + case WSA885X_IRQ_INT_BOP: + case WSA885X_IRQ_INT_UVLO: + case WSA885X_IRQ_INT_PCM_DATA0_DC: + case WSA885X_IRQ_INT_PCM_DATA1_DC: + case WSA885X_IRQ_INT_PLL_UNLOCKED: + case WSA885X_IRQ_INT_PROT_MODE_CHANGE: + case WSA885X_IRQ_INT_PB_CLOCK_VALID: + case WSA885X_IRQ_INT_SENSE_CLOCK_VALID: + break; + case WSA885X_IRQ_INT_PCM_DATA0_WD: + case WSA885X_IRQ_INT_PCM_DATA1_WD: + if (!wsa885x) + return IRQ_NONE; + if (irq == WSA885X_IRQ_INT_PCM_DATA0_WD) { + regmap_update_bits(wsa885x->regmap, 0x84A0, + 0x04, 0x00); + regmap_update_bits(wsa885x->regmap, 0x84A0, + 0x04, 0x01); + } else { + regmap_update_bits(wsa885x->regmap, 0x84A4, + 0x04, 0x00); + regmap_update_bits(wsa885x->regmap, 0x84A4, + 0x04, 0x01); + } + break; + case WSA885X_IRQ_INT_PA0_FSM_ERR: + case WSA885X_IRQ_INT_PA1_FSM_ERR: + case WSA885X_IRQ_INT_MAIN_FSM_ERR: + if (!wsa885x) + return IRQ_NONE; + + if (irq == WSA885X_IRQ_INT_MAIN_FSM_ERR) { + regmap_update_bits(wsa885x->regmap, WSA885X_POWER_FSM_CTL0, + 0x08, 0x00); + regmap_update_bits(wsa885x->regmap, WSA885X_POWER_FSM_CTL0, + 0x08, 0x08); + regmap_update_bits(wsa885x->regmap, WSA885X_POWER_FSM_CTL0, + 0x08, 0x00); + } else if (irq == WSA885X_IRQ_INT_PA0_FSM_ERR) { + regmap_update_bits(wsa885x->regmap, WSA885X_PA0_FSM_CTL0, + 0x04, 0x00); + regmap_update_bits(wsa885x->regmap, WSA885X_PA0_FSM_CTL0, + 0x04, 0x04); + regmap_update_bits(wsa885x->regmap, WSA885X_PA0_FSM_CTL0, + 0x04, 0x00); + } else if (irq == WSA885X_IRQ_INT_PA1_FSM_ERR) { + regmap_update_bits(wsa885x->regmap, WSA885X_PA1_FSM_CTL0, + 0x04, 0x00); + regmap_update_bits(wsa885x->regmap, WSA885X_PA1_FSM_CTL0, + 0x04, 0x04); + regmap_update_bits(wsa885x->regmap, WSA885X_PA1_FSM_CTL0, + 0x04, 0x00); + } + break; + default: + dev_warn(wsa885x->dev, "Unhandled IRQ: %d\n", irq); + return IRQ_NONE; + } + + pr_err_ratelimited("%s: handled %s interrupt\n", __func__, + wsa885x_irq_names[irq]); + + return IRQ_HANDLED; +} + +static irqreturn_t wsa885x_interrupt_handler(int irq, void *data) +{ + unsigned int status[NUM_REGS]; + int i, bit, ret = IRQ_NONE; + int irq_num; + struct wsa885x_i2c_priv *wsa885x = data; + int status_reg[NUM_REGS] = { + WSA885X_INTR_STATUS0, + WSA885X_INTR_STATUS0 + 1, + WSA885X_INTR_STATUS0 + 2 + }; + int clear_reg[NUM_REGS] = { + WSA885X_INTR_CLEAR0, + WSA885X_INTR_CLEAR0 + 1, + WSA885X_INTR_CLEAR0 + 2 + }; + + pr_debug("%s: interrupt for irq = %d triggered\n", __func__, irq); + /* Read all status registers */ + for (i = 0; i < NUM_REGS; i++) { + ret = regmap_read(wsa885x->regmap, status_reg[i], &status[i]); + if (ret) { + dev_err(wsa885x->dev, "Failed to read status_reg[%d] (0x%x): %d\n", + i, status_reg[i], ret); + return IRQ_NONE; + } + } + + for (i = 0; i < NUM_REGS; i++) { + for (bit = 0; bit < 8; bit++) { + if (status[i] & (1 << bit)) { + irq_num = i * 8 + bit; + ret = handle_wsa885x_i2c_irq(irq_num, wsa885x); + /* Clear the interrupt by writing 1 to the bit */ + regmap_update_bits(wsa885x->regmap, + clear_reg[i], + (1 << bit), + (1 << bit)); + /* Optionally clear again to 0 if needed */ + regmap_update_bits(wsa885x->regmap, + clear_reg[i], + (1 << bit), 0); + } + } + } + return ret; +} + +static int wsa885x_register_irq(struct wsa885x_i2c_priv *wsa885x) +{ + int ret; + + /* Get the IRQ number for the GPIO */ + int irq_number = gpiod_to_irq(wsa885x->intr_pin); + + if (irq_number < 0) { + pr_err("Failed to get IRQ number\n"); + gpiod_put(wsa885x->intr_pin); + return irq_number; + } + + ret = devm_request_threaded_irq(wsa885x->dev, irq_number, NULL, + wsa885x_interrupt_handler, + IRQF_SHARED | IRQF_ONESHOT | IRQF_TRIGGER_FALLING, "WSA885X I2C Interrupt", + wsa885x); + if (ret) { + dev_err(wsa885x->dev, "Failed to request IRQ for wsa885x i2c\n"); + gpiod_put(wsa885x->intr_pin); + return ret; + } + return ret; +} + +static int wsa885x_i2c_probe(struct i2c_client *client) +{ + struct wsa885x_i2c_priv *wsa885x; + const char *init_table_prop = "wsa885x-init-table"; + int ret, i; + struct device *dev = &client->dev; + + wsa885x = devm_kzalloc(&client->dev, sizeof(struct wsa885x_i2c_priv), + GFP_KERNEL); + if (!wsa885x) + return -ENOMEM; + + wsa885x->client = client; + wsa885x->dev = dev; + wsa885x->stereo_voldB = -84; + wsa885x->regmap = devm_regmap_init_i2c(client, ®map_cfg); + atomic_set(&wsa885x->open_count, 0); + + if (IS_ERR(wsa885x->regmap)) + return PTR_ERR(wsa885x->regmap); + + wsa885x->init_table_size = + of_property_count_u32_elems(dev->of_node, init_table_prop); + + if (wsa885x->init_table_size <= 0) { + dev_err(dev, "%s: Failed to count elements from %s\n", + __func__, init_table_prop); + return -EINVAL; + } + + if (wsa885x->init_table_size % 2 != 0) { + dev_err(dev, "%s: Invalid number of elements in %s\n", + __func__, init_table_prop); + return -EINVAL; + } + + wsa885x->init_table = devm_kzalloc( + dev, wsa885x->init_table_size * sizeof(u32), GFP_KERNEL); + if (!wsa885x->init_table) + return -ENOMEM; + + if (of_property_read_u32_array(dev->of_node, init_table_prop, + wsa885x->init_table, + wsa885x->init_table_size)) { + dev_err(dev, + "%s: Failed to read %s\n", + __func__, init_table_prop); + return -EINVAL; + } + + ret = of_property_read_u32(dev->of_node, "qcom,battery_config", &wsa885x->batt_conf); + if (ret) { + dev_err(dev, "battery_config not specified, 1S is default: %d\n", ret); + wsa885x->batt_conf = batt_1s; + } + + for (i = 0; i < SUPPLIES_NUM; i++) + wsa885x->supplies[i].supply = supply_name[i]; + + ret = devm_regulator_bulk_get(dev, SUPPLIES_NUM, wsa885x->supplies); + if (ret) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); + + ret = regulator_bulk_enable(SUPPLIES_NUM, wsa885x->supplies); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable regulators\n"); + + ret = devm_add_action_or_reset(dev, wsa885x_regulator_disable, + wsa885x->supplies); + if (ret) { + dev_err(dev, "failed to devm_add_action_or_reset, %d\n", ret); + return ret; + } + + wsa885x->sd_n = + devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH); + if (IS_ERR(wsa885x->sd_n)) + return dev_err_probe(dev, PTR_ERR(wsa885x->sd_n), + "Shutdown Control GPIO not found\n"); + + ret = wsa885x_gpio_set(wsa885x, false); + if (ret != 0) + return ret; + + ret = devm_add_action_or_reset(dev, wsa885x_gpio_powerdown, + wsa885x->sd_n); + if (ret) { + dev_err(dev, "failed to devm_add_action_or_reset, %d\n", ret); + return ret; + } + + ret = devm_snd_soc_register_component(dev, &wsa885x_i2c_component, wsa885x_i2c_dai, + ARRAY_SIZE(wsa885x_i2c_dai)); + if (ret) { + dev_err(dev, "Codec component registration failed\n"); + } else { + dev_dbg(dev, "Codec component:dai %s registration success!\n", + wsa885x_i2c_dai[0].name); + } + + i2c_set_clientdata(client, wsa885x); + + wsa885x->intr_pin = devm_gpiod_get_optional(dev, "interrupt", GPIOD_IN); + if (IS_ERR(wsa885x->intr_pin)) { + ret = PTR_ERR(wsa885x->intr_pin); + dev_err(dev, "Failed to get interrupt pin, %d\n", ret); + return ret; + } + + ret = wsa885x_register_irq(wsa885x); + if (ret) + dev_err(dev, "wsa885x irq registration failed ret: %d\n", ret); + + return ret; +} + +static const struct of_device_id wsa885x_i2c_dt_match[] = { + { + .compatible = "qcom,wsa885x-i2c", + }, + {}}; + +static const struct i2c_device_id wsa885x_id_i2c[] = { + {"wsa885x_i2c", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, wsa885x_id_i2c); + +static struct i2c_driver i2c_slave_driver = { + .driver = { + .name = "wsa885x_i2c", + .of_match_table = wsa885x_i2c_dt_match, + }, + .probe = wsa885x_i2c_probe, + .id_table = wsa885x_id_i2c, +}; + +module_i2c_driver(i2c_slave_driver); + +MODULE_DESCRIPTION("ASoC WSA8855-I2C Smart PA Codec Driver"); +MODULE_LICENSE("GPL"); From 3de6f606238ae1c0f4e8f2483730fc09e1b07a3d Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 11 May 2026 12:07:27 +0530 Subject: [PATCH 0921/1330] arm64: defconfig: Enable WSA885X-I2C and PM4125 Shikra EVK boards Signed-off-by: Mohammad Rafi Shaik (cherry picked from commit 74e831cd3e38548fb1916c0fb41cc78649de7ad5) --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c2dde76d6b08f..a943d6c7d677e 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1094,6 +1094,8 @@ CONFIG_SND_MESON_AXG_SOUND_CARD=m CONFIG_SND_MESON_GX_SOUND_CARD=m CONFIG_SND_SOC_QCOM=m CONFIG_SND_SOC_APQ8016_SBC=m +CONFIG_SND_SOC_PM4125=m +CONFIG_SND_SOC_PM4125_SDW=m CONFIG_SND_SOC_QDSP6_USB=m CONFIG_SND_SOC_MSM8996=m CONFIG_SND_SOC_SDM845=m @@ -1176,6 +1178,7 @@ CONFIG_SND_SOC_WM8978=m CONFIG_SND_SOC_WSA881X=m CONFIG_SND_SOC_WSA883X=m CONFIG_SND_SOC_WSA884X=m +CONFIG_SND_SOC_WSA885X_I2C=m CONFIG_SND_SOC_NAU8822=m CONFIG_SND_SOC_LPASS_WSA_MACRO=m CONFIG_SND_SOC_LPASS_VA_MACRO=m From aae7aad60361fdf7da06a3c6b5b33ad8aa51a8ae Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Tue, 13 May 2025 09:58:23 +0530 Subject: [PATCH 0922/1330] FROMLIST: misc: fastrpc: Fix initial memory allocation for Audio PD memory pool The initial buffer allocated for the Audio PD memory pool is never added to the pool because pageslen is set to 0. As a result, the buffer is not registered with Audio PD and is never used, causing a memory leak. Audio PD immediately falls back to allocating memory from the remote heap since the pool starts out empty. Fix this by setting pageslen to 1 so that the initially allocated buffer is correctly registered and becomes part of the Audio PD memory pool. Link: https://lore.kernel.org/all/20260409062617.1182-2-jianping.li@oss.qualcomm.com/ Fixes: 0871561055e66 ("misc: fastrpc: Add support for audiopd") Cc: stable@kernel.org Co-developed-by: Ekansh Gupta Signed-off-by: Ekansh Gupta Signed-off-by: Jianping Li (cherry picked from commit 9dcad42c27d25d0f584fe7089ed35555248e839d) --- drivers/misc/fastrpc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 5a67b60f7d9a5..9e43fa6409163 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -1579,7 +1579,9 @@ static int fastrpc_init_create_static_process(struct fastrpc_user *fl, err = PTR_ERR(name); goto err; } - + inbuf.client_id = fl->client_id; + inbuf.namelen = init.namelen; + inbuf.pageslen = 0; if (!fl->cctx->remote_heap) { err = fastrpc_remote_heap_alloc(fl, fl->sctx->dev, init.memlen, &fl->cctx->remote_heap); @@ -1602,12 +1604,10 @@ static int fastrpc_init_create_static_process(struct fastrpc_user *fl, goto err_map; } scm_done = true; + inbuf.pageslen = 1; } } - inbuf.client_id = fl->client_id; - inbuf.namelen = init.namelen; - inbuf.pageslen = 0; fl->pd = USER_PD; args[0].ptr = (u64)(uintptr_t)&inbuf; From 9ff9d9af9278a3419bf50aa29020e27056acc668 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Tue, 13 May 2025 09:58:24 +0530 Subject: [PATCH 0923/1330] FROMLIST: misc: fastrpc: Remove buffer from list prior to unmap operation fastrpc_req_munmap_impl() is called to unmap any buffer. The buffer is getting removed from the list after it is unmapped from DSP. This can create potential race conditions if any other thread removes the entry from list while unmap operation is ongoing. Remove the entry before calling unmap operation. Link: https://lore.kernel.org/all/20260409062617.1182-3-jianping.li@oss.qualcomm.com/ Fixes: 2419e55e532de ("misc: fastrpc: add mmap/unmap support") Cc: stable@kernel.org Co-developed-by: Ekansh Gupta Signed-off-by: Ekansh Gupta Signed-off-by: Jianping Li (cherry picked from commit cd522d4183baf51a28731a64174fd8a610ceab8c) --- drivers/misc/fastrpc.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 9e43fa6409163..04c9b88d49c0b 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -2141,9 +2141,6 @@ static int fastrpc_req_munmap_impl(struct fastrpc_user *fl, struct fastrpc_buf * &args[0]); if (!err) { dev_dbg(dev, "unmmap\tpt 0x%09lx OK\n", buf->raddr); - spin_lock(&fl->lock); - list_del(&buf->node); - spin_unlock(&fl->lock); fastrpc_buf_free(buf); } else { dev_err(dev, "unmmap\tpt 0x%09lx ERROR\n", buf->raddr); @@ -2157,6 +2154,7 @@ static int fastrpc_req_munmap(struct fastrpc_user *fl, char __user *argp) struct fastrpc_buf *buf = NULL, *iter, *b; struct fastrpc_req_munmap req; struct device *dev = fl->sctx->dev; + int err; if (copy_from_user(&req, argp, sizeof(req))) return -EFAULT; @@ -2164,6 +2162,7 @@ static int fastrpc_req_munmap(struct fastrpc_user *fl, char __user *argp) spin_lock(&fl->lock); list_for_each_entry_safe(iter, b, &fl->mmaps, node) { if ((iter->raddr == req.vaddrout) && (iter->size == req.size)) { + list_del(&iter->node); buf = iter; break; } @@ -2176,7 +2175,14 @@ static int fastrpc_req_munmap(struct fastrpc_user *fl, char __user *argp) return -EINVAL; } - return fastrpc_req_munmap_impl(fl, buf); + err = fastrpc_req_munmap_impl(fl, buf); + if (err) { + spin_lock(&fl->lock); + list_add_tail(&buf->node, &fl->mmaps); + spin_unlock(&fl->lock); + } + + return err; } static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) @@ -2267,14 +2273,17 @@ static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) if (copy_to_user((void __user *)argp, &req, sizeof(req))) { err = -EFAULT; - goto err_assign; + goto err_copy; } dev_dbg(dev, "mmap\t\tpt 0x%09lx OK [len 0x%08llx]\n", buf->raddr, buf->size); return 0; - +err_copy: + spin_lock(&fl->lock); + list_del(&buf->node); + spin_unlock(&fl->lock); err_assign: fastrpc_req_munmap_impl(fl, buf); From 306a2a46eefd6efdd45acdb64ae0069c8dbc7ab8 Mon Sep 17 00:00:00 2001 From: Jianping Li Date: Tue, 23 Dec 2025 15:50:59 +0800 Subject: [PATCH 0924/1330] FROMLIST: misc: fastrpc: Allocate entire reserved memory for Audio PD in probe Allocating and freeing Audio PD memory from userspace is unsafe because the kernel cannot reliably determine when the DSP has finished using the memory. Userspace may free buffers while they are still in use by the DSP, and remote free requests cannot be safely trusted. Allocate the entire Audio PD reserved-memory region upfront during rpmsg probe and tie its lifetime to the rpmsg channel. This avoids userspace- controlled alloc/free and ensures memory is reclaimed only when the DSP shuts down. Link: https://lore.kernel.org/all/20260409062617.1182-4-jianping.li@oss.qualcomm.com/ Signed-off-by: Jianping Li (cherry picked from commit c9010fca1f0da1ba943f691be84f78d298fa4770) --- drivers/misc/fastrpc.c | 103 ++++++++++++++++++++--------------------- 1 file changed, 51 insertions(+), 52 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 04c9b88d49c0b..29506f71b88f5 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -294,6 +294,8 @@ struct fastrpc_channel_ctx { struct kref refcount; /* Flag if dsp attributes are cached */ bool valid_attributes; + /* Flag if audio PD init mem was allocated */ + bool audio_init_mem; u32 dsp_attributes[FASTRPC_MAX_DSP_ATTRIBUTES]; struct fastrpc_device *secure_fdevice; struct fastrpc_device *fdevice; @@ -1550,15 +1552,16 @@ static int fastrpc_init_create_static_process(struct fastrpc_user *fl, struct fastrpc_init_create_static init; struct fastrpc_invoke_args *args; struct fastrpc_phy_page pages[1]; + struct fastrpc_channel_ctx *cctx = fl->cctx; char *name; int err; - bool scm_done = false; struct { int client_id; u32 namelen; u32 pageslen; } inbuf; u32 sc; + unsigned long flags; args = kzalloc_objs(*args, FASTRPC_CREATE_STATIC_PROCESS_NARGS); if (!args) @@ -1582,31 +1585,6 @@ static int fastrpc_init_create_static_process(struct fastrpc_user *fl, inbuf.client_id = fl->client_id; inbuf.namelen = init.namelen; inbuf.pageslen = 0; - if (!fl->cctx->remote_heap) { - err = fastrpc_remote_heap_alloc(fl, fl->sctx->dev, init.memlen, - &fl->cctx->remote_heap); - if (err) - goto err_name; - - /* Map if we have any heap VMIDs associated with this ADSP Static Process. */ - if (fl->cctx->vmcount) { - u64 src_perms = BIT(QCOM_SCM_VMID_HLOS); - - err = qcom_scm_assign_mem(fl->cctx->remote_heap->dma_addr, - (u64)fl->cctx->remote_heap->size, - &src_perms, - fl->cctx->vmperms, fl->cctx->vmcount); - if (err) { - dev_err(fl->sctx->dev, - "Failed to assign memory with dma_addr %pad size 0x%llx err %d\n", - &fl->cctx->remote_heap->dma_addr, - fl->cctx->remote_heap->size, err); - goto err_map; - } - scm_done = true; - inbuf.pageslen = 1; - } - } fl->pd = USER_PD; @@ -1618,8 +1596,25 @@ static int fastrpc_init_create_static_process(struct fastrpc_user *fl, args[1].length = inbuf.namelen; args[1].fd = -1; - pages[0].addr = fl->cctx->remote_heap->dma_addr; - pages[0].size = fl->cctx->remote_heap->size; + spin_lock_irqsave(&cctx->lock, flags); + if (!fl->cctx->audio_init_mem) { + if (!fl->cctx->remote_heap || + !fl->cctx->remote_heap->dma_addr || + !fl->cctx->remote_heap->size) { + spin_unlock_irqrestore(&cctx->lock, flags); + err = -ENOMEM; + goto err; + } + + pages[0].addr = fl->cctx->remote_heap->dma_addr; + pages[0].size = fl->cctx->remote_heap->size; + fl->cctx->audio_init_mem = true; + inbuf.pageslen = 1; + } else { + pages[0].addr = 0; + pages[0].size = 0; + } + spin_unlock_irqrestore(&cctx->lock, flags); args[2].ptr = (u64)(uintptr_t) pages; args[2].length = sizeof(*pages); @@ -1637,27 +1632,7 @@ static int fastrpc_init_create_static_process(struct fastrpc_user *fl, return 0; err_invoke: - if (fl->cctx->vmcount && scm_done) { - u64 src_perms = 0; - struct qcom_scm_vmperm dst_perms; - u32 i; - - for (i = 0; i < fl->cctx->vmcount; i++) - src_perms |= BIT(fl->cctx->vmperms[i].vmid); - - dst_perms.vmid = QCOM_SCM_VMID_HLOS; - dst_perms.perm = QCOM_SCM_PERM_RWX; - err = qcom_scm_assign_mem(fl->cctx->remote_heap->dma_addr, - (u64)fl->cctx->remote_heap->size, - &src_perms, &dst_perms, 1); - if (err) - dev_err(fl->sctx->dev, "Failed to assign memory dma_addr %pad size 0x%llx err %d\n", - &fl->cctx->remote_heap->dma_addr, fl->cctx->remote_heap->size, err); - } -err_map: - fastrpc_buf_free(fl->cctx->remote_heap); - fl->cctx->remote_heap = NULL; -err_name: + fl->cctx->audio_init_mem = false; kfree(name); err: kfree(args); @@ -2679,7 +2654,7 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) } } - if (domain_id == SDSP_DOMAIN_ID) { + if (domain_id == SDSP_DOMAIN_ID || domain_id == ADSP_DOMAIN_ID) { struct resource res; u64 src_perms; @@ -2693,6 +2668,15 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) goto err_free_data; } + if (domain_id == ADSP_DOMAIN_ID) { + data->remote_heap = + kzalloc_obj(*data->remote_heap, GFP_KERNEL); + if (!data->remote_heap) + return -ENOMEM; + + data->remote_heap->dma_addr = res.start; + data->remote_heap->size = resource_size(&res); + } } secure_dsp = !(of_property_read_bool(rdev->of_node, "qcom,non-secure-domain")); @@ -2773,6 +2757,7 @@ static void fastrpc_rpmsg_remove(struct rpmsg_device *rpdev) struct fastrpc_buf *buf, *b; struct fastrpc_user *user; unsigned long flags; + int err; /* No invocations past this point */ spin_lock_irqsave(&cctx->lock, flags); @@ -2790,8 +2775,22 @@ static void fastrpc_rpmsg_remove(struct rpmsg_device *rpdev) list_for_each_entry_safe(buf, b, &cctx->invoke_interrupted_mmaps, node) list_del(&buf->node); - if (cctx->remote_heap) - fastrpc_buf_free(cctx->remote_heap); + if (cctx->remote_heap && cctx->vmcount) { + u64 src_perms = 0; + struct qcom_scm_vmperm dst_perms; + + for (u32 i = 0; i < cctx->vmcount; i++) + src_perms |= BIT(cctx->vmperms[i].vmid); + + dst_perms.vmid = QCOM_SCM_VMID_HLOS; + dst_perms.perm = QCOM_SCM_PERM_RWX; + + err = qcom_scm_assign_mem(cctx->remote_heap->dma_addr, + cctx->remote_heap->size, &src_perms, + &dst_perms, 1); + if (!err) + fastrpc_buf_free(cctx->remote_heap); + } of_platform_depopulate(&rpdev->dev); From 4da7cc8f5ebbd0a639c8415a1e70e028544b3002 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Tue, 13 May 2025 09:58:21 +0530 Subject: [PATCH 0925/1330] FROMLIST: misc: fastrpc: Allow fastrpc_buf_free() to accept NULL Make fastrpc_buf_free() a no-op when passed a NULL pointer, allowing callers to avoid open-coded NULL checks. Link: https://lore.kernel.org/all/20260409062617.1182-5-jianping.li@oss.qualcomm.com/ Co-developed-by: Ekansh Gupta Signed-off-by: Ekansh Gupta Signed-off-by: Jianping Li (cherry picked from commit e0ba7183d63d0a96142a2eac288975e0393d172c) --- drivers/misc/fastrpc.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 29506f71b88f5..d8b61217adbe0 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -461,17 +461,12 @@ static int fastrpc_map_lookup(struct fastrpc_user *fl, int fd, static void fastrpc_buf_free(struct fastrpc_buf *buf) { - struct fastrpc_user *fl = buf->fl; - - if (!fl) + if (!buf) return; - mutex_lock(&fl->sctx->mutex); - if (fl->sctx->dev) { - dma_free_coherent(buf->dev, buf->size, buf->virt, - fastrpc_ipa_to_dma_addr(buf->fl->cctx, buf->dma_addr)); - kfree(buf); - } - mutex_unlock(&fl->sctx->mutex); + + dma_free_coherent(buf->dev, buf->size, buf->virt, + fastrpc_ipa_to_dma_addr(buf->fl->cctx, buf->dma_addr)); + kfree(buf); } static int __fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, @@ -590,8 +585,7 @@ static void fastrpc_context_free(struct kref *ref) for (i = 0; i < ctx->nbufs; i++) fastrpc_map_put(ctx->maps[i]); - if (ctx->buf) - fastrpc_buf_free(ctx->buf); + fastrpc_buf_free(ctx->buf); spin_lock_irqsave(&cctx->lock, flags); idr_remove(&cctx->ctx_idr, FIELD_GET(FASTRPC_CTXID_MASK, ctx->ctxid)); @@ -1820,8 +1814,7 @@ static int fastrpc_device_release(struct inode *inode, struct file *file) list_del(&fl->user); spin_unlock_irqrestore(&cctx->lock, flags); - if (fl->init_mem) - fastrpc_buf_free(fl->init_mem); + fastrpc_buf_free(fl->init_mem); list_for_each_entry_safe(ctx, n, &fl->pending, node) { list_del(&ctx->node); From 0cfa60c0dc71a320a5de5343c628a0168e20e716 Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Thu, 30 Apr 2026 15:38:03 +0530 Subject: [PATCH 0926/1330] PENDING: dt-bindings: media: qcom: venus: add iommu-map support Add optional iommu-map property to the Qualcomm Venus video codec binding to describe IOMMU stream IDs for additional functional blocks exposed by the hardware. Update the example to show how the firmware stream can be mapped to an SMMU stream ID using a function identifier. Signed-off-by: Renjiang Han (cherry picked from commit d2e80f291c1755e1a5e1b516847a971988886f4a) --- .../devicetree/bindings/media/qcom,sc7180-venus.yaml | 5 +++++ include/dt-bindings/media/qcom,qcs615-venus.h | 11 +++++++++++ 2 files changed, 16 insertions(+) create mode 100644 include/dt-bindings/media/qcom,qcs615-venus.h diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml index bfd8b1ad47312..5de4445a486d7 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml @@ -50,6 +50,9 @@ properties: iommus: maxItems: 1 + iommu-map: + maxItems: 1 + memory-region: maxItems: 1 @@ -101,6 +104,7 @@ unevaluatedProperties: false examples: - | #include + #include #include venus: video-codec@aa00000 { @@ -118,5 +122,6 @@ examples: clock-names = "core", "iface", "bus", "vcodec0_core", "vcodec0_bus"; iommus = <&apps_smmu 0x0c00 0x60>; + iommu-map = ; memory-region = <&venus_mem>; }; diff --git a/include/dt-bindings/media/qcom,qcs615-venus.h b/include/dt-bindings/media/qcom,qcs615-venus.h new file mode 100644 index 0000000000000..ca755f2f6aa40 --- /dev/null +++ b/include/dt-bindings/media/qcom,qcs615-venus.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_MEDIA_QCOM_QCS615_VENUS_H_ +#define _DT_BINDINGS_MEDIA_QCOM_QCS615_VENUS_H_ + +#define VENUS_FIRMWARE 0 + +#endif From 20e33cd5df21ed3a92d396824308d452dd74f3fd Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Thu, 30 Apr 2026 15:56:48 +0530 Subject: [PATCH 0927/1330] PENDING: media: qcom: venus: support PAS boot and flexible IOMMU handling On platforms where PAS is available, firmware authentication and reset are performed via the secure world, while IOMMU configuration may be handled either by Linux or outside of it. Extend the Venus firmware flow to support both PAS and non-PAS setups. When PAS is available, load the firmware using a PAS context and trigger the prepare/auth/reset sequence. If the firmware device is IOMMU-mapped, use its IOMMU domain to map the reserved firmware memory before reset; otherwise, retain the existing secure-world-managed behavior. When PAS is not available, fall back to the existing non-PAS firmware loading path where Linux performs firmware loading and IOMMU mapping. The firmware stream ID is described via the iommu-map function identifier in the device tree. Signed-off-by: Renjiang Han (cherry picked from commit 5ee68afd88991524d9bb3ff979c7928c70b1fa41) --- drivers/media/platform/qcom/venus/core.h | 2 + drivers/media/platform/qcom/venus/firmware.c | 294 ++++++++++++++----- 2 files changed, 217 insertions(+), 79 deletions(-) diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index a3a6cb4cc37bf..3921d65389cbc 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -221,6 +221,8 @@ struct venus_core { size_t mapped_mem_size; phys_addr_t mem_phys; size_t mem_size; + struct qcom_scm_pas_context *ctx; + bool iommu_domain_owned; } fw; struct mutex lock; struct list_head instances; diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/platform/qcom/venus/firmware.c index 1de7436713ed9..dbfb322a99978 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "core.h" #include "firmware.h" @@ -78,87 +79,125 @@ int venus_set_hw_state(struct venus_core *core, bool resume) return 0; } -static int venus_load_fw(struct venus_core *core, const char *fwname, - phys_addr_t *mem_phys, size_t *mem_size) +static int venus_load_fw_prepare(struct venus_core *core, const char *fwname, + phys_addr_t *mem_phys, size_t *res_size, + const struct firmware **mdt) { - const struct firmware *mdt; struct resource res; - struct device *dev; ssize_t fw_size; - void *mem_va; int ret; - *mem_phys = 0; - *mem_size = 0; - - dev = core->dev; - ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); + ret = of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res); if (ret) { - dev_err(dev, "failed to lookup reserved memory-region\n"); + dev_err(core->dev, "failed to lookup reserved memory-region\n"); return -EINVAL; } - ret = request_firmware(&mdt, fwname, dev); - if (ret < 0) + *mem_phys = res.start; + *res_size = resource_size(&res); + + ret = request_firmware(mdt, fwname, core->dev); + if (ret < 0) { + dev_err(core->dev, "%s: request_firmware: %d\n", __func__, ret); return ret; + } - fw_size = qcom_mdt_get_size(mdt); + fw_size = qcom_mdt_get_size(*mdt); if (fw_size < 0) { ret = fw_size; - goto err_release_fw; + goto err_release; } - *mem_phys = res.start; - *mem_size = resource_size(&res); - - if (*mem_size < fw_size || fw_size > VENUS_FW_MEM_SIZE) { + if (*res_size < fw_size || fw_size > VENUS_FW_MEM_SIZE) { ret = -EINVAL; - goto err_release_fw; - } - - mem_va = memremap(*mem_phys, *mem_size, MEMREMAP_WC); - if (!mem_va) { - dev_err(dev, "unable to map memory region %pa size %#zx\n", mem_phys, *mem_size); - ret = -ENOMEM; - goto err_release_fw; + goto err_release; } - if (core->use_tz) - ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID, - mem_va, *mem_phys, *mem_size, NULL); - else - ret = qcom_mdt_load_no_init(dev, mdt, fwname, mem_va, - *mem_phys, *mem_size, NULL); + return 0; - memunmap(mem_va); -err_release_fw: - release_firmware(mdt); +err_release: + release_firmware(*mdt); return ret; } -static int venus_boot_no_tz(struct venus_core *core, phys_addr_t mem_phys, - size_t mem_size) +static int venus_load_fw(struct venus_core *core, + const struct firmware *mdt, const char *fwname, + phys_addr_t mem_phys, size_t res_size) { - struct iommu_domain *iommu; + struct qcom_scm_pas_context *ctx; struct device *dev; int ret; - dev = core->fw.dev; - if (!dev) - return -EPROBE_DEFER; + dev = core->fw.dev ? core->fw.dev : core->dev; + ctx = devm_qcom_scm_pas_context_alloc(dev, VENUS_PAS_ID, mem_phys, res_size); + if (!ctx) { + dev_err(core->dev, "%s: ctx is null\n", __func__); + return -ENOMEM; + } - iommu = core->fw.iommu_domain; - core->fw.mapped_mem_size = mem_size; + ctx->use_tzmem = !!core->fw.dev; - ret = iommu_map(iommu, VENUS_FW_START_ADDR, mem_phys, mem_size, - IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + ret = qcom_mdt_pas_load(ctx, mdt, fwname, NULL); + qcom_scm_pas_metadata_release(ctx); if (ret) { - dev_err(dev, "could not map video firmware region\n"); + dev_err(core->dev, "%s: qcom_mdt_pas_load: %d\n", __func__, ret); return ret; } - venus_reset_cpu(core); + if (core->fw.iommu_domain) { + ret = iommu_map(core->fw.iommu_domain, 0, mem_phys, res_size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + if (ret) { + dev_err(core->dev, "%s: iommu_map: %d\n", __func__, ret); + return ret; + } + } + + core->fw.mapped_mem_size = res_size; + + ret = qcom_scm_pas_prepare_and_auth_reset(ctx); + if (ret) { + dev_err(core->dev, "%s: qcom_scm_pas_prepare_and_auth_reset: %d\n", __func__, ret); + if (core->fw.iommu_domain) + iommu_unmap(core->fw.iommu_domain, 0, res_size); + core->fw.mapped_mem_size = 0; + return ret; + } + core->fw.ctx = ctx; + return 0; +} + +static int venus_load_fw_no_tz(struct venus_core *core, + const struct firmware *mdt, const char *fwname, + phys_addr_t mem_phys, size_t res_size) +{ + void *mem_va; + int ret; + + mem_va = memremap(mem_phys, res_size, MEMREMAP_WC); + if (!mem_va) { + dev_err(core->dev, + "unable to map memory region %pa size %#zx\n", &mem_phys, res_size); + return -ENOMEM; + } + + ret = qcom_mdt_load_no_init(core->fw.dev, mdt, fwname, mem_va, mem_phys, res_size, NULL); + memunmap(mem_va); + if (ret) { + dev_err(core->dev, "%s: qcom_mdt_load_no_init: %d\n", __func__, ret); + return ret; + } + + ret = iommu_map(core->fw.iommu_domain, VENUS_FW_START_ADDR, mem_phys, + res_size, IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + if (ret) { + dev_err(core->dev, "could not map video firmware region\n"); + return ret; + } + + core->fw.mapped_mem_size = res_size; + venus_reset_cpu(core); return 0; } @@ -212,36 +251,35 @@ int venus_boot(struct venus_core *core) { struct device *dev = core->dev; const struct venus_resources *res = core->res; + const struct firmware *mdt; const char *fwpath = NULL; phys_addr_t mem_phys; - size_t mem_size; + size_t res_size; int ret; if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) || - (core->use_tz && !qcom_scm_is_available())) - return -EPROBE_DEFER; + (!core->use_tz && !core->fw.dev)) + return driver_deferred_probe_check_state(core->dev); - ret = of_property_read_string_index(dev->of_node, "firmware-name", 0, - &fwpath); + ret = of_property_read_string_index(dev->of_node, "firmware-name", 0, &fwpath); if (ret) fwpath = core->res->fwname; - ret = venus_load_fw(core, fwpath, &mem_phys, &mem_size); - if (ret) { - dev_err(dev, "fail to load video firmware\n"); - return -EINVAL; - } - - core->fw.mem_size = mem_size; - core->fw.mem_phys = mem_phys; + ret = venus_load_fw_prepare(core, fwpath, &mem_phys, &res_size, &mdt); + if (ret) + return ret; if (core->use_tz) - ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID); + ret = venus_load_fw(core, mdt, fwpath, mem_phys, res_size); else - ret = venus_boot_no_tz(core, mem_phys, mem_size); + ret = venus_load_fw_no_tz(core, mdt, fwpath, mem_phys, res_size); - if (ret) + release_firmware(mdt); + + if (ret) { + dev_err(dev, "fail to load video firmware\n"); return ret; + } if (core->use_tz && res->cp_size) { /* @@ -259,24 +297,29 @@ int venus_boot(struct venus_core *core) res->cp_nonpixel_start, res->cp_nonpixel_size); if (ret) { - qcom_scm_pas_shutdown(VENUS_PAS_ID); - dev_err(dev, "set virtual address ranges fail (%d)\n", - ret); + venus_shutdown(core); + dev_err(dev, "set virtual address ranges fail (%d)\n", ret); return ret; } } - return 0; + return ret; } int venus_shutdown(struct venus_core *core) { int ret; - if (core->use_tz) + if (core->use_tz) { ret = qcom_scm_pas_shutdown(VENUS_PAS_ID); - else + if (core->fw.iommu_domain && core->fw.mapped_mem_size) { + iommu_unmap(core->fw.iommu_domain, 0, core->fw.mapped_mem_size); + core->fw.mapped_mem_size = 0; + } + core->fw.ctx = NULL; + } else { ret = venus_shutdown_no_tz(core); + } return ret; } @@ -301,6 +344,94 @@ int venus_firmware_check(struct venus_core *core) return -EINVAL; } +static struct device *venus_firmware_alloc_platform_dev(struct venus_core *core, + const char *name, const u32 *f_id) +{ + struct platform_device *pdev; + int ret; + + pdev = platform_device_alloc(name, 0); + if (!pdev) { + dev_err(core->dev, "%s: platform_device_alloc err\n", __func__); + return ERR_PTR(-ENOMEM); + } + + pdev->dev.parent = core->dev; + + ret = platform_device_add(pdev); + if (ret) { + dev_err(core->dev, "%s: platform_device_add err(%d)\n", __func__, ret); + platform_device_put(pdev); + return ERR_PTR(ret); + } + + ret = of_dma_configure_id(&pdev->dev, core->dev->of_node, true, f_id); + if (ret) { + dev_err(core->dev, "%s: of_dma_configure_id err(%d)\n", __func__, ret); + platform_device_unregister(to_platform_device(&pdev->dev)); + return ERR_PTR(ret); + } + + return &pdev->dev; +} + +static int venus_firmware_setup_iommu_dev(struct venus_core *core) +{ + const u32 f_id = VENUS_FIRMWARE; + struct device *dev; + int ret = 0; + + dev = venus_firmware_alloc_platform_dev(core, "video_firmware", &f_id); + if (IS_ERR(dev)) { + dev_err(core->dev, "%s: err\n", __func__); + return PTR_ERR(dev); + } + + if (!device_iommu_mapped(dev)) { + device_unregister(dev); + return -ENODEV; + } + + ret = dma_set_mask_and_coherent(dev, core->res->dma_mask); + if (ret) { + device_unregister(dev); + return ret; + } + + core->fw.dev = dev; + core->fw.iommu_domain = iommu_get_domain_for_dev(core->fw.dev); + core->fw.iommu_domain_owned = false; + + return 0; +} + +static int venus_firmware_init_auto_detect(struct venus_core *core) +{ + int ret; + + core->use_tz = false; + if (qcom_scm_is_available()) { + if (qcom_scm_pas_supported(VENUS_PAS_ID)) + core->use_tz = true; + } else { + ret = driver_deferred_probe_check_state(core->dev); + if (ret == -EPROBE_DEFER) + return ret; + } + + /* + * 1. use_tz is false: No authentication is performed. + * 2. use_tz is true: TZ perform authentication. + * a. device_iommu_mapped true: Linux config smmu + * b. device_iommu_mapped false: TZ config smmu + */ + ret = venus_firmware_setup_iommu_dev(core); + if (ret == -ENODEV && core->use_tz) + ret = 0; + + return ret; +} + int venus_firmware_init(struct venus_core *core) { struct platform_device_info info; @@ -311,8 +442,8 @@ int venus_firmware_init(struct venus_core *core) np = of_get_child_by_name(core->dev->of_node, "video-firmware"); if (!np) { - core->use_tz = true; - return 0; + ret = venus_firmware_init_auto_detect(core); + return ret; } memset(&info, 0, sizeof(info)); @@ -351,6 +482,7 @@ int venus_firmware_init(struct venus_core *core) } core->fw.iommu_domain = iommu_dom; + core->fw.iommu_domain_owned = true; of_node_put(np); @@ -359,6 +491,7 @@ int venus_firmware_init(struct venus_core *core) err_iommu_free: iommu_domain_free(iommu_dom); err_unregister: + core->fw.dev = NULL; platform_device_unregister(pdev); of_node_put(np); return ret; @@ -371,14 +504,17 @@ void venus_firmware_deinit(struct venus_core *core) if (!core->fw.dev) return; - iommu = core->fw.iommu_domain; - - iommu_detach_device(iommu, core->fw.dev); + if (!core->use_tz && core->fw.iommu_domain_owned) { + iommu = core->fw.iommu_domain; - if (core->fw.iommu_domain) { - iommu_domain_free(iommu); - core->fw.iommu_domain = NULL; + if (iommu) { + iommu_detach_device(iommu, core->fw.dev); + iommu_domain_free(iommu); + } } - platform_device_unregister(to_platform_device(core->fw.dev)); + core->fw.dev = NULL; + core->fw.ctx = NULL; + core->fw.iommu_domain = NULL; + core->fw.iommu_domain_owned = false; } From e55d4104b9bf54cc0874a4b99336912ab6276191 Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Thu, 30 Apr 2026 16:02:01 +0530 Subject: [PATCH 0928/1330] PENDING: arm64: dts: qcom: talos: enable video codec on Talos Enable video codec on Talos in the EL2 configuration and describe the firmware IOMMU mapping using the iommu-map property. Signed-off-by: Renjiang Han (cherry picked from commit 9e2f111b1297b44c140e3b9c46a2507a3e162741) --- arch/arm64/boot/dts/qcom/talos-el2.dtso | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos-el2.dtso b/arch/arm64/boot/dts/qcom/talos-el2.dtso index f6818c058d724..08b5c9a537fb6 100644 --- a/arch/arm64/boot/dts/qcom/talos-el2.dtso +++ b/arch/arm64/boot/dts/qcom/talos-el2.dtso @@ -5,6 +5,8 @@ * Talos specific modifications required to boot in EL2. */ +#include + /dts-v1/; /plugin/; @@ -21,5 +23,6 @@ }; &venus { - status = "disabled"; + iommu-map = ; + status = "okay"; }; From a610d4d1b1a7118d550d0a7cf5c384f7c3e56f31 Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Fri, 8 May 2026 02:51:03 -0700 Subject: [PATCH 0929/1330] FROMLIST: media: dt-bindings: Add CAMSS device for SM8750 Add bindings for Camera Subsystem (CAMSS) on the Qualcomm SM8750 platform. The SM8750 platform provides: - 6 x CSIPHY (CSI Physical Layer) - 3 x TPG (Test Pattern Generator) - 3 x CSID (CSI Decoder) - 2 x CSID Lite - 3 x VFE (Video Front End), 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260508-add-support-for-camss-on-sm8750-v3-1-fc6861a65c67@oss.qualcomm.com/ (cherry picked from commit 5c809096d7f2b980895982845afc1c3d43087ddf) --- .../bindings/media/qcom,sm8750-camss.yaml | 433 ++++++++++++++++++ 1 file changed, 433 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml new file mode 100644 index 0000000000000..fc0550899c074 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml @@ -0,0 +1,433 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8750-camss + + reg: + maxItems: 19 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 35 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: cpas_vfe_lite + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + + interrupts: + maxItems: 16 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 1 + + power-domains: + items: + - description: + IFE0 GDSC - Global Distributed Switch Controller for IFE0. + - description: + IFE1 GDSC - Global Distributed Switch Controller for IFE1. + - description: + IFE2 GDSC - Global Distributed Switch Controller for IFE2. + - description: + Titan GDSC - Global Distributed Switch Controller for the entire camss. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + vdd-csiphy0-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY0 core block. + + vdd-csiphy0-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 pll block. + + vdd-csiphy1-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY1 core block. + + vdd-csiphy1-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY1 pll block. + + vdd-csiphy2-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY2 core block. + + vdd-csiphy2-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 pll block. + + vdd-csiphy3-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY3 core block. + + vdd-csiphy3-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 pll block. + + vdd-csiphy4-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY4 core block. + + vdd-csiphy4-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY4 pll block. + + vdd-csiphy5-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY5 core block. + + vdd-csiphy5-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY5 pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input ports for receiving CSI data on CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@ad27000 { + compatible = "qcom,sm8750-camss"; + + reg = <0x0 0x0ad27000 0x0 0x2b00>, + <0x0 0x0ad2a000 0x0 0x2b00>, + <0x0 0x0ad2d000 0x0 0x2b00>, + <0x0 0x0ad6d000 0x0 0xa00>, + <0x0 0x0ad72000 0x0 0xa00>, + <0x0 0x0ada9000 0x0 0x2000>, + <0x0 0x0adab000 0x0 0x2000>, + <0x0 0x0adad000 0x0 0x2000>, + <0x0 0x0adaf000 0x0 0x2000>, + <0x0 0x0adb1000 0x0 0x2000>, + <0x0 0x0adb3000 0x0 0x2000>, + <0x0 0x0ad8b000 0x0 0x400>, + <0x0 0x0ad8c000 0x0 0x400>, + <0x0 0x0ad8d000 0x0 0x400>, + <0x0 0x0ac86000 0x0 0x10000>, + <0x0 0x0ac96000 0x0 0x10000>, + <0x0 0x0aca6000 0x0 0x10000>, + <0x0 0x0ad6e000 0x0 0x3000>, + <0x0 0x0ad73000 0x0 0x3000>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x1c00 0x00>; + + power-domains = <&camcc CAM_CC_TFE_0_GDSC>, + <&camcc CAM_CC_TFE_1_GDSC>, + <&camcc CAM_CC_TFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top"; + + vdd-csiphy0-0p9-supply = <&vreg_0p9_supply>; + vdd-csiphy0-1p2-supply = <&vreg_1p2_supply>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy_ep0: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; From 8690d02bf534ab755f14be323b93eca5f70b1741 Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Tue, 12 May 2026 21:49:27 -0700 Subject: [PATCH 0930/1330] FROMLIST: media: qcom: camss: Add SM8750 compatible camss driver Add SM8750 platform support to the CAMSS driver with ICC bandwidth resources and device tree match entry. Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260508-add-support-for-camss-on-sm8750-v3-2-fc6861a65c67@oss.qualcomm.com/ (cherry picked from commit 7e6df2deab4545fe87e78e469e1b7beb08c4ef37) --- drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 4df05fb2d685b..86f1f1b8fcd29 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4297,6 +4297,20 @@ static const struct resources_icc icc_res_sa8775p[] = { }, }; +static const struct resources_icc icc_res_sm8750[] = { + { + .name = "ahb", + .icc_bw_tbl.avg = 150000, + .icc_bw_tbl.peak = 300000, + }, + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */ + { + .name = "hf_mnoc", + .icc_bw_tbl.avg = 471860, + .icc_bw_tbl.peak = 925857, + }, +}; + static const struct camss_subdev_resources csiphy_res_x1e80100[] = { /* CSIPHY0 */ { @@ -5949,6 +5963,13 @@ static const struct camss_resources sm8650_resources = { .vfe_num = ARRAY_SIZE(vfe_res_sm8650), }; +static const struct camss_resources sm8750_resources = { + .version = CAMSS_8750, + .pd_name = "top", + .icc_res = icc_res_sm8750, + .icc_path_num = ARRAY_SIZE(icc_res_sm8750), +}; + static const struct camss_resources x1e80100_resources = { .version = CAMSS_X1E80100, .pd_name = "top", @@ -5999,6 +6020,7 @@ static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources }, { .compatible = "qcom,sm8650-camss", .data = &sm8650_resources }, + { .compatible = "qcom,sm8750-camss", .data = &sm8750_resources }, { .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources }, { .compatible = "qcom,x1p42100-camss", .data = &x1p42100_resources }, { } diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index ff318b334eec8..381dcd816d841 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -94,6 +94,7 @@ enum camss_version { CAMSS_845, CAMSS_8550, CAMSS_8650, + CAMSS_8750, CAMSS_8775P, CAMSS_KAANAPALI, CAMSS_X1E80100, From d35334605ebdc4914115d0a2adfc30dcd64a091b Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Fri, 8 May 2026 02:51:05 -0700 Subject: [PATCH 0931/1330] FROMLIST: media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY Add more detailed resource information for CSIPHY devices in the camss driver along with the support for v2.3.0 in the 2 phase CSIPHY driver that is responsible for the PHY lane register configuration, module reset and interrupt handling. Additionally, generalize the struct name for the lane configuration that had been added for Kaanapali and use it for SM8750 as well as they share the settings. Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260508-add-support-for-camss-on-sm8750-v3-3-fc6861a65c67@oss.qualcomm.com/ (cherry picked from commit 3a8ba0a4439bda4d4d3c2ee419a66a8f7c66d5a2) --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 +- drivers/media/platform/qcom/camss/camss.c | 125 ++++++++++++++++++ 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index ed1f6b6f2f953..8132f8da7849b 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -684,7 +684,7 @@ csiphy_lane_regs lane_regs_sm8650[] = { {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, }; -/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */ +/* 3nm 2PH v 2.3.0/2.4.0 2p5Gbps 4 lane DPHY mode */ static const struct csiphy_lane_regs lane_regs_2_4_0[] = { /* LN 0 */ @@ -1135,6 +1135,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_845: case CAMSS_8550: case CAMSS_8650: + case CAMSS_8750: case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: @@ -1254,7 +1255,9 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs = &lane_regs_sa8775p[0]; regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); break; + case CAMSS_8750: case CAMSS_KAANAPALI: + /* CSPHY v2.4.0 is backward compatible with v2.3.0 settings */ regs->lane_regs = &lane_regs_2_4_0[0]; regs->lane_array_size = ARRAY_SIZE(lane_regs_2_4_0); regs->offset = 0x1000; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 86f1f1b8fcd29..2cf7cad198a1d 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4297,6 +4297,129 @@ static const struct resources_icc icc_res_sa8775p[] = { }, }; +static const struct camss_subdev_resources csiphy_res_8750[] = { + /* CSIPHY0 */ + { + .regulators = { + { .supply = "vdd-csiphy0-0p9", .init_load_uA = 148000 }, + { .supply = "vdd-csiphy0-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy0", "csiphy0_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .csiphy = { + .id = 0, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators = { + { .supply = "vdd-csiphy1-0p9", .init_load_uA = 148000 }, + { .supply = "vdd-csiphy1-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy1", "csiphy1_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .csiphy = { + .id = 1, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators = { + { .supply = "vdd-csiphy2-0p9", .init_load_uA = 148000 }, + { .supply = "vdd-csiphy2-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy2", "csiphy2_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .csiphy = { + .id = 2, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators = { + { .supply = "vdd-csiphy3-0p9", .init_load_uA = 148000 }, + { .supply = "vdd-csiphy3-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy3", "csiphy3_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" }, + .csiphy = { + .id = 3, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY4 */ + { + .regulators = { + { .supply = "vdd-csiphy4-0p9", .init_load_uA = 148000 }, + { .supply = "vdd-csiphy4-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy4", "csiphy4_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy4" }, + .interrupt = { "csiphy4" }, + .csiphy = { + .id = 4, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY5 */ + { + .regulators = { + { .supply = "vdd-csiphy5-0p9", .init_load_uA = 148000 }, + { .supply = "vdd-csiphy5-1p2", .init_load_uA = 14660 } + }, + .clock = { "csiphy5", "csiphy5_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg = { "csiphy5" }, + .interrupt = { "csiphy5" }, + .csiphy = { + .id = 5, + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, +}; + static const struct resources_icc icc_res_sm8750[] = { { .name = "ahb", @@ -5966,7 +6089,9 @@ static const struct camss_resources sm8650_resources = { static const struct camss_resources sm8750_resources = { .version = CAMSS_8750, .pd_name = "top", + .csiphy_res = csiphy_res_8750, .icc_res = icc_res_sm8750, + .csiphy_num = ARRAY_SIZE(csiphy_res_8750), .icc_path_num = ARRAY_SIZE(icc_res_sm8750), }; From 8889659b5273336b966a1b133d0e62c039c0ab8b Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Fri, 8 May 2026 02:51:06 -0700 Subject: [PATCH 0932/1330] FROMLIST: media: qcom: camss: csid: Add support for CSID 980 Add more detailed resource information for CSID devices along with the driver for CSID 980 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. In SM8750, RUP and AUP updates for the CSID Full modules are split into two registers along with a SET register. However, CSID Lite modules still use a single register to update RUP and AUP without the additional SET register. Handled such differences in the driver. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260508-add-support-for-camss-on-sm8750-v3-4-fc6861a65c67@oss.qualcomm.com/ (cherry picked from commit b74bc189948b7766532195995921b4829f737c51) --- drivers/media/platform/qcom/camss/Makefile | 1 + .../platform/qcom/camss/camss-csid-980.c | 442 ++++++++++++++++++ .../media/platform/qcom/camss/camss-csid.h | 1 + drivers/media/platform/qcom/camss/camss.c | 75 +++ 4 files changed, 519 insertions(+) create mode 100644 drivers/media/platform/qcom/camss/camss-csid-980.c diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index b114ca37e36e2..c19d3183882a9 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -8,6 +8,7 @@ qcom-camss-objs += \ camss-csid-4-7.o \ camss-csid-340.o \ camss-csid-680.o \ + camss-csid-980.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ camss-csid-gen4.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c new file mode 100644 index 0000000000000..79eb063000b8d --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-980.c @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-980.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0xC +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10 +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x14 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x18 +#define CSID_AUP_CMD 0x1C +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x20 +#define RUP_SET BIT(0) +#define MUP BIT(4) + +#define CSID_LITE_RUP_AUP_CMD 0x18 +#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi)) +#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi)) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C : 0x84) +#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88) +#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 : 0x8C) +#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90) +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C : 0xA4) +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 16) +#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90 : 0xA8) +#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ? 0x94 : 0xAC) +#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98 : 0xB0) + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ? 0x9C : 0xB4) +#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0 : 0xB8) +#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4 : 0xBC) +#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 : 0xC0) + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 : 0x400) +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404) +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4 : 5) + +#define CSID_RDI_CFG0(rdi) \ + ({ \ + __typeof__(rdi) _rdi = (rdi); \ + csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \ + 0xE00 + 0x200 * _rdi; \ + }) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_DT_ID 27 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) \ + ({ \ + __typeof__(rdi) _rdi = (rdi); \ + csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \ + 0xE04 + 0x200 * _rdi; \ + }) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) \ + ({ \ + __typeof__(rdi) _rdi = (rdi); \ + csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \ + 0xE10 + 0x200 * _rdi; \ + }) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \ + (csid_is_lite(csid) ? 0xEC : 0x114 + 0x10 * (rdi)) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \ + (csid_is_lite(csid) ? 0xF4 : 0x11C + 0x10 * (rdi)) +#define INFO_RUP_DONE BIT(23) + +static void __csid_full_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + if (csid_is_lite(csid)) { + /* CSID Lites in v980 follow the legacy way of a combined RUP + * and AUP commands without an explicit SET register. + */ + csid->reg_update |= CSID_LITE_AUP_RDI(port_id); + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD); + } else { + csid->aup_update |= CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + /* CSID Fulls in v980 split AUP and RUP commands, which requires + * additional SET operation to make registers modification take + * effect. + */ + __csid_full_aup_rup_trigger(csid); + } +} + +static void __csid_rup_update(struct csid_device *csid, int port_id) +{ + if (csid_is_lite(csid)) { + /* CSID Lites in v980 follow the legacy way of a combined RUP + * and AUP commands without an explicit SET register. + */ + csid->reg_update |= CSID_LITE_RUP_RDI(port_id); + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD); + } else { + csid->rup_update |= CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + /* CSID Fulls in v980 split AUP and RUP commands, which requires + * additional SET operation to make registers modification take + * effect. + */ + __csid_full_aup_rup_trigger(csid); + } +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + if (csid_is_lite(csid)) { + csid->reg_update &= ~CSID_LITE_RUP_RDI(port_id); + csid->reg_update &= ~CSID_LITE_AUP_RDI(port_id); + } else { + csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id); + } +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val = CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val = readl(csid->base + CSID_CSI2_RX_CFG1); + val |= CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val = 0; + u32 rdi_ctrl_offset = CSID_RDI_CTRL(rdi); + + if (enable) + val = RDI_CTRL_START_CMD; + + writel(val, csid->base + rdi_ctrl_offset); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi) +{ + u32 val; + + /* + * Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc) +{ + u32 val; + u8 lane_cnt = csid->phy.lane_cnt; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port]; + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt = 4; + + /* + * DT_ID is a two bit bitfield that is concatenated with + * the four least significant bits of the five bit VC + * bitfield to generate an internal CID value. + * + * CSID_RDI_CFG0(vc) + * DT_ID : 28:27 + * VC : 26:22 + * DT : 21:16 + * + * CID : VC 3:0 << 2 | DT_ID 1:0 + */ + u8 dt_id = vc & 0x03; + u32 rdi_cfg0_offset = CSID_RDI_CFG0(port); + u32 rdi_cfg1_offset = CSID_RDI_CFG1(port); + u32 rdi_ctrl_offset = CSID_RDI_CTRL(port); + + val = RDI_CFG0_TIMESTAMP_EN; + val |= RDI_CFG0_TIMESTAMP_STB_SEL; + val |= RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |= vc << RDI_CFG0_VC; + val |= format->data_type << RDI_CFG0_DT; + val |= dt_id << RDI_CFG0_DT_ID; + writel(val, csid->base + rdi_cfg0_offset); + + val = RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + rdi_cfg1_offset); + + /* Configure pixel store using dedicated register in 980 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, port); + + val = 0; + writel(val, csid->base + rdi_ctrl_offset); + + val = readl(csid->base + rdi_cfg0_offset); + + if (enable) + val |= RDI_CFG0_EN; + + writel(val, csid->base + rdi_cfg0_offset); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i, k; + + __csid_configure_rx(csid, &csid->phy); + + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { + if (csid->phy.en_vc & BIT(i)) { + __csid_configure_rdi_stream(csid, enable, i, 0); + __csid_configure_rx_vc(csid, 0); + + for (k = 0; k < CAMSS_INIT_BUF_COUNT; k++) { + __csid_aup_update(csid, i); + __csid_rup_update(csid, i); + } + + __csid_ctrl_rdi(csid, enable, i); + } + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid = dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val = readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done = val & INFO_RST_DONE; + + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { + if (csid->phy.en_vc & BIT(i)) { + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val = IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val = 0; + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val = IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val = RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val = SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time = wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_980 = { + .configure_stream = csid_configure_stream, + .configure_testgen_pattern = csid_configure_testgen_pattern, + .hw_version = csid_hw_version, + .isr = csid_isr, + .reset = csid_reset, + .src_pad_code = csid_src_pad_code, + .subdev_init = csid_subdev_init, + .reg_update = csid_subdev_reg_update, +}; + diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index e6590b2bd8be5..dd9c0868e9c73 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -224,6 +224,7 @@ extern const struct csid_hw_ops csid_ops_4_1; extern const struct csid_hw_ops csid_ops_4_7; extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; +extern const struct csid_hw_ops csid_ops_980; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; extern const struct csid_hw_ops csid_ops_gen4; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 2cf7cad198a1d..095216703dc4c 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4420,6 +4420,79 @@ static const struct camss_subdev_resources csiphy_res_8750[] = { }, }; +static const struct camss_subdev_resources csid_res_8750[] = { + /* CSID0 */ + { + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_980, + .formats = &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_980, + .formats = &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_980, + .formats = &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid_lite0" }, + .interrupt = { "csid_lite0" }, + .csid = { + .is_lite = true, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_980, + .formats = &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid_lite1" }, + .interrupt = { "csid_lite1" }, + .csid = { + .is_lite = true, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_980, + .formats = &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_sm8750[] = { { .name = "ahb", @@ -6090,8 +6163,10 @@ static const struct camss_resources sm8750_resources = { .version = CAMSS_8750, .pd_name = "top", .csiphy_res = csiphy_res_8750, + .csid_res = csid_res_8750, .icc_res = icc_res_sm8750, .csiphy_num = ARRAY_SIZE(csiphy_res_8750), + .csid_num = ARRAY_SIZE(csid_res_8750), .icc_path_num = ARRAY_SIZE(icc_res_sm8750), }; From c9a5e5502b6eb851914354a74c9ce566c53133bc Mon Sep 17 00:00:00 2001 From: Hangxiang Ma Date: Fri, 8 May 2026 02:51:07 -0700 Subject: [PATCH 0933/1330] FROMLIST: media: qcom: camss: vfe: Add support for VFE 980 Add support for Video Front End (VFE) that is on the SM8750 SoCs. VFE gen4 has support for VFE 980. This change limits SM8750 VFE output lines to 3 for now as constrained by the CAMSS driver framework. Reviewed-by: Bryan O'Donoghue Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma Link: https://lore.kernel.org/all/20260508-add-support-for-camss-on-sm8750-v3-5-fc6861a65c67@oss.qualcomm.com/ (cherry picked from commit b9a32dcb4b4b887590163fbcf3daab7eca5d6ffe) --- .../platform/qcom/camss/camss-vfe-gen4.c | 10 +- drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 135 ++++++++++++++++++ 3 files changed, 144 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c index d73d70898710a..46d8e61b9bac0 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c @@ -13,8 +13,12 @@ #include "camss.h" #include "camss-vfe.h" -/* VFE-gen4 Bus Register Base Addresses */ -#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000) +#define IS_VFE_980(vfe) ((vfe)->camss->res->version == CAMSS_8750) + +#define BUS_REG_BASE_980 (vfe_is_lite(vfe) ? 0x200 : 0x800) +#define BUS_REG_BASE_1080 (vfe_is_lite(vfe) ? 0x800 : 0x1000) +#define BUS_REG_BASE \ + (IS_VFE_980(vfe) ? BUS_REG_BASE_980 : BUS_REG_BASE_1080) #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) @@ -55,7 +59,7 @@ * DISPLAY_DS2_C 6 * FD_Y 7 * FD_C 8 - * PIXEL_RAW 9 + * RAW_OUT(1080)/IR_OUT(980) 9 * STATS_AEC_BG 10 * STATS_AEC_BHIST 11 * STATS_TINTLESS_BG 12 diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index ad2aa93bd8000..8dd39c7312f7b 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -351,6 +351,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, case CAMSS_845: case CAMSS_8550: case CAMSS_8650: + case CAMSS_8750: case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: @@ -2015,6 +2016,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_845: case CAMSS_8550: case CAMSS_8650: + case CAMSS_8750: case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 095216703dc4c..6a48487181c0f 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4493,6 +4493,139 @@ static const struct camss_subdev_resources csid_res_8750[] = { } }; +static const struct camss_subdev_resources vfe_res_8750[] = { + /* VFE0 - TFE Full */ + { + .clock = { "gcc_axi_hf", "vfe0_fast_ahb", "vfe0", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .reg_update_after_csid_config = true, + .has_pd = true, + .pd_name = "ife0", + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE1 - TFE Full */ + { + .clock = { "gcc_axi_hf", "vfe1_fast_ahb", "vfe1", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .reg_update_after_csid_config = true, + .has_pd = true, + .pd_name = "ife1", + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE2 - TFE Full */ + { + .clock = { "gcc_axi_hf", "vfe2_fast_ahb", "vfe2", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe2" }, + .interrupt = { "vfe2" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .reg_update_after_csid_config = true, + .has_pd = true, + .pd_name = "ife2", + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE_LITE0 */ + { + .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite", + "cpas_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .reg_update_after_csid_config = true, + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE_LITE1 */ + { + .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite", + "cpas_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate = { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .reg_update_after_csid_config = true, + .hw_ops = &vfe_ops_gen4, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + } +}; + static const struct resources_icc icc_res_sm8750[] = { { .name = "ahb", @@ -6164,9 +6297,11 @@ static const struct camss_resources sm8750_resources = { .pd_name = "top", .csiphy_res = csiphy_res_8750, .csid_res = csid_res_8750, + .vfe_res = vfe_res_8750, .icc_res = icc_res_sm8750, .csiphy_num = ARRAY_SIZE(csiphy_res_8750), .csid_num = ARRAY_SIZE(csid_res_8750), + .vfe_num = ARRAY_SIZE(vfe_res_8750), .icc_path_num = ARRAY_SIZE(icc_res_sm8750), }; From 032f2142cb230bdcc31eded2c2a702926b6febbe Mon Sep 17 00:00:00 2001 From: Anandu Krishnan E Date: Thu, 14 May 2026 18:00:08 +0530 Subject: [PATCH 0934/1330] misc: fastrpc: fix NULL dereference on coherent sessions in fastrpc_map_attach() Commit c7d8100749c6 introduced a brace-less if that skips the dma_buf_map_attachment_unlocked() call when sess->coherent is true, leaving 'table' uninitialized. The unconditional IS_ERR(table) check that follows does not catch NULL, so execution continues with a NULL sg_table, causing a level-0 translation fault when the sgl pointer is dereferenced. Remove the guard; the mapping is always needed to obtain DMA addresses consumed by the rest of the function. Signed-off-by: Anandu Krishnan E (cherry picked from commit fb2eca4487592c0ab7774217f1b0e80bd9f08ae4) --- drivers/misc/fastrpc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index d8b61217adbe0..b266fc5a3bb32 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -899,7 +899,6 @@ static int fastrpc_map_attach(struct fastrpc_user *fl, int fd, mutex_unlock(&fl->sctx->mutex); goto attach_err; } - if (!sess->coherent) table = dma_buf_map_attachment_unlocked(map->attach, DMA_BIDIRECTIONAL); if (IS_ERR(table)) { err = PTR_ERR(table); From 1945691228a1ea2079a7a1e13be0d6f9117b69a3 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Thu, 14 May 2026 12:56:26 +0530 Subject: [PATCH 0935/1330] Add qcom-next log files for 20260514 Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud (cherry picked from commit 1a5fa218ff9c5330c01631d2f80c8707c4664a84) --- qcom-next/merge.log | 135 +++++++++++++++++++++++-------------------- qcom-next/topic_SHA1 | 82 +++++++++++++------------- 2 files changed, 112 insertions(+), 105 deletions(-) diff --git a/qcom-next/merge.log b/qcom-next/merge.log index 16473635eb8f1..c6d6e50693e98 100644 --- a/qcom-next/merge.log +++ b/qcom-next/merge.log @@ -1,5 +1,5 @@ Verified existence of local and remote repos: Success -/local/mnt/workspace/automerge/actions-runner/_work/kernel-automation/kernel-automation/kernel-topics /local/mnt/workspace/automerge/actions-runner/_work/kernel-automation/kernel-automation/kernel-topics +/local/mnt/workspace/sgaud/Builds/Github/All_Runners/kernel-automation/actions-runner/_work/kernel-automation/kernel-automation/kernel-topics /local/mnt/workspace/sgaud/Builds/Github/All_Runners/kernel-automation/actions-runner/_work/kernel-automation/kernel-automation/kernel-topics Reuse-Recorded-Resolution: Enabled Downloaded shared rerere cache Local tree is clean @@ -13,6 +13,10 @@ Adding remote baseline https://github.com/qualcomm-linux/kernel.git qcom-next-st Updating baseline Adding remote tech/bsp/clk https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/clk Updating tech/bsp/clk +Adding remote tech/bsp/devfreq https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/devfreq +Updating tech/bsp/devfreq +Adding remote tech/bsp/ec https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/ec +Updating tech/bsp/ec Adding remote tech/bsp/interconnect https://github.com/qualcomm-linux/kernel-topics.git tech/bsp/interconnect Updating tech/bsp/interconnect Adding remote tech/mem/secure-buffer https://github.com/qualcomm-linux/kernel-topics.git tech/mem/secure-buffer @@ -151,9 +155,11 @@ Adding remote early/hwe/shikra/drivers https://github.com/qualcomm-linux/kernel- Updating early/hwe/shikra/drivers Adding remote early/hwe/shikra/dt https://github.com/qualcomm-linux/kernel-topics.git early/hwe/shikra/dt Updating early/hwe/shikra/dt -Done, added 71 new remote(s). +Done, added 73 new remote(s). Updating the remotes ... Updating tech/bsp/clk +Updating tech/bsp/devfreq +Updating tech/bsp/ec Updating tech/bsp/interconnect Updating tech/mem/secure-buffer Updating tech/security/firmware-smc @@ -226,49 +232,52 @@ Updating early/hwe/shikra/dt Done, updated 0 remote(s). Updating baseline ... Fetching baseline -latest tag/id is 7aaa8047eafd0bd628065b15757d9b48c5f9c07d +latest tag/id is 7fd2df204f342fc17d1a0bfcd474b24232fb0f32 Done, updated baseline. -Latest tag is 7aaa8047eafd0bd628065b15757d9b48c5f9c07d -Create a new integration branch based on 7aaa8047eafd0bd628065b15757d9b48c5f9c07d +Latest tag is 7fd2df204f342fc17d1a0bfcd474b24232fb0f32 +Create a new integration branch based on 7fd2df204f342fc17d1a0bfcd474b24232fb0f32 Merging topic branches... ------------------------------------------ ** Merging topic branch: tech/bsp/clk/tech/bsp/clk -Merge successful : tech/bsp/clk : 90af1d3e6dede77b7c2eb4aa2ee56677023aedb3 : 12 +Merge successful : tech/bsp/clk : eea3e9858db5f675261967f5b88b78727049bf98 : 11 +------------------------------------------ + ** Merging topic branch: tech/bsp/devfreq/tech/bsp/devfreq +Merge successful : tech/bsp/devfreq : 6ebf719c35b8661be830d69b2ea595473cced6d0 : 6 +------------------------------------------ + ** Merging topic branch: tech/bsp/ec/tech/bsp/ec +Merge successful : tech/bsp/ec : 069ea63569dca468e6fda270ad396ce580a75325 : 2 ------------------------------------------ ** Merging topic branch: tech/bsp/interconnect/tech/bsp/interconnect -Merge successful : tech/bsp/interconnect : 7d3a72c70998b3a0c25928ab7e61b4231467700d : 5 +Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/mem/secure-buffer/tech/mem/secure-buffer Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/security/firmware-smc/tech/security/firmware-smc -Merge successful : tech/security/firmware-smc : a50984a91bb9d551ee48136ee2db90eca0929979 : 2 +Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/bsp/soc-infra/tech/bsp/soc-infra -Merge successful : tech/bsp/soc-infra : c793ce5e280bffeca61ab6cdf9ef058c3ad92a99 : 5 +Merge successful : tech/bsp/soc-infra : 20c09ce873000ed6ee8e4ad9a3ff596f49f63778 : 3 ------------------------------------------ ** Merging topic branch: tech/debug/soc/tech/debug/soc Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/bsp/pinctrl/tech/bsp/pinctrl -Merge successful : tech/bsp/pinctrl : 28c2b80824ce68f269fd85b0308df499bca9181d : 1 +Merge successful : tech/bsp/pinctrl : 3f1acf892d6623a15a7245d398ae04bb6d1e9f50 : 1 ------------------------------------------ ** Merging topic branch: tech/bsp/remoteproc/tech/bsp/remoteproc -Merge successful : tech/bsp/remoteproc : abb91aeb56bf212aa9f8a0929bc728237e685d56 : 5 +Merge successful : tech/bsp/remoteproc : a7b9b6d8b0ef8713aea096ed6c6c0fa74db2ed25 : 10 ------------------------------------------ ** Merging topic branch: tech/bus/peripherals/tech/bus/peripherals -Merge successful : tech/bus/peripherals : 8c19ed7289a5e75d811af1ab68c79a971b18a554 : 2 +Merge successful : tech/bus/peripherals : 287f0f5c451d23c09c4c15a25cff6c282ab9b13b : 8 ------------------------------------------ ** Merging topic branch: tech/bus/pci/all/tech/bus/pci/all -Merge successful : tech/bus/pci/all : 6a697f861422a7e8a1e0e189455baffdad08a9c1 : 6 +Merge successful : tech/bus/pci/all : 13f302ced37e4e647c50f669e91aeacc66677a55 : 9 ------------------------------------------ ** Merging topic branch: tech/bus/pci/mhi/tech/bus/pci/mhi -Merge successful : tech/bus/pci/mhi : fb9c1632f424ecdcd7fef1205499a1b64d477cdc : 1 +Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/bus/pci/phy/tech/bus/pci/phy -Merge failed, manual merge -No files need merging -[qcom-next 98edf480f0e9] Merge remote-tracking branch tech/bus/pci/phy into qcom-next Merge successful : tech/bus/pci/phy : aaf8ef1234f456bd05343c235d7ad0b921a97220 : 4 ------------------------------------------ ** Merging topic branch: tech/bus/pci/pwrctl/tech/bus/pci/pwrctl @@ -287,7 +296,7 @@ Merge successful : tech/bus/usb/phy : 8c7f91d8f5390117341ccedf03dbca8620e1fede : Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/debug/hwtracing/tech/debug/hwtracing -Merge successful : tech/debug/hwtracing : 87ae82d339bfcb4af6216f36d831240b42fe8d73 : 31 +Merge successful : tech/debug/hwtracing : 25c6a748cd3b64e815a8ee8c741a7adcf3852618 : 30 ------------------------------------------ ** Merging topic branch: tech/debug/rdbg/tech/debug/rdbg Nothing to merge: Already up to date. @@ -299,7 +308,7 @@ Nothing to merge: Already up to date. Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/pmic/misc/tech/pmic/misc -Merge successful : tech/pmic/misc : e6525e383cf7a4fe2a6f0b5713045620ef6a9b91 : 9 +Merge successful : tech/pmic/misc : eee20da4b7d0716a8a3b6994d8eee25631aca37e : 1 ------------------------------------------ ** Merging topic branch: tech/pmic/regulator/tech/pmic/regulator Merge successful : tech/pmic/regulator : 81fc8fbf0f0a02a7b2d855aee574b88bd7d59107 : 6 @@ -311,31 +320,31 @@ Nothing to merge: Already up to date. Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/mem/iommu/tech/mem/iommu -Merge successful : tech/mem/iommu : 43dfdd1471b043f0b8240f9bc79b03f9fe63e598 : 4 +Merge successful : tech/mem/iommu : 1fa98cb308186a3c850369ade7be19f644199f66 : 5 ------------------------------------------ ** Merging topic branch: tech/mm/audio/all/tech/mm/audio/all -Merge successful : tech/mm/audio/all : d38b67b0aa386ae60c62d75dd3a5d2ea06ddeb62 : 14 +Merge successful : tech/mm/audio/all : cab3357f188207843476df34b2a294a9009efa5b : 10 ------------------------------------------ ** Merging topic branch: tech/mm/audio/soundwire/tech/mm/audio/soundwire Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/mm/camss/tech/mm/camss -Merge successful : tech/mm/camss : ef80fadce4f21a59dc47963b82dd837fbaf27566 : 20 +Merge successful : tech/mm/camss : b9a32dcb4b4b887590163fbcf3daab7eca5d6ffe : 31 ------------------------------------------ ** Merging topic branch: tech/mm/drm/tech/mm/drm -Merge successful : tech/mm/drm : b17e72357fffb70eaa2577edada34e30557208ee : 12 +Merge successful : tech/mm/drm : 2fbdd74ad152cbed32ae7fb4d4be2bec77f2f192 : 60 ------------------------------------------ ** Merging topic branch: tech/mm/fastrpc/tech/mm/fastrpc -Merge successful : tech/mm/fastrpc : c29b2a8795e0f64836ca9314837d167013d0699e : 5 +Merge successful : tech/mm/fastrpc : e0ba7183d63d0a96142a2eac288975e0393d172c : 9 ------------------------------------------ ** Merging topic branch: tech/mm/phy/tech/mm/phy -Nothing to merge: Already up to date. +Merge successful : tech/mm/phy : 56ccbf40aba9e63c5917bd041bc51dce8a05a75d : 1 ------------------------------------------ ** Merging topic branch: tech/mm/video/tech/mm/video -Merge successful : tech/mm/video : fa0e48250f91c77370e01fec89db5539ee3401ca : 4 +Merge successful : tech/mm/video : 5ee68afd88991524d9bb3ff979c7928c70b1fa41 : 38 ------------------------------------------ ** Merging topic branch: tech/mm/gpu/tech/mm/gpu -Merge successful : tech/mm/gpu : 9c8e55ded527bf43ab608810515b6c74e251b99f : 2 +Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/mproc/rpmsg/tech/mproc/rpmsg Nothing to merge: Already up to date. @@ -344,22 +353,22 @@ Nothing to merge: Already up to date. Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/net/ath/tech/net/ath -Merge successful : tech/net/ath : f8562ba7c0e1a81bdf56a29fe0caf2fee6c301fe : 2 +Merge successful : tech/net/ath : 3623de023fc23c916a464f2bc9768875d595bbbc : 13 ------------------------------------------ ** Merging topic branch: tech/net/eth/tech/net/eth -Merge successful : tech/net/eth : 49b156fb09e0950aab5d3b4d6f1a92a3a78766d1 : 1 +Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/net/rmnet/tech/net/rmnet Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/net/qrtr/tech/net/qrtr -Merge successful : tech/net/qrtr : 64d75f7e2a793b65d86fd9b35f8d4c40595ba799 : 1 +Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/net/phy/tech/net/phy Merge successful : tech/net/phy : a3602e9cbd3dd4519ddc446ddba1261fe4e156bd : 1 ------------------------------------------ ** Merging topic branch: tech/net/bluetooth/tech/net/bluetooth -Merge successful : tech/net/bluetooth : 229e73eda5f991c40b55c97150f2547433b083f2 : 3 +Merge successful : tech/net/bluetooth : 9cca4937e7633b28cefedc4c976f4ca2a0442cb3 : 2 ------------------------------------------ ** Merging topic branch: tech/pm/opp/tech/pm/opp Nothing to merge: Already up to date. @@ -368,25 +377,25 @@ Nothing to merge: Already up to date. Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/pm/power/tech/pm/power -Merge successful : tech/pm/power : 25fc1b70fb8b9e86cabdb3f633590a5469e72756 : 9 +Merge successful : tech/pm/power : 2d42c35af66ed0db002e2d2d8481719dd05b804b : 9 ------------------------------------------ ** Merging topic branch: tech/pm/thermal/tech/pm/thermal -Merge successful : tech/pm/thermal : d174ed3bbac5d6ab7ba02a96b0356ea6e57935f8 : 6 +Merge successful : tech/pm/thermal : 90f2db5804218785652b5a88f9d12e798edde273 : 5 ------------------------------------------ ** Merging topic branch: tech/security/crypto/tech/security/crypto -Merge successful : tech/security/crypto : a6ce790e0668cc6f98549c390017c5d1be5d983d : 12 +Merge successful : tech/security/crypto : f030676615c0917a3bb04a3d0f4ca63d7561371b : 14 ------------------------------------------ ** Merging topic branch: tech/security/fscrypt/tech/security/fscrypt Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/security/ice/tech/security/ice -Merge successful : tech/security/ice : 5184a0ec45bba44504d3f09f49cb25142f988403 : 15 +Merge successful : tech/security/ice : 1564b829d7522416a7f06506f0c800139c0c1680 : 25 ------------------------------------------ ** Merging topic branch: tech/storage/nvmem/tech/storage/nvmem Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/storage/phy/tech/storage/phy -Nothing to merge: Already up to date. +Merge successful : tech/storage/phy : cf1667fd75c27b29680062ba04eddb466195156b : 1 ------------------------------------------ ** Merging topic branch: tech/storage/all/tech/storage/all Merge successful : tech/storage/all : e254daed78f7b24bf852df097b78455ca142666a : 1 @@ -395,65 +404,65 @@ Merge successful : tech/storage/all : e254daed78f7b24bf852df097b78455ca142666a : Nothing to merge: Already up to date. ------------------------------------------ ** Merging topic branch: tech/all/dt/qcs6490/tech/all/dt/qcs6490 -Merge successful : tech/all/dt/qcs6490 : 5fb16ec0d2e8ab7658e147729274e6ea6f29494b : 16 +Merge successful : tech/all/dt/qcs6490 : 5828ac79f9793009a4c522f6653cd3a005c5e18c : 17 ------------------------------------------ ** Merging topic branch: tech/all/dt/qcs9100/tech/all/dt/qcs9100 -Merge successful : tech/all/dt/qcs9100 : 5586aacbb055f02fa9989c1c3b587ec7e13d3b82 : 19 +Merge successful : tech/all/dt/qcs9100 : 8a00fd72654f81e29c115c4d853a6f63f87ee16b : 17 ------------------------------------------ ** Merging topic branch: tech/all/dt/qcs8300/tech/all/dt/qcs8300 -Merge successful : tech/all/dt/qcs8300 : 37ae3467288572b7c48fe9e4f1761c8669f68639 : 21 +Merge successful : tech/all/dt/qcs8300 : 90ba0063424e047ccea4f3c96e9786bee0ff18f1 : 15 ------------------------------------------ ** Merging topic branch: tech/all/dt/qcs615/tech/all/dt/qcs615 -Merge successful : tech/all/dt/qcs615 : 367314f4728d5949e932dad7ca5dbc27d66844a0 : 27 +Merge successful : tech/all/dt/qcs615 : 9e2f111b1297b44c140e3b9c46a2507a3e162741 : 9 ------------------------------------------ ** Merging topic branch: tech/all/dt/agatti/tech/all/dt/agatti Merge successful : tech/all/dt/agatti : c828f10cd2c53b7ff2cc061e73b239973ee17bc6 : 1 ------------------------------------------ ** Merging topic branch: tech/all/dt/hamoa/tech/all/dt/hamoa -Merge successful : tech/all/dt/hamoa : 49fad942ea2e8cb32ae046842a58fdec0577b714 : 32 +Merge successful : tech/all/dt/hamoa : 670d0021452a91a99d66fcef03c0af876b85469f : 29 ------------------------------------------ ** Merging topic branch: tech/all/dt/glymur/tech/all/dt/glymur -Merge successful : tech/all/dt/glymur : 3aa6f058d95da70702d42a820eba09bbc6b95050 : 23 +Merge successful : tech/all/dt/glymur : 9251e2445a53df7f065cd6b016a67800b66ca2d4 : 28 ------------------------------------------ ** Merging topic branch: tech/all/dt/kaanapali/tech/all/dt/kaanapali -Merge successful : tech/all/dt/kaanapali : 70486f23c076015ff1cee6616beb776b564cf529 : 23 +Merge failed, manual merge +No files need merging +[qcom-next 1581d6e86097] Merge remote-tracking branch tech/all/dt/kaanapali into qcom-next +Merge successful : tech/all/dt/kaanapali : 7436a0814e107c3b27f4ee0369fd130e6f275474 : 9 ------------------------------------------ ** Merging topic branch: tech/all/dt/pakala/tech/all/dt/pakala -Merge successful : tech/all/dt/pakala : 86103bc08e13ed2feea53df030b7410456d0f69b : 6 +Merge successful : tech/all/dt/pakala : 705ac5445b8a756b1cac0a8c4d6b4a621d42b147 : 6 ------------------------------------------ ** Merging topic branch: tech/all/config/tech/all/config -Merge successful : tech/all/config : 9050b95eabc118e790acfe2f77dfece9beef819a : 53 +Merge successful : tech/all/config : ff67f6a055a339d05f0386c7e3bcbfbe3cc472a9 : 61 ------------------------------------------ ** Merging topic branch: tech/overlay/dt/tech/overlay/dt -Merge failed, manual merge -No files need merging -[qcom-next 2003a1c586be] Merge remote-tracking branch tech/overlay/dt into qcom-next -Merge successful : tech/overlay/dt : bbed7cfb3264aadc265375d97a95316c703ecb0f : 24 +Merge successful : tech/overlay/dt : 88293dfec01cf603c4c8e8d59fe2c37460a2672e : 43 ------------------------------------------ ** Merging topic branch: tech/all/workaround/tech/all/workaround Merge failed, manual merge No files need merging -[qcom-next 10f0a2f6dae8] Merge remote-tracking branch tech/all/workaround into qcom-next -Merge successful : tech/all/workaround : c3f9d3b06c59cdca5219c05d5d313fb780541114 : 13 +[qcom-next effa36a44bef] Merge remote-tracking branch tech/all/workaround into qcom-next +Merge successful : tech/all/workaround : d15f5a17f8be4c6116c1a398ab5e6c3a25852ef1 : 15 ------------------------------------------ ** Merging topic branch: tech/mproc/all/tech/mproc/all -Merge successful : tech/mproc/all : eabd91e71290eab8529edcb342f0bccd7d94c08f : 4 +Merge successful : tech/mproc/all : 0aa90b7d45babe6116bcbb3006ae4636256b6e0f : 3 ------------------------------------------ ** Merging topic branch: tech/noup/debug/all/tech/noup/debug/all -Merge successful : tech/noup/debug/all : 342aeb8c5a4125bff7f8431acf4b6f8b73920dd9 : 15 +Merge successful : tech/noup/debug/all : 53e8e4b953a1812f7460d3d0bbec56eb62d091e3 : 24 ------------------------------------------ ** Merging topic branch: tech/hwe/unoq/tech/hwe/unoq -Merge failed, manual merge -No files need merging -[qcom-next b0da29906863] Merge remote-tracking branch tech/hwe/unoq into qcom-next -Merge successful : tech/hwe/unoq : 7d981feccfaaddb1057ff650e656dcac4e76371b : 16 +Merge successful : tech/hwe/unoq : b2ea57bfc5f97af1b5f7b0d750ae315c60921580 : 5 ------------------------------------------ ** Merging topic branch: early/hwe/shikra/drivers/early/hwe/shikra/drivers -Merge successful : early/hwe/shikra/drivers : 347ed4487fd0ee0230e49b8d918481335843ba6c : 25 +Merge failed, manual merge +No files need merging +[qcom-next 6fea5f460f4c] Merge remote-tracking branch early/hwe/shikra/drivers into qcom-next +Merge successful : early/hwe/shikra/drivers : 74e831cd3e38548fb1916c0fb41cc78649de7ad5 : 69 ------------------------------------------ ** Merging topic branch: early/hwe/shikra/dt/early/hwe/shikra/dt -Merge successful : early/hwe/shikra/dt : 6ae20adae0cce5d240772fc24a45d01a4d6b7935 : 15 -Done, merged 49 topic(s). -[main c650a68] New rr-cache entries from ci-merge - 2 files changed, 5759 insertions(+), 8 deletions(-) - create mode 100644 rr-cache/99839c91a45bfcee801607737b8189856f3cb12e/thisimage.1 +Merge successful : early/hwe/shikra/dt : 8f7e16e4d0ed7a8e661c67589c02f9987abf29dc : 53 +Done, merged 47 topic(s). +[main 801b793] New rr-cache entries from ci-merge + 1 file changed, 1305 insertions(+) + create mode 100644 rr-cache/9204ca65db427e68ec14af7c99c55b9e1c35e051/thisimage.2 diff --git a/qcom-next/topic_SHA1 b/qcom-next/topic_SHA1 index 095e6e7adc297..7e0f67a633469 100644 --- a/qcom-next/topic_SHA1 +++ b/qcom-next/topic_SHA1 @@ -1,51 +1,49 @@ Name SHA Commits ------------------------------------------------------------------------------------ -tech/bsp/clk 90af1d3e6dede77b7c2eb4aa2ee56677023aedb3 12 -tech/bsp/interconnect 7d3a72c70998b3a0c25928ab7e61b4231467700d 5 -tech/security/firmware-smc a50984a91bb9d551ee48136ee2db90eca0929979 2 -tech/bsp/soc-infra c793ce5e280bffeca61ab6cdf9ef058c3ad92a99 5 -tech/bsp/pinctrl 28c2b80824ce68f269fd85b0308df499bca9181d 1 -tech/bsp/remoteproc abb91aeb56bf212aa9f8a0929bc728237e685d56 5 -tech/bus/peripherals 8c19ed7289a5e75d811af1ab68c79a971b18a554 2 -tech/bus/pci/all 6a697f861422a7e8a1e0e189455baffdad08a9c1 6 -tech/bus/pci/mhi fb9c1632f424ecdcd7fef1205499a1b64d477cdc 1 +tech/bsp/clk eea3e9858db5f675261967f5b88b78727049bf98 11 +tech/bsp/devfreq 6ebf719c35b8661be830d69b2ea595473cced6d0 6 +tech/bsp/ec 069ea63569dca468e6fda270ad396ce580a75325 2 +tech/bsp/soc-infra 20c09ce873000ed6ee8e4ad9a3ff596f49f63778 3 +tech/bsp/pinctrl 3f1acf892d6623a15a7245d398ae04bb6d1e9f50 1 +tech/bsp/remoteproc a7b9b6d8b0ef8713aea096ed6c6c0fa74db2ed25 10 +tech/bus/peripherals 287f0f5c451d23c09c4c15a25cff6c282ab9b13b 8 +tech/bus/pci/all 13f302ced37e4e647c50f669e91aeacc66677a55 9 tech/bus/pci/phy aaf8ef1234f456bd05343c235d7ad0b921a97220 4 tech/bus/usb/dwc 49ac8e0eb9656bdaa63dfa8431879f8fe6798742 2 tech/bus/usb/phy 8c7f91d8f5390117341ccedf03dbca8620e1fede 35 -tech/debug/hwtracing 87ae82d339bfcb4af6216f36d831240b42fe8d73 31 -tech/pmic/misc e6525e383cf7a4fe2a6f0b5713045620ef6a9b91 9 +tech/debug/hwtracing 25c6a748cd3b64e815a8ee8c741a7adcf3852618 30 +tech/pmic/misc eee20da4b7d0716a8a3b6994d8eee25631aca37e 1 tech/pmic/regulator 81fc8fbf0f0a02a7b2d855aee574b88bd7d59107 6 -tech/mem/iommu 43dfdd1471b043f0b8240f9bc79b03f9fe63e598 4 -tech/mm/audio/all d38b67b0aa386ae60c62d75dd3a5d2ea06ddeb62 14 -tech/mm/camss ef80fadce4f21a59dc47963b82dd837fbaf27566 20 -tech/mm/drm b17e72357fffb70eaa2577edada34e30557208ee 12 -tech/mm/fastrpc c29b2a8795e0f64836ca9314837d167013d0699e 5 -tech/mm/video fa0e48250f91c77370e01fec89db5539ee3401ca 4 -tech/mm/gpu 9c8e55ded527bf43ab608810515b6c74e251b99f 2 -tech/net/ath f8562ba7c0e1a81bdf56a29fe0caf2fee6c301fe 2 -tech/net/eth 49b156fb09e0950aab5d3b4d6f1a92a3a78766d1 1 -tech/net/qrtr 64d75f7e2a793b65d86fd9b35f8d4c40595ba799 1 +tech/mem/iommu 1fa98cb308186a3c850369ade7be19f644199f66 5 +tech/mm/audio/all cab3357f188207843476df34b2a294a9009efa5b 10 +tech/mm/camss b9a32dcb4b4b887590163fbcf3daab7eca5d6ffe 31 +tech/mm/drm 2fbdd74ad152cbed32ae7fb4d4be2bec77f2f192 60 +tech/mm/fastrpc e0ba7183d63d0a96142a2eac288975e0393d172c 9 +tech/mm/phy 56ccbf40aba9e63c5917bd041bc51dce8a05a75d 1 +tech/mm/video 5ee68afd88991524d9bb3ff979c7928c70b1fa41 38 +tech/net/ath 3623de023fc23c916a464f2bc9768875d595bbbc 13 tech/net/phy a3602e9cbd3dd4519ddc446ddba1261fe4e156bd 1 -tech/net/bluetooth 229e73eda5f991c40b55c97150f2547433b083f2 3 -tech/pm/power 25fc1b70fb8b9e86cabdb3f633590a5469e72756 9 -tech/pm/thermal d174ed3bbac5d6ab7ba02a96b0356ea6e57935f8 6 -tech/security/crypto a6ce790e0668cc6f98549c390017c5d1be5d983d 12 -tech/security/ice 5184a0ec45bba44504d3f09f49cb25142f988403 15 +tech/net/bluetooth 9cca4937e7633b28cefedc4c976f4ca2a0442cb3 2 +tech/pm/power 2d42c35af66ed0db002e2d2d8481719dd05b804b 9 +tech/pm/thermal 90f2db5804218785652b5a88f9d12e798edde273 5 +tech/security/crypto f030676615c0917a3bb04a3d0f4ca63d7561371b 14 +tech/security/ice 1564b829d7522416a7f06506f0c800139c0c1680 25 +tech/storage/phy cf1667fd75c27b29680062ba04eddb466195156b 1 tech/storage/all e254daed78f7b24bf852df097b78455ca142666a 1 -tech/all/dt/qcs6490 5fb16ec0d2e8ab7658e147729274e6ea6f29494b 16 -tech/all/dt/qcs9100 5586aacbb055f02fa9989c1c3b587ec7e13d3b82 19 -tech/all/dt/qcs8300 37ae3467288572b7c48fe9e4f1761c8669f68639 21 -tech/all/dt/qcs615 367314f4728d5949e932dad7ca5dbc27d66844a0 27 +tech/all/dt/qcs6490 5828ac79f9793009a4c522f6653cd3a005c5e18c 17 +tech/all/dt/qcs9100 8a00fd72654f81e29c115c4d853a6f63f87ee16b 17 +tech/all/dt/qcs8300 90ba0063424e047ccea4f3c96e9786bee0ff18f1 15 +tech/all/dt/qcs615 9e2f111b1297b44c140e3b9c46a2507a3e162741 9 tech/all/dt/agatti c828f10cd2c53b7ff2cc061e73b239973ee17bc6 1 -tech/all/dt/hamoa 49fad942ea2e8cb32ae046842a58fdec0577b714 32 -tech/all/dt/glymur 3aa6f058d95da70702d42a820eba09bbc6b95050 23 -tech/all/dt/kaanapali 70486f23c076015ff1cee6616beb776b564cf529 23 -tech/all/dt/pakala 86103bc08e13ed2feea53df030b7410456d0f69b 6 -tech/all/config 9050b95eabc118e790acfe2f77dfece9beef819a 53 -tech/overlay/dt bbed7cfb3264aadc265375d97a95316c703ecb0f 24 -tech/all/workaround c3f9d3b06c59cdca5219c05d5d313fb780541114 13 -tech/mproc/all eabd91e71290eab8529edcb342f0bccd7d94c08f 4 -tech/noup/debug/all 342aeb8c5a4125bff7f8431acf4b6f8b73920dd9 15 -tech/hwe/unoq 7d981feccfaaddb1057ff650e656dcac4e76371b 16 -early/hwe/shikra/drivers 347ed4487fd0ee0230e49b8d918481335843ba6c 25 -early/hwe/shikra/dt 6ae20adae0cce5d240772fc24a45d01a4d6b7935 15 +tech/all/dt/hamoa 670d0021452a91a99d66fcef03c0af876b85469f 29 +tech/all/dt/glymur 9251e2445a53df7f065cd6b016a67800b66ca2d4 28 +tech/all/dt/kaanapali 7436a0814e107c3b27f4ee0369fd130e6f275474 9 +tech/all/dt/pakala 705ac5445b8a756b1cac0a8c4d6b4a621d42b147 6 +tech/all/config ff67f6a055a339d05f0386c7e3bcbfbe3cc472a9 61 +tech/overlay/dt 88293dfec01cf603c4c8e8d59fe2c37460a2672e 43 +tech/all/workaround d15f5a17f8be4c6116c1a398ab5e6c3a25852ef1 15 +tech/mproc/all 0aa90b7d45babe6116bcbb3006ae4636256b6e0f 3 +tech/noup/debug/all 53e8e4b953a1812f7460d3d0bbec56eb62d091e3 24 +tech/hwe/unoq b2ea57bfc5f97af1b5f7b0d750ae315c60921580 5 +early/hwe/shikra/drivers 74e831cd3e38548fb1916c0fb41cc78649de7ad5 69 +early/hwe/shikra/dt 8f7e16e4d0ed7a8e661c67589c02f9987abf29dc 53 From 5e3f428062abf7dda8c88250d83ddc6bb541d90b Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 15:03:48 +0200 Subject: [PATCH 0936/1330] update configs after rebase Signed-off-by: Kuba Pawlak --- debian.qcom/config/annotations | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index d4fd3b082ddd5..47046ceda64dd 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -301,6 +301,10 @@ CONFIG_CHARGER_SC2731 policy<{'arm64': '-'}> CONFIG_CIX_MBOX policy<{'arm64': '-'}> CONFIG_CLKSRC_STM32_LP policy<{'arm64': '-'}> CONFIG_CLK_ACTIONS policy<{'arm64': '-'}> +CONFIG_CLK_ELIZA_DISPCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> +CONFIG_CLK_ELIZA_GCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> +CONFIG_CLK_ELIZA_TCSRCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> +CONFIG_CLK_GLYMUR_CAMCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_GPUCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_VIDEOCC policy<{'arm64': 'y'}> @@ -317,6 +321,7 @@ CONFIG_CLK_INTEL_SOCFPGA64 policy<{'arm64': '-'}> CONFIG_CLK_KAANAPALI_TCSRCC policy<{'arm64': 'n'}> CONFIG_CLK_LS1028A_PLLDIG policy<{'arm64': '-'}> CONFIG_CLK_MA35D1 policy<{'arm64': '-'}> +CONFIG_CLK_NORD_GCC policy<{'arm64': 'm'}> CONFIG_CLK_OWL_S500 policy<{'arm64': '-'}> CONFIG_CLK_OWL_S700 policy<{'arm64': '-'}> CONFIG_CLK_OWL_S900 policy<{'arm64': '-'}> @@ -368,7 +373,9 @@ CONFIG_CLK_RK3588 policy<{'arm64': '-'}> CONFIG_CLK_RV1126B policy<{'arm64': '-'}> CONFIG_CLK_RZG2L policy<{'arm64': '-'}> CONFIG_CLK_RZV2H policy<{'arm64': '-'}> +CONFIG_CLK_SHIKRA_DISPCC policy<{'arm64': 'm'}> CONFIG_CLK_SHIKRA_GCC policy<{'arm64': 'y'}> +CONFIG_CLK_SHIKRA_GPUCC policy<{'arm64': 'm'}> CONFIG_CLK_SOPHGO_CV1800 policy<{'arm64': '-'}> CONFIG_CLK_SOPHGO_SG2042_CLKGEN policy<{'arm64': '-'}> CONFIG_CLK_SOPHGO_SG2042_PLL policy<{'arm64': '-'}> @@ -647,6 +654,7 @@ CONFIG_DEBUG_MUTEXES policy<{'arm64': 'n', 'arm64-qco CONFIG_DEBUG_RWSEMS policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_DETECT_HUNG_TASK_BLOCKER policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI policy<{'arm64': '-'}> +CONFIG_DEVFREQ_GOV_REMOTE policy<{'arm64': 'y'}> CONFIG_DEV_DAX policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_DEV_DAX_CXL policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_DEV_DAX_KMEM policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> @@ -723,6 +731,7 @@ CONFIG_DRM_NOUVEAU_SIL164 policy<{'arm64': '-'}> CONFIG_DRM_NOUVEAU_SVM policy<{'arm64': '-'}> CONFIG_DRM_NOVA policy<{'arm64': 'n'}> CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS policy<{'arm64': '-'}> +CONFIG_DRM_PANEL_DLC0697 policy<{'arm64': 'y'}> CONFIG_DRM_PL111 policy<{'arm64': 'n'}> CONFIG_DRM_RADEON policy<{'arm64': 'n'}> CONFIG_DRM_RADEON_USERPTR policy<{'arm64': '-'}> @@ -797,6 +806,8 @@ CONFIG_DWMAC_SUNXI policy<{'arm64': '-'}> CONFIG_DWMAC_TEGRA policy<{'arm64': '-'}> CONFIG_DWMAC_VISCONTI policy<{'arm64': '-'}> CONFIG_DW_APB_ICTL policy<{'arm64': '-'}> +CONFIG_EC_LENOVO_YOGA_SLIM7X policy<{'arm64': '-'}> +CONFIG_EC_QCOM_HAMOA policy<{'arm64': 'y'}> CONFIG_EDAC_ALTERA policy<{'arm64': '-'}> CONFIG_EDAC_ALTERA_ETHERNET policy<{'arm64': '-'}> CONFIG_EDAC_ALTERA_NAND policy<{'arm64': '-'}> @@ -1025,6 +1036,7 @@ CONFIG_INTERCONNECT_QCOM_KAANAPALI policy<{'arm64': 'y'}> CONFIG_INTERCONNECT_QCOM_QCS615 policy<{'arm64': 'y'}> CONFIG_INTERCONNECT_QCOM_QCS8300 policy<{'arm64': 'y'}> CONFIG_INTERCONNECT_QCOM_SDM845 policy<{'arm64': 'y'}> +CONFIG_INTERCONNECT_QCOM_SHIKRA policy<{'arm64': 'm'}> CONFIG_INTERCONNECT_QCOM_SM8450 policy<{'arm64': 'y'}> CONFIG_INTERCONNECT_QCOM_SM8550 policy<{'arm64': 'y'}> CONFIG_INTERCONNECT_QCOM_SM8650 policy<{'arm64': 'y'}> @@ -1765,6 +1777,7 @@ CONFIG_QCOM_QMI_HELPERS policy<{'arm64': 'y'}> CONFIG_QCOM_QPS615_PCIE_SWITCH policy<{'arm64': '-'}> CONFIG_QCOM_RPMPD policy<{'arm64': 'y'}> CONFIG_QCOM_RPROC_MINIDUMP policy<{'arm64': '-'}> +CONFIG_QCOM_SCMI_GENERIC_EXT policy<{'arm64': 'y'}> CONFIG_QCOM_SCM_ADDON policy<{'arm64': '-'}> CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT policy<{'arm64': '-'}> CONFIG_QCOM_SECURE_BUFFER policy<{'arm64': '-'}> @@ -1928,6 +1941,7 @@ CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> CONFIG_RTSN policy<{'arm64': '-'}> +CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11)"'}> CONFIG_RZG2L_ADC policy<{'arm64': '-'}> CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> @@ -1940,6 +1954,7 @@ CONFIG_S32G_WDT policy<{'arm64': '-'}> CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': '-'}> CONFIG_SATA_RCAR policy<{'arm64': '-'}> CONFIG_SC27XX_ADC policy<{'arm64': '-'}> +CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ policy<{'arm64': 'y'}> CONFIG_SCSI_UFS_AMD_VERSAL2 policy<{'arm64': '-'}> CONFIG_SCSI_UFS_HISI policy<{'arm64': '-'}> CONFIG_SCSI_UFS_MEDIATEK policy<{'arm64': '-'}> @@ -2198,6 +2213,7 @@ CONFIG_SND_SOC_TI_UDMA_PCM policy<{'arm64': '-'}> CONFIG_SND_SOC_WM8994 policy<{'arm64': '-'}> CONFIG_SND_SOC_WM9712 policy<{'arm64': '-'}> CONFIG_SND_SOC_WM_HUBS policy<{'arm64': '-'}> +CONFIG_SND_SOC_WSA885X_I2C policy<{'arm64': 'y'}> CONFIG_SND_SUN4I_CODEC policy<{'arm64': '-'}> CONFIG_SND_SUN4I_I2S policy<{'arm64': '-'}> CONFIG_SND_SUN4I_SPDIF policy<{'arm64': '-'}> From 409b3d6a149f69d6dcc2d9134f6f833a684498f3 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 15:22:32 +0200 Subject: [PATCH 0937/1330] arm64: dts: qcom: Add mahua-crd.dts (missed during rebase) mahua-crd.dtb was referenced in arch/arm64/boot/dts/qcom/Makefile (pulled in as context during the monaco-ac-evk Makefile conflict resolution) but the source file mahua-crd.dts was never added to the tree. The commit 'FROMLIST: arm64: dts: qcom: Add Mahua SoC and CRD' (8a19512e25ad in qualcomm-linux) was skipped during cherry-pick because mahua.dtsi was already present via the WORKAROUND commit, but mahua-crd.dts was not brought along. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts new file mode 100644 index 0000000000000..9c8244e892ddd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "mahua.dtsi" +#include "glymur-crd.dtsi" + +/delete-node/ &pmcx0102_d_e0; +/delete-node/ &pmcx0102_d0_thermal; +/delete-node/ &pmh0104_i_e0; +/delete-node/ &pmh0104_i0_thermal; +/delete-node/ &pmh0104_j_e0; +/delete-node/ &pmh0104_j0_thermal; + +/ { + model = "Qualcomm Technologies, Inc. Mahua CRD"; + compatible = "qcom,mahua-crd", "qcom,mahua"; +}; From 8c119445953f88459e0112eb1c4878cf0c24c5f7 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 15:43:28 +0200 Subject: [PATCH 0938/1330] arm64: dts: qcom: Fix DTS build errors from graduated upstream commits Several commits that were in qcom-next-7.0-rc6 graduated into upstream Linux 7.1-rc2 and were therefore excluded from the cherry-pick list (correctly, as they're in upstream). However, our tree is based on Linux 7.0 and is missing these changes. Fix three distinct build errors: 1. mahua-crd.dtb / mahua.dtsi: 'Label or path not found' errors - glymur.dtsi was missing thermal zone labels (thermal_cpu_2_*, thermal_aoss_*, thermal_gpu_*, thermal_nsp*, thermal_camera_*, thermal_ddr_*, thermal_video_*, thermal_gpuss_*), the cpu_map_cluster2 label, and updated CPU compatible strings (qcom,oryon -> qcom,oryon-2-1/2-2). - pmcx0102.dtsi missing pmcx0102_d0_thermal label. - pmh0104-glymur.dtsi missing pmh0104_i0_thermal and pmh0104_j0_thermal labels. All labels are referenced by mahua.dtsi and mahua-crd.dts via /delete-node/ &label syntax. Fix: update glymur.dtsi, pmcx0102.dtsi, pmh0104-glymur.dtsi to qcom-next-7.1-rc2 versions (label additions only, no functional change). 2. monaco-arduino-monza.dtb: 'No rule to make target' error - monaco-arduino-monza.dts and its dependency monaco-monza-som.dtsi were never added to the tree, but the Makefile entry was pulled in during a conflict resolution. Fix: add monaco-arduino-monza.dts and monaco-monza-som.dtsi from qcom-next-7.1-rc2. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/glymur.dtsi | 311 +++++++----- .../boot/dts/qcom/monaco-arduino-monza.dts | 466 ++++++++++++++++++ .../arm64/boot/dts/qcom/monaco-monza-som.dtsi | 323 ++++++++++++ arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +- 5 files changed, 967 insertions(+), 139 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts create mode 100644 arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 560c2d2287b81..f38fe52a97dad 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -39,7 +39,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-2"; reg = <0x0 0x0>; enable-method = "psci"; power-domains = <&cpu_pd0>, <&scmi_perf 0>; @@ -55,7 +55,7 @@ cpu1: cpu@100 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-2"; reg = <0x0 0x100>; enable-method = "psci"; power-domains = <&cpu_pd1>, <&scmi_perf 0>; @@ -65,7 +65,7 @@ cpu2: cpu@200 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-2"; reg = <0x0 0x200>; enable-method = "psci"; power-domains = <&cpu_pd2>, <&scmi_perf 0>; @@ -75,7 +75,7 @@ cpu3: cpu@300 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-2"; reg = <0x0 0x300>; enable-method = "psci"; power-domains = <&cpu_pd3>, <&scmi_perf 0>; @@ -85,7 +85,7 @@ cpu4: cpu@400 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-2"; reg = <0x0 0x400>; enable-method = "psci"; power-domains = <&cpu_pd4>, <&scmi_perf 0>; @@ -95,7 +95,7 @@ cpu5: cpu@500 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-2"; reg = <0x0 0x500>; enable-method = "psci"; power-domains = <&cpu_pd5>, <&scmi_perf 0>; @@ -105,7 +105,7 @@ cpu6: cpu@10000 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x10000>; enable-method = "psci"; power-domains = <&cpu_pd6>, <&scmi_perf 1>; @@ -121,7 +121,7 @@ cpu7: cpu@10100 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x10100>; enable-method = "psci"; power-domains = <&cpu_pd7>, <&scmi_perf 1>; @@ -131,7 +131,7 @@ cpu8: cpu@10200 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x10200>; enable-method = "psci"; power-domains = <&cpu_pd8>, <&scmi_perf 1>; @@ -141,7 +141,7 @@ cpu9: cpu@10300 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x10300>; enable-method = "psci"; power-domains = <&cpu_pd9>, <&scmi_perf 1>; @@ -151,7 +151,7 @@ cpu10: cpu@10400 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x10400>; enable-method = "psci"; power-domains = <&cpu_pd10>, <&scmi_perf 1>; @@ -161,7 +161,7 @@ cpu11: cpu@10500 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x10500>; enable-method = "psci"; power-domains = <&cpu_pd11>, <&scmi_perf 1>; @@ -171,7 +171,7 @@ cpu12: cpu@20000 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x20000>; enable-method = "psci"; power-domains = <&cpu_pd12>, <&scmi_perf 2>; @@ -187,7 +187,7 @@ cpu13: cpu@20100 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x20100>; enable-method = "psci"; power-domains = <&cpu_pd13>, <&scmi_perf 2>; @@ -197,7 +197,7 @@ cpu14: cpu@20200 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x20200>; enable-method = "psci"; power-domains = <&cpu_pd14>, <&scmi_perf 2>; @@ -207,7 +207,7 @@ cpu15: cpu@20300 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x20300>; enable-method = "psci"; power-domains = <&cpu_pd15>, <&scmi_perf 2>; @@ -217,7 +217,7 @@ cpu16: cpu@20400 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x20400>; enable-method = "psci"; power-domains = <&cpu_pd16>, <&scmi_perf 2>; @@ -227,7 +227,7 @@ cpu17: cpu@20500 { device_type = "cpu"; - compatible = "qcom,oryon"; + compatible = "qcom,oryon-2-1"; reg = <0x0 0x20500>; enable-method = "psci"; power-domains = <&cpu_pd17>, <&scmi_perf 2>; @@ -288,7 +288,7 @@ }; }; - cluster2 { + cpu_map_cluster2: cluster2 { core0 { cpu = <&cpu12>; }; @@ -2447,6 +2447,28 @@ status = "disabled"; }; + mdss_dp3_phy: phy@faac00 { + compatible = "qcom,glymur-dp-phy"; + reg = <0x0 0x00faac00 0x0 0x1d0>, + <0x0 0x00faa400 0x0 0x128>, + <0x0 0x00faa800 0x0 0x128>, + <0x0 0x00faa000 0x0 0x358>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + usb_0_hsphy: phy@fd3000 { compatible = "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; @@ -2593,27 +2615,7 @@ }; }; }; - mdss_dp3_phy: phy@faac00 { - compatible = "qcom,glymur-dp-phy"; - reg = <0 0x00faac00 0 0x1d0>, - <0 0x00faa400 0 0x128>, - <0 0x00faa800 0 0x128>, - <0 0x00faa000 0 0x358>; - clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&tcsr TCSR_EDP_CLKREF_EN>; - clock-names = "aux", - "cfg_ahb", - "ref"; - - power-domains = <&rpmhpd RPMHPD_MX>; - - #clock-cells = <1>; - #phy-cells = <0>; - - status = "disabled"; - }; /* cluster0 */ bwmon_cluster0: pmu@100c400 { @@ -2673,6 +2675,10 @@ opp-10 { opp-peak-kBps = <19046400>; }; + + opp-11 { + opp-peak-kBps = <21332000>; + }; }; }; @@ -2701,7 +2707,6 @@ operating-points-v2 = <&cpu_bwmon_opp_table>; }; - cnoc_main: interconnect@1500000 { compatible = "qcom,glymur-cnoc-main"; reg = <0x0 0x01500000 0x0 0x17080>; @@ -4434,7 +4439,7 @@ reg = <3>; iommus = <&apps_smmu 0x1003 0x80>, - <&apps_smmu 0x1043 0x20>; + <&apps_smmu 0x1063 0x20>; dma-coherent; }; @@ -4443,7 +4448,7 @@ reg = <4>; iommus = <&apps_smmu 0x1004 0x80>, - <&apps_smmu 0x1044 0x20>; + <&apps_smmu 0x1064 0x20>; dma-coherent; }; @@ -4452,7 +4457,7 @@ reg = <5>; iommus = <&apps_smmu 0x1005 0x80>, - <&apps_smmu 0x1045 0x20>; + <&apps_smmu 0x1065 0x20>; dma-coherent; }; @@ -4461,7 +4466,7 @@ reg = <6>; iommus = <&apps_smmu 0x1006 0x80>, - <&apps_smmu 0x1046 0x20>; + <&apps_smmu 0x1066 0x20>; dma-coherent; }; @@ -4480,7 +4485,7 @@ reg = <8>; iommus = <&apps_smmu 0x1008 0x80>, - <&apps_smmu 0x1048 0x20>; + <&apps_smmu 0x1068 0x20>; dma-coherent; }; }; @@ -5373,8 +5378,8 @@ mdss_mdp: display-controller@ae01000 { compatible = "qcom,glymur-dpu"; - reg = <0 0x0ae01000 0 0x93000>, - <0 0x0aeb0000 0 0x2008>; + reg = <0x0 0x0ae01000 0x0 0x93000>, + <0x0 0x0aeb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; @@ -5435,6 +5440,11 @@ mdp_opp_table: opp-table { compatible = "operating-points-v2"; + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + opp-205000000 { opp-hz = /bits/ 64 <205000000>; required-opps = <&rpmhpd_opp_low_svs>; @@ -5459,16 +5469,30 @@ opp-hz = /bits/ 64 <600000000>; required-opps = <&rpmhpd_opp_nom_l1>; }; + + opp-660000000 { + opp-hz = /bits/ 64 <660000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-717000000 { + opp-hz = /bits/ 64 <717000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; }; }; mdss_dp0: displayport-controller@af54000 { compatible = "qcom,glymur-dp"; - reg = <0x0 0xaf54000 0x0 0x104>, - <0x0 0xaf54200 0x0 0xc0>, - <0x0 0xaf55000 0x0 0x770>, - <0x0 0xaf56000 0x0 0x9c>, - <0x0 0xaf57000 0x0 0x9c>; + reg = <0x0 0xaf54000 0x0 0x200>, + <0x0 0xaf54200 0x0 0x200>, + <0x0 0xaf55000 0x0 0xc00>, + <0x0 0xaf56000 0x0 0x400>, + <0x0 0xaf57000 0x0 0x400>, + <0x0 0xaf58000 0x0 0x400>, + <0x0 0xaf59000 0x0 0x400>, + <0x0 0xaf5a000 0x0 0x600>, + <0x0 0xaf5b000 0x0 0x600>; interrupts-extended = <&mdss 12>; @@ -5482,7 +5506,8 @@ "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, @@ -5526,11 +5551,6 @@ mdss_dp0_opp_table: opp-table { compatible = "operating-points-v2"; - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - required-opps = <&rpmhpd_opp_low_svs_d1>; - }; - opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_low_svs>; @@ -5538,6 +5558,11 @@ opp-540000000 { opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; @@ -5550,11 +5575,15 @@ mdss_dp1: displayport-controller@af5c000 { compatible = "qcom,glymur-dp"; - reg = <0x0 0xaf5c000 0x0 0x104>, - <0x0 0xaf5c200 0x0 0xc0>, - <0x0 0xaf5d000 0x0 0x770>, - <0x0 0xaf5e000 0x0 0x9c>, - <0x0 0xaf5f000 0x0 0x9c>; + reg = <0x0 0xaf5c000 0x0 0x200>, + <0x0 0xaf5c200 0x0 0x200>, + <0x0 0xaf5d000 0x0 0xc00>, + <0x0 0xaf5e000 0x0 0x400>, + <0x0 0xaf5f000 0x0 0x400>, + <0x0 0xaf60000 0x0 0x400>, + <0x0 0xaf61000 0x0 0x400>, + <0x0 0xaf62000 0x0 0x600>, + <0x0 0xaf63000 0x0 0x600>; interrupts-extended = <&mdss 13>; @@ -5568,7 +5597,8 @@ "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, @@ -5612,11 +5642,15 @@ mdss_dp2: displayport-controller@af64000 { compatible = "qcom,glymur-dp"; - reg = <0x0 0x0af64000 0x0 0x104>, - <0x0 0x0af64200 0x0 0xc0>, - <0x0 0x0af65000 0x0 0x770>, - <0x0 0x0af66000 0x0 0x9c>, - <0x0 0x0af67000 0x0 0x9c>; + reg = <0x0 0x0af64000 0x0 0x200>, + <0x0 0x0af64200 0x0 0x200>, + <0x0 0x0af65000 0x0 0xc00>, + <0x0 0x0af66000 0x0 0x400>, + <0x0 0x0af67000 0x0 0x400>, + <0x0 0x0af68000 0x0 0x400>, + <0x0 0x0af69000 0x0 0x400>, + <0x0 0x0af6a000 0x0 0x600>, + <0x0 0x0af6b000 0x0 0x600>; interrupts-extended = <&mdss 14>; @@ -5630,7 +5664,8 @@ "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, @@ -5673,11 +5708,15 @@ mdss_dp3: displayport-controller@af6c000 { compatible = "qcom,glymur-dp"; - reg = <0 0x0af6c000 0 0x200>, - <0 0x0af6c200 0 0x200>, - <0 0x0af6d000 0 0xc00>, - <0 0x0af6e000 0 0x400>, - <0 0x0af6f000 0 0x400>; + reg = <0x0 0x0af6c000 0x0 0x200>, + <0x0 0x0af6c200 0x0 0x200>, + <0x0 0x0af6d000 0x0 0xc00>, + <0x0 0x0af6e000 0x0 0x400>, + <0x0 0x0af6f000 0x0 0x400>, + <0x0 0x0af70000 0x0 0x400>, + <0x0 0x0af71000 0x0 0x400>, + <0x0 0x0af72000 0x0 0x600>, + <0x0 0x0af73000 0x0 0x600>; interrupts-extended = <&mdss 15>; @@ -8131,7 +8170,7 @@ compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; reg = <0x0 0x32300000 0x0 0x10000>; - iommus = <&apps_smmu 0x2000 0x400>; + iommus = <&apps_smmu 0x2400 0x400>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, @@ -8186,7 +8225,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <1>; - iommus = <&apps_smmu 0x2001 0x440>, + iommus = <&apps_smmu 0x2401 0x440>, <&apps_smmu 0x1961 0x0>, <&apps_smmu 0x19c1 0x0>; dma-coherent; @@ -8196,7 +8235,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <2>; - iommus = <&apps_smmu 0x2002 0x440>, + iommus = <&apps_smmu 0x2402 0x440>, <&apps_smmu 0x1962 0x0>, <&apps_smmu 0x19c2 0x0>; dma-coherent; @@ -8206,7 +8245,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <3>; - iommus = <&apps_smmu 0x2003 0x440>, + iommus = <&apps_smmu 0x2403 0x440>, <&apps_smmu 0x1963 0x0>, <&apps_smmu 0x19c3 0x0>; dma-coherent; @@ -8216,7 +8255,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <4>; - iommus = <&apps_smmu 0x2004 0x440>, + iommus = <&apps_smmu 0x2404 0x440>, <&apps_smmu 0x1964 0x0>, <&apps_smmu 0x19c4 0x0>; dma-coherent; @@ -8226,7 +8265,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <5>; - iommus = <&apps_smmu 0x2005 0x440>, + iommus = <&apps_smmu 0x2405 0x440>, <&apps_smmu 0x1965 0x0>, <&apps_smmu 0x19c5 0x0>; dma-coherent; @@ -8236,7 +8275,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <6>; - iommus = <&apps_smmu 0x2006 0x440>, + iommus = <&apps_smmu 0x2406 0x440>, <&apps_smmu 0x1966 0x0>, <&apps_smmu 0x19c6 0x0>; dma-coherent; @@ -8246,7 +8285,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <7>; - iommus = <&apps_smmu 0x2007 0x440>, + iommus = <&apps_smmu 0x2407 0x440>, <&apps_smmu 0x1967 0x0>, <&apps_smmu 0x19c7 0x0>; dma-coherent; @@ -8256,7 +8295,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <8>; - iommus = <&apps_smmu 0x2008 0x440>, + iommus = <&apps_smmu 0x2408 0x440>, <&apps_smmu 0x1968 0x0>, <&apps_smmu 0x19c8 0x0>; dma-coherent; @@ -8268,7 +8307,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <10>; - iommus = <&apps_smmu 0x200c 0x440>, + iommus = <&apps_smmu 0x240c 0x440>, <&apps_smmu 0x196c 0x0>, <&apps_smmu 0x19cc 0x0>; dma-coherent; @@ -8278,7 +8317,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <11>; - iommus = <&apps_smmu 0x200d 0x440>, + iommus = <&apps_smmu 0x240d 0x440>, <&apps_smmu 0x196d 0x0>, <&apps_smmu 0x19cd 0x0>; dma-coherent; @@ -8288,7 +8327,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <12>; - iommus = <&apps_smmu 0x200e 0x440>, + iommus = <&apps_smmu 0x240e 0x440>, <&apps_smmu 0x196e 0x0>, <&apps_smmu 0x19ce 0x0>; dma-coherent; @@ -8567,7 +8606,7 @@ }; }; - video-0-thermal { + thermal_video_0: video-0-thermal { thermal-sensors = <&tsens1 7>; trips { @@ -8579,7 +8618,7 @@ }; }; - video-1-thermal { + thermal_video_1: video-1-thermal { thermal-sensors = <&tsens1 8>; trips { @@ -8855,7 +8894,7 @@ }; }; - cpu-2-0-0-thermal { + thermal_cpu_2_0_0: cpu-2-0-0-thermal { thermal-sensors = <&tsens4 1>; trips { @@ -8867,7 +8906,7 @@ }; }; - cpu-2-0-1-thermal { + thermal_cpu_2_0_1: cpu-2-0-1-thermal { thermal-sensors = <&tsens4 2>; trips { @@ -8879,7 +8918,7 @@ }; }; - cpu-2-1-0-thermal { + thermal_cpu_2_1_0: cpu-2-1-0-thermal { thermal-sensors = <&tsens4 3>; trips { @@ -8891,7 +8930,7 @@ }; }; - cpu-2-1-1-thermal { + thermal_cpu_2_1_1: cpu-2-1-1-thermal { thermal-sensors = <&tsens4 4>; trips { @@ -8903,7 +8942,7 @@ }; }; - cpu-2-2-0-thermal { + thermal_cpu_2_2_0: cpu-2-2-0-thermal { thermal-sensors = <&tsens4 5>; trips { @@ -8915,7 +8954,7 @@ }; }; - cpu-2-2-1-thermal { + thermal_cpu_2_2_1: cpu-2-2-1-thermal { thermal-sensors = <&tsens4 6>; trips { @@ -8927,7 +8966,7 @@ }; }; - cpu-2-3-0-thermal { + thermal_cpu_2_3_0: cpu-2-3-0-thermal { thermal-sensors = <&tsens4 7>; trips { @@ -8939,7 +8978,7 @@ }; }; - cpu-2-3-1-thermal { + thermal_cpu_2_3_1: cpu-2-3-1-thermal { thermal-sensors = <&tsens4 8>; trips { @@ -8951,7 +8990,7 @@ }; }; - cpu-2-4-0-thermal { + thermal_cpu_2_4_0: cpu-2-4-0-thermal { thermal-sensors = <&tsens4 9>; trips { @@ -8963,7 +9002,7 @@ }; }; - cpu-2-4-1-thermal { + thermal_cpu_2_4_1: cpu-2-4-1-thermal { thermal-sensors = <&tsens4 10>; trips { @@ -8975,7 +9014,7 @@ }; }; - cpu-2-5-0-thermal { + thermal_cpu_2_5_0: cpu-2-5-0-thermal { thermal-sensors = <&tsens4 11>; trips { @@ -8987,7 +9026,7 @@ }; }; - cpu-2-5-1-thermal { + thermal_cpu_2_5_1: cpu-2-5-1-thermal { thermal-sensors = <&tsens4 12>; trips { @@ -9011,7 +9050,7 @@ }; }; - cpullc-2-0-thermal { + thermal_cpullc_2_0: cpullc-2-0-thermal { thermal-sensors = <&tsens5 1>; trips { @@ -9023,7 +9062,7 @@ }; }; - cpuillc-2-1-thermal { + thermal_cpuillc_2_1: cpuillc-2-1-thermal { thermal-sensors = <&tsens5 2>; trips { @@ -9035,7 +9074,7 @@ }; }; - qmx-2-0-thermal { + thermal_qmx_2_0: qmx-2-0-thermal { thermal-sensors = <&tsens5 3>; trips { @@ -9047,7 +9086,7 @@ }; }; - qmx-2-1-thermal { + thermal_qmx_2_1: qmx-2-1-thermal { thermal-sensors = <&tsens5 4>; trips { @@ -9059,7 +9098,7 @@ }; }; - qmx-2-2-thermal { + thermal_qmx_2_2: qmx-2-2-thermal { thermal-sensors = <&tsens5 5>; trips { @@ -9071,7 +9110,7 @@ }; }; - qmx-2-3-thermal { + thermal_qmx_2_3: qmx-2-3-thermal { thermal-sensors = <&tsens5 6>; trips { @@ -9083,7 +9122,7 @@ }; }; - qmx-2-4-thermal { + thermal_qmx_2_4: qmx-2-4-thermal { thermal-sensors = <&tsens5 7>; trips { @@ -9095,7 +9134,7 @@ }; }; - aoss-6-thermal { + thermal_aoss_6: aoss-6-thermal { thermal-sensors = <&tsens6 0>; trips { @@ -9107,7 +9146,7 @@ }; }; - nsphvx-0-thermal { + thermal_nsphvx_0: nsphvx-0-thermal { thermal-sensors = <&tsens6 1>; trips { @@ -9119,7 +9158,7 @@ }; }; - nsphvx-1-thermal { + thermal_nsphvx_1: nsphvx-1-thermal { thermal-sensors = <&tsens6 2>; trips { @@ -9131,7 +9170,7 @@ }; }; - nsphvx-2-thermal { + thermal_nsphvx_2: nsphvx-2-thermal { thermal-sensors = <&tsens6 3>; trips { @@ -9143,7 +9182,7 @@ }; }; - nsphvx-3-thermal { + thermal_nsphvx_3: nsphvx-3-thermal { thermal-sensors = <&tsens6 4>; trips { @@ -9155,7 +9194,7 @@ }; }; - nsphmx-0-thermal { + thermal_nsphmx_0: nsphmx-0-thermal { thermal-sensors = <&tsens6 5>; trips { @@ -9167,7 +9206,7 @@ }; }; - nsphmx-1-thermal { + thermal_nsphmx_1: nsphmx-1-thermal { thermal-sensors = <&tsens6 6>; trips { @@ -9179,7 +9218,7 @@ }; }; - nsphmx-2-thermal { + thermal_nsphmx_2: nsphmx-2-thermal { thermal-sensors = <&tsens6 7>; trips { @@ -9191,7 +9230,7 @@ }; }; - nsphmx-3-thermal { + thermal_nsphmx_3: nsphmx-3-thermal { thermal-sensors = <&tsens6 8>; trips { @@ -9203,7 +9242,7 @@ }; }; - camera-0-thermal { + thermal_camera_0: camera-0-thermal { thermal-sensors = <&tsens6 9>; trips { @@ -9215,7 +9254,7 @@ }; }; - camera-1-thermal { + thermal_camera_1: camera-1-thermal { thermal-sensors = <&tsens6 10>; trips { @@ -9227,7 +9266,7 @@ }; }; - ddr-1-thermal { + thermal_ddr_1: ddr-1-thermal { thermal-sensors = <&tsens6 11>; trips { @@ -9239,7 +9278,7 @@ }; }; - ddr-2-thermal { + thermal_ddr_2: ddr-2-thermal { thermal-sensors = <&tsens6 12>; trips { @@ -9251,7 +9290,7 @@ }; }; - aoss-7-thermal { + thermal_aoss_7: aoss-7-thermal { thermal-sensors = <&tsens7 0>; trips { @@ -9263,7 +9302,7 @@ }; }; - gpu-0-0-thermal { + thermal_gpu_0_0: gpu-0-0-thermal { thermal-sensors = <&tsens7 1>; trips { @@ -9281,7 +9320,7 @@ }; }; - gpu-0-1-thermal { + thermal_gpu_0_1: gpu-0-1-thermal { thermal-sensors = <&tsens7 2>; trips { @@ -9299,7 +9338,7 @@ }; }; - gpu-0-2-thermal { + thermal_gpu_0_2: gpu-0-2-thermal { thermal-sensors = <&tsens7 3>; trips { @@ -9317,7 +9356,7 @@ }; }; - gpu-1-0-thermal { + thermal_gpu_1_0: gpu-1-0-thermal { thermal-sensors = <&tsens7 4>; trips { @@ -9335,7 +9374,7 @@ }; }; - gpu-1-1-thermal { + thermal_gpu_1_1: gpu-1-1-thermal { thermal-sensors = <&tsens7 5>; trips { @@ -9353,7 +9392,7 @@ }; }; - gpu-1-2-thermal { + thermal_gpu_1_2: gpu-1-2-thermal { thermal-sensors = <&tsens7 6>; trips { @@ -9371,7 +9410,7 @@ }; }; - gpu-2-0-thermal { + thermal_gpu_2_0: gpu-2-0-thermal { thermal-sensors = <&tsens7 7>; trips { @@ -9389,7 +9428,7 @@ }; }; - gpu-2-1-thermal { + thermal_gpu_2_1: gpu-2-1-thermal { thermal-sensors = <&tsens7 8>; trips { @@ -9407,7 +9446,7 @@ }; }; - gpu-2-2-thermal { + thermal_gpu_2_2: gpu-2-2-thermal { thermal-sensors = <&tsens7 9>; trips { @@ -9425,7 +9464,7 @@ }; }; - gpu-3-0-thermal { + thermal_gpu_3_0: gpu-3-0-thermal { thermal-sensors = <&tsens7 10>; trips { @@ -9443,7 +9482,7 @@ }; }; - gpu-3-1-thermal { + thermal_gpu_3_1: gpu-3-1-thermal { thermal-sensors = <&tsens7 11>; trips { @@ -9461,7 +9500,7 @@ }; }; - gpu-3-2-thermal { + thermal_gpu_3_2: gpu-3-2-thermal { thermal-sensors = <&tsens7 12>; trips { @@ -9479,7 +9518,7 @@ }; }; - gpuss-0-thermal { + thermal_gpuss_0: gpuss-0-thermal { thermal-sensors = <&tsens7 13>; trips { @@ -9497,7 +9536,7 @@ }; }; - gpuss-1-thermal { + thermal_gpuss_1: gpuss-1-thermal { thermal-sensors = <&tsens7 14>; trips { diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts new file mode 100644 index 0000000000000..ca14f0ea4dae6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" +#include "monaco-monza-som.dtsi" + +/ { + model = "Arduino VENTUNO Q"; + compatible = "arduino,monza", "qcom,qcs8300"; + + aliases { + ethernet0 = ðernet0; + i2c1 = &i2c1; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-home { + label = "Home Key"; + linux,code = ; + gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + sound { + compatible = "qcom,qcs8275-sndcard"; + model = "arduino-monza"; + audio-routing = "IN12", "Headset Mic12", + "Headset Mic12", "MICBIAS", + "IN56", "Headset Mic56", + "Headset Mic56", "MICBIAS", + "MIC1", "MICBIAS", + "Headphone", "HPL", + "Headphone", "HPR", + "Receiver", "RCVL", + "Receiver", "RCVR", + "Speaker", "SPKL", + "Speaker", "SPKR"; + + pinctrl-0 = <&quad_mi2s_active>, <&quad_mclk_active>, <&lpi_i2s4_active>; + pinctrl-names = "default"; + + pri-i2s-playback-dai-link { + link-name = "Analog Playback"; + + codec { + sound-dai = <&max98091>; + }; + + cpu { + sound-dai = <&q6apmbedai 137>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + pri-i2s-capture-dai-link { + link-name = "Analog Capture"; + + codec { + sound-dai = <&max98091>; + }; + + cpu { + sound-dai = <&q6apmbedai 138>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + hdmi-mi2s-playback-dai-link { + link-name = "HDMI Playback"; + + codec { + sound-dai = <&adv7535>; + }; + + cpu { + sound-dai = <&q6apmbedai 145>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vdc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdc_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdc_5v: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <20000>; + }; + + vreg_nvme: regulator-3p3-m2 { + compatible = "regulator-fixed"; + regulator-name = "vreg_m2_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; +}; + +ðernet0 { + phy-mode = "2500base-x"; + phy-handle = <&hsgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&i2c12 { + clock-frequency = <400000>; + + status = "okay"; + + max98091: audio-codec@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + pinctrl-0 = <&max98091_default>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_16 */ + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_3 LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + + adv7535: bridge@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + pinctrl-0 = <&adv7535_default>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 93 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <&vdc_1v8>; + dvdd-supply = <&vdc_1v8>; + pvdd-supply = <&vdc_1v8>; + a2vdd-supply = <&vdc_1v8>; + v3p3-supply = <&vdc_3v3>; + v1p2-supply = <&vdc_1v8>; + adi,dsi-lanes = <4>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp0_phy { + status = "okay"; +}; + +&mdss_dsi0 { + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&adv7535_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vdc_3v3>; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vreg_nvme>; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + + pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x01 0xff>; + ranges; + reg = <0x010000 0x00 0x00 0x00 0x00>; + + pci@2,0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges; + reg = <0x021000 0x00 0x00 0x00 0x00>; + + usb@0 { + compatible = "pci104c,8241"; + reg = <0 0 0 0 0>; + ti,pwron-active-high; + }; + }; + }; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; +}; + +&tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio5"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio6"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + max98091_default: max98091-default-state { + pins = "gpio16"; + function = "gpio"; + bias-pull-up; + }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio79"; + function = "gpio"; + bias-disable; + }; + + adv7535_default: adv7535-default-state { + pins = "gpio93"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +/* Internally connected to the MCU (e.g. for DFU). */ +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi new file mode 100644 index 0000000000000..9b5ed55939b86 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" + +/ { + /* This comes from a PMIC handled within the SAIL domain */ + vreg_s2s: vreg-s2s { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2s"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s5c: smps5 { /* LPDDR VDD2H */ + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { /* LPDDR VDDQ */ + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <512000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { /* LPDDR VDD2L */ + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { /* LPDDR VDD1 */ + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { /* QFPROM */ + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hpd>; + pinctrl-names = "default"; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l5a>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l4a>; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + +&iris { + status = "okay"; +}; + +/* PCIe0 Gen4 x2 */ +&pcie0 { + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>, + <0x200 &pcie_smmu 0x0007 0x1>, + <0x208 &pcie_smmu 0x0002 0x1>, + <0x210 &pcie_smmu 0x0003 0x1>, + <0x218 &pcie_smmu 0x0004 0x1>, + <0x300 &pcie_smmu 0x0005 0x1>, + <0x400 &pcie_smmu 0x0006 0x1>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +/* PCIe1 Gen4 x4 */ +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + status = "okay"; +}; + +/* There is a HW/FW issue preventing proper REFGEN hardware voting + * for the USB2 HS PHY. As a workaround, we force REFGEN to stay + * always‑on in software, matching initial bootloader config. + */ +&refgen { + regulator-always-on; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8300/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8300/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp { + firmware-name = "qcom/qcs8300/gpdsp0.mbn"; + + status = "okay"; +}; + +/* OnSom eMMC */ +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; + + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + no-sd; + no-sdio; + non-removable; + + status = "okay"; +}; + +/* Ethernet/SGMII */ +&serdes0 { + phy-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&tlmm { + dp_hpd: dp-hpd-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; +}; + +/* USB0 HS + SS */ +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +/* USB1 HS */ +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi index c3ccd2b756099..db2da9ef4f019 100644 --- a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -46,7 +46,7 @@ }; }; - pmcx0102-d0-thermal { + pmcx0102_d0_thermal: pmcx0102-d0-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmcx0102_d_e0_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi index d89cceda53a3f..7a1e5f355c175 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -8,7 +8,7 @@ /{ thermal_zones { - pmh0104-i0-thermal { + pmh0104_i0_thermal: pmh0104-i0-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmh0104_i_e0_temp_alarm>; @@ -27,7 +27,7 @@ }; }; - pmh0104-j0-thermal { + pmh0104_j0_thermal: pmh0104-j0-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmh0104_j_e0_temp_alarm>; From 721e8f63369f15a405ae67e1b6a3c0fae035bb74 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 16:12:57 +0200 Subject: [PATCH 0939/1330] arm64: dts: qcom: monaco: Add lpass_tlmm pinctrl node (graduated upstream) monaco-arduino-monza.dts references pinctrl labels quad_mi2s_active, quad_mclk_active, and lpi_i2s4_active which are defined inside the lpass_tlmm node. These were added to monaco.dtsi by a commit that graduated into upstream Linux 7.1-rc2, so they were excluded from the cherry-pick list but are missing from our 7.0-based tree. Also add the required dt-bindings/sound/qcom,q6dsp-lpass-ports.h include for the LPASS_HW_MACRO_VOTE / LPASS_HW_DCODEC_VOTE clock references inside lpass_tlmm. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/monaco.dtsi | 70 ++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 2a2bcce4cb9c3..bc7fe82e236c0 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -21,6 +21,7 @@ #include #include #include +#include #include / { @@ -2900,6 +2901,75 @@ }; }; + lpass_tlmm: pinctrl@3440000 { + compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl"; + reg = <0x0 0x03440000 0x0 0x20000>, + <0x0 0x034d0000 0x0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + quad_mclk_active: quad-mclk-state { + clk-pins { + pins = "gpio5"; + function = "ext_mclk1_c"; + drive-strength = <8>; + bias-disable; + }; + }; + + quad_mi2s_active: quad-active-state { + data-pins { + pins = "gpio2", "gpio3"; + function = "qua_mi2s_data"; + drive-strength = <8>; + bias-disable; + }; + + sclk-pins { + pins = "gpio0"; + function = "qua_mi2s_sclk"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio1"; + function = "qua_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + + lpi_i2s4_active: lpi_i2s4-active-state { + data0-pins { + pins = "gpio17"; + function = "i2s4_data"; + drive-strength = <8>; + bias-disable; + }; + + clk-pins { + pins = "gpio12"; + function = "i2s4_clk"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio13"; + function = "i2s4_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,qcs8300-lpass-ag-noc"; reg = <0x0 0x03c40000 0x0 0x17200>; From 8179847fd2ca10d5dcbf36deab91e4813b1b94f7 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 16:40:15 +0200 Subject: [PATCH 0940/1330] arm64: dts: qcom: hamoa: Restore camss/csiphy1/csiphy2 nodes (bad conflict resolution) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 'Add CCI definitions' cherry-pick (e66b2b80fda5, from qcom-linux 486e11c5046c) removed the camss: isp@acb7000 node and its csiphy1/ csiphy2 children from hamoa.dtsi as a bad conflict resolution. In qcom-linux those nodes are nested inside the camss node; in our ubuntu tree they had been added as standalone nodes by the SAUCE commit (dc744c9ecf88), so the cherry-pick stripped them out entirely. purwa.dtsi (which inherits hamoa.dtsi) references &csiphy1, &csiphy2, and &camss via /delete-node/ and node override syntax, causing DTC build failures: Error: purwa.dtsi: Label or path csiphy1 not found Error: purwa.dtsi: Label or path csiphy2 not found Error: purwa.dtsi: Label or path camss not found Re-add the full camss: isp@acb7000 block (camss, csiphy0–csiphy3, cci0, cci1 and children) from qcom-next-7.1-rc2 tip, inserted before the camcc: clock-controller@ade0000 node. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 346 ++++++++++++++++++++++++++++ 1 file changed, 346 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index cbd06b794c317..c7d558e164447 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5912,6 +5912,352 @@ }; }; + camss: isp@acb7000 { + compatible = "qcom,x1e80100-camss"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0ace6000 0 0x1000>, + <0 0x0ace8000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x820 0x60>, + <&apps_smmu 0x840 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x18a0 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + phys = <&csiphy0 PHY_QCOM_CSI2_MODE_DPHY>, + <&csiphy1 PHY_QCOM_CSI2_MODE_DPHY>, + <&csiphy2 PHY_QCOM_CSI2_MODE_DPHY>, + <&csiphy4 PHY_QCOM_CSI2_MODE_DPHY>; + phy-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4"; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy0_inep0: endpoint@0 { + reg = <0>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy1_inep0: endpoint@0 { + reg = <0>; + }; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy2_inep0: endpoint@0 { + reg = <0>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy4_inep0: endpoint@0 { + reg = <0>; + }; + }; + }; + + csiphy0: phy@ace4000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace4000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + + interrupts = ; + + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "mx", + "mmcx"; + + #phy-cells = <1>; + + status = "disabled"; + }; + + csiphy1: phy@ace6000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace6000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + + interrupts = ; + + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "mx", + "mmcx"; + + #phy-cells = <1>; + + status = "disabled"; + }; + + csiphy2: phy@ace8000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace8000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + + interrupts = ; + + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "mx", + "mmcx"; + + #phy-cells = <1>; + + status = "disabled"; + }; + + csiphy4: phy@acec000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0acec000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + operating-points-v2 = <&csiphy_mxa_opp_table>; + + interrupts = ; + + power-domains = <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "mx", + "mmcx"; + + #phy-cells = <1>; + + status = "disabled"; + }; + + csiphy_mxc_opp_table: opp-table-mxc { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + }; + + csiphy_mxa_opp_table: opp-table-mxa { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,x1e80100-camcc"; reg = <0 0x0ade0000 0 0x20000>; From 048b20027ee326241dbe65ad6e554451350937fe Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 17:11:23 +0200 Subject: [PATCH 0941/1330] dt-bindings/phy + arm64: dts: qcom: hamoa: Add phy-qcom-mipi-csi2.h The camss block in hamoa.dtsi uses PHY_QCOM_CSI2_MODE_DPHY from include/dt-bindings/phy/phy-qcom-mipi-csi2.h, which is a new header introduced by the same graduated-upstream commit that added the camss node. Add the header file and include it in hamoa.dtsi. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 1 + include/dt-bindings/phy/phy-qcom-mipi-csi2.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 include/dt-bindings/phy/phy-qcom-mipi-csi2.h diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index c7d558e164447..92acfe414fcac 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/include/dt-bindings/phy/phy-qcom-mipi-csi2.h b/include/dt-bindings/phy/phy-qcom-mipi-csi2.h new file mode 100644 index 0000000000000..fa48fd75c58d8 --- /dev/null +++ b/include/dt-bindings/phy/phy-qcom-mipi-csi2.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Qualcomm MIPI CSI2 PHY constants + * + * Copyright (C) 2026 Linaro Limited + */ + +#ifndef __DT_BINDINGS_PHY_MIPI_CSI2__ +#define __DT_BINDINGS_PHY_MIPI_CSI2__ + +#define PHY_QCOM_CSI2_MODE_DPHY 0 +#define PHY_QCOM_CSI2_MODE_CPHY 1 +#define PHY_QCOM_CSI2_MODE_SPLIT_DPHY 2 + +#endif /* __DT_BINDINGS_PHY_MIPI_CSI2__ */ From 7c0d0b585b9792005320d897e48082c1a82c43b9 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 17:29:10 +0200 Subject: [PATCH 0942/1330] arm64: dts: qcom: Fix missing DTS/DTSO files and composite DTB definitions Add missing source files: - qcs6490-thundercomm-minipc-g1iot.dts - sc7180-ecs-liva-qc710.dts - sm8550-hdk-display-card.dtso - sm8550-hdk-rear-camera-card.dtso Add missing composite DTB definitions in Makefile: - sm8550-hdk-display-card-dtbs - sm8550-hdk-display-card-rear-camera-card-dtbs Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/qcs6490-thundercomm-minipc-g1iot.dts | 1093 +++++++++++++++++ .../boot/dts/qcom/sc7180-ecs-liva-qc710.dts | 616 ++++++++++ .../dts/qcom/sm8550-hdk-display-card.dtso | 132 ++ 4 files changed, 1843 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8550-hdk-display-card.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7880dbf7a35ef..b1b452d7cbd5f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -393,6 +393,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb sm8550-hdk-rear-camera-card-dtbs := sm8550-hdk.dtb sm8550-hdk-rear-camera-card.dtbo +sm8550-hdk-display-card-dtbs := sm8550-hdk.dtb sm8550-hdk-display-card.dtbo +sm8550-hdk-display-card-rear-camera-card-dtbs := sm8550-hdk.dtb sm8550-hdk-display-card.dtbo sm8550-hdk-rear-camera-card.dtbo dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card-rear-camera-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card.dtbo diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts new file mode 100644 index 0000000000000..a5ad796cb65d0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -0,0 +1,1093 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Roger Shimizu + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include "kodiak.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model = "Thundercomm AI Mini PC G1 IoT"; + compatible = "thundercomm,minipc-g1iot", "qcom,qcm6490"; + chassis-type = "desktop"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_usb_con_ss>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&redriver_usb_con_sbu>; + }; + }; + }; + }; + }; + + lt9611_1v2: regulator-lt9611-vdd12 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@86100000 { + reg = <0x0 0x86100000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@88900000 { + reg = <0x0 0x88900000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@8a700000 { + reg = <0x0 0x8a700000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@8ae00000 { + reg = <0x0 0x8ae00000 0x0 0x500000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@8b31a000 { + reg = <0x0 0x8b31a000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_0P9"; + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + enable-active-high; + pinctrl-0 = <&ntn_0p9_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_1P8"; + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn_1p8_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + thermal-zones { + sdm-skin-thermal { + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; + vdd-l8-supply = <&vreg_s7b_0p972>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; + vdd-l13-supply = <&vreg_s7b_0p972>; + vdd-l14-l16-supply = <&vreg_s8b_1p272>; + + vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p872>; + vdd-l2-l8-supply = <&vreg_s1b_1p872>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p972>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2208000>; + }; + + vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs6490/a660_zap.mbn"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <&vreg_l11c_2p8>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l18b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_usb_con_ss: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_phy_con_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@2 { + reg = <2>; + + redriver_usb_con_sbu: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_clkreq_n>, + <&pcie0_reset_n>, + <&pcie0_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_clkreq_n>, + <&pcie1_reset_n>, + <&pcie1_wake_n>; + pinctrl-names = "default"; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x400 &apps_smmu 0x1c88 0x1>, + <0x500 &apps_smmu 0x1c89 0x1>, + <0x501 &apps_smmu 0x1c90 0x1>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1_port0 { + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + i2c-parent = <&i2c0 0x77>; + + resx-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&pm7250b_gpios { + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio2"; + function = "normal"; + + output-high; + input-disable; + power-source = <0>; + }; +}; + +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8350c_gpios { + ntn_0p9_en: ntn-0p9-en-state { + pins = "gpio2"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + ntn_1p8_en: ntn-1p8-en-state { + pins = "gpio3"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + tc9563_resx_n: tc9563-resx-state { + pins = "gpio1"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; +}; + +&pm8350c_pwm { + nvmem = <&pmk8350_sdam_21>, + <&pmk8350_sdam_22>; + nvmem-names = "lpg_chan_sdam", + "lut_sdam"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + channel@3 { + reg = ; + label = "pmk7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = ; + label = "xo_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg = ; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + + status = "okay"; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; + + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <32 2>, /* ADSP */ + <48 4>; /* NFC */ + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sd_cd: sd-cd-state { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart5 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p912>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_phy_con_ss>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts b/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts new file mode 100644 index 0000000000000..b84da371581b9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include +#include +#include + +#include "sc7180.dtsi" + +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/delete-node/ &tz_mem; +/delete-node/ &ipa_fw_mem; + +/ { + model = "ECS LIVA QC710"; + compatible = "ecs,liva-qc710", "qcom,sc7180"; + chassis-type = "desktop"; + + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart3; + wifi0 = &wifi; + }; + + hdmi-bridge { + compatible = "algoltek,ag6311"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + reserved-memory { + gpu_mem: zap-shader@80840000 { + reg = <0x0 0x80840000 0 0x2000>; + no-map; + }; + + venus_mem: venus@85b00000 { + reg = <0x0 0x85b00000 0 0x500000>; + no-map; + }; + + mpss_mem: mpss@86000000 { + reg = <0x0 0x86000000 0x0 0x2000000>; + no-map; + }; + + adsp_mem: adsp@8e400000 { + reg = <0x0 0x8e400000 0x0 0x2800000>; + no-map; + }; + + wlan_mem: wlan@93900000 { + reg = <0x0 0x93900000 0x0 0x200000>; + no-map; + }; + }; + + usb_a_connector: usb-a-connector { + compatible = "usb-a-connector"; + + port { + usb_a_connector_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_out>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s1a_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_l4a_0p8: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <928000>; + regulator-initial-mode = ; + }; + + vreg_l9a_0p6: ldo9 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p9: ldo19 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1168000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sc7180/ecs/liva-qc710/qcdxkmsuc7180.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; +}; + +&pm6150_rtc { + qcom,uefi-rtc-info; + + status = "okay"; +}; + +&qfprom { + vcc-supply = <&vreg_l11a_1p8>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + memory-region = <&adsp_mem>; + firmware-name = "qcom/sc7180/ecs/liva-qc710/qcadsp7180.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sc7180/ecs/liva-qc710/qcmpss7180_nm.mbn"; + + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l19a_2p9>; + vqmmc-supply = <&vreg_l12a_1p8>; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + /* + * The TZ seem to protect those because some boards can have + * fingerprint sensor connected to this range. Not connected + * on this board + */ + gpio-reserved-ranges = <58 5>; + + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + function = "gpio"; + bias-pull-down; + }; + + rts-pins { + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + pins = "gpio39"; + function = "gpio"; + bias-pull-down; + }; + + tx-pins { + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + pins = "gpio40"; + function = "gpio"; + bias-pull-up; + }; + + rx-pins { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + pins = "gpio41"; + function = "gpio"; + bias-pull-up; + }; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <16>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio69"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd-pins { + pins = "gpio69"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; +}; +&uart3 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart3_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3991-bt"; + vddio-supply = <&vreg_l10a_1p8>; + vddxo-supply = <&vreg_l1c_1p8>; + vddrf-supply = <&vreg_l2c_1p3>; + vddch0-supply = <&vreg_l10c_3p3>; + max-speed = <3200000>; + }; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb5e3,608"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* @1: 3.0 Type-A port on the back + * @2: 2.0 Type-A port the side + * @3: 2.0 Type-C port on the back + */ + + ethernet@4 { + compatible = "usbbda,8152"; + reg = <4>; + }; + }; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l11a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; + qcom,imp-res-offset-value = <8>; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + qcom,bias-ctrl-value = <0x22>; + qcom,charge-ctrl-value = <3>; + qcom,hsdisc-trim-value = <0>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l4a_0p8>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_qmpphy_dp_out: endpoint@0 { + reg = <0>; + + data-lanes = <3 2>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + usb_1_qmpphy_usb_ss_out: endpoint@1 { + reg = <1>; + + data-lanes = <1 0>; + remote-endpoint = <&usb_a_connector_ss_in>; + }; + }; + }; +}; + +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss_dp_out>; +}; + +&venus { + firmware-name = "qcom/sc7180/ecs/liva-qc710/qcvss7180.mbn"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>; + vdd-1.8-xo-supply = <&vreg_l1c_1p8>; + vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; + vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; + + qcom,calibration-variant = "ECS_QC710"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk-display-card.dtso b/arch/arm64/boot/dts/qcom/sm8550-hdk-display-card.dtso new file mode 100644 index 0000000000000..7b54b084b8bd4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk-display-card.dtso @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2026, Linaro Limited + */ + +/* + * Display Card kit overlay + * This requires S5702 Switch 7 to be turned to OFF to route DSI0 to the display panel + */ + +#include +#include + +/dts-v1/; +/plugin/; + +/* Disable HDMI bridge related nodes (mutually exclusive with the display card) */ + +&i2c0 { + status = "disabled"; +}; + +<9611_1v2 { + status = "disabled"; +}; + +<9611_3v3 { + status = "disabled"; +}; + +&vreg_bob_3v3 { + status = "disabled"; +}; + +<9611_codec { + status = "disabled"; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; +}; + +&spi4 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l14b_3p2>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_irq>, <&ts_reset>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync: mdp-vsync-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_irq: ts-irq-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-disable; + }; + + ts_reset: ts-reset-state { + pins = "gpio24"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; From 7107637af33aec404680d7fb30c9922860e1c22d Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 17:38:32 +0200 Subject: [PATCH 0943/1330] arm64: dts: qcom: shikra: Add missing clocks block (xo_board, sleep_clk) Graduated-upstream gap: the clocks{} block with xo_board and sleep_clk fixed-clock nodes was missing from shikra.dtsi, causing DTC errors: 'Reference to non-existent node or label sleep_clk' Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/shikra.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 441d1f510a269..9a27b9ee5c15c 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -22,6 +22,20 @@ #address-cells = <2>; #size-cells = <2>; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; From 18d2d5aa9538ec7a27e30682dafe75e09e218136 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 17:50:20 +0200 Subject: [PATCH 0944/1330] arm64: dts: qcom: Fix duplicate camcc node and missing LED includes sm8750.dtsi: Remove duplicate camcc: clock-controller@ade0000 node introduced by conflicting cherry-picks. x1e78100-lenovo-thinkpad-t14s.dtsi, x1e80100-lenovo-yoga-slim7x.dts: Add missing #include needed for LED_FUNCTION_INDICATOR constant. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 17 ----------------- .../dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 1 + .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 1 + 3 files changed, 2 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 0bb75ee63918d..961342779e33f 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3489,23 +3489,6 @@ #power-domain-cells = <1>; }; - camcc: clock-controller@ade0000 { - compatible = "qcom,sm8750-camcc"; - reg = <0x0 0xade0000 0x0 0x20000>; - clocks = <&gcc GCC_CAMERA_AHB_CLK>, - <&bi_tcxo_div2>, - <&bi_tcxo_ao_div2>, - <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>, - <&rpmhpd RPMHPD_MXC>; - required-opps = <&rpmhpd_opp_low_svs>, - <&rpmhpd_opp_low_svs>; - - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index c6f259b8068f2..deaabba8ff103 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 5a1ab0da86696..5d105c20f54e7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -7,6 +7,7 @@ #include #include +#include #include #include From 6605075fefe64dc7ec56064b44640d63a240a9f2 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 17:53:30 +0200 Subject: [PATCH 0945/1330] arm64: dts: qcom: sm8750-mtp: Resolve leftover cherry-pick conflict Unresolved conflict marker was left in sm8750-mtp.dts from cherry-pick e9ecb2652be8 (arm64: dts: qcom: sm8750-mtp: Enable display). Keep the incoming mdss_dp0 and mdss_dp0_out enable blocks. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index f63e0cd54f2ca..69ebd0138db70 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -941,8 +941,6 @@ status = "okay"; }; -<<<<<<< HEAD -======= &mdss_dp0 { status = "okay"; }; @@ -950,7 +948,6 @@ &mdss_dp0_out { link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; ->>>>>>> e9ecb2652be8 (arm64: dts: qcom: sm8750-mtp: Enable display) &mdss_dsi0 { vdda-supply = <&vreg_l3g_1p2>; From a84c4cddbff3b5f446dc2cf7b11628450797e840 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 17:57:44 +0200 Subject: [PATCH 0946/1330] arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Restore cam_indicator_en pinctrl Cherry-pick af5ea14df3af removed the cam_indicator_en pinctrl state from &tlmm but the leds{} node still references it via pinctrl-0. Restore the pin state definition to fix the DTC phandle error. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 5d105c20f54e7..5a27914f5cfa1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1503,6 +1503,13 @@ }; }; + cam_indicator_en: cam-indicator-en-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From ef01dc6ef56b8acc2a7d4e8919106d612c23fd08 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 18:21:33 +0200 Subject: [PATCH 0947/1330] regulator: qcom-rpmh: Restore missing struct definitions after double cherry-pick Double application of the 'new resource name format' refactor (6a8cdef7dc2a FROMLIST + e58946a61101 FROMGIT) caused ~947 lines of struct definitions and PMIC regulator data to be removed: - struct rpmh_vreg_hw_data - struct rpmh_vreg - struct rpmh_vreg_init_data - All pmic4/pmic5 hw_data definitions - All pm*_vreg_data arrays Restore the complete working file from qcom-linux. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/regulator/qcom-rpmh-regulator.c | 1146 +++++++++++++++++++++++ 1 file changed, 1146 insertions(+) diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qcom-rpmh-regulator.c index 2809036034322..6e4cb2871fca8 100644 --- a/drivers/regulator/qcom-rpmh-regulator.c +++ b/drivers/regulator/qcom-rpmh-regulator.c @@ -97,6 +97,953 @@ static const struct resource_name_formats vreg_rsc_name_lookup[NUM_REGULATOR_TYP #define PMIC530_LDO_MODE_OPM 5 #define PMIC530_LDO_MODE_HPM 7 +#define PMIC_ID_LEN 4 +/** + * struct rpmh_vreg_hw_data - RPMh regulator hardware configurations + * @regulator_type: RPMh accelerator type used to manage this + * regulator + * @ops: Pointer to regulator ops callback structure + * @voltage_ranges: The possible ranges of voltages supported by this + * PMIC regulator type + * @n_linear_ranges: Number of entries in voltage_ranges + * @n_voltages: The number of unique voltage set points defined + * by voltage_ranges + * @hpm_min_load_uA: Minimum load current in microamps that requires + * high power mode (HPM) operation. This is used + * for LDO hardware type regulators only. + * @pmic_mode_map: Array indexed by regulator framework mode + * containing PMIC hardware modes. Must be large + * enough to index all framework modes supported + * by this regulator hardware type. + * @of_map_mode: Maps an RPMH_REGULATOR_MODE_* mode value defined + * in device tree to a regulator framework mode + */ +struct rpmh_vreg_hw_data { + enum rpmh_regulator_type regulator_type; + const struct regulator_ops *ops; + const struct linear_range *voltage_ranges; + int n_linear_ranges; + int n_voltages; + int hpm_min_load_uA; + const int *pmic_mode_map; + unsigned int (*of_map_mode)(unsigned int mode); +}; + +/** + * struct rpmh_vreg - individual RPMh regulator data structure encapsulating a + * single regulator device + * @dev: Device pointer for the top-level PMIC RPMh + * regulator parent device. This is used as a + * handle in RPMh write requests. + * @addr: Base address of the regulator resource within + * an RPMh accelerator + * @rdesc: Regulator descriptor + * @hw_data: PMIC regulator configuration data for this RPMh + * regulator + * @always_wait_for_ack: Boolean flag indicating if a request must always + * wait for an ACK from RPMh before continuing even + * if it corresponds to a strictly lower power + * state (e.g. enabled --> disabled). + * @enabled: Flag indicating if the regulator is enabled or + * not + * @bypassed: Boolean indicating if the regulator is in + * bypass (pass-through) mode or not. This is + * only used by BOB rpmh-regulator resources. + * @voltage_selector: Selector used for get_voltage_sel() and + * set_voltage_sel() callbacks + * @mode: RPMh VRM regulator current framework mode + */ +struct rpmh_vreg { + struct device *dev; + u32 addr; + struct regulator_desc rdesc; + const struct rpmh_vreg_hw_data *hw_data; + bool always_wait_for_ack; + + int enabled; + bool bypassed; + int voltage_selector; + unsigned int mode; +}; + +/** + * struct rpmh_vreg_init_data - initialization data for an RPMh regulator + * @name: Name for the regulator which also corresponds + * to the device tree subnode name of the regulator + * @index: This is the index number of the regulator present + * on the PMIC. + * @vreg_hw_type: Regulator HW type enum, this must be BOB, SMPS, + * LDO, VS, based on the regulator HW type. + * @supply_name: Parent supply regulator name + * @hw_data: Configuration data for this PMIC regulator type + */ +struct rpmh_vreg_init_data { + const char *name; + enum regulator_hw_type vreg_hw_type; + int index; + const char *supply_name; + const struct rpmh_vreg_hw_data *hw_data; +}; + +/** + * rpmh_regulator_send_request() - send the request to RPMh + * @vreg: Pointer to the RPMh regulator + * @cmd: Pointer to the RPMh command to send + * @wait_for_ack: Boolean indicating if execution must wait until the + * request has been acknowledged as complete + * + * Return: 0 on success, or a negative error number on failure + */ +static int rpmh_regulator_send_request(struct rpmh_vreg *vreg, + struct tcs_cmd *cmd, bool wait_for_ack) +{ + int ret; + + if (wait_for_ack || vreg->always_wait_for_ack) + ret = rpmh_write(vreg->dev, RPMH_ACTIVE_ONLY_STATE, cmd, 1); + else + ret = rpmh_write_async(vreg->dev, RPMH_ACTIVE_ONLY_STATE, cmd, + 1); + + return ret; +} + +static int _rpmh_regulator_vrm_set_voltage_sel(struct regulator_dev *rdev, + unsigned int selector, bool wait_for_ack) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + struct tcs_cmd cmd = { + .addr = vreg->addr + RPMH_REGULATOR_REG_VRM_VOLTAGE, + }; + int ret; + + /* VRM voltage control register is set with voltage in millivolts. */ + cmd.data = DIV_ROUND_UP(regulator_list_voltage_linear_range(rdev, + selector), 1000); + + ret = rpmh_regulator_send_request(vreg, &cmd, wait_for_ack); + if (!ret) + vreg->voltage_selector = selector; + + return ret; +} + +static int rpmh_regulator_vrm_set_voltage_sel(struct regulator_dev *rdev, + unsigned int selector) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + + if (vreg->enabled == -EINVAL) { + /* + * Cache the voltage and send it later when the regulator is + * enabled or disabled. + */ + vreg->voltage_selector = selector; + return 0; + } + + return _rpmh_regulator_vrm_set_voltage_sel(rdev, selector, + selector > vreg->voltage_selector); +} + +static int rpmh_regulator_vrm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + + return vreg->voltage_selector; +} + +static int rpmh_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + + return vreg->enabled; +} + +static int rpmh_regulator_set_enable_state(struct regulator_dev *rdev, + bool enable) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + struct tcs_cmd cmd = { + .addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE, + .data = enable, + }; + int ret; + + if (vreg->enabled == -EINVAL && + vreg->voltage_selector != -ENOTRECOVERABLE) { + ret = _rpmh_regulator_vrm_set_voltage_sel(rdev, + vreg->voltage_selector, true); + if (ret < 0) + return ret; + } + + ret = rpmh_regulator_send_request(vreg, &cmd, enable); + if (!ret) + vreg->enabled = enable; + + return ret; +} + +static int rpmh_regulator_enable(struct regulator_dev *rdev) +{ + return rpmh_regulator_set_enable_state(rdev, true); +} + +static int rpmh_regulator_disable(struct regulator_dev *rdev) +{ + return rpmh_regulator_set_enable_state(rdev, false); +} + +static int rpmh_regulator_vrm_set_mode_bypass(struct rpmh_vreg *vreg, + unsigned int mode, bool bypassed) +{ + struct tcs_cmd cmd = { + .addr = vreg->addr + RPMH_REGULATOR_REG_VRM_MODE, + }; + int pmic_mode; + + if (mode > REGULATOR_MODE_STANDBY) + return -EINVAL; + + pmic_mode = vreg->hw_data->pmic_mode_map[mode]; + if (pmic_mode < 0) + return pmic_mode; + + if (bypassed) + cmd.data = PMIC4_BOB_MODE_PASS; + else + cmd.data = pmic_mode; + + return rpmh_regulator_send_request(vreg, &cmd, true); +} + +static int rpmh_regulator_vrm_set_mode(struct regulator_dev *rdev, + unsigned int mode) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + int ret; + + if (mode == vreg->mode) + return 0; + + ret = rpmh_regulator_vrm_set_mode_bypass(vreg, mode, vreg->bypassed); + if (!ret) + vreg->mode = mode; + + return ret; +} + +static unsigned int rpmh_regulator_vrm_get_mode(struct regulator_dev *rdev) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + + return vreg->mode; +} + +/** + * rpmh_regulator_vrm_get_optimum_mode() - get the mode based on the load + * @rdev: Regulator device pointer for the rpmh-regulator + * @input_uV: Input voltage + * @output_uV: Output voltage + * @load_uA: Aggregated load current in microamps + * + * This function is used in the regulator_ops for VRM type RPMh regulator + * devices. + * + * Return: 0 on success, or a negative error number on failure + */ +static unsigned int rpmh_regulator_vrm_get_optimum_mode( + struct regulator_dev *rdev, int input_uV, int output_uV, int load_uA) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + + if (load_uA >= vreg->hw_data->hpm_min_load_uA) + return REGULATOR_MODE_NORMAL; + else + return REGULATOR_MODE_IDLE; +} + +static int rpmh_regulator_vrm_set_bypass(struct regulator_dev *rdev, + bool enable) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + int ret; + + if (vreg->bypassed == enable) + return 0; + + ret = rpmh_regulator_vrm_set_mode_bypass(vreg, vreg->mode, enable); + if (!ret) + vreg->bypassed = enable; + + return ret; +} + +static int rpmh_regulator_vrm_get_bypass(struct regulator_dev *rdev, + bool *enable) +{ + struct rpmh_vreg *vreg = rdev_get_drvdata(rdev); + + *enable = vreg->bypassed; + + return 0; +} + +static const struct regulator_ops rpmh_regulator_vrm_ops = { + .enable = rpmh_regulator_enable, + .disable = rpmh_regulator_disable, + .is_enabled = rpmh_regulator_is_enabled, + .set_voltage_sel = rpmh_regulator_vrm_set_voltage_sel, + .get_voltage_sel = rpmh_regulator_vrm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_mode = rpmh_regulator_vrm_set_mode, + .get_mode = rpmh_regulator_vrm_get_mode, +}; + +static const struct regulator_ops rpmh_regulator_vrm_drms_ops = { + .enable = rpmh_regulator_enable, + .disable = rpmh_regulator_disable, + .is_enabled = rpmh_regulator_is_enabled, + .set_voltage_sel = rpmh_regulator_vrm_set_voltage_sel, + .get_voltage_sel = rpmh_regulator_vrm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_mode = rpmh_regulator_vrm_set_mode, + .get_mode = rpmh_regulator_vrm_get_mode, + .get_optimum_mode = rpmh_regulator_vrm_get_optimum_mode, +}; + +static const struct regulator_ops rpmh_regulator_vrm_bypass_ops = { + .enable = rpmh_regulator_enable, + .disable = rpmh_regulator_disable, + .is_enabled = rpmh_regulator_is_enabled, + .set_voltage_sel = rpmh_regulator_vrm_set_voltage_sel, + .get_voltage_sel = rpmh_regulator_vrm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_mode = rpmh_regulator_vrm_set_mode, + .get_mode = rpmh_regulator_vrm_get_mode, + .set_bypass = rpmh_regulator_vrm_set_bypass, + .get_bypass = rpmh_regulator_vrm_get_bypass, +}; + +static const struct regulator_ops rpmh_regulator_xob_ops = { + .enable = rpmh_regulator_enable, + .disable = rpmh_regulator_disable, + .is_enabled = rpmh_regulator_is_enabled, +}; + +/** + * rpmh_regulator_init_vreg() - initialize all attributes of an rpmh-regulator + * @vreg: Pointer to the individual rpmh-regulator resource + * @dev: Pointer to the top level rpmh-regulator PMIC device + * @node: Pointer to the individual rpmh-regulator resource + * device node + * @pmic_id: String used to identify the top level rpmh-regulator + * PMIC device on the board + * @pmic_rpmh_data: Pointer to a null-terminated array of rpmh-regulator + * resources defined for the top level PMIC device + * + * Return: 0 on success, or a negative error number on failure + */ +static int rpmh_regulator_init_vreg(struct rpmh_vreg *vreg, struct device *dev, + struct device_node *node, const char *pmic_id, + const struct rpmh_vreg_init_data *pmic_rpmh_data) +{ + struct regulator_config reg_config = {}; + char rpmh_resource_name[20] = ""; + const char *rsc_name; + const struct rpmh_vreg_init_data *rpmh_data; + struct regulator_init_data *init_data; + struct regulator_dev *rdev; + int ret; + + vreg->dev = dev; + + for (rpmh_data = pmic_rpmh_data; rpmh_data->name; rpmh_data++) + if (of_node_name_eq(node, rpmh_data->name)) + break; + + if (!rpmh_data->name) { + dev_err(dev, "Unknown regulator %pOFn\n", node); + return -EINVAL; + } + + if (strnlen(pmic_id, PMIC_ID_LEN) > 1 && strnstr(pmic_id, "_E", PMIC_ID_LEN)) { + rsc_name = vreg_rsc_name_lookup[rpmh_data->vreg_hw_type].rsc_name_fmt; + scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name), + rsc_name, rpmh_data->index, pmic_id); + + } else { + rsc_name = vreg_rsc_name_lookup[rpmh_data->vreg_hw_type].rsc_name_fmt1; + scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name), + rsc_name, pmic_id, rpmh_data->index); + } + + vreg->addr = cmd_db_read_addr(rpmh_resource_name); + if (!vreg->addr) { + dev_err(dev, "%pOFn: could not find RPMh address for resource %s\n", + node, rpmh_resource_name); + return -ENODEV; + } + + vreg->rdesc.name = rpmh_data->name; + vreg->rdesc.supply_name = rpmh_data->supply_name; + vreg->hw_data = rpmh_data->hw_data; + + vreg->enabled = -EINVAL; + vreg->voltage_selector = -ENOTRECOVERABLE; + vreg->mode = REGULATOR_MODE_INVALID; + + if (rpmh_data->hw_data->n_voltages) { + vreg->rdesc.linear_ranges = rpmh_data->hw_data->voltage_ranges; + vreg->rdesc.n_linear_ranges = rpmh_data->hw_data->n_linear_ranges; + vreg->rdesc.n_voltages = rpmh_data->hw_data->n_voltages; + } + + vreg->always_wait_for_ack = of_property_read_bool(node, + "qcom,always-wait-for-ack"); + + vreg->rdesc.owner = THIS_MODULE; + vreg->rdesc.type = REGULATOR_VOLTAGE; + vreg->rdesc.ops = vreg->hw_data->ops; + vreg->rdesc.of_map_mode = vreg->hw_data->of_map_mode; + + init_data = of_get_regulator_init_data(dev, node, &vreg->rdesc); + if (!init_data) + return -ENOMEM; + + if (rpmh_data->hw_data->regulator_type == XOB && + init_data->constraints.min_uV && + init_data->constraints.min_uV == init_data->constraints.max_uV) { + vreg->rdesc.fixed_uV = init_data->constraints.min_uV; + vreg->rdesc.n_voltages = 1; + } + + reg_config.dev = dev; + reg_config.init_data = init_data; + reg_config.of_node = node; + reg_config.driver_data = vreg; + + rdev = devm_regulator_register(dev, &vreg->rdesc, ®_config); + if (IS_ERR(rdev)) { + ret = PTR_ERR(rdev); + dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", + node, ret); + return ret; + } + + dev_dbg(dev, "%pOFn regulator registered for RPMh resource %s @ 0x%05X\n", + node, rpmh_resource_name, vreg->addr); + + return 0; +} + +static const int pmic_mode_map_pmic4_ldo[REGULATOR_MODE_STANDBY + 1] = { + [REGULATOR_MODE_INVALID] = -EINVAL, + [REGULATOR_MODE_STANDBY] = PMIC4_LDO_MODE_RETENTION, + [REGULATOR_MODE_IDLE] = PMIC4_LDO_MODE_LPM, + [REGULATOR_MODE_NORMAL] = PMIC4_LDO_MODE_HPM, + [REGULATOR_MODE_FAST] = -EINVAL, +}; + +static const int pmic_mode_map_pmic5_ldo[REGULATOR_MODE_STANDBY + 1] = { + [REGULATOR_MODE_INVALID] = -EINVAL, + [REGULATOR_MODE_STANDBY] = PMIC5_LDO_MODE_RETENTION, + [REGULATOR_MODE_IDLE] = PMIC5_LDO_MODE_LPM, + [REGULATOR_MODE_NORMAL] = PMIC5_LDO_MODE_HPM, + [REGULATOR_MODE_FAST] = -EINVAL, +}; + +static const int pmic_mode_map_pmic5_ldo_hpm[REGULATOR_MODE_STANDBY + 1] = { + [REGULATOR_MODE_INVALID] = -EINVAL, + [REGULATOR_MODE_STANDBY] = -EINVAL, + [REGULATOR_MODE_IDLE] = -EINVAL, + [REGULATOR_MODE_NORMAL] = PMIC5_LDO_MODE_HPM, + [REGULATOR_MODE_FAST] = -EINVAL, +}; + +static const int pmic_mode_map_pmic530_ldo[REGULATOR_MODE_STANDBY + 1] = { + [REGULATOR_MODE_INVALID] = -EINVAL, + [REGULATOR_MODE_STANDBY] = PMIC530_LDO_MODE_RETENTION, + [REGULATOR_MODE_IDLE] = PMIC530_LDO_MODE_LPM, + [REGULATOR_MODE_NORMAL] = PMIC530_LDO_MODE_OPM, + [REGULATOR_MODE_FAST] = PMIC530_LDO_MODE_HPM, +}; + +static unsigned int rpmh_regulator_pmic4_ldo_of_map_mode(unsigned int rpmh_mode) +{ + unsigned int mode; + + switch (rpmh_mode) { + case RPMH_REGULATOR_MODE_HPM: + mode = REGULATOR_MODE_NORMAL; + break; + case RPMH_REGULATOR_MODE_LPM: + mode = REGULATOR_MODE_IDLE; + break; + case RPMH_REGULATOR_MODE_RET: + mode = REGULATOR_MODE_STANDBY; + break; + default: + mode = REGULATOR_MODE_INVALID; + break; + } + + return mode; +} + +static unsigned int rpmh_regulator_pmic530_ldo_of_map_mode(unsigned int rpmh_mode) +{ + unsigned int mode; + + switch (rpmh_mode) { + case RPMH_REGULATOR_MODE_HPM: + mode = REGULATOR_MODE_FAST; + break; + case RPMH_REGULATOR_MODE_AUTO: + mode = REGULATOR_MODE_NORMAL; + break; + case RPMH_REGULATOR_MODE_LPM: + mode = REGULATOR_MODE_IDLE; + break; + case RPMH_REGULATOR_MODE_RET: + mode = REGULATOR_MODE_STANDBY; + break; + default: + mode = REGULATOR_MODE_INVALID; + break; + } + return mode; +} + +static const int pmic_mode_map_pmic4_smps[REGULATOR_MODE_STANDBY + 1] = { + [REGULATOR_MODE_INVALID] = -EINVAL, + [REGULATOR_MODE_STANDBY] = PMIC4_SMPS_MODE_RETENTION, + [REGULATOR_MODE_IDLE] = PMIC4_SMPS_MODE_PFM, + [REGULATOR_MODE_NORMAL] = PMIC4_SMPS_MODE_AUTO, + [REGULATOR_MODE_FAST] = PMIC4_SMPS_MODE_PWM, +}; + +static const int pmic_mode_map_pmic5_smps[REGULATOR_MODE_STANDBY + 1] = { + [REGULATOR_MODE_INVALID] = -EINVAL, + [REGULATOR_MODE_STANDBY] = PMIC5_SMPS_MODE_RETENTION, + [REGULATOR_MODE_IDLE] = PMIC5_SMPS_MODE_PFM, + [REGULATOR_MODE_NORMAL] = PMIC5_SMPS_MODE_AUTO, + [REGULATOR_MODE_FAST] = PMIC5_SMPS_MODE_PWM, +}; + +static unsigned int +rpmh_regulator_pmic4_smps_of_map_mode(unsigned int rpmh_mode) +{ + unsigned int mode; + + switch (rpmh_mode) { + case RPMH_REGULATOR_MODE_HPM: + mode = REGULATOR_MODE_FAST; + break; + case RPMH_REGULATOR_MODE_AUTO: + mode = REGULATOR_MODE_NORMAL; + break; + case RPMH_REGULATOR_MODE_LPM: + mode = REGULATOR_MODE_IDLE; + break; + case RPMH_REGULATOR_MODE_RET: + mode = REGULATOR_MODE_STANDBY; + break; + default: + mode = REGULATOR_MODE_INVALID; + break; + } + + return mode; +} + +static const int pmic_mode_map_pmic4_bob[REGULATOR_MODE_STANDBY + 1] = { + [REGULATOR_MODE_INVALID] = -EINVAL, + [REGULATOR_MODE_STANDBY] = -EINVAL, + [REGULATOR_MODE_IDLE] = PMIC4_BOB_MODE_PFM, + [REGULATOR_MODE_NORMAL] = PMIC4_BOB_MODE_AUTO, + [REGULATOR_MODE_FAST] = PMIC4_BOB_MODE_PWM, +}; + +static const int pmic_mode_map_pmic5_bob[REGULATOR_MODE_STANDBY + 1] = { + [REGULATOR_MODE_INVALID] = -EINVAL, + [REGULATOR_MODE_STANDBY] = -EINVAL, + [REGULATOR_MODE_IDLE] = PMIC5_BOB_MODE_PFM, + [REGULATOR_MODE_NORMAL] = PMIC5_BOB_MODE_AUTO, + [REGULATOR_MODE_FAST] = PMIC5_BOB_MODE_PWM, +}; + +static unsigned int rpmh_regulator_pmic4_bob_of_map_mode(unsigned int rpmh_mode) +{ + unsigned int mode; + + switch (rpmh_mode) { + case RPMH_REGULATOR_MODE_HPM: + mode = REGULATOR_MODE_FAST; + break; + case RPMH_REGULATOR_MODE_AUTO: + mode = REGULATOR_MODE_NORMAL; + break; + case RPMH_REGULATOR_MODE_LPM: + mode = REGULATOR_MODE_IDLE; + break; + default: + mode = REGULATOR_MODE_INVALID; + break; + } + + return mode; +} + +static const struct rpmh_vreg_hw_data pmic4_pldo = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 256, + .hpm_min_load_uA = 10000, + .pmic_mode_map = pmic_mode_map_pmic4_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic4_pldo_lv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 128, + .hpm_min_load_uA = 10000, + .pmic_mode_map = pmic_mode_map_pmic4_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic4_nldo = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 128, + .hpm_min_load_uA = 30000, + .pmic_mode_map = pmic_mode_map_pmic4_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic4_hfsmps3 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 216, + .pmic_mode_map = pmic_mode_map_pmic4_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic4_ftsmps426 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000), + }, + .n_linear_ranges = 1, + .n_voltages = 259, + .pmic_mode_map = pmic_mode_map_pmic4_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic4_bob = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_bypass_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000), + }, + .n_linear_ranges = 1, + .n_voltages = 84, + .pmic_mode_map = pmic_mode_map_pmic4_bob, + .of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic4_lvs = { + .regulator_type = XOB, + .ops = &rpmh_regulator_xob_ops, + /* LVS hardware does not support voltage or mode configuration. */ +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 256, + .hpm_min_load_uA = 10000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo_lv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 63, + .hpm_min_load_uA = 10000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo515_mv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1800000, 0, 187, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 188, + .hpm_min_load_uA = 10000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo502 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 256, + .pmic_mode_map = pmic_mode_map_pmic5_ldo_hpm, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo502ln = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1800000, 0, 2, 200000), + REGULATOR_LINEAR_RANGE(2608000, 3, 28, 16000), + REGULATOR_LINEAR_RANGE(3104000, 29, 30, 96000), + REGULATOR_LINEAR_RANGE(3312000, 31, 31, 0), + }, + .n_linear_ranges = 4, + .n_voltages = 32, + .pmic_mode_map = pmic_mode_map_pmic5_ldo_hpm, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_nldo = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 124, + .hpm_min_load_uA = 30000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_nldo515 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 211, + .hpm_min_load_uA = 30000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_nldo502 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(528000, 0, 127, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 128, + .hpm_min_load_uA = 30000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .of_map_mode = rpmh_regulator_pmic4_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_hfsmps510 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 216, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps510 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(300000, 0, 263, 4000), + }, + .n_linear_ranges = 1, + .n_voltages = 264, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps520 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(300000, 0, 263, 4000), + }, + .n_linear_ranges = 1, + .n_voltages = 264, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps525 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(300000, 0, 267, 4000), + REGULATOR_LINEAR_RANGE(1376000, 268, 438, 8000), + }, + .n_linear_ranges = 2, + .n_voltages = 439, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps527 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 215, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_hfsmps515 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 235, 16000), + }, + .n_linear_ranges = 1, + .n_voltages = 236, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_hfsmps515_1 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(900000, 0, 4, 16000), + }, + .n_linear_ranges = 1, + .n_voltages = 5, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_bob = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_bypass_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(3000000, 0, 31, 32000), + }, + .n_linear_ranges = 1, + .n_voltages = 32, + .pmic_mode_map = pmic_mode_map_pmic5_bob, + .of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_nldo530 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 211, + .hpm_min_load_uA = 30000, + .pmic_mode_map = pmic_mode_map_pmic530_ldo, + .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp150 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 256, + .hpm_min_load_uA = 10000, + .pmic_mode_map = pmic_mode_map_pmic530_ldo, + .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp300 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 256, + .hpm_min_load_uA = 20000, + .pmic_mode_map = pmic_mode_map_pmic530_ldo, + .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp600 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 256, + .hpm_min_load_uA = 40000, + .pmic_mode_map = pmic_mode_map_pmic530_ldo, + .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps530 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_ops, + .voltage_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(252000, 0, 305, 4000), + REGULATOR_LINEAR_RANGE(1480000, 306, 464, 8000), + }, + .n_linear_ranges = 2, + .n_voltages = 465, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + #define RPMH_VREG(_name, _vreg_hw_type, _index, _hw_data, _supply_name) \ { \ .name = _name, \ @@ -597,6 +1544,205 @@ static const struct rpmh_vreg_init_data pmh0110_vreg_data[] = { RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3"), RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l4"), {} +}; + +static const struct rpmh_vreg_init_data pmx55_vreg_data[] = { + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps510, "vdd-s3"), + RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"), + RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"), + RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"), + RPMH_VREG("smps7", SMPS, 7, &pmic5_hfsmps510, "vdd-s7"), + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l9"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4-l12"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7-l8"), + RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l7-l8"), + RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l3-l9"), + RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10-l11-l13"), + RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l10-l11-l13"), + RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l4-l12"), + RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l10-l11-l13"), + RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14"), + RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l15"), + RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l16"), + {} +}; + +static const struct rpmh_vreg_init_data pmx65_vreg_data[] = { + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps510, "vdd-s3"), + RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"), + RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"), + RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"), + RPMH_VREG("smps7", SMPS, 7, &pmic5_hfsmps510, "vdd-s7"), + RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"), + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l18"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6-l16"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6-l16"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7"), + RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8-l9"), + RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l8-l9"), + RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10"), + RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l11-l13"), + RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l12"), + RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l11-l13"), + RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14"), + RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l15"), + RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l5-l6-l16"), + RPMH_VREG("ldo17", LDO, 17, &pmic5_nldo, "vdd-l17"), + /* ldo18 not configured */ + RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo, "vdd-l19"), + RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo, "vdd-l20"), + RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo, "vdd-l21"), + {} +}; + +static const struct rpmh_vreg_init_data pmx75_vreg_data[] = { + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"), + RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"), + RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"), + RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"), + RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps525, "vdd-s7"), + RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps525, "vdd-s8"), + RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps525, "vdd-s9"), + RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps525, "vdd-s10"), + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-18"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l4-l16"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo_lv, "vdd-l5-l6"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo_lv, "vdd-l5-l6"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"), + RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo515, "vdd-l8-l9"), + RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo515, "vdd-l8-l9"), + RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10"), + RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l11-l13"), + RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo515, "vdd-l12"), + RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l11-l13"), + RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo515, "vdd-l14"), + RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo515, "vdd-l15"), + RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo515, "vdd-l4-l16"), + RPMH_VREG("ldo17", LDO, 17, &pmic5_nldo515, "vdd-l17"), + /* ldo18 not configured */ + RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo515, "vdd-l19"), + RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo515, "vdd-l20-l21"), + RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo515, "vdd-l20-l21"), +}; + +static const struct rpmh_vreg_init_data pm7325_vreg_data[] = { + RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps510, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps520, "vdd-s3"), + RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps520, "vdd-s4"), + RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps520, "vdd-s5"), + RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps520, "vdd-s6"), + RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps520, "vdd-s7"), + RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"), + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l4-l12-l15"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l7"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l1-l4-l12-l15"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9-l10"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l2-l7"), + RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8"), + RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9-l10"), + RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo, "vdd-l6-l9-l10"), + RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"), + RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l1-l4-l12-l15"), + RPMH_VREG("ldo13", LDO, 13, &pmic5_nldo, "vdd-l13"), + RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14-l16"), + RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l1-l4-l12-l15"), + RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo, "vdd-l14-l16"), + RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"), + RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"), + RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"), + {} +}; + +static const struct rpmh_vreg_init_data pm7550_vreg_data[] = { + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"), + RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"), + RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"), + RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"), + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-l3"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l2-l3"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l4-l5"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-l4-l5"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"), + RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo515, "vdd-l8"), + RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo515, "vdd-l9-l10"), + RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo515, "vdd-l9-l10"), + RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo515, "vdd-l11"), + RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo515_mv, "vdd-l12-l14"), + RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo515_mv, "vdd-l13-l16"), + RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo, "vdd-l12-l14"), + RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), + RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l13-l16"), + RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), + RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), + RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), + RPMH_VREG("ldo20", LDO, 20, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), + RPMH_VREG("ldo21", LDO, 21, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), + RPMH_VREG("ldo22", LDO, 22, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), + RPMH_VREG("ldo23", LDO, 23, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"), + RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"), + {} +}; + +static const struct rpmh_vreg_init_data pmr735a_vreg_data[] = { + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps520, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps515, "vdd-s3"), + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5-l6"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l5-l6"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-bob"), + {} +}; + +static const struct rpmh_vreg_init_data pmr735b_vreg_data[] = { + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7-l8"), + RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l7-l8"), + RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l9"), + RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo_lv, "vdd-l10"), + RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo, "vdd-l11"), + RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l12"), + {} +}; + +static const struct rpmh_vreg_init_data pmr735d_vreg_data[] = { + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1-l2-l5"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l1-l2-l5"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3-l4"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l3-l4"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-l1-l2-l5"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"), {} }; From 25cfc26ca86fab1060728804e2d628d1dcac16d7 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 18:32:57 +0200 Subject: [PATCH 0948/1330] soc: qcom: smem: Restore debugfs_dir field and smem_dram_parse support The struct qcom_smem was missing the debugfs_dir dentry field and the associated smem_dram_parse() usage from qcom-next. This caused: 'struct qcom_smem has no member named debugfs_dir' Restore complete working file from qcom-linux. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/soc/qcom/smem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 95afeaa00066e..4315512d3a1d4 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -284,6 +284,8 @@ struct qcom_smem { struct smem_partition global_partition; struct xarray partitions; + struct dentry *debugfs_dir; + unsigned num_regions; struct smem_region regions[] __counted_by(num_regions); }; From d5a66f51bb4a4c92c2b8de6035dcb3989869426f Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 18:44:28 +0200 Subject: [PATCH 0949/1330] soc: qcom: ice: Add missing pm_runtime.h include Ubuntu-specific additions use devm_pm_runtime_enable() and pm_runtime_get_sync() but the required header was missing. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/soc/qcom/ice.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index e6a0e647c9b1d..5b8c829212073 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -17,6 +17,7 @@ #include #include #include +#include #include From 4e55700aa15fd1fa015d625bc282f5159e7eb81a Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 19:28:40 +0200 Subject: [PATCH 0950/1330] FROMLIST: misc: fastrpc: fix UAF and kernel panic during cleanup on process abort When a userspace FastRPC client is abruptly terminated, FastRPC cleanup paths can race with device and session teardown. This results in kernel panics in different release paths: - fastrpc_release() when using remote heap, originating from fastrpc_buf_free() - fastrpc_device_release() when using system heap, originating from fastrpc_free_map() In addition, fastrpc_map_put() may trigger refcount use-after-free due to concurrent cleanup without proper synchronization. Fix by introducing mutex protection for map and buf lifetime, serializing cleanup against device teardown, and skipping operations when the device is already gone. Also guard mutex_destroy in fastrpc_channel_ctx_free with the new 'allocated' flag. Applied manually: patch context didn't match due to ubuntu-specific 'bool coherent' field and pre-existing 'struct mutex mutex' in struct fastrpc_session_ctx. Link: https://lore.kernel.org/all/20260427105310.4056-1-jianping.li@oss.qualcomm.com/ Fixes: c68cfb718c8f9 ("misc: fastrpc: Add support for context Invoke method") Cc: stable@kernel.org Signed-off-by: Jianping Li Signed-off-by: Kuba Pawlak --- drivers/misc/fastrpc.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index b266fc5a3bb32..15d7622a29f02 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -273,6 +273,8 @@ struct fastrpc_session_ctx { bool used; bool valid; bool coherent; + bool allocated; + struct mutex mutex; }; struct fastrpc_soc_data { @@ -464,9 +466,18 @@ static void fastrpc_buf_free(struct fastrpc_buf *buf) if (!buf) return; - dma_free_coherent(buf->dev, buf->size, buf->virt, - fastrpc_ipa_to_dma_addr(buf->fl->cctx, buf->dma_addr)); - kfree(buf); + struct fastrpc_user *fl = buf->fl; + + if (!fl) + return; + mutex_lock(&fl->sctx->mutex); + if (fl->sctx->dev) { + dma_free_coherent(buf->dev, buf->size, buf->virt, + fastrpc_ipa_to_dma_addr(buf->fl->cctx, + buf->dma_addr)); + kfree(buf); + } + mutex_unlock(&fl->sctx->mutex); } static int __fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, @@ -535,8 +546,10 @@ static void fastrpc_channel_ctx_free(struct kref *ref) struct fastrpc_channel_ctx *cctx; cctx = container_of(ref, struct fastrpc_channel_ctx, refcount); - for (int i = 0; i < FASTRPC_MAX_SESSIONS; i++) - mutex_destroy(&cctx->session[i].mutex); + for (int i = 0; i < FASTRPC_MAX_SESSIONS; i++) { + if (cctx->session[i].allocated) + mutex_destroy(&cctx->session[i].mutex); + } kfree(cctx); } @@ -2476,6 +2489,8 @@ static int fastrpc_cb_probe(struct platform_device *pdev) sess->dev = dev; sess->coherent = of_property_read_bool(dev->of_node, "dma-coherent"); dev_set_drvdata(dev, sess); + mutex_init(&sess->mutex); + sess->allocated = true; if (cctx->domain_id == CDSP_DOMAIN_ID) dma_bits = cctx->soc_data->dma_addr_bits_cdsp; @@ -2492,6 +2507,7 @@ static int fastrpc_cb_probe(struct platform_device *pdev) dup_sess = &cctx->session[cctx->sesscount++]; memcpy(dup_sess, sess, sizeof(*dup_sess)); mutex_init(&dup_sess->mutex); + dup_sess->allocated = true; } } spin_unlock_irqrestore(&cctx->lock, flags); From c02bc59f03c47377b8cb3f88b91c11a3df8ae041 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 19:44:13 +0200 Subject: [PATCH 0951/1330] clk: qcom: nord: Add missing Nord GCC/TCSR clock source files and headers Makefile referenced gcc-nord.o, negcc-nord.o, nwgcc-nord.o, segcc-nord.o, tcsrcc-nord.o but the source files were never cherry-picked. Add: - drivers/clk/qcom/gcc-nord.c - drivers/clk/qcom/negcc-nord.c - drivers/clk/qcom/nwgcc-nord.c - drivers/clk/qcom/segcc-nord.c - drivers/clk/qcom/tcsrcc-nord.c - include/dt-bindings/clock/qcom,nord-{gcc,negcc,tcsrcc}.h Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/clk/qcom/gcc-nord.c | 1902 +++++++++++++++++ drivers/clk/qcom/negcc-nord.c | 1987 ++++++++++++++++++ drivers/clk/qcom/nwgcc-nord.c | 688 ++++++ drivers/clk/qcom/segcc-nord.c | 1609 ++++++++++++++ drivers/clk/qcom/tcsrcc-nord.c | 337 +++ include/dt-bindings/clock/qcom,nord-gcc.h | 147 ++ include/dt-bindings/clock/qcom,nord-negcc.h | 124 ++ include/dt-bindings/clock/qcom,nord-tcsrcc.h | 26 + 8 files changed, 6820 insertions(+) create mode 100644 drivers/clk/qcom/gcc-nord.c create mode 100644 drivers/clk/qcom/negcc-nord.c create mode 100644 drivers/clk/qcom/nwgcc-nord.c create mode 100644 drivers/clk/qcom/segcc-nord.c create mode 100644 drivers/clk/qcom/tcsrcc-nord.c create mode 100644 include/dt-bindings/clock/qcom,nord-gcc.h create mode 100644 include/dt-bindings/clock/qcom,nord-negcc.h create mode 100644 include/dt-bindings/clock/qcom,nord-tcsrcc.h diff --git a/drivers/clk/qcom/gcc-nord.c b/drivers/clk/qcom/gcc-nord.c new file mode 100644 index 0000000000000..3098d8fac0fb2 --- /dev/null +++ b/drivers/clk/qcom/gcc-nord.c @@ -0,0 +1,1902 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_PCIE_A_PIPE_CLK, + DT_PCIE_B_PIPE_CLK, + DT_PCIE_C_PIPE_CLK, + DT_PCIE_D_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_GCC_GPLL0_OUT_EVEN, + P_GCC_GPLL0_OUT_MAIN, + P_PCIE_A_PIPE_CLK, + P_PCIE_B_PIPE_CLK, + P_PCIE_C_PIPE_CLK, + P_PCIE_D_PIPE_CLK, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gcc_gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x9d020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gpll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_gcc_gpll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gpll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &gcc_gpll0.clkr.hw }, + { .hw = &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gcc_gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, + { .hw = &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &gcc_gpll0.clkr.hw }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_a_pipe_clk_src = { + .reg = 0x49094, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_pipe_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_A_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_b_pipe_clk_src = { + .reg = 0x4a094, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_pipe_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_B_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_c_pipe_clk_src = { + .reg = 0x4b094, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_pipe_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_C_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_d_pipe_clk_src = { + .reg = 0x4c094, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_pipe_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_D_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x30004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gp1_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x31004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gp2_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_a_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_a_aux_clk_src = { + .cmd_rcgr = 0x49098, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_aux_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_a_phy_aux_clk_src = { + .cmd_rcgr = 0x4d020, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_phy_aux_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_a_phy_rchng_clk_src[] = { + F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_a_phy_rchng_clk_src = { + .cmd_rcgr = 0x4907c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_phy_rchng_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_b_aux_clk_src = { + .cmd_rcgr = 0x4a098, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_aux_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_b_phy_aux_clk_src = { + .cmd_rcgr = 0x4e020, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_phy_aux_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_b_phy_rchng_clk_src = { + .cmd_rcgr = 0x4a07c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_phy_rchng_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_c_aux_clk_src = { + .cmd_rcgr = 0x4b098, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_aux_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_c_phy_aux_clk_src = { + .cmd_rcgr = 0x4f020, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_phy_aux_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_c_phy_rchng_clk_src = { + .cmd_rcgr = 0x4b07c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_phy_rchng_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_d_aux_clk_src = { + .cmd_rcgr = 0x4c098, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_aux_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_d_phy_aux_clk_src = { + .cmd_rcgr = 0x50020, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_phy_aux_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_d_phy_rchng_clk_src = { + .cmd_rcgr = 0x4c07c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_phy_rchng_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_noc_refgen_clk_src = { + .cmd_rcgr = 0x52094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_refgen_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_noc_safety_clk_src = { + .cmd_rcgr = 0x520ac, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_safety_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + F(40000000, P_GCC_GPLL0_OUT_MAIN, 15, 0, 0), + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x1a010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = { + .name = "gcc_qupv3_wrap3_qspi_ref_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = { + .cmd_rcgr = 0x23174, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init, +}; + +static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = { + .reg = 0x2316c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap3_s0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x1f004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x30000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x31000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmu_0_tcu_vote_clk = { + .halt_reg = 0x7d094, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d094, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_mmu_0_tcu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_aux_clk = { + .halt_reg = 0x49058, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x49058, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_a_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_cfg_ahb_clk = { + .halt_reg = 0x49054, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x49054, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(13), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_dti_qtc_clk = { + .halt_reg = 0x49018, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x49018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_dti_qtc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_mstr_axi_clk = { + .halt_reg = 0x49040, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x49040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(12), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_phy_aux_clk = { + .halt_reg = 0x4d01c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(12), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_a_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_phy_rchng_clk = { + .halt_reg = 0x49078, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x49078, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(16), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_phy_rchng_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_a_phy_rchng_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_pipe_clk = { + .halt_reg = 0x49068, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x49068, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(15), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_a_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_slv_axi_clk = { + .halt_reg = 0x4902c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x4902c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(11), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_slv_q2a_axi_clk = { + .halt_reg = 0x49024, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x49024, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(10), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_a_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_aux_clk = { + .halt_reg = 0x4a058, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(23), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_b_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_cfg_ahb_clk = { + .halt_reg = 0x4a054, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x4a054, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(22), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_dti_qtc_clk = { + .halt_reg = 0x4a018, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x4a018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(17), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_dti_qtc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_mstr_axi_clk = { + .halt_reg = 0x4a040, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x4a040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(21), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_phy_aux_clk = { + .halt_reg = 0x4e01c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(13), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_b_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_phy_rchng_clk = { + .halt_reg = 0x4a078, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(25), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_phy_rchng_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_b_phy_rchng_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_pipe_clk = { + .halt_reg = 0x4a068, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(24), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_b_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_slv_axi_clk = { + .halt_reg = 0x4a02c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x4a02c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_slv_q2a_axi_clk = { + .halt_reg = 0x4a024, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_b_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_aux_clk = { + .halt_reg = 0x4b058, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_c_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_cfg_ahb_clk = { + .halt_reg = 0x4b054, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x4b054, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(31), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_dti_qtc_clk = { + .halt_reg = 0x4b018, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x4b018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(26), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_dti_qtc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_mstr_axi_clk = { + .halt_reg = 0x4b040, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x4b040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(30), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_phy_aux_clk = { + .halt_reg = 0x4f01c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_c_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_phy_rchng_clk = { + .halt_reg = 0x4b078, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(2), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_phy_rchng_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_c_phy_rchng_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_pipe_clk = { + .halt_reg = 0x4b068, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(1), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_c_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_slv_axi_clk = { + .halt_reg = 0x4b02c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x4b02c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(29), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_slv_q2a_axi_clk = { + .halt_reg = 0x4b024, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d008, + .enable_mask = BIT(28), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_c_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_aux_clk = { + .halt_reg = 0x4c058, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(9), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_d_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_cfg_ahb_clk = { + .halt_reg = 0x4c054, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x4c054, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_dti_qtc_clk = { + .halt_reg = 0x4c018, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x4c018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(3), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_dti_qtc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_mstr_axi_clk = { + .halt_reg = 0x4c040, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x4c040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(7), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_phy_aux_clk = { + .halt_reg = 0x5001c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(16), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_d_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_phy_rchng_clk = { + .halt_reg = 0x4c078, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(11), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_phy_rchng_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_d_phy_rchng_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_pipe_clk = { + .halt_reg = 0x4c068, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(10), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_d_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_slv_axi_clk = { + .halt_reg = 0x4c02c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x4c02c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = { + .halt_reg = 0x4c024, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(5), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_d_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_link_ahb_clk = { + .halt_reg = 0x52464, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52464, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_link_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_link_xo_clk = { + .halt_reg = 0x52468, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x52468, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52468, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_link_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_async_bridge_clk = { + .halt_reg = 0x52048, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x52048, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d018, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_async_bridge_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_cnoc_sf_qx_clk = { + .halt_reg = 0x52040, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x52040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(24), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_cnoc_sf_qx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_m_cfg_clk = { + .halt_reg = 0x52060, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x52060, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d018, + .enable_mask = BIT(4), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_m_cfg_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_m_pdb_clk = { + .halt_reg = 0x52084, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x52084, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d018, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_m_pdb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_mstr_axi_clk = { + .halt_reg = 0x52050, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x52050, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(25), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_pwrctl_clk = { + .halt_reg = 0x52080, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d018, + .enable_mask = BIT(7), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_pwrctl_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = { + .halt_reg = 0x52074, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_qosgen_extref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_refgen_clk = { + .halt_reg = 0x52078, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52078, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_refgen_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_noc_refgen_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_s_cfg_clk = { + .halt_reg = 0x52064, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d018, + .enable_mask = BIT(5), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_s_cfg_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_s_pdb_clk = { + .halt_reg = 0x5208c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x5208c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d018, + .enable_mask = BIT(9), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_s_pdb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_safety_clk = { + .halt_reg = 0x5207c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5207c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_safety_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_noc_safety_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_slave_axi_clk = { + .halt_reg = 0x52058, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x52058, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(26), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_slave_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_tsctr_clk = { + .halt_reg = 0x52070, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_xo_clk = { + .halt_reg = 0x52068, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d018, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_noc_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x1a00c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a00c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x1a004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1a004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x1a008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { + .halt_reg = 0x23020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d000, + .enable_mask = BIT(24), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap3_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_core_clk = { + .halt_reg = 0x2300c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d000, + .enable_mask = BIT(23), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap3_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_m_clk = { + .halt_reg = 0x23004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x23004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d000, + .enable_mask = BIT(22), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap3_m_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = { + .halt_reg = 0x23170, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d000, + .enable_mask = BIT(26), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap3_qspi_ref_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_s0_clk = { + .halt_reg = 0x2315c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9d000, + .enable_mask = BIT(25), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap3_s0_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_s_ahb_clk = { + .halt_reg = 0x23008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x23008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x9d010, + .enable_mask = BIT(15), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap3_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_smmu_pcie_qtc_vote_clk = { + .halt_reg = 0x7d0b8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d0b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_smmu_pcie_qtc_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gcc_pcie_a_gdsc = { + .gdscr = 0x49004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(1), + .pd = { + .name = "gcc_pcie_a_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_a_phy_gdsc = { + .gdscr = 0x4d004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(5), + .pd = { + .name = "gcc_pcie_a_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_b_gdsc = { + .gdscr = 0x4a004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(2), + .pd = { + .name = "gcc_pcie_b_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_b_phy_gdsc = { + .gdscr = 0x4e004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(6), + .pd = { + .name = "gcc_pcie_b_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_c_gdsc = { + .gdscr = 0x4b004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(3), + .pd = { + .name = "gcc_pcie_c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_c_phy_gdsc = { + .gdscr = 0x4f004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(7), + .pd = { + .name = "gcc_pcie_c_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_d_gdsc = { + .gdscr = 0x4c004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(4), + .pd = { + .name = "gcc_pcie_d_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_d_phy_gdsc = { + .gdscr = 0x50004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(8), + .pd = { + .name = "gcc_pcie_d_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_noc_gdsc = { + .gdscr = 0x52004, + .gds_hw_ctrl = 0x52018, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .collapse_ctrl = 0x8d02c, + .collapse_mask = BIT(0), + .pd = { + .name = "gcc_pcie_noc_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct clk_regmap *gcc_nord_clocks[] = { + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, + [GCC_GPLL0] = &gcc_gpll0.clkr, + [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, + [GCC_MMU_0_TCU_VOTE_CLK] = &gcc_mmu_0_tcu_vote_clk.clkr, + [GCC_PCIE_A_AUX_CLK] = &gcc_pcie_a_aux_clk.clkr, + [GCC_PCIE_A_AUX_CLK_SRC] = &gcc_pcie_a_aux_clk_src.clkr, + [GCC_PCIE_A_CFG_AHB_CLK] = &gcc_pcie_a_cfg_ahb_clk.clkr, + [GCC_PCIE_A_DTI_QTC_CLK] = &gcc_pcie_a_dti_qtc_clk.clkr, + [GCC_PCIE_A_MSTR_AXI_CLK] = &gcc_pcie_a_mstr_axi_clk.clkr, + [GCC_PCIE_A_PHY_AUX_CLK] = &gcc_pcie_a_phy_aux_clk.clkr, + [GCC_PCIE_A_PHY_AUX_CLK_SRC] = &gcc_pcie_a_phy_aux_clk_src.clkr, + [GCC_PCIE_A_PHY_RCHNG_CLK] = &gcc_pcie_a_phy_rchng_clk.clkr, + [GCC_PCIE_A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_a_phy_rchng_clk_src.clkr, + [GCC_PCIE_A_PIPE_CLK] = &gcc_pcie_a_pipe_clk.clkr, + [GCC_PCIE_A_PIPE_CLK_SRC] = &gcc_pcie_a_pipe_clk_src.clkr, + [GCC_PCIE_A_SLV_AXI_CLK] = &gcc_pcie_a_slv_axi_clk.clkr, + [GCC_PCIE_A_SLV_Q2A_AXI_CLK] = &gcc_pcie_a_slv_q2a_axi_clk.clkr, + [GCC_PCIE_B_AUX_CLK] = &gcc_pcie_b_aux_clk.clkr, + [GCC_PCIE_B_AUX_CLK_SRC] = &gcc_pcie_b_aux_clk_src.clkr, + [GCC_PCIE_B_CFG_AHB_CLK] = &gcc_pcie_b_cfg_ahb_clk.clkr, + [GCC_PCIE_B_DTI_QTC_CLK] = &gcc_pcie_b_dti_qtc_clk.clkr, + [GCC_PCIE_B_MSTR_AXI_CLK] = &gcc_pcie_b_mstr_axi_clk.clkr, + [GCC_PCIE_B_PHY_AUX_CLK] = &gcc_pcie_b_phy_aux_clk.clkr, + [GCC_PCIE_B_PHY_AUX_CLK_SRC] = &gcc_pcie_b_phy_aux_clk_src.clkr, + [GCC_PCIE_B_PHY_RCHNG_CLK] = &gcc_pcie_b_phy_rchng_clk.clkr, + [GCC_PCIE_B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_b_phy_rchng_clk_src.clkr, + [GCC_PCIE_B_PIPE_CLK] = &gcc_pcie_b_pipe_clk.clkr, + [GCC_PCIE_B_PIPE_CLK_SRC] = &gcc_pcie_b_pipe_clk_src.clkr, + [GCC_PCIE_B_SLV_AXI_CLK] = &gcc_pcie_b_slv_axi_clk.clkr, + [GCC_PCIE_B_SLV_Q2A_AXI_CLK] = &gcc_pcie_b_slv_q2a_axi_clk.clkr, + [GCC_PCIE_C_AUX_CLK] = &gcc_pcie_c_aux_clk.clkr, + [GCC_PCIE_C_AUX_CLK_SRC] = &gcc_pcie_c_aux_clk_src.clkr, + [GCC_PCIE_C_CFG_AHB_CLK] = &gcc_pcie_c_cfg_ahb_clk.clkr, + [GCC_PCIE_C_DTI_QTC_CLK] = &gcc_pcie_c_dti_qtc_clk.clkr, + [GCC_PCIE_C_MSTR_AXI_CLK] = &gcc_pcie_c_mstr_axi_clk.clkr, + [GCC_PCIE_C_PHY_AUX_CLK] = &gcc_pcie_c_phy_aux_clk.clkr, + [GCC_PCIE_C_PHY_AUX_CLK_SRC] = &gcc_pcie_c_phy_aux_clk_src.clkr, + [GCC_PCIE_C_PHY_RCHNG_CLK] = &gcc_pcie_c_phy_rchng_clk.clkr, + [GCC_PCIE_C_PHY_RCHNG_CLK_SRC] = &gcc_pcie_c_phy_rchng_clk_src.clkr, + [GCC_PCIE_C_PIPE_CLK] = &gcc_pcie_c_pipe_clk.clkr, + [GCC_PCIE_C_PIPE_CLK_SRC] = &gcc_pcie_c_pipe_clk_src.clkr, + [GCC_PCIE_C_SLV_AXI_CLK] = &gcc_pcie_c_slv_axi_clk.clkr, + [GCC_PCIE_C_SLV_Q2A_AXI_CLK] = &gcc_pcie_c_slv_q2a_axi_clk.clkr, + [GCC_PCIE_D_AUX_CLK] = &gcc_pcie_d_aux_clk.clkr, + [GCC_PCIE_D_AUX_CLK_SRC] = &gcc_pcie_d_aux_clk_src.clkr, + [GCC_PCIE_D_CFG_AHB_CLK] = &gcc_pcie_d_cfg_ahb_clk.clkr, + [GCC_PCIE_D_DTI_QTC_CLK] = &gcc_pcie_d_dti_qtc_clk.clkr, + [GCC_PCIE_D_MSTR_AXI_CLK] = &gcc_pcie_d_mstr_axi_clk.clkr, + [GCC_PCIE_D_PHY_AUX_CLK] = &gcc_pcie_d_phy_aux_clk.clkr, + [GCC_PCIE_D_PHY_AUX_CLK_SRC] = &gcc_pcie_d_phy_aux_clk_src.clkr, + [GCC_PCIE_D_PHY_RCHNG_CLK] = &gcc_pcie_d_phy_rchng_clk.clkr, + [GCC_PCIE_D_PHY_RCHNG_CLK_SRC] = &gcc_pcie_d_phy_rchng_clk_src.clkr, + [GCC_PCIE_D_PIPE_CLK] = &gcc_pcie_d_pipe_clk.clkr, + [GCC_PCIE_D_PIPE_CLK_SRC] = &gcc_pcie_d_pipe_clk_src.clkr, + [GCC_PCIE_D_SLV_AXI_CLK] = &gcc_pcie_d_slv_axi_clk.clkr, + [GCC_PCIE_D_SLV_Q2A_AXI_CLK] = &gcc_pcie_d_slv_q2a_axi_clk.clkr, + [GCC_PCIE_LINK_AHB_CLK] = &gcc_pcie_link_ahb_clk.clkr, + [GCC_PCIE_LINK_XO_CLK] = &gcc_pcie_link_xo_clk.clkr, + [GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] = &gcc_pcie_noc_async_bridge_clk.clkr, + [GCC_PCIE_NOC_CNOC_SF_QX_CLK] = &gcc_pcie_noc_cnoc_sf_qx_clk.clkr, + [GCC_PCIE_NOC_M_CFG_CLK] = &gcc_pcie_noc_m_cfg_clk.clkr, + [GCC_PCIE_NOC_M_PDB_CLK] = &gcc_pcie_noc_m_pdb_clk.clkr, + [GCC_PCIE_NOC_MSTR_AXI_CLK] = &gcc_pcie_noc_mstr_axi_clk.clkr, + [GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr, + [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr, + [GCC_PCIE_NOC_REFGEN_CLK] = &gcc_pcie_noc_refgen_clk.clkr, + [GCC_PCIE_NOC_REFGEN_CLK_SRC] = &gcc_pcie_noc_refgen_clk_src.clkr, + [GCC_PCIE_NOC_S_CFG_CLK] = &gcc_pcie_noc_s_cfg_clk.clkr, + [GCC_PCIE_NOC_S_PDB_CLK] = &gcc_pcie_noc_s_pdb_clk.clkr, + [GCC_PCIE_NOC_SAFETY_CLK] = &gcc_pcie_noc_safety_clk.clkr, + [GCC_PCIE_NOC_SAFETY_CLK_SRC] = &gcc_pcie_noc_safety_clk_src.clkr, + [GCC_PCIE_NOC_SLAVE_AXI_CLK] = &gcc_pcie_noc_slave_axi_clk.clkr, + [GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr, + [GCC_PCIE_NOC_XO_CLK] = &gcc_pcie_noc_xo_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, + [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, + [GCC_QUPV3_WRAP3_M_CLK] = &gcc_qupv3_wrap3_m_clk.clkr, + [GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr, + [GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr, + [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, + [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, + [GCC_QUPV3_WRAP3_S_AHB_CLK] = &gcc_qupv3_wrap3_s_ahb_clk.clkr, + [GCC_SMMU_PCIE_QTC_VOTE_CLK] = &gcc_smmu_pcie_qtc_vote_clk.clkr, +}; + +static struct gdsc *gcc_nord_gdscs[] = { + [GCC_PCIE_A_GDSC] = &gcc_pcie_a_gdsc, + [GCC_PCIE_A_PHY_GDSC] = &gcc_pcie_a_phy_gdsc, + [GCC_PCIE_B_GDSC] = &gcc_pcie_b_gdsc, + [GCC_PCIE_B_PHY_GDSC] = &gcc_pcie_b_phy_gdsc, + [GCC_PCIE_C_GDSC] = &gcc_pcie_c_gdsc, + [GCC_PCIE_C_PHY_GDSC] = &gcc_pcie_c_phy_gdsc, + [GCC_PCIE_D_GDSC] = &gcc_pcie_d_gdsc, + [GCC_PCIE_D_PHY_GDSC] = &gcc_pcie_d_phy_gdsc, + [GCC_PCIE_NOC_GDSC] = &gcc_pcie_noc_gdsc, +}; + +static const struct qcom_reset_map gcc_nord_resets[] = { + [GCC_PCIE_A_BCR] = { 0x49000 }, + [GCC_PCIE_A_LINK_DOWN_BCR] = { 0xb9000 }, + [GCC_PCIE_A_NOCSR_COM_PHY_BCR] = { 0xb900c }, + [GCC_PCIE_A_PHY_BCR] = { 0x4d000 }, + [GCC_PCIE_A_PHY_CFG_AHB_BCR] = { 0xb9014 }, + [GCC_PCIE_A_PHY_COM_BCR] = { 0xb9018 }, + [GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR] = { 0xb9010 }, + [GCC_PCIE_B_BCR] = { 0x4a000 }, + [GCC_PCIE_B_LINK_DOWN_BCR] = { 0xba000 }, + [GCC_PCIE_B_NOCSR_COM_PHY_BCR] = { 0xba008 }, + [GCC_PCIE_B_PHY_BCR] = { 0x4e000 }, + [GCC_PCIE_B_PHY_CFG_AHB_BCR] = { 0xba010 }, + [GCC_PCIE_B_PHY_COM_BCR] = { 0xba014 }, + [GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR] = { 0xba00c }, + [GCC_PCIE_C_BCR] = { 0x4b000 }, + [GCC_PCIE_C_LINK_DOWN_BCR] = { 0xbb07c }, + [GCC_PCIE_C_NOCSR_COM_PHY_BCR] = { 0xbb084 }, + [GCC_PCIE_C_PHY_BCR] = { 0x4f000 }, + [GCC_PCIE_C_PHY_CFG_AHB_BCR] = { 0xbb08c }, + [GCC_PCIE_C_PHY_COM_BCR] = { 0xbb090 }, + [GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR] = { 0xbb088 }, + [GCC_PCIE_D_BCR] = { 0x4c000 }, + [GCC_PCIE_D_LINK_DOWN_BCR] = { 0xbc000 }, + [GCC_PCIE_D_NOCSR_COM_PHY_BCR] = { 0xbc008 }, + [GCC_PCIE_D_PHY_BCR] = { 0x50000 }, + [GCC_PCIE_D_PHY_CFG_AHB_BCR] = { 0xbc010 }, + [GCC_PCIE_D_PHY_COM_BCR] = { 0xbc014 }, + [GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR] = { 0xbc00c }, + [GCC_PCIE_NOC_BCR] = { 0x52000 }, + [GCC_PDM_BCR] = { 0x1a000 }, + [GCC_QUPV3_WRAPPER_3_BCR] = { 0x23000 }, + [GCC_TCSR_PCIE_BCR] = { 0xb901c }, +}; + +static const struct clk_rcg_dfs_data gcc_nord_dfs_clocks[] = { + DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src), +}; + +static const struct regmap_config gcc_nord_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f41f0, + .fast_io = true, +}; + +static struct qcom_cc_driver_data gcc_nord_driver_data = { + .dfs_rcgs = gcc_nord_dfs_clocks, + .num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks), +}; + +static const struct qcom_cc_desc gcc_nord_desc = { + .config = &gcc_nord_regmap_config, + .clks = gcc_nord_clocks, + .num_clks = ARRAY_SIZE(gcc_nord_clocks), + .resets = gcc_nord_resets, + .num_resets = ARRAY_SIZE(gcc_nord_resets), + .gdscs = gcc_nord_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_nord_gdscs), + .use_rpm = true, + .driver_data = &gcc_nord_driver_data, +}; + +static const struct of_device_id gcc_nord_match_table[] = { + { .compatible = "qcom,nord-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_nord_match_table); + +static int gcc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_nord_desc); +} + +static struct platform_driver gcc_nord_driver = { + .probe = gcc_nord_probe, + .driver = { + .name = "gcc-nord", + .of_match_table = gcc_nord_match_table, + }, +}; + +static int __init gcc_nord_init(void) +{ + return platform_driver_register(&gcc_nord_driver); +} +subsys_initcall(gcc_nord_init); + +static void __exit gcc_nord_exit(void) +{ + platform_driver_unregister(&gcc_nord_driver); +} +module_exit(gcc_nord_exit); + +MODULE_DESCRIPTION("QTI GCC NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c new file mode 100644 index 0000000000000..1aa24e2784e53 --- /dev/null +++ b/drivers/clk/qcom/negcc-nord.c @@ -0,0 +1,1987 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_UFS_PHY_RX_SYMBOL_0_CLK, + DT_UFS_PHY_RX_SYMBOL_1_CLK, + DT_UFS_PHY_TX_SYMBOL_0_CLK, + DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, + DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_NE_GCC_GPLL0_OUT_EVEN, + P_NE_GCC_GPLL0_OUT_MAIN, + P_NE_GCC_GPLL2_OUT_MAIN, + P_SLEEP_CLK, + P_UFS_PHY_RX_SYMBOL_0_CLK, + P_UFS_PHY_RX_SYMBOL_1_CLK, + P_UFS_PHY_TX_SYMBOL_0_CLK, + P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, + P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, +}; + +static struct clk_alpha_pll ne_gcc_gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gpll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_ne_gcc_gpll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv ne_gcc_gpll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_ne_gcc_gpll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_ne_gcc_gpll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gpll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static struct clk_alpha_pll ne_gcc_gpll2 = { + .offset = 0x2000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(2), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gpll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct parent_map ne_gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &ne_gcc_gpll0.clkr.hw }, +}; + +static const struct parent_map ne_gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_NE_GCC_GPLL0_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &ne_gcc_gpll0.clkr.hw }, + { .hw = &ne_gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map ne_gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_NE_GCC_GPLL2_OUT_MAIN, 3 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &ne_gcc_gpll0.clkr.hw }, + { .hw = &ne_gcc_gpll2.clkr.hw }, +}; + +static const struct parent_map ne_gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map ne_gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &ne_gcc_gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map ne_gcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_5[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map ne_gcc_parent_map_6[] = { + { P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_6[] = { + { .index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map ne_gcc_parent_map_7[] = { + { P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_7[] = { + { .index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK }, + { .index = DT_BI_TCXO }, +}; + +static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src = { + .reg = 0x33068, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_rx_symbol_0_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_1_clk_src = { + .reg = 0x330f0, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_rx_symbol_1_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src = { + .reg = 0x33058, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_tx_symbol_0_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_mux ne_gcc_usb3_prim_phy_pipe_clk_src = { + .reg = 0x2a078, + .shift = 0, + .width = 2, + .parent_map = ne_gcc_parent_map_6, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_prim_phy_pipe_clk_src", + .parent_data = ne_gcc_parent_data_6, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_6), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux ne_gcc_usb3_sec_phy_pipe_clk_src = { + .reg = 0x2c078, + .shift = 0, + .width = 2, + .parent_map = ne_gcc_parent_map_7, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_sec_phy_pipe_clk_src", + .parent_data = ne_gcc_parent_data_7, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_7), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_gp1_clk_src[] = { + F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_gp1_clk_src = { + .cmd_rcgr = 0x21004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_4, + .freq_tbl = ftbl_ne_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gp1_clk_src", + .parent_data = ne_gcc_parent_data_4, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_gp2_clk_src = { + .cmd_rcgr = 0x22004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_4, + .freq_tbl = ftbl_ne_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gp2_clk_src", + .parent_data = ne_gcc_parent_data_4, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s0_clk_src[] = { + F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), + F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), + F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), + F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), + F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), + F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), + F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), + F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 64, 375), + F(112000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 14, 75), + F(117964800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625), + F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s0_clk_src_init = { + .name = "ne_gcc_qupv3_wrap2_s0_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s0_clk_src = { + .cmd_rcgr = 0x3816c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &ne_gcc_qupv3_wrap2_s0_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s1_clk_src_init = { + .name = "ne_gcc_qupv3_wrap2_s1_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s1_clk_src = { + .cmd_rcgr = 0x382a8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &ne_gcc_qupv3_wrap2_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s2_clk_src[] = { + F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), + F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), + F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), + F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), + F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), + F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), + F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), + F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s2_clk_src_init = { + .name = "ne_gcc_qupv3_wrap2_s2_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s2_clk_src = { + .cmd_rcgr = 0x383e4, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &ne_gcc_qupv3_wrap2_s2_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s3_clk_src_init = { + .name = "ne_gcc_qupv3_wrap2_s3_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s3_clk_src = { + .cmd_rcgr = 0x38520, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &ne_gcc_qupv3_wrap2_s3_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s4_clk_src_init = { + .name = "ne_gcc_qupv3_wrap2_s4_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s4_clk_src = { + .cmd_rcgr = 0x3865c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &ne_gcc_qupv3_wrap2_s4_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s5_clk_src_init = { + .name = "ne_gcc_qupv3_wrap2_s5_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s5_clk_src = { + .cmd_rcgr = 0x38798, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &ne_gcc_qupv3_wrap2_s5_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s6_clk_src_init = { + .name = "ne_gcc_qupv3_wrap2_s6_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s6_clk_src = { + .cmd_rcgr = 0x388d4, + .mnd_width = 16, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &ne_gcc_qupv3_wrap2_s6_clk_src_init, +}; + +static const struct freq_tbl ftbl_ne_gcc_sdcc4_apps_clk_src[] = { + F(37500000, P_NE_GCC_GPLL0_OUT_MAIN, 16, 0, 0), + F(50000000, P_NE_GCC_GPLL0_OUT_MAIN, 12, 0, 0), + F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_sdcc4_apps_clk_src = { + .cmd_rcgr = 0x1801c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_sdcc4_apps_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_sdcc4_apps_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_ufs_phy_axi_clk_src[] = { + F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + F(201500000, P_NE_GCC_GPLL2_OUT_MAIN, 4, 0, 0), + F(300000000, P_NE_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + F(403000000, P_NE_GCC_GPLL2_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_ufs_phy_axi_clk_src = { + .cmd_rcgr = 0x33034, + .mnd_width = 8, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_2, + .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_axi_clk_src", + .parent_data = ne_gcc_parent_data_2, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_ufs_phy_ice_core_clk_src = { + .cmd_rcgr = 0x3308c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_2, + .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_ice_core_clk_src", + .parent_data = ne_gcc_parent_data_2, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_ufs_phy_phy_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_ufs_phy_phy_aux_clk_src = { + .cmd_rcgr = 0x330c0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_5, + .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_phy_aux_clk_src", + .parent_data = ne_gcc_parent_data_5, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_ufs_phy_unipro_core_clk_src = { + .cmd_rcgr = 0x330a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_2, + .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_unipro_core_clk_src", + .parent_data = ne_gcc_parent_data_2, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_usb20_master_clk_src[] = { + F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_usb20_master_clk_src = { + .cmd_rcgr = 0x31030, + .mnd_width = 8, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_usb20_master_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb20_master_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb20_mock_utmi_clk_src = { + .cmd_rcgr = 0x31048, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb20_mock_utmi_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_usb31_prim_master_clk_src[] = { + F(85714286, P_NE_GCC_GPLL0_OUT_MAIN, 7, 0, 0), + F(133333333, P_NE_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_NE_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_usb31_prim_master_clk_src = { + .cmd_rcgr = 0x2a038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_1, + .freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_prim_master_clk_src", + .parent_data = ne_gcc_parent_data_1, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb31_prim_mock_utmi_clk_src = { + .cmd_rcgr = 0x2a050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_prim_mock_utmi_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb31_sec_master_clk_src = { + .cmd_rcgr = 0x2c038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_sec_master_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb31_sec_mock_utmi_clk_src = { + .cmd_rcgr = 0x2c050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_0, + .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_sec_mock_utmi_clk_src", + .parent_data = ne_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb3_prim_phy_aux_clk_src = { + .cmd_rcgr = 0x2a07c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_3, + .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_prim_phy_aux_clk_src", + .parent_data = ne_gcc_parent_data_3, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb3_sec_phy_aux_clk_src = { + .cmd_rcgr = 0x2c07c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ne_gcc_parent_map_3, + .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_sec_phy_aux_clk_src", + .parent_data = ne_gcc_parent_data_3, + .num_parents = ARRAY_SIZE(ne_gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div ne_gcc_usb20_mock_utmi_postdiv_clk_src = { + .reg = 0x31060, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb20_mock_utmi_postdiv_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb20_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src = { + .reg = 0x2a068, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src = { + .reg = 0x2c068, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch ne_gcc_aggre_noc_ufs_phy_axi_clk = { + .halt_reg = 0x330f4, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x330f4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x330f4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_aggre_noc_ufs_phy_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_aggre_noc_usb2_axi_clk = { + .halt_reg = 0x31068, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x31068, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x31068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_aggre_noc_usb2_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_aggre_noc_usb3_prim_axi_clk = { + .halt_reg = 0x2a098, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2a098, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2a098, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_aggre_noc_usb3_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_aggre_noc_usb3_sec_axi_clk = { + .halt_reg = 0x2c098, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2c098, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2c098, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_aggre_noc_usb3_sec_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ahb2phy_clk = { + .halt_reg = 0x30004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x30004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x30004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ahb2phy_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_cnoc_usb2_axi_clk = { + .halt_reg = 0x31064, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x31064, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x31064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_cnoc_usb2_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_cnoc_usb3_prim_axi_clk = { + .halt_reg = 0x2a094, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2a094, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2a094, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_cnoc_usb3_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_cnoc_usb3_sec_axi_clk = { + .halt_reg = 0x2c094, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2c094, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2c094, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_cnoc_usb3_sec_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_frq_measure_ref_clk = { + .halt_reg = 0x20008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x20008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_frq_measure_ref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gp1_clk = { + .halt_reg = 0x21000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x21000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gp1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gp2_clk = { + .halt_reg = 0x22000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x22000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gp2_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_cfg_clk = { + .halt_reg = 0x34004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x34004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x34004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gpu_2_cfg_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gpu_2_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gpu_2_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_gpll0_out_even.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_hscnoc_gfx_clk = { + .halt_reg = 0x34014, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x34014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x34014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gpu_2_hscnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_smmu_vote_clk = { + .halt_reg = 0x57028, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_gpu_2_smmu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_core_2x_clk = { + .halt_reg = 0x38020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(1), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_core_clk = { + .halt_reg = 0x3800c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_m_ahb_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x38004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(30), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s0_clk = { + .halt_reg = 0x3815c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(2), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_s0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s1_clk = { + .halt_reg = 0x38298, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(3), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_s1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s2_clk = { + .halt_reg = 0x383d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(4), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_s2_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s3_clk = { + .halt_reg = 0x38510, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(5), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_s3_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s4_clk = { + .halt_reg = 0x3864c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_s4_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s5_clk = { + .halt_reg = 0x38788, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(7), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_s5_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s6_clk = { + .halt_reg = 0x388c4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_s6_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s_ahb_clk = { + .halt_reg = 0x38008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x38008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(31), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_qupv3_wrap2_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_sdcc4_apps_clk = { + .halt_reg = 0x18004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x18004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_sdcc4_apps_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_sdcc4_axi_clk = { + .halt_reg = 0x18014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x18014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_sdcc4_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_ahb_clk = { + .halt_reg = 0x33028, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x33028, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x33028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_axi_clk = { + .halt_reg = 0x33018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x33018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x33018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_ice_core_clk = { + .halt_reg = 0x3307c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x3307c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x3307c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_ice_core_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_phy_aux_clk = { + .halt_reg = 0x330bc, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x330bc, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x330bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_rx_symbol_0_clk = { + .halt_reg = 0x33030, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x33030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_rx_symbol_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_rx_symbol_1_clk = { + .halt_reg = 0x330d8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x330d8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_rx_symbol_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_tx_symbol_0_clk = { + .halt_reg = 0x3302c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x3302c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_tx_symbol_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_unipro_core_clk = { + .halt_reg = 0x3306c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x3306c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x3306c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_ufs_phy_unipro_core_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb20_master_clk = { + .halt_reg = 0x31018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb20_master_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb20_mock_utmi_clk = { + .halt_reg = 0x3102c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3102c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb20_mock_utmi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb20_sleep_clk = { + .halt_reg = 0x31028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb20_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_atb_clk = { + .halt_reg = 0x2a018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x2a018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_prim_atb_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_eud_ahb_clk = { + .halt_reg = 0x2a02c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2a02c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2a02c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_prim_eud_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_master_clk = { + .halt_reg = 0x2a01c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_prim_master_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_mock_utmi_clk = { + .halt_reg = 0x2a034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_prim_mock_utmi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_sleep_clk = { + .halt_reg = 0x2a030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_prim_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_atb_clk = { + .halt_reg = 0x2c018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x2c018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_sec_atb_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_eud_ahb_clk = { + .halt_reg = 0x2c02c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2c02c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2c02c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_sec_eud_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_master_clk = { + .halt_reg = 0x2c01c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_sec_master_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_mock_utmi_clk = { + .halt_reg = 0x2c034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_sec_mock_utmi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_sleep_clk = { + .halt_reg = 0x2c030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb31_sec_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_prim_phy_aux_clk = { + .halt_reg = 0x2a06c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a06c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_prim_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk = { + .halt_reg = 0x2a070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_prim_phy_com_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk = { + .halt_reg = 0x2a074, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2a074, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2a074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_prim_phy_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_sec_phy_aux_clk = { + .halt_reg = 0x2c06c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c06c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_sec_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk = { + .halt_reg = 0x2c070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_sec_phy_com_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk = { + .halt_reg = 0x2c074, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2c074, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2c074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ne_gcc_usb3_sec_phy_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc ne_gcc_ufs_mem_phy_gdsc = { + .gdscr = 0x32000, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "ne_gcc_ufs_mem_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_ufs_phy_gdsc = { + .gdscr = 0x33004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "ne_gcc_ufs_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb20_prim_gdsc = { + .gdscr = 0x31004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "ne_gcc_usb20_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb31_prim_gdsc = { + .gdscr = 0x2a004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "ne_gcc_usb31_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb31_sec_gdsc = { + .gdscr = 0x2c004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "ne_gcc_usb31_sec_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb3_phy_gdsc = { + .gdscr = 0x2b00c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "ne_gcc_usb3_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb3_sec_phy_gdsc = { + .gdscr = 0x2d00c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "ne_gcc_usb3_sec_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *ne_gcc_nord_clocks[] = { + [NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK] = &ne_gcc_aggre_noc_ufs_phy_axi_clk.clkr, + [NE_GCC_AGGRE_NOC_USB2_AXI_CLK] = &ne_gcc_aggre_noc_usb2_axi_clk.clkr, + [NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK] = &ne_gcc_aggre_noc_usb3_prim_axi_clk.clkr, + [NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK] = &ne_gcc_aggre_noc_usb3_sec_axi_clk.clkr, + [NE_GCC_AHB2PHY_CLK] = &ne_gcc_ahb2phy_clk.clkr, + [NE_GCC_CNOC_USB2_AXI_CLK] = &ne_gcc_cnoc_usb2_axi_clk.clkr, + [NE_GCC_CNOC_USB3_PRIM_AXI_CLK] = &ne_gcc_cnoc_usb3_prim_axi_clk.clkr, + [NE_GCC_CNOC_USB3_SEC_AXI_CLK] = &ne_gcc_cnoc_usb3_sec_axi_clk.clkr, + [NE_GCC_FRQ_MEASURE_REF_CLK] = &ne_gcc_frq_measure_ref_clk.clkr, + [NE_GCC_GP1_CLK] = &ne_gcc_gp1_clk.clkr, + [NE_GCC_GP1_CLK_SRC] = &ne_gcc_gp1_clk_src.clkr, + [NE_GCC_GP2_CLK] = &ne_gcc_gp2_clk.clkr, + [NE_GCC_GP2_CLK_SRC] = &ne_gcc_gp2_clk_src.clkr, + [NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr, + [NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr, + [NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr, + [NE_GCC_GPU_2_CFG_CLK] = &ne_gcc_gpu_2_cfg_clk.clkr, + [NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr, + [NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr, + [NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr, + [NE_GCC_GPU_2_SMMU_VOTE_CLK] = &ne_gcc_gpu_2_smmu_vote_clk.clkr, + [NE_GCC_QUPV3_WRAP2_CORE_2X_CLK] = &ne_gcc_qupv3_wrap2_core_2x_clk.clkr, + [NE_GCC_QUPV3_WRAP2_CORE_CLK] = &ne_gcc_qupv3_wrap2_core_clk.clkr, + [NE_GCC_QUPV3_WRAP2_M_AHB_CLK] = &ne_gcc_qupv3_wrap2_m_ahb_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S0_CLK] = &ne_gcc_qupv3_wrap2_s0_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S0_CLK_SRC] = &ne_gcc_qupv3_wrap2_s0_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S1_CLK] = &ne_gcc_qupv3_wrap2_s1_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S1_CLK_SRC] = &ne_gcc_qupv3_wrap2_s1_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S2_CLK] = &ne_gcc_qupv3_wrap2_s2_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S2_CLK_SRC] = &ne_gcc_qupv3_wrap2_s2_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S3_CLK] = &ne_gcc_qupv3_wrap2_s3_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S3_CLK_SRC] = &ne_gcc_qupv3_wrap2_s3_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S4_CLK] = &ne_gcc_qupv3_wrap2_s4_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S4_CLK_SRC] = &ne_gcc_qupv3_wrap2_s4_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S5_CLK] = &ne_gcc_qupv3_wrap2_s5_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S5_CLK_SRC] = &ne_gcc_qupv3_wrap2_s5_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S6_CLK] = &ne_gcc_qupv3_wrap2_s6_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S6_CLK_SRC] = &ne_gcc_qupv3_wrap2_s6_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S_AHB_CLK] = &ne_gcc_qupv3_wrap2_s_ahb_clk.clkr, + [NE_GCC_SDCC4_APPS_CLK] = &ne_gcc_sdcc4_apps_clk.clkr, + [NE_GCC_SDCC4_APPS_CLK_SRC] = &ne_gcc_sdcc4_apps_clk_src.clkr, + [NE_GCC_SDCC4_AXI_CLK] = &ne_gcc_sdcc4_axi_clk.clkr, + [NE_GCC_UFS_PHY_AHB_CLK] = &ne_gcc_ufs_phy_ahb_clk.clkr, + [NE_GCC_UFS_PHY_AXI_CLK] = &ne_gcc_ufs_phy_axi_clk.clkr, + [NE_GCC_UFS_PHY_AXI_CLK_SRC] = &ne_gcc_ufs_phy_axi_clk_src.clkr, + [NE_GCC_UFS_PHY_ICE_CORE_CLK] = &ne_gcc_ufs_phy_ice_core_clk.clkr, + [NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &ne_gcc_ufs_phy_ice_core_clk_src.clkr, + [NE_GCC_UFS_PHY_PHY_AUX_CLK] = &ne_gcc_ufs_phy_phy_aux_clk.clkr, + [NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &ne_gcc_ufs_phy_phy_aux_clk_src.clkr, + [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_rx_symbol_0_clk.clkr, + [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr, + [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &ne_gcc_ufs_phy_rx_symbol_1_clk.clkr, + [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr, + [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_tx_symbol_0_clk.clkr, + [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr, + [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK] = &ne_gcc_ufs_phy_unipro_core_clk.clkr, + [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &ne_gcc_ufs_phy_unipro_core_clk_src.clkr, + [NE_GCC_USB20_MASTER_CLK] = &ne_gcc_usb20_master_clk.clkr, + [NE_GCC_USB20_MASTER_CLK_SRC] = &ne_gcc_usb20_master_clk_src.clkr, + [NE_GCC_USB20_MOCK_UTMI_CLK] = &ne_gcc_usb20_mock_utmi_clk.clkr, + [NE_GCC_USB20_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb20_mock_utmi_clk_src.clkr, + [NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr, + [NE_GCC_USB20_SLEEP_CLK] = &ne_gcc_usb20_sleep_clk.clkr, + [NE_GCC_USB31_PRIM_ATB_CLK] = &ne_gcc_usb31_prim_atb_clk.clkr, + [NE_GCC_USB31_PRIM_EUD_AHB_CLK] = &ne_gcc_usb31_prim_eud_ahb_clk.clkr, + [NE_GCC_USB31_PRIM_MASTER_CLK] = &ne_gcc_usb31_prim_master_clk.clkr, + [NE_GCC_USB31_PRIM_MASTER_CLK_SRC] = &ne_gcc_usb31_prim_master_clk_src.clkr, + [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK] = &ne_gcc_usb31_prim_mock_utmi_clk.clkr, + [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr, + [NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = + &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr, + [NE_GCC_USB31_PRIM_SLEEP_CLK] = &ne_gcc_usb31_prim_sleep_clk.clkr, + [NE_GCC_USB31_SEC_ATB_CLK] = &ne_gcc_usb31_sec_atb_clk.clkr, + [NE_GCC_USB31_SEC_EUD_AHB_CLK] = &ne_gcc_usb31_sec_eud_ahb_clk.clkr, + [NE_GCC_USB31_SEC_MASTER_CLK] = &ne_gcc_usb31_sec_master_clk.clkr, + [NE_GCC_USB31_SEC_MASTER_CLK_SRC] = &ne_gcc_usb31_sec_master_clk_src.clkr, + [NE_GCC_USB31_SEC_MOCK_UTMI_CLK] = &ne_gcc_usb31_sec_mock_utmi_clk.clkr, + [NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr, + [NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = + &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr, + [NE_GCC_USB31_SEC_SLEEP_CLK] = &ne_gcc_usb31_sec_sleep_clk.clkr, + [NE_GCC_USB3_PRIM_PHY_AUX_CLK] = &ne_gcc_usb3_prim_phy_aux_clk.clkr, + [NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_prim_phy_aux_clk_src.clkr, + [NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &ne_gcc_usb3_prim_phy_com_aux_clk.clkr, + [NE_GCC_USB3_PRIM_PHY_PIPE_CLK] = &ne_gcc_usb3_prim_phy_pipe_clk.clkr, + [NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr, + [NE_GCC_USB3_SEC_PHY_AUX_CLK] = &ne_gcc_usb3_sec_phy_aux_clk.clkr, + [NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_sec_phy_aux_clk_src.clkr, + [NE_GCC_USB3_SEC_PHY_COM_AUX_CLK] = &ne_gcc_usb3_sec_phy_com_aux_clk.clkr, + [NE_GCC_USB3_SEC_PHY_PIPE_CLK] = &ne_gcc_usb3_sec_phy_pipe_clk.clkr, + [NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr, +}; + +static struct gdsc *ne_gcc_nord_gdscs[] = { + [NE_GCC_UFS_MEM_PHY_GDSC] = &ne_gcc_ufs_mem_phy_gdsc, + [NE_GCC_UFS_PHY_GDSC] = &ne_gcc_ufs_phy_gdsc, + [NE_GCC_USB20_PRIM_GDSC] = &ne_gcc_usb20_prim_gdsc, + [NE_GCC_USB31_PRIM_GDSC] = &ne_gcc_usb31_prim_gdsc, + [NE_GCC_USB31_SEC_GDSC] = &ne_gcc_usb31_sec_gdsc, + [NE_GCC_USB3_PHY_GDSC] = &ne_gcc_usb3_phy_gdsc, + [NE_GCC_USB3_SEC_PHY_GDSC] = &ne_gcc_usb3_sec_phy_gdsc, +}; + +static const struct qcom_reset_map ne_gcc_nord_resets[] = { + [NE_GCC_GPU_2_BCR] = { 0x34000 }, + [NE_GCC_QUPV3_WRAPPER_2_BCR] = { 0x38000 }, + [NE_GCC_SDCC4_BCR] = { 0x18000 }, + [NE_GCC_UFS_PHY_BCR] = { 0x33000 }, + [NE_GCC_USB20_PRIM_BCR] = { 0x31000 }, + [NE_GCC_USB31_PRIM_BCR] = { 0x2a000 }, + [NE_GCC_USB31_SEC_BCR] = { 0x2c000 }, + [NE_GCC_USB3_DP_PHY_PRIM_BCR] = { 0x2b008 }, + [NE_GCC_USB3_DP_PHY_SEC_BCR] = { 0x2d008 }, + [NE_GCC_USB3_PHY_PRIM_BCR] = { 0x2b000 }, + [NE_GCC_USB3_PHY_SEC_BCR] = { 0x2d000 }, + [NE_GCC_USB3PHY_PHY_PRIM_BCR] = { 0x2b004 }, + [NE_GCC_USB3PHY_PHY_SEC_BCR] = { 0x2d004 }, +}; + +static const struct clk_rcg_dfs_data ne_gcc_nord_dfs_clocks[] = { + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s0_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s1_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s2_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s3_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s4_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s5_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s6_clk_src), +}; + +static const struct regmap_config ne_gcc_nord_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf41f0, + .fast_io = true, +}; + +static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap) +{ + /* FORCE_MEM_CORE_ON for ne_gcc_ufs_phy_ice_core_clk and ne_gcc_ufs_phy_axi_clk */ + qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_ice_core_clk, true); + qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true); +} + +static struct qcom_cc_driver_data ne_gcc_nord_driver_data = { + .dfs_rcgs = ne_gcc_nord_dfs_clocks, + .num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks), + .clk_regs_configure = clk_nord_regs_configure, +}; + +static const struct qcom_cc_desc ne_gcc_nord_desc = { + .config = &ne_gcc_nord_regmap_config, + .clks = ne_gcc_nord_clocks, + .num_clks = ARRAY_SIZE(ne_gcc_nord_clocks), + .resets = ne_gcc_nord_resets, + .num_resets = ARRAY_SIZE(ne_gcc_nord_resets), + .gdscs = ne_gcc_nord_gdscs, + .num_gdscs = ARRAY_SIZE(ne_gcc_nord_gdscs), + .driver_data = &ne_gcc_nord_driver_data, +}; + +static const struct of_device_id ne_gcc_nord_match_table[] = { + { .compatible = "qcom,nord-negcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, ne_gcc_nord_match_table); + +static int ne_gcc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &ne_gcc_nord_desc); +} + +static struct platform_driver ne_gcc_nord_driver = { + .probe = ne_gcc_nord_probe, + .driver = { + .name = "negcc-nord", + .of_match_table = ne_gcc_nord_match_table, + }, +}; + +module_platform_driver(ne_gcc_nord_driver); + +MODULE_DESCRIPTION("QTI NEGCC NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/nwgcc-nord.c b/drivers/clk/qcom/nwgcc-nord.c new file mode 100644 index 0000000000000..163ab63c872bc --- /dev/null +++ b/drivers/clk/qcom/nwgcc-nord.c @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_NW_GCC_GPLL0_OUT_EVEN, + P_NW_GCC_GPLL0_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll nw_gcc_gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_nw_gcc_gpll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv nw_gcc_gpll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_nw_gcc_gpll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_nw_gcc_gpll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &nw_gcc_gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map nw_gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_NW_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_NW_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data nw_gcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &nw_gcc_gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, + { .hw = &nw_gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct freq_tbl ftbl_nw_gcc_gp1_clk_src[] = { + F(60000000, P_NW_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + F(100000000, P_NW_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_NW_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 nw_gcc_gp1_clk_src = { + .cmd_rcgr = 0x20004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = nw_gcc_parent_map_0, + .freq_tbl = ftbl_nw_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gp1_clk_src", + .parent_data = nw_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(nw_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 nw_gcc_gp2_clk_src = { + .cmd_rcgr = 0x21004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = nw_gcc_parent_map_0, + .freq_tbl = ftbl_nw_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gp2_clk_src", + .parent_data = nw_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(nw_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch nw_gcc_acmu_mux_clk = { + .halt_reg = 0x1f01c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_acmu_mux_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_camera_hf_axi_clk = { + .halt_reg = 0x16008, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x16008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x16008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_camera_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_camera_sf_axi_clk = { + .halt_reg = 0x1601c, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x1601c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1601c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_camera_sf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_camera_trig_clk = { + .halt_reg = 0x16034, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x16034, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x16034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_camera_trig_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_disp_0_hf_axi_clk = { + .halt_reg = 0x18008, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x18008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x18008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_disp_0_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_disp_0_trig_clk = { + .halt_reg = 0x1801c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1801c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1801c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_disp_0_trig_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_disp_1_hf_axi_clk = { + .halt_reg = 0x19008, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x19008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x19008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_disp_1_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_disp_1_trig_clk = { + .halt_reg = 0x1901c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1901c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1901c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_disp_1_trig_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_dprx0_axi_hf_clk = { + .halt_reg = 0x29004, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x29004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x29004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_dprx0_axi_hf_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_dprx1_axi_hf_clk = { + .halt_reg = 0x2a004, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x2a004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2a004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_dprx1_axi_hf_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_eva_axi0_clk = { + .halt_reg = 0x1b008, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x1b008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1b008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_eva_axi0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_eva_axi0c_clk = { + .halt_reg = 0x1b01c, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x1b01c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1b01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_eva_axi0c_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_eva_trig_clk = { + .halt_reg = 0x1b028, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1b028, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1b028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_eva_trig_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_frq_measure_ref_clk = { + .halt_reg = 0x1f008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_frq_measure_ref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gp1_clk = { + .halt_reg = 0x20000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x20000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gp1_clk", + .parent_hws = (const struct clk_hw*[]) { + &nw_gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gp2_clk = { + .halt_reg = 0x21000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x21000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gp2_clk", + .parent_hws = (const struct clk_hw*[]) { + &nw_gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_2_gpll0_clk_src = { + .halt_reg = 0x24150, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x24150, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x76000, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpu_2_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nw_gcc_gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_2_gpll0_div_clk_src = { + .halt_reg = 0x24158, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x24158, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x76000, + .enable_mask = BIT(7), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpu_2_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nw_gcc_gpll0_out_even.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_2_hscnoc_gfx_clk = { + .halt_reg = 0x2400c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2400c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2400c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpu_2_hscnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_gpll0_clk_src = { + .halt_reg = 0x23150, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x23150, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x76000, + .enable_mask = BIT(4), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nw_gcc_gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_gpll0_div_clk_src = { + .halt_reg = 0x23158, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x23158, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x76000, + .enable_mask = BIT(5), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpu_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &nw_gcc_gpll0_out_even.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_hscnoc_gfx_clk = { + .halt_reg = 0x2300c, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x2300c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2300c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpu_hscnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_smmu_vote_clk = { + .halt_reg = 0x86038, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x86038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_gpu_smmu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_hscnoc_gpu_2_axi_clk = { + .halt_reg = 0x24160, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x24160, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x24160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_hscnoc_gpu_2_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_hscnoc_gpu_axi_clk = { + .halt_reg = 0x23160, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x23160, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x23160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_hscnoc_gpu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_mmu_1_tcu_vote_clk = { + .halt_reg = 0x86040, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x86040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_mmu_1_tcu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_video_axi0_clk = { + .halt_reg = 0x1a008, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x1a008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_video_axi0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_video_axi0c_clk = { + .halt_reg = 0x1a01c, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x1a01c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_video_axi0c_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_video_axi1_clk = { + .halt_reg = 0x1a030, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x1a030, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nw_gcc_video_axi1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *nw_gcc_nord_clocks[] = { + [NW_GCC_ACMU_MUX_CLK] = &nw_gcc_acmu_mux_clk.clkr, + [NW_GCC_CAMERA_HF_AXI_CLK] = &nw_gcc_camera_hf_axi_clk.clkr, + [NW_GCC_CAMERA_SF_AXI_CLK] = &nw_gcc_camera_sf_axi_clk.clkr, + [NW_GCC_CAMERA_TRIG_CLK] = &nw_gcc_camera_trig_clk.clkr, + [NW_GCC_DISP_0_HF_AXI_CLK] = &nw_gcc_disp_0_hf_axi_clk.clkr, + [NW_GCC_DISP_0_TRIG_CLK] = &nw_gcc_disp_0_trig_clk.clkr, + [NW_GCC_DISP_1_HF_AXI_CLK] = &nw_gcc_disp_1_hf_axi_clk.clkr, + [NW_GCC_DISP_1_TRIG_CLK] = &nw_gcc_disp_1_trig_clk.clkr, + [NW_GCC_DPRX0_AXI_HF_CLK] = &nw_gcc_dprx0_axi_hf_clk.clkr, + [NW_GCC_DPRX1_AXI_HF_CLK] = &nw_gcc_dprx1_axi_hf_clk.clkr, + [NW_GCC_EVA_AXI0_CLK] = &nw_gcc_eva_axi0_clk.clkr, + [NW_GCC_EVA_AXI0C_CLK] = &nw_gcc_eva_axi0c_clk.clkr, + [NW_GCC_EVA_TRIG_CLK] = &nw_gcc_eva_trig_clk.clkr, + [NW_GCC_FRQ_MEASURE_REF_CLK] = &nw_gcc_frq_measure_ref_clk.clkr, + [NW_GCC_GP1_CLK] = &nw_gcc_gp1_clk.clkr, + [NW_GCC_GP1_CLK_SRC] = &nw_gcc_gp1_clk_src.clkr, + [NW_GCC_GP2_CLK] = &nw_gcc_gp2_clk.clkr, + [NW_GCC_GP2_CLK_SRC] = &nw_gcc_gp2_clk_src.clkr, + [NW_GCC_GPLL0] = &nw_gcc_gpll0.clkr, + [NW_GCC_GPLL0_OUT_EVEN] = &nw_gcc_gpll0_out_even.clkr, + [NW_GCC_GPU_2_GPLL0_CLK_SRC] = &nw_gcc_gpu_2_gpll0_clk_src.clkr, + [NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &nw_gcc_gpu_2_gpll0_div_clk_src.clkr, + [NW_GCC_GPU_2_HSCNOC_GFX_CLK] = &nw_gcc_gpu_2_hscnoc_gfx_clk.clkr, + [NW_GCC_GPU_GPLL0_CLK_SRC] = &nw_gcc_gpu_gpll0_clk_src.clkr, + [NW_GCC_GPU_GPLL0_DIV_CLK_SRC] = &nw_gcc_gpu_gpll0_div_clk_src.clkr, + [NW_GCC_GPU_HSCNOC_GFX_CLK] = &nw_gcc_gpu_hscnoc_gfx_clk.clkr, + [NW_GCC_GPU_SMMU_VOTE_CLK] = &nw_gcc_gpu_smmu_vote_clk.clkr, + [NW_GCC_HSCNOC_GPU_2_AXI_CLK] = &nw_gcc_hscnoc_gpu_2_axi_clk.clkr, + [NW_GCC_HSCNOC_GPU_AXI_CLK] = &nw_gcc_hscnoc_gpu_axi_clk.clkr, + [NW_GCC_MMU_1_TCU_VOTE_CLK] = &nw_gcc_mmu_1_tcu_vote_clk.clkr, + [NW_GCC_VIDEO_AXI0_CLK] = &nw_gcc_video_axi0_clk.clkr, + [NW_GCC_VIDEO_AXI0C_CLK] = &nw_gcc_video_axi0c_clk.clkr, + [NW_GCC_VIDEO_AXI1_CLK] = &nw_gcc_video_axi1_clk.clkr, +}; + +static const struct qcom_reset_map nw_gcc_nord_resets[] = { + [NW_GCC_CAMERA_BCR] = { 0x16000 }, + [NW_GCC_DISPLAY_0_BCR] = { 0x18000 }, + [NW_GCC_DISPLAY_1_BCR] = { 0x19000 }, + [NW_GCC_DPRX0_BCR] = { 0x29000 }, + [NW_GCC_DPRX1_BCR] = { 0x2a000 }, + [NW_GCC_EVA_BCR] = { 0x1b000 }, + [NW_GCC_GPU_2_BCR] = { 0x24000 }, + [NW_GCC_GPU_BCR] = { 0x23000 }, + [NW_GCC_VIDEO_BCR] = { 0x1a000 }, +}; + +static u32 nw_gcc_nord_critical_cbcrs[] = { + 0x16004, /* NW_GCC_CAMERA_AHB_CLK */ + 0x16030, /* NW_GCC_CAMERA_XO_CLK */ + 0x18004, /* NW_GCC_DISP_0_AHB_CLK */ + 0x19004, /* NW_GCC_DISP_1_AHB_CLK */ + 0x29018, /* NW_GCC_DPRX0_CFG_AHB_CLK */ + 0x2a018, /* NW_GCC_DPRX1_CFG_AHB_CLK */ + 0x1b004, /* NW_GCC_EVA_AHB_CLK */ + 0x1b024, /* NW_GCC_EVA_XO_CLK */ + 0x23004, /* NW_GCC_GPU_CFG_AHB_CLK */ + 0x24004, /* NW_GCC_GPU_2_CFG_AHB_CLK */ + 0x1a004, /* NW_GCC_VIDEO_AHB_CLK */ + 0x1a044, /* NW_GCC_VIDEO_XO_CLK */ +}; + +static struct qcom_cc_driver_data nw_gcc_nord_driver_data = { + .clk_cbcrs = nw_gcc_nord_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(nw_gcc_nord_critical_cbcrs), +}; + +static const struct regmap_config nw_gcc_nord_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf41f0, + .fast_io = true, +}; + +static const struct qcom_cc_desc nw_gcc_nord_desc = { + .config = &nw_gcc_nord_regmap_config, + .clks = nw_gcc_nord_clocks, + .num_clks = ARRAY_SIZE(nw_gcc_nord_clocks), + .resets = nw_gcc_nord_resets, + .num_resets = ARRAY_SIZE(nw_gcc_nord_resets), + .driver_data = &nw_gcc_nord_driver_data, +}; + +static const struct of_device_id nw_gcc_nord_match_table[] = { + { .compatible = "qcom,nord-nwgcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, nw_gcc_nord_match_table); + +static int nw_gcc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &nw_gcc_nord_desc); +} + +static struct platform_driver nw_gcc_nord_driver = { + .probe = nw_gcc_nord_probe, + .driver = { + .name = "nwgcc-nord", + .of_match_table = nw_gcc_nord_match_table, + }, +}; + +module_platform_driver(nw_gcc_nord_driver); + +MODULE_DESCRIPTION("QTI NWGCC NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/segcc-nord.c b/drivers/clk/qcom/segcc-nord.c new file mode 100644 index 0000000000000..1aab0999de4dd --- /dev/null +++ b/drivers/clk/qcom/segcc-nord.c @@ -0,0 +1,1609 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_SE_GCC_GPLL0_OUT_EVEN, + P_SE_GCC_GPLL0_OUT_MAIN, + P_SE_GCC_GPLL2_OUT_MAIN, + P_SE_GCC_GPLL4_OUT_MAIN, + P_SE_GCC_GPLL5_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll se_gcc_gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gpll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_se_gcc_gpll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv se_gcc_gpll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_se_gcc_gpll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_se_gcc_gpll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gpll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static struct clk_alpha_pll se_gcc_gpll2 = { + .offset = 0x2000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(2), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gpll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll se_gcc_gpll4 = { + .offset = 0x4000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(4), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gpll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll se_gcc_gpll5 = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(5), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gpll5", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct parent_map se_gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SE_GCC_GPLL0_OUT_EVEN, 2 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &se_gcc_gpll0.clkr.hw }, + { .hw = &se_gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map se_gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &se_gcc_gpll0.clkr.hw }, +}; + +static const struct parent_map se_gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &se_gcc_gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map se_gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SE_GCC_GPLL5_OUT_MAIN, 3 }, + { P_SE_GCC_GPLL4_OUT_MAIN, 5 }, + { P_SE_GCC_GPLL2_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &se_gcc_gpll0.clkr.hw }, + { .hw = &se_gcc_gpll5.clkr.hw }, + { .hw = &se_gcc_gpll4.clkr.hw }, + { .hw = &se_gcc_gpll2.clkr.hw }, +}; + +static const struct parent_map se_gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SE_GCC_GPLL0_OUT_EVEN, 2 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &se_gcc_gpll0.clkr.hw }, + { .hw = &se_gcc_gpll0_out_even.clkr.hw }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_se_gcc_eee_emac0_clk_src[] = { + F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_eee_emac0_clk_src = { + .cmd_rcgr = 0x240b8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_2, + .freq_tbl = ftbl_se_gcc_eee_emac0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_eee_emac0_clk_src", + .parent_data = se_gcc_parent_data_2, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_eee_emac1_clk_src = { + .cmd_rcgr = 0x250b8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_2, + .freq_tbl = ftbl_se_gcc_eee_emac0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_eee_emac1_clk_src", + .parent_data = se_gcc_parent_data_2, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_emac0_phy_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_emac0_phy_aux_clk_src = { + .cmd_rcgr = 0x24030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = se_gcc_parent_map_2, + .freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_phy_aux_clk_src", + .parent_data = se_gcc_parent_data_2, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_emac0_ptp_clk_src[] = { + F(150000000, P_SE_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_emac0_ptp_clk_src = { + .cmd_rcgr = 0x24084, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_3, + .freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_ptp_clk_src", + .parent_data = se_gcc_parent_data_3, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_emac0_rgmii_clk_src[] = { + F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_emac0_rgmii_clk_src = { + .cmd_rcgr = 0x2406c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_3, + .freq_tbl = ftbl_se_gcc_emac0_rgmii_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_rgmii_clk_src", + .parent_data = se_gcc_parent_data_3, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_emac1_phy_aux_clk_src = { + .cmd_rcgr = 0x25030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = se_gcc_parent_map_2, + .freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_phy_aux_clk_src", + .parent_data = se_gcc_parent_data_2, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_emac1_ptp_clk_src = { + .cmd_rcgr = 0x25084, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_3, + .freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_ptp_clk_src", + .parent_data = se_gcc_parent_data_3, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_emac1_rgmii_clk_src = { + .cmd_rcgr = 0x2506c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_3, + .freq_tbl = ftbl_se_gcc_emac0_rgmii_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_rgmii_clk_src", + .parent_data = se_gcc_parent_data_3, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_gp1_clk_src[] = { + F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_SE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_gp1_clk_src = { + .cmd_rcgr = 0x19004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_4, + .freq_tbl = ftbl_se_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gp1_clk_src", + .parent_data = se_gcc_parent_data_4, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_gp2_clk_src = { + .cmd_rcgr = 0x1a004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_4, + .freq_tbl = ftbl_se_gcc_gp1_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gp2_clk_src", + .parent_data = se_gcc_parent_data_4, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), + F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), + F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), + F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), + F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), + F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), + F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), + F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 64, 375), + F(112000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 14, 75), + F(117964800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625), + F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s0_clk_src_init = { + .name = "se_gcc_qupv3_wrap0_s0_clk_src", + .parent_data = se_gcc_parent_data_1, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s0_clk_src = { + .cmd_rcgr = 0x2616c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_1, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s1_clk_src_init = { + .name = "se_gcc_qupv3_wrap0_s1_clk_src", + .parent_data = se_gcc_parent_data_1, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s1_clk_src = { + .cmd_rcgr = 0x262a8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_1, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s2_clk_src[] = { + F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), + F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), + F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), + F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), + F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), + F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), + F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), + F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s2_clk_src_init = { + .name = "se_gcc_qupv3_wrap0_s2_clk_src", + .parent_data = se_gcc_parent_data_1, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s2_clk_src = { + .cmd_rcgr = 0x263e4, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_1, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s3_clk_src_init = { + .name = "se_gcc_qupv3_wrap0_s3_clk_src", + .parent_data = se_gcc_parent_data_1, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s3_clk_src = { + .cmd_rcgr = 0x26520, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_1, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s4_clk_src_init = { + .name = "se_gcc_qupv3_wrap0_s4_clk_src", + .parent_data = se_gcc_parent_data_1, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s4_clk_src = { + .cmd_rcgr = 0x2665c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_1, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s5_clk_src_init = { + .name = "se_gcc_qupv3_wrap0_s5_clk_src", + .parent_data = se_gcc_parent_data_1, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s5_clk_src = { + .cmd_rcgr = 0x26798, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_1, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s6_clk_src_init = { + .name = "se_gcc_qupv3_wrap0_s6_clk_src", + .parent_data = se_gcc_parent_data_1, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s6_clk_src = { + .cmd_rcgr = 0x268d4, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_1, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s0_clk_src_init = { + .name = "se_gcc_qupv3_wrap1_s0_clk_src", + .parent_data = se_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s0_clk_src = { + .cmd_rcgr = 0x2716c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_0, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s1_clk_src_init = { + .name = "se_gcc_qupv3_wrap1_s1_clk_src", + .parent_data = se_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s1_clk_src = { + .cmd_rcgr = 0x272a8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_0, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s2_clk_src_init = { + .name = "se_gcc_qupv3_wrap1_s2_clk_src", + .parent_data = se_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s2_clk_src = { + .cmd_rcgr = 0x273e4, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_0, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s3_clk_src_init = { + .name = "se_gcc_qupv3_wrap1_s3_clk_src", + .parent_data = se_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s3_clk_src = { + .cmd_rcgr = 0x27520, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_0, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s4_clk_src_init = { + .name = "se_gcc_qupv3_wrap1_s4_clk_src", + .parent_data = se_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s4_clk_src = { + .cmd_rcgr = 0x2765c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_0, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s5_clk_src_init = { + .name = "se_gcc_qupv3_wrap1_s5_clk_src", + .parent_data = se_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s5_clk_src = { + .cmd_rcgr = 0x27798, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_0, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s6_clk_src_init = { + .name = "se_gcc_qupv3_wrap1_s6_clk_src", + .parent_data = se_gcc_parent_data_0, + .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s6_clk_src = { + .cmd_rcgr = 0x278d4, + .mnd_width = 16, + .hid_width = 5, + .parent_map = se_gcc_parent_map_0, + .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &se_gcc_qupv3_wrap1_s6_clk_src_init, +}; + +static struct clk_branch se_gcc_eee_emac0_clk = { + .halt_reg = 0x240b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x240b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_eee_emac0_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_eee_emac0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_eee_emac1_clk = { + .halt_reg = 0x250b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x250b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_eee_emac1_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_eee_emac1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_axi_clk = { + .halt_reg = 0x2401c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2401c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2401c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_cc_sgmiiphy_rx_clk = { + .halt_reg = 0x24064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x24064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_cc_sgmiiphy_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_cc_sgmiiphy_tx_clk = { + .halt_reg = 0x2405c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2405c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_cc_sgmiiphy_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_phy_aux_clk = { + .halt_reg = 0x2402c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2402c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_emac0_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_ptp_clk = { + .halt_reg = 0x24048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x24048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_ptp_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_emac0_ptp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_rgmii_clk = { + .halt_reg = 0x24058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x24058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_rgmii_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_emac0_rgmii_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_rpcs_rx_clk = { + .halt_reg = 0x240a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x240a8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_rpcs_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_rpcs_tx_clk = { + .halt_reg = 0x240a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x240a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_rpcs_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_xgxs_rx_clk = { + .halt_reg = 0x240b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x240b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_xgxs_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_xgxs_tx_clk = { + .halt_reg = 0x240ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x240ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_xgxs_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_axi_clk = { + .halt_reg = 0x2501c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2501c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2501c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_cc_sgmiiphy_rx_clk = { + .halt_reg = 0x25064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x25064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_cc_sgmiiphy_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_cc_sgmiiphy_tx_clk = { + .halt_reg = 0x2505c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2505c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_cc_sgmiiphy_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_phy_aux_clk = { + .halt_reg = 0x2502c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2502c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_emac1_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_ptp_clk = { + .halt_reg = 0x25048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x25048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_ptp_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_emac1_ptp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_rgmii_clk = { + .halt_reg = 0x25058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x25058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_rgmii_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_emac1_rgmii_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_rpcs_rx_clk = { + .halt_reg = 0x250a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x250a8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_rpcs_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_rpcs_tx_clk = { + .halt_reg = 0x250a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x250a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_rpcs_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_xgxs_rx_clk = { + .halt_reg = 0x250b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x250b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_xgxs_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_xgxs_tx_clk = { + .halt_reg = 0x250ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x250ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_xgxs_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_frq_measure_ref_clk = { + .halt_reg = 0x18008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x18008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_frq_measure_ref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_gp1_clk = { + .halt_reg = 0x19000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gp1_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_gp2_clk = { + .halt_reg = 0x1a000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_gp2_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_mmu_2_tcu_vote_clk = { + .halt_reg = 0x57040, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_mmu_2_tcu_vote_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_core_2x_clk = { + .halt_reg = 0x26020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(15), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_core_clk = { + .halt_reg = 0x2600c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_m_ahb_clk = { + .halt_reg = 0x26004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x26004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(12), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s0_clk = { + .halt_reg = 0x2615c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(16), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_s0_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s1_clk = { + .halt_reg = 0x26298, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(17), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_s1_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s2_clk = { + .halt_reg = 0x263d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_s2_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s3_clk = { + .halt_reg = 0x26510, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_s3_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s4_clk = { + .halt_reg = 0x2664c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_s4_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s5_clk = { + .halt_reg = 0x26788, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(21), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_s5_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s6_clk = { + .halt_reg = 0x268c4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(22), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_s6_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s_ahb_clk = { + .halt_reg = 0x26008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x26008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(13), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap0_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_core_2x_clk = { + .halt_reg = 0x27020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(26), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_core_clk = { + .halt_reg = 0x2700c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(25), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_m_ahb_clk = { + .halt_reg = 0x27004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x27004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(23), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s0_clk = { + .halt_reg = 0x2715c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(27), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_s0_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s1_clk = { + .halt_reg = 0x27298, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(28), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_s1_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s2_clk = { + .halt_reg = 0x273d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(29), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_s2_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s3_clk = { + .halt_reg = 0x27510, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(30), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_s3_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s4_clk = { + .halt_reg = 0x2764c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(31), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_s4_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s5_clk = { + .halt_reg = 0x27788, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_s5_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s6_clk = { + .halt_reg = 0x278c4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x57008, + .enable_mask = BIT(1), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_s6_clk", + .parent_hws = (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s_ahb_clk = { + .halt_reg = 0x27008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x27008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x57000, + .enable_mask = BIT(24), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_qupv3_wrap1_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc se_gcc_emac0_gdsc = { + .gdscr = 0x24004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "se_gcc_emac0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc se_gcc_emac1_gdsc = { + .gdscr = 0x25004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "se_gcc_emac1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *se_gcc_nord_clocks[] = { + [SE_GCC_EEE_EMAC0_CLK] = &se_gcc_eee_emac0_clk.clkr, + [SE_GCC_EEE_EMAC0_CLK_SRC] = &se_gcc_eee_emac0_clk_src.clkr, + [SE_GCC_EEE_EMAC1_CLK] = &se_gcc_eee_emac1_clk.clkr, + [SE_GCC_EEE_EMAC1_CLK_SRC] = &se_gcc_eee_emac1_clk_src.clkr, + [SE_GCC_EMAC0_AXI_CLK] = &se_gcc_emac0_axi_clk.clkr, + [SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac0_cc_sgmiiphy_rx_clk.clkr, + [SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac0_cc_sgmiiphy_tx_clk.clkr, + [SE_GCC_EMAC0_PHY_AUX_CLK] = &se_gcc_emac0_phy_aux_clk.clkr, + [SE_GCC_EMAC0_PHY_AUX_CLK_SRC] = &se_gcc_emac0_phy_aux_clk_src.clkr, + [SE_GCC_EMAC0_PTP_CLK] = &se_gcc_emac0_ptp_clk.clkr, + [SE_GCC_EMAC0_PTP_CLK_SRC] = &se_gcc_emac0_ptp_clk_src.clkr, + [SE_GCC_EMAC0_RGMII_CLK] = &se_gcc_emac0_rgmii_clk.clkr, + [SE_GCC_EMAC0_RGMII_CLK_SRC] = &se_gcc_emac0_rgmii_clk_src.clkr, + [SE_GCC_EMAC0_RPCS_RX_CLK] = &se_gcc_emac0_rpcs_rx_clk.clkr, + [SE_GCC_EMAC0_RPCS_TX_CLK] = &se_gcc_emac0_rpcs_tx_clk.clkr, + [SE_GCC_EMAC0_XGXS_RX_CLK] = &se_gcc_emac0_xgxs_rx_clk.clkr, + [SE_GCC_EMAC0_XGXS_TX_CLK] = &se_gcc_emac0_xgxs_tx_clk.clkr, + [SE_GCC_EMAC1_AXI_CLK] = &se_gcc_emac1_axi_clk.clkr, + [SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac1_cc_sgmiiphy_rx_clk.clkr, + [SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac1_cc_sgmiiphy_tx_clk.clkr, + [SE_GCC_EMAC1_PHY_AUX_CLK] = &se_gcc_emac1_phy_aux_clk.clkr, + [SE_GCC_EMAC1_PHY_AUX_CLK_SRC] = &se_gcc_emac1_phy_aux_clk_src.clkr, + [SE_GCC_EMAC1_PTP_CLK] = &se_gcc_emac1_ptp_clk.clkr, + [SE_GCC_EMAC1_PTP_CLK_SRC] = &se_gcc_emac1_ptp_clk_src.clkr, + [SE_GCC_EMAC1_RGMII_CLK] = &se_gcc_emac1_rgmii_clk.clkr, + [SE_GCC_EMAC1_RGMII_CLK_SRC] = &se_gcc_emac1_rgmii_clk_src.clkr, + [SE_GCC_EMAC1_RPCS_RX_CLK] = &se_gcc_emac1_rpcs_rx_clk.clkr, + [SE_GCC_EMAC1_RPCS_TX_CLK] = &se_gcc_emac1_rpcs_tx_clk.clkr, + [SE_GCC_EMAC1_XGXS_RX_CLK] = &se_gcc_emac1_xgxs_rx_clk.clkr, + [SE_GCC_EMAC1_XGXS_TX_CLK] = &se_gcc_emac1_xgxs_tx_clk.clkr, + [SE_GCC_FRQ_MEASURE_REF_CLK] = &se_gcc_frq_measure_ref_clk.clkr, + [SE_GCC_GP1_CLK] = &se_gcc_gp1_clk.clkr, + [SE_GCC_GP1_CLK_SRC] = &se_gcc_gp1_clk_src.clkr, + [SE_GCC_GP2_CLK] = &se_gcc_gp2_clk.clkr, + [SE_GCC_GP2_CLK_SRC] = &se_gcc_gp2_clk_src.clkr, + [SE_GCC_GPLL0] = &se_gcc_gpll0.clkr, + [SE_GCC_GPLL0_OUT_EVEN] = &se_gcc_gpll0_out_even.clkr, + [SE_GCC_GPLL2] = &se_gcc_gpll2.clkr, + [SE_GCC_GPLL4] = &se_gcc_gpll4.clkr, + [SE_GCC_GPLL5] = &se_gcc_gpll5.clkr, + [SE_GCC_MMU_2_TCU_VOTE_CLK] = &se_gcc_mmu_2_tcu_vote_clk.clkr, + [SE_GCC_QUPV3_WRAP0_CORE_2X_CLK] = &se_gcc_qupv3_wrap0_core_2x_clk.clkr, + [SE_GCC_QUPV3_WRAP0_CORE_CLK] = &se_gcc_qupv3_wrap0_core_clk.clkr, + [SE_GCC_QUPV3_WRAP0_M_AHB_CLK] = &se_gcc_qupv3_wrap0_m_ahb_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S0_CLK] = &se_gcc_qupv3_wrap0_s0_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S0_CLK_SRC] = &se_gcc_qupv3_wrap0_s0_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S1_CLK] = &se_gcc_qupv3_wrap0_s1_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S1_CLK_SRC] = &se_gcc_qupv3_wrap0_s1_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S2_CLK] = &se_gcc_qupv3_wrap0_s2_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S2_CLK_SRC] = &se_gcc_qupv3_wrap0_s2_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S3_CLK] = &se_gcc_qupv3_wrap0_s3_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S3_CLK_SRC] = &se_gcc_qupv3_wrap0_s3_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S4_CLK] = &se_gcc_qupv3_wrap0_s4_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S4_CLK_SRC] = &se_gcc_qupv3_wrap0_s4_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S5_CLK] = &se_gcc_qupv3_wrap0_s5_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S5_CLK_SRC] = &se_gcc_qupv3_wrap0_s5_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S6_CLK] = &se_gcc_qupv3_wrap0_s6_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S6_CLK_SRC] = &se_gcc_qupv3_wrap0_s6_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S_AHB_CLK] = &se_gcc_qupv3_wrap0_s_ahb_clk.clkr, + [SE_GCC_QUPV3_WRAP1_CORE_2X_CLK] = &se_gcc_qupv3_wrap1_core_2x_clk.clkr, + [SE_GCC_QUPV3_WRAP1_CORE_CLK] = &se_gcc_qupv3_wrap1_core_clk.clkr, + [SE_GCC_QUPV3_WRAP1_M_AHB_CLK] = &se_gcc_qupv3_wrap1_m_ahb_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S0_CLK] = &se_gcc_qupv3_wrap1_s0_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S0_CLK_SRC] = &se_gcc_qupv3_wrap1_s0_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S1_CLK] = &se_gcc_qupv3_wrap1_s1_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S1_CLK_SRC] = &se_gcc_qupv3_wrap1_s1_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S2_CLK] = &se_gcc_qupv3_wrap1_s2_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S2_CLK_SRC] = &se_gcc_qupv3_wrap1_s2_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S3_CLK] = &se_gcc_qupv3_wrap1_s3_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S3_CLK_SRC] = &se_gcc_qupv3_wrap1_s3_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S4_CLK] = &se_gcc_qupv3_wrap1_s4_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S4_CLK_SRC] = &se_gcc_qupv3_wrap1_s4_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S5_CLK] = &se_gcc_qupv3_wrap1_s5_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S5_CLK_SRC] = &se_gcc_qupv3_wrap1_s5_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S6_CLK] = &se_gcc_qupv3_wrap1_s6_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S6_CLK_SRC] = &se_gcc_qupv3_wrap1_s6_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S_AHB_CLK] = &se_gcc_qupv3_wrap1_s_ahb_clk.clkr, +}; + +static struct gdsc *se_gcc_nord_gdscs[] = { + [SE_GCC_EMAC0_GDSC] = &se_gcc_emac0_gdsc, + [SE_GCC_EMAC1_GDSC] = &se_gcc_emac1_gdsc, +}; + +static const struct qcom_reset_map se_gcc_nord_resets[] = { + [SE_GCC_EMAC0_BCR] = { 0x24000 }, + [SE_GCC_EMAC1_BCR] = { 0x25000 }, + [SE_GCC_QUPV3_WRAPPER_0_BCR] = { 0x26000 }, + [SE_GCC_QUPV3_WRAPPER_1_BCR] = { 0x27000 }, +}; + +static const struct clk_rcg_dfs_data se_gcc_nord_dfs_clocks[] = { + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s5_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s6_clk_src), +}; + +static const struct regmap_config se_gcc_nord_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf41f0, + .fast_io = true, +}; + +static struct qcom_cc_driver_data se_gcc_nord_driver_data = { + .dfs_rcgs = se_gcc_nord_dfs_clocks, + .num_dfs_rcgs = ARRAY_SIZE(se_gcc_nord_dfs_clocks), +}; + +static const struct qcom_cc_desc se_gcc_nord_desc = { + .config = &se_gcc_nord_regmap_config, + .clks = se_gcc_nord_clocks, + .num_clks = ARRAY_SIZE(se_gcc_nord_clocks), + .resets = se_gcc_nord_resets, + .num_resets = ARRAY_SIZE(se_gcc_nord_resets), + .gdscs = se_gcc_nord_gdscs, + .num_gdscs = ARRAY_SIZE(se_gcc_nord_gdscs), + .driver_data = &se_gcc_nord_driver_data, +}; + +static const struct of_device_id se_gcc_nord_match_table[] = { + { .compatible = "qcom,nord-segcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, se_gcc_nord_match_table); + +static int se_gcc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &se_gcc_nord_desc); +} + +static struct platform_driver se_gcc_nord_driver = { + .probe = se_gcc_nord_probe, + .driver = { + .name = "segcc-nord", + .of_match_table = se_gcc_nord_match_table, + }, +}; + +module_platform_driver(se_gcc_nord_driver); + +MODULE_DESCRIPTION("QTI SEGCC NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/tcsrcc-nord.c b/drivers/clk/qcom/tcsrcc-nord.c new file mode 100644 index 0000000000000..ed0f4909158f6 --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-nord.c @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_dp_rx_0_clkref_en = { + .halt_reg = 0xa008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xa008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_dp_rx_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_rx_1_clkref_en = { + .halt_reg = 0xb008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xb008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_dp_rx_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_tx_0_clkref_en = { + .halt_reg = 0xc008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xc008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_dp_tx_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_tx_1_clkref_en = { + .halt_reg = 0xd008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xd008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_dp_tx_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_tx_2_clkref_en = { + .halt_reg = 0xe008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xe008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_dp_tx_2_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_tx_3_clkref_en = { + .halt_reg = 0xf008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xf008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_dp_tx_3_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_clkref_en = { + .halt_reg = 0x8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_pcie_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en = { + .halt_reg = 0x3008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x3008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_ufs_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_0_clkref_en = { + .halt_reg = 0x4008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x4008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_usb2_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_1_clkref_en = { + .halt_reg = 0x5008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_usb2_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_2_clkref_en = { + .halt_reg = 0x6008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x6008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_usb2_2_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_0_clkref_en = { + .halt_reg = 0x8008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x8008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_usb3_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_1_clkref_en = { + .halt_reg = 0x7008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_usb3_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ux_sgmii_0_clkref_en = { + .halt_reg = 0x1008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_ux_sgmii_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ux_sgmii_1_clkref_en = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_ux_sgmii_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_nord_clocks[] = { + [TCSR_DP_RX_0_CLKREF_EN] = &tcsr_dp_rx_0_clkref_en.clkr, + [TCSR_DP_RX_1_CLKREF_EN] = &tcsr_dp_rx_1_clkref_en.clkr, + [TCSR_DP_TX_0_CLKREF_EN] = &tcsr_dp_tx_0_clkref_en.clkr, + [TCSR_DP_TX_1_CLKREF_EN] = &tcsr_dp_tx_1_clkref_en.clkr, + [TCSR_DP_TX_2_CLKREF_EN] = &tcsr_dp_tx_2_clkref_en.clkr, + [TCSR_DP_TX_3_CLKREF_EN] = &tcsr_dp_tx_3_clkref_en.clkr, + [TCSR_PCIE_CLKREF_EN] = &tcsr_pcie_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr, + [TCSR_USB2_0_CLKREF_EN] = &tcsr_usb2_0_clkref_en.clkr, + [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr, + [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr, + [TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr, + [TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr, + [TCSR_UX_SGMII_0_CLKREF_EN] = &tcsr_ux_sgmii_0_clkref_en.clkr, + [TCSR_UX_SGMII_1_CLKREF_EN] = &tcsr_ux_sgmii_1_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_nord_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf008, + .fast_io = true, +}; + +static const struct qcom_cc_desc tcsr_cc_nord_desc = { + .config = &tcsr_cc_nord_regmap_config, + .clks = tcsr_cc_nord_clocks, + .num_clks = ARRAY_SIZE(tcsr_cc_nord_clocks), +}; + +static const struct of_device_id tcsr_cc_nord_match_table[] = { + { .compatible = "qcom,nord-tcsrcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_nord_match_table); + +static int tcsr_cc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &tcsr_cc_nord_desc); +} + +static struct platform_driver tcsr_cc_nord_driver = { + .probe = tcsr_cc_nord_probe, + .driver = { + .name = "tcsrcc-nord", + .of_match_table = tcsr_cc_nord_match_table, + }, +}; + +module_platform_driver(tcsr_cc_nord_driver); + +MODULE_DESCRIPTION("QTI TCSRCC NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/clock/qcom,nord-gcc.h b/include/dt-bindings/clock/qcom,nord-gcc.h new file mode 100644 index 0000000000000..8fbde162c8598 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gcc.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H + +/* GCC clocks */ +#define GCC_BOOT_ROM_AHB_CLK 0 +#define GCC_GP1_CLK 1 +#define GCC_GP1_CLK_SRC 2 +#define GCC_GP2_CLK 3 +#define GCC_GP2_CLK_SRC 4 +#define GCC_GPLL0 5 +#define GCC_GPLL0_OUT_EVEN 6 +#define GCC_MMU_0_TCU_VOTE_CLK 7 +#define GCC_PCIE_A_AUX_CLK 8 +#define GCC_PCIE_A_AUX_CLK_SRC 9 +#define GCC_PCIE_A_CFG_AHB_CLK 10 +#define GCC_PCIE_A_DTI_QTC_CLK 11 +#define GCC_PCIE_A_MSTR_AXI_CLK 12 +#define GCC_PCIE_A_PHY_AUX_CLK 13 +#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14 +#define GCC_PCIE_A_PHY_RCHNG_CLK 15 +#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16 +#define GCC_PCIE_A_PIPE_CLK 17 +#define GCC_PCIE_A_PIPE_CLK_SRC 18 +#define GCC_PCIE_A_SLV_AXI_CLK 19 +#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20 +#define GCC_PCIE_B_AUX_CLK 21 +#define GCC_PCIE_B_AUX_CLK_SRC 22 +#define GCC_PCIE_B_CFG_AHB_CLK 23 +#define GCC_PCIE_B_DTI_QTC_CLK 24 +#define GCC_PCIE_B_MSTR_AXI_CLK 25 +#define GCC_PCIE_B_PHY_AUX_CLK 26 +#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27 +#define GCC_PCIE_B_PHY_RCHNG_CLK 28 +#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29 +#define GCC_PCIE_B_PIPE_CLK 30 +#define GCC_PCIE_B_PIPE_CLK_SRC 31 +#define GCC_PCIE_B_SLV_AXI_CLK 32 +#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33 +#define GCC_PCIE_C_AUX_CLK 34 +#define GCC_PCIE_C_AUX_CLK_SRC 35 +#define GCC_PCIE_C_CFG_AHB_CLK 36 +#define GCC_PCIE_C_DTI_QTC_CLK 37 +#define GCC_PCIE_C_MSTR_AXI_CLK 38 +#define GCC_PCIE_C_PHY_AUX_CLK 39 +#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40 +#define GCC_PCIE_C_PHY_RCHNG_CLK 41 +#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_C_PIPE_CLK 43 +#define GCC_PCIE_C_PIPE_CLK_SRC 44 +#define GCC_PCIE_C_SLV_AXI_CLK 45 +#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46 +#define GCC_PCIE_D_AUX_CLK 47 +#define GCC_PCIE_D_AUX_CLK_SRC 48 +#define GCC_PCIE_D_CFG_AHB_CLK 49 +#define GCC_PCIE_D_DTI_QTC_CLK 50 +#define GCC_PCIE_D_MSTR_AXI_CLK 51 +#define GCC_PCIE_D_PHY_AUX_CLK 52 +#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53 +#define GCC_PCIE_D_PHY_RCHNG_CLK 54 +#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55 +#define GCC_PCIE_D_PIPE_CLK 56 +#define GCC_PCIE_D_PIPE_CLK_SRC 57 +#define GCC_PCIE_D_SLV_AXI_CLK 58 +#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59 +#define GCC_PCIE_LINK_AHB_CLK 60 +#define GCC_PCIE_LINK_XO_CLK 61 +#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62 +#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63 +#define GCC_PCIE_NOC_M_CFG_CLK 64 +#define GCC_PCIE_NOC_M_PDB_CLK 65 +#define GCC_PCIE_NOC_MSTR_AXI_CLK 66 +#define GCC_PCIE_NOC_PWRCTL_CLK 67 +#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68 +#define GCC_PCIE_NOC_REFGEN_CLK 69 +#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70 +#define GCC_PCIE_NOC_S_CFG_CLK 71 +#define GCC_PCIE_NOC_S_PDB_CLK 72 +#define GCC_PCIE_NOC_SAFETY_CLK 73 +#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74 +#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75 +#define GCC_PCIE_NOC_TSCTR_CLK 76 +#define GCC_PCIE_NOC_XO_CLK 77 +#define GCC_PDM2_CLK 78 +#define GCC_PDM2_CLK_SRC 79 +#define GCC_PDM_AHB_CLK 80 +#define GCC_PDM_XO4_CLK 81 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82 +#define GCC_QUPV3_WRAP3_CORE_CLK 83 +#define GCC_QUPV3_WRAP3_M_CLK 84 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86 +#define GCC_QUPV3_WRAP3_S0_CLK 87 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88 +#define GCC_QUPV3_WRAP3_S_AHB_CLK 89 +#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90 + +/* GCC power domains */ +#define GCC_PCIE_A_GDSC 0 +#define GCC_PCIE_A_PHY_GDSC 1 +#define GCC_PCIE_B_GDSC 2 +#define GCC_PCIE_B_PHY_GDSC 3 +#define GCC_PCIE_C_GDSC 4 +#define GCC_PCIE_C_PHY_GDSC 5 +#define GCC_PCIE_D_GDSC 6 +#define GCC_PCIE_D_PHY_GDSC 7 +#define GCC_PCIE_NOC_GDSC 8 + +/* GCC resets */ +#define GCC_PCIE_A_BCR 0 +#define GCC_PCIE_A_LINK_DOWN_BCR 1 +#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2 +#define GCC_PCIE_A_PHY_BCR 3 +#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4 +#define GCC_PCIE_A_PHY_COM_BCR 5 +#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_B_BCR 7 +#define GCC_PCIE_B_LINK_DOWN_BCR 8 +#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_B_PHY_BCR 10 +#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11 +#define GCC_PCIE_B_PHY_COM_BCR 12 +#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_C_BCR 14 +#define GCC_PCIE_C_LINK_DOWN_BCR 15 +#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_C_PHY_BCR 17 +#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18 +#define GCC_PCIE_C_PHY_COM_BCR 19 +#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20 +#define GCC_PCIE_D_BCR 21 +#define GCC_PCIE_D_LINK_DOWN_BCR 22 +#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23 +#define GCC_PCIE_D_PHY_BCR 24 +#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25 +#define GCC_PCIE_D_PHY_COM_BCR 26 +#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27 +#define GCC_PCIE_NOC_BCR 28 +#define GCC_PDM_BCR 29 +#define GCC_QUPV3_WRAPPER_3_BCR 30 +#define GCC_TCSR_PCIE_BCR 31 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h new file mode 100644 index 0000000000000..95f333d8e1aa7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-negcc.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H + +/* NE_GCC clocks */ +#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0 +#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1 +#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2 +#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3 +#define NE_GCC_AHB2PHY_CLK 4 +#define NE_GCC_CNOC_USB2_AXI_CLK 5 +#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6 +#define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7 +#define NE_GCC_FRQ_MEASURE_REF_CLK 8 +#define NE_GCC_GP1_CLK 9 +#define NE_GCC_GP1_CLK_SRC 10 +#define NE_GCC_GP2_CLK 11 +#define NE_GCC_GP2_CLK_SRC 12 +#define NE_GCC_GPLL0 13 +#define NE_GCC_GPLL0_OUT_EVEN 14 +#define NE_GCC_GPLL2 15 +#define NE_GCC_GPU_2_CFG_CLK 16 +#define NE_GCC_GPU_2_GPLL0_CLK_SRC 17 +#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18 +#define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19 +#define NE_GCC_GPU_2_SMMU_VOTE_CLK 20 +#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21 +#define NE_GCC_QUPV3_WRAP2_CORE_CLK 22 +#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23 +#define NE_GCC_QUPV3_WRAP2_S0_CLK 24 +#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25 +#define NE_GCC_QUPV3_WRAP2_S1_CLK 26 +#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27 +#define NE_GCC_QUPV3_WRAP2_S2_CLK 28 +#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29 +#define NE_GCC_QUPV3_WRAP2_S3_CLK 30 +#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31 +#define NE_GCC_QUPV3_WRAP2_S4_CLK 32 +#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33 +#define NE_GCC_QUPV3_WRAP2_S5_CLK 34 +#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35 +#define NE_GCC_QUPV3_WRAP2_S6_CLK 36 +#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37 +#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38 +#define NE_GCC_SDCC4_APPS_CLK 39 +#define NE_GCC_SDCC4_APPS_CLK_SRC 40 +#define NE_GCC_SDCC4_AXI_CLK 41 +#define NE_GCC_UFS_PHY_AHB_CLK 42 +#define NE_GCC_UFS_PHY_AXI_CLK 43 +#define NE_GCC_UFS_PHY_AXI_CLK_SRC 44 +#define NE_GCC_UFS_PHY_ICE_CORE_CLK 45 +#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46 +#define NE_GCC_UFS_PHY_PHY_AUX_CLK 47 +#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48 +#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49 +#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50 +#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51 +#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52 +#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53 +#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54 +#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55 +#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56 +#define NE_GCC_USB20_MASTER_CLK 57 +#define NE_GCC_USB20_MASTER_CLK_SRC 58 +#define NE_GCC_USB20_MOCK_UTMI_CLK 59 +#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60 +#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61 +#define NE_GCC_USB20_SLEEP_CLK 62 +#define NE_GCC_USB31_PRIM_ATB_CLK 63 +#define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64 +#define NE_GCC_USB31_PRIM_MASTER_CLK 65 +#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69 +#define NE_GCC_USB31_PRIM_SLEEP_CLK 70 +#define NE_GCC_USB31_SEC_ATB_CLK 71 +#define NE_GCC_USB31_SEC_EUD_AHB_CLK 72 +#define NE_GCC_USB31_SEC_MASTER_CLK 73 +#define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74 +#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75 +#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76 +#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77 +#define NE_GCC_USB31_SEC_SLEEP_CLK 78 +#define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79 +#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80 +#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81 +#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82 +#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83 +#define NE_GCC_USB3_SEC_PHY_AUX_CLK 84 +#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85 +#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86 +#define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87 +#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88 + +/* NE_GCC power domains */ +#define NE_GCC_UFS_MEM_PHY_GDSC 0 +#define NE_GCC_UFS_PHY_GDSC 1 +#define NE_GCC_USB20_PRIM_GDSC 2 +#define NE_GCC_USB31_PRIM_GDSC 3 +#define NE_GCC_USB31_SEC_GDSC 4 +#define NE_GCC_USB3_PHY_GDSC 5 +#define NE_GCC_USB3_SEC_PHY_GDSC 6 + +/* NE_GCC resets */ +#define NE_GCC_GPU_2_BCR 0 +#define NE_GCC_QUPV3_WRAPPER_2_BCR 1 +#define NE_GCC_SDCC4_BCR 2 +#define NE_GCC_UFS_PHY_BCR 3 +#define NE_GCC_USB20_PRIM_BCR 4 +#define NE_GCC_USB31_PRIM_BCR 5 +#define NE_GCC_USB31_SEC_BCR 6 +#define NE_GCC_USB3_DP_PHY_PRIM_BCR 7 +#define NE_GCC_USB3_DP_PHY_SEC_BCR 8 +#define NE_GCC_USB3_PHY_PRIM_BCR 9 +#define NE_GCC_USB3_PHY_SEC_BCR 10 +#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11 +#define NE_GCC_USB3PHY_PHY_SEC_BCR 12 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-tcsrcc.h b/include/dt-bindings/clock/qcom,nord-tcsrcc.h new file mode 100644 index 0000000000000..3f0e2ff7acc72 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-tcsrcc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H + +/* TCSR_CC clocks */ +#define TCSR_DP_RX_0_CLKREF_EN 0 +#define TCSR_DP_RX_1_CLKREF_EN 1 +#define TCSR_DP_TX_0_CLKREF_EN 2 +#define TCSR_DP_TX_1_CLKREF_EN 3 +#define TCSR_DP_TX_2_CLKREF_EN 4 +#define TCSR_DP_TX_3_CLKREF_EN 5 +#define TCSR_PCIE_CLKREF_EN 6 +#define TCSR_UFS_CLKREF_EN 7 +#define TCSR_USB2_0_CLKREF_EN 8 +#define TCSR_USB2_1_CLKREF_EN 9 +#define TCSR_USB2_2_CLKREF_EN 10 +#define TCSR_USB3_0_CLKREF_EN 11 +#define TCSR_USB3_1_CLKREF_EN 12 +#define TCSR_UX_SGMII_0_CLKREF_EN 13 +#define TCSR_UX_SGMII_1_CLKREF_EN 14 + +#endif From 7c835ba374117296dffe90891e0472b2e967d06a Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 19:55:08 +0200 Subject: [PATCH 0952/1330] clk: qcom: nord: Add missing nwgcc and segcc dt-bindings headers Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- include/dt-bindings/clock/qcom,nord-nwgcc.h | 69 +++++++++++++++ include/dt-bindings/clock/qcom,nord-segcc.h | 98 +++++++++++++++++++++ 2 files changed, 167 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,nord-nwgcc.h create mode 100644 include/dt-bindings/clock/qcom,nord-segcc.h diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h new file mode 100644 index 0000000000000..b6253dd2aa85a --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H + +/* NW_GCC clocks */ +#define NW_GCC_ACMU_MUX_CLK 0 +#define NW_GCC_CAMERA_AHB_CLK 1 +#define NW_GCC_CAMERA_HF_AXI_CLK 2 +#define NW_GCC_CAMERA_SF_AXI_CLK 3 +#define NW_GCC_CAMERA_TRIG_CLK 4 +#define NW_GCC_CAMERA_XO_CLK 5 +#define NW_GCC_DISP_0_AHB_CLK 6 +#define NW_GCC_DISP_0_HF_AXI_CLK 7 +#define NW_GCC_DISP_0_TRIG_CLK 8 +#define NW_GCC_DISP_1_AHB_CLK 9 +#define NW_GCC_DISP_1_HF_AXI_CLK 10 +#define NW_GCC_DISP_1_TRIG_CLK 11 +#define NW_GCC_DPRX0_AXI_HF_CLK 12 +#define NW_GCC_DPRX0_CFG_AHB_CLK 13 +#define NW_GCC_DPRX1_AXI_HF_CLK 14 +#define NW_GCC_DPRX1_CFG_AHB_CLK 15 +#define NW_GCC_EVA_AHB_CLK 16 +#define NW_GCC_EVA_AXI0_CLK 17 +#define NW_GCC_EVA_AXI0C_CLK 18 +#define NW_GCC_EVA_TRIG_CLK 19 +#define NW_GCC_EVA_XO_CLK 20 +#define NW_GCC_FRQ_MEASURE_REF_CLK 21 +#define NW_GCC_GP1_CLK 22 +#define NW_GCC_GP1_CLK_SRC 23 +#define NW_GCC_GP2_CLK 24 +#define NW_GCC_GP2_CLK_SRC 25 +#define NW_GCC_GPLL0 26 +#define NW_GCC_GPLL0_OUT_EVEN 27 +#define NW_GCC_GPU_2_CFG_AHB_CLK 28 +#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29 +#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30 +#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31 +#define NW_GCC_GPU_CFG_AHB_CLK 32 +#define NW_GCC_GPU_GPLL0_CLK_SRC 33 +#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34 +#define NW_GCC_GPU_HSCNOC_GFX_CLK 35 +#define NW_GCC_GPU_SMMU_VOTE_CLK 36 +#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37 +#define NW_GCC_HSCNOC_GPU_AXI_CLK 38 +#define NW_GCC_MMU_1_TCU_VOTE_CLK 39 +#define NW_GCC_VIDEO_AHB_CLK 40 +#define NW_GCC_VIDEO_AXI0_CLK 41 +#define NW_GCC_VIDEO_AXI0C_CLK 42 +#define NW_GCC_VIDEO_AXI1_CLK 43 +#define NW_GCC_VIDEO_XO_CLK 44 + +/* NW_GCC power domains */ + +/* NW_GCC resets */ +#define NW_GCC_CAMERA_BCR 0 +#define NW_GCC_DISPLAY_0_BCR 1 +#define NW_GCC_DISPLAY_1_BCR 2 +#define NW_GCC_DPRX0_BCR 3 +#define NW_GCC_DPRX1_BCR 4 +#define NW_GCC_EVA_BCR 5 +#define NW_GCC_GPU_2_BCR 6 +#define NW_GCC_GPU_BCR 7 +#define NW_GCC_VIDEO_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h new file mode 100644 index 0000000000000..f0f7422af692d --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-segcc.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H + +/* SE_GCC clocks */ +#define SE_GCC_EEE_EMAC0_CLK 0 +#define SE_GCC_EEE_EMAC0_CLK_SRC 1 +#define SE_GCC_EEE_EMAC1_CLK 2 +#define SE_GCC_EEE_EMAC1_CLK_SRC 3 +#define SE_GCC_EMAC0_AXI_CLK 4 +#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5 +#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6 +#define SE_GCC_EMAC0_PHY_AUX_CLK 7 +#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8 +#define SE_GCC_EMAC0_PTP_CLK 9 +#define SE_GCC_EMAC0_PTP_CLK_SRC 10 +#define SE_GCC_EMAC0_RGMII_CLK 11 +#define SE_GCC_EMAC0_RGMII_CLK_SRC 12 +#define SE_GCC_EMAC0_RPCS_RX_CLK 13 +#define SE_GCC_EMAC0_RPCS_TX_CLK 14 +#define SE_GCC_EMAC0_XGXS_RX_CLK 15 +#define SE_GCC_EMAC0_XGXS_TX_CLK 16 +#define SE_GCC_EMAC1_AXI_CLK 17 +#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18 +#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19 +#define SE_GCC_EMAC1_PHY_AUX_CLK 20 +#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21 +#define SE_GCC_EMAC1_PTP_CLK 22 +#define SE_GCC_EMAC1_PTP_CLK_SRC 23 +#define SE_GCC_EMAC1_RGMII_CLK 24 +#define SE_GCC_EMAC1_RGMII_CLK_SRC 25 +#define SE_GCC_EMAC1_RPCS_RX_CLK 26 +#define SE_GCC_EMAC1_RPCS_TX_CLK 27 +#define SE_GCC_EMAC1_XGXS_RX_CLK 28 +#define SE_GCC_EMAC1_XGXS_TX_CLK 29 +#define SE_GCC_FRQ_MEASURE_REF_CLK 30 +#define SE_GCC_GP1_CLK 31 +#define SE_GCC_GP1_CLK_SRC 32 +#define SE_GCC_GP2_CLK 33 +#define SE_GCC_GP2_CLK_SRC 34 +#define SE_GCC_GPLL0 35 +#define SE_GCC_GPLL0_OUT_EVEN 36 +#define SE_GCC_GPLL2 37 +#define SE_GCC_GPLL4 38 +#define SE_GCC_GPLL5 39 +#define SE_GCC_MMU_2_TCU_VOTE_CLK 40 +#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41 +#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42 +#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43 +#define SE_GCC_QUPV3_WRAP0_S0_CLK 44 +#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45 +#define SE_GCC_QUPV3_WRAP0_S1_CLK 46 +#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47 +#define SE_GCC_QUPV3_WRAP0_S2_CLK 48 +#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49 +#define SE_GCC_QUPV3_WRAP0_S3_CLK 50 +#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51 +#define SE_GCC_QUPV3_WRAP0_S4_CLK 52 +#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53 +#define SE_GCC_QUPV3_WRAP0_S5_CLK 54 +#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55 +#define SE_GCC_QUPV3_WRAP0_S6_CLK 56 +#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57 +#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58 +#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59 +#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60 +#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61 +#define SE_GCC_QUPV3_WRAP1_S0_CLK 62 +#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63 +#define SE_GCC_QUPV3_WRAP1_S1_CLK 64 +#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65 +#define SE_GCC_QUPV3_WRAP1_S2_CLK 66 +#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67 +#define SE_GCC_QUPV3_WRAP1_S3_CLK 68 +#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69 +#define SE_GCC_QUPV3_WRAP1_S4_CLK 70 +#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71 +#define SE_GCC_QUPV3_WRAP1_S5_CLK 72 +#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73 +#define SE_GCC_QUPV3_WRAP1_S6_CLK 74 +#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75 +#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76 + +/* SE_GCC power domains */ +#define SE_GCC_EMAC0_GDSC 0 +#define SE_GCC_EMAC1_GDSC 1 + +/* SE_GCC resets */ +#define SE_GCC_EMAC0_BCR 0 +#define SE_GCC_EMAC1_BCR 1 +#define SE_GCC_QUPV3_WRAPPER_0_BCR 2 +#define SE_GCC_QUPV3_WRAPPER_1_BCR 3 + +#endif From 6dcee295f5ca069fd072deaaceabae33f66694ad Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 9 Jun 2026 20:18:06 +0200 Subject: [PATCH 0953/1330] Fix multiple C source build errors from rebase - dp_ctrl.c: Remove duplicate msm_dp_ctrl_off_link (older version without MST support); keep the newer version matching qcom-linux - venus/core.c: Move sc8280xp_freq_table and sc8280xp_res inside the reference sm8350_reg_preset, sm8250_bw_table_enc/dec and VPU_VERSION_IRIS2 which are all guarded by the same #if - ath12k/wifi7/dp_rx.c: Fix 3-arg call to ath12k_dp_rx_check_nwifi_hdr_len_valid; add missing rx_desc argument to match the 4-parameter function signature - reboot-mode.c: Replace garbled hybrid file (mix of ubuntu rb_class approach and qcom-linux reboot_mode_sysfs_data approach) with clean qcom-linux version; the name field support is already included --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 22 --- drivers/media/platform/qcom/venus/core.c | 87 ++++++----- drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c | 2 +- drivers/power/reset/reboot-mode.c | 135 ++++++++++++------ 4 files changed, 138 insertions(+), 108 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 84238721ab548..6642c986c81fe 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2950,28 +2950,6 @@ void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl) phy, phy->init_count, phy->power_count); } -void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) -{ - struct msm_dp_ctrl_private *ctrl; - struct phy *phy; - - ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - phy = ctrl->phy; - - msm_dp_ctrl_mainlink_disable(ctrl); - - dev_pm_opp_set_rate(ctrl->dev, 0); - msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); - - DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n", - phy, phy->init_count, phy->power_count); - - phy_power_off(phy); - - DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n", - phy, phy->init_count, phy->power_count); -} - void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c index 64e6f87dbbe23..d8e3588b4b5f5 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -1127,6 +1127,49 @@ static const struct venus_resources sc7280_res = { .dec_nodename = "video-decoder", .enc_nodename = "video-encoder", }; + +static const struct freq_tbl sc8280xp_freq_table[] = { + { 0, 239999999 }, + { 0, 338000000 }, + { 0, 366000000 }, + { 0, 444000000 }, + { 0, 533000000 }, + { 0, 560000000 }, +}; + +static const struct venus_resources sc8280xp_res = { + .freq_tbl = sc8280xp_freq_table, + .freq_tbl_size = ARRAY_SIZE(sc8280xp_freq_table), + .reg_tbl = sm8350_reg_preset, + .reg_tbl_size = ARRAY_SIZE(sm8350_reg_preset), + .bw_tbl_enc = sm8250_bw_table_enc, + .bw_tbl_enc_size = ARRAY_SIZE(sm8250_bw_table_enc), + .bw_tbl_dec = sm8250_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), + .clks = { "core", "iface" }, + .clks_num = 2, + .resets = { "core" }, + .resets_num = 1, + .vcodec0_clks = { "vcodec0_core" }, + .vcodec_clks_num = 1, + .vcodec_pmdomains = (const char *[]) { "venus", "vcodec0" }, + .vcodec_pmdomains_num = 2, + .opp_pmdomain = (const char *[]) { "mx", NULL }, + .vcodec_num = 1, + .max_load = 7833600, /* 7680x4320@60fps */ + .hfi_version = HFI_VERSION_6XX, + .vpu_version = VPU_VERSION_IRIS2, + .num_vpp_pipes = 4, + .vmem_id = VIDC_RESOURCE_NONE, + .vmem_size = 0, + .vmem_addr = 0, + .dma_mask = GENMASK(31, 29) - 1, + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + .fwname = "qcom/vpu-2.0/venus.mbn", +}; #endif static const struct bw_tbl qcm2290_bw_table_dec[] = { @@ -1178,50 +1221,6 @@ static const struct venus_resources qcm2290_res = { .min_fw = &min_fw, }; -static const struct freq_tbl sc8280xp_freq_table[] = { - { 0, 239999999 }, - { 0, 338000000 }, - { 0, 366000000 }, - { 0, 444000000 }, - { 0, 533000000 }, - { 0, 560000000 }, -}; - -static const struct venus_resources sc8280xp_res = { - .freq_tbl = sc8280xp_freq_table, - .freq_tbl_size = ARRAY_SIZE(sc8280xp_freq_table), - .reg_tbl = sm8350_reg_preset, - .reg_tbl_size = ARRAY_SIZE(sm8350_reg_preset), - .bw_tbl_enc = sm8250_bw_table_enc, - .bw_tbl_enc_size = ARRAY_SIZE(sm8250_bw_table_enc), - .bw_tbl_dec = sm8250_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), - .clks = { "core", "iface" }, - .clks_num = 2, - .resets = { "core" }, - .resets_num = 1, - .vcodec0_clks = { "vcodec0_core" }, - .vcodec_clks_num = 1, - .vcodec_pmdomains = (const char *[]) { "venus", "vcodec0" }, - .vcodec_pmdomains_num = 2, - .opp_pmdomain = (const char *[]) { "mx", NULL }, - .vcodec_num = 1, - .max_load = 7833600, /* 7680x4320@60fps */ - .hfi_version = HFI_VERSION_6XX, - .vpu_version = VPU_VERSION_IRIS2, - .num_vpp_pipes = 4, - .vmem_id = VIDC_RESOURCE_NONE, - .vmem_size = 0, - .vmem_addr = 0, - .dma_mask = GENMASK(31, 29) - 1, - .cp_start = 0, - .cp_size = 0x25800000, - .cp_nonpixel_start = 0x1000000, - .cp_nonpixel_size = 0x24800000, - .fwname = "qcom/vpu-2.0/venus.mbn", -}; - - static const struct of_device_id venus_dt_match[] = { { .compatible = "qcom,msm8916-venus", .data = &msm8916_res, }, { .compatible = "qcom,msm8996-venus", .data = &msm8996_res, }, diff --git a/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c b/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c index 0407536c92cd5..1e280234b9412 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c @@ -1030,7 +1030,7 @@ static int ath12k_wifi7_dp_rx_h_verify_tkip_mic(struct ath12k_pdev_dp *dp_pdev, RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; skb_pull(msdu, hal_rx_desc_sz); - if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(dp, msdu, + if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(dp, rx_desc, msdu, rx_info))) { dev_kfree_skb_any(msdu); return -EINVAL; diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c index d1e3b81f889b7..0b9179100335f 100644 --- a/drivers/power/reset/reboot-mode.c +++ b/drivers/power/reset/reboot-mode.c @@ -15,6 +15,7 @@ #include #include #include +#include #define PREFIX "mode-" @@ -24,7 +25,53 @@ struct mode_info { struct list_head list; }; -static struct class *rb_class; +struct reboot_mode_sysfs_data { + struct device *reboot_mode_device; + struct list_head head; +}; + +static inline void reboot_mode_release_list(struct reboot_mode_sysfs_data *priv) +{ + struct mode_info *info; + struct mode_info *next; + + list_for_each_entry_safe(info, next, &priv->head, list) { + list_del(&info->list); + kfree_const(info->mode); + kfree(info); + } +} + +static ssize_t reboot_modes_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct reboot_mode_sysfs_data *priv; + struct mode_info *sysfs_info; + ssize_t size = 0; + + priv = dev_get_drvdata(dev); + if (!priv) + return -ENODATA; + + list_for_each_entry(sysfs_info, &priv->head, list) + size += sysfs_emit_at(buf, size, "%s ", sysfs_info->mode); + + if (!size) + return -ENODATA; + + return size + sysfs_emit_at(buf, size - 1, "\n"); +} +static DEVICE_ATTR_RO(reboot_modes); + +static struct attribute *reboot_mode_attrs[] = { + &dev_attr_reboot_modes.attr, + NULL, +}; +ATTRIBUTE_GROUPS(reboot_mode); + +static const struct class reboot_mode_class = { + .name = "reboot-mode", + .dev_groups = reboot_mode_groups, +}; static u64 get_reboot_mode_magic(struct reboot_mode_driver *reboot, const char *cmd) { @@ -68,9 +115,10 @@ static int reboot_mode_notify(struct notifier_block *this, return NOTIFY_DONE; } -static ssize_t reboot_modes_show(struct device *dev, struct device_attribute *attr, char *buf) +static int reboot_mode_create_device(struct reboot_mode_driver *reboot) { - struct reboot_mode_driver *reboot; + struct reboot_mode_sysfs_data *priv; + struct mode_info *sysfs_info; struct mode_info *info; const char *dev_name; int ret; @@ -86,12 +134,23 @@ static ssize_t reboot_modes_show(struct device *dev, struct device_attribute *at if (!priv) return -ENOMEM; - list_for_each_entry(info, &reboot->head, list) - size += sysfs_emit_at(buf, size, "%s ", info->mode); + INIT_LIST_HEAD(&priv->head); + + list_for_each_entry(info, &reboot->head, list) { + sysfs_info = kzalloc_obj(*sysfs_info, GFP_KERNEL); + if (!sysfs_info) { + ret = -ENOMEM; + goto error; + } - if (size) { - size += sysfs_emit_at(buf, size - 1, "\n"); - return size; + sysfs_info->mode = kstrdup_const(info->mode, GFP_KERNEL); + if (!sysfs_info->mode) { + kfree(sysfs_info); + ret = -ENOMEM; + goto error; + } + + list_add_tail(&sysfs_info->list, &priv->head); } priv->reboot_mode_device = device_create(&reboot_mode_class, NULL, 0, @@ -102,16 +161,11 @@ static ssize_t reboot_modes_show(struct device *dev, struct device_attribute *at goto error; } - reboot->reboot_dev = device_create(rb_class, NULL, 0, (void *)reboot, reboot->driver_name); - if (IS_ERR(reboot->reboot_dev)) - return PTR_ERR(reboot->reboot_dev); - - ret = device_create_file(reboot->reboot_dev, &dev_attr_reboot_modes); - if (ret) { - device_unregister(reboot->reboot_dev); - return ret; - } + return 0; +error: + reboot_mode_release_list(priv); + kfree(priv); return ret; } @@ -125,7 +179,6 @@ static ssize_t reboot_modes_show(struct device *dev, struct device_attribute *at int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle *fwnode) { struct mode_info *info; - struct mode_info *next; struct device_node *np; struct property *prop; size_t len = strlen(PREFIX); @@ -133,17 +186,13 @@ int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle u32 magic_arg2; int ret; - if (!fwnode || !reboot->driver_name) + if (!fwnode) return -EINVAL; np = to_of_node(fwnode); if (!np) return -EINVAL; - ret = create_reboot_mode_device(reboot); - if (ret) - return ret; - INIT_LIST_HEAD(&reboot->head); for_each_property_of_node(np, prop) { @@ -171,12 +220,12 @@ int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle info->mode = kstrdup_const(prop->name + len, GFP_KERNEL); if (!info->mode) { ret = -ENOMEM; - goto err_info; + goto error; } else if (info->mode[0] == '\0') { kfree_const(info->mode); ret = -EINVAL; pr_err("invalid mode name(%s): too short!\n", prop->name); - goto err_info; + goto error; } list_add_tail(&info->list, &reboot->head); @@ -185,19 +234,15 @@ int reboot_mode_register(struct reboot_mode_driver *reboot, struct fwnode_handle reboot->reboot_notifier.notifier_call = reboot_mode_notify; register_reboot_notifier(&reboot->reboot_notifier); + ret = reboot_mode_create_device(reboot); + if (ret) + goto error; + return 0; -err_info: - kfree(info); error: - list_for_each_entry_safe(info, next, &reboot->head, list) { - list_del(&info->list); - kfree_const(info->mode); - kfree(info); - } - - device_remove_file(reboot->reboot_dev, &dev_attr_reboot_modes); - device_unregister(reboot->reboot_dev); + kfree(info); + reboot_mode_unregister(reboot); return ret; } EXPORT_SYMBOL_GPL(reboot_mode_register); @@ -250,10 +295,8 @@ int reboot_mode_unregister(struct reboot_mode_driver *reboot) struct mode_info *info; struct mode_info *next; - if (!reboot->reboot_dev) - return -EINVAL; - unregister_reboot_notifier(&reboot->reboot_notifier); + reboot_mode_unregister_device(reboot); list_for_each_entry_safe(info, next, &reboot->head, list) { list_del(&info->list); @@ -261,8 +304,6 @@ int reboot_mode_unregister(struct reboot_mode_driver *reboot) kfree(info); } - device_remove_file(reboot->reboot_dev, &dev_attr_reboot_modes); - device_unregister(reboot->reboot_dev); return 0; } EXPORT_SYMBOL_GPL(reboot_mode_unregister); @@ -292,7 +333,6 @@ int devm_reboot_mode_register(struct device *dev, if (!dr) return -ENOMEM; - reboot->driver_name = reboot->dev->driver->name; rc = reboot_mode_register(reboot, of_fwnode_handle(reboot->dev->of_node)); if (rc) { devres_free(dr); @@ -330,6 +370,19 @@ void devm_reboot_mode_unregister(struct device *dev, } EXPORT_SYMBOL_GPL(devm_reboot_mode_unregister); +static int __init reboot_mode_init(void) +{ + return class_register(&reboot_mode_class); +} + +static void __exit reboot_mode_exit(void) +{ + class_unregister(&reboot_mode_class); +} + +subsys_initcall(reboot_mode_init); +module_exit(reboot_mode_exit); + MODULE_AUTHOR("Andy Yan "); MODULE_DESCRIPTION("System reboot mode core library"); MODULE_LICENSE("GPL v2"); From e58179d6b4760880275198bc2c1b764e24259ec3 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Wed, 10 Jun 2026 09:28:05 +0200 Subject: [PATCH 0954/1330] drm/msm/dp: adapt dp_mst_drm to older DRM private state API Ubuntu kernel (7.0) still uses old 4-argument drm_atomic_private_obj_init() and drm_private_state_funcs without atomic_create_state hook. Remove msm_dp_mst_create_bridge_state and atomic_create_state hook. Allocate initial state inline and pass it as 3rd arg to the old 4-arg drm_atomic_private_obj_init(). This fix needs to be re-applied whenever the ubuntu base kernel is rebased, as long as it predates the DRM atomic_create_state API. --- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/dp_mst_drm.c index a6cf700378f1d..f6337b7a532bf 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -84,22 +84,9 @@ static void msm_dp_mst_destroy_bridge_state(struct drm_private_obj *obj, kfree(mst_bridge_state); } -static struct drm_private_state * -msm_dp_mst_create_bridge_state(struct drm_private_obj *obj) -{ - struct msm_dp_mst_bridge_state *mst_bridge_state; - - mst_bridge_state = kzalloc_obj(*mst_bridge_state); - if (!mst_bridge_state) - return ERR_PTR(-ENOMEM); - __drm_atomic_helper_private_obj_create_state(obj, &mst_bridge_state->base); - - return &mst_bridge_state->base; -} static const struct drm_private_state_funcs msm_dp_mst_bridge_state_funcs = { - .atomic_create_state = msm_dp_mst_create_bridge_state, .atomic_duplicate_state = msm_dp_mst_duplicate_bridge_state, .atomic_destroy_state = msm_dp_mst_destroy_bridge_state, }; @@ -471,8 +458,18 @@ int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, struct drm_encoder *enc goto end; } - drm_atomic_private_obj_init(dev, &bridge->obj, - &msm_dp_mst_bridge_state_funcs); + { + struct msm_dp_mst_bridge_state *init_state; + + init_state = kzalloc(sizeof(*init_state), GFP_KERNEL); + if (!init_state) { + rc = -ENOMEM; + goto end; + } + drm_atomic_private_obj_init(dev, &bridge->obj, + &init_state->base, + &msm_dp_mst_bridge_state_funcs); + } drm_dbg_dp(dp_display->drm_dev, "MST drm bridge init. bridge id:%d\n", i); From ac54199c30e869907e5361522b9a9745af3787bf Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Tue, 19 May 2026 17:40:19 +0800 Subject: [PATCH 0955/1330] PENDING: media: qcom: iris: move hwmode setup into power_on_hw sequence Call iris_genpd_set_hwmode() directly in iris_vpu_power_on_hw() instead of relying on the set_hwmode vpu_op callback. This ensures hwmode is configured as part of the power-on sequence with proper error handling, including unwinding the AHB clock on failure. Remove set_hwmode from iris_vpu3_ops since it is now handled in the common power-on path. Add a NULL check in iris_vpu_switch_to_hwmode() to safely handle platforms that do not implement this op. Signed-off-by: Wangao Wang Signed-off-by: Kuba Pawlak --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 1 - drivers/media/platform/qcom/iris/iris_vpu_common.c | 9 +++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 60359d45ed981..ba93c25e9363c 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -420,7 +420,6 @@ const struct vpu_ops iris_vpu3_ops = { .power_off_controller = iris_vpu_power_off_controller, .power_on_controller = iris_vpu_power_on_controller, .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, - .set_hwmode = iris_vpu_set_hwmode, }; const struct vpu_ops iris_vpu3_purwa_ops = { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index c96c02862aeec..215ed79ab2339 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -291,8 +291,14 @@ int iris_vpu_power_on_hw(struct iris_core *core) if (ret && ret != -ENOENT) goto err_disable_hw_clock; + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); + if (ret) + goto err_disable_hw_ahb_clock; + return 0; +err_disable_hw_ahb_clock: + iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: @@ -308,6 +314,9 @@ int iris_vpu_set_hwmode(struct iris_core *core) int iris_vpu_switch_to_hwmode(struct iris_core *core) { + if (!core->iris_platform_data->vpu_ops->set_hwmode) + return 0; + return core->iris_platform_data->vpu_ops->set_hwmode(core); } From 42af4faca7824e7e742e898693c21bd44e936270 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 14 May 2026 17:39:01 +0800 Subject: [PATCH 0956/1330] WORKAROUND: phy: qcom: qmp-pcie: add x1e80100 qref supplies All PCIe PHYs on the X1E80100 SOC require the vdda-qref, which feeds QREF clocks provided by the TCSR device. Hence, restore the vdda-qref request for the 6th and the 3th PCIe instance by reverting commit 031b46b4729b ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies") and commit eb7a22f830f6("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supply"). For the 4th PCIe instance (Gen3 x2), add a new driver data entry, namely x1e80100_qmp_gen3x2_pciephy_cfg, which is a copy of sm8550_qmp_gen3x2_pciephy_cfg but uses sm8550_qmp_phy_vreg_l instead. Workaround will be reverted once the vote qref regulator for PCIe available in upstream. Fixes: eb7a22f830f6 ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies") Fixes: 031b46b4729b ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies") Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") Cc: Johan Hovold Cc: Abel Vesa Signed-off-by: Wenbin Yao Signed-off-by: Qiang Yu Signed-off-by: Ziyue Zhang Signed-off-by: Kuba Pawlak --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index ef652918704b3..86e71ff796d9e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4524,8 +4524,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4556,8 +4556,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4591,8 +4591,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4624,8 +4624,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, From 28a7591716b4c3a5ee37f5d63aa1d90edba47f12 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 26 May 2026 15:53:18 +0530 Subject: [PATCH 0957/1330] FROMLIST: spi: qcom-geni: Fix cs_change handling on the last transfer Commit b99181cdf9fa ("spi-geni-qcom: remove manual CS control") introduced automatic CS control via the FRAGMENTATION bit, but missed the case where cs_change is set on the last transfer in a message. For the last transfer, cs_change means that CS should remain asserted after the message completes. Since GENI SPI controls CS through FRAGMENTATION, set FRAGMENTATION for this case as well as for non-last transfers where cs_change is not set. Additionally, setup_gsi_xfer() was storing FRAGMENTATION (BIT(2) = 4) in peripheral.fragmentation, which is a boolean field consumed by gpi_create_spi_tre() via u32_encode_bits(..., TRE_SPI_GO_FRAG). Storing 4 causes u32_encode_bits to mask it to 0, silently disabling the FRAG bit in the GPI TRE regardless of the cs_change logic. Store 1 instead. Without these fixes, TPM TIS SPI transfers deassert CS between single-transfer messages that use cs_change to keep CS asserted across the header, wait-state, and data phases, breaking TCG SPI flow control: tpm_tis_spi: probe of spi11.0 failed with error -110 Update both setup_se_xfer() and setup_gsi_xfer() to handle this condition. Link: https://lore.kernel.org/all/20260529-fix-spi-fragmentation-bit-logic-v1-1-3b30f1a3dd7d@oss.qualcomm.com/ Fixes: b99181cdf9fa ("spi-geni-qcom: remove manual CS control") Cc: stable@vger.kernel.org Signed-off-by: Viken Dadhaniya Signed-off-by: Kuba Pawlak --- drivers/spi/spi-geni-qcom.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index d5fb0edc8e0c8..ddae7daaee739 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -440,10 +440,15 @@ static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas return ret; } - if (!xfer->cs_change) { - if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) - peripheral.fragmentation = FRAGMENTATION; - } + /* + * Set fragmentation to keep CS asserted after this transfer when: + * - non-last transfer with cs_change=0: keep CS between chained transfers + * - last transfer with cs_change=1: keep CS asserted after the message + * (e.g. TPM TIS SPI uses cs_change=1 on single-transfer messages to + * keep CS asserted across header, wait-state and data phases) + */ + peripheral.fragmentation = list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers) ? + xfer->cs_change : !xfer->cs_change; if (peripheral.cmd & SPI_RX) { dmaengine_slave_config(mas->rx, &config); @@ -849,10 +854,16 @@ static int setup_se_xfer(struct spi_transfer *xfer, mas->cur_xfer_mode = GENI_SE_DMA; geni_se_select_mode(se, mas->cur_xfer_mode); - if (!xfer->cs_change) { - if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) - m_params = FRAGMENTATION; - } + /* + * Set FRAGMENTATION to keep CS asserted after this transfer when: + * - non-last transfer with cs_change=0: keep CS between chained transfers + * - last transfer with cs_change=1: keep CS asserted after the message + * (e.g. TPM TIS SPI uses cs_change=1 on single-transfer messages to + * keep CS asserted across header, wait-state and data phases) + */ + if (list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers) ? + xfer->cs_change : !xfer->cs_change) + m_params = FRAGMENTATION; /* * Lock around right before we start the transfer since our From e406699e8ae5131e4d8949339086ea1e5615f234 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Fri, 15 May 2026 11:53:23 +0530 Subject: [PATCH 0958/1330] FROMLIST: arm64: dts: qcom: hamoa-iot-evk: add MCP2518FD CAN on spi18 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the Microchip MCP2518FD CAN-FD controller on hamoa. The controller is connected via SPI18 and uses a 40 MHz oscillator. Link: https://lore.kernel.org/all/20260515-hamoa-spi-can-devicetree-v2-1-d0e922608065@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Viken Dadhaniya Signed-off-by: Kuba Pawlak --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 53915dd10a02d..9abf24c8017d3 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -29,6 +29,14 @@ pinctrl-names = "default"; }; + clocks { + mcp2518fd_osc: clock-40000000 { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + wcd938x: audio-codec { compatible = "qcom,wcd9385-codec"; @@ -1257,6 +1265,19 @@ }; }; +&spi18 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 68 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mcp2518fd_osc>; + spi-max-frequency = <14000000>; + microchip,xstbyen; + }; +}; + &swr0 { status = "okay"; From 9f2c18d466ad44263353b2b747da581cae28c618 Mon Sep 17 00:00:00 2001 From: Anvesh Jain P Date: Fri, 13 Mar 2026 18:14:48 +0530 Subject: [PATCH 0959/1330] FROMLIST: dt-bindings: embedded-controller: Add EC bindings for Qualcomm reference devices Add bindings for the EC firmware running on Hamoa/Purwa and Glymur reference devices. Link: https://lore.kernel.org/lkml/20260313-v04-add-driver-for-ec-v4-1-ca9d0efd62aa@oss.qualcomm.com/ Signed-off-by: Anvesh Jain P Signed-off-by: Kuba Pawlak --- .../embedded-controller/qcom,hamoa-ec.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml diff --git a/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml new file mode 100644 index 0000000000000..baa95f06644ae --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/qcom,hamoa-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hamoa Embedded Controller + +maintainers: + - Sibi Sankar + - Anvesh Jain P + +description: + Qualcomm Snapdragon based Hamoa/Purwa and Glymur reference devices have an + EC running on different MCU chips. The EC handles things like fan control, + temperature sensors, access to EC internal state changes. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,glymur-crd-ec + - qcom,hamoa-iot-evk-ec + - const: qcom,hamoa-crd-ec + - enum: + - qcom,hamoa-crd-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@76 { + compatible = "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... From f96b0543b433399beae76e6ce7490f35404322f6 Mon Sep 17 00:00:00 2001 From: Xueyao An Date: Thu, 12 Feb 2026 16:25:57 +0800 Subject: [PATCH 0960/1330] arm64: dts: qcom: hamoa-iot-som: Add firmware-name to QUPv3 nodes Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Xueyao An Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260212082558.2811953-1-xueyao.an@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 5d9af325c931e..6d369c319f84e 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -462,14 +462,20 @@ }; &qupv3_0 { + firmware-name = "qcom/x1e80100/qupv3fw.elf"; + status = "okay"; }; &qupv3_1 { + firmware-name = "qcom/x1e80100/qupv3fw.elf"; + status = "okay"; }; &qupv3_2 { + firmware-name = "qcom/x1e80100/qupv3fw.elf"; + status = "okay"; }; From 4ce72ed05393fe530cc99aa680ee8df4d7fb8028 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Fri, 12 Jun 2026 10:21:27 +0200 Subject: [PATCH 0961/1330] soc: qcom: geni-se: Initialize wrapper AHB master CGC in geni_se_resources_on On platforms using Linux-side SE firmware loading (indicated by firmware-name DT property), TrustZone may skip the QUP wrapper hardware initialization that sets QUPV3_SE_AHB_M_CFG.AHB_M_CLK_CGC_ON. Without this bit, the AHB master clock path to SE registers is disabled, causing a synchronous external abort (bus error) when any SE driver attempts to read its protocol register via geni_se_read_proto(). This was observed on hamoa-iot-evk with spi18 (MCP2518FD CAN controller on QUPV3_2 SE2): the probe crashed with: spi_geni_init+0x44: synchronous external abort: 0000000096000010 geni_load_se_fw() already sets this bit but only after the protocol read, creating a chicken-and-egg problem. Fix this by setting AHB_M_CLK_CGC_ON in geni_se_resources_on() so SE registers are accessible immediately after clocks are enabled. Setting this bit is idempotent and harmless on platforms where TZ already set it. Also fix spi_geni_init() to properly check and propagate the return value of pm_runtime_get_sync(), preventing a silent runtime_resume failure from causing a subsequent bus error. Signed-off-by: Kuba Pawlak Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/soc/qcom/qcom-geni-se.c | 12 ++++++++++++ drivers/spi/spi-geni-qcom.c | 6 +++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 1a60832ace168..94cfd2dc9b00f 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -647,6 +647,18 @@ int geni_se_resources_on(struct geni_se *se) if (ret) return ret; + /* + * Enable hardware-controlled AHB master clock gating on the wrapper. + * On platforms using Linux-side SE firmware loading (firmware-name DT + * property), TZ may not initialize this register, leaving the AHB + * master path to SE registers disabled. Setting this bit here ensures + * SE registers are accessible after clocks are enabled, regardless of + * whether TZ or Linux loaded the firmware. + */ + if (se->wrapper) + geni_setbits32(se->wrapper->base + QUPV3_SE_AHB_M_CFG, + AHB_M_CLK_CGC_ON); + ret = pinctrl_pm_select_default_state(se->dev); if (ret) geni_se_clks_off(se); diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index ddae7daaee739..248c874094641 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -604,7 +604,11 @@ static int spi_geni_init(struct spi_geni_master *mas) u32 spi_tx_cfg, fifo_disable; int ret = -ENXIO; - pm_runtime_get_sync(mas->dev); + ret = pm_runtime_get_sync(mas->dev); + if (ret < 0) { + pm_runtime_put_noidle(mas->dev); + return ret; + } proto = geni_se_read_proto(se); From e9de2e6335b13ed689742f031fa9838aca4a7886 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Fri, 12 Jun 2026 11:39:23 +0200 Subject: [PATCH 0962/1330] UBUNTU: [Config] Synchronize with Qualcomm config Signed-off-by: Kuba Pawlak --- debian.qcom/config/annotations | 51 ++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 47046ceda64dd..5c76bf0a15f37 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -264,7 +264,14 @@ CONFIG_ARM_TEGRA194_CPUFREQ policy<{'arm64': '-'}> CONFIG_ARM_TEGRA20_CPUFREQ policy<{'arm64': '-'}> CONFIG_ARM_TEGRA_DEVFREQ policy<{'arm64': '-'}> CONFIG_ARM_TI_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ATH10K_DFS_CERTIFIED policy<{'arm64': 'n'}> CONFIG_ATH11K_COREDUMP policy<{'arm64': '-'}> +CONFIG_ATH5K_TEST_CHANNELS policy<{'arm64': 'n'}> +CONFIG_ATH6KL_REGDOMAIN policy<{'arm64': 'n'}> +CONFIG_ATH9K_DFS_CERTIFIED policy<{'arm64': 'n'}> +CONFIG_ATH9K_TX99 policy<{'arm64': 'n'}> +CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING policy<{'arm64': 'n'}> +CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS policy<{'arm64': 'y'}> CONFIG_AX88179B policy<{'arm64': '-'}> CONFIG_AXI_DMAC policy<{'arm64': '-'}> CONFIG_BACKLIGHT_APPLE_DWI policy<{'arm64': '-'}> @@ -296,6 +303,11 @@ CONFIG_CEC_PIN policy<{'arm64': 'y', 'arm64-qco CONFIG_CEC_PIN_ERROR_INJ policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_CEC_STM32 policy<{'arm64': '-'}> CONFIG_CEC_TEGRA policy<{'arm64': '-'}> +CONFIG_CFG80211_CERTIFICATION_ONUS policy<{'arm64': 'y'}> +CONFIG_CFG80211_EXTRA_REGDB_KEYDIR policy<{'arm64': '""'}> +CONFIG_CFG80211_REG_CELLULAR_HINTS policy<{'arm64': 'n'}> +CONFIG_CFG80211_REG_RELAX_NO_IR policy<{'arm64': 'n'}> +CONFIG_CGROUP_FAVOR_DYNMODS policy<{'arm64': 'y'}> CONFIG_CHARGER_CPCAP policy<{'arm64': '-'}> CONFIG_CHARGER_SC2731 policy<{'arm64': '-'}> CONFIG_CIX_MBOX policy<{'arm64': '-'}> @@ -588,6 +600,20 @@ CONFIG_COMMON_CLK_ZYNQMP policy<{'arm64': '-'}> CONFIG_COMMON_RESET_HI3660 policy<{'arm64': '-'}> CONFIG_COMMON_RESET_HI6220 policy<{'arm64': '-'}> CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'arm64': '1', 'arm64-qcom-rt': '0'}> +CONFIG_CORESIGHT policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_CPU_DEBUG policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_CTI policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_DUMMY policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_LINKS_AND_SINKS policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_LINK_AND_SINK_TMC policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_SINK_ETBV10 policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_SINK_TPIU policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_SOURCE_ETM4X policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_STM policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_TNOC policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_TPDA policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_TPDM policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_TRBE policy<{'arm64': 'n'}> CONFIG_CPUMASK_OFFSTACK policy<{'arm64': '-'}> CONFIG_CRC7 policy<{'arm64': 'y'}> CONFIG_CRC_ITU_T policy<{'arm64': 'y'}> @@ -647,6 +673,10 @@ CONFIG_CRYPTO_DEV_TI_DTHEV2 policy<{'arm64': '-'}> CONFIG_CRYPTO_DEV_XILINX_TRNG policy<{'arm64': '-'}> CONFIG_CRYPTO_DEV_ZYNQMP_AES policy<{'arm64': '-'}> CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 policy<{'arm64': '-'}> +CONFIG_CRYPTO_USER_API policy<{'arm64': 'y'}> +CONFIG_CRYPTO_USER_API_AEAD policy<{'arm64': 'y'}> +CONFIG_CRYPTO_USER_API_HASH policy<{'arm64': 'y'}> +CONFIG_CRYPTO_USER_API_SKCIPHER policy<{'arm64': 'y'}> CONFIG_CV1800_MBOX policy<{'arm64': '-'}> CONFIG_CZNIC_PLATFORMS policy<{'arm64': '-'}> CONFIG_DEBUG_KERNEL_DC policy<{'arm64': '-'}> @@ -826,6 +856,7 @@ CONFIG_EEPROM_93CX6 policy<{'arm64': 'y'}> CONFIG_EFI_SBAT_FILE policy<{'arm64': '-'}> CONFIG_EINT_MTK policy<{'arm64': '-'}> CONFIG_EMAC_ROCKCHIP policy<{'arm64': '-'}> +CONFIG_ETM4X_IMPDEF_FEATURE policy<{'arm64': 'n'}> CONFIG_EXTCON_RTK_TYPE_C policy<{'arm64': '-'}> CONFIG_FB_IMX policy<{'arm64': '-'}> CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA policy<{'arm64': '-'}> @@ -957,6 +988,7 @@ CONFIG_I2C_OMAP policy<{'arm64': '-'}> CONFIG_I2C_OWL policy<{'arm64': '-'}> CONFIG_I2C_PXA policy<{'arm64': '-'}> CONFIG_I2C_PXA_SLAVE policy<{'arm64': '-'}> +CONFIG_I2C_QCOM_GENI policy<{'arm64': 'y'}> CONFIG_I2C_QUP policy<{'arm64': 'y'}> CONFIG_I2C_RCAR policy<{'arm64': '-'}> CONFIG_I2C_RIIC policy<{'arm64': '-'}> @@ -971,6 +1003,7 @@ CONFIG_I2C_TEGRA_BPMP policy<{'arm64': '-'}> CONFIG_I2C_VERSATILE policy<{'arm64': '-'}> CONFIG_I2C_XGENE_SLIMPRO policy<{'arm64': '-'}> CONFIG_I2C_XLP9XX policy<{'arm64': '-'}> +CONFIG_I6300ESB_WDT policy<{'arm64': 'y'}> CONFIG_IIO_STM32_LPTIMER_TRIGGER policy<{'arm64': '-'}> CONFIG_IIO_STM32_TIMER_TRIGGER policy<{'arm64': '-'}> CONFIG_IMX2_WDT policy<{'arm64': '-'}> @@ -1115,6 +1148,8 @@ CONFIG_LOG_BUF_SHIFT policy<{'arm64': '17'}> CONFIG_LSM_MMAP_MIN_ADDR policy<{'arm64': '32768'}> CONFIG_LS_EXTIRQ policy<{'arm64': '-'}> CONFIG_LS_SCFG_MSI policy<{'arm64': '-'}> +CONFIG_MACVLAN policy<{'arm64': 'y'}> +CONFIG_MACVTAP policy<{'arm64': 'y'}> CONFIG_MARVELL_CN10K_DDR_PMU policy<{'arm64': '-'}> CONFIG_MARVELL_CN10K_DPI policy<{'arm64': '-'}> CONFIG_MARVELL_CN10K_TAD_PMU policy<{'arm64': '-'}> @@ -1496,6 +1531,7 @@ CONFIG_PHY_TEGRA_XUSB policy<{'arm64': '-'}> CONFIG_PHY_TI_GMII_SEL policy<{'arm64': '-'}> CONFIG_PHY_XGENE policy<{'arm64': '-'}> CONFIG_PHY_XILINX_ZYNQMP policy<{'arm64': '-'}> +CONFIG_PID_IN_CONTEXTIDR policy<{'arm64': 'y'}> CONFIG_PINCTRL_AC5 policy<{'arm64': '-'}> CONFIG_PINCTRL_AIROHA policy<{'arm64': '-'}> CONFIG_PINCTRL_AMDISP policy<{'arm64': '-'}> @@ -1796,7 +1832,7 @@ CONFIG_QCOM_SOC_DEBUG policy<{'arm64': '-'}> CONFIG_QCOM_SPMI_ADC5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_ADC_TM5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_MBG_TM policy<{'arm64': '-'}> -CONFIG_QCOM_TGU policy<{'arm64': 'y'}> +CONFIG_QCOM_TGU policy<{'arm64': 'm'}> CONFIG_QCOM_WATCHDOG_BARK_TIME policy<{'arm64': '-'}> CONFIG_QCOM_WATCHDOG_IPI_PING policy<{'arm64': '-'}> CONFIG_QCOM_WATCHDOG_PET_TIME policy<{'arm64': '-'}> @@ -1951,6 +1987,7 @@ CONFIG_RZ_DMAC policy<{'arm64': '-'}> CONFIG_RZ_MTU3 policy<{'arm64': '-'}> CONFIG_RZ_MTU3_CNT policy<{'arm64': '-'}> CONFIG_S32G_WDT policy<{'arm64': '-'}> +CONFIG_SAMPLE_CORESIGHT_SYSCFG policy<{'arm64': 'n'}> CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': '-'}> CONFIG_SATA_RCAR policy<{'arm64': '-'}> CONFIG_SC27XX_ADC policy<{'arm64': '-'}> @@ -1971,6 +2008,7 @@ CONFIG_SDM_DISPCC_845 policy<{'arm64': 'y'}> CONFIG_SDM_GCC_845 policy<{'arm64': 'y'}> CONFIG_SDM_GPUCC_845 policy<{'arm64': 'y'}> CONFIG_SDM_VIDEOCC_845 policy<{'arm64': 'y'}> +CONFIG_SENSORS_AMC6821 policy<{'arm64': 'y'}> CONFIG_SENSORS_EMC2305 policy<{'arm64': 'y'}> CONFIG_SENSORS_MACSMC_HWMON policy<{'arm64': '-'}> CONFIG_SENSORS_QCOM_BCL policy<{'arm64': 'y'}> @@ -2387,6 +2425,7 @@ CONFIG_SYS_R9A09G056 policy<{'arm64': '-'}> CONFIG_SYS_R9A09G057 policy<{'arm64': '-'}> CONFIG_SYS_SUPPORTS_SH_CMT policy<{'arm64': '-'}> CONFIG_SYS_SUPPORTS_SH_TMU policy<{'arm64': '-'}> +CONFIG_TAP policy<{'arm64': 'y'}> CONFIG_TCG_TIS_SYNQUACER policy<{'arm64': '-'}> CONFIG_TEE_STMM_EFI policy<{'arm64': 'n'}> CONFIG_TEGRA186_GPC_DMA policy<{'arm64': '-'}> @@ -2469,6 +2508,7 @@ CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_WITHIN_SIZE policy<{'arm64': 'n', 'arm64- CONFIG_TURRIS_MOX_RWTM policy<{'arm64': '-'}> CONFIG_TURRIS_MOX_RWTM_KEYCTL policy<{'arm64': '-'}> CONFIG_TURRIS_SIGNING_KEY policy<{'arm64': '-'}> +CONFIG_ULTRASOC_SMB policy<{'arm64': 'n'}> CONFIG_USB_CDNS3_IMX policy<{'arm64': '-'}> CONFIG_USB_CDNS3_TI policy<{'arm64': '-'}> CONFIG_USB_DWC3_AM62 policy<{'arm64': '-'}> @@ -2511,7 +2551,12 @@ CONFIG_V4L2_H264 policy<{'arm64': '-'}> CONFIG_V4L2_ISP policy<{'arm64': '-'}> CONFIG_V4L2_JPEG_HELPER policy<{'arm64': '-'}> CONFIG_V4L2_VP9 policy<{'arm64': '-'}> +CONFIG_VCPU_STALL_DETECTOR policy<{'arm64': 'y'}> CONFIG_VFIO_FSL_MC policy<{'arm64': '-'}> +CONFIG_VHOST policy<{'arm64': 'y'}> +CONFIG_VHOST_IOTLB policy<{'arm64': 'y'}> +CONFIG_VHOST_NET policy<{'arm64': 'y'}> +CONFIG_VHOST_VSOCK policy<{'arm64': 'y'}> CONFIG_VIDEO_ALLEGRO_DVT policy<{'arm64': '-'}> CONFIG_VIDEO_AMD_ISP4_CAPTURE policy<{'arm64': '-'}> CONFIG_VIDEO_AMPHION_VPU policy<{'arm64': '-'}> @@ -2583,11 +2628,13 @@ CONFIG_VIDEO_TI_CAL policy<{'arm64': '-'}> CONFIG_VIDEO_TI_CAL_MC policy<{'arm64': '-'}> CONFIG_VIDEO_TI_J721E_CSI2RX policy<{'arm64': '-'}> CONFIG_VIDEO_WAVE_VPU policy<{'arm64': '-'}> +CONFIG_VIRTIO_VSOCKETS_COMMON policy<{'arm64': 'y'}> CONFIG_VISCONTI_WATCHDOG policy<{'arm64': '-'}> CONFIG_VMAP_PFN policy<{'arm64': '-'}> +CONFIG_VSOCKETS policy<{'arm64': 'y'}> CONFIG_W1_MASTER_MXC policy<{'arm64': '-'}> CONFIG_WLAN_VENDOR_BCMDHD policy<{'arm64': '-'}> -CONFIG_WQ_POWER_EFFICIENT_DEFAULT policy<{'arm64': 'y', 'arm64-qcom-rt': 'n'}> +CONFIG_WQ_POWER_EFFICIENT_DEFAULT policy<{'arm64': 'n'}> CONFIG_XE_VFIO_PCI policy<{'arm64': '-'}> CONFIG_XGENE_DMA policy<{'arm64': '-'}> CONFIG_XGENE_PMU policy<{'arm64': '-'}> From e086cf867396bb54f9c359e1b1dd0fffc7f58e67 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Fri, 12 Jun 2026 15:58:15 +0200 Subject: [PATCH 0963/1330] arm64: dts: qcom: hamoa: Disable spi18 and fix qupv3_2 firmware-name spi18 (MCP2518FD CAN at 0x888000, SE2 of QUPv3_2) causes a synchronous external abort (ESR 0x96000010, SLVERR from TZ firewall) when the spi_geni_qcom driver tries to read GENI_FW_REVISION_RO. TrustZone firmware on this hardware initialises uart21 (SE5 of QUPv3_2, the boot console) but does not grant non-secure access to SE2. Any attempt to read spi18 SE registers results in a hardware bus error. Additionally, remove firmware-name from the qupv3_2 wrapper node. The upstream commit cb7db0f4010f intentionally only added firmware-name to qupv3_0 and qupv3_1. qupv3_2 remains TZ-managed until TZ firmware is updated to support Linux-side SE firmware loading for that wrapper. Disable spi18 until TZ firmware is updated to allow non-secure access to QUPv3_2 SE2. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 17 +++++++---------- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 2 -- 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 9abf24c8017d3..1fbe272830cff 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -1265,17 +1265,14 @@ }; }; +/* + * spi18 (MCP2518FD CAN) is disabled because TrustZone firmware on this + * hardware does not grant Linux access to SE2 of QUPv3_2 (physical 0x888000). + * Probing spi18 causes a synchronous external abort (SLVERR) from TZ firewall. + * Re-enable once TZ firmware is updated to allow access to this SE. + */ &spi18 { - status = "okay"; - - can@0 { - compatible = "microchip,mcp2518fd"; - reg = <0>; - interrupts-extended = <&tlmm 68 IRQ_TYPE_LEVEL_LOW>; - clocks = <&mcp2518fd_osc>; - spi-max-frequency = <14000000>; - microchip,xstbyen; - }; + status = "disabled"; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 6d369c319f84e..478ab8df020a0 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -474,8 +474,6 @@ }; &qupv3_2 { - firmware-name = "qcom/x1e80100/qupv3fw.elf"; - status = "okay"; }; From d5bc14eaad59bcbc0faf5f1b7405371e6b43270a Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Sat, 13 Jun 2026 18:46:53 +0200 Subject: [PATCH 0964/1330] media: qcom: camss: csiphy: Remove obsolete PHY_TYPE_DPHY mode check The DTS now uses PHY_QCOM_CSI2_MODE_DPHY (= 0) from phy-qcom-mipi-csi2.h as the #phy-cells argument in the phys property, while the driver checked against PHY_TYPE_DPHY (= 10) from the generic phy.h, causing the probe to fail with -ENOTSUP on any CSIPHY that passes the DPHY mode. Align with qcom-next which removed this combo_mode argument parsing from msm_csiphy_subdev_init() entirely. The cfg.combo_mode field defaults to 0 (set in csiphy_subdev_init via hw_ops->init), matching DPHY mode. Fixes: qcom-camss probe failure: 'csiphy1 mode 0 not supported' Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/media/platform/qcom/camss/camss-csiphy.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index 886ea61c9ea7b..0dc1899e345fd 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -7,7 +7,6 @@ * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. * Copyright (C) 2016-2018 Linaro Ltd. */ -#include #include #include #include @@ -796,7 +795,6 @@ int msm_csiphy_subdev_init(struct camss *camss, { struct device *dev = camss->dev; struct of_phandle_args args; - u8 combo_mode; int idx; int ret; @@ -817,13 +815,6 @@ int msm_csiphy_subdev_init(struct camss *camss, if (!of_device_is_available(args.np)) goto put_np; - combo_mode = args.args[0]; - if (combo_mode != PHY_TYPE_DPHY) { - dev_err(dev, "%s mode %d not supported\n", csiphy->name, combo_mode); - ret = -EOPNOTSUPP; - goto put_np; - } - csiphy->phy = devm_phy_get(dev, csiphy->name); if (IS_ERR(csiphy->phy)) { ret = PTR_ERR(csiphy->phy); @@ -832,7 +823,6 @@ int msm_csiphy_subdev_init(struct camss *camss, csiphy->camss = camss; csiphy->id = id; - csiphy->cfg.combo_mode = combo_mode; csiphy->res = &res->csiphy; ret = phy_init(csiphy->phy); From a352fd58c920ff53f39998462b2353e470deece5 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Sat, 13 Jun 2026 22:53:04 +0200 Subject: [PATCH 0965/1330] phy: qcom-mipi-csi2-phy: Fix x1e80100 clock names to match DTS The x1e80100 csiphy DTS node uses clock-names "core" and "timer", but the driver was using "camnoc_axi", "cpas_ahb", "csiphy", "csiphy_timer", causing devm_clk_bulk_get to fail with -ENOENT and preventing qcom-mipi-csi2-phy from probing on hamoa. Fix by aligning the clock name array with what the DTS provides, matching the qcom-next reference implementation. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index f9f3451e9a5e1..b94b1d0f92678 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -335,8 +335,6 @@ static const struct mipi_csi2phy_hw_ops phy_qcom_mipi_csi2_ops_3ph_1_0 = { .lanes_disable = phy_qcom_mipi_csi2_lanes_disable, }; -static const struct mipi_csi2phy_clk_freq zero = { 0 }; - static const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy = { .freq = { 300000000, 400000000, 480000000 @@ -352,10 +350,8 @@ static const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy_timer = { }; static const char * const x1e_clks[] = { - "camnoc_axi", - "cpas_ahb", - "csiphy", - "csiphy_timer" + "core", + "timer" }; const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { @@ -373,11 +369,9 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { .num_supplies = 2, .clk_names = (const char **)x1e_clks, .num_clk = ARRAY_SIZE(x1e_clks), - .opp_clk = x1e_clks[2], - .timer_clk = x1e_clks[3], + .opp_clk = x1e_clks[0], + .timer_clk = x1e_clks[1], .clk_freq = { - zero, - zero, dphy_4nm_x1e_csiphy, dphy_4nm_x1e_csiphy_timer, }, From aba0bef3e490694ffd6e7668d0e2b4cd6d1b05d3 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 15 Jun 2026 14:24:34 +0200 Subject: [PATCH 0966/1330] UBUNTU: Ubuntu-qcom-7.0.0-1006.8 Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 1069 +++++++++++++++++++++++++++++++- debian.qcom/config/annotations | 2 - debian.qcom/reconstruct | 4 + 3 files changed, 1068 insertions(+), 7 deletions(-) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index b626b97896758..abe70f56d21da 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,10 +1,1069 @@ -linux-qcom (7.0.0-1006.8) UNRELEASED; urgency=medium +linux-qcom (7.0.0-1006.8) resolute; urgency=medium - CHANGELOG: Do not edit directly. Autogenerated at release. - CHANGELOG: Use the printchanges target to see the current changes. - CHANGELOG: Use the insertchanges target to create the final log. + * resolute/linux-qcom: 7.0.0-1006.8 -proposed tracker (LP: #2154429) - -- Kuba Pawlak Fri, 29 May 2026 11:23:21 +0200 + * Packaging resync (LP: #1786013) + - [Packaging] update Ubuntu.md + + * Miscellaneous Ubuntu changes + - [Config] Synchronize with Qualcomm config + + * Miscellaneous upstream changes + - FROMGIT: regulator: rpmh-regulator: Add support for new resource name + format + - FROMLIST: media: qcom: venus: drop extra padding in NV12 raw size + calculation + - FROMLIST: media: qcom: venus: relax encoder frame/blur dimension steps + on v4 + - FROMLIST: media: qcom: venus: relax encoder frame/blur step size on v6 + - FROMLIST: media: qcom: iris: increase H265D_MAX_SLICE to fix H.265 + decoding on SC7280 + - FROMLIST: media: qcom: venus: flip the venus/iris switch + - FROMLIST: media: iris: add FPS calculation and VPP FW overhead in + frequency formula + - QCLINUX: qcom-dcc: add logic to configure linked list in probe + - QCLINUX: qcom-dcc: add register list for the Talos + - QCLINUX: qcom-dcc: use late_initcall and build as built-in for boot + debug + - QCLINUX: memory-dump: use late_initcall and build as built-in for boot + debug + - PENDING: media: iris: enable sm8550 context banks via init_cb_devs + - PENDING: media: iris: add context bank devices using iommu-map + - PENDING: media: iris: add helper to select context bank device + - PENDING: dt-bindings: media: iris: add sm8550 iris context bank function + IDs + - FROMLIST: media: iris: switch to hardware mode after firmware boot + - FROMLIST: media: qcom: iris: drop pas_id from the iris_platform_data + struct + - FROMLIST: media: qcom: iris: use common set_preset_registers function + - FROMLIST: media: qcom: iris: don't use function indirection in + gen2-specific code + - FROMLIST: media: qcom: iris: split HFI session ops from core ops + - FROMLIST: media: qcom: iris: merge hfi_response_ops and hfi_command_ops + - FROMLIST: media: qcom: iris: move get_instance to iris_hfi_sys_ops + - FROMLIST: media: qcom: iris: drop hw_response_timeout_val from platform + data + - FROMLIST: media: qcom: iris: split firmware_data from raw platform data + - FROMLIST: media: qcom: iris: split platform data from firmware data + - FROMLIST: media: qcom: iris: use new firmware name for SM8250 + - FROMLIST: media: qcom: iris: extract firmware description data + - FROMLIST: phy: qcom-qmp-ufs: Fix kaanapali PHY PLL lock failure after + SM8650 G4 fix + - FROMLIST: dt-bindings: media: qcom,sm8550-iris: Add X1P42100 compatible + - FROMLIST: media: iris: Add hardware power on/off ops for X1P42100 + - FROMLIST: media: iris: Add platform data for X1P42100 + - FROMLIST: iommu/arm-smmu-qcom: Fix fastrpc compatible string in ACTLR + client match table + - FROMLIST: of: Add convenience wrappers for of_map_id() + - FROMLIST: of: Factor arguments passed to of_map_id() into a struct + - FROMLIST: of: Respect #{iommu,msi}-cells in maps + - QCLINUX: qcom-dcc: add lemans register list and move config to header + - QCLINUX: qcom-dcc: move talos config to qcom-dcc-talos-config.h + - QCLINUX: qcom-dcc: group lemans and monaco SoC IDs with comments + - arm64: dts: qcom: sm8750: Add camera clock controller + - arm64: dts: qcom: sm8750-mtp: Enable display + - arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC + - QCLINUX: qcom-dcc: add kodiak register list and move config to header + - QCLINUX: qcom-dcc: add pakala register list and move config to header + - QCLINUX: arm64: dts: qcom: Add Hamoa camx overlay dts + - QCLINUX: arm64: dts: qcom: align hamoa camera DTB variable naming + - PENDING: arm64: dts: qcom: lemans-evk: add overlay for QPS615 ethernet + - PENDING: arm64: dts: qcom: monaco-evk: add overlay for QPS615 ethernet + - PENDING: arm64: dts: qcom: rb3gen2: add overlay for QPS615 ethernet + - PEDNING: arm64: dts: qcom: qcs6490-rb3gen2: fix root node overlay for + phy-vreg + - PENDING: arm64: qcom: dts: talos: add TGU device in staging dtso + - PENDING: arm64: dts: qcom: lemans: add TGU device in staging dtso + - PENDING: arm64: dts: qcom: monaco: add TGU device in staging dtso + - PENDING: arm64: dts: qcom: kodiak: add TGU device in staging dtso + - QCLINUX: arm64: dts: qcom: talos-evk: Switch to interrupt-cells 4 + - PENDING: arm64: dts: qcom: rb3gen2-industrial-mezzanine: add overlay for + QPS615 + - FROMLIST: pinctrl: qcom: lpass-lpi: Switch to PM clock framework for + runtime PM + - FROMLIST: pinctrl: qcom: lpass-lpi: Fix GPIO register access helper + return types + - FROMLIST: pinctrl: qcom: lpass-lpi: Resume clocks for GPIO access + - FROMLIST: ASoC: codecs: lpass-wsa-macro: Switch to PM clock framework + for runtime PM + - FROMLIST: ASoC: codecs: lpass-va-macro: Switch to PM clock framework for + runtime PM + - FROMLIST: ASoC: codecs: lpass-wsa-macro: Guard optional NPL clock rate + programming + - FROMLIST: pinctrl: qcom: lpass-lpi: Enable runtime PM hooks on remaining + SoCs + - FROMLIST: phy: dphy: Add lane_positions to DPHY config struct + - FROMLIST: phy: dphy: Add lane_polarities to DPHY config struct + - FROMLIST: phy: dphy: Add clock_lane_position to DPHY config struct + - FROMLIST: phy: dphy: Add clock_lane_polarity to DPHY config struct + - FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Describe iommu + entries + - FROMLIST: media: qcom: camss: Add support to populate sub-devices + - FROMLIST: arm64: dts: qcom: pm8350c: Enable Qualcomm BCL device + - FROMLIST: arm64: dts: qcom: pm7250b: Enable Qualcomm BCL device + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable 4-lane DisplayPort + Alt Mode + - QCLINUX: debug: Enable ATH11K CFR + - QCLINUX: qcom.config: Enable MMC_CRYPTO for ICE emmc + - QCLINUX: prune.config: Enable Realtek PHY config for Rb3Gen2 Industrial + board + - QCLINUX: qcom.config: Enable SYSFS config + - QCLINUX: prune.config: Disable MMU_500 CPRE ERRATA workaround for + Qualcomm SOC + - FROMLIST: arm64: dts: qcom: sm8750: Enable cpufreq cooling devices + - PENDING: arm64: dts: qcom: Add EL2 support for Iris for monaco + - FROMLIST: arm64: dts: qcom: monaco-evk: Extract common EVK hardware into + shared dtsi + - FROMLIST: dt-bindings: arm: qcom: Add monaco-ac-evk support + - FROMLIST: arm64: dts: qcom: monaco: Add monaco-ac EVK board + - WORKAROUND: arm64: dts: qcom: monaco-evk: Use refgen regulator for usb2 + HS PHY + - FROMLIST: arm64: dts: qcom: monaco: fix wrong connection for the + replicator + - FROMLIST: dt-bindings: clock: qcom: Add Glymur camera clock controller + - FROMLIST: clk: qcom: camcc-glymur: Add camera clock controller driver + - FROMLIST: cpuidle: Deny idle entry when CPU already have IPI interrupt + pending + - FROMLIST: dt-bindings: i2c: qcom,i2c-geni: Document multi-owner + controller support + - FROMLIST: dmaengine: qcom: gpi: Add lock/unlock TREs for multi-owner I2C + transfers + - FROMLIST: soc: qcom: geni-se: Keep pinctrl active for multi-owner + controllers + - FROMLIST: i2c: qcom-geni: Support multi-owner controllers in GPI mode + - WORKAROUND: i2c: qcom-geni: Fix -EACCES error during system resume + - FROMLIT: drm/display: add hw_params callback function to + drm_connector_hdmi_audio_ops + - FROMLIST: drm/msm/dp: fix HPD state status bit shift value + - FROMLIST:drm/msm/dp: Fix the ISR_* enum values + - FROMLIST:drm/msm/dp: Read DPCD and sink count in bridge detect() + - FROMLIST:drm/msm/dp: Move link training to atomic_enable() + - FROMLIST:drm/msm/dp: Drop EV_USER_NOTIFICATION + - FROMLIST:drm/msm/dp: drop event data + - FROMLIST:drm/msm/dp: rework HPD handling + - FROMLIST:drm/msm/dp: Add sink_count to debug logs + - FROMLIST:drm/msm/dp: turn link_ready into plugged + - FROMLIST:drm/msm/dp: clear EDID on display unplug + - FROMLIST: phy: qualcomm: qmp-combo: update DP PHY PLL programming on + Glymur + - FROMLIST: PCI: Introduce an API to check if RC/platform can retain + device context during suspend + - FROMLIST: PCI: Indicate context lost if L1ss exit is broken during + resume from system suspend + - FROMLIST: PCI: qcom: Indicate broken L1ss exit during resume from system + suspend + - FROMLIST: nvme-pci: Use pci_dev_suspend_retention_supported() API during + suspend + - FROMLIST: coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs read + operations + - FROMLIST: coresight: cti: encode trigger register index in register + offsets + - FROMLIST: coresight: cti: add Qualcomm extended CTI identification and + quirks + - FROMLIST: coresight: cti: expose banked sysfs registers for Qualcomm + extended CTI + - PENDING: arm64: dts: qcom: kaanapali: add the GPU SMMU node + - PENDING: arm64: dts: qcom: kaanapali: Add GPU support for Kaanapali + - PENDING: arm64: dts: qcom: kaanapali-qrd: Enable GPU + - PENDING: arm64: dts: qcom: kaanapali-mtp: Enable GPU + - FROMLIST: arm64: dts: qcom: kaanapali: Enable cpufreq cooling devices + - FROMLIST: serial: qcom_geni: fix kfifo underflow when flush precedes DMA + completion IRQ + - FROMLIST: drivers: soc: qcom: smem: Switch partitions to xarray + - dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk + - soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE + - arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node + - arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node + - arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node + - arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node + - arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node + - arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node + - arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node + - arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node + - arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node + - arm64: dts: qcom: kodiak: Fix ICE reg size + - arm64: dts: qcom: sm8450: Fix ICE reg size + - arm64: dts: qcom: kodiak: Add iface clock and power domain for ice sdhc + - arm64: dts: qcom: monaco: Add iface clock and power domain for ice sdhc + - FROMLIST: soc: qcom: ice: Add OPP-based clock scaling support for ICE + - FROMLIST: ufs: host: Add ICE clock scaling during UFS clock changes + - FROMLIST: mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init + - FROMLIST: arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE + eMMC nodes + - FROMLIST: arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE + eMMC nodes + - PENDING: arm64: dts: qcom: glymur: add TGU and ETR in staging dtso + - FROMLIST: phy: qcom: edp: Initialize swing_pre_emph_cfg for sc7280 + - FROMLIST: arm64: dts: qcom: install DT overlays via dtbs_install + - QCLINUX: arm64: dts: qcom: Install camx DTBO overlays + - FROMLIST: dt-bindings: embedded-controller: Add Qualcomm reference + device EC description + - FROMLIST: platform: arm64: Add driver for EC found on Qualcomm reference + devices + - FROMLIST: arm64: dts: qcom: Move board nodes to common DTSI + - FROMLIST: arm64: dts: glymur: Add LPASS macro codecs and pinctrl + - FROMLIST: arm64: dts: qcom: glymur-crd: add Audio sound card node + - PENDING: arm64: dts: qcom: Glymur GPU opp-supported-hw + - PENDING: arm64: dts: qcom: Glymur BW update + - FROMLIST: arm64: dts: qcom: glymur: Add remoteproc PAS loader for SoCCP + on Glymur DT + - FROMLIST: arm64: dts: qcom: glymur: Add iris video node + - FROMLIST: arm64: dts: qcom: glymur: Add psci reboot-mode edl + - WORKAROUND: arm64: dts: qcom: Mahua: Removing Qdss DSP node + - FROMLIST: arm64: defconfig: Enable Qualcomm reference device EC driver + - PENDING: arm64: dts: qcom: glymur: Removed the glymur-iris.h dt-bindings + dependency + - FROMLIST: arm64: dts: qcom: x1e80100: Add CCI definitions + - FROMLIST: arm64: dts: qcom: x1e80100-t14s: Add pm8010 camera PMIC with + voltage levels for IR and RGB camera + - FROMLIST: arm64: dts: qcom: x1e80100-t14s: Add on ov02c10 RGB sensor on + CSIPHY4 + - FROMLIST: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add ov02c10 RGB + sensor on CSIPHY4 + - FROMLIST: arm64: dts: qcom: x1e80100-dell-inspiron14-7441: Switch on + CAMSS RGB sensor + - FROMLIST: arm64: dts: qcom: purwa: Fix GPU IOMMU property + - FROMLIST: arm64: dts: qcom: purwa: Add camss node + - FROMLIST: arm64: dts: qcom: purwa-iot-evk: Add camss node + - FROMLIST: arm64: dts: qcom: x1-crd: Add Embedded controller node + - FROMLIST: arm64: dts: qcom: hamoa-iot-evk: Add Embedded controller node + - FROMLIST: arm64: dts: qcom: purwa: Override Iris clocks and operating + points + - FROMLIST: arm64: dts: qcom: purwa-iot-som: enable video + - PENDING: arm64: dts: qcom: hamoa: switch iris iommus to iommu-map + - PENDING: arm64: dts: qcom: glymur: removing iommu-map for iris video + - FROMLIST: arm64: dts: qcom: glymur: Mark USB SS1 and SS2 as role-switch + capable + - FROMLIST: arm64: dts: qcom: glymur-crd: Drop forced host mode for USB + SS0 and SS1 + - QCLINUX: arm64: dts: qcom: Add kodiak lite camx overlay dts + - QCLINUX: arm64: dts: qcom: Add kodiak lite camx overlay dts + - QCLINUX: arm64: dts: qcom: Add kodiak lite camx overlay dts + - FROMLIST: media: iris: Fix VM count passed to firmware + - FROMLIST: dt-bindings: media: qcom,glymur-iris: Add glymur video codec + - FROMLIST: media: iris: Rename clock and power domain macros to use + vcodec prefix + - FROMLIST: media: iris: Use power domain type to look up pd_devs index + - FROMLIST: media: iris: Add power sequence for Glymur + - FROMLIST: media: iris: Add support to select core for dual core + platforms + - FROMLIST: media: iris: Add platform data for glymur + - FROMLIST: drm/msm/dp: remove cached drm_edid from panel + - FROMLIST: drm/msm/dp: drop deprecated .mode_set() and use .atomic_enable + - FROMLIST: drm/msm/dp: break up dp_display_enable into two parts + - FROMLIST: drm/msm/dp: re-arrange dp_display_disable() into functional + parts + - FROMLIST: drm/msm/dp: splite msm_dp_ctrl_config_ctrl() into link parts + and stream parts + - FROMLIST: drm/msm/dp: extract MISC1_MISC0 configuration into a separate + function + - FROMLIST: drm/msm/dp: split link setup from source params + - FROMLIST: drm/msm/dp: allow dp_ctrl stream APIs to use any panel passed + to it + - FROMLIST: drm/msm/dp: move the pixel clock control to its own API + - FROMLIST: drm/msm/dp: split dp_ctrl_off() into stream and link parts + - FROMLIST: drm/msm/dp: make bridge helpers use dp_display to allow re-use + - FROMLIST: drm/msm/dp: separate dp_display_prepare() into its own API + - FROMLIST: drm/msm/dp: introduce stream_id for each DP panel + - FROMLIST: drm/msm/dp: introduce max_streams for DP controller MST + support + - FROMLIST: drm/msm/dp: Add support for programming p1/p2/p3 register + blocks + - FROMLIST: drm/msm/dp: use stream_id to change offsets in dp_catalog + - FROMLIST: drm/msm/dp: Add catalog support for 3rd/4th stream MST + - FROMLIST: drm/msm/dp: add support to send ACT packets for MST + - FROMLIST: drm/msm/dp: Add support to enable MST in mainlink control + - FROMLIST: drm/msm/dp: no need to update tu calculation for mst + - FROMLIST: drm/msm/dp: Add support for MST channel slot allocation + - FROMLIST: drm/msm/dp: Add support for sending VCPF packets in DP + controller + - FROMLIST: drm/msm/dp: Always program MST_FIFO_CONSTANT_FILL for MST use + cases + - FROMLIST: drm/msm/dp: simplify link and clock disable sequence + - FROMLIST: drm/msm/dp: pass panel to display enable/disable helpers + - FROMLIST: drm/msm/dp: abstract out the dp_display stream helpers to + accept a panel + - FROMLIST: drm/msm/dp: replace power_on with active_stream_cnt for + dp_display + - FROMLIST: drm/msm/dp: Mark the SST bridge disconnected when mst is + active + - FROMLIST: drm/msm/dp: add an API to initialize MST on sink side + - FROMLIST: drm/msm/dp: add dp_display_get_panel() to initialize DP panel + - FROMLIST: drm/msm/dp: add prepared to manage link-level operations + - FROMLIST: drm/msm/dpu: initialize encoders per stream for DP MST + - FROMLIST: drm/msm/dp: initialize dp_mst module for each DP MST + controller + - QCLINUX: arm64: dts: qcom: Add Purwa camx overlay dts + - FROMLIST: dt-bindings: remoteproc: qcom: cleanup qcom,adsp.yaml + - FROMLIST: dt-bindings: remoteproc: qcom: move interrupts and interrupt- + names list out of pas-common + - FROMLIST: dt-bindings: remoteproc: qcom: Document pas for SoCCP on + Kaanapali and Glymur platforms + - FROMLIST: remoteproc: qcom: pas: Add late attach support for subsystems + - FROMLIST: remoteproc: qcom_q6v5_pas: Add SoCCP node on Kaanapali + - PENDING: arm64: dts: qcom: lemans: switch iris iommus to iommu-map + - PENDING: arm64: dts: qcom: lemans-ride: Drop video firmware from common + - WORKAROUND: arm64: dts: qcom: sc7280: avoid EFI overlap for ADSP remote + heap + - arm64: dts: qcom: kodiak: Add EL2 overlay + - arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller + - dt-bindings: arm: Document reboot mode magic + - FROMLIST: drm/msm/dp: add dp_mst_drm to manage DP MST bridge operations + - FROMLIST: drm/msm/dp: wire MST helpers into atomic check and commit + paths + - FROMLIST: drm/msm/dp: add connector abstraction for DP MST + - FROMLIST: drm/msm/dp: add HPD callback for dp MST + - FROMLIST: drm/msm/dpu: use msm_dp_get_mst_intf_id() to get the intf id + - FROMLIST: drm/msm/dp: Add MST stream support for SA8775P DP controller 0 + and 1 + - WORKAROUND: power: reset: reboot-mode: fix NULL deref when dev is not + set + - FROMLIST: wifi: ath12k: add channel 177 to the 5 GHz channel list + - FROMLIST: wifi: ath12k: fix peer_id usage in normal RX path + - FROMLIST: wifi: ath12k: fix TLV32 length mask + - FROMLIST: wifi: ath12k: refactor HAL TLV32/64 decode helpers + - FROMLIST: wifi: ath12k: add HAL ops for monitor TLV header decode and + alignment + - FROMLIST: wifi: ath12k: add dp_mon support 32-bit TLV headers + - FROMLIST: wifi: ath12k: tighten RX monitor TLV bounds check + - arm64: dts: qcom: shikra: Add TCSR mutex hwlock support + - arm64: dts: msm: add interconnect devices for Shikra + - arm64: dts: qcom: shikra: Add download mode support + - arm64: dts: qcom: Add QUPv3 UART console node for shikra + - arm64: dts: qcom: Add eMMC support for shikra SoC + - arm64: dts: qcom: Enable eMMC for shikra EVK + - arm64: dts: qcom: Add SD Card support for shikra SoC + - arm64: dts: qcom: Add USB changes for Shikra + - arm64: dts: qcom: shikra: Add cpufreq scaling node + - arm64: dts: qcom: shikra: Add SMP2P nodes + - arm64: dts: qcom: Enable primary usb controller on IQS platform + - arm64: dts: qcom: shikra: Enable TSENS and thermal zones + - arm64: dts: qcom: shikra: Add firmware-name to QUPv3 nodes + - arm64: dts: qcom: shikra: Add PMIC thermal and ADC support + - arm64: dts: qcom: Add DISPCC and GPUCC nodes support + - arm64: dts: qcom: Add clock nodes for adreno smmu + - arm64: dts: qcom: shikra: add WiFi node support + - arm64: dts: qcom: shikra: enable WiFi on EVK boards + - arm64: dts: qcom: shikra: Add Iris video codec node + - arm64: dts: qcom: shikra-evk: Enable Iris core + - arm64: dts: qcom: Add QUPv3 configuration for Shikra + - arm64: dts: qcom: shikra: enable USB-C port handling + - arm64: dts: qcom: shikra: correct RPM tags for iris interconnects + - arm64: dts: qcom: shikra: Add LLCC node + - arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes + - arm64: dts: qcom: shikra-cqm: Enable CDSP, LPAICP and MPSS + - arm64: dts: qcom: shikra-cqs: Enable CDSP and LPAICP + - arm64: dts: qcom: shikra-iqs: Enable CDSP and LPAICP + - arm64: dts: qcom: shikra: Enable cpufreq cooling devices + - dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC + - dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for Shikra + - dt-bindings: phy: qcom,qusb2: Add bindings for Shikra + - dt-bindings: usb: qcom,snps-dwc3: Add Shikra compatible + - phy: qcom-qusb2: Add support for Shikra + - phy: qcom: qmp-usbc: Add qmp configuration for Shikra + - dt-bindings: interconnect: document the RPM Network-On-Chip interconnect + in Shikra SoC + - interconnect: qcom: add Shikra interconnect provider driver + - arm64: defconfig: Enable interconnect driver for Shikra + - dt-bindings: mfd: qcom,tcsr: Add compatible for Shikra + - dt-bindings: mmc: sdhci-msm: Add compatible for shikra + - dt-bindings: cpufreq: qcom-hw: Document Shikra CPUFREQ Hardware + - cpufreq: qcom-cpufreq-hw: Add RIMPS based cpufreq support for Shikra SoC + - arm64: defconfig: Enable Pinctrl on Shikra EVK boards + - dt-bindings: thermal: qcom-tsens: Document the Shikra Temperature Sensor + - WORKAROUND:arm64: dts: glymur: Q6APM SID fixed + - FROMLIST: firmware: arm_scmi: Add QCOM Generic Vendor Protocol + documentation + - FROMLIST: firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions + - FROMLIST: PM / devfreq: Add new target_freq attribute flag for governors + - FROMLIST: PM / devfreq: Add new track_remote flag for governors + - FROMLIST: PM / devfreq: Add a governor for tracking remote device + frequencies + - FROMLIST: PM / devfreq: Introduce the QCOM SCMI Memlat devfreq device + - FROMLIST: arm64: dts: qcom: purwa: Add EL2 overlay for purwa-iot-evk + - FROMLIST: arm64: dts: qcom: glymur: add TRNG node + - FROMLIST: arm64: dts: qcom: glymur: Add crypto engine and BAM + - FROMLIST: dt-bindings: crypto: qcom,prng: Document Glymur TRNG + - FROMLIST: dt-bindings: crypto: qcom-qce: Document the Glymur crypto + engine + - FROMLIST: arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS dvfs + - FROMLIST: clk: qcom: gdsc: Add custom disable callback for GX GDSC + - FROMLIST: clk: qcom: gxclkctl: Use custom disable callback for gx_gdsc + - FROMLIST: clk: qcom: common: ensure runtime PM suspend completes on + probe + - FROMLIST: clk: qcom: gxclkctl: Remove GX/GMxC rail votes to align with + IFPC + - FROMLIST: arm64: dts: qcom: hamoa: Enable LLCC/DDR/DDR_QOS dvfs + - arm64: dts: qcom: shikra: update reserved memory regions + - arm64: dts: qcom: shikra: fix compatible field for iommu nodes + - arm64: dts: qcom: Modify MPM pin count for shikra + - arm64: dts: qcom: Update Min and max Voltages for Shikra Retail + - dt-bindings: clock: qcom: Add Shikra Display clock controller + - dt-bindings: clock: qcom: Add Shikra GPU clock controller + - clk: qcom: Add support for Display Clock Controller on Shikra + - clk: qcom: Add support for GPU Clock Controller on Shikra + - arm64: defconfig: Enable DISPCC and GPUCC on Shikra EVK boards + - pinctrl: qcom: Add GPIO-MPM map for shikra + - interconnect: qcom: shikra: program QoS mode for ICC masters + - dt-bindings: cache: qcom,llcc: Document Qualcomm Shikra LLCC + - FROMLIST: soc: qcom: smem: Switch partitions to xarray + - FROMLIST: pinctrl: qcom: Unconditionally mark gpio as wakeup enable + - remoteproc: qcom: pas: Add Shikra remoteproc support + - dt-bindings: remoteproc: qcom: Add Shikra PAS binding + - dt-bindings: clock: qcom: Add GCC_QUSB2PHY_SEC_BCR support for Shikra + - clk: qcom: gcc-shikra: Update GCC driver for Shikra + - clk: qcom: gpucc-shikra: Drop unused DT_BI_TCXO_AO index + - FROMLIST: wifi: ath12k: fix memory leak in + ath12k_wifi7_dp_rx_h_verify_tkip_mic() + - FROMLIST: wifi: ath11k: fix invalid data access in + ath11k_dp_rx_h_undecap_nwifi + - FROMLIST: wifi: ath11k: add MSDU length validation for TKIP MIC error + - FROMLIST: wifi: ath12k: allow peer_id 0 in dp peer lookup + - Bluetooth: hci_qca: Convert timeout from jiffies to ms + - QCLINUX: qcom.config: Enable QCOM SCMI memlat bus scaling + - WORKAROUND: arm64: dts: qcom: purwa-iot-evk: support Bluetooth over both + USB and UART + - FROMLIST: arm64: defconfig: Enable CAMCC driver on Qualcomm Glymur SoC + - dt-bindings: clock: qcom: shikra-gcc: Add power-domains property + - dt-bindings: mailbox: qcom: Modify Shikra APCS compatible + - misc: fastrpc: Introduce cache maintenance operations + - arm64: dts: qcom: shikra: Add CX power domain to GCC + - arm64: dts: qcom: Modify compatible for Shikra APCS device + - FROMLIST: media: qcom: camss: Add common TPG support + - FROMLIST: media: qcom: camss: Add link support for TPG + - FROMLIST: media: qcom: camss: tpg: Add TPG support for multiple targets + - FROMLIST: dt-bindings: media: Add bindings for qcom,x1p42100-camss + - FROMLIST: media: qcom: camss: add support for X1P42100 camss + - FROMLIST: arm64: dts: qcom: glymur: Add camera clock controller support + - dt-bindings: media: qcom,qcm2290-venus: document shikra Iris compatible + - arm64: dts: qcom: shikra: Add coresight nodes + - arm64: dts: qcom: shikra: Enable BT support on EVK boards. + - arm64: dts: qcom: shikra: Add MDSS display subsystem + - arm64: dts: qcom: shikra-cqm-evk: Enable display and add DLC0697 panel + - iommu/arm-smmu: Add ACTLR settings for missing MDSS devices for new + Shikra platform + - dt-bindings: display: msm: qcm2290: Add Shikra MDSS + - dt-bindings: display: panel: Add DLC0697 DSI panel binding + - drm/msm/mdss: Add Shikra support + - drm/panel: Add driver for DLC0697 FHD video-mode DSI panel + - arm64: defconfig: Enable DLC0697 DSI panel driver + - soc: qcom: ubwc: Add Shikra UBWC config + - ASoC: dt-bindings: Add schema for qcom,wsa885x-i2c + - ASoC: codecs: add Qualcomm WSA885X I2C codec driver + - arm64: defconfig: Enable WSA885X-I2C and PM4125 Shikra EVK boards + - FROMLIST: misc: fastrpc: Fix initial memory allocation for Audio PD + memory pool + - FROMLIST: misc: fastrpc: Remove buffer from list prior to unmap + operation + - FROMLIST: misc: fastrpc: Allocate entire reserved memory for Audio PD in + probe + - FROMLIST: misc: fastrpc: Allow fastrpc_buf_free() to accept NULL + - PENDING: dt-bindings: media: qcom: venus: add iommu-map support + - PENDING: media: qcom: venus: support PAS boot and flexible IOMMU + handling + - PENDING: arm64: dts: qcom: talos: enable video codec on Talos + - FROMLIST: media: dt-bindings: Add CAMSS device for SM8750 + - FROMLIST: media: qcom: camss: Add SM8750 compatible camss driver + - FROMLIST: media: qcom: camss: csiphy: Add support for v2.3.0 two-phase + CSIPHY + - FROMLIST: media: qcom: camss: csid: Add support for CSID 980 + - FROMLIST: media: qcom: camss: vfe: Add support for VFE 980 + - misc: fastrpc: fix NULL dereference on coherent sessions in + fastrpc_map_attach() + - Add qcom-next log files for 20260514 + - update configs after rebase + - arm64: dts: qcom: Add mahua-crd.dts (missed during rebase) + - arm64: dts: qcom: Fix DTS build errors from graduated upstream commits + - arm64: dts: qcom: monaco: Add lpass_tlmm pinctrl node (graduated + upstream) + - arm64: dts: qcom: hamoa: Restore camss/csiphy1/csiphy2 nodes (bad + conflict resolution) + - dt-bindings/phy + arm64: dts: qcom: hamoa: Add phy-qcom-mipi-csi2.h + - arm64: dts: qcom: Fix missing DTS/DTSO files and composite DTB + definitions + - arm64: dts: qcom: shikra: Add missing clocks block (xo_board, sleep_clk) + - arm64: dts: qcom: Fix duplicate camcc node and missing LED includes + - arm64: dts: qcom: sm8750-mtp: Resolve leftover cherry-pick conflict + - arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Restore cam_indicator_en + pinctrl + - regulator: qcom-rpmh: Restore missing struct definitions after double + cherry-pick + - soc: qcom: smem: Restore debugfs_dir field and smem_dram_parse support + - soc: qcom: ice: Add missing pm_runtime.h include + - FROMLIST: misc: fastrpc: fix UAF and kernel panic during cleanup on + process abort + - clk: qcom: nord: Add missing Nord GCC/TCSR clock source files and + headers + - clk: qcom: nord: Add missing nwgcc and segcc dt-bindings headers + - Fix multiple C source build errors from rebase + - drm/msm/dp: adapt dp_mst_drm to older DRM private state API + - PENDING: media: qcom: iris: move hwmode setup into power_on_hw sequence + - WORKAROUND: phy: qcom: qmp-pcie: add x1e80100 qref supplies + - FROMLIST: spi: qcom-geni: Fix cs_change handling on the last transfer + - FROMLIST: arm64: dts: qcom: hamoa-iot-evk: add MCP2518FD CAN on spi18 + - FROMLIST: dt-bindings: embedded-controller: Add EC bindings for Qualcomm + reference devices + - arm64: dts: qcom: hamoa-iot-som: Add firmware-name to QUPv3 nodes + - soc: qcom: geni-se: Initialize wrapper AHB master CGC in + geni_se_resources_on + - arm64: dts: qcom: hamoa: Disable spi18 and fix qupv3_2 firmware-name + - media: qcom: camss: csiphy: Remove obsolete PHY_TYPE_DPHY mode check + - phy: qcom-mipi-csi2-phy: Fix x1e80100 clock names to match DTS + + [ Ubuntu: 7.0.0-26.26 ] + + * resolute/linux: 7.0.0-26.26 -proposed tracker (LP: #2154530) + * Packaging resync (LP: #1786013) + - Revert "UBUNTU: SAUCE: import Huawei ES3000_V2 (2.1.0.23)" + - [Packaging] debian.master/dkms-versions -- remove dkms-versions + (main/2026.05.18) + * Fix mic mute led on a HP EliteBook 6 G2a platform (LP: #2150065) + - ALSA: hda/realtek: Add LED fixup for HP EliteBook 6 G2a Laptops + * ov08x40 module mounted upside down on a certain DELL platforms + (LP: #2146517) + - SAUCE: media: ipu-bridge: Add DMI quirk for new Dell XPS laptops with + upside down sensors + - SAUCE: media: ipu-bridge: Add DMI quirk for Dell 14 laptops with upside + down sensors + * Support additional 2888x1808@30fps 900MHz for OVTI05C1 camera sensor + (LP: #2147409) + - SAUCE: media: ipu-bridge: Add 900MHz for OV05C10 + - SAUCE: platform/x86: int3472: increase handshake delay to 50ms for + OV05C10 + * Support Samsung S5K3J1 sensor for Intel MIPI camera (LP: #2121852) + - SAUCE: media: ipu-bridge: Support s5k3j1 sensor + * [SRU] ASoC: enable rt1320 speaker amp and DMIC on PTL SoundWire platforms + (LP: #2150196) + - ASoC: Intel: soc-acpi-intel-ptl-match: drop rt722 monolithic match + tables + - ASoC: SOF: Intel: Add a is_amp flag to fix the wrong name prefix + - ASoC: sdw_utils: add rt1320 and rt1321 dmic dai in codec_info_list + * powerpc-build in ubuntu_kernel_selftests fails to build due to + uninitialized value (LP: #2129844) + - selftests/powerpc: Suppress -Wmaybe-uninitialized with GCC 15 + * Ubuntu 26.04 linux kernel has non-functional nova-core GPU driver enabled, + conflicting with nouveau (LP: #2150845) + - [Config] Disable DRM_NOVA + * Resolute update: v7.0.6 upstream stable release (LP: #2152558) + - Linux 7.0.6 + - Upstream stable to v7.0.6 + * Resolute update: v7.0.5 upstream stable release (LP: #2152556) + - Linux 7.0.5 + - Upstream stable to v7.0.5 + * Resolute update: v7.0.4 upstream stable release (LP: #2152552) + - ALSA: usb-audio: stop parsing UAC2 rates at MAX_NR_RATES + - ALSA: usb-audio: Avoid false E-MU sample-rate notifications + - ALSA: usb-audio: Fix Audio Advantage Micro II SPDIF switch + - usb: xhci: Make usb_host_endpoint.hcpriv survive endpoint_disable() + - usb: chipidea: otg: not wait vbus drop if use role_switch + - usb: chipidea: core: allow ci_irq_handler() handle both ID and VBUS + change + - ALSA: usb-audio: Evaluate packsize caps at the right place + - LoongArch: Add spectre boundry for syscall dispatch table + - drm/nouveau: fix u32 overflow in pushbuf reloc bounds check + - leds: qcom-lpg: Check for array overflow when selecting the high + resolution + - greybus: gb-beagleplay: bound bootloader receive buffering + - greybus: gb-beagleplay: fix sleep in atomic context in hdlc_tx_frames() + - misc: ibmasm: fix OOB MMIO read in ibmasm_handle_mouse_interrupt() + - ibmasm: fix OOB reads in command_file_write due to missing size checks + - ibmasm: fix heap over-read in ibmasm_send_i2o_message() + - sysfs: attribute_group: Respect is_visible_const() when changing owner + - driver core: Don't let a device probe until it's ready + - device property: Make modifications of fwnode "flags" thread safe + - drm/nouveau: fix nvkm_device leak on aperture removal failure + - rust: dma: remove DMA_ATTR_NO_KERNEL_MAPPING from public attrs + - kbuild: rust: allow `clippy::uninlined_format_args` + - fs: afs: revert mmap_prepare() change + - firmware: google: framebuffer: Do not mark framebuffer as busy + - lib: test_hmm: evict device pages on file close to avoid use-after-free + - arm64/mm: Enable batched TLB flush in unmap_hotplug_range() + - arm64: mm: Fix rodata=full block mapping support for realm guests + - mm: migrate: requeue destination folio on deferred split queue + - mm: prevent droppable mappings from being locked + - mm: fix deferred split queue races during migration + - ocfs2: split transactions in dio completion to avoid credit exhaustion + - Input: edt-ft5x06 - fix use-after-free in debugfs teardown + - zram: do not forget to endio for partial discard requests + - wifi: rtw88: check for PCI upstream bridge existence + - wifi: mwifiex: fix use-after-free in mwifiex_adapter_cleanup() + - vfio: selftests: Fix VLA initialisation in vfio_pci_irq_set() + - vfio/xe: Add a missing vfio_pci_core_release_dev() + - vfio/virtio: Convert list_lock from spinlock to mutex + - vfio/cdx: Serialize VFIO_DEVICE_SET_IRQS with a per-device mutex + - vfio/cdx: Fix NULL pointer dereference in interrupt trigger path + - um: drivers: call kernel_strrchr() explicitly in cow_user.c + - thermal: core: Fix thermal zone governor cleanup issues + - spi: imx: fix use-after-free on unbind + - spi: ch341: fix memory leaks on probe failures + - crypto: algif_aead - snapshot IV for async AEAD requests + - crypto: pcrypt - Fix handling of MAY_BACKLOG requests + - dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock + constraints + - of: unittest: fix use-after-free in of_unittest_changeset() + - of: unittest: fix use-after-free in testdrv_probe() + - hwmon: (powerz) Fix missing usb_kill_urb() on signal interrupt + - EDAC/versalnet: Fix device_node leak in mc_probe() + - PCI: imx6: Skip waiting for L2/L3 Ready on i.MX6SX + - media: amphion: Fix race between m2m job_abort and device_run + - ALSA: control: Validate buf_len before strnlen() in + snd_ctl_elem_init_enum_names() + - net: caif: clear client service pointer on teardown + - net: strparser: fix skb_head leak in strp_abort_strp() + - media: mtk-jpeg: fix use-after-free in release path due to uncancelled + work + - crypto: atmel-sha204a - Fix OTP sysfs read and error handling + - PCI: endpoint: pci-epf-ntb: Remove duplicate resource teardown + - Revert "ALSA: usb: Increase volume range that triggers a warning" + - phy: qcom: m31-eusb2: clear PLL_EN during init + - PCI: epf-mhi: Return 0, not remaining timeout, when eDMA ops complete + - lib/ts_kmp: fix integer overflow in pattern length calculation + - media: i2c: imx219: Check return value of devm_gpiod_get_optional() in + imx219_probe() + - net: qrtr: ns: Fix use-after-free in driver remove() + - ext2: reject inodes with zero i_nlink and valid mode in ext2_iget() + - mm/zsmalloc: copy KMSAN metadata in zs_page_migrate() + - ALSA: aoa: i2sbus: clear stale prepared state + - ALSA: aoa: i2sbus: fix OF node lifetime handling + - ALSA: aoa: Skip devices with no codecs in i2sbus_resume() + - ALSA: ctxfi: Add fallback to default RSR for S/PDIF + - ALSA: seq_oss: return full count for successful SEQ_FULLSIZE writes + - erofs: fix the out-of-bounds nameoff handling for trailing dirents + - ipmi:ssif: Clean up kthread on errors + - jbd2: fix deadlock in jbd2_journal_cancel_revoke() + - KVM: selftests: Fix reserved value WRMSR testcase for multi-feature MSRs + - md/raid10: fix deadlock with check operation and nowait requests + - media: rc: igorplugusb: heed coherency rules + - media: rockchip: rkcif: fix off by one bugs + - media: rockchip: rkcif: comply with minimum number of buffers + requirement + - mfd: stpmic1: Attempt system shutdown twice in case PMIC is confused + - mm/alloc_tag: clear codetag for pages allocated before page_ext + initialization + - mm/damon/core: fix damon_call() vs kdamond_fn() exit race + - mm/damon/core: fix damos_walk() vs kdamond_fn() exit race + - mm/hugetlb: fix early boot crash on parameters without '=' separator + - mtd: docg3: fix use-after-free in docg3_release() + - nvme-pci: add NVME_QUIRK_DISABLE_WRITE_ZEROES for Kingston OM3SGP4 + - nvme: respect NVME_QUIRK_DISABLE_WRITE_ZEROES when wzsl is set + - parisc: _llseek syscall is only available for 32-bit userspace + - parisc: Drop ip_fast_csum() inline assembly implementation + - PCI: cadence: Use cdns_pcie_read_sz() for byte or word read access + - PCI: imx6: Fix reference clock source selection for i.MX95 + - perf annotate: Use jump__delete when freeing LoongArch jumps + - RDMA/mana_ib: Disable RX steering on RSS QP destroy + - remoteproc: xlnx: Only access buffer information if IPI is buffered + - reset: rzv2h-usb2phy: Keep PHY clock enabled for entire device lifetime + - sched: Use u64 for bandwidth ratio calculations + - selftests/mqueue: Fix incorrectly named file + - landlock: Fix LOG_SUBDOMAINS_OFF inheritance across fork() + - landlock: Allow TSYNC with LOG_SUBDOMAINS_OFF and fd=-1 + - selftests/landlock: Drain stale audit records on init + - selftests/landlock: Fix format warning for __u64 in net_test + - selftests/landlock: Fix snprintf truncation checks in audit helpers + - selftests/landlock: Skip stale records in audit_match_record() + - rbd: fix null-ptr-deref when device_add_disk() fails + - mm/zone_device: do not touch device folio after calling ->folio_free() + - block: fix zone write plugs refcount handling in + disk_zone_wplug_schedule_bio_work() + - io_uring/zcrx: return back two step unregistration + - io_uring/timeout: check unused sqe fields + - block: relax pgmap check in bio_add_page for compatible zone device + pages + - iio: adc: ti-ads7950: use iio_push_to_buffers_with_ts_unaligned() + - io_uring/register: fix ring resizing with mixed/large SQEs/CQEs + - io_uring/zcrx: fix user_struct uaf + - io_uring/poll: fix signed comparison in io_poll_get_ownership() + - io_uring/poll: ensure EPOLL_ONESHOT is propagated for EPOLL_URING_WAKE + - module.lds,codetag: force 0 sh_addr for sections + - module.lds.S: Fix modules on 32-bit parisc architecture + - ALSA: core: Fix potential data race at fasync handling + - ALSA: caiaq: Fix control_put() result and cache rollback + - ALSA: caiaq: Handle probe errors properly + - ALSA: 6fire: Fix input volume change detection + - ALSA: hda/realtek - Add mute LED support for HP Victus 15-fa2xxx + - ALSA: pcmtest: fix reference leak on failed device registration + - ALSA: pcmtest: Fix resource leaks in module init error paths + - iio: adc: ad7768-1: fix one-shot mode data acquisition + - iio: adc: ad7768-1: remove switch to one-shot mode + - rxrpc: Fix memory leaks in rxkad_verify_response() + - rxrpc: Fix rxkad crypto unalignment handling + - rxrpc: Fix error handling in rxgk_extract_token() + - rxrpc: Fix re-decryption of RESPONSE packets + - EDAC/versalnet: Fix memory leak in remove and probe error paths + - tools/accounting: handle truncated taskstats netlink messages + - net: txgbe: fix RTNL assertion warning when remove module + - arm64: dts: marvell: uDPU: add ethernet aliases + - net: qrtr: ns: Limit the maximum server registration per node + - net: qrtr: ns: Limit the maximum number of lookups + - net: qrtr: ns: Free the node during ctrl_cmd_bye() + - net: qrtr: ns: Limit the total number of nodes + - net: rds: fix MR cleanup on copy error + - net: txgbe: fix firmware version check + - net/smc: avoid early lgr access in smc_clc_wait_msg + - net: ks8851: Reinstate disabling of BHs around IRQ handler + - net: bridge: use a stable FDB dst snapshot in RCU readers + - netconsole: avoid out-of-bounds access on empty string in trim_newline() + - net: mctp: fix don't require received header reserved bits to be zero + - net: ks8851: Avoid excess softirq scheduling + - drm/arcpgu: fix device node leak + - slub: fix data loss and overflow in krealloc() + - tracing/fprobe: Reject registration of a registered fprobe before init + - RDMA/rxe: Validate pad and ICRC before payload_size() in rxe_rcv + - printf: Compile the kunit test with DISABLE_BRANCH_PROFILING + DISABLE_BRANCH_PROFILING + - ipv4: icmp: validate reply type before using icmp_pointers + - libceph: Prevent potential null-ptr-deref in ceph_handle_auth_reply() + - spi: fix resource leaks on device setup failure + - extract-cert: Wrap key_pass with '#ifdef USE_PKCS11_ENGINE' + - tpm: avoid -Wunused-but-set-variable + - LoongArch: Make arch_irq_work_has_interrupt() true only if IPI HW exist + - LoongArch: Show CPU vulnerabilites correctly + - fbdev: defio: Disconnect deferred I/O from the lifetime of struct + fb_info + - power: supply: axp288_charger: Do not cancel work before initializing it + - hwmon: (isl28022) Fix integer overflow in power calculation on 32-bit + - hwmon: (powerz) Avoid cacheline sharing for DMA buffer + - media: rzv2h-ivc: Revise default VBLANK formula + - media: rzv2h-ivc: Fix AXIRX_VBLANK register write + - fs: prepare for adding LSM blob to backing_file + - lsm: add backing_file LSM hooks + - selinux: fix overlayfs mmap() and mprotect() access checks + - hwmon: (pt5161l) Fix bugs in pt5161l_read_block_data() + - randomize_kstack: Maintain kstack_offset per task + - mmc: block: use single block write in retry + - mmc: sdhci-of-dwcmshc: Disable clock before DLL configuration + - arm64: dts: ti: am62-verdin: Enable pullup for eMMC data pins + - crypto: qat - fix IRQ cleanup on 6xxx probe failure + - xfs: start gc on zonegc_low_space attribute updates + - xfs: fix a resource leak in xfs_alloc_buftarg() + - firmware: google: framebuffer: Do not unregister platform device + - firmware: exynos-acpm: Drop fake 'const' on handle pointer + - crypto: talitos - fix SEC1 32k ahash request limitation + - crypto: talitos - rename first/last to first_desc/last_desc + - pwm: imx-tpm: Count the number of enabled channels in probe + - tpm2-sessions: Fix missing tpm_buf_destroy() in tpm2_read_public() + - tpm: Fix auth session leak in tpm2_get_random() error path + - tpm: Use kfree_sensitive() to free auth session in tpm_dev_release() + - tpm: tpm_tis: add error logging for data transfer + - tpm: tpm_tis: stop transmit if retries are exhausted + - rtc: ntxec: fix OF node reference imbalance + - mm/vmalloc: take vmap_purge_lock in shrinker + - mm/memfd_luo: fix physical address conversion in put_folios cleanup + - mm/mempolicy: fix memory leaks in weighted_interleave_auto_store() + - mm/damon/stat: fix memory leak on damon_start() failure in + damon_stat_start() + - mm/damon/core: validate damos_quota_goal->nid for + node_mem_{used,free}_bp + - mm/damon/core: validate damos_quota_goal->nid for + node_memcg_{used,free}_bp + - mm/damon/core: use time_in_range_open() for damos quota window start + - mm/damon/core: disallow time-quota setting zero esz + - mm/damon/core: disallow non-power of two min_region_sz on damon_start() + - userfaultfd: allow registration of ranges below mmap_min_addr + - LoongArch: KVM: Use CSR_CRMD_PLV in kvm_arch_vcpu_in_kernel() + - KVM: x86: Defer non-architectural deliver of exception payload to + userspace read + - KVM: nSVM: Mark all of vmcb02 dirty when restoring nested state + - KVM: nSVM: Sync NextRIP to cached vmcb12 after VMRUN of L2 + - KVM: nSVM: Sync interrupt shadow to cached vmcb12 after VMRUN of L2 + - KVM: SVM: Inject #UD for INVLPGA if EFER.SVME=0 + - KVM: SVM: Explicitly mark vmcb01 dirty after modifying VMCB intercepts + - KVM: nSVM: Ensure AVIC is inhibited when restoring a vCPU to guest mode + - KVM: nSVM: Always use NextRIP as vmcb02's NextRIP after first L2 VMRUN + - KVM: nSVM: Delay stuffing L2's current RIP into NextRIP until vCPU run + - KVM: nSVM: Use vcpu->arch.cr2 when updating vmcb12 on nested #VMEXIT + - KVM: arm64: Account for RESx bits in __compute_fgt() + - KVM: nSVM: Avoid clearing VMCB_LBR in vmcb12 + - KVM: nSVM: Delay setting soft IRQ RIP tracking fields until vCPU run + - KVM: SVM: Switch svm_copy_lbrs() to a macro + - KVM: SVM: Add missing save/restore handling of LBR MSRs + - KVM: nSVM: Always inject a #GP if mapping VMCB12 fails on nested VMRUN + - KVM: nSVM: Refactor checking LBRV enablement in vmcb12 into a helper + - KVM: nSVM: Refactor writing vmcb12 on nested #VMEXIT as a helper + - KVM: nSVM: Triple fault if restore host CR3 fails on nested #VMEXIT + - KVM: nSVM: Triple fault if mapping VMCB12 fails on nested #VMEXIT + - KVM: nSVM: Clear GIF on nested #VMEXIT(INVALID) + - KVM: nSVM: Clear EVENTINJ fields in vmcb12 on nested #VMEXIT + - KVM: nSVM: Clear tracking of L1->L2 NMI and soft IRQ on nested #VMEXIT + - KVM: nSVM: Add missing consistency check for EFER, CR0, CR4, and CS + - KVM: nSVM: Drop the non-architectural consistency check for NP_ENABLE + - KVM: nSVM: Add missing consistency check for nCR3 validity + - KVM: nSVM: Raise #UD if unhandled VMMCALL isn't intercepted by L1 + - KVM: nSVM: Always intercept VMMCALL when L2 is active + - ARM: 9472/1: fix race condition on PG_dcache_clean in + __sync_icache_dcache() + - ring-buffer: Do not double count the reader_page + - ext4: fix bounds check in check_xattrs() to prevent out-of-bounds access + - ext4: fix missing brelse() in ext4_xattr_inode_dec_ref_all() + - udf: fix partition descriptor append bookkeeping + - mtd: spi-nor: sst: Fix write enable before AAI sequence + - mtd: spinand: winbond: Declare the QE bit on W25NxxJW + - amdgpu/jpeg: fix deepsleep register for jpeg 5_0_0 and 5_0_2 + - md/md-llbitmap: skip reading rdevs that are not in_sync + - md/md-llbitmap: raise barrier before state machine transition + - md/raid5: fix soft lockup in retry_aligned_read() + - md/raid5: validate payload size before accessing journal metadata + - check-uapi: link into shared objects + - mm, swap: speed up hibernation allocation and writeout + - HID: apple: ensure the keyboard backlight is off if suspending + - inotify: fix watch count leak when fsnotify_add_inode_mark_locked() + fails + - x86/cpu: Disable FRED when PTI is forced on + - x86/shstk: Prevent deadlock during shstk sigreturn + - wifi: rtl8xxxu: fix potential use of uninitialized value + - tcp: call sk_data_ready() after listener migration + - taskstats: set version in TGID exit notifications + - mptcp: sync the msk->sndbuf at accept() time + - mfd: core: Preserve OF node when ACPI handle is present + - 9p: fix access mode flags being ORed instead of replaced + - Bluetooth: hci_event: fix potential UAF in SSP passkey handlers + - bus: mhi: host: pci_generic: Switch to async power up to avoid boot + delays + - can: ucan: fix devres lifetime + - crypto: acomp - fix wrong pointer stored by acomp_save_req() + - crypto: arm64/aes - Fix 32-bit aes_mac_update() arg treated as 64-bit + - crypto: atmel-aes - Fix 3-page memory leak in atmel_aes_buff_cleanup + - crypto: atmel-ecc - Release client on allocation failure + - crypto: hisilicon - Fix dma_unmap_single() direction + - crypto: ccree - fix a memory leak in cc_mac_digest() + - crypto: atmel-tdes - fix DMA sync direction + - crypto: atmel-sha204a - Fix error codes in OTP reads + - crypto: atmel-sha204a - Fix potential UAF and memory leak in remove path + - crypto: atmel-sha204a - Fix uninitialized data access on OTP read error + - crypto: nx - fix bounce buffer leaks in nx842_crypto_{alloc,free}_ctx + - crypto: nx - fix context leak in nx842_crypto_free_ctx + - crypto: nx - Fix packed layout in struct nx842_crypto_header + - dm mirror: fix integer overflow in create_dirty_log() + - erofs: fix unsigned underflow in z_erofs_lz4_handle_overlap() + - ceph: fix num_ops off-by-one when crypto allocation fails + - ceph: only d_add() negative dentries when they are unhashed + - gtp: disable BH before calling udp_tunnel_xmit_skb() + - IB/core: Fix zero dmac race in neighbor resolution + - ktest: Fix the month in the name of the failure directory + - NFSv4.1: Apply session size limits on clone path + - ntfs3: add buffer boundary checks to run_unpack() + - ntfs3: fix integer overflow in run_unpack() volume boundary check + - rtmutex: Use waiter::task instead of current in remove_waiter() + - rxgk: Fix potential integer overflow in length check + - sched_ext: Documentation: Clarify ops.dispatch() role in task lifecycle + - scsi: sd: fix missing put_disk() when device_add(&disk_dev) fails + - seg6: fix seg6 lwtunnel output redirect for L2 reduced encap mode + - perf loongarch: Fix build failure with CONFIG_LIBDW_DWARF_UNWIND + - iio: frequency: admv1013: add dev variable + - iio: frequency: admv1013: fix NULL pointer dereference on str + - wifi: mt76: mt792x: describe USB WFSYS reset with a descriptor + - wifi: mt76: mt792x: fix mt7925u USB WFSYS reset handling + - mm: various small mmap_prepare cleanups + - mm: avoid deadlock when holding rmap on mmap_prepare error + - mei: me: use PCI_DEVICE_DATA macro + - mei: me: add nova lake point H DID + - crypto: authencesn - reject short ahash digests during instance creation + - driver core: Add kernel-doc for DEV_FLAG_COUNT enum value + - ALSA: caiaq: Fix potentially leftover ep1_in_urb at error path + - ALSA: caiaq: Don't abort when no input device is available + - ipv6: rpl: reserve mac_len headroom when recompressed SRH grows + - drm/amdgpu: fix zero-size GDS range init on RDNA4 + - drm/imagination: Fix segfault when updating ftrace mask + - ALSA: caiaq: fix usb_dev refcount leak on probe failure + - ALSA: aloop: Fix peer runtime UAF during format-change stop + - vmalloc: fix buffer overflow in vrealloc_node_align() + - mm/page_alloc: return NULL early from alloc_frozen_pages_nolock() in NMI + on UP + - mm/slab: return NULL early from kmalloc_nolock() in NMI on UP + - net: ipv6: fix NOREF dst use in seg6 and rpl lwtunnels + - netfilter: reject zero shift in nft_bitwise + - ipmi:ssif: Remove unnecessary indention + - ipmi:ssif: NULL thread on error + - Linux 7.0.4 + - Upstream stable to v7.0.4 + * Resolute update: v7.0.3 upstream stable release (LP: #2152550) + - Buffer overflow in drivers/xen/sys-hypervisor.c + - xen/privcmd: fix double free via VMA splitting + - Linux 7.0.3 + - Upstream stable to v7.0.3 + * Resolute update: v7.0.2 upstream stable release (LP: #2150553) + - crypto: authencesn - Fix src offset when decrypting in-place + - pwm: th1520: fix `CLIPPY=1` warning + - drm/amdgpu: replace PASID IDR with XArray + - crypto: krb5enc - fix sleepable flag handling in encrypt dispatch + - crypto: krb5enc - fix async decrypt skipping hash verification + - ksmbd: fix use-after-free in __ksmbd_close_fd() via durable scavenger + - ksmbd: validate owner of durable handle on reconnect + - scripts: generate_rust_analyzer.py: define scripts + - scripts/dtc: Remove unused dts_version in dtc-lexer.l + - fs/ntfs3: validate rec->used in journal-replay file record check + - f2fs: fix to do sanity check on dcc->discard_cmd_cnt conditionally + - f2fs: fix UAF caused by decrementing sbi->nr_pages[] in + f2fs_write_end_io() + - f2fs: fix to avoid memory leak in f2fs_rename() + - f2fs: fix to avoid uninit-value access in f2fs_sanity_check_node_footer + - fuse: reject oversized dirents in page cache + - fuse: abort on fatal signal during sync init + - fuse: Check for large folio with SPLICE_F_MOVE + - fuse: quiet down complaints in fuse_conn_limit_write + - fuse: fuse_dev_ioctl_clone() should wait for device file to be + initialized + - ksmbd: require minimum ACE size in smb_check_perm_dacl() + - smb: server: fix active_num_conn leak on transport allocation failure + - smb: client: fix dir separator in SMB1 UNIX mounts + - smb: server: fix max_connections off-by-one in tcp accept path + - smb: client: require a full NFS mode SID before reading mode bits + - smb: client: validate the whole DACL before rewriting it in cifsacl + - smb: client: fix OOB read in smb2_ioctl_query_info QUERY_INFO path + - ksmbd: validate response sizes in ipc_validate_msg() + - ksmbd: validate num_aces and harden ACE walk in smb_inherit_dacl() + - ksmbd: fix out-of-bounds write in smb2_get_ea() EA alignment + - ksmbd: use check_add_overflow() to prevent u16 DACL size overflow + - ksmbd: reset rcount per connection in ksmbd_conn_wait_idle_sess_id() + - writeback: Fix use after free in inode_switch_wbs_work_fn() + - f2fs: fix use-after-free of sbi in f2fs_compress_write_end_io() + - ALSA: usb-audio: apply quirk for MOONDROP JU Jiu + - ALSA: hda/realtek: Add quirk for Legion S7 15IMH + - ALSA: caiaq: take a reference on the USB device in create_card() + - net/packet: fix TOCTOU race on mmap'd vnet_hdr in tpacket_snd() + - crypto: ccp: Don't attempt to copy CSR to userspace if PSP command + failed + - crypto: ccp: Don't attempt to copy PDH cert to userspace if PSP command + failed + - crypto: ccp: Don't attempt to copy ID to userspace if PSP command failed + - rxrpc: Fix missing validation of ticket length in non-XDR key preparsing + - mshv_vtl: Fix vmemmap_shift exceeding MAX_FOLIO_ORDER + - Linux 7.0.2 + * Resolute update: v7.0.1 upstream stable release (LP: #2150547) + - Revert "UBUNTU: SAUCE: cdc-acm: Exclude Exar USB serial ports" + - nfc: llcp: add missing return after LLCP_CLOSED checks + - x86/CPU: Fix FPDSS on Zen1 + - can: raw: fix ro->uniq use-after-free in raw_rcv() + - i2c: s3c24xx: check the size of the SMBUS message before using it + - staging: rtl8723bs: initialize le_tmp64 in rtw_BIP_verify() + - HID: alps: fix NULL pointer dereference in alps_raw_event() + - HID: core: clamp report_size in s32ton() to avoid undefined shift + - net: usb: cdc-phonet: fix skb frags[] overflow in rx_complete() + - NFC: digital: Bounds check NFC-A cascade depth in SDD response handler + - drm/vc4: platform_get_irq_byname() returns an int + - bnge: return after auxiliary_device_uninit() in error path + - ALSA: usx2y: us144mkii: fix NULL deref on missing interface 0 + - ALSA: fireworks: bound device-supplied status before string array lookup + - fbdev: tdfxfb: avoid divide-by-zero on FBIOPUT_VSCREENINFO + - usb: gadget: f_ncm: validate minimum block_len in ncm_unwrap_ntb() + - usb: gadget: f_phonet: fix skb frags[] overflow in pn_rx_complete() + - usb: gadget: renesas_usb3: validate endpoint index in standard request + handlers + - smb: client: fix off-by-8 bounds check in check_wsl_eas() + - smb: client: fix OOB reads parsing symlink error response + - ksmbd: validate EaNameLength in smb2_get_ea() + - ksmbd: require 3 sub-authorities before reading sub_auth[2] + - ksmbd: fix mechToken leak when SPNEGO decode fails after token alloc + - smb: client: avoid double-free in smbd_free_send_io() after + smbd_send_batch_flush() + - smb: server: avoid double-free in smb_direct_free_sendmsg after + smb_direct_flush_send_list() + - usbip: validate number_of_packets in usbip_pack_ret_submit() + - usb: typec: fusb302: Switch to threaded IRQ handler + - usb: storage: Expand range of matched versions for VL817 quirks entry + - USB: cdc-acm: Add quirks for Yoga Book 9 14IAH10 INGENIC touchscreen + - usb: gadget: f_hid: don't call cdev_init while cdev in use + - usb: port: add delay after usb_hub_set_port_power() + - fbdev: udlfb: avoid divide-by-zero on FBIOPUT_VSCREENINFO + - scripts/gdb/symbols: handle module path parameters + - scripts: generate_rust_analyzer.py: avoid FD leak + - wifi: rtw88: fix device leak on probe failure + - staging: sm750fb: fix division by zero in ps_to_hz() + - selftests/mm: hmm-tests: don't hardcode THP size to 2MB + - USB: serial: option: add Telit Cinterion FN990A MBIM composition + - Docs/admin-guide/mm/damon/reclaim: warn commit_inputs vs param updates + race + - Docs/admin-guide/mm/damon/lru_sort: warn commit_inputs vs param updates + race + - ALSA: ctxfi: Limit PTP to a single page + - dcache: Limit the minimal number of bucket to two + - vfio/xe: Reorganize the init to decouple migration from reset + - arm64: mm: Handle invalid large leaf mappings correctly + - media: vidtv: fix NULL pointer dereference in + vidtv_channel_pmt_match_sections + - ocfs2: fix possible deadlock between unlink and dio_end_io_write + - ocfs2: fix use-after-free in ocfs2_fault() when VM_FAULT_RETRY + - ocfs2: handle invalid dinode in ocfs2_group_extend + - PCI: endpoint: pci-epf-vntb: Stop cmd_handler work in + epf_ntb_epc_cleanup + - PCI: endpoint: pci-epf-vntb: Remove duplicate resource teardown + - KVM: selftests: Remove duplicate LAUNCH_UPDATE_VMSA call in SEV-ES + migrate test + - KVM: SEV: Reject attempts to sync VMSA of an already-launched/encrypted + vCPU + - KVM: SEV: Protect *all* of sev_mem_enc_register_region() with kvm->lock + - KVM: SEV: Disallow LAUNCH_FINISH if vCPUs are actively being created + - KVM: SEV: Lock all vCPUs when synchronzing VMSAs for SNP launch finish + - KVM: SEV: Drop WARN on large size for KVM_MEMORY_ENCRYPT_REG_REGION + - mm: call ->free_folio() directly in folio_unmap_invalidate() + - checkpatch: add support for Assisted-by tag + - x86-64: rename misleadingly named '__copy_user_nocache()' function + - x86: rename and clean up __copy_from_user_inatomic_nocache() + - x86-64/arm64/powerpc: clean up and rename __copy_from_user_flushcache + - KVM: x86: Use scratch field in MMIO fragment to hold small write values + - ASoC: qcom: q6apm: move component registration to unmanaged version + - mm/kasan: fix double free for kasan pXds + - mm: blk-cgroup: fix use-after-free in cgwb_release_workfn() + - media: vidtv: fix nfeeds state corruption on start_streaming failure + - media: mediatek: vcodec: fix use-after-free in encoder release path + - media: em28xx: fix use-after-free in em28xx_v4l2_open() + - hwmon: (powerz) Fix use-after-free on USB disconnect + - ALSA: 6fire: fix use-after-free on disconnect + - bcache: fix cached_dev.sb_bio use-after-free and crash + - wireguard: device: use exit_rtnl callback instead of manual rtnl_lock in + pre_exit + - media: as102: fix to not free memory after the device is registered in + as102_usb_probe() + - nilfs2: fix NULL i_assoc_inode dereference in + nilfs_mdt_save_to_shadow_map + - media: vidtv: fix pass-by-value structs causing MSAN warnings + - media: hackrf: fix to not free memory after the device is registered in + hackrf_probe() + - mm/userfaultfd: fix hugetlb fault mutex hash calculation + - clockevents: Add missing resets of the next_event_forced flag + - Linux 7.0.1 + * GRO managed-frag use-after-free leading to local privilege escalation + (LP: #2154172) + - net: gro: don't merge zcopy skbs + * AppArmor Vulnerabilities (LP: #2151747) + - SAUCE: apparmor: pass big_resp to handler + - SAUCE: apparmor: remove redundant kref_init for listener->count + - SAUCE: apparmor: fix NULL pointer dereference in unpack_pdb + * AppArmor Vulnerabilities (LP: #2151747) // CVE-2026-47337 + - SAUCE: apparmor: fix NULL pointer dereference in bind_map_addr + * AppArmor Vulnerabilities (LP: #2151747) // CVE-2026-47334 + - SAUCE: apparmor: fix sleep prone memory allocation under a spin_lock + * AppArmor Vulnerabilities (LP: #2151747) // CVE-2026-47333 + - SAUCE: apparmor: fix dfa unpacking size of the notification filter + * AppArmor Vulnerabilities (LP: #2151747) // CVE-2026-47332 + - SAUCE: apparmor: fix size check against type instead of pointer + * apparmor: LLVM/clang build failure due to uninitialized variable in + notify.c (LP: #2148809) // CVE-2026-47330 + - SAUCE: apparmor: initialize variable used in uninitialized context + * AppArmor Vulnerabilities (LP: #2151747) // CVE-2026-47329 + - SAUCE: apparmor: fix name validation bypass on notification + * AppArmor Vulnerabilities (LP: #2151747) // CVE-2026-47327 // + CVE-2026-47328 + - SAUCE: apparmor: fix glob memory leak after kstrdup + * AppArmor Vulnerabilities (LP: #2151747) // CVE-2026-47326 + - SAUCE: apparmor: fix inverted NULL check after aa_get_buffer + * CVE-2026-46300 + - net: skbuff: preserve shared-frag marker during coalescing + - net: skbuff: propagate shared-frag marker through frag-transfer helpers + * net/rds: reset op_nents when zerocopy page pin fails (LP: #2153962) + - net/rds: reset op_nents when zerocopy page pin fails + * CVE-2026-46333 + - ptrace: slightly saner 'get_dumpable()' logic + * CVE-2026-43500 + - rxrpc: Fix conn-level packet handling to unshare RESPONSE packets + - rxrpc: Fix potential UAF after skb_unshare() failure + - rxrpc: Fix rxrpc_input_call_event() to only unshare DATA packets + - rxrpc: Also unshare DATA/RESPONSE packets when paged frags are present + * CVE-2026-43284 + - xfrm: esp: avoid in-place decrypt on shared skb frags + + -- Kuba Pawlak Mon, 15 Jun 2026 14:24:34 +0200 linux-qcom (7.0.0-1005.7) resolute; urgency=medium diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 5c76bf0a15f37..5e2f0fa483d73 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -759,7 +759,6 @@ CONFIG_DRM_NOUVEAU_CH7006 policy<{'arm64': '-'}> CONFIG_DRM_NOUVEAU_GSP_DEFAULT policy<{'arm64': '-'}> CONFIG_DRM_NOUVEAU_SIL164 policy<{'arm64': '-'}> CONFIG_DRM_NOUVEAU_SVM policy<{'arm64': '-'}> -CONFIG_DRM_NOVA policy<{'arm64': 'n'}> CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS policy<{'arm64': '-'}> CONFIG_DRM_PANEL_DLC0697 policy<{'arm64': 'y'}> CONFIG_DRM_PL111 policy<{'arm64': 'n'}> @@ -1977,7 +1976,6 @@ CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> CONFIG_RTSN policy<{'arm64': '-'}> -CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11)"'}> CONFIG_RZG2L_ADC policy<{'arm64': '-'}> CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> diff --git a/debian.qcom/reconstruct b/debian.qcom/reconstruct index 16e52ee71b8a0..01029ffd62b3a 100644 --- a/debian.qcom/reconstruct +++ b/debian.qcom/reconstruct @@ -31,4 +31,8 @@ chmod +x 'debian/templates/image.prerm.in' chmod +x 'debian/tests/rebuild' chmod +x 'debian/tests/ubuntu-regression-suite' # Remove any files deleted from the orig. +rm -f 'arch/parisc/lib/checksum.c' +rm -f 'drivers/media/platform/qcom/iris/iris_platform_gen1.c' +rm -f 'drivers/media/platform/qcom/iris/iris_platform_gen2.c' +rm -f 'tools/testing/selftests/mqueue/setting' exit 0 From 3e0867395fd1873b7be1e0a090aab12a0c11b9e9 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 14 May 2026 17:37:04 +0800 Subject: [PATCH 0967/1330] WORKAROUND: arm64: dts: qcom: Add qref supply for PCIe PHYs All PCIe PHYs on X1E80100 require vdda-qref power supplies, but this is missing in the current PHY device tree node. The PCIe port can still function because the regulator L3J, which vdda-qref consumes, is voted by other components. Since the device tree should accurately describe the hardware, add the vdda-qref power supply explicitly in all PCIe PHY device nodes. Workaround will be reverted once the vote qref regulator for PCIe available in upstream. Signed-off-by: Qiang Yu Signed-off-by: Ziyue Zhang Signed-off-by: Kuba Pawlak --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 478ab8df020a0..696e2ab5630d2 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -415,6 +415,7 @@ &pcie3_phy { vdda-phy-supply = <&vreg_l3c_0p8>; vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; @@ -429,6 +430,7 @@ &pcie4_phy { vdda-phy-supply = <&vreg_l3i_0p8>; vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; @@ -443,6 +445,7 @@ &pcie5_phy { vdda-phy-supply = <&vreg_l3i_0p8>; vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; @@ -457,6 +460,7 @@ &pcie6a_phy { vdda-phy-supply = <&vreg_l1d_0p8>; vdda-pll-supply = <&vreg_l2j_1p2>; + vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; From 605bfc67e18c281d39d65ec341aca646375a06e1 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 17 Feb 2026 17:01:42 +0530 Subject: [PATCH 0968/1330] PCI: dwc: Proceed with system suspend even if the endpoint doesn't respond with PME_TO_Ack message PCIe spec r7.0, sec 5.3.3.2.1, recommends proceeding with L2/L3 sequence even if one or devices do not respond with PME_TO_Ack message after 10ms timeout. So just print a warning if the timeout happens and proceed with the system suspend. Reported-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam Tested-by: Neil Armstrong # on SM8650-HDK Reviewed-by: Frank Li Link: https://patch.msgid.link/20260217113142.9140-1-manivannan.sadhasivam@oss.qualcomm.com Signed-off-by: Kuba Pawlak (cherry picked from commit eed390775470ff0db32cce37a681f3acc2b941c3) --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 5ca1ddd12b7da..9861768631efa 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1240,9 +1240,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US, false, pci); if (ret) { - /* Only log message when LTSSM isn't in DETECT or POLL */ - dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); - return ret; + /* + * Failure is non-fatal since spec r7.0, sec 5.3.3.2.1, + * recommends proceeding with L2/L3 sequence even if one or more + * devices do not respond with PME_TO_Ack after 10ms timeout. + */ + dev_warn(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); + ret = 0; } /* From b076e19e9861cd98f9c126fec98f961340a049ac Mon Sep 17 00:00:00 2001 From: Yu-Hsiang Tseng Date: Thu, 23 Apr 2026 02:08:14 +0800 Subject: [PATCH 0969/1330] wifi: ath12k: use lockdep_assert_in_rcu_read_lock() for RCU assertions Two functions in ath12k assert that the caller holds an RCU read lock: ath12k_mac_get_arvif() and ath12k_p2p_noa_update_vdev_iter(). Both use: WARN_ON(!rcu_read_lock_any_held()); On kernels using preemptible RCU (CONFIG_PREEMPT=y or CONFIG_PREEMPT_RT=y) without CONFIG_DEBUG_LOCK_ALLOC, this produces a false positive splat whenever these functions are invoked from paths that do hold the RCU read lock (e.g. firmware stats processing or mac80211 interface iteration). Root cause: - Without CONFIG_DEBUG_LOCK_ALLOC, rcu_read_lock_any_held() is a static inline that returns !preemptible() as a proxy for "in an RCU read section". - With preemptible RCU, rcu_read_lock() does not disable preemption. A task can therefore be preemptible while legitimately holding an RCU read lock, making the proxy unreliable. - Callers such as ath12k_wmi_tlv_rssi_chain_parse() (via guard(rcu)()) and ieee80211_iterate_active_interfaces_atomic() do hold the RCU read lock, so these warnings are incorrect. Typical splat seen on a WCN7850 station with periodic fw stats processing: WARNING: drivers/net/wireless/ath/ath12k/mac.c:791 at ath12k_mac_get_arvif+0x9e/0xd0 [ath12k] Tainted: G W O 6.19.13-rt #1 PREEMPT_RT Call Trace: ath12k_wmi_tlv_rssi_chain_parse+0x69/0x170 [ath12k] ath12k_wmi_tlv_iter+0x7f/0x120 [ath12k] ath12k_wmi_tlv_fw_stats_parse+0x342/0x6b0 [ath12k] ath12k_wmi_op_rx+0xe9e/0x3150 [ath12k] ath12k_htc_rx_completion_handler+0x3df/0x5b0 [ath12k] ath12k_ce_per_engine_service+0x325/0x3e0 [ath12k] ath12k_pci_ce_workqueue+0x20/0x40 [ath12k] Replace WARN_ON(!rcu_read_lock_any_held()) with lockdep_assert_in_rcu_read_lock(), which is gated on CONFIG_PROVE_RCU and therefore compiles out entirely when PROVE_RCU is disabled. PROVE_RCU kernels continue to get the full lockdep-based check, and the new helper precisely checks for rcu_read_lock() rather than any RCU variant, which better matches the callers' expectations. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: 3dd2c68f206e ("wifi: ath12k: prepare vif data structure for MLO handling") Suggested-by: Baochen Qiang Suggested-by: Sebastian Andrzej Siewior Reviewed-by: Baochen Qiang Reviewed-by: Rameshkumar Sundaram Signed-off-by: Yu-Hsiang Tseng Reviewed-by: Sebastian Andrzej Siewior Link: https://patch.msgid.link/20260422180814.1938317-1-asas1asas200@gmail.com Signed-off-by: Jeff Johnson --- drivers/net/wireless/ath/ath12k/mac.c | 2 +- drivers/net/wireless/ath/ath12k/p2p.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c index 6c5890637cf53..ad547b06c0483 100644 --- a/drivers/net/wireless/ath/ath12k/mac.c +++ b/drivers/net/wireless/ath/ath12k/mac.c @@ -792,7 +792,7 @@ struct ath12k_link_vif *ath12k_mac_get_arvif(struct ath12k *ar, u32 vdev_id) /* To use the arvif returned, caller must have held rcu read lock. */ - WARN_ON(!rcu_read_lock_any_held()); + lockdep_assert_in_rcu_read_lock(); arvif_iter.vdev_id = vdev_id; arvif_iter.ar = ar; diff --git a/drivers/net/wireless/ath/ath12k/p2p.c b/drivers/net/wireless/ath/ath12k/p2p.c index 59589748f1a8c..19ebcd1d8eb25 100644 --- a/drivers/net/wireless/ath/ath12k/p2p.c +++ b/drivers/net/wireless/ath/ath12k/p2p.c @@ -123,7 +123,7 @@ static void ath12k_p2p_noa_update_vdev_iter(void *data, u8 *mac, struct ath12k_p2p_noa_arg *arg = data; struct ath12k_link_vif *arvif; - WARN_ON(!rcu_read_lock_any_held()); + lockdep_assert_in_rcu_read_lock(); arvif = &ahvif->deflink; if (!arvif->is_created || arvif->ar != arg->ar || arvif->vdev_id != arg->vdev_id) return; From 49fb63f5c9d051301656c3905dd601b3a5a56cab Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 23 Jun 2026 12:47:03 +0200 Subject: [PATCH 0970/1330] Revert "arm64: dts: qcom: hamoa: Disable spi18 and fix qupv3_2 firmware-name" This reverts commit e4592a1d5d4ab5b08110c01802794e1f412556b1. --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 17 ++++++++++------- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 2 ++ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 1fbe272830cff..9abf24c8017d3 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -1265,14 +1265,17 @@ }; }; -/* - * spi18 (MCP2518FD CAN) is disabled because TrustZone firmware on this - * hardware does not grant Linux access to SE2 of QUPv3_2 (physical 0x888000). - * Probing spi18 causes a synchronous external abort (SLVERR) from TZ firewall. - * Re-enable once TZ firmware is updated to allow access to this SE. - */ &spi18 { - status = "disabled"; + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 68 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mcp2518fd_osc>; + spi-max-frequency = <14000000>; + microchip,xstbyen; + }; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 696e2ab5630d2..a0443b53b417a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -478,6 +478,8 @@ }; &qupv3_2 { + firmware-name = "qcom/x1e80100/qupv3fw.elf"; + status = "okay"; }; From c984f3fcceeec0958def2bba874d0003d2df11e0 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 29 Jun 2026 19:32:42 +0200 Subject: [PATCH 0971/1330] UBUNTU: [Config] qcom: build x1e80100 camcc/dispcc/gpucc/videocc in The apps_smmu (qcom,x1e80100-smmu-500) and its clients (USB, UFS, PCIe, camera ISP, display) are built into the kernel and probe during early init. Each per-master SMMU TBU is power-gated by the client's GDSC, which is supplied by the camera/display/gpu/video clock controllers. When those controllers are modules, a built-in client can issue an SMMU TLB sync against a still-unpowered TBU before the modular GDSC provider registers, producing 'arm-smmu ... TLB sync timed out -- SMMU may be deadlocked' and a boot loop (observed with a slimmed initramfs). Build the four controllers in (matching CLK_X1E80100_GCC) so their GDSCs register during init, removing the probe-ordering race. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- debian.qcom/config/annotations | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 5e2f0fa483d73..f330a0cd5dccb 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -18,6 +18,15 @@ CONFIG_ARCH_ROCKCHIP note<'LP: #1825222'> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': 'y'}> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT note<'LP: #2102032'> +CONFIG_CLK_X1E80100_CAMCC policy<{'arm64': 'y'}> +CONFIG_CLK_X1E80100_CAMCC note<'builtin: apps_smmu camera TBU GDSC must register before built-in clients probe to avoid TLB-sync deadlock'> + +CONFIG_CLK_X1E80100_DISPCC policy<{'arm64': 'y'}> +CONFIG_CLK_X1E80100_DISPCC note<'builtin: apps_smmu display TBU GDSC must register before built-in clients probe to avoid TLB-sync deadlock'> + +CONFIG_CLK_X1E80100_GPUCC policy<{'arm64': 'y'}> +CONFIG_CLK_X1E80100_GPUCC note<'builtin: GPU TBU GDSC must register before built-in clients probe to avoid TLB-sync deadlock'> + CONFIG_DRM_AMDGPU_CIK policy<{'arm64': '-'}> CONFIG_DRM_AMDGPU_CIK note<'for zesty'> @@ -90,6 +99,9 @@ CONFIG_SERIAL_SH_SCI_CONSOLE note<'LP: #2022361'> CONFIG_SERIAL_SH_SCI_EARLYCON policy<{'arm64': '-'}> CONFIG_SERIAL_SH_SCI_EARLYCON note<'LP: #2022361'> +CONFIG_SM_VIDEOCC_8550 policy<{'arm64': 'y'}> +CONFIG_SM_VIDEOCC_8550 note<'builtin: x1e80100 video TBU GDSC must register before built-in clients probe to avoid TLB-sync deadlock'> + CONFIG_SND policy<{'arm64': 'y'}> CONFIG_SND note<'LP: #2126816'> @@ -1976,6 +1988,7 @@ CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> CONFIG_RTSN policy<{'arm64': '-'}> +CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11)"'}> CONFIG_RZG2L_ADC policy<{'arm64': '-'}> CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> From 109543d39d36ee5b135d7177ded48ae582db720a Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 30 Jun 2026 13:39:46 +0200 Subject: [PATCH 0972/1330] UBUNTU: [Config] change CONFIG_MEMLAT_DEVFREQ to m Signed-off-by: Kuba Pawlak --- debian.qcom/config/annotations | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index f330a0cd5dccb..01b334de26d36 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -2002,7 +2002,7 @@ CONFIG_SAMPLE_CORESIGHT_SYSCFG policy<{'arm64': 'n'}> CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': '-'}> CONFIG_SATA_RCAR policy<{'arm64': '-'}> CONFIG_SC27XX_ADC policy<{'arm64': '-'}> -CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ policy<{'arm64': 'y'}> +CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ policy<{'arm64': 'm'}> CONFIG_SCSI_UFS_AMD_VERSAL2 policy<{'arm64': '-'}> CONFIG_SCSI_UFS_HISI policy<{'arm64': '-'}> CONFIG_SCSI_UFS_MEDIATEK policy<{'arm64': '-'}> From 95b007bf3dd9cabfb2c39dc8ef3c923b3239904e Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 6 Jul 2026 12:32:14 +0200 Subject: [PATCH 0973/1330] UBUNTU: [Config]: synchronize config after rebase to 7.0.0-28.28 Signed-off-by: Kuba Pawlak --- debian.qcom/config/annotations | 2 ++ 1 file changed, 2 insertions(+) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 01b334de26d36..8d798b66af371 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -887,6 +887,7 @@ CONFIG_FSL_DPAA2_ETH policy<{'arm64': '-'}> CONFIG_FSL_DPAA2_ETH_DCB policy<{'arm64': '-'}> CONFIG_FSL_DPAA2_PTP_CLOCK policy<{'arm64': '-'}> CONFIG_FSL_DPAA2_QDMA policy<{'arm64': '-'}> +CONFIG_FSL_DPAA2_SWITCH policy<{'arm64': '-'}> CONFIG_FSL_DPAA_CHECKING policy<{'arm64': '-'}> CONFIG_FSL_DPAA_ETH policy<{'arm64': '-'}> CONFIG_FSL_FMAN policy<{'arm64': '-'}> @@ -2576,6 +2577,7 @@ CONFIG_VIDEO_C3_MIPI_ADAPTER policy<{'arm64': '-'}> CONFIG_VIDEO_C3_MIPI_CSI2 policy<{'arm64': '-'}> CONFIG_VIDEO_CODA policy<{'arm64': '-'}> CONFIG_VIDEO_DW100 policy<{'arm64': '-'}> +CONFIG_VIDEO_DW_MIPI_CSI2RX policy<{'arm64': '-'}> CONFIG_VIDEO_E5010_JPEG_ENC policy<{'arm64': '-'}> CONFIG_VIDEO_HANTRO policy<{'arm64': '-'}> CONFIG_VIDEO_HANTRO_HEVC_RFC policy<{'arm64': '-'}> From d3dc84fc71a1230de331904a8312c25ae3653286 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Sun, 14 Jun 2026 13:35:11 +0530 Subject: [PATCH 0974/1330] FROMLIST: arm64: dts: qcom: hamoa-pmics: Add ADC support Add ADC node and define channels for: - Die temperature for PMK8550, PM8550VE* and PMC8380* PMICs. - PM8550: Die temperature, VPH power, and system thermistors. Define thermal zones 'sys-0-thermal' through 'sys-6-thermal' which correspond to the off-PMIC system thermistors connected via PM8550 AMUX/GPIO lines. Also,add io-channels and io-channel-names properties to the temp_alarm nodes so that they can get temperature reading from the ADC die_temp channels. Link: https://lore.kernel.org/all/20260614-adc5_gen3_dt-v2-4-32ec576c5865@oss.qualcomm.com/ Signed-off-by: Ayyagari Ushasreevalli Signed-off-by: Jishnu Prakash Signed-off-by: Kuba Pawlak --- arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 250 ++++++++++++++++++++++ 1 file changed, 250 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi index 6a31a0adf8be4..2e746ede850f8 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi @@ -6,7 +6,9 @@ #include #include #include +#include #include +#include "qcom-adc5-gen3.h" / { thermal-zones { @@ -189,6 +191,90 @@ }; }; }; + + sys-0-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_GPIO_100K_PU(1)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-1-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_GPIO_100K_PU(1)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-2-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-3-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-4-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-5-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-6-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; }; @@ -277,6 +363,142 @@ status = "disabled"; }; + + pmk8550_vadc: adc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #io-channel-cells = <1>; + pinctrl-0 = <&sys_therm_0_gpio3>, <&sys_therm_1_gpio4>; + pinctrl-names = "default"; + + channel@3 { + reg = ; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@14a { + reg = ; + label = "pm8550_gpio_01"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@14b { + reg = ; + label = "pm8550_gpio_02"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@144 { + reg = ; + label = "pm8550_therm_2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_therm_3"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_therm_4"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_therm_5"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_therm_6"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@203 { + reg = ; + label = "pm8550ve_2_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@303 { + reg = ; + label = "pmc8380_3_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@403 { + reg = ; + label = "pmc8380_4_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@503 { + reg = ; + label = "pmc8380_5_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@603 { + reg = ; + label = "pmc8380_6_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@803 { + reg = ; + label = "pm8550ve_8_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@903 { + reg = ; + label = "pm8550ve_9_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; }; /* PMC8380C */ @@ -291,6 +513,8 @@ reg = <0xa00>; interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; }; pm8550_gpios: gpio@8800 { @@ -301,6 +525,18 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + sys_therm_0_gpio3: sys-therm_0-gpio3-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + sys_therm_1_gpio4: sys-therm-1-gpio4-state { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; }; pm8550_flash: led-controller@ee00 { @@ -329,6 +565,8 @@ reg = <0xa00>; interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; }; pm8550ve_2_gpios: gpio@8800 { @@ -354,6 +592,8 @@ reg = <0xa00>; interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; }; pmc8380_3_gpios: gpio@8800 { @@ -378,6 +618,8 @@ reg = <0xa00>; interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; }; pmc8380_4_gpios: gpio@8800 { @@ -402,6 +644,8 @@ reg = <0xa00>; interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(5)>; + io-channel-names = "thermal"; }; pmc8380_5_gpios: gpio@8800 { @@ -426,6 +670,8 @@ reg = <0xa00>; interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; }; pmc8380_6_gpios: gpio@8800 { @@ -451,6 +697,8 @@ reg = <0xa00>; interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(8)>; + io-channel-names = "thermal"; }; pm8550ve_8_gpios: gpio@8800 { @@ -476,6 +724,8 @@ reg = <0xa00>; interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(9)>; + io-channel-names = "thermal"; }; pm8550ve_9_gpios: gpio@8800 { From 9fc0037f1bbd80c4ae47605daa2c46218bb6daab Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 30 Apr 2026 14:28:56 +0530 Subject: [PATCH 0975/1330] FROMLIST: arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Add macro definitions for virtual channels (combination of ADC channel number and PMIC SID number), to be used in devicetree by clients of ADC5 GEN3 device and in the "reg" property of ADC channels. Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-1-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash Signed-off-by: Kuba Pawlak --- arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h | 88 +++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h diff --git a/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h new file mode 100644 index 0000000000000..aa8e54d7e786a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__ +#define __DTS_ARM64_QCOM_ADC5_GEN3_H__ + +/* ADC channels for PMIC5 Gen3 */ + +#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan)) + +#define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00) +#define ADC5_GEN3_1P25VREF(sid) VIRT_CHAN(sid, 0x01) +#define ADC5_GEN3_VREF_VADC(sid) VIRT_CHAN(sid, 0x02) +#define ADC5_GEN3_DIE_TEMP(sid) VIRT_CHAN(sid, 0x03) + +#define ADC5_GEN3_AMUX1_THM(sid) VIRT_CHAN(sid, 0x04) +#define ADC5_GEN3_AMUX2_THM(sid) VIRT_CHAN(sid, 0x05) +#define ADC5_GEN3_AMUX3_THM(sid) VIRT_CHAN(sid, 0x06) +#define ADC5_GEN3_AMUX4_THM(sid) VIRT_CHAN(sid, 0x07) +#define ADC5_GEN3_AMUX5_THM(sid) VIRT_CHAN(sid, 0x08) +#define ADC5_GEN3_AMUX6_THM(sid) VIRT_CHAN(sid, 0x09) +#define ADC5_GEN3_AMUX1_GPIO(sid) VIRT_CHAN(sid, 0x0a) +#define ADC5_GEN3_AMUX2_GPIO(sid) VIRT_CHAN(sid, 0x0b) +#define ADC5_GEN3_AMUX3_GPIO(sid) VIRT_CHAN(sid, 0x0c) +#define ADC5_GEN3_AMUX4_GPIO(sid) VIRT_CHAN(sid, 0x0d) + +#define ADC5_GEN3_CHG_TEMP(sid) VIRT_CHAN(sid, 0x10) +#define ADC5_GEN3_USB_SNS_V_16(sid) VIRT_CHAN(sid, 0x11) +#define ADC5_GEN3_VIN_DIV16_MUX(sid) VIRT_CHAN(sid, 0x12) +#define ADC5_GEN3_VREF_BAT_THERM(sid) VIRT_CHAN(sid, 0x15) +#define ADC5_GEN3_IIN_FB(sid) VIRT_CHAN(sid, 0x17) +#define ADC5_GEN3_TEMP_ALARM_LITE(sid) VIRT_CHAN(sid, 0x18) +#define ADC5_GEN3_IIN_SMB(sid) VIRT_CHAN(sid, 0x19) +#define ADC5_GEN3_ICHG_SMB(sid) VIRT_CHAN(sid, 0x1b) +#define ADC5_GEN3_ICHG_FB(sid) VIRT_CHAN(sid, 0xa1) + +/* 30k pull-up */ +#define ADC5_GEN3_AMUX1_THM_30K_PU(sid) VIRT_CHAN(sid, 0x24) +#define ADC5_GEN3_AMUX2_THM_30K_PU(sid) VIRT_CHAN(sid, 0x25) +#define ADC5_GEN3_AMUX3_THM_30K_PU(sid) VIRT_CHAN(sid, 0x26) +#define ADC5_GEN3_AMUX4_THM_30K_PU(sid) VIRT_CHAN(sid, 0x27) +#define ADC5_GEN3_AMUX5_THM_30K_PU(sid) VIRT_CHAN(sid, 0x28) +#define ADC5_GEN3_AMUX6_THM_30K_PU(sid) VIRT_CHAN(sid, 0x29) +#define ADC5_GEN3_AMUX1_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2a) +#define ADC5_GEN3_AMUX2_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2b) +#define ADC5_GEN3_AMUX3_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2c) +#define ADC5_GEN3_AMUX4_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2d) + +/* 100k pull-up */ +#define ADC5_GEN3_AMUX1_THM_100K_PU(sid) VIRT_CHAN(sid, 0x44) +#define ADC5_GEN3_AMUX2_THM_100K_PU(sid) VIRT_CHAN(sid, 0x45) +#define ADC5_GEN3_AMUX3_THM_100K_PU(sid) VIRT_CHAN(sid, 0x46) +#define ADC5_GEN3_AMUX4_THM_100K_PU(sid) VIRT_CHAN(sid, 0x47) +#define ADC5_GEN3_AMUX5_THM_100K_PU(sid) VIRT_CHAN(sid, 0x48) +#define ADC5_GEN3_AMUX6_THM_100K_PU(sid) VIRT_CHAN(sid, 0x49) +#define ADC5_GEN3_AMUX1_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4a) +#define ADC5_GEN3_AMUX2_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4b) +#define ADC5_GEN3_AMUX3_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4c) +#define ADC5_GEN3_AMUX4_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4d) + +/* 400k pull-up */ +#define ADC5_GEN3_AMUX1_THM_400K_PU(sid) VIRT_CHAN(sid, 0x64) +#define ADC5_GEN3_AMUX2_THM_400K_PU(sid) VIRT_CHAN(sid, 0x65) +#define ADC5_GEN3_AMUX3_THM_400K_PU(sid) VIRT_CHAN(sid, 0x66) +#define ADC5_GEN3_AMUX4_THM_400K_PU(sid) VIRT_CHAN(sid, 0x67) +#define ADC5_GEN3_AMUX5_THM_400K_PU(sid) VIRT_CHAN(sid, 0x68) +#define ADC5_GEN3_AMUX6_THM_400K_PU(sid) VIRT_CHAN(sid, 0x69) +#define ADC5_GEN3_AMUX1_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6a) +#define ADC5_GEN3_AMUX2_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6b) +#define ADC5_GEN3_AMUX3_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6c) +#define ADC5_GEN3_AMUX4_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6d) + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8a) +#define ADC5_GEN3_AMUX2_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8b) +#define ADC5_GEN3_AMUX3_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8c) +#define ADC5_GEN3_AMUX4_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8d) + +#define ADC5_GEN3_VPH_PWR(sid) VIRT_CHAN(sid, 0x8e) +#define ADC5_GEN3_VBAT_SNS_QBG(sid) VIRT_CHAN(sid, 0x8f) + +#define ADC5_GEN3_VBAT_SNS_CHGR(sid) VIRT_CHAN(sid, 0x94) +#define ADC5_GEN3_VBAT_2S_MID_QBG(sid) VIRT_CHAN(sid, 0x96) +#define ADC5_GEN3_VBAT_2S_MID_CHGR(sid) VIRT_CHAN(sid, 0x9d) + +#endif /* __DTS_ARM64_QCOM_ADC5_GEN3_H__ */ From 9f7abb1aecfb84b4da87864844f9c8e9e7a018f1 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 6 Jul 2026 13:16:38 +0200 Subject: [PATCH 0976/1330] UBUNTU: SAUCE: fix struct qcom_edp_phy_cfg MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Between Ubuntu-7.0.0-26.26 and Ubuntu-7.0.0-28.28, the upstream kernel refactored struct qcom_edp_phy_cfg to split the generic swing_pre_emph_cfg pointer into two separate pointers: dp_swing_pre_emph_cfg and edp_swing_pre_emph_cfg. The sc7280_dp_phy_cfg initializer (a Qualcomm addiition) wasn't updated to match the new struct layout, leaving the stale .swing_pre_emph_cfg field name. The fix renames it to .dp_swing_pre_emph_cfg to match the current struct definition. Signed-off-by: Kuba Pawlak --- drivers/phy/qualcomm/phy-qcom-edp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index e38ec2e972802..d21d2de311171 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -563,7 +563,7 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = { static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = { .aux_cfg = edp_phy_aux_cfg_v4, .vco_div_cfg = edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, .ver_ops = &qcom_edp_phy_ops_v4, }; From f8df6a99e0746fef34c70f5ebbce99ed2daf0f4e Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 14 May 2026 17:03:23 +0800 Subject: [PATCH 0977/1330] FROMLIST: PCI: qcom: Set max OPP before DBI access during resume Before accessing DBI registers during resume, the OPP (Operating Performance Point) must be set to maximum to ensure the required voltage corner is available. Without this, DBI access may fail on some platforms. Refactor the open-coded max OPP selection in probe() into a helper qcom_pcie_set_max_opp(), and call it during resume before re-enabling the CPU-PCIe interconnect. Link: https://lore.kernel.org/r/20260416-setmaxopp-v1-1-6a74e2d945a0@oss.qualcomm.com Signed-off-by: Qiang Yu Signed-off-by: Ziyue Zhang Signed-off-by: Kuba Pawlak --- drivers/pci/controller/dwc/pcie-qcom.c | 50 +++++++++++++++++--------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index d3f90e3d10cbb..98499684ab410 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1650,6 +1650,22 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) } } +static int qcom_pcie_set_max_opp(struct device *dev) +{ + unsigned long max_freq = ULONG_MAX; + struct dev_pm_opp *opp; + int ret; + + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + ret = dev_pm_opp_set_opp(dev, opp); + dev_pm_opp_put(opp); + + return ret; +} + static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) { struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); @@ -1882,9 +1898,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct qcom_pcie_perst *perst, *tmp_perst; struct qcom_pcie_port *port, *tmp_port; const struct qcom_pcie_cfg *pcie_cfg; - unsigned long max_freq = ULONG_MAX; struct device *dev = &pdev->dev; - struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; struct resource *res; @@ -1988,21 +2002,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) * probe(), OPP will be updated using qcom_pcie_icc_opp_update(). */ if (!ret) { - opp = dev_pm_opp_find_freq_floor(dev, &max_freq); - if (IS_ERR(opp)) { - ret = PTR_ERR(opp); - dev_err_probe(pci->dev, ret, - "Unable to find max freq OPP\n"); - goto err_pm_runtime_put; - } else { - ret = dev_pm_opp_set_opp(dev, opp); - } - - dev_pm_opp_put(opp); + ret = qcom_pcie_set_max_opp(dev); if (ret) { - dev_err_probe(pci->dev, ret, - "Failed to set OPP for freq %lu\n", - max_freq); + dev_err_probe(dev, ret, "Failed to set max OPP in probe\n"); goto err_pm_runtime_put; } @@ -2111,6 +2113,14 @@ static int qcom_pcie_suspend_noirq(struct device *dev) } } + if (pcie->use_pm_opp) { + ret = qcom_pcie_set_max_opp(dev); + if (ret) { + dev_err(dev, "Failed to set max OPP in resume: %d\n", ret); + return ret; + } + } + /* * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. * Because on some platforms, DBI access can happen very late during the @@ -2156,6 +2166,14 @@ static int qcom_pcie_resume_noirq(struct device *dev) return ret; } else { if (pm_suspend_target_state != PM_SUSPEND_MEM) { + if (pcie->use_pm_opp) { + ret = qcom_pcie_set_max_opp(dev); + if (ret) { + dev_err(dev, "Failed to set max OPP in resume: %d\n", ret); + return ret; + } + } + ret = icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", From 262750445409c4e181e55c2a8a46703ab81c96ca Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 6 Jul 2026 15:03:40 +0200 Subject: [PATCH 0978/1330] UBUNTU: Start new release Ignore: yes Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index abe70f56d21da..1eb6f4c99aa60 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,3 +1,11 @@ +linux-qcom (7.0.0-1008.11) UNRELEASED; urgency=medium + + CHANGELOG: Do not edit directly. Autogenerated at release. + CHANGELOG: Use the printchanges target to see the current changes. + CHANGELOG: Use the insertchanges target to create the final log. + + -- Kuba Pawlak Mon, 06 Jul 2026 15:03:39 +0200 + linux-qcom (7.0.0-1006.8) resolute; urgency=medium * resolute/linux-qcom: 7.0.0-1006.8 -proposed tracker (LP: #2154429) From 90a3832addda450b571affcd5595465e5543da9b Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Thu, 9 Jul 2026 16:29:20 +0200 Subject: [PATCH 0979/1330] UBUNTU: Ubuntu-qcom-7.0.0-1008.11 Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 3101 +++++++++++++++++++++++++++++++- debian.qcom/config/annotations | 1 - debian.qcom/reconstruct | 6 + 3 files changed, 3102 insertions(+), 6 deletions(-) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 1eb6f4c99aa60..439bc5f14e546 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,10 +1,3101 @@ -linux-qcom (7.0.0-1008.11) UNRELEASED; urgency=medium +linux-qcom (7.0.0-1008.11) resolute; urgency=medium - CHANGELOG: Do not edit directly. Autogenerated at release. - CHANGELOG: Use the printchanges target to see the current changes. - CHANGELOG: Use the insertchanges target to create the final log. + * Miscellaneous Ubuntu changes + - [Config] qcom: build x1e80100 camcc/dispcc/gpucc/videocc in + - [Config] change CONFIG_MEMLAT_DEVFREQ to m + - [Config]: synchronize config after rebase to 7.0.0-28.28 + - SAUCE: fix struct qcom_edp_phy_cfg + + * Miscellaneous upstream changes + - WORKAROUND: arm64: dts: qcom: Add qref supply for PCIe PHYs + - PCI: dwc: Proceed with system suspend even if the endpoint doesn't + respond with PME_TO_Ack message + - wifi: ath12k: use lockdep_assert_in_rcu_read_lock() for RCU assertions + - Revert "arm64: dts: qcom: hamoa: Disable spi18 and fix qupv3_2 firmware- + name" + - FROMLIST: arm64: dts: qcom: hamoa-pmics: Add ADC support + - FROMLIST: arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros + - FROMLIST: PCI: qcom: Set max OPP before DBI access during resume + + [ Ubuntu: 7.0.0-28.28 ] + + * resolute/linux: 7.0.0-28.28 -proposed tracker (LP: #2157520) + * Backport ASoC SDCA, AMD SoundWire, and RT722 audio fixes (LP: #2154418) + - ASoC: amd: acp-sdw-legacy: rename the dmic component name + - SAUCE: ASoC: rt722-sdca: add FU06 Playback Switch for speaker mute + control + * MIPI camera of a BBG809N3A_B sensor SKU of the DELL Pro 14 Premium PA14260 + renders upside-down (LP: #2155837) + - SAUCE: media: ipu-bridge: correct platform handling for DELL Pro 14 + Premium PA14260 + * resolute ubuntu_kernel_selftests:seccomp_build test compilation issue + (LP: #2154174) + - SAUCE: selftests/seccomp fix compilation issue for amd64 + * [Ubuntu 26.04] Severe Performance Degradation on kernel 7.0.0-15 + (LP: #2154748) + - s390: Remove GENERIC_LOCKBREAK Kconfig option + - UBUNTU [Config]: Remove GENERIC_LOCKBREAK in s390x + * Fix no sound output device on Dell GhostRider PTL no camera SKU + (LP: #2156559) + - ASoC: Intel: sof_sdw: append dai type to dai link name unconditionally + * Fix no audio from right built-in speaker on HP ZBook with TAS2781 + amplifier (LP: #2156556) + - ALSA: hda/tas2781: Fix device-0 reset issue and handle -EXDEV in block + data processing + * Installer fails internally with a RSync error due to page fault + (LP: #2150640) + - ovl: keep err zero after successful ovl_cache_get() + * Internal display black screen on Intel Lunar Lake with eDP panel + (LP: #2156312) + - drm/i915/alpm: Allow LOBF only for platform that have Always on VRR TG + * Thunderbolt DP tunnel torn down during boot with LUKS Full Disk Encryption + (LP: #2155096) + - SAUCE: thunderbolt: Defer DP tunnel teardown until display driver is + ready + * watchdog: lenovo_se10_wdt: Add SE10 Gen 2 support (LP: #2154715) + - watchdog: lenovo_se10_wdt: Add support for SE10 Gen 2 platform + - watchdog: lenovo_se10_wdt: Fix use-after-free and resource leak risk + * [Ubuntu 26.04] KVM: IBM Test Accelerator for Z (TAZ) not working properly + (LP: #2153159) + - KVM: s390: only deliver service interrupt with payload + - KVM: s390: vsie: Allow non-zarch guests + - KVM: s390: vsie: Disable some bits when in ESA mode + - KVM: s390: vsie: Accommodate ESA prefix pages + - KVM: s390: Add KVM capability for ESA mode guests + * ubuntu_bpf failed to build on Resolute (error: expected ‘:’, ‘,’, ‘;’, ‘}’ + or ‘__attribute__’ before ‘__counted_by’) (LP: #2150071) + - tools/headers: Regenerate stddef.h to fix BPF selftests + * ubuntu_bpf: FTBFS with clang 23 / gcc 15 (LP: #2154343) + - selftests/bpf: Fix const qualifier warning in fexit_bpf2bpf.c + * ALSA: hda/tas2781 Audio Fix for the front-right speacker (LP: #2149770) + - ALSA: hda/tas2781: Fix sound abnormal issue on some SPI device + * Fix bad audio record quality when volume above 50% on Framework PTL + (LP: #2153155) + - ALSA: hda/realtek: fix mic boost on Framework PTL + * Patchset for TUXEDO devices (LP: #2152570) + - drm/i915/vbt: Add edp pipe joiner enable/disable bits + - drm/i915/dp: Avoid joiner for eDP if not enabled in VBT + - drm/amd/display: Add Idle state manager(ISM) + - drm/i915/backlight: Remove try_vesa_interface + - drm/i915/backlight: Use intel_panel variable instead of intel_connector + - drm/i915/backlight: Take luminance_set into account for VESA backlight + - drm/i915/backlight: Check luminance_set when disabling PWM via AUX VESA + backlight + - drm/i915/backlight: Short circuit intel_dp_aux_supports_hdr_backlight + - drm/i915/backlight: Update debug log during backlight setup + - drm/i915/backlight: Check if VESA backlight is possible + - drm/i915/backlight: Provide clear description on how backlight level is + controlled + - drm/i915/backlight: Fix VESA backlight possible check condition + * Resolute update: v7.0.12 upstream stable release (LP: #2156636) + - Input: usbtouchscreen - clamp NEXIO data_len/x_len to URB buffer size + - ACPI: button: Fix ACPI GPE handler leak during removal + - ACPI: button: Enable wakeup GPEs for ACPI buttons at probe time + - xfrm: move policy_bydst RCU sync from per-netns .exit to .pre_exit + - net/sched: sch_sfb: Replace direct dequeue call with peek and + qdisc_dequeue_peeked + - bcache: fix uninitialized closure object + - nfc: llcp: Fix use-after-free in llcp_sock_release() + - nfc: llcp: Fix use-after-free race in nfc_llcp_recv_cc() + - xfrm: Check for underflow in xfrm_state_mtu + - nfc: nxp-nci: i2c: use rising-edge IRQ on ACPI systems + - tools/bootconfig: Fix buf leaks in apply_xbc + - HID: remove duplicate hid_warn_ratelimited definition + - kunit: fix use-after-free in debugfs when using kunit.filter + - accel/rocket: fix UAF via dangling GEM handle in create_bo + - netfilter: synproxy: refresh tcphdr after skb_ensure_writable + - netfilter: xt_cpu: prefer raw_smp_processor_id + - netfilter: ebtables: fix OOB read in compat_mtw_from_user + - netfilter: nf_tables: fix dst corruption in same register operation + - vsock: keep poll shutdown state consistent + - net: netlink: fix sending unassigned nsid after assigned one + - net: netlink: don't set nsid on local notifications + - net/smc: Do not re-initialize smc hashtables + - net/iucv: fix locking in .getsockopt + - scsi: core: Run queues for all non-SDEV_DEL devices from + scsi_run_host_queues + - scsi: scsi_debug: Add missing newline in scsi_debug_device_reset() + - ipv4: free net->ipv4.sysctl_local_reserved_ports after + unregister_net_sysctl_table() + - ALSA: hda: cs35l56: Fix system name string leaks + - ALSA: pcm: oss: Fix setup list UAF on proc write error + - ASoC: Intel: bytcht_es8316: Fix MCLK leak on init errors + - net/mlx5: HWS: Reject unsupported remove-header action + - net: hsr: fix potential OOB access in supervision frame handling + - accel/ivpu: prevent uninitialized data bug in debugfs + - gpio: mxc: fix irq_high handling + - drm/i915/aux: use polling when irqs are unavailable + - net: Avoid checksumming unreadable skb tail on trim + - ethtool: rss: avoid modifying the RSS context response + - ethtool: rss: add missing errno on RSS context delete + - ethtool: rss: fix falsely ignoring indir table updates + - ethtool: rss: fix indir_table and hkey leak on get_rxfh failure + - ethtool: rss: fix hkey leak when indir_size is 0 + - ethtool: rss: avoid device context leak on reply-build failure + - ethtool: module: call ethnl_ops_complete() on module flash errors + - ethtool: module: avoid leaking a netdev ref on module flash errors + - ethtool: module: avoid racy updates to dev->ethtool bitfield + - ethtool: module: check fw_flash_in_progress under rtnl_lock + - ethtool: module: fix cleanup if socket used for flashing multiple + devices + - ethtool: cmis: require exact CDB reply length + - ethtool: cmis: fix u16-to-u8 truncation of msleep_pre_rpl + - ethtool: cmis: validate start_cmd_payload_size from module + - ethtool: cmis: validate fw->size against start_cmd_payload_size + - cxl/test: Update mock dev array before calling platform_device_add() + - blk-mq: reinsert cached request to the list + - tunnels: load network headers after skb_cow() in + iptunnel_pmtud_build_icmp[v6]() + - vxlan: do not reuse cached ip_hdr() value after skb_tunnel_check_pmtu() + - tunnels: do not assume transport header in iptunnel_pmtud_check_icmp() + - ksmbd: fix FSCTL permission bypass by adding a permission check for + FSCTL_SET_SPARSE + - ASoC: codecs: simple-mux: Fix enum control bounds check + - drm/xe: Restore IDLEDLY regiter on engine reset + - Bluetooth: 6lowpan: check skb_clone() return value in send_mcast_pkt() + - bonding: refuse to enslave CAN devices + - bridge: Fix sleep in atomic context in netlink path + - bridge: Fix sleep in atomic context in sysfs path + - ethtool: coalesce: cap profile updates at NET_DIM_PARAMS_NUM_PROFILES + - ethtool: tsconfig: fix reply error handling + - ethtool: linkstate: fix unbalanced ethnl_ops_complete() on PHY lookup + error + - ethtool: pse-pd: fix missing ethnl_ops_complete() + - ethtool: tsconfig: fix missing ethnl_ops_complete() + - ethtool: tsinfo: fix uninitialized stats on the by-PHC path + - ethtool: tsinfo: don't pass ERR_PTR to genlmsg_cancel on prepare failure + - ethtool: strset: fix header attribute index in ethnl_req_get_phydev() + - ethtool: eeprom: add missing ethnl_ops_begin() / _complete() during + fallback + - ethtool: eeprom: add more safeties to EEPROM Netlink fallback + - ipv6: rpl: fix hdrlen overflow in ipv6_rpl_srh_decompress() + - net/sched: Revert "net/sched: Restrict conditions for adding duplicating + netems to qdisc tree" + - net/sched: fix packet loop on netem when duplicate is on + - net: Introduce skb tc depth field to track packet loops + - net/sched: Fix ethx:ingress -> ethy:egress -> ethx:ingress mirred loop + - net/sched: act_mirred: Fix blockcast recursion bypass leading to stack + overflow + - net/sched: act_mirred: Fix return code in early mirred redirect error + paths + - net: hibmcge: disable Relaxed Ordering to fix RX packet corruption + - net: hibmcge: move dma_rmb() after dma_sync_single_for_cpu() in RX path + - net/handshake: Use spin_lock_bh for hn_lock + - nvme-tcp: store negative errno in queue->tls_err + - net/handshake: Pass negative errno through handshake_complete() + - net/handshake: hand off the pinned file reference to accept_doit + - net/handshake: Take a long-lived file reference at submit + - net/handshake: Drain pending requests at net namespace exit + - dpll: zl3073x: detect DPLL channel count from chip ID at runtime + - dpll: zl3073x: add die temperature reporting for supported chips + - dpll: export __dpll_device_change_ntf() for use under dpll_lock + - dpll: zl3073x: use __dpll_device_change_ntf() and remove change_work + - Bluetooth: l2cap: clear chan->ident on ECRED reconfiguration success + - Bluetooth: L2CAP: Fix possible crash on l2cap_ecred_conn_rsp + - Bluetooth: hci_sync: Set HCI_CMD_DRAIN_WORKQUEUE during device close + - Bluetooth: hci_sync: Reset device counters in hci_dev_close_sync() + - gpio: adnp: fix flow control regression caused by scoped_guard() + - gpio: virtuser: Fix uninitialized data bug in + gpio_virtuser_direction_do_write() + - gpio: rockchip: convert bank->clk to devm_clk_get_enabled() + - gpio: rockchip: teardown bugs and resource leaks + - net: mana: Add NULL guards in teardown path to prevent panic on attach + failure + - net: mana: Skip redundant detach on already-detached port + - sctp: fix race between sctp_wait_for_connect and peeloff + - net: pcs: pcs-mtk-lynxi: fix bpi-r3 serdes configuration + - vsock/virtio: bind uarg before filling zerocopy skb + - ipv6: fix possible infinite loop in rt6_fill_node() + - ipv6: fix possible infinite loop in fib6_select_path() + - net: skbuff: fix pskb_carve leaking zcopy pages + - Revert "ipv6: preserve insertion order for same-scope addresses" + - Revert "x86/fpu: Refine and simplify the magic number check during + signal return" + - drm/i915/psr: Add defininitions for INTEL_WA_REGISTER_CAPS DPCD register + - drm/i915/psr: Read Intel DPCD workaround register + - drm/i915/psr: Apply Intel DPCD workaround when SDP on prior line used + - iio: imu: st_lsm6dsx: fix stack leak in tagged FIFO buffer + - iio: imu: adis16550: fix stack leak in trigger handler + - iio: pressure: bmp280: fix stack leak in bmp580 trigger handler + - usb: typec: ucsi: ccg: reject firmware images without a ':' record + header + - usb: typec: tcpm: validate VDO count in Discover Identity ACK handlers + - usb: typec: tcpm: bound altmode_desc[] per iteration in + svdm_consume_modes() + - usb: typec: ucsi: displayport: NAK DP_CMD_CONFIGURE without a payload + VDO + - usb: typec: altmodes/displayport: validate count before reading Status + Update VDO + - usb: typec: wcove: don't write past struct pd_message in + wcove_read_rx_buffer() + - usb: typec: tcpm/tcpci_maxim: validate header NDO against RX_BYTE_CNT + - usb: typec: ucsi: validate connector number in ucsi_connector_change() + - USB: serial: safe_serial: fix memory corruption with small endpoint + - media: rc: igorplugusb: fix control request setup packet + - Input: ims-pcu - fix usb_free_coherent() size in ims_pcu_buffers_free() + - USB: serial: cypress_m8: fix memory corruption with small endpoint + - HID: quirks: Add ALWAYS_POLL quirk for SIGMACHIP USB mouse + - Bluetooth: btusb: Allow firmware re-download when version matches + - mm/vmalloc: do not trigger BUG() on BH disabled context + - hpfs: fix a crash if hpfs_map_dnode_bitmap fails + - mm/damon/sysfs-schemes: delete tried region in regions_rmdirs() + - ipc: limit next_id allocation to the valid ID range + - mm: memcontrol: propagate NMI slab stats to memcg vmstats + - mm/migrate_device: fix pgtable leak in migrate_vma_insert_huge_pmd_page + - memfd: deny writeable mappings when implying SEAL_WRITE + - zram: fix use-after-free in zram_writeback_endio + - mm/rmap: initialize nr_pages to 1 at loop start in try_to_unmap_one + - auxdisplay: line-display: fix OOB read on zero-length message_store() + - smb: client: fix uninitialized variable in smb2_writev_callback + - Bluetooth: L2CAP: use chan timer to close channels in cleanup_listen() + - Bluetooth: L2CAP: fix chan ref leak in l2cap_chan_timeout() on !conn + - Bluetooth: HIDP: fix missing length checks in hidp_input_report() + - Bluetooth: ISO: fix UAF in iso_recv_frame + - Bluetooth: ISO: serialize iso_sock_clear_timer with socket lock + - Bluetooth: hci_conn: Fix memory leak in hci_le_big_terminate() + - Bluetooth: hci_qca: Use 100 ms SSR delay for rampatch and NVM loading + - Bluetooth: hci_sync: fix UAF in hci_le_create_cis_sync + - Input: xpad - fix out-of-bounds access for Share button + - parport: Fix race between port and client registration + - rust_binder: Avoid holding lock when dropping delivered_death + - rust_binder: avoid calling pending_oneway_finished() on TF_UPDATE_TXN + - USB: cdc-acm: Fix bit overlap and move quirk definitions to header + - KVM: arm64: Correctly cap ZCR_EL2 provided by a guest hypervisor + - KVM: arm64: PMU: Preserve AArch32 counter low bits + - KVM: SVM: Flush the current TLB when transitioning from xAVIC => x2AVIC + - KVM: SEV: Require in-GHCB scratch area if GHCB v2+ is in use + - KVM: SEV: Ignore Port I/O requests of length '0' + - KVM: SEV: Use the size of the PSC header as the minimum size for PSC + requests + - KVM: SEV: WARN if KVM attempts to setup scratch area with min_len==0 + - KVM: SEV: Compute the correct max length of the in-GHCB scratch area + - KVM: SEV: Check PSC request indices against the actual size of the + buffer + - KVM: SEV: Use READ_ONCE() when reading entries/indices from PSC buffer + - KVM: SEV: Don't explicitly pass PSC buffer to snp_begin_psc() + - gpio: shared: undo the vote of the proxy on GPIO free + - gpio: shared: fix deadlock on shared proxy's parent removal + - gpio: shared: fix lockdep false positive by removing unneeded lock + - Disable -Wattribute-alias for clang-23 and newer + - iio: adc: xilinx-xadc: Fix sequencer mode in postdisable for dual mux + - iio: adc: npcm: fix unbalanced clk_disable_unprepare() + - iio: dac: ad3530r: Fix AD3531/AD3531R powerdown mode strings + - iio: dac: max5821: fix return value check in powerdown sync + - iio: dac: ad5686: fix ref bit initialization for single-channel parts + - iio: dac: ad5686: fix input raw value check + - iio: dac: ad5686: acquire lock when doing powerdown control + - iio: dac: ad5686: fix powerdown control on dual-channel devices + - iio: adc: mt6359: fix unchecked return value in mt6358_read_imp + - iio: adc: viperboard: Fix error handling in vprbrd_iio_read_raw + - iio: adc: ad4695: Fix call ordering in offload buffer postenable + - iio: adc: nxp-sar-adc: fix division by zero in write_raw + - iio: adc: nxp-sar-adc: Avoid division by zero + - iio: adc: nxp-sar-adc: zero-initialize dma_slave_config + - iio: gyro: itg3200: fix i2c read into the wrong stack location + - iio: gyro: adis16260: fix division by zero in write_raw + - iio: ssp_sensors: cancel delayed work_refresh on remove + - iio: temperature: tsys01: fix broken PROM checksum validation + - iio: magnetometer: st_magn: fix default DRDY pin selection for LIS2MDL + - iio: light: veml6070: Fix resource leak in probe error path + - iio: Fix iio_multiply_value use in iio_read_channel_processed_scale + - iio: chemical: mhz19b: reject oversized serial replies + - iio: chemical: scd30: fix division by zero in write_raw + - iio: light: cm3323: fix reg_conf not being initialized correctly + - iio: buffer: hw-consumer: fix use-after-free in error path + - iio: buffer: Fix DMA fence leak in iio_buffer_enqueue_dmabuf() + - USB: serial: omninet: fix memory corruption with small endpoint + - usb: cdns3: gadget: fix request skipping after clearing halt + - usb: cdns3: plat: fix leaked usb2_phy initialization on usb3_phy + acquisition failure + - usb: cdns3: plat: fix unbalanced pm_runtime_forbid() call permanently + leaks the runtime PM usage counter across bind/unbind cycles + - usb: dwc2: Fix use after free in debug code + - Input: elan_i2c - validate firmware size before use + - i2c: davinci: fix division by zero on missing clock-frequency + - x86/ftrace: Relocate %rip-relative percpu refs in dynamic trampolines + - wireguard: send: append trailer after expanding head + - bpf: sockmap: fix tail fragment offset in bpf_msg_push_data + - macsec: fix replay protection at XPN lower-PN wrap + - ipv6: exthdrs: refresh nh pointer after ipv6_hop_jumbo() + - ASoC: qcom: q6asm-dai: fix error handling in prepare and set_params + - octeontx2-af: validate body pcifunc in rvu_mbox_handler_rep_event_notify + - ipv6: exthdrs: refresh nh after handling HAO option + - ip6: vti: Use ip6_tnl.net in vti6_siocdevprivate(). + - ipv6: validate extension header length before copying to cmsg + - xfrm: input: hold netns during deferred transport reinjection + - l2tp: use refcount_inc_not_zero in l2tp_session_get_by_ifname + - ip6: vti: Use ip6_tnl.net in vti6_changelink(). + - net: skbuff: fix missing zerocopy reference in pskb_carve helpers + - spi: spi-mem: avoid mutating op template in spi_mem_supports_op() + - HID: wacom: Fix OOB write in wacom_hid_set_device_mode() + - iommu, debugobjects: avoid gcc-16.1 section mismatch warnings + - nfc: hci: fix out-of-bounds read in HCP header parsing + - xfrm: route MIGRATE notifications to caller's netns + - xfrm: ipcomp: Free destination pages on acomp errors + - xfrm: ah: use skb_to_full_sk in async output callbacks + - ALSA: scarlett2: Fix 2i2 Gen 4 direct monitor gain on firmware 2417 + - ALSA: firewire-motu: Protect register DSP event queue positions + - netfilter: conntrack: tcp: do not force CLOSE on invalid-seq RST without + direction check + - ASoC: qcom: q6asm-dai: close stream only when running + - ASoC: qcom: q6asm-dai: do not set stream state in event and trigger + callbacks + - xfrm: esp: restore combined single-frag length gate + - ALSA: hda/realtek: Fix speaker output on ASUS ROG Strix G615LP + - xfrm: iptfs: reset runtime state when cloning SAs + - dma-buf: fix UAF in dma_buf_fd() tracepoint + - Input: xpad - add "Nova 2 Lite" from GameSir + - Input: xpad - add support for ASUS ROG RAIKIRI II + - ksmbd: OOB read regression in smb_check_perm_dacl() ACE-walk loops + - misc: rp1: Send IACK on IRQ activate to fix kdump/kexec + - Input: atmel_mxt_ts - fix boundary check in mxt_prepare_cfg_mem + - Input: synaptics - add LEN2058 to SMBus passlist for ThinkPad E490 + - dt-bindings: usb: Fix EIC7700 USB reset's issue + - comedi: comedi_test: fix check for valid scan_begin_src in + waveform_ai_cmdtest() + - comedi: comedi_test: Fix limiting of convert_arg in + waveform_ai_cmdtest() + - counter: Fix refcount leak in counter_alloc() error path + - tty: serial: pch_uart: add check for dma_alloc_coherent() + - tty: serial: samsung: Remove redundant port lock acquisition in rx + helpers + - uio: uio_pci_generic_sva: fix double free of devm_kzalloc() memory + - usb: chipidea: core: convert ci_role_switch to local variable + - usb: core: Fix up Interrupt IN endpoints with bogus wBytesPerInterval + - usb: dwc3: xilinx: fix error handling in zynqmp init error paths + - usb: musb: omap2430: Fix use-after-free in omap2430_probe() + - USB: quirks: add NO_LPM for Lenovo ThinkPad USB-C Dock Gen2 hub + controllers + - usb: storage: Add quirks for PNY Elite Portable SSD + - usbip: vudc: Fix use after free bug in vudc_remove due to race condition + - usb: usbtmc: check URB actual_length for interrupt-IN notifications + - usb: usbtmc: reject interrupt endpoints with small wMaxPacketSize + - usb: typec: tipd: Fix error code in tps6598x_probe() + - usb: typec: tcpm: improve handling of DISCOVER_MODES failures + - usb: typec: ucsi: Check if power role change actually happened before + handling + - usb: typec: ucsi: Don't update power_supply on power role change if not + connected + - USB: serial: option: add MeiG SRM813Q + - USB: serial: option: add missing RSVD(5) flag for Rolling RW135R-GL + - USB: serial: belkin_sa: validate interrupt status length + - USB: serial: cypress_m8: validate interrupt packet headers + - USB: serial: digi_acceleport: fix memory corruption with small endpoints + - USB: serial: keyspan: fix missing indat transfer sanity check + - USB: serial: mxuport: fix memory corruption with small endpoint + - USB: serial: mct_u232: fix memory corruption with small endpoint + - USB: serial: mct_u232: fix missing interrupt-in transfer sanity check + - usb: gadget: uvc: hold opts->lock across XU walks in uvc_function_bind + - usb: gadget: net2280: Fix double free in probe error path + - usb: gadget: f_hid: fix device reference leak in hidg_alloc() + - usb: gadget: composite: fix integer underflow in WebUSB GET_URL handling + - usb: gadget: dummy_hcd: Reject hub port requests for non-existent ports + - usb: gadget: f_fs: copy only received bytes on short ep0 read + - usb: gadget: f_fs: serialize DMABUF cancel against request completion + - thunderbolt: property: Reject u32 wrap in tb_property_entry_valid() + - thunderbolt: property: Reject dir_len < 4 to prevent size_t underflow + - thunderbolt: property: Cap recursion depth in __tb_property_parse_dir() + - scsi: fcoe: Reject FIP descriptors with zero fip_dlen in CVL walker + - scsi: scsi_transport_fc: Widen FPIN pname walker counter to u32 + - scsi: target: iscsi: Fix CRC overread and double-free in + iscsit_handle_text_cmd() + - scsi: target: iscsi: Bound iscsi_encode_text_output() appends to rsp_buf + - scsi: target: iscsi: Validate CHAP_R length before base64 decode + - drm/hyperv: validate resolution_count and fix WIN8 fallback + - drm/hyperv: validate VMBus packet size in receive callback + - drm/gem: fix race between change_handle and handle_delete + - drm/i915/color: Fix HDR pre-CSC LUT programming loop + - drm/i915/psr: Block DC states on vblank enable when Panel Replay + supported + - drm/i915/psr: Use DC_OFF wake reference to block DC6 on vblank enable + - drm/i915: Fix potential UAF in TTM object purge + - drm/amd/pm/si: Disregard vblank time when no displays are connected + - serial: altera_jtaguart: handle uart_add_one_port() failures + - serial: qcom-geni: fix UART_RX_PAR_EN bit position + - serial: qcom_geni: fix kfifo underflow when flush precedes DMA + completion IRQ + - serial: sh-sci: fix memory region release in error path + - serial: zs: Fix swapped RI/DSR modem line transition counting + - serial: fsl_lpuart: fix rx buffer and DMA map leaks in start_rx_dma + - drm/amdkfd: fix NULL pointer bug in svm_range_set_attr + - drm/amdkfd: fix a vulnerability of integer overflow in kfd debugger + - drm/amdkfd: Check for pdd drm file first in CRIU restore path + - drm/amdgpu: fix lock leak on ENOMEM in AMDGPU_GEM_OP_GET_MAPPING_INFO + - drm/amdgpu: fix calling VM invalidation in amdgpu_hmm_invalidate_gfx + - drm/amdgpu: fix amdgpu_hmm_range_get_pages + - drm/amdgpu: check num_entries in GEM_OP GET_MAPPING_INFO + - serial: dz: Fix bootconsole message clobbering at chip reset + - serial: dz: Fix bootconsole handover lockup + - serial: dz: Convert to use a platform device + - serial: zs: Fix bootconsole handover lockup + - serial: zs: Switch to using channel reset + - serial: zs: Convert to use a platform device + - serial: core: introduce guard(uart_port_lock_check_sysrq_irqsave) + - serial: 8250: dispatch SysRq character in serial8250_handle_irq() + - serial: 8250_dw: dispatch SysRq character in dw8250_handle_irq() + - platform/x86/intel/vsec: Refactor base_addr handling + - platform/x86/intel/vsec: Make driver_data info const + - platform/x86/intel/vsec: Fix enable_cnt imbalance on PCIe error recovery + - rxrpc: Fix RESPONSE packet verification to extract skb to a linear + buffer + - ALSA: hda/realtek: Fix mute and mic-mute LEDs for HP Envy X360 15-fh0xxx + - ALSA: hda/realtek: Fix mute and mic-mute LEDs for HP 16 Piston OmniBook + X + - arm64: tlb: Flush walk cache when unsharing PMD tables + - i2c: tegra: make tegra_i2c_mutex_unlock() return void + - hwmon: (pmbus) Add support for guarded PMBus lock + - hwmon: (pmbus/adm1266) serialize sequencer_state debugfs read with + pmbus_lock + - hwmon: (pmbus/adm1266) serialize GPIO PMBus accesses with pmbus_lock + - net: phy: micrel: fix LAN8814 QSGMII soft reset + - xhci: tegra: Fix ghost USB device on dual-role port unplug + - mailbox: Fix NULL message support in mbox_send_message() + - usb: core: Fix SuperSpeed root hub wMaxPacketSize + - tools: ynl: add scope qualifier for definitions + - Linux 7.0.12 + * Resolute update: v7.0.12 upstream stable release (LP: #2156636) // + CVE-2026-46318 + - Revert "mm/hugetlbfs: update hugetlbfs to use mmap_prepare" + * Resolute update: v7.0.12 upstream stable release (LP: #2156636) // + CVE-2026-46322 + - tun: free page on build_skb failure in tun_xdp_one() + * Resolute update: v7.0.12 upstream stable release (LP: #2156636) // + CVE-2026-46320 + - tap: free page on error paths in tap_get_user_xdp() + * Resolute update: v7.0.12 upstream stable release (LP: #2156636) // + CVE-2026-46321 + - tun: free page on short-frame rejection in tun_xdp_one() + * CVE-2026-46316 // CVE-2026-46317 + - KVM: arm64: Reassign nested_mmus array behind mmu_lock + * CVE-2026-46316 + - KVM: arm64: vgic-its: Drop the translation cache reference only for the + erased entry + - KVM: arm64: Take the SRCU lock for page table walks in fault injection + and AT emulation + * Resolute update: v7.0.11 upstream stable release (LP: #2156390) + - iommu/amd: Fix illegal cap/mmio access in IOMMU debugfs + - iommu/amd: Remove latent out-of-bounds access in IOMMU debugfs + - ksmbd: close durable scavenger races against m_fp_list lookups + - ata: libata-scsi: improve readability of ata_scsi_qc_issue() + - ata: libata-scsi: do not use the deferred QC feature for ATA_DEFER_PORT + - ata: libata-scsi: do not use the deferred QC feature on PMPs with CBS + - ata: libata-scsi: do not needlessly defer commands when using PMP with + FBS + - sysfs: don't remove existing directory on update failure + - mm/damon/sysfs-schemes: call missing mem_cgroup_iter_break() + - ksmbd: fix null pointer dereference in compare_guid_key() + - ksmbd: fix null pointer dereference in proc_show_files() + - ksmbd: fix SID memory leak in set_posix_acl_entries_dacl() on overflow + - ksmbd: validate SID in parent security descriptor during ACL inheritance + - regulator: tps65219: fix irq_data.rdev not being assigned + - x86/mm: Disable broadcast TLB flush when PCID is disabled + - scripts/gdb: mm: cast untyped symbols in x86_page_ops + - smb: client: require net admin for CIFS SWN netlink + - smb: client: protect tc_count increment in + smb2_find_smb_sess_tcon_unlocked() + - smb: client: use data_len for SMB2 READ encrypted folioq copy + - smb/server: promote S_DEL_ON_CLS to S_DEL_PENDING when close + - hwmon: (pmbus/adm1266) widen blackbox-info buffer to I2C_SMBUS_BLOCK_MAX + - ALSA: ua101: Reject too-short USB descriptors + - ALSA: pcm: Don't setup bogus iov_iter for silencing + - ALSA: asihpi: Fix potential OOB array access at reading cache + - ALSA: scarlett2: Allow flash writes ending at segment boundary + - ACPI: battery: Fix system wakeup on critical battery status + - efi: Allocate runtime workqueue before ACPI init + - spi: amd: Set correct bus number in ACPI probe path + - io_uring/waitid: clear waitid info before copying it to userspace + - drivers/base/memory: fix memory block reference leak in poison + accounting + - ipv6: ioam: refresh hdr pointer before ioam6_event() + - mm/memory: fix spurious warning when unmapping device-private/exclusive + pages + - mm: fix __vm_normal_page() to handle missing support for + pmd_special()/pud_special() + - mm/memory_hotplug: fix memory block reference leak on remove + - mm/page_alloc: fix initialization of tags of the huge zero folio with + init_on_free + - mm/migrate_device: fix spinlock leak in migrate_vma_insert_huge_pmd_page + - selftests/mm: run_vmtests.sh: fix destructive tests invocation + - mm/damon: fix damos_stat tracepoint format for sz_applied + - net: wwan: iosm: fix potential memory leaks in ipc_imem_init() + - Bluetooth: fix UAF in l2cap_sock_cleanup_listen() vs l2cap_conn_del() + - Bluetooth: ISO: drop ISO_END frames received without prior ISO_START + - Bluetooth: bnep: Fix UAF read of dev->name + - Bluetooth: hci_uart: fix UAFs and race conditions in close and init + paths + - Bluetooth: L2CAP: ecred_reconfigure: send packed pdu, not stack pointer + - Bluetooth: hci_qca: Convert timeout from jiffies to ms + - Bluetooth: MGMT: validate Add Extended Advertising Data length + - Bluetooth: serialize accept_q access + - phonet/pep: disable BH around forwarded sk_receive_skb() + - net: bcmgenet: keep RBUF EEE/PM disabled + - net: devmem: reject dma-buf bind with non-page-aligned size or SG length + - net: phy: skip EEE advertisement write when autoneg is disabled + - net: hsr: defer node table free until after RCU readers + - net/mlx5e: Fix use-after-free in mlx5e_tx_reporter_timeout_recover + - net: ifb: report ethtool stats over num_tx_queues + - net: pse-pd: fix sign on -ENOENT check in of_load_pse_pis() + - netfilter: ip6t_hbh: reject oversized option lists + - netfilter: nf_queue: hold bridge skb->dev while queued + - netfilter: ipset: stop hash:* range iteration at end + - net: ethtool: fix NULL pointer dereference in phy_reply_size + - net: ethtool: phy: avoid NULL deref when PHY driver is unbound + - ACPI: driver: Check ACPI_COMPANION() against NULL during probe + - sched_ext: Fix missing warning in scx_set_task_state() default case + - sched_ext: Avoid UAF in scx_root_enable_workfn() init failure path + - l2tp: use list_del_rcu in l2tp_session_unhash + - qed: fix double free in qed_cxt_tables_alloc() + - ring-buffer: Fix reporting of missed events in iterator + - ring-buffer: Flush and stop persistent ring buffer on panic + - wifi: mac80211: capture fast-RX rate before mesh reuses skb->cb + - ipv6: ioam: add NULL check for idev in ipv6_hop_ioam() + - selftests: mptcp: drop nanoseconds width specifier + - mptcp: pm: fix ADD_ADDR timer infinite retry on option space + insufficient + - vsock/vmci: fix UAF when peer resets connection during handshake + - vsock/virtio: reset connection on receiving queue overflow + - ice: fix VF queue configuration with low MTU values + - wifi: ath11k: clear shared SRNG pointer state on restart + - wifi: iwlwifi: mvm: fix driver-set TX rates on old devices + - wifi: iwlwifi: mld: stop TX during firmware restart + - ipv4: raw: reject IP_HDRINCL packets with ihl < 5 + - ixgbevf: fix use-after-free in VEPA multicast source pruning + - rbd: eliminate a race in lock_dwork draining on unmap + - mptcp: do not drop partial packets + - mptcp: reset rcv wnd on disconnect + - lsm: hold cred_guard_mutex for lsm_set_self_attr() + - octeontx2-af: CGX: add bounds check to cgx_speed_mbps index + - octeontx2-pf: fix double free in rvu_rep_rsrc_init() + - igc: fix potential skb leak in igc_fpe_xmit_smd_frame() + - ice: fix locking around wait_event_interruptible_locked_irq + - ice: fix setting promisc mode while adding VID filter + - ice: restore PTP Rx timestamp config after ethtool set-channels + - wifi: cfg80211: advance loop vars in cfg80211_merge_profile() + - af_unix: Fix UAF read of tail->len in unix_stream_data_wait() + - wifi: mac80211: consume only present negotiated TTLM maps + - octeontx2-pf: avoid double free of pool->stack on AQ init failure + - cifs: Fix busy dentry used after unmounting + - tracing: Do not call map->ops->elt_free() if elt_alloc() fails + - ASoC: codecs: pcm512x: fix null-ptr dereference in + pcm512x_overclock_xxx_put() + - arm64: probes: Handle probes on hinted conditional branch instructions + - KVM: arm64: vgic-its: Reject restored DTE with out-of-range + num_eventid_bits + - KVM: arm64: vgic: Free private_irqs when init fails after allocation + - KVM: SVM: Disable AVIC IPI virtualization on Hygon Family 18h (erratum + #1235) + - riscv: kvm: return SBI_ERR_FAILURE for pmu_snapshot_set_shmem() when OOM + - riscv: kvm: return SBI_ERR_FAILURE for pmu_event_info() when OOM + - virt: sev-guest: Explicitly leak pages in unknown state + - i2c: tegra: fix pm_runtime leak on mutex_lock failure + - drm/bridge: chipone-icn6211: use devm_drm_bridge_add in i2c probe + - spi: qup: fix error pointer deref after DMA setup failure + - phy: exynos5-usbdrd: fix USB 2.0 HS PHY tuning values for Exynos7870 + - phy: tegra: xusb: Fix per-pad high-speed termination calibration + - phy: qcom-qmp-ufs: Fix kaanapali PHY PLL lock failure after SM8650 G4 + fix + - phy: qcom: edp: Unify generic DP/eDP swing and pre-emphasis tables + - phy: qcom: edp: Add eDP/DP mode switch support + - phy: qcom: edp: Fix AUX_CFG8 programming for DP mode + - scsi: isci: Fix use-after-free in device removal path + - spi: ep93xx: fix error pointer deref after DMA setup failure + - spi: sprd: fix error pointer deref after DMA setup failure + - spi: ti-qspi: fix use-after-free after DMA setup failure + - mm/slub: hold cpus_read_lock around flush_rcu_sheaves_on_cache() + - RDMA/siw: Reject MPA FPDU length underflow before signed receive math + - s390/cio: Restore GFP_DMA for CHSC allocation + - s390/pai: Disable duplicate read of kernel PAI counter value + - s390/pai: Fix missing PAI counter increments under heavy load + - fwctl: pds: Validate RPC input size before parsing + - LoongArch: kprobes: Use larch_insn_text_copy() to patch instructions + - LoongArch: Remove unused code to avoid build warning + - cpufreq: intel_pstate: Use correct scaling factor on Raptor Lake-E + - device property: set fwnode->secondary to NULL in fwnode_init() + - drm/i915/display: Copy color pipeline from plane in the primary joiner + pipe + - drm/msm: Fix shrinker deadlock + - drm/v3d: Fix use-after-free of CPU job query arrays on error path + - drm/v3d: Release indirect CSD GEM reference on CPU job free + - drm/virtio: use uninterruptible resv lock for plane updates + - drm/xe/multi_queue: Fix secondary queue error case + - drm/amdgpu/vpe: Force collaborate sync after TRAP + - drm/bridge: it66121: acquire reset GPIO in probe + - drm/bridge: megachips: remove bridge when irq request fails + - drm/amd/display: Fix integer overflow in bios_get_image() + - drm/amd/display: Validate GPIO pin LUT table size before iterating + - drm/amd/display: Validate payload length and link_index in + dc_process_dmub_aux_transfer_async + - batman-adv: v: stop OGMv2 on disabled interface + - batman-adv: tvlv: abort OGM send on tvlv append failure + - batman-adv: tvlv: reject oversized TVLV packets + - batman-adv: iv: recover OGM scheduling after forward packet error + - batman-adv: mcast: fix use-after-free in orig_node RCU release + - batman-adv: clear current gateway during teardown + - batman-adv: dat: handle forward allocation error + - batman-adv: fix fragment reassembly length accounting + - batman-adv: fix tp_meter counter underflow during shutdown + - batman-adv: frag: disallow unicast fragment in fragment + - batman-adv: bla: fix report_work leak on backbone_gw purge + - batman-adv: bla: avoid double decrement of bla.num_requests + - batman-adv: bla: avoid NULL-ptr deref for claim via dropped interface + - batman-adv: tp_meter: avoid use of uninit sender vars + - batman-adv: tp_meter: directly shut down timer on cleanup + - batman-adv: tp_meter: fix tp_vars reference leak in receiver shutdown + - batman-adv: tp_meter: fix race condition in send error reporting + - batman-adv: tp_meter: avoid role confusion in tp_list + - batman-adv: tt: fix TOCTOU race for reported vlans + - batman-adv: tt: reject oversized local TVLV buffers + - batman-adv: tt: avoid empty VLAN responses + - batman-adv: tt: fix negative last_changeset_len + - batman-adv: tt: fix negative tt_buff_len + - batman-adv: tt: prevent TVLV entry number overflow + - hwmon: (pmbus/adm1266) seed timestamp from the real-time clock + - hwmon: (pmbus/adm1266) reject implausible blackbox record_count + - hwmon: (pmbus/adm1266) include PEC byte in pmbus_block_xfer read buffer + - hwmon: (pmbus/adm1266) bounce blackbox records through a protocol-sized + buffer + - hwmon: (pmbus/adm1266) cap PDIO scan in get_multiple at ADM1266_PDIO_NR + - hwmon: (pmbus/adm1266) don't clobber GPIO bits before PDIO read in + get_multiple + - hwmon: (pmbus/adm1266) register the gpio_chip after pmbus_do_probe() + - hwmon: (pmbus/adm1266) register the nvmem device after pmbus_do_probe() + - hwmon: (pmbus/adm1266) reject short block-read responses in the GPIO + accessors + - pinctrl: mediatek: moore: implement gpio_chip::get_direction() + - pinctrl: qcom: ipq4019: mark gpio as a GPIO pin function + - arm64: dts: renesas: r8a78000: Fix SCIF brg_int clocks + - ARM: dts: renesas: genmai: Drop superfluous cells + - ARM: dts: renesas: rskrza1: Drop superfluous cells + - pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high + pins during suspend/resume + - pinctrl: renesas: rzg2l: Fix SMT register cache handling + - pinctrl: meson: amlogic-a4: fix deadlock issue + - pinctrl: qcom: Fix GPIO to PDC wake irq map for qcs615 + - kho: skip KHO for crash kernel + - mm/memfd_luo: report error when restoring a folio fails mid-loop + - HID: intel-thc-hid: Intel-quickspi: Fix some error codes + - HID: uclogic: Fix regression of input name assignment + - firmware: arm_ffa: Check for NULL FF-A ID table while driver + registration + - firmware: arm_ffa: Skip free_pages on RX buffer alloc failure + - firmware: arm_ffa: Fix per-vcpu self notifications handling in workqueue + - firmware: arm_ffa: Unregister bus notifier on teardown for FF-A v1.0 + - riscv: errata: Fix bitwise vs logical AND in MIPS errata patching + - riscv: Fix register corruption from uninitialized cregs on error + - riscv: mm: Fixup no5lvl failure when vaddr is invalid + - kunit: config: Enable KUNIT_DEBUGFS by default + - kunit: config: KUNIT_DEBUGFS should depend on DEBUG_FS + - pinctrl: qcom: Fix wakeirq map by removing disconnected irqs for sm8150 + - firmware: arm_ffa: Bound PARTITION_INFO_GET_REGS copies + - firmware: arm_ffa: Keep framework RX release under lock + - firmware: arm_ffa: Validate framework notification message layout + - firmware: arm_ffa: Align RxTx buffer size before mapping + - firmware: arm_ffa: Snapshot notifier callbacks under lock + - firmware: arm_ffa: Fix sched-recv callback partition lookup + - ARM: integrator: Fix early initialization + - ALSA: hda: cs35l56: Put ACPI device after setting companion + - ALSA: hda: cs35l41: Put ACPI device on missing physical node + - btrfs: tracepoints: fix sleep while in atomic context in + btrfs_sync_file() + - netfilter: x_tables: allow initial table replace without emitting audit + log message + - netfilter: x_tables: allocate hook ops while under mutex + - netfilter: x_tables: unregister the templates first + - netfilter: x_tables: add and use xt_unregister_table_pre_exit + - netfilter: x_tables: add and use xtables_unregister_table_exit + - netfilter: ebtables: move to two-stage removal scheme + - netfilter: ebtables: close dangling table module init race + - netfilter: x_tables: close dangling table module init race + - netfilter: bridge: eb_tables: close module init race + - netfilter: nf_conntrack_expect: restore helper propagation via + expectation + - kprobes: skip non-symbol addresses in kprobe_add_ksym_blacklist() + - test_kprobes: clear kprobes between test runs + - tcp: Fix imbalanced icsk_accept_queue count. + - net: napi: Avoid gro timer misfiring at end of busypoll + - net: shaper: Reject reparenting of existing nodes + - idpf: fix read_dev_clk_lock spinlock init in idpf_ptp_init() + - ice: fix setting RSS VSI hash for E830 + - ice: fix locking in ice_dcb_rebuild() + - ice: dpll: fix rclk pin state get for E810 + - ice: dpll: fix misplaced header macros + - net: lan966x: avoid unregistering netdev on register failure + - net: ti: icssm-prueth: fix eth_ports_node leak in probe + - phy: marvell: mvebu-a3700-utmi: fix incorrect USB2_PHY_CTRL register + access + - phy: spacemit: Remove incorrect clk_disable() in spacemit_usb2phy_init() + - NFSD: Fix infinite loop in layout state revocation + - ASoC: sdw_utils: Add quirk to ignore RT712 CODEC_MIC + - ASoC: sdw_utils: Add quirk to ignore RT721 CODEC_MIC + - fprobe: Fix unregister_fprobe() to wait for RCU grace period + - fs/statmount: fix slab out-of-bounds write in statmount_mnt_idmap + - fs: Fix return in jfs_mkdir and orangefs_mkdir + - irqchip/ath79-cpu: Remove unused function + - fs: fix forced iversion increment on lazytime timestamp updates + - ublk: reject max_sectors smaller than PAGE_SECTORS in parameter + validation + - nsfs: fix wrong error code returned for pidns ioctls + - irq_work: Fix use-after-free in irq_work_single() on PREEMPT_RT + - nvme: fix bio leak on mapping failure + - nvme-pci: fix use-after-free in nvme_free_host_mem() + - zonefs: handle integer overflow in zonefs_fname_to_fno + - tcp: Fix out-of-bounds access for twsk in tcp_ao_established_key(). + - ASoC: SOF: amd: Fix error code handling in psp_send_cmd() + - powerpc: 82xx: fix uninitialized pointers with free attribute + - powerpc: fix dead default for GUEST_STATE_BUFFER_TEST + - powerpc/hv-gpci: fix preempt count leak in sysfs show paths + - netfs: Fix cancellation of a DIO and single read subrequests + - netfs: Fix missing locking around retry adding new subreqs + - netfs: Fix missing barriers when accessing stream->subrequests + locklessly + - netfs: Fix netfs_read_to_pagecache() to pause on subreq failure + - netfs: Fix potential for tearing in ->remote_i_size and ->zero_point + - netfs: Fix zeropoint update where i_size > remote_i_size + - netfs: fix VM_BUG_ON_FOLIO() issue in netfs_write_begin() call + - netfs: Fix overrun check in netfs_extract_user_iter() + - netfs: Fix netfs_invalidate_folio() to clear dirty bit if all changes + gone + - netfs: Defer the emission of trace_netfs_folio() + - netfs: Fix streaming write being overwritten + - netfs: Fix potential deadlock in write-through mode + - netfs: Fix read-gaps to remove netfs_folio from filled folio + - netfs: Fix write streaming disablement if fd open O_RDWR + - netfs: Fix early put of sink folio in netfs_read_gaps() + - netfs: Fix leak of request in netfs_write_begin() error handling + - netfs: Fix potential UAF in netfs_unlock_abandoned_read_pages() + - netfs: Fix partial invalidation of streaming-write folio + - netfs: Fix folio->private handling in netfs_perform_write() + - netfs: Fix netfs_read_folio() to wait on writeback + - netfs, afs: Fix write skipping in dir/link writepages + - afs: Fix the locking used by afs_get_link() + - net: ethernet: cortina: Make RX SKB per-port + - net: ethernet: cortina: Drop half-assembled SKB + - net: ethernet: cortina: Carry over frag counter + - net: ethernet: cs89x0: remove stale CONFIG_MACH_MX31ADS reference + - wifi: ath11k: fix error path leaks in some WMI WOW calls + - wifi: ath11k: fix error path leak in ath11k_tm_cmd_wmi_ftm() + - wifi: ath10k: skip WMI and beacon transmission when device is wedged + - net: shaper: flip the polarity of the valid flag + - net: shaper: fix trivial ordering issue in net_shaper_commit() + - net: shaper: reject duplicate leaves in GROUP request + - net: shaper: set ret to -ENOMEM when genlmsg_new() fails in group_doit + - net: shaper: fix undersized reply skb allocation in GROUP command + - net: shaper: enforce singleton NETDEV scope with id 0 + - net: shaper: reject QUEUE scope handle with missing id + - block: don't overwrite bip_vcnt in bio_integrity_copy_user() + - block: recompute nr_integrity_segments in blk_insert_cloned_request + - HID: quirks: really enable the intended work around for appledisplay + - block: bio-integrity: Fix null-ptr-deref in bio_integrity_map_user() + - accel/qaic: Add overflow check to remap_pfn_range during mmap + - net/smc: avoid NULL deref of conn->lnk in smc_msg_event tracepoint + - ethtool: fix ethnl_bitmap32_not_zero() bit interval semantics + - drm/msm/dpu: fix UV scanlines calculation for YUV UBWC formats + - drm/msm/dpu: Fix Kaanapali CWB register configuration + - drm/msm/dsi: don't dump registers past the mapped region + - drm/msm/dpu: don't mix devm and drmm functions + - block: rename struct gendisk zone_wplugs_lock field + - block: allow submitting all zone writes from a single context + - block: fix handling of dead zone write plugs + - selftests: ublk: cap nthreads to kernel's actual nr_hw_queues + - x86/mce: Restore MCA polling interval halving + - Documentation: intel_pstate: Fix description of asymmetric packing with + SMT + - drm/msm: Fix GMEM_BASE for A650 + - drm/msm/a6xx: Add soft fuse detection support + - drm/msm/adreno: Fix a reference leak in a6xx_gpu_init() + - drm/msm/adreno: fix userspace-triggered crash on a2xx-a4xx + - drm/msm/a6xx: Restore sysprof_active + - drm/msm: Fix iommu_map_sgtable() return value check and avoid WARN + - drm/msm/a6xx: Check kzalloc return in a8xx_hfi_send_perf_table + - ASoC: intel: sof_sdw: Prepare for configuration without a jack + - ASoC: sdw_utils: cs42l43: allow spk component names to be combined + - ASoC: sdw_utils: Check speaker component string allocation + - riscv: Docs: fix unmatched quote warning + - powerpc/time: Remove redundant preempt_disable|enable() calls from + arch_irq_work_raise() + - net/smc: reject CHID-0 ACCEPT that matches an empty ism_dev slot + - net: tls: fix off-by-one in sg_chain entry count for wrapped sk_msg ring + - net: tls: prevent chain-after-chain in plain text SG + - net: phy: DP83TC811: add reading of abilities + - ovpn: tcp - use cached peer pointer in ovpn_tcp_close() + - ovpn: respect peer refcount in CMD_NEW_PEER error path + - ovpn: fix race between deleting interface and adding new peer + - cifs: client: stage smb3_reconfigure() updates and restore ctx on + failure + - phy: apple: atc: Fix typec switch/mux leak on unbind + - gcc-plugins: Always define CONST_CAST_GIMPLE and CONST_CAST_TREE + - x86/xen: Fix xen_e820_swap_entry_with_ram() + - vfio/pci: Check BAR resources before exporting a DMABUF + - ovpn: disable BHs when updating device stats + - tls: Preserve sk_err across recvmsg() when data has been copied + - net/mlx5: Do not restore destination-less TC rules + - net/mlx5: Skip disabled vports when setting max TX speed + - scsi: sd: Fix return code handling in sd_spinup_disk() + - ASoC: codecs: fs210x: fix possible buffer overflow + - iommupt: Directly call iommupt's unmap_range() + - iommupt: Avoid rewalking during map + - iommu: Fix loss of errno on map failure for classic ops + - iommu: Fix up map/unmap debugging for iommupt domains + - iommu: Handle unmap error when iommu_debug is enabled + - iommupt: Check for missing PAGE_SIZE in the pgsize_bitmap + - iommupt: Fix the end_index calculation in __map_range_leaf() + - ALSA: scarlett2: Add missing error check when initialise Autogain Status + - ALSA: hda/ca0132: Disable auto-detect on manual output select + - cachefiles: Fix error return when vfs_mkdir() fails + - io_uring/net: punt IORING_OP_BIND async if it needs file create + - vsock/virtio: fix zerocopy completion for multi-skb sends + - btrfs: check for subvolume before deleting squota qgroup + - btrfs: fix squota accounting during enable generation + - ASoC: amd: acp-sdw-legacy: check CPU DAI name before logging + - spi: mtk-snfi: Fix resource leak in mtk_snand_read_page_cache() + - netfilter: nft_inner: release local_lock before re-enabling softirqs + - ALSA: hda/realtek: Use ALC287_FIXUP_TXNW2781_I2C for ASUS Strix Gxx5 + - drm/msm/snapshot: fix dumping of the unaligned regions + - hwmon: (lm90) Stop work before releasing hwmon device + - hwmon: (lm90) Add lock protection to lm90_alert + - wifi: iwlwifi: mld: fix TSO segmentation explosion when AMSDU is + disabled + - wifi: iwlwifi: mld: don't dereference a pointer before NULL checking it + - dma-mapping: move dma_map_resource() sanity check into debug code + - drm/gem: Make the GEM LRU lock part of drm_device + - drm/xe/gsc: Fix double-free of managed BO in error path + - drm/xe/vf: Fix signature of print functions + - drm/xe/pf: Fix CFI failure in debugfs access + - drm/xe: Consolidate workaround entries for Wa_14019988906 + - drm/xe: Consolidate workaround entries for Wa_18033852989 + - drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN1 + - drm/xe/tuning: Apply windower hardware filtering setting on Xe3 and Xe3p + - drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN4 + - wifi: ath11k: fix peer resolution on rx path when peer_id=0 + - wifi: ath12k: fix EHT TX MCS limitation due to wrong 20 MHz-only parsing + - drm/mediatek: mtk_hdmi_ddc_v2: Fix non-static global variable + - drm/mediatek: mtk_hdmi_v2: Fix non-static global variable + - drm/mediatek: mtk_cec: Fix non-static global variable + - drm/mediatek: mtk_hdmi_ddc: Fix non-static global variable + - io_uring: propagate array_index_nospec opcode into req->opcode + - srcu: Don't queue workqueue handlers to never-online CPUs + - cgroup/rstat: validate cpu before css_rstat_cpu() access + - net/mlx5e: xsk: Fix unlocked writing to ICOSQ + - cifs: Fix undefined variables + - ice: ptp: serialize E825 PHY timer start with PTP lock + - ice: ptp: use primary NAC semaphore on E825 + - igc: set tx buffer type for SMD frames + - drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP + - phy: qcom: qmp-usbc: Fix out-of-bounds array access in dp swing config + - kbuild: pacman-pkg: make "rc" releases adhere to pacman versioning + scheme + - net: dsa: mt7530: fix FDB entries not aging out with short timeout + - net: dsa: mt7530: preserve VLAN tags on trapped link-local frames + - net: mana: Fix TOCTOU double-fetch of hwc_msg_id from DMA buffer + - platform/surface: aggregator_registry: omit battery & AC nodes on + Surface Laptop 7 + - platform/x86: adv_swbutton: Check ACPI_HANDLE() against NULL + - platform/x86: hp_accel: Check ACPI_COMPANION() against NULL + - platform/x86: intel-hid: Check ACPI_HANDLE() against NULL + - platform/x86: intel_sar: Check ACPI_HANDLE() against NULL + - platform/x86: intel-vbtn: Check ACPI_HANDLE() against NULL + - platform/x86: uniwill-laptop: Properly initialize charging threshold + - platform/x86: uniwill-laptop: Accept charging threshold of 0 + - platform/x86: uniwill-laptop: Fix behavior of "force" module param + - platform/x86: asus-armoury: fix mini-LED mode get/set on MODE2 devices + - ASoC: soc-utils: Add missing va_end in snd_soc_ret() + - drm/amdgpu: Align amdgpu_gtt_mgr entries to TLB size on Tahiti (v2) + - drm/amdgpu/vce1: Check that the GPU address is < 128 MiB + - drm/amdgpu/vce1: Fix VCE 1 firmware size and offsets + - RDMA/mana_ib: Report max_msg_sz in mana_ib_query_port + - RDMA/rtrs: Fix use-after-free in path file creation cleanup + - bridge: mcast: Fix a possible use-after-free when removing a bridge port + - net: phy: honor eee_disabled_modes in phy_support_eee() + - net: phy: honor eee_disabled_modes in phy_advertise_eee_all() + - net: airoha: Fix NPU RX DMA descriptor bits + - pds_core: fix error handling in pdsc_devcmd_wait + - pds_core: fix debugfs_lookup dentry leak and error handling + - erofs: fix managed cache race for unaligned extents + - erofs: harden h_shared_count in erofs_init_inode_xattrs() + - erofs: fix metabuf leak in inode xattr initialization + - wifi: mac80211: bounds-check link_id in ieee80211_ml_epcs + - wifi: mac80211: fix MLE defragmentation + - wifi: mac80211: fix multi-link element inheritance + - wifi: wilc1000: fix dma_buffer leak on bus acquire failure + - ALSA: seq: Serialize UMP output teardown with event_input + - cgroup: rstat: relax NMI guard after switch to try_cmpxchg + - tracing: Avoid NULL return from hist_field_name() on truncation + - Bluetooth: hci_sync: Fix not setting mask for + HCI_EVT_LE_ALL_REMOTE_FEATURES_COMPLETE + - Bluetooth: btintel_pcie: Fix incorrect MAC access programming + - Bluetooth: btmtk: fix urb->setup_packet leak in error paths + - udp: gso: Fix handling checksum in __udp_gso_segment + - udp: Fix UDP length on last GSO_PARTIAL segment + - net/mlx5e: Fix eswitch mode block underflow on IPsec acquire SA + - net: shaper: annotate the data races + - net: shaper: rework the VALID marking (again) + - crypto/krb5, rxrpc: Fix lack of pre-decrypt/pre-verify length checks + - rxrpc: Fix DATA decrypt vs splice() by copying data to buffer in recvmsg + - net: ag71xx: check error for platform_get_irq + - bpf, skmsg: fix verdict sk_data_ready racing with ktls rx + - tcp: fix stale per-CPU tcp_tw_isn leak enabling ISN prediction + - net: stmmac: eswin: fix HSP CSR init ordering after clock enable + - net: stmmac: eswin: clear TXD and RXD delay registers during + initialization + - net: stmmac: eswin: correct RGMII delay granularity to 20 ps + - net: stmmac: eswin: validate RGMII delay values + - gpio: cdev: check if uAPI v2 config attributes are correctly zeroed + - gpio: aggregator: fix a potential use-after-free + - gpio: aggregator: stop using dev-sync-probe + - gpio: aggregator: remove the software node when deactivating the + aggregator + - gpio: aggregator: lock device when calling device_is_bound() + - ASoC: cs35l56: Fix flushing of IRQ work in cs35l56_sdw_remove() + - drm/xe/oa: Fix exec_queue leak on width check in stream open + - ASoC: cs-amp-lib: Fix wrong sizeof() in + _cs_amp_set_efi_calibration_data() + - ASoC: cs-amp-lib: Fix missing dput() after debugfs_lookup() + - selftests: net: Fix checksums in xdp_native + - nvme-pci: fix dma_vecs leak on p2p memory + - nvme-pci: fix dma mapping leak on data setup error + - octeontx2-af: npc: Fix allmulticast skip logic for LBK and SDP VFs + - net: mana: validate rx_req_idx to prevent out-of-bounds array access + - tap: fix stack info leak in tap_ioctl() SIOCGIFHWADDR + - net: airoha: Disable GDM2 forwarding before configuring GDM2 loopback + - pds_core: ensure null-termination for firmware version strings + - net: enetc: fix missing error code when pf->vf_state allocation fails + - io_uring/nop: pass all errors to userspace + - blk-mq: pop cached request if it is usable + - ksmbd: fix durable reconnect error path file lifetime + - LoongArch: kprobes: Fix handling of fatal unrecoverable recursions + - block: avoid use-after-free in disk_free_zone_resources() + - Documentation: laptops: Update documentation for uniwill laptops + - platform/x86: uniwill-laptop: Do not enable the charging limit even when + forced + - drm/msm: Restore second parameter name in purge() and evict() + - security/keys: fix missed RCU read section on lookup + - Linux 7.0.11 + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) + - blk-cgroup: wait for blkcg cleanup before initializing new disk + - md: suppress spurious superblock update error message for dm-raid + - fs/omfs: reject s_sys_blocksize smaller than OMFS_DIR_START + - fs/mbcache: cancel shrink work before destroying the cache + - md/raid1: fix the comparing region of interval tree + - fs: fix archiecture-specific compat_ftruncate64 + - drbd: Balance RCU calls in drbd_adm_dump_devices() + - loop: fix partition scan race between udev and loop_reread_partitions() + - block: fix zones_cond memory leak on zone revalidation error paths + - nilfs2: reject zero bd_oblocknr in nilfs_ioctl_mark_blocks_dirty() + - blk-cgroup: fix disk reference leak in blkcg_maybe_throttle_current() + - pstore/ram: fix resource leak when ioremap() fails + - erofs: include the trailing NUL in FS_IOC_GETFSLABEL + - md: fix array_state=clear sysfs deadlock + - ublk: reset per-IO canceled flag on each fetch + - blk-wbt: remove WARN_ON_ONCE from wbt_init_enable_default() + - erofs: handle 48-bit blocks/uniaddr for extra devices + - md: remove unused static md_wq workqueue + - md: wake raid456 reshape waiters before suspend + - dcache: permit dynamic_dname()s up to NAME_MAX + - btrfs: fix the inline compressed extent check in inode_need_compress() + - btrfs: fix deadlock between reflink and transaction commit when using + flushoncommit + - btrfs: do not reject a valid running dev-replace + - OPP: debugfs: Use performance level if available to distinguish between + rates + - OPP: Move break out of scoped_guard in dev_pm_opp_xlate_required_opp() + - ACPI: x86: cmos_rtc: Clean up address space handler driver + - ACPI: x86: cmos_rtc: Improve coordination with ACPI TAD driver + - devres: fix missing node debug info in devm_krealloc() + - thermal/drivers/spear: Fix error condition for reading st,thermal-flags + - debugfs: check for NULL pointer in debugfs_create_str() + - debugfs: fix placement of EXPORT_SYMBOL_GPL for debugfs_create_str() + - soundwire: debugfs: initialize firmware_file to empty string + - amd-pstate: Fix memory leak in amd_pstate_epp_cpu_init() + - amd-pstate: Update cppc_req_cached in fast_switch case + - cpufreq: Pass the policy to cpufreq_driver->adjust_perf() + - PCI: use generic driver_override infrastructure + - platform/wmi: use generic driver_override infrastructure + - vdpa: use generic driver_override infrastructure + - s390/cio: use generic driver_override infrastructure + - s390/ap: use generic driver_override infrastructure + - bus: fsl-mc: use generic driver_override infrastructure + - locking/mutex: Rename mutex_init_lockep() + - locking/mutex: Fix wrong comment for CONFIG_DEBUG_LOCK_ALLOC + - irqchip/irq-pic32-evic: Address warning related to wrong printf() + formatter + - hrtimer: Avoid pointless reprogramming in __hrtimer_start_range_ns() + - hrtimer: Reduce trace noise in hrtimer_start() + - locking: Fix rwlock and spinlock lock context annotations + - signal: Fix the lock_task_sighand() annotation + - ww-mutex: Fix the ww_acquire_ctx function annotations + - perf/amd/ibs: Account interrupt for discarded samples + - perf/amd/ibs: Preserve PhyAddrVal bit when clearing PhyAddr MSR + - perf/amd/ibs: Avoid calling perf_allow_kernel() from the IBS NMI handler + - x86/tdx: Fix the typo in TDX_ATTR_MIGRTABLE + - rust: sync: atomic: Remove bound `T: Sync` for `Atomic::from_ptr()` + - sparc64: vdso: Link with -z noexecstack + - scripts/gdb: timerlist: Adapt to move of tk_core + - locking: Fix rwlock support in + - sched/topology: Compute sd_weight considering cpuset partitions + - x86/irqflags: Preemptively move include paravirt.h directive where it + belongs + - sched/topology: Fix sched_domain_span() + - irqchip/renesas-rzg2l: Fix error path in rzg2l_irqc_common_probe() + - ASoC: Intel: avs: Check maximum valid CPUID leaf + - ASoC: Intel: avs: Include CPUID header at file scope + - x86/vdso: Clean up remnants of VDSO32_NOTE_MASK + - firmware: dmi: Correct an indexing error in dmi.h + - fs/resctrl: Report invalid domain ID when parsing io_alloc_cbm + - sched: Make class_schedulers avoid pushing current, and get rid of + proxy_tag_curr() + - sched/rt: Skip group schedulable check with rt_group_sched=0 + - wifi: ath11k: fix memory leaks in beacon template setup + - wifi: mwifiex: Fix memory leak in mwifiex_11n_aggregate_pkt() + - wifi: rtlwifi: pci: fix possible use-after-free caused by unfinished + irq_prepare_bcn_tasklet + - bpf: test_run: Fix the null pointer dereference issue in + bpf_lwt_xmit_push_encap + - wifi: ath12k: account TX stats only when ACK/BA status is present + - wifi: ath12k: Fix legacy rate mapping for monitor mode capture + - selftests/bpf: Handle !CONFIG_SMC in bpf_smc.c + - wifi: ieee80211: fix definition of EHT-MCS 15 in MRU + - dpaa2: add independent dependencies for FSL_DPAA2_SWITCH + - [Config] Disable CONFIG_FSL_DPAA2_SWITCH on armhf and ppc64el + - dpaa2: compile dpaa2 even CONFIG_FSL_DPAA2_ETH=n + - s390/bpf: Zero-extend bpf prog return values and kfunc arguments + - powerpc/pgtable-frag: Fix bad page state in pte_frag_destroy + - powerpc/64s: Fix unmap race with PMD migration entries + - module: Fix freeing of charp module parameters when CONFIG_SYSFS=n + - wifi: libertas: use USB anchors for tracking in-flight URBs + - wifi: libertas: don't kill URBs in interrupt context + - bpf: Do not allow deleting local storage in NMI + - selftests/nolibc: fix test_file_stream() on musl libc + - selftests/nolibc: Fix build with host headers and libc + - tools/nolibc/printf: Change variables 'c' to 'ch' and 'tmpbuf[]' to + 'outbuf[]' + - tools/nolibc/printf: Move snprintf length check to callback + - tools/nolibc: MIPS: fix clobbers of 'lo' and 'hi' registers on different + ISAs + - tools/nolibc: avoid -Wundef warning for __STDC_VERSION__ + - wifi: mt76: mt7996: fix the behavior of radar detection + - wifi: mt76: mt7996: fix iface combination for different chipsets + - wifi: mt76: mt7996: Set mtxq->wcid just for primary link + - wifi: mt76: mt7996: Reset mtxq->idx if primary link is removed in + mt7996_vif_link_remove() + - wifi: mt76: mt7996: Switch to the secondary link if the default one is + removed + - wifi: mt76: mt7996: Clear wcid pointer in mt7996_mac_sta_deinit_link() + - wifi: mt76: mt7996: Reset ampdu_state state in case of failure in + mt7996_tx_check_aggr() + - wifi: mt76: mt7921: Reset ampdu_state state in case of failure in + mt76_connac2_tx_check_aggr() + - wifi: mt76: mt7925: Fix incorrect MLO mode in firmware control + - wifi: mt76: mt7615: fix use_cts_prot support + - wifi: mt76: mt7915: fix use_cts_prot support + - wifi: mt76: mt7925: prevent NULL pointer dereference in + mt7925_tx_check_aggr() + - wifi: mt76: mt7925: prevent NULL vif dereference in + mt7925_mac_write_txwi + - wifi: mt76: mt7996: fix FCS error flag check in RX descriptor + - wifi: mt76: mt7921: Place upper limit on station AID + - wifi: mt76: Fix memory leak destroying device + - wifi: mt76: mt7996: Fix NPU stop procedure + - wifi: mt76: npu: Add missing rx_token_size initialization + - wifi: mt76: mt7925: drop puncturing handling from BSS change path + - wifi: mt76: mt7925: fix potential deadlock in mt7925_roc_abort_sync + - wifi: mt76: Fix memory leak after mt76_connac_mcu_alloc_sta_req() + - wifi: mt76: mt7925: fix tx power setting failure after chip reset + - wifi: mt76: mt7921: fix potential deadlock in mt7921_roc_abort_sync + - wifi: mt76: fix deadlock in remain-on-channel + - wifi: mt76: fix backoff fields and max_power calculation + - arm64: cpufeature: Make PMUVer and PerfMon unsigned + - bpf: Switch CONFIG_CFI_CLANG to CONFIG_CFI + - wifi: mt76: mt7996: fix wrong DMAD length when using MAC TXP + - wifi: mt76: mt7996: fix struct mt7996_mcu_uni_event + - wifi: mt76: mt7915: fix use-after-free bugs in mt7915_mac_dump_work() + - wifi: mt76: mt7996: fix use-after-free bugs in mt7996_mac_dump_work() + - wifi: mt76: mt7921: fix 6GHz regulatory update on connection + - wifi: mt76: mt7996: Add missing CHANCTX_STA_CSA property + - wifi: mt76: mt7996: Remove link pointer dependency in + mt7996_mac_sta_remove_links() + - wifi: mt76: mt7996: Decrement sta counter removing the link in + mt7996_mac_reset_sta_iter() + - wifi: mt76: fix multi-radio on-channel scanning + - wifi: mt76: support upgrading passive scans to active + - wifi: mt76: mt7996: fix RRO EMU configuration + - bpf: Fix refcount check in check_struct_ops_btf_id() + - selftests/bpf: Fix sockmap_multi_channels reliability + - bpf: Use RCU-safe iteration in dev_map_redirect_multi() SKB path + - bpf: Fix variable length stack write over spilled pointers + - arm_mpam: Ensure in_reset_state is false after applying configuration + - arm_mpam: Reset when feature configuration bit unset + - bpf,arc_jit: Fix missing newline in pr_err messages + - wifi: rtw89: phy: fix uninitialized variable access in + rtw89_phy_cfo_set_crystal_cap() + - drivers/vfio_pci_core: Change PXD_ORDER check from switch case to + if/else block + - r8152: fix incorrect register write to USB_UPHY_XTAL + - selftests/tracing: Fix to make --logdir option work again + - selftests/tracing: Fix to check awk supports non POSIX strtonum() + - powerpc/crash: fix backup region offset update to elfcorehdr + - powerpc/crash: Update backup region offset in elfcorehdr on memory + hotplug + - bpf: Fix abuse of kprobe_write_ctx via freplace + - macvlan: annotate data-races around port->bc_queue_len_used + - bpf: Use copy_map_value_locked() in alloc_htab_elem() for BPF_F_LOCK + - bpf: Fix stale offload->prog pointer after constant blinding + - net: ethernet: ti-cpsw:: rename soft_reset() function + - net: ethernet: ti-cpsw: fix linking built-in code to modules + - wifi: brcmfmac: Fix error pointer dereference + - wifi: mac80211: handle VHT EXT NSS in ieee80211_determine_our_sta_mode() + - bpf: Drop task_to_inode and inet_conn_established from lsm sleepable + hooks + - bpf: Prefer vmlinux symbols over module symbols for unqualified kprobes + - wifi: ath10k: fix station lookup failure during disconnect + - bpf: Fix linked reg delta tracking when src_reg == dst_reg + - net: dropreason: add SKB_DROP_REASON_RECURSION_LIMIT + - net: plumb drop reasons to __dev_queue_xmit() + - net: qdisc_pkt_len_segs_init() cleanup + - net: pull headers in qdisc_pkt_len_segs_init() + - arm64: entry: Don't preempt with SError or Debug masked + - ACPI: AGDI: fix missing newline in error message + - arm64: kexec: Remove duplicate allocation for trans_pgd + - bpf: Propagate error from visit_tailcall_insn + - bpf: Fix ld_{abs,ind} failure path analysis in subprogs + - bpf: Remove static qualifier from local subprog pointer + - mptcp: better mptcp-level RTT estimator + - bpf: Fix use-after-free in offloaded map/prog info fill + - macsec: Support VLAN-filtering lower devices + - net: bcmgenet: fix off-by-one in bcmgenet_put_txcb + - net: bcmgenet: fix leaking free_bds + - net: bcmgenet: fix racing timeout handler + - net: airoha: Add dma_rmb() and READ_ONCE() in airoha_qdma_rx_process() + - eth: fbnic: Use wake instead of start + - netfilter: xt_socket: enable defrag after all other checks + - netfilter: nft_fwd_netdev: check ttl/hl before forwarding + - bpf: fix mm lifecycle in open-coded task_vma iterator + - bpf: switch task_vma iterator from mmap_lock to per-VMA locks + - bpf: return VMA snapshot from task_vma iterator + - bpf: Fix RCU stall in bpf_fd_array_map_clear() + - net: hamradio: 6pack: fix uninit-value in sixpack_receive_buf + - net: airoha: Fix FE_PSE_BUF_SET configuration if PPE2 is available + - bpf: Enforce regsafe base id consistency for BPF_ADD_CONST scalars + - selftests/bpf: fix __jited_unpriv tag name + - net/sched: cls_fw: fix NULL dereference of "old" filters before change() + - net/sched: act_ct: Only release RCU read lock after ct_ft + - selftests: netfilter: nft_tproxy.sh: adjust to socat changes + - net: mana: Use pci_name() for debugfs directory naming + - net: mana: Move current_speed debugfs file to mana_init_port() + - net: airoha: Add missing RX_CPU_IDX() configuration in + airoha_qdma_cleanup_rx_queue() + - net_sched: fix skb memory leak in deferred qdisc drops + - bpf: Fix same-register dst/src OOB read and pointer leak in sock_ops + - bpf: Allow instructions with arena source and non-arena dest registers + - selftests/bpf: Fix reg_bounds to match new tnum-based refinement + - net/rds: Optimize rds_ib_laddr_check + - net/rds: Restrict use of RDS/IB to the initial network namespace + - bpf: Fix OOB in pcpu_init_value + - ppp: require CAP_NET_ADMIN in target netns for unattached ioctls + - net: ipa: Fix programming of QTIME_TIMESTAMP_CFG + - net: ipa: Fix decoding EV_PER_EE for IPA v5.0+ + - dt-bindings: net: dsa: nxp,sja1105: make spi-cpol optional for sja1110 + - net: phy: fix a return path in get_phy_c45_ids() + - net/mlx5e: Fix features not applied during netdev registration + - net/mlx5e: IPsec, fix ASO poll timeout with read_poll_timeout_atomic() + - net: ethernet: mtk_eth_soc: initialize PPE per-tag-layer MTU registers + - net: fix skb_ext_total_length() BUILD_BUG_ON with + CONFIG_GCOV_PROFILE_ALL + - bpf: reject short IPv4/IPv6 inputs in bpf_prog_test_run_skb + - Bluetooth: L2CAP: Fix printing wrong information if SDU length exceeds + MTU + - Bluetooth: hci_ldisc: Clear HCI_UART_PROTO_INIT on error + - Bluetooth: fix locking in hci_conn_request_evt() with HCI_PROTO_DEFER + - Bluetooth: l2cap: Add missing chan lock in l2cap_ecred_reconf_rsp + - Bluetooth: SCO: check for codecs->num_codecs == 1 before assigning to + sco_pi(sk)->codec + - net: phy: qcom: at803x: Use the correct bit to disable extended next + page + - udp: Force compute_score to always inline + - tcp: Don't set treq->req_usec_ts in cookie_tcp_reqsk_init(). + - sctp: fix missing encap_port propagation for GSO fragments + - sctp: disable BH before calling udp_tunnel_xmit_skb() + - selftests/namespaces: remove unused utils.h include from + listns_efault_test + - net, bpf: fix null-ptr-deref in xdp_master_redirect() for down master + - net: airoha: Fix VIP configuration for AN7583 SoC + - net: airoha: Add missing PPE configurations in airoha_ppe_hw_init() + - drm/panel: ilitek-ili9882t: Select DRM_DISPLAY_DSC_HELPER + - selftests/futex: Fix incorrect result reporting of futex_requeue test + item + - drm/komeda: fix integer overflow in AFBC framebuffer size check + - dma-fence: Fix sparse warnings due __rcu annotations + - drm/gpusvm: Fix unbalanced unlock in drm_gpusvm_scan_mm() + - drm/virtio: Allow importing prime buffers when 3D is enabled + - ASoC: soc-compress: use function to clear symmetric params + - PCI/TPH: Allow TPH enable for RCiEPs + - PCI: endpoint: pci-epf-vntb: Fix MSI doorbell IRQ unwind + - PCI: endpoint: pci-epf-test: Don't free doorbell IRQ unless requested + - PCI: endpoint: pci-ep-msi: Fix error unwind and prevent double alloc + - drm/sun4i: mixer: Fix layer init code + - drm/sun4i: backend: fix error pointer dereference + - drm/xe: Consolidate workaround entries for Wa_14019877138 + - drm/xe: Consolidate workaround entries for Wa_14019386621 + - drm/xe/xe2_hpg: Drop invalid workaround Wa_15010599737 + - gpu: nova-core: gsp: use empty slices instead of [0..0] ranges + - gpu: nova-core: gsp: fix improper handling of empty slot in cmdq + - drm/amdkfd: Removed commented line for MQD queue priority + - PCI: imx6: Fix device node reference leak in imx_pcie_probe() + - crypto: inside-secure/eip93 - fix register definition + - ASoC: sti: Return errors from regmap_field_alloc() + - ASoC: sti: use managed regmap_field allocations + - dm cache: fix null-deref with concurrent writes in passthrough mode + - dm cache: fix write path cache coherency in passthrough mode + - dm cache: fix write hang in passthrough mode + - dm cache policy smq: fix missing locks in invalidating cache blocks + - dm cache: fix concurrent write failure in passthrough mode + - dm cache: fix dirty mapping checking in passthrough mode switching + - dm-mpath: don't stop probing paths at presuspend + - drm/amd/ras: Fix type size of remainder argument + - dt-bindings: mmc: dwcmshc-sdhci: Fix resets array validation + - drm/amdgpu: GFX12.1 scratch memory limit up to 57-bit + - platform/chrome: chromeos_tbmc: Drop wakeup source on remove + - gpu: nova-core: use checked arithmetic in FWSEC firmware parsing + - gpu: nova-core: create falcon firmware DMA objects lazily + - gpu: nova-core: falcon: rename load parameters to reflect DMA dependency + - gpu: nova-core: firmware: fix and explain v2 header offsets computations + - PCI: dwc: ep: Fix MSI-X Table Size configuration in + dw_pcie_ep_set_msix() + - PCI: dwc: ep: Mirror the max link width and speed fields to all + functions + - PCI: dwc: Perform cleanup in the error path of dw_pcie_resume_noirq() + - dm cache metadata: fix memory leak on metadata abort retry + - dm log: fix out-of-bounds write due to region_count overflow + - iopoll: fix function parameter names in read_poll_timeout_atomic() + - drm/bridge: cadence: cdns-mhdp8546-core: Set the mhdp connector earlier + in atomic_enable() + - drm/bridge: cadence: cdns-mhdp8546-core: Add mode_valid hook to + drm_bridge_funcs + - drm/bridge: cadence: cdns-mhdp8546-core: Handle HDCP state in bridge + atomic check + - spi: nxp-xspi: Use reinit_completion() for repeated operations + - spi: nxp-fspi: Use reinit_completion() for repeated operations + - spi: fsl-qspi: Use reinit_completion() for repeated operations + - spi: axiado: Remove redundant pm_runtime_mark_last_busy() call + - media: i2c: og01a1b: Fix V4L2 subdevice data initialization on probe + - media: synopsys: VIDEO_DW_MIPI_CSI2RX should depend on ARCH_ROCKCHIP + - [Config] VIDEO_DW_MIPI_CSI2RX depends on ARCH_ROCKCHIP + - drm/amd/pm: Fix xgmi max speed reporting + - spi: atcspi200: fix mutex initialization order + - selftests/sched_ext: Add missing error check for exit__load() + - drm/v3d: Handle error from drm_sched_entity_init() + - drm/sun4i: Fix resource leaks + - crypto: inside-secure/eip93 - register hash before authenc algorithms + - PCI: rzg3s-host: Fix reset handling in probe error path + - PCI: rzg3s-host: Reorder reset assertion during suspend + - dt-bindings: PCI: renesas,r9a08g045s33-pcie: Fix naming properties + - iommu/riscv: Add IOTINVAL after updating DDT/PDT entries + - iommu/riscv: Skip IRQ count check when using MSI interrupts + - iommu/riscv: Add missing GENERIC_MSI_IRQ + - iommu/riscv: Stop polling when CQCSR reports an error + - drm/amdkfd: Update queue properties for metadata ring + - drm/amd/ras: Fix NULL deref in ras_core_ras_interrupt_detected() + - drm/amdgpu: Add default case in DVI mode validation + - regulator: dt-bindings: fp9931: Make vin-supply property as required + - regulator: fp9931: Fix handling of mandatory "vin" supply + - drm/amd/ras: Fix NULL deref in ras_core_get_utc_second_timestamp() + - drm/amdgpu: Drop redundant queue NULL check in hang detect worker + - drm/amdgpu: Remove dead negative offset check in + amdgpu_virt_init_critical_region() + - dm init: ensure device probing has finished in dm-mod.waitfor= + - fbdev: matroxfb: Mark variable with __maybe_unused to avoid W=1 build + break + - crypto: simd - reject compat registrations without __ prefixes + - crypto: tegra - Disable softirqs before finalizing request + - crypto: atmel-aes - guard unregister on error in atmel_aes_register_algs + - padata: Remove cpu online check from cpu add and removal + - padata: Put CPU offline callback in ONLINE section to allow failure + - PCI: dwc: rcar-gen4: Change EPC BAR alignment to 4K as per the + documentation + - accel/amdxdna: fix missing newline in pr_err message + - drm/amd/ras: Remove redundant NULL check in pending bad-bank list + iteration + - drm/amdgpu/gfx10: look at the right prop for gfx queue priority + - drm/amdgpu/gfx11: look at the right prop for gfx queue priority + - spi: hisi-kunpeng: prevent infinite while() loop in hisi_spi_flush_fifo + - PCI: sky1: Fix missing cleanup of ECAM config on probe failure + - drm/imagination: Switch reset_reason fields from enum to u32 + - iommu/tegra241-cmdqv: Set supports_cmd op in tegra241_vcmdq_hw_init() + - iommu/tegra241-cmdqv: Update uAPI to clarify HYP_OWN requirement + - drm/msm: add missing MODULE_DEVICE_ID definitions + - drm/msm/dpu: fix mismatch between power and frequency + - drm/msm/dsi: add the missing parameter description + - drm/msm/dpu: don't try using 2 LMs if only one DSC is available + - drm/msm/dsi: fix bits_per_pclk + - drm/msm/dsi: fix hdisplay calculation for CMD mode panel + - drm/msm/dsi: rename MSM8998 DSI version from V2_2_0 to V2_0_0 + - ASoC: rockchip: rockchip_sai: Set slot width for non-TDM mode + - tools/sched_ext: scx_pair: fix pair_ctx indexing for CPU pairs + - drm/panel: sharp-ls043t1le01: make use of prepare_prev_first + - drm/panel: simple: Correct G190EAN01 prepare timing + - PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion + support + - PCI: Prevent shrinking bridge window from its required size + - PCI: Fix premature removal from realloc_head list during resource + assignment + - crypto: hisilicon/sec2 - prevent req used-after-free for sec + - PCI: Fix alignment calculation for resource size larger than align + - iommu/riscv: Fix signedness bug + - ALSA: core: Validate compress device numbers without dynamic minors + - drm/amd/display: Avoid NULL dereference in dc_dmub_srv error paths + - ASoC: amd: acp: update dmic_num logic for acp pdm dmic + - drm/amd/pm/ci: Use highest MCLK on CI when MCLK DPM is disabled + - drm/amd/pm/ci: Disable MCLK DPM on problematic CI ASICs + - drm/amd/pm/smu7: Fix SMU7 voltage dependency on display clock + - drm/amd/pm/ci: Fix powertune defaults for Hawaii 0x67B0 + - drm/amd/pm/ci: Clear EnabledForActivity field for memory levels + - drm/amd/pm/ci: Fill DW8 fields from SMC + - drm/amd/pm/smu7: Add SCLK cap for quirky Hawaii board + - drm/amdgpu/uvd4.2: Don't initialize UVD 4.2 when DPM is disabled + - PCI/DPC: Log AER error info for DPC/EDR uncorrectable errors + - hwmon: (aspeed-g6-pwm-tach): remove redundant driver remove callback + - ALSA: hda/realtek: fix bad indentation for alc269 + - ALSA: hda/realtek: fix code style (ERROR: else should follow close brace + '}') + - ASoC: SOF: Intel: hda: Place check before dereference + - drm/msm/vma: Avoid lock in VM_BIND fence signaling path + - drm/msm/a6xx: Add missing aperture_lock init + - drm/msm: Reject fb creation from _NO_SHARE objs + - drm/msm: Fix VM_BIND UNMAP locking + - drm/msm/a6xx: Fix HLSQ register dumping + - drm/msm/shrinker: Fix can_block() logic + - drm/msm/a6xx: Fix dumping A650+ debugbus blocks + - drm/msm/a6xx: Use barriers while updating HFI Q headers + - drm/msm/a8xx: Fix the ticks used in submit traces + - drm/msm/a6xx: Switch to preemption safe AO counter + - drm/msm/a6xx: Correct OOB usage + - drm/msm/adreno: Implement gx_is_on() for A8x + - drm/msm/a6xx: Fix gpu init from secure world + - ALSA: hda/cmedia: Remove duplicate pin configuration parsing + - pmdomain: ti: omap_prm: Fix a reference leak on device node + - pmdomain: imx: scu-pd: Fix device_node reference leak during ->probe() + - PM: domains: De-constify fields in struct dev_pm_domain_attach_data + - drm/msm/dpu: drop INTF_0 on MSM8953 + - ASoC: fsl_micfil: Add access property for "VAD Detected" + - ASoC: fsl_micfil: Fix event generation in hwvad_put_enable() + - ASoC: fsl_micfil: Fix event generation in hwvad_put_init_mode() + - ASoC: fsl_micfil: Fix event generation in micfil_range_set() + - ASoC: fsl_micfil: Fix event generation in micfil_put_dc_remover_state() + - ASoC: fsl_micfil: Fix event generation in micfil_quality_set() + - ASoC: fsl_xcvr: Fix event generation in fsl_xcvr_arc_mode_put() + - ASoC: fsl_xcvr: Fix event generation in fsl_xcvr_mode_put() + - ASoC: fsl_easrc: Check the variable range in fsl_easrc_iec958_put_bits() + - ASoC: fsl_easrc: Fix value type in fsl_easrc_iec958_get_bits() + - ASoC: fsl_easrc: Change the type for iec958 channel status controls + - iommu/amd: Fix clone_alias() to use the original device's devid + - iommu/riscv: Remove overflows on the invalidation path + - ASoC: qcom: qdsp6: topology: check widget type before accessing data + - PCI: dwc: Fix type mismatch for kstrtou32_from_user() return value + - crypto: qat - disable 4xxx AE cluster when lead engine is fused off + - crypto: qat - disable 420xx AE cluster when lead engine is fused off + - crypto: qat - fix compression instance leak + - crypto: qat - fix type mismatch in RAS sysfs show functions + - crypto: iaa - fix per-node CPU counter reset in rebalance_wq_table() + - crypto: qat - use swab32 macro + - ALSA: hda: Notify IEC958 Default PCM switch state changes + - ASoC: rsnd: Fix potential out-of-bounds access of component_dais[] + - PCI: Enable AtomicOps only if Root Port supports them + - PCI: imx6: Keep Root Port MSI capability with iMSI-RX to work around + hardware bug + - PCI: aspeed: Fix IRQ domain leak on platform_get_irq() failure + - dt-bindings: PCI: imx6q-pcie: Fix maxItems of clocks and clock-names + - PCI: mediatek-gen3: Prevent leaking IRQ domains when IRQ not found + - gpu: nova-core: bitfield: fix broken Default implementation + - selftests/mm: skip migration tests if NUMA is unavailable + - Documentation: fix a hugetlbfs reservation statement + - Docs/admin-guide/mm/damn/lru_sort: fix intervals autotune parameter name + - Docs/mm/damon/index: fix typo: autoamted -> automated + - zram: do not permit params change after init + - selftest: memcg: skip memcg_sock test if address family not supported + - gpu: nova-core: remove redundant `.as_ref()` for `dev_*` print + - gpu: nova-core: fix missing colon in SEC2 boot debug message + - ALSA: scarlett2: Add missing sentinel initializer field + - ASoC: qcom: audioreach: explicitly enable speaker protection modules + - ASoC: SOF: compress: return the configured codec from get_params + - PCI/NPEM: Set LED_HW_PLUGGABLE for hotplug-capable ports + - tools/sched_ext: Fix off-by-one in scx_sdt payload zeroing + - ASoC: soc-component: re-add pcm_new()/pcm_free() + - ASoC: amd: name back to pcm_new()/pcm_free() + - ASoC: amd: ps: fix the pcm device numbering for acp pdm dmic + - ALSA: usb-audio: qcom: Fix incorrect type in enable_audio_stream + - PCI: tegra194: Fix polling delay for L2 state + - PCI: tegra194: Increase LTSSM poll time on surprise link down + - PCI: tegra194: Disable LTSSM after transition to Detect on surprise link + down + - PCI: tegra194: Don't force the device into the D0 state before L2 + - PCI: tegra194: Disable PERST# IRQ only in Endpoint mode + - PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk- + select" + - PCI: tegra194: Disable direct speed change for Endpoint mode + - PCI: tegra194: Set LTR message request before PCIe link up in Endpoint + mode + - PCI: tegra194: Allow system suspend when the Endpoint link is not up + - PCI: tegra194: Free up Endpoint resources during remove() + - PCI: tegra194: Use DWC IP core version + - PCI: dwc: Apply ECRC workaround to DesignWare 5.00a as well + - PCI: tegra194: Disable L1.2 capability of Tegra234 EP + - PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on + - drm/fb-helper: Fix a locking bug in an error path + - PCI: cadence: Add flags for disabling ASPM capability for broken Root + Ports + - PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports + - ASoC: SDCA: Fix cleanup inversion in class driver + - spi: rzv2h-rspi: Fix invalid SPR=0/BRDV=0 clock configuration + - spi: mtk-snfi: unregister ECC engine on probe failure and remove() + callback + - ALSA: sc6000: Keep the programmed board state in card-private data + - dm cache: fix missing return in invalidate_committed's error path + - sched_ext: Track @p's rq lock across set_cpus_allowed_scx -> + ops.set_cpumask + - sched_ext: Fix ops.cgroup_move() invocation kf_mask and rq tracking + - spi: cadence-qspi: Revert the filtering of certain opcodes in ODTR + - crypto: jitterentropy - replace long-held spinlock with mutex + - ALSA: usb-audio: Exclude Scarlett 18i20 1st Gen from SKIP_IFACE_SETUP + - ALSA: hda/realtek - fixed speaker no sound update + - gfs2: Call unlock_new_inode before d_instantiate + - fanotify: avoid/silence premature LSM capability checks + - fanotify: call fanotify_events_supported() before path_permission() and + security_path_notify() + - fuse: fix uninit-value in fuse_dentry_revalidate() + - ktest: Avoid undef warning when WARNINGS_FILE is unset + - ktest: Honor empty per-test option overrides + - ktest: Run POST_KTEST hooks on failure and cancellation + - vfio: selftests: fix crash in vfio_dma_mapping_mmio_test + - rtla/utils: Fix resource leak in set_comm_sched_attr() + - tools/rtla: Generate optstring from long options + - rtla: Fix segfault on multiple SIGINTs + - vfio: selftests: Build tests on aarch64 + - gfs2: less aggressive low-memory log flushing + - quota: Fix race of dquot_scan_active() with quota deactivation + - vfio: unhide vdev->debug_root + - gfs2: add some missing log locking + - gfs2: prevent NULL pointer dereference during unmount + - efi/capsule-loader: fix incorrect sizeof in phys array reallocation + - ksmbd: fix use-after-free from async crypto on Qualcomm crypto engine + - arm64: dts: mediatek: mt8365: Describe infracfg-nao as a pure syscon + - ARM: dts: mediatek: mt7623: fix efuse fallback compatible + - memory: tegra124-emc: Fix dll_change check + - memory: tegra30-emc: Fix dll_change check + - arm64: dts: imx8-apalis: Fix LEDs name collision + - arm64: dts: imx91-11x11-evk: change usdhc tuning step for eMMC and SD + - riscv: dts: spacemit: pcie: fix missing power regulator + - arm64: dts: mediatek: mt7988a-bpi-r4pro: fix model string + - arm64: dts: rockchip: Make Jaguar PCIe-refclk pin use pull-up config + - arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO + (M.2 W_DISABLE1) + - iommufd: vfio compatibility extension check for noiommu mode + - arm64: dts: qcom: sm6125-xiaomi-ginkgo: Remove board-id + - arm64: dts: qcom: sm6125-xiaomi-ginkgo: Correct reserved memory ranges + - arm64: dts: qcom: sm6125-xiaomi-ginkgo: Remove extcon + - arm64: dts: qcom: sm6125-xiaomi-ginkgo: Fix reserved gpio ranges + - arm64: dts: qcom: qcs6490-rubikpi3: Use lt9611 DSI Port B + - arm64: dts: qcom: talos: Add missing clock-names to GCC + - arm64: dts: ti: k3-am62l: include WKUP_UART0 in wakeup peripheral window + - arm64: dts: mediatek: mt6795: Fix gpio-ranges pin count + - arm64: dts: mediatek: mt7981b: Fix gpio-ranges pin count + - arm64: dts: mediatek: mt7986a: Fix gpio-ranges pin count + - iommufd/selftest: Fix page leaks in mock_viommu_{init,destroy} + - arm64: dts: imx8mp-kontron: Fix touch reset configuration on DL devices + - arm64: dts: imx8mp-kontron: Drop vmmc-supply to fix SD card on SMARC + eval carrier + - arm64: dts: imx8mp-hummingboard-pulse/cubox-m: fix vmmc gpio polarity + - arm64: dts: imx8mp-hummingboard-pulse: fix mini-hdmi dsi port reference + - ARM: dts: BCM5301X: Drop extra NAND controller compatible + - arm64: dts: qcom: msm8953-xiaomi-vince: correct wled ovp value + - arm64: dts: qcom: msm8937-xiaomi-land: correct wled ovp value + - arm64: dts: qcom: msm8953-xiaomi-daisy: fix backlight + - firmware: qcom_scm: don't opencode kmemdup + - soc: qcom: ubwc: disable bank swizzling for Glymur platform + - arm64: dts: rockchip: Fix Bluetooth stability on LCKFB TaiShan Pi + - Revert "arm64: dts: rockchip: add SPDIF audio to Beelink A1" + - arm64: dts: rockchip: Correct Fan Supply for Gameforce Ace + - arm64: dts: rockchip: Correct Joystick Axes on Gameforce Ace + - soc: qcom: ocmem: make the core clock optional + - soc: qcom: ocmem: register reasons for probe deferrals + - soc: qcom: ocmem: return -EPROBE_DEFER is ocmem is not available + - riscv: dts: spacemit: drop incorrect pinctrl for combo PHY + - arm64: dts: rockchip: Fix RK3562 EVB2 model name + - arm64: dts: rockchip: Add mphy reset to ufshc node + - bus: rifsc: fix RIF configuration check for peripherals + - arm64: dts: qcom: arduino-imola: fix faulty spidev node + - Revert "UBUNTU: SAUCE: arm64: dts: add missing denali-oled.dtb to + Makefile" + - arm64: dts: qcom: add missing denali-oled.dtb to Makefile + - arm64: dts: qcom: hamoa: correct Iris corners for the MXC rail + - arm64: dts: qcom: lemans: correct Iris corners for the MXC rail + - arm64: dts: qcom: monaco: correct Iris corners for the MXC rail + - arm64: dts: qcom: sm8550: correct Iris corners for the MXC rail + - arm64: dts: qcom: sm8650: correct Iris corners for the MXC rail + - arm64: dts: qcom: sm8750: correct Iris corners for the MXC rail + - arm64: dts: qcom: kaanapali: Fix GIC_ITS range length + - arm64: dts: qcom: milos: Fix GIC_ITS range length + - arm64: dts: qcom: sm8450: Fix GIC_ITS range length + - arm64: dts: qcom: sm8550: Fix GIC_ITS range length + - arm64: dts: qcom: sm8650: Fix GIC_ITS range length + - arm64: dts: qcom: sm8750: Fix GIC_ITS range length + - arm64: dts: qcom: sm8550: Fix xo clock supply of platform SD host + controller + - arm64: dts: qcom: sm8650: Fix xo clock supply of SD host controller + - arm64: dts: qcom: hamoa: Fix xo clock supply of platform SD host + controller + - arm64: dts: qcom: sm8450: Enable UHS-I SDR50 and SDR104 SD card modes + - arm64: dts: qcom: sm8550: Enable UHS-I SDR50 and SDR104 SD card modes + - arm64: dts: qcom: sm8650: Enable UHS-I SDR50 and SDR104 SD card modes + - arm64: dts: qcom: sm7225-fairphone-fp4: Fix conflicting bias pinctrl + - arm64: dts: qcom: sdm845-xiaomi-beryllium: Mark l1a regulator as powered + during boot + - arm64: dts: qcom: msm8917-xiaomi-riva: Fix board-id for all bootloader + - arm64: dts: ti: k3-am62p5-sk: Disable MMC1 internal pulls on data pins + - arm64: dts: ti: k3-am62l3-evm: Disable MMC1 internal pulls on data pins + - arm64: dts: ti: k3-am62-lp-sk: Enable internal pulls for MMC0 data pins + - arm64: dts: ti: k3-am62-verdin: Fix SPI_1 GPIO CS pinctrl label + - arm64: dts: freescale: imx8mp-tqma8mpql-mba8mp-ras314: fix UART1 RTS/CTS + muxing + - arm64: dts: imx91: Remove TMU's superfluous sensor ID + - arm64: dts: imx8mp-kontron: Fix boot order for PMIC and RTC + - arm64: dts: imx8dxl-evk: Use audio-graph-card2 for wm8960-2 and wm8960-3 + - arm64: dts: imx8mp-evk: Specify ADV7535 register addresses + - arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit + - arm64: dts: lx2160a: remove duplicate pinmux nodes + - arm64: dts: lx2160a: rename pinmux nodes for readability + - arm64: dts: lx2160a: add sda gpio references for i2c bus recovery + - arm64: dts: lx2160a: change zeros to hexadecimal in pinmux nodes + - arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word + - arm64: dts: imx8qm-mek: switch Type-C connector power-role to dual + - arm64: dts: imx8qxp-mek: switch Type-C connector power-role to dual + - soc/tegra: cbb: Set ERD on resume for err interrupt + - soc/tegra: cbb: Fix incorrect ARRAY_SIZE in fabric lookup tables + - soc/tegra: cbb: Fix cross-fabric target timeout lookup + - arm64: tegra: Fix RTC aliases + - soc/tegra: pmc: Add kerneldoc for reboot notifier + - soc/tegra: pmc: Correct function names in kerneldoc + - soc/tegra: pmc: Add kerneldoc for wake-up variables + - unshare: fix nsproxy leak in ksys_unshare() on set_cred_ucounts() + failure + - ocfs2/dlm: validate qr_numregions in dlm_match_regions() + - ocfs2/dlm: fix off-by-one in dlm_match_regions() region comparison + - soc: qcom: llcc: fix v1 SB syndrome register offset + - soc: qcom: aoss: compare against normalized cooling state + - arm64: dts: qcom: milos: Add missing CX power domain to GCC + - arm64: dts: qcom: sm8250: Add missing CPU7 3.09GHz OPP + - ARM: OMAP1: Fix DEBUG_LL and earlyprintk on OMAP16XX + - arm64/xor: fix conflicting attributes for xor_block_template + - lib: kunit_iov_iter: fix memory leaks + - ARM: dts: imx27-eukrea: replace interrupts with interrupts-extended + - firmware: arm_ffa: Use the correct buffer size during RXTX_MAP + - fwctl: Fix class init ordering to avoid NULL pointer dereference on + device removal + - ocfs2: fix listxattr handling when the buffer is full + - ocfs2: validate bg_bits during freefrag scan + - ocfs2: validate group add input before caching + - dmaengine: dw-axi-dmac: fix Alignment should match open parenthesis + - dmaengine: dw-axi-dmac: Remove unnecessary return statement from void + function + - phy: apple: apple: Use local variable for ioremap return value + - soundwire: bus: demote UNATTACHED state warnings to dev_dbg() + - soundwire: Intel: test bus.bpt_stream before assigning it + - dmaengine: mxs-dma: Fix missing return value from + of_dma_controller_register() + - soundwire: cadence: Clear message complete before signaling waiting + thread + - tracing: move __printf() attribute on __ftrace_vbprintk() + - tracing: Rebuild full_name on each hist_field_name() call + - hte: tegra194: remove Kconfig dependency on Tegra194 SoC + - [Config] Enable CONFIG_HTE_TEGRA194 on armhf + - remoteproc: xlnx: Fix sram property parsing + - stop_machine: Fix the documentation for a NULL cpus argument + - remoteproc: imx_rproc: Check return value of regmap_attach_dev() in + imx_rproc_mmio_detect_mode() + - ima: check return value of crypto_shash_final() in boot aggregate + - HID: asus: make asus_resume adhere to linux kernel coding standards + - HID: asus: do not abort probe when not necessary + - workqueue: devres: Add device-managed allocate workqueue + - power: supply: max77705: Drop duplicated IRQ error message + - power: supply: max77705: Free allocated workqueue and fix removal order + - mtd: physmap_of_gemini: Fix disabled pinctrl state check + - ima_fs: Correctly create securityfs files for unsupported hash algos + - dt-bindings: interrupt-controller: arm,gic-v3: Fix EPPI range + - mtd: spi-nor: core: correct the op.dummy.nbytes when check read + operations + - mtd: spi-nor: update spi_nor_fixups::post_sfdp() documentation + - mtd: spi-nor: micron-st: add SNOR_CMD_PP_8_8_8_DTR sfdp fixup for + mt35xu512aba + - mtd: spi-nor: swp: check SR_TB flag when getting tb_mask + - mtd: parsers: ofpart: call of_node_put() only in ofpart_fail path + - mtd: parsers: ofpart: call of_node_get() for dedicated subpartitions + - cxl/pci: Check memdev driver binding status in cxl_reset_done() + - mtd: rawnand: sunxi: fix sunxi_nfc_hw_ecc_read_extra_oob + - mtd: spinand: winbond: Clarify when to enable the HS bit + - HID: usbhid: fix deadlock in hid_post_reset() + - ext4: fix miss unlock 'sb->s_umount' in extents_kunit_init() + - ext4: call deactivate_super() in extents_kunit_exit() + - ext4: fix the error handling process in extents_kunit_init). + - ext4: fix possible null-ptr-deref in extents_kunit_exit() + - ext4: fix possible null-ptr-deref in mbt_kunit_exit() + - bpf, arm64: Reject out-of-range B.cond targets + - bpf, arm64: Fix off-by-one in check_imm signed range check + - bpf, arm64: Remove redundant bpf_flush_icache() after pack allocator + finalize + - bpf, riscv: Remove redundant bpf_flush_icache() after pack allocator + finalize + - bpf, sockmap: Fix af_unix iter deadlock + - bpf, sockmap: Fix af_unix null-ptr-deref in proto update + - bpf, sockmap: Take state lock for af_unix iter + - bpf: Fix precedence bug in convert_bpf_ld_abs alignment check + - bpf: Fix NULL deref in map_kptr_match_type for scalar regs + - bpf: allow UTF-8 literals in bpf_bprintf_prepare() + - libbpf: Prevent double close and leak of btf objects + - bpf: Validate node_id in arena_alloc_pages() + - bpf, arm32: Reject BPF-to-BPF calls and callbacks in the JIT + - perf trace: Fix IS_ERR() vs NULL check bug + - dt-bindings: pinctrl: marvell,armada3710-xb-pinctrl: add missing items + keyword + - pinctrl: pinctrl-pic32: Fix resource leak + - perf trace: Avoid an ERR_PTR in syscall_stats + - pinctrl: microchip-mssio: Fix missing return in probe + - perf test type profiling: Remote typedef on struct + - pinctrl: cy8c95x0: remove duplicate error message + - pinctrl: cy8c95x0: Unify messages with help of dev_err_probe() + - pinctrl: cy8c95x0: Avoid returning positive values to user space + - perf branch: Avoid incrementing NULL + - perf: tools: cs-etm: Fix print issue for Coresight debug in ETE/TRBE + trace + - pinctrl: pinconf-generic: Fully validate 'pinmux' property + - pinctrl: realtek: Fix function signature for config argument + - pinctrl: abx500: Fix type of 'argument' variable + - pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} + registers + - tools build: Correct link flags for libopenssl + - perf lock: Fix option value type in parse_max_stack + - perf stat: Fix opt->value type for parse_cache_level + - memblock: reserve_mem: fix end caclulation in + reserve_mem_release_by_name() + - perf stat: Fix crash on arm64 + - perf tools: Fix module symbol resolution for non-zero .text sh_addr + - perf test: Fix ratio_to_prev event parsing test + - perf test: Skip perf data type profiling tests for s390 + - perf expr: Return -EINVAL for syntax error in expr__find_ids() + - perf metrics: Make common stalled metrics conditional on having the + event + - ipmi: ssif_bmc: fix missing check for copy_to_user() partial failure + - ipmi: ssif_bmc: fix message desynchronization after truncated response + - ipmi: ssif_bmc: change log level to dbg in irq callback + - perf cgroup: Update metric leader in evlist__expand_cgroup + - pinctrl: sophgo: pinctrl-sg2042: Fix wrong module description + - pinctrl: sophgo: pinctrl-sg2044: Fix wrong module description + - perf maps: Fix fixup_overlap_and_insert that can break sorted by name + order + - perf maps: Fix copy_from that can break sorted by name order + - perf util: Kill die() prototype, dead for a long time + - i3c: master: dw-i3c: Fix missing reset assertion in remove() callback + - i3c: master: dw-i3c: Balance PM runtime usage count on probe failure + - i3c: master: renesas: Fix memory leak in renesas_i3c_i3c_xfers() + - i3c: dw: Fix memory leak in dw_i3c_master_i3c_xfers() + - i3c: master: adi: Fix error propagation for CCCs + - i3c: mipi-i3c-hci: fix IBI payload length calculation for final status + - fs/ntfs3: prevent uninitialized lcn caused by zero len + - backlight: sky81452-backlight: Check return value of + devm_gpiod_get_optional() in sky81452_bl_parse_dt() + - platform/surface: surfacepro3_button: Drop wakeup source on remove + - leds: lgm-sso: Remove duplicate assignments for priv->mmap + - usb: typec: Fix error pointer dereference + - tty: hvc_iucv: fix off-by-one in number of supported devices + - usb: typec: ps883x: Fix Oops at unbind + - platform/x86: panasonic-laptop: Fix OPTD notifier registration and + cleanup + - platform/x86: barco-p50-gpio: normalize return value of gpio_get + - fs/ntfs3: fix missing run load for vcn0 in attr_data_get_block_locked() + - mfd: mc13xxx-core: Fix memory leak in mc13xxx_add_subdevice_pdata() + - nfs/blocklayout: Fix compilation error (`make W=1`) in + bl_write_pagelist() + - sunrpc: Kill RPC_IFDEBUG() + - sunrpc: Fix compilation error (`make W=1`) when dprintk() is no-op + - NFSD: fix nfs4_file access extra count in nfsd4_add_rdaccess_to_wrdeleg + - nfsd: use dynamic allocation for oversized NFSv4.0 replay cache + - RDMA/umem: Use consistent DMA attributes when unmapping entries + - greybus: raw: fix use-after-free on cdev close + - greybus: raw: fix use-after-free if write is called after disconnect + - platform/x86: asus-wmi: adjust screenpad power/brightness handling + - platform/x86: asus-wmi: fix screenpad brightness range + - tty: serial: ip22zilog: Fix section mispatch warning + - fs/ntfs3: terminate the cached volume label after UTF-8 conversion + - platform/x86: hp-wmi: fix ignored return values in fan settings + - platform/x86: hp-wmi: avoid cancel_delayed_work_sync from work handler + - platform/x86: hp-wmi: use mod_delayed_work to reset keep-alive timer + - platform/x86: hp-wmi: fix u8 underflow in gpu_delta calculation + - platform/x86: hp-wmi: add locking for concurrent hwmon access + - platform/x86: dell_rbu: avoid uninit value usage in packet_size_write() + - platform/x86: dell-wmi-sysman: bound enumeration string aggregation + - RDMA/core: Prefer NLA_NUL_STRING + - platform/x86: hp-wmi: fix fan table parsing + - dt-bindings: clock: qcom: Add GCC video axi reset clock for Glymur + - clk: qcom: gcc-glymur: Add video axi clock resets for glymur + - clk: qcom: dispcc-glymur: use RCG2 ops for DPTX1 AUX clock source + - clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source + - clk: renesas: r9a09g057: Fix ordering of module clocks array + - clk: renesas: r9a09g056: Fix ordering of module clocks array + - clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock + - scsi: sg: Fix sysctl sg-big-buff register during sg_init() + - scsi: sg: Resolve soft lockup issue when opening /dev/sgX + - clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from + byte_div_clk_src dividers + - clk: qcom: dispcc-glymur: Fix DSI byte clock rate setting + - clk: qcom: dispcc-kaanapali: Fix DSI byte clock rate setting + - clk: qcom: dispcc-milos: Fix DSI byte clock rate setting + - clk: qcom: dispcc-sm4450: Fix DSI byte clock rate setting + - clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting + - clk: renesas: r9a09g057: Remove entries for WDT{0,2,3} + - scsi: target: core: Fix integer overflow in UNMAP bounds check + - scsi: ufs: rockchip,rk3576-ufshc: dt-bindings: Add new mphy reset item + - dt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs + - clk: qcom: gcc-sc8180x: Add missing GDSCs + - clk: qcom: gcc-sc8180x: Use retention for USB power domains + - clk: qcom: gcc-sc8180x: Use retention for PCIe power domains + - clk: qcom: dispcc-sm8250: Use shared ops on the mdss vsync clk + - clk: qcom: dispcc-sm8250: Enable parents for pixel clocks + - clk: imx: imx6q: Fix device node reference leak in pll6_bypassed() + - clk: imx: imx6q: Fix device node reference leak in + of_assigned_ldb_sels() + - clk: imx8mq: Correct the CSI PHY sels + - um: Fix potential race condition in TLB sync + - x86/um: fix vDSO installation + - clk: qoriq: avoid format string warning + - clk: xgene: Fix mapping leak in xgene_pllclk_init() + - clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc() + - f2fs: avoid reading already updated pages during GC + - printk_ringbuffer: Fix get_data() size sanity check + - clk: qcom: gdsc: Fix error path on registration of multiple pm + subdomains + - lib/hexdump: print_hex_dump_bytes() calls print_hex_dump_debug() + - f2fs: fix data loss caused by incorrect use of nat_entry flag + - f2fs: fix to preserve previous reserve_{blocks,node} value when remount + - scsi: hpsa: Enlarge controller and IRQ name buffers + - drm/amd/display: Fix parameter mismatch in panel self-refresh helper + - clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON + - clk: visconti: pll: initialize clk_init_data to zero + - f2fs: allow empty mount string for Opt_usr|grp|projjquota + - f2fs: protect extension_list reading with sb_lock in f2fs_sbi_show() + - drm/i915/wm: Verify the correct plane DDB entry + - virt: arm-cca-guest: fix error check for RSI_INCOMPLETE + - crypto: eip93 - fix hmac setkey algo selection + - crypto: sa2ul - Fix AEAD fallback algorithm names + - crypto: ccp - copy IV using skcipher ivsize + - sh: Include in dac.h + - erofs: unify lcn as u64 for 32-bit platforms + - tools: hv: Fix cross-compilation + - Drivers: hv: vmbus: fix hyperv_cpuhp_online variable shadowing + - arm64: dts: imx8mp-debix-model-a: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-debix-som-a: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-navqp: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-icore-mx8mp: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-edm-g: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-aristainetos3a-som-v1: Correct PAD settings for + PMIC_nINT + - arm64: dts: imx8mp-nitrogen-som: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-sr-som: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-ultra-mach-sbc: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for + PMIC_nINT + - PCMCIA: Fix garbled log messages for KERN_CONT + - reset: amlogic: t7: Fix null reset ops + - arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT + - arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT + - arm64: dts: marvell: armada-37xx: use 'usb2-phy' in USB3 controller's + phy-names + - pwm: stm32: Fix rounding issue for requests with inverted polarity + - net/sched: act_mirred: fix wrong device for mac_header_xmit check in + tcf_blockcast_redir + - macvlan: fix macvlan_get_size() not reserving space for + IFLA_MACVLAN_BC_CUTOFF + - net/sched: sch_cake: fix NAT destination port not being updated in + cake_update_flowkeys + - nexthop: fix IPv6 route referencing IPv4 nexthop + - net: airoha: Wait for NPU PPE configuration to complete in + airoha_ppe_offload_setup() + - net/sched: taprio: fix use-after-free in advance_sched() on schedule + switch + - net: dsa: remove redundant netdev_lock_ops() from conduit ethtool ops + - net: enetc: correct the command BD ring consumer index + - net: enetc: fix NTMP DMA use-after-free issue + - ksmbd: fix use-after-free in smb2_open during durable reconnect + - tcp: move tp->chrono_type next tp->chrono_stat[] + - tcp: inline tcp_chrono_start() + - tcp: annotate data-races in tcp_get_info_chrono_stats() + - tcp: add data-race annotations around tp->data_segs_out and + tp->total_retrans + - tcp: add data-races annotations around tp->reordering, tp->snd_cwnd + - tcp: annotate data-races around tp->snd_ssthresh + - tcp: annotate data-races around tp->delivered and tp->delivered_ce + - tcp: add data-race annotations for TCP_NLA_SNDQ_SIZE + - tcp: annotate data-races around tp->bytes_sent + - tcp: annotate data-races around tp->bytes_retrans + - tcp: annotate data-races around tp->dsack_dups + - tcp: annotate data-races around tp->reord_seen + - tcp: annotate data-races around tp->srtt_us + - tcp: annotate data-races around tp->timeout_rehash + - tcp: annotate data-races around (tp->write_seq - tp->snd_nxt) + - tcp: annotate data-races around tp->plb_rehash + - ice: fix 'adjust' timer programming for E830 devices + - ice: update PCS latency settings for E825 10G/25Gb modes + - ice: fix double-free of tx_buf skb + - ice: fix PHY config on media change with link-down-on-close + - ice: fix ICE_AQ_LINK_SPEED_M for 200G + - ice: fix race condition in TX timestamp ring cleanup + - ice: fix potential NULL pointer deref in error path of + ice_set_ringparam() + - i40e: don't advertise IFF_SUPP_NOFCS + - iavf: fix wrong VLAN mask for legacy Rx descriptors L2TAG2 + - e1000e: Unroll PTP in probe error handling + - ipv6: fix possible UAF in icmpv6_rcv() + - af_unix: Drop all SCM attributes for SOCKMAP. + - sctp: fix OOB write to userspace in sctp_getsockopt_peer_auth_chunks + - pppoe: drop PFC frames + - net/mlx5: Fix HCA caps leak on notifier init failure + - net: airoha: Fix possible TX queue stall in airoha_qdma_tx_napi_poll() + - netfilter: nft_osf: restrict it to ipv4 + - netfilter: conntrack: remove sprintf usage + - netfilter: xtables: restrict several matches to inet family + - netfilter: nat: use kfree_rcu to release ops + - ipvs: fix MTU check for GSO packets in tunnel mode + - netfilter: nfnetlink_osf: fix out-of-bounds read on option matching + - netfilter: nfnetlink_osf: fix potential NULL dereference in ttl check + - net/sched: sch_dualpi2: drain both C-queue and L-queue in + dualpi2_change() + - arm64: dts: amlogic: meson-axg: Add missing cache information to cpu0 + - arm64: dts: meson-gxl-p230: fix ethernet PHY interrupt number + - vfio/pci: Clean up DMABUFs before disabling function + - pwm: atmel-tcb: Cache clock rates and mark chip as atomic + - ksmbd: destroy tree_conn_ida in ksmbd_session_destroy() + - ksmbd: destroy async_ida in ksmbd_conn_free() + - ksmbd: fix durable fd leak on ClientGUID mismatch in durable v2 open + - ksmbd: scope conn->binding slowpath to bound sessions only + - net: validate skb->napi_id in RX tracepoints + - bnge: fix initial HWRM sequence + - bnge: remove unsupported backing store type + - sctp: fix sockets_allocated imbalance after sk_clone() + - net/rds: zero per-item info buffer before handing it to visitors + - ice: fix timestamp interrupt configuration for E825C + - ice: perform PHY soft reset for E825C ports at initialization + - ice: fix ready bitmap check for non-E822 devices + - ice: fix ice_ptp_read_tx_hwtstamp_status_eth56g + - net_sched: sch_hhf: annotate data-races in hhf_dump_stats() + - net/sched: sch_pie: annotate data-races in pie_dump_stats() + - net/sched: sch_fq_codel: remove data-races from fq_codel_dump_stats() + - net/sched: sch_red: annotate data-races in red_dump_stats() + - net/sched: sch_sfb: annotate data-races in sfb_dump_stats() + - net: airoha: Move ndesc initialization at end of airoha_qdma_init_tx() + - net: airoha: Add missing bits in airoha_qdma_cleanup_tx_queue() + - net: dsa: realtek: rtl8365mb: fix mode mask calculation + - net: airoha: Move ndesc initialization at end of + airoha_qdma_init_rx_queue() + - net: airoha: Rework the code flow in airoha_remove() and in + airoha_probe() error path + - net: airoha: Add size check for TX NAPIs in airoha_qdma_cleanup() + - net: mana: Init link_change_work before potential error paths in probe + - net: mana: Init gf_stats_work before potential error paths in probe + - net: mana: Guard mana_remove against double invocation + - net: mana: Don't overwrite port probe error with add_adev result + - net: mana: Fix EQ leak in mana_remove on NULL port + - vsock/virtio: fix MSG_ZEROCOPY pinned-pages accounting + - virtio_net: sync rss_trailer.max_tx_vq on queue_pairs change via + VQ_PAIRS_SET + - nfp: fix swapped arguments in nfp_encode_basic_qdr() calls + - tcp: send a challenge ACK on SEG.ACK > SND.NXT + - tipc: fix double-free in tipc_buf_append() + - vhost_net: fix sleeping with preempt-disabled in vhost_net_busy_poll() + - nstree: fix func. parameter kernel-doc warnings + - eventpoll: use hlist_is_singular_node() in __ep_remove() + - eventpoll: split __ep_remove() + - eventpoll: kill __ep_remove() + - eventpoll: drop vestigial __ prefix from ep_remove_{file,epi}() + - eventpoll: move epi_fget() up + - fs/adfs: validate nzones in adfs_validate_bblk() + - rtc: abx80x: Disable alarm feature if no interrupt attached + - kbuild: builddeb - avoid recompiles for non-cross-compiles + - tools/power turbostat: Fix AMD RAPL regression on big systems + - fbdev: offb: fix PCI device reference leak on probe failure + - tools/power turbostat: Fix unrecognized option '-P' + - tools/power turbostat: Fix --cpu-set 0 regression on HT systems + - tools/power turbostat: Fix --cpu-set 1 regression on HT systems + - kbuild: Never respect CONFIG_WERROR / W=e to fixdep + - mailbox: mtk-vcp-mailbox: Fix the return value in mtk_vcp_mbox_xlate() + - mailbox: mtk-cmdq: Fix CURR and END addr for task insert case + - mailbox: mailbox-test: free channels on probe error + - sched/psi: fix race between file release and pressure write + - cgroup/rdma: fix integer overflow in rdmacg_try_charge() + - cgroup/cpuset: record DL BW alloc CPU for attach rollback + - mailbox: add sanity check for channel array + - mailbox: mailbox-test: handle channel errors consistently + - mailbox: mailbox-test: don't free the reused channel + - mailbox: mailbox-test: initialize struct earlier + - mailbox: mailbox-test: make data_ready a per-instance variable + - fsnotify: fix inode reference leak in fsnotify_recalc_mask() + - btrfs: fix bytes_may_use leak in move_existing_remap() + - btrfs: fix bytes_may_use leak in do_remap_reloc_trans() + - btrfs: don't clobber errors in add_remap_tree_entries() + - btrfs: fix double-decrement of bytes_may_use in + submit_one_async_extent() + - tracing: branch: Fix inverted check on stat tracer registration + - nvmet-tcp: propagate nvmet_tcp_build_pdu_iovec() errors to its callers + - netfilter: nf_tables: use list_del_rcu for netlink hooks + - rculist: add list_splice_rcu() for private lists + - netfilter: nf_tables: join hook list via splice_list_rcu() in commit + phase + - netfilter: nf_tables: add hook transactions for device deletions + - nvme-pci: fix missed admin queue sq doorbell write + - drm/amdgpu: avoid double drm_exec_fini() in userq validate + - drm/amdgpu/gmc: Fix AMDGPU_GART_PLACEMENT_LOW to not overlap with VRAM + - drm/amd/pm: fix missing fine-grained dpm table flag on aldebaran + - drm/amdgpu: fix AMDGPU_INFO_READ_MMR_REG + - drm/amdgpu/uvd3.1: Don't validate the firmware when already validated + - drm/amdgpu/gfx6: Support harvested SI chips with disabled TCCs (v2) + - drm/amdgpu: Only send RMA CPER when threshold is exceeded + - netfilter: xt_policy: fix strict mode inbound policy matching + - netfilter: nf_conntrack_sip: don't use simple_strtoul + - spi: rzv2h-rspi: Fix silent failure in clock setup error path + - ASoC: amd: acp: Add DMI quirk for Valve Steam Deck OLED + - ASoC: SOF: Intel: add an empty adr_link + - spi: rockchip: Read ISR, not IMR, to detect cs-inactive IRQ + - ASoC: tas2764: Mark die temp register as volatile + - ASoC: tas2770: Fix order of operations for temperature calculation + - drm/sysfb: ofdrm: fix PCI device reference leaks + - drm/color-mgmt: Typo s/R332/RGB332/ + - arm64/scs: Fix potential sign extension issue of advance_loc4 + - spi: spi-mem: Add a packed command operation + - mtd: spinand: Add support for packed read data ODTR commands + - mtd: spinand: winbond: Set the packed page read flag to W35N02/04JW + - mtd: spinand: winbond: Fix ODTR write VCR on W35NxxJW + - ACPICA: Provide #defines for EINJV2 error types + - ACPI: APEI: EINJ: Fix EINJV2 memory error injection + - cdrom, scsi: sr: propagate read-only status to block layer via + set_disk_ro() + - spi: axiado: replace usleep_range() with udelay() in IRQ path + - netdevsim: zero initialize struct iphdr in dummy sk_buff + - net/sched: netem: fix probability gaps in 4-state loss model + - net/sched: netem: fix queue limit check to include reordered packets + - net/sched: netem: only reseed PRNG when seed is explicitly provided + - net/sched: netem: validate slot configuration + - net/sched: netem: fix slot delay calculation overflow + - net/sched: netem: check for negative latency and jitter + - net: airoha: fix BQL imbalance in TX path + - net: airoha: stop net_device TX queue before updating CPU index + - net: airoha: fix typo in function name + - net: airoha: Do not wake all netdev TX queues in + airoha_qdma_wake_netdev_txqs() + - net: airoha: Do not read uninitialized fragment address in + airoha_dev_xmit() + - net/sched: sch_choke: annotate data-races in choke_dump_stats() + - net/sched: sch_fq_pie: annotate data-races in fq_pie_dump_stats() + - vrf: Fix a potential NPD when removing a port from a VRF + - net: usb: rtl8150: fix use-after-free in rtl8150_start_xmit() + - net: usb: rtl8150: free skb on usb_submit_urb() failure in xmit + - spi: amlogic-spisg: initialize completion before requesting IRQ + - NFC: trf7970a: Ignore antenna noise when checking for RF field + - net: phonet: do not BUG_ON() in pn_socket_autobind() on failed bind + - neigh: let neigh_xmit take skb ownership + - tcp: make probe0 timer handle expired user timeout + - netpoll: fix IPv6 local-address corruption + - ALSA: usb-audio: Fix potential leak of pd at parsing UAC3 streams + - sched/fair: Fix wakeup_preempt_fair() vs delayed dequeue + - sched/fair: Clear rel_deadline when initializing forked entities + - net: mctp i2c: check length before marking flow active + - md/raid1,raid10: don't fail devices for invalid IO errors + - md: add fallback to correct bitmap_ops on version mismatch + - md: factor bitmap creation away from sysfs handling + - md/md-bitmap: split bitmap sysfs groups + - md/md-bitmap: add a none backend for bitmap grow + - s390/mm: Fix phys_to_folio() usage in do_secure_storage_access() + - net: phy: dp83869: fix setting CLK_O_SEL field. + - drm/amd/display: properly handle family setting for early GC 11.5.4 + - drm/amdgpu/vcn: set no_user_fence for VCN v2.0 enc/dec rings + - drm/amdgpu/vcn: set no_user_fence for VCN v2.5 enc/dec rings + - drm/amdgpu/vcn: set no_user_fence for VCN v3.0 enc/dec rings + - drm/amdgpu/vcn: set no_user_fence for VCN v4.0 enc ring + - drm/amdgpu/vcn: set no_user_fence for VCN v4.0.3 enc ring + - drm/amdgpu/vcn: set no_user_fence for VCN v4.0.5 enc ring + - drm/amdgpu/vcn: set no_user_fence for VCN v5.0.0 enc ring + - drm/amdgpu/vcn: set no_user_fence for VCN v5.0.1 enc ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v2.0 ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v2.5 ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v3.0 ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v4.0 ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v4.0.3 ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v4.0.5 ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v5.0.0 ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v5.0.1 ring + - drm/amdgpu/jpeg: set no_user_fence for JPEG v5.3.0 ring + - drm/amd/pm: Add fine grained flag to SMU v13.0.6 + - io_uring/napi: cap busy_poll_to 10 msec + - ASoC: cs35l56: Fix illegal writes to OTP_MEM registers + - net: psp: check for device unregister when creating assoc + - net: psp: require admin permission for dev-set and key-rotate + - ASoC: codecs: ab8500: Fix casting of private data + - netfilter: skip recording stale or retransmitted INIT + - sctp: discard stale INIT after handshake completion + - net/sched: sch_cake: annotate data-races in cake_dump_stats() (I) + - net/sched: sch_cake: annotate data-races in cake_dump_stats() (II) + - net/sched: sch_cake: annotate data-races in cake_dump_stats() (III) + - net/sched: sch_cake: annotate data-races in cake_dump_stats() (IV) + - net/sched: sch_cake: annotate data-races in cake_dump_stats() (V) + - netconsole: return count instead of strnlen(buf, count) from store + callbacks + - netconsole: avoid clobbering userdatum value on truncated write + - netconsole: propagate device name truncation in dev_name_store() + - netconsole: restore userdatum value on update_userdata() failure + - ALSA: hda/conexant: Fix missing error check for jack detection + - ALSA: hda: cs35l56: Fix uninitialized value in cs35l56_hda_read_acpi() + - ALSA: hda/tas2781: Fix incorrect bit update for non-book-zero or book 0 + pages >1 + - futex: Prevent lockup in requeue-PI during signal/ timeout wakeup + - drm/amd/display: Allow embedded connectors without DDC + - drm/amd/display: Allow DCE link encoder without AUX registers + - drm/amd/display: Allow constructing DCE6 link encoder without DDC + - drm/amd/display: Allow constructing DCE8 link encoder without DDC + - drm/amd/display: Read EDID from VBIOS embedded panel info + - drm/amd/display: Use EDID from VBIOS embedded panel info + - drm/xe: Use XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET enum instead of magic + number + - drm/xe: Drop registration of guc_submit_wedged_fini from + xe_guc_submit_wedge() + - drm/xe/debugfs: Correct printing of register whitelist ranges + - drm/xe: Fix potential NULL deref in + xe_exec_queue_tlb_inval_last_fence_put_unlocked + - drm/xe: Fix error cleanup in xe_exec_queue_create_ioctl() + - drm/xe/eustall: Fix drm_dev_put called before stream disable in close + - drm/xe/gsc: Fix BO leak on error in query_compatibility_version() + - drm/xe/xelp: Fix Wa_18022495364 + - net: airoha: Do not return err in ndo_stop() callback + - bonding: print churn state via netlink + - bonding: 3ad: implement proper RCU rules for port->aggregator + - page_pool: fix memory-provider leak in page_pool_create_percpu() error + path + - iavf: rename IAVF_VLAN_IS_NEW to IAVF_VLAN_ADDING + - iavf: stop removing VLAN filters from PF on interface down + - iavf: wait for PF confirmation before removing VLAN filters + - iavf: add VIRTCHNL_OP_ADD_VLAN to success completion handler + - ice: fix NULL pointer dereference in ice_reset_all_vfs() + - ice: fix infinite recursion in ice_cfg_tx_topo via ice_init_dev_hw + - ice: fix missing SMA pin initialization in DPLL subsystem + - ice: fix SMA and U.FL pin state changes affecting paired pin + - ice: fix missing dpll notifications for SW pins + - dpll: export __dpll_pin_change_ntf() for use under dpll_lock + - ice: add dpll peer notification for paired SMA and U.FL pins + - net: tls: fix strparser anchor skb leak on offload RX setup failure + - sfc: fix error code in efx_devlink_info_running_versions() + - net/sched: cls_flower: revert unintended changes + - kselftest/arm64: Include for user_gcs definition + - arm64: Reserve an extra page for early kernel mapping + - futex: Drop CLONE_THREAD requirement for private default hash alloc + - PCI: Initialize temporary device in new_id_store() + - workqueue: fix devm_alloc_workqueue() va_list misuse + - net/sched: sch_pie: annotate more data-races in pie_dump_stats() + - sched/fair: Fix wakeup_preempt_fair() for not waking up task + - crypto: af_alg - Cap AEAD AD length to 0x80000000 + - i40e: Cleanup PTP pins on probe failure + - workqueue: Fix wq->cpu_pwq leak in alloc_and_link_pwqs() WQ_UNBOUND path + - net: ena: PHC: Fix potential use-after-free in get_timestamp + - cgroup/cpuset: Reset DL migration state on can_attach() failure + - netfilter: nf_conntrack_sip: get helper before allocating expectation + - audit: fix incorrect inheritable capability in CAPSET records + - net: ena: PHC: Check return code before setting timestamp output + - cgroup/dmem: Return -ENOMEM on failed pool preallocation + - idpf: fix double free and use-after-free in aux device error paths + - cgroup/cpuset: Reserve DL bandwidth only for root-domain moves + - Revert "ACPI: CPPC: Adjust debug messages in amd_set_max_freq_ratio() to + warn" + - netfilter: nft_ct: fix missing expect put in obj eval + - net: atlantic: preserve PCI wake-from-D3 on shutdown when WOL enabled + - audit: enforce AUDIT_LOCKED for AUDIT_TRIM and AUDIT_MAKE_EQUIV + - cgroup/cpuset: Return only actually allocated CPUs during partition + invalidation + - KVM: x86: Swap the dst and src operand for MOVNTDQA + - KVM: Reject wrapped offset in kvm_reset_dirty_gfn() + - KVM: s390: pci: fix GAIT table indexing due to double-scaling pointer + arithmetic + - KVM: x86: Fix Xen hypercall tracepoint argument assignment + - HID: pass the buffer size to hid_report_raw_event + - HID: core: introduce hid_safe_input_report() + - rseq: Revert to historical performance killing behaviour + - rseq: Implement read only ABI enforcement for optimized RSEQ V2 mode + - rseq: Reenable performance optimizations conditionally + - HID: core: Fix size_t specifier in hid_report_raw_event() + - ata: libata-scsi: fix requeue of deferred ATA PASS-THROUGH commands + - media: staging: imx: configure src_mux in csi_start + - Bluetooth: btmtk: accept too short WMT FUNC_CTRL events + - nvme-apple: Reset q->sq_tail during queue init + - smb/client: fix possible infinite loop and oob read in symlink_data() + - drm/loongson: Use managed KMS polling + - drm: Replace old pointer to new idr + - drm/bridge: imx8qxp-pxl2dpi: avoid ERR_PTR with device_node cleanup + - drm/i915/dp: Fix VSC dynamic range signaling for RGB formats + - drm/amd/display: Wrap DCN32 phantom-plane allocation in + DC_RUN_WITH_PREEMPTION_ENABLED + - drm/ttm: Fix ttm_bo_swapout() infinite LRU walk on swapout failure + - platform/x86: intel: Move debugfs register before creating devices + - platform/x86: lenovo-wmi-helpers: Move gamezone enums to wmi-helpers + - platform/x86: lenovo-wmi-helpers: Fix memory leak in + lwmi_dev_evaluate_int() + - platform/x86: lenovo-wmi-other: Balance IDA id allocation and free + - platform/x86: lenovo-wmi-other: Balance component bind and unbind + - platform/x86: lenovo-wmi-other: Zero initialize WMI arguments + - platform/x86: lenovo-wmi-other: Fix tunable_attr_01 struct members + - platform/x86: lenovo-wmi-other: Add Attribute ID helper functions + - platform/x86: lenovo-wmi-other: Limit adding attributes to supported + devices + - accel/rocket: Fix prep_bo ioctl leaking positive return from + dma_resv_wait_timeout() + - ALSA: hda/realtek: Add mute LED quirk for HP Pavilion Laptop 16-ag0xxx + - ALSA: hda/realtek: Add quirk for Samsung Galaxy Book5 360 headphone + - ALSA: usb-audio: Bound MIDI 2.0 endpoint descriptor scans + - ALSA: usb-audio: Bound MIDI endpoint descriptor scans + - ALSA: usb-audio: qcom: Check offload mapping failures + - btrfs: only release the dirty pages io tree after successful writes + - ceph: fix a buffer leak in __ceph_setxattr() + - ceph: fix BUG_ON in __ceph_build_xattrs_blob() due to stale blob size + - ceph: put folios not suitable for writeback + - io-wq: check that the predecessor is hashed in io_wq_remove_pending() + - iommu/amd: Bounds-check devid in __rlookup_amd_iommu() + - x86/kexec: Push kjump return address even for non-kjump kexec + - xfs: fix memory leak on error in xfs_alloc_zone_info() + - virt: sev-guest: Do not use host-controlled page order in cleanup path + - powerpc/warp: Fix error handling in pika_dtm_thread + - netfs: fix error handling in netfs_extract_user_iter() + - nfsd: fix GET_DIR_DELEGATION when VFS leases are disabled + - nfsd: fix file change detection in CB_GETATTR + - nfsd: update mtime/ctime on CLONE in presense of delegated attributes + - nfsd: update mtime/ctime on COPY in presence of delegated attributes + - irqchip/riscv-imsic: Clear interrupt move state during CPU offlining + - irqchip/meson-gpio: Use the correct register in + meson_s4_gpio_irq_set_type() + - irqchip/gic-v5: Move LPI allocation into the LPI domain + - irqchip/gic-v5: Support range allocation for LPIs + - irqchip/gic-v5: Allocate ITS parent LPIs as a range + - libceph: Fix potential out-of-bounds access in osdmap_decode() + - libceph: Fix potential null-ptr-deref in decode_choose_args() + - libceph: Fix potential out-of-bounds access in __ceph_x_decrypt() + - libceph: Fix potential out-of-bounds access in crush_decode() + - libceph: handle rbtree insertion error in decode_choose_args() + - iommu/vt-d: Disable DMAR for Intel Q35 IGFX + - iommu/vt-d: Fix oops due to out of scope access + - iommu/vt-d: Avoid NULL pointer dereference or refcount corruption + - iommu: Fix NULL group->domain dereference in pci_dev_reset_iommu_done() + - iommu: Replace per-group resetting_domain with per-gdev blocked flag + - iommu: Fix WARN_ON in __iommu_group_set_domain_nofail() due to reset + - iommu: Fix pasid attach in pci_dev_reset_iommu_prepare/done() + - iommu: Fix nested pci_dev_reset_iommu_prepare/done() + - iommu: Fix ATS invalidation timeouts during __iommu_remove_group_pasid() + - drm/i915: skip __i915_request_skip() for already signaled requests + - drm/panfrost: Fix wait_bo ioctl leaking positive return from + dma_resv_wait_timeout() + - drm/xe/dma-buf: handle empty bo and UAF races + - drm/xe/dma-buf: fix UAF with retry loop + - drm/ttm: Fix ttm_bo_shrink() infinite LRU walk on backup failure + - drm/ttm: Convert -EAGAIN from dmem_cgroup_try_charge to -ENOSPC + - drm/gma500/oaktrail_hdmi: fix i2c adapter leak on setup + - drm/gma500/oaktrail_lvds: fix hang on init failure + - drm/gma500/oaktrail_lvds: fix i2c adapter leaks on init + - arm_mpam: Fix monitor instance selection when checking for hardware NRDY + - arm_mpam: Pretend that NRDY is always hardware managed + - arm_mpam: Improve check for whether or not NRDY is hardware managed + - arm_mpam: Fix false positive assert failure during mpam_disable() + - arm_mpam: Check whether the config array is allocated before destroying + it + - eventfs: Simplify code using guard()s + - eventfs: Use list_add_tail_rcu() for SRCU-protected children list + - smb: client: Use FullSessionKey for AES-256 encryption key derivation + - spi: sifive: Simplify clock handling with devm_clk_get_enabled() + - spi: sifive: fix controller deregistration + - tracefs: Removed unused 'ret' variable in eventfs_iterate() + - workqueue: Annotate alloc_workqueue_va() with __printf(1, 0) + - selftests/bpf: Remove test_access_variable_array + - netfs: Fix potential uninitialised var in netfs_extract_user_iter() + - Linux 7.0.10 + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45846 + - bareudp: fix NULL pointer dereference in bareudp_fill_metadata_dst() + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45845 + - net/sched: taprio: fix NULL pointer dereference in class dump + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45844 + - netfilter: arp_tables: fix IEEE1394 ARP payload parsing + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-46242 + - eventpoll: fix ep_remove struct eventpoll / struct file UAF + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45843 + - slip: bound decode() reads against the compressed packet length + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45842 + - slip: reject VJ receive packets on instances with no rstate array + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45841 + - netfilter: nfnetlink_osf: fix divide-by-zero in OSF_WSS_MODULO + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45840 + - openvswitch: cap upcall PID array size and pre-size vport replies + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45839 + - bpf: reject negative CO-RE accessor indices in bpf_core_parse_spec() + * Resolute update: v7.0.10 upstream stable release (LP: #2156385) // + CVE-2026-45838 + - bpf: fix end-of-list detection in cgroup_storage_get_next_key() + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) + - Linux 7.0.8 + - HID: pidff: Fix integer overflow in pidff_rescale + - media: uvcvideo: Enable VB2_DMABUF for metadata stream + - drm/msm/hdmi: Fix wrong CTRL1 register used in writing info frames + - media: rzv2h-ivc: Avoid double job scheduling + - media: nxp: imx8-isi: Reduce minimum queued buffers from 2 to 0 + - media: rzv2h-ivc: Write AXIRX_PIXFMT once + - media: rzv2h-ivc: Fix FM_STOP register write + - media: rzv2h-ivc: Fix concurrent buffer list access + - media: mali-c55: Initialize the ISP in enable_streams() + - media: mali-c55: Fix Iridix bypass macros + - media: renesas: vsp1: Fix NULL pointer deref on module unload + - media: renesas: vin: Fix RAW8 (again) + - media: i2c: ov8856: free control handler on error in + ov8856_init_controls() + - media: dt-bindings: rockchip,vdec: Add alternative reg-names order for + RK35{76,88} + - media: dt-bindings: rockchip,vdec: Mark reg-names required for + RK35{76,88} + - media: chips-media: wave5: fix a potential memory leak in + wave5_vdi_init() + - media: chips-media: wave5: add missing spinlock protection for + send_eos_event() + - media: chips-media: wave5: add missing spinlock protection for + handle_dynamic_resolution_change() + - arm64: dts: freescale: imx95-toradex-smarc: fix PMIC_SD2_VSEL label + position + - drm/gpusvm: Allow device pages to be mapped in mixed mappings after + system pages + - drm/gpusvm: Force unmapping on error in drm_gpusvm_get_pages + - spi: bcm63xx: fix controller deregistration + - spi: atmel: fix controller deregistration + - arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux + - regulator: mt6357: fix OF node reference imbalance + - spi: st-ssc4: fix controller deregistration + - regulator: max77650: fix OF node reference imbalance + - media: ti: vpe: Add missing v4l2_device_unregister in vip_remove() + - media: rc: streamzap: Error handling in probe + - media: i2c: imx283: Enter full standby when stopping streaming + - regulator: bq257xx: fix OF node reference imbalance + - regulator: rk808: fix OF node reference imbalance + - media: videobuf2: Set vma_flags in vb2_dma_sg_mmap + - media: mali-c55: Fully reset the ISP configuration + - media: intel/ipu6: fix error pointer dereference + - media: i2c: imx283: Fix hang when going from large to small resolution + - regulator: act8945a: fix OF node reference imbalance + - regulator: s2dos05: fix OF node reference imbalance + - regulator: bd9571mwv: fix OF node reference imbalance + - spi: lantiq-ssc: fix controller deregistration + - spi: meson-spicc: fix controller deregistration + - spi: qup: fix controller deregistration + - arm64: dts: ti: k3-am69-aquila-clover: Fix DP regulator enable GPIO + - spi: at91-usart: fix controller deregistration + - media: ipu-bridge: Add upside-down sensor DMI quirk for Dell XPS 13 9340 + and XPS 14 9440 + - spi: amlogic-spisg: fix controller deregistration + - spi: aspeed-smc: fix controller deregistration + - drm/colorop: Preserve bypass value in duplicate_state() + - drm/atomic: Add affected colorops with affected planes + - platform/x86: hp-wmi: Ignore backlight and FnLock events + - vsock/virtio: fix MSG_PEEK ignoring skb offset when calculating bytes to + copy + - arm64: dts: broadcom: bcm2712-d-rpi-5-b: add fixes for + pinctrl/pinctrl_aon + - arm64: dts: broadcom: bcm2712-d-rpi-5-b: update uart10 interrupt + - media: pci: zoran: fix potential memory leak in zoran_probe() + - media: dib8000: avoid division by 0 in dib8000_set_dds() + - media: i2c: imx412: Assert reset GPIO during probe + - media: staging: imx: request mbus_config in csi_start + - media: i2c: ov08d10: fix image vertical start setting + - media: i2c: ov08d10: fix runtime PM handling in probe + - media: omap3isp: drop the use count of v4l2 pipeline + - media: iris: fix QCOM_MDT_LOADER dependency + - media: qcom: camss: Fix csid clock configuration for sa8775p + - media: qcom: camss: Fix csid IRQ offset for sa8775p + - media: qcom: iris: increase H265D_MAX_SLICE to fix H.265 decoding on + SC7280 + - media: venus: fix QCOM_MDT_LOADER dependency + - media: iris: Fix dma_free_attrs() size in iris_hfi_queues_init() + - media: iris: switch to hardware mode after firmware boot + - media: qcom: camss: Add missing clocks for VFE lite on sa8775p + - spi: mxs: fix controller deregistration + - spi: mt65xx: fix controller deregistration + - spi: dln2: fix controller deregistration + - spi: s3c64xx: fix controller deregistration + - spi: fsl-espi: fix controller deregistration + - spi: omap2-mcspi: fix controller deregistration + - spi: pic32: fix controller deregistration + - spi: ep93xx: fix controller deregistration + - spi: mtk-nor: fix controller deregistration + - spi: pl022: fix controller deregistration + - spi: sh-hspi: fix controller deregistration + - spi: bcmbca-hsspi: fix controller deregistration + - spi: coldfire-qspi: fix controller deregistration + - spi: npcm-pspi: fix controller deregistration + - spi: cavium-thunderx: fix controller deregistration + - spi: pic32-sqi: fix controller deregistration + - spi: sprd: fix controller deregistration + - spi: sh-msiof: fix controller deregistration + - spi: slave-mt27xx: fix controller deregistration + - spi: img-spfi: fix controller deregistration + - spi: mpfs: fix controller deregistration + - spi: octeon: fix controller deregistration + - spi: imx: fix runtime pm leak on probe deferral + - spi: mxic: fix controller deregistration + - spi: orion: fix controller deregistration + - spi: orion: fix runtime pm leak on unbind + - spi: orion: fix clock imbalance on registration failure + - spi: cadence: fix controller deregistration + - spi: cadence-quadspi: fix controller deregistration + - spi: cadence: fix unclocked access on unbind + - spi: cadence: fix clock imbalance on probe failure + - spi: cadence-quadspi: fix runtime pm disable imbalance on probe failure + - spi: cadence-quadspi: fix clock imbalance on probe failure + - spi: cadence-quadspi: fix runtime pm and clock imbalance on unbind + - drm/colorop: Fix blob property reference tracking in state lifecycle + - drm/imx: parallel-display: Prefer bus format set via legacy "interface- + pix-fmt" DT property + - drm/msm: always recover the gpu + - drm/v3d: Reject empty multisync extension to prevent infinite loop + - drm/i915/psr: Init variable to avoid early exit from et alignment loop + - drm/amd/display: fix math_mod() using arg1 instead of arg2 + - drm/amd: Add missing firmware declaration for PSP v15.0.0 + - drm/amdgpu: Use NBIF offset for register RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 + . + - drm/amdgpu: Use SMUIO 15.0.0 offsets for TSC upper and lower count. + - drm/amdgpu: gate VM CPU HDP flush on reset lock + - drm/amd/pm: fix incorrect FeatureCtrlMask setting on smu v14.0.x + - drm/amdkfd: Add upper bound check for num_of_nodes + - drm/amdgpu/vce: Prevent partial address patches + - drm/amd/display: Change dither policy for 10 bpc output back to + dithering + - drm/appletbdrm: Use kvzalloc for big allocations + - drm/amdgpu: Avoid reset in AMDGPU unload path for APUs with GFX V11 and + higher. + - drm/udl: Increase GET_URB_TIMEOUT + - drm/xe/bo: Fix bo leak on GGTT flag validation in xe_bo_init_locked() + - drm/xe/bo: Fix bo leak on unaligned size validation in + xe_bo_init_locked() + - drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise + - drm/radeon: add missing revision check for CI + - drm/amdgpu: zero-initialize GART table on allocation + - drm/exynos: remove bridge when component_add fails + - drm/amdgpu/userq: fix access to stale wptr mapping + - drm/panel: himax-hx83102: restore MODE_LPM after sending disable cmds + - drm/amdgpu/gfx9: drop unnecessary 64-bit fence flag check in KIQ + - drm/bridge: tda998x: Use __be32 for audio port OF property pointer + - drm/sti: remove bridge when sti_hda component_add fails + - drm/panel: boe-tv101wum-nl6: restore MODE_LPM after sending disable cmds + - drm/amdkfd: Make all TLB-flushes heavy-weight + - drm/amdgpu/pm: add missing revision check for CI + - drm/amdgpu/pm: align Hawaii mclk workaround with radeon + - arm64: dts: qcom: kodiak: Fix PCIe1 PHY ref clock voting + - arm64: dts: qcom: lemans: Correct QUP interrupt numbers + - arm64: dts: ti: k3-am62a7-sk: Fix pin name in comment from M19 to N22 + - arm64: dts: ti: k3-am69-aquila-dev: Fix DP regulator enable GPIO + - batman-adv: tp_meter: fix tp_num leak on kmalloc failure + - sched_ext: Use HK_TYPE_DOMAIN_BOOT to detect isolcpus= domain isolation + - usb: typec: tcpm: reset internal port states on soft reset AMS + - io_uring/zcrx: use guards for locking + - io_uring/zcrx: warn on freelist violations + - kho: fix error handling in kho_add_subtree() + - EDAC/versalnet: Refactor memory controller initialization and cleanup + - spi: uniphier: Simplify clock handling with devm_clk_get_enabled() + - spi: uniphier: fix controller deregistration + - cgroup: Increment nr_dying_subsys_* from rmdir context + - sched_ext: Skip tasks with stale task_rq in bypass_lb_cpu() + - perf build: fix "argument list too long" in second location + - mm/vma: do not try to unmap a VMA if mmap_prepare() invoked from mmap() + - vsock/virtio: fix length and offset in tap skb for split packets + - drm/amdgpu/vcn3: Avoid overflow on msg bound check + - drm/amdgpu/vcn4: Avoid overflow on msg bound check + - Linux 7.0.9 + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46214 + - vsock/virtio: fix accept queue count leak on transport mismatch + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46207 + - vsock/virtio: fix empty payload in tap skb for non-linear buffers + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46234 + - vsock: fix buffer size clamping order + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46223 + - cgroup: Defer css percpu_ref kill on rmdir until cgroup is depopulated + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46221 + - EDAC/versalnet: Fix device name memory leak + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46231 + - batman-adv: bla: put backbone reference on failed claim hash insert + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46233 + - batman-adv: bla: only purge non-released claims + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46212 + - batman-adv: bla: prevent use-after-free when deleting claims + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46238 + - batman-adv: stop caching unowned originator pointers in BAT IV + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46208 + - batman-adv: stop tp_meter sessions during mesh teardown + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46206 + - batman-adv: reject new tp_meter sessions during teardown + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46198 + - batman-adv: fix integer overflow on buff_pos + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46227 + - sctp: revalidate list cursor after sctp_sendmsg_to_asoc() in + SCTP_SENDALL + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46220 + - drm/amdgpu/sdma4: replace BUG_ON with WARN_ON in fence emission + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46215 + - drm: Set old handle to NULL before prime swap in change_handle + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46201 + - drm/xe: Fix dma-buf attachment leak in xe_gem_prime_import() + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46224 + - drm/xe: Fix bo leak in xe_dma_buf_init_obj() on allocation failure + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46197 + - drm/amdkfd: validate SVM ioctl nattr against buffer size + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46209 + - drm/gem: Fix inconsistent plane dimension calculation in + drm_gem_fb_init_with_funcs() + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46230 + - drm/amdgpu/vcn3: Prevent OOB reads when parsing dec msg + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46199 + - drm/amdgpu/vcn4: Prevent OOB reads when parsing dec msg + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46204 + - drm/amdgpu/vcn4: Prevent OOB reads when parsing IB + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46218 + - drm/amdgpu: Add bounds checking to ib_{get,set}_value + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46229 + - drm/amdkfd: Clear VRAM on allocation to prevent stale data exposure + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46211 + - drm/msm/gem: fix error handling in msm_ioctl_gem_info_get_metadata() + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46203 + - spi: cadence-quadspi: fix unclocked access on unbind + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46219 + - spi: mpc52xx: fix use-after-free on unbind + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46200 + - spi: mpc52xx: fix controller deregistration + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46241 + - spi: mpc52xx: fix use-after-free on registration failure + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46225 + - spi: rspi: fix controller deregistration + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46226 + - spi: fsl: fix controller deregistration + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46228 + - spi: ch341: fix devres lifetime + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46216 + - drm/xe/hdcp: Add NULL check for media_gt in + intel_hdcp_gsc_check_status() + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46210 + - media: iris: fix use-after-free of fmt_src during MBPF check + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46240 + - media: iris: Fix use-after-free in iris_release_internal_buffers() + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46235 + - media: saa7164: add ioremap return checks and cleanups + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46222 + - media: rockchip: rkcif: Add missing MUST_CONNECT flag to pads + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46239 + - media: i2c: ov5647: Fix runtime PM refcount leak in s_ctrl + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46236 + - media: rc: xbox_remote: heed DMA restrictions + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46205 + - staging: media: atomisp: Disallow all private IOCTLs + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46202 + - HID: appletb-kbd: run inactivity autodim from workqueues + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46213 + - HID: appletb-kbd: fix UAF in inactivity-timer cleanup path + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46232 + - HID: playstation: Clamp num_touch_reports + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) + - ACPI: arm64: cpuidle: Tolerate platforms with no deep PSCI idle states + - ACPI: scan: Use acpi_dev_put() in object add error paths + - ACPI: video: Add backlight=native quirk for Dell OptiPlex 7770 AIO + - ACPI: CPPC: Fix related_cpus inconsistency during CPU hotplug + - ACPI: video: force native backlight on HP OMEN 16 (8A44) + - iommufd: Fix a race with concurrent allocation and unmap + - wifi: mt76: mt7925: fix incorrect TLV length in CLC command + - spi: rockchip: fix controller deregistration + - ksmbd: rewrite stop_sessions() with restartable iteration + - flow_dissector: do not dissect PPPoE PFC frames + - smb: client/smbdirect: fix MR registration for coalesced SG lists + - wifi: mt76: mt7925: fix AMPDU state handling in mt7925_tx_check_aggr + - wifi: mt76: mt7925: fix incorrect length field in txpower command + - wifi: mt76: mt7921: fix ROC abort flow interruption in mt7921_roc_work + - wifi: ath5k: do not access array OOB + - ALSA: usb-audio: midi2: Restart output URBs on resume + - ALSA: usb-audio: Fix UAC3 cluster descriptor size check + - usb: dwc3: Move GUID programming after PHY initialization + - USB: omap_udc: DMA: Don't enable burst 4 mode + - USB: serial: option: add Telit Cinterion LE910Cx compositions + - usb: typec: tcpm: fix debug accessory mode detection for sink ports + - ALSA: hda: cs35l56: Propagate ASP TX source control errors + - ALSA: hda/realtek: Fix speaker silence after S3 resume on Xiaomi Mi + Laptop Pro 15 + - ALSA: firewire-tascam: Do not drop unread control events + - ALSA: core: Serialize deferred fasync state checks + - ALSA: seq: Fix UMP group 16 filtering + - powerpc/kdump: fix KASAN sanitization flag for core_$(BITS).o + - x86/efi: Restore IRQ state in EFI page fault handler + - xfrm: provide message size for XFRM_MSG_MAPPING + - selinux: fix avdcache auditing + - selinux: don't reserve xattr slot when we won't fill it + - selinux: shrink critical section in sel_write_load() + - selinux: prune /sys/fs/selinux/checkreqprot + - selinux: prune /sys/fs/selinux/disable + - selinux: prune /sys/fs/selinux/user + - selinux: allow multiple opens of /sys/fs/selinux/policy + - io_uring/kbuf: support min length left for incremental buffers + - io_uring/tw: serialize ctx->retry_llist with ->uring_lock + - LoongArch: KVM: Fix missing EMULATE_FAIL in kvm_emu_mmio_read() + - rust: drm: gem: clean up GEM state in init failure case + - rust: allow `clippy::collapsible_match` globally + - rust: allow `clippy::collapsible_if` globally + - rust: pin-init: internal: move alignment check to `make_field_check` + - spi: syncuacer: fix controller deregistration + - spi: sun4i: fix controller deregistration + - spi: zynq-qspi: fix controller deregistration + - spi: ti-qspi: fix controller deregistration + - spi: sun6i: fix controller deregistration + - spi: tegra114: fix controller deregistration + - spi: zynqmp-gqspi: fix controller deregistration + - spi: tegra20-sflash: fix controller deregistration + - spi: s3c64xx: fix NULL-deref on driver unbind + - staging: rtl8723bs: os_dep: avoid NULL pointer dereference in + rtw_cbuf_alloc + - staging: vme_user: fix root device leak on init failure + - KVM: arm64: Fix kvm_vcpu_initialized() macro parameter + - arm64: signal: Preserve POR_EL0 if poe_context is missing + - mm/hugetlb_cma: round up per_node before logging it + - LoongArch: Fix SYM_SIGFUNC_START definition for 32BIT + - LoongArch: KVM: Compile switch.S directly into the kernel + - mptcp: pm: ADD_ADDR rtx: skip inactive subflows + - perf/x86/intel: Improve validation and configuration of ACR masks + - selftests/rseq: Don't run tests with runner scripts outside of the + scripts + - rseq: Set rseq::cpu_id_start to 0 on unregistration + - rseq: Protect rseq_reset() against interrupts + - rseq: Don't advertise time slice extensions if disabled + - selftests/rseq: Make registration flexible for legacy and optimized mode + - selftests/rseq: Skip tests if time slice extensions are not available + - selftests/rseq: Validate legacy behavior + - selftests/rseq: Expand for optimized RSEQ ABI v2 + - pseries/papr-hvpipe: Fix race with interrupt handler + - pseries/papr-hvpipe: Fix & simplify error handling in papr_hvpipe_init() + - pseries/papr-hvpipe: Fix the usage of copy_to_user() + - net: libwx: use request_irq for VF misc interrupt + - netpoll: pass buffer size to egress_dev() to avoid MAC truncation + - ovl: fix verity lazy-load guard broken by fsverity_active() semantic + change + - parisc: Fix IRQ leak in LASI driver + - x86/efi: Fix graceful fault handling after FPU softirq changes + - hwmon: (ltc2992) Clamp threshold writes to hardware range + - hwmon: (ltc2992) Fix u32 overflow in power read path + - clk: rk808: fix OF node reference imbalance + - hwmon: (corsair-psu) Close HID device on probe errors + - af_unix: Reject SIOCATMARK on non-stream sockets + - arm64/fpsimd: ptrace: zero target's fpsimd_state, not the tracer's + - pmdomain: mediatek: fix use-after-free in + scpsys_get_bus_protection_legacy() + - block: fix zone write plug removal + - block: only read from sqe on initial invocation of blkdev_uring_cmd() + - cifs: abort open_cached_dir if we don't request leases + - cifs: change_conf needs to be called for session setup + - extcon: ptn5150: handle pending IRQ events during system resume + - gpio: of: clear OF_POPULATED on hog nodes in remove path + - hv: Select CONFIG_SYSFB only for CONFIG_HYPERV_VMBUS + - hv_sock: fix ARM64 support + - hv_sock: Report EOF instead of -EIO for FIN + - hv_sock: Return -EIO for malformed/short packets + - spi: microchip-core-qspi: fix controller deregistration + - spi: microchip-core-spi: fix controller deregistration + - tracefs: Fix default permissions not being applied on initial mount + - udf: reject descriptors with oversized CRC length + - x86/boot/e820: Re-enable BIOS fallback if e820 table is empty + - thermal: core: Free thermal zone ID later during removal + - thermal/drivers/sprd: Fix temperature clamping in + sprd_thm_temp_to_rawdata + - thermal/drivers/sprd: Fix raw temperature clamping in + sprd_thm_rawdata_to_temp + - spi: topcliff-pch: fix controller deregistration + - spi: topcliff-pch: fix use-after-free on unbind + - tracing/fprobe: Avoid kcalloc() in rcu_read_lock section + - tracing/fprobe: Remove fprobe from hash in failure path + - tracing/fprobe: Unregister fprobe even if memory allocation fails + - tracing/probes: Limit size of event probe to 3K + - tracing/fprobe: Check the same type fprobe on table as the unregistered + one + - clk: imx: imx8-acm: fix flags for acm clocks + - clk: microchip: mpfs-ccc: fix out of bounds access during output + registration + - cpuidle: powerpc: avoid double clear when breaking snooze + - ASoC: amd: yc: Add HP OMEN Gaming Laptop 16-ap0xxx product line in quirk + table + - ASoC: ES8389: convert to devm_clk_get_optional() to get clock + - ASoC: fsl_easrc: fix comment typo + - ASoC: Intel: bytcr_wm5102: Fix MCLK leak on platform_clock_control error + - ASoC: qcom: q6apm-dai: reset queue ptr on trigger stop + - ASoC: qcom: q6apm: remove child devices when apm is removed + - btrfs: do not mark inode incompressible after inline attempt fails + - dm: don't report warning when doing deferred remove + - dm: fix a buffer overflow in ioctl processing + - dm-verity-fec: correctly reject too-small FEC devices + - dm-verity-fec: correctly reject too-small hash devices + - dm-verity-fec: fix corrected block count stat + - dm-verity-fec: fix the size of dm_verity_fec_io::erasures + - isofs: validate Rock Ridge CE continuation extent against volume size + - iommufd: Fix return value of iommufd_fault_fops_write() + - iommu/vt-d: Block PASID attachment to nested domain with dirty tracking + - iommu/arm-smmu-v3: Add a missing dma_wmb() for hitless STE update + - lib/crc: tests: Make crc_kunit test only the enabled CRC variants + - lib/scatterlist: fix temp buffer in extract_user_to_sg() + - nvme-apple: drop invalid put of admin queue reference count + - nvmet: avoid recursive nvmet-wq flush in nvmet_ctrl_free + - pmdomain: core: Fix detach procedure for virtual devices in genpd + - psp: strip variable-length PSP header in psp_dev_rcv() + - s390/debug: Reject zero-length input in debug_input_flush_fn() + - s390/debug: Reject zero-length input before trimming a newline + - KVM: x86: Do IRR scan in __kvm_apic_update_irr even if PIR is empty + - mm/damon/lru_sort: detect and use fresh enabled and kdamond_pid values + - mm/damon/reclaim: detect and use fresh enabled and kdamond_pid values + - mm/damon/stat: detect and use fresh enabled value + - PCI: Update saved_config_space upon resource assignment + - PCI/AER: Clear only error bits in PCIe Device Status + - PCI/AER: Stop ruling out unbound devices as error source + - PCI/ASPM: Fix pci_clear_and_set_config_dword() usage + - power: supply: max17042: avoid overflow when determining health + - perf/x86/intel: Always reprogram ACR events to prevent stale masks + - perf/x86/intel: Disable PMI for self-reloaded ACR events + - perf/x86/intel: Enable auto counter reload for DMR + - RDMA/ionic: bound node_desc sysfs read with %.64s + - RDMA/ionic: Fix typo in format string + - remoteproc: imx_rproc: Fix NULL vs IS_ERR() bug in imx_rproc_addr_init() + - remoteproc: k3: Fix NULL vs IS_ERR() bug in k3_reserved_mem_init() + - sched_ext: idle: Recheck prev_cpu after narrowing allowed mask + - sched_ext: Use dsq->first_task instead of list_empty() in + dispatch_enqueue() FIFO-tail + - selftests: mptcp: check output: catch cmd errors + - selftests: mptcp: pm: restrict 'unknown' check to pm_nl_ctl + - mptcp: fastclose msk when linger time is 0 + - mptcp: use MPJoinSynAckHMacFailure for SynAck HMAC failure + - mptcp: use MPTCP_RST_EMPTCP for ACK HMAC validation failure + - mptcp: sockopt: set timestamp flags on subflow socket, not msk + - mptcp: sockopt: increase seq in mptcp_setsockopt_all_sf + - mptcp: fix rx timestamp corruption on fastopen + - mptcp: pm: prio: skip closed subflows + - mptcp: pm: kernel: reset fullmesh counter after flush + - mptcp: pm: kernel: correctly retransmit ADD_ADDR ID 0 + - mptcp: pm: ADD_ADDR rtx: resched blocked ADD_ADDR quicker + - mptcp: pm: ADD_ADDR rtx: return early if no retrans + - f2fs: add READ_ONCE() for i_blocks in f2fs_update_inode() + - f2fs: fix false alarm of lockdep on cp_global_sem lock + - f2fs: fix fiemap boundary handling when read extent cache is incomplete + - f2fs: fix fsck inconsistency caused by incorrect nat_entry flag usage + - f2fs: fix incorrect file address mapping when inline inode is unwritten + - f2fs: fix incorrect multidevice info in trace_f2fs_map_blocks() + - f2fs: fix uninitialized kobject put in f2fs_init_sysfs() + - f2fs: refactor f2fs_move_node_folio function + - f2fs: fix inline data not being written to disk in writeback path + - KVM: arm64: Wake-up from WFI when iqrchip is in userspace + - KVM: arm64: vgic: Fix IIDR revision field extracted from wrong value + - KVM: arm64: Fix initialisation order in __pkvm_init_finalise() + - KVM: arm64: Fix FEAT_SPE_FnE to use PMSIDR_EL1.FnE, not PMSVer + - KVM: arm64: Fix FEAT_Debugv8p9 to check DebugVer, not PMUVer + - LoongArch: KVM: Cap KVM_CAP_NR_VCPUS by KVM_CAP_MAX_VCPUS + - LoongArch: KVM: Fix "unreliable stack" for kvm_exc_entry + - LoongArch: KVM: Fix HW timer interrupt lost when inject interrupt by + software + - LoongArch: KVM: Move unconditional delay into timer clear scenery + - LoongArch: KVM: Use kvm_set_pte() in kvm_flush_pte() + - LoongArch: Use per-root-bridge PCIH flag to skip mem resource fixup + - mmc: core: Adjust MDT beyond 2025 + - mmc: core: Add quirk for incorrect manufacturing date + - mmc: core: Optimize time for secure erase/trim for some Kingston eMMCs + - crypto: qat - fix indentation of macros in qat_hal.c + - crypto: qat - fix firmware loading failure for GEN6 devices + - hfsplus: fix held lock freed on hfsplus_fill_super() + - 8021q: use RCU for egress QoS mappings + - printk: add print_hex_dump_devel() + - crypto: caam - guard HMAC key hex dumps in hash_digest_key + - net: stmmac: rename STMMAC_GET_ENTRY() -> STMMAC_NEXT_ENTRY() + - rust: pin-init: fix incorrect accessor reference lifetime + - Linux 7.0.7 + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-43490 + - ksmbd: validate inherited ACE SID length + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46174 + - x86/CPU/AMD: Prevent improper isolation of shared resources in Zen2's op + cache + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46110 + - net: stmmac: Prevent NULL deref when RX memory exhausted + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46153 + - 8021q: delete cleared egress QoS mappings + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46169 + - hfsplus: fix uninit-value by validating catalog record size + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46188 + - octeon_ep_vf: add NULL check for napi_build_skb() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-45837 + - bpf: Fix use-after-free in arena_vm_close on fork + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46156 + - LoongArch: Fix potential ADE in loongson_gpu_fixup_dma_hang() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46147 + - KVM: arm64: Fix pin leak and publication ordering in __pkvm_init_vcpu() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46175 + - f2fs: fix fsck inconsistency caused by FGGC of node block + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46194 + - f2fs: fix node_cnt race between extent node destroy and writeback + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46170 + - mptcp: pm: ADD_ADDR rtx: free sk if last + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46158 + - mptcp: pm: ADD_ADDR rtx: always decrease sk refcount + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46168 + - mptcp: fix scheduling with atomic in timestamp sockopt + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46189 + - RDMA/vmw_pvrdma: Fix double free on pvrdma_alloc_ucontext() error path + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46133 + - RDMA/rxe: Reject unknown opcodes before ICRC processing + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46114 + - RDMA/rxe: Reject non-8-byte ATOMIC_WRITE payloads + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46127 + - RDMA/ocrdma: Don't NULL deref uctx on errors in ocrdma_copy_pd_uresp() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46176 + - RDMA/mlx5: Fix error path fall-through in mlx5_ib_dev_res_srq_init() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46178 + - RDMA/mlx4: Fix resource leak on error in mlx4_ib_create_srq() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46181 + - RDMA/mlx4: Fix mis-use of RCU in mlx4_srq_event() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46145 + - RDMA/mana: Validate rx_hash_key_len + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46117 + - RDMA/mana: Remove user triggerable WARN_ON() in mana_ib_create_qp_rss() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46126 + - RDMA/mana: Fix mana_destroy_wq_obj() cleanup in mana_ib_create_qp_rss() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46144 + - RDMA/mana: Fix error unwind in mana_ib_create_qp_rss() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46141 + - powerpc/xive: fix kmemleak caused by incorrect chip_data lookup + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46183 + - mm/damon/sysfs-schemes: protect path kfree() with damon_sysfs_lock + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46121 + - mm/damon/sysfs-schemes: protect memcg_path kfree() with damon_sysfs_lock + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46131 + - KVM: x86: check for nEPT/nNPT in slow flush hypercalls + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46139 + - smb: client: use kzalloc to zero-initialize security descriptor buffer + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46105 + - scsi: mpt3sas: Limit NVMe request size to 2 MiB + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46171 + - riscv: kvm: fix vector context allocation leak + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46112 + - RDMA/hns: Fix unlocked call to hns_roce_qp_remove() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46165 + - openvswitch: vport: fix self-deadlock on release of tunnel ports + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46161 + - md/raid10: fix divide-by-zero in setup_geo() with zero far_copies + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-43492 + - lib/crypto: mpi: Fix integer underflow in mpi_read_raw_from_sgl() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46124 + - isofs: validate block number from NFS file handle in isofs_export_iget + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46130 + - dm-verity-fec: fix reading parity bytes split across blocks (take 3) + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46106 + - eventfs: Hold eventfs_mutex and SRCU when remount walks events + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46107 + - dm-thin: fix metadata refcount underflow + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46160 + - btrfs: fix missing last_unlink_trans update when removing a directory + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46164 + - btrfs: fix double free in create_space_info_sub_group() error path + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46129 + - btrfs: fix double free in create_space_info() error path + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46159 + - btrfs: fix btrfs_ioctl_space_info() slot_count TOCTOU which can lead to + info-leak + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46143 + - ASoC: qcom: q6apm-lpass-dai: Fix multiple graph opens + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46148 + - spi: microchip-core-qspi: control built-in cs manually + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46192 + - spi: microchip-core-qspi: don't attempt to transmit during emulated + read-only dual/quad operations + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46162 + - ice: fix double free in ice_sf_eth_activate() error path + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46273 + - ibmveth: Disable GSO for packets with small MSS + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46191 + - fbcon: Avoid OOB font access if console rotation fails + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46134 + - platform/chrome: cros_ec_typec: Init mutex in Thunderbolt registration + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-43495 + - net: wwan: t7xx: validate port_count against message length in + t7xx_port_enum_msg_handler + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-43502 + - net/rds: handle zerocopy send cleanup before the message is queued + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46120 + - ip6_gre: Use cached t->net in ip6erspan_changelink(). + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46142 + - net: libwx: fix VF illegal register access + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46118 + - pseries/papr-hvpipe: Fix null ptr deref in + papr_hvpipe_dev_create_handle() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46182 + - pseries/papr-hvpipe: Prevent kernel stack memory leak to userspace + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46184 + - sound: ua101: fix division by zero at probe + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-43498 + - accel/ivpu: Disallow re-exporting imported GEM objects + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46132 + - net: rtnetlink: zero ifla_vf_broadcast to avoid stack infoleak in + rtnl_fill_vfinfo + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46190 + - mtd: spi-nor: debugfs: fix out-of-bounds read in spi_nor_params_show() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46150 + - fanotify: fix false positive on permission events + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-45836 + - Bluetooth: L2CAP: Fix null-ptr-deref in l2cap_sock_get_sndtimeo_cb() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-45834 + - Bluetooth: L2CAP: Fix null-ptr-deref in l2cap_sock_state_change_cb() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-45835 + - Bluetooth: L2CAP: Fix null-ptr-deref in l2cap_sock_new_connection_cb() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46138 + - Bluetooth: hci_event: Fix OOB read and infinite loop in + hci_le_create_big_complete_evt + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46111 + - Bluetooth: hci_conn: fix potential UAF in create_big_sync + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46140 + - Bluetooth: btmtk: validate WMT event SKB length before struct access + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46186 + - Bluetooth: virtio_bt: validate rx pkt_type header length + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46123 + - Bluetooth: virtio_bt: clamp rx length before skb_put + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46104 + - selinux: use sk blob accessor in socket permission helpers + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46193 + - xfrm: ah: account for ESN high bits in async callbacks + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46172 + - ipv6: xfrm6: release dst on error in xfrm6_rcv_encap() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46116 + - xfrm: defensively unhash xfrm_state lists in __xfrm_state_delete + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46154 + - sched_ext: Read scx_root under scx_cgroup_ops_rwsem in cgroup setters + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46157 + - ALSA: pcm: oss: Fix data race at accessing runtime.oss.trigger + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46109 + - usb: ulpi: fix memory leak on ulpi_register() error paths + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46146 + - ALSA: usb-audio: Avoid potential endless loop in convert_chmap_v3() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46167 + - usb: usblp: fix uninitialized heap leak via LPGETSTATUS ioctl + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46151 + - usb: usblp: fix heap leak in IEEE 1284 device ID via short response + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46180 + - wifi: brcmfmac: Fix potential use-after-free issue when stopping + watchdog task + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46122 + - wifi: b43: enforce bounds check on firmware key index in b43_rx() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46125 + - wifi: mac80211: remove station if connection prep fails + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46166 + - wifi: mac80211: use safe list iteration in radar detect work + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46187 + - wifi: rsi: fix kthread lifetime race between self-exit and external-stop + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46152 + - wifi: mac80211: drop stray 'static' from fast-RX rx_result + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46163 + - wifi: b43legacy: enforce bounds check on firmware key index in RX path + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46136 + - wifi: mt76: mt7921: fix a potential clc buffer length underflow + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46173 + - exit: prevent preemption of oopsing TASK_DEAD task + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-43496 + - net/sched: sch_red: Replace direct dequeue call with peek and + qdisc_dequeue_peeked + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46113 + - KVM: x86: Fix shadow paging use-after-free due to unexpected GFN + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46179 + - ASoC: SOF: Don't allow pointer operations on unconfigured streams + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46196 + - tracepoint: balance regfunc() on func_add() failure in + tracepoint_add_func() + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-43497 + - fbdev: udlfb: add vm_ops to dlfb_ops_mmap to prevent use-after-free + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46108 + - ipmi:si: Return state to normal if message allocation fails + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46128 + - ipmi: Check event message buffer response for bad data + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46177 + - ipmi: Add limits to event and receive message requests + * Resolute update: v7.0.7 upstream stable release (LP: #2155988) // + CVE-2026-46149 + - scsi: target: configfs: Bound snprintf() return in + tg_pt_gp_members_show() + * Ubuntu 26.04 linux kernel has non-functional nova-core GPU driver enabled, + conflicting with nouveau (LP: #2150845) + - [Config] Disable NOVA_CORE + * CVE-2026-46244 + - netfilter: nft_inner: Fix IPv6 inner_thoff desync + * CVE-2026-46137 + - mptcp: pm: ADD_ADDR rtx: allow ID 0 + - mptcp: pm: ADD_ADDR rtx: fix potential data-race + * CVE-2026-46185 + - smb/client: fix out-of-bounds read in symlink_data() + * CVE-2026-46195 + - smb: client: validate dacloffset before building DACL pointers + * CVE-2026-46289 + - lib/scatterlist: fix length calculations in extract_kvec_to_sg + * CVE-2026-46119 + - libceph: Fix slab-out-of-bounds access in auth message processing + * CVE-2026-46135 + - nvmet-tcp: fix race between ICReq handling and queue teardown + * CVE-2026-46155 + - smb/client: fix out-of-bounds read in smb2_compound_op() + * CVE-2026-46115 + - block: add pgmap check to biovec_phys_mergeable + * CVE-2026-46243 + - smb: client: reject userspace cifs.spnego descriptions - -- Kuba Pawlak Mon, 06 Jul 2026 15:03:39 +0200 + -- Kuba Pawlak Thu, 09 Jul 2026 16:29:19 +0200 linux-qcom (7.0.0-1006.8) resolute; urgency=medium diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 8d798b66af371..a639b51de92b5 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -1989,7 +1989,6 @@ CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> CONFIG_RTSN policy<{'arm64': '-'}> -CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11)"'}> CONFIG_RZG2L_ADC policy<{'arm64': '-'}> CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> diff --git a/debian.qcom/reconstruct b/debian.qcom/reconstruct index 01029ffd62b3a..4e5a27f340119 100644 --- a/debian.qcom/reconstruct +++ b/debian.qcom/reconstruct @@ -30,9 +30,15 @@ chmod +x 'debian/templates/image.preinst.in' chmod +x 'debian/templates/image.prerm.in' chmod +x 'debian/tests/rebuild' chmod +x 'debian/tests/ubuntu-regression-suite' +chmod +x 'tools/testing/selftests/rseq/run_legacy_check.sh' +chmod +x 'tools/testing/selftests/rseq/run_timeslice_test.sh' # Remove any files deleted from the orig. +rm -f 'Documentation/ABI/obsolete/sysfs-selinux-user' rm -f 'arch/parisc/lib/checksum.c' rm -f 'drivers/media/platform/qcom/iris/iris_platform_gen1.c' rm -f 'drivers/media/platform/qcom/iris/iris_platform_gen2.c' +rm -f 'drivers/platform/x86/lenovo/wmi-gamezone.h' +rm -f 'tools/testing/selftests/bpf/prog_tests/access_variable_array.c' +rm -f 'tools/testing/selftests/bpf/progs/test_access_variable_array.c' rm -f 'tools/testing/selftests/mqueue/setting' exit 0 From 42b8d7f25c273485f7b580383893188b2d2e589d Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Tue, 14 Jul 2026 16:21:17 +0200 Subject: [PATCH 0980/1330] FROMLIST: drm/msm/dp: return 0 from audio_prepare when cable is disconnected PipeWire treats a non-zero return from prepare as fatal, marking the DP audio device as a dummy sink when the cable is unplugged. The active_stream_cnt guard already prevents any unclocked hardware access, so return success instead of -EINVAL when the link is not active. (adjusted after merging: replace power_on with active_stream_cnt for dp_display) LP: #2132964 Link: https://lore.kernel.org/all/20260616151252.3599089-2-kumar.singh@oss.qualcomm.com/ Signed-off-by: Kumar Anurag Signed-off-by: Kuba Pawlak --- drivers/gpu/drm/msm/dp/dp_audio.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_audio.c index 035e230201fd9..8118130a3220f 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -284,10 +284,8 @@ int msm_dp_audio_prepare(struct drm_bridge *bridge, * such cases check for connection status and bail out if not * connected. */ - if (!msm_dp_display->active_stream_cnt) { - rc = -EINVAL; + if (!msm_dp_display->active_stream_cnt) goto end; - } audio = msm_dp_audio_get_data(msm_dp_display); if (IS_ERR(audio)) { From be83c433ed59f819247faf07e6c3db81bd809abb Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 29 Apr 2026 12:12:23 +0530 Subject: [PATCH 0981/1330] FROMLIST: PCI: host-common: Add helper to determine host bridge D3cold eligibility Add a common helper, pci_host_common_d3cold_possible(), to determine whether PCIe devices under host bridge can safely transition to D3cold. This helper is intended to be used by PCI host controller drivers to decide whether they may safely put the host bridge into D3cold based on the power state and wakeup capabilities of downstream endpoints. The helper walks all devices on the all bridge buses and only allows the devices to enter D3cold if all PCIe endpoints are already in PCI_D3hot. This ensures that we do not power off the host bridge while any active endpoint still requires the link to remain powered. For devices that may wake the system, the helper additionally requires that the device supports PME wake from D3cold (via WAKE#). Devices that do not have wakeup enabled are not restricted by this check and do not block the devices under host bridge from entering D3cold. Devices without a bound driver and with PCI not enabled via sysfs are treated as inactive and therefore do not prevent the devices under host bridge from entering D3cold. This allows controllers to power down more aggressively when there are no actively managed endpoints. Some devices (e.g. M.2 without auxiliary power) lose PME detection when main power is removed. Even if such devices advertise PME-from-D3cold capability, entering D3cold may break wakeup. So, return PME-from-D3cold capability via an output parameter so PCIe controller drivers can apply platform-specific handling to preserve wakeup functionality. Link: https://lore.kernel.org/r/20260429-d3cold-v5-1-89e9735b9df6@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang (cherry picked from commit b323b93436feb062fcf65c043ec733ad988fcd00) --- drivers/pci/controller/pci-host-common.c | 66 +++++++++++++++++++----- drivers/pci/controller/pci-host-common.h | 2 +- 2 files changed, 55 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c index 1e53819f5e720..09432d69175c7 100644 --- a/drivers/pci/controller/pci-host-common.c +++ b/drivers/pci/controller/pci-host-common.c @@ -17,6 +17,9 @@ #include "pci-host-common.h" +#define PCI_HOST_D3COLD_ALLOWED BIT(0) +#define PCI_HOST_PME_D3COLD_CAPABLE BIT(1) + static void gen_pci_unmap_cfg(void *ptr) { pci_ecam_free((struct pci_config_window *)ptr); @@ -106,34 +109,73 @@ void pci_host_common_remove(struct platform_device *pdev) } EXPORT_SYMBOL_GPL(pci_host_common_remove); -static int pci_host_common_check_d3cold(struct pci_dev *pdev, void *userdata) +static int __pci_host_common_d3cold_possible(struct pci_dev *pdev, void *userdata) { - bool *d3cold_allow = userdata; + u32 *flags = userdata; + int type; + + /* Ignore conventional PCI devices */ + if (!pci_is_pcie(pdev)) + return 0; + + type = pci_pcie_type(pdev); + if (type != PCI_EXP_TYPE_ENDPOINT && + type != PCI_EXP_TYPE_LEG_END && + type != PCI_EXP_TYPE_RC_END) + return 0; - if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ENDPOINT) + if (!pdev->dev.driver && !pci_is_enabled(pdev)) return 0; if (pdev->current_state != PCI_D3hot) goto exit; - if (device_may_wakeup(&pdev->dev) && !pci_pme_capable(pdev, PCI_D3cold)) - goto exit; + if (device_may_wakeup(&pdev->dev)) { + if (!pci_pme_capable(pdev, PCI_D3cold)) + goto exit; + else + *flags |= PCI_HOST_PME_D3COLD_CAPABLE; + } return 0; + exit: - *d3cold_allow = false; - return -EBUSY; + *flags &= ~PCI_HOST_D3COLD_ALLOWED; + + return -EOPNOTSUPP; } -bool pci_host_common_can_enter_d3cold(struct pci_host_bridge *bridge) +/** + * pci_host_common_d3cold_possible - Determine whether the host bridge can transition the + * devices into D3Cold. + * + * @bridge: PCI host bridge to check + * @pme_capable: Pointer to update if there is any device which is capable of generating + * PME from D3cold. + * + * Walk downstream PCIe endpoint devices and determine whether the host bridge + * is permitted to transition the devices into D3cold. + * + * Devices under host bridge can enter D3cold only if all active PCIe endpoints are in + * PCI_D3hot and any wakeup-enabled endpoint is capable of generating PME from D3cold. + * Inactive endpoints are ignored. + * + * The @pme_capable output allows PCIe controller drivers to apply + * platform-specific handling to preserve wakeup functionality. + * + * Return: %true if the host bridge may enter D3cold, otherwise %false. + */ +bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge, bool *pme_capable) { - bool d3cold_allow = true; + u32 flags = PCI_HOST_D3COLD_ALLOWED; + + pci_walk_bus(bridge->bus, __pci_host_common_d3cold_possible, &flags); - pci_walk_bus(bridge->bus, pci_host_common_check_d3cold, &d3cold_allow); + *pme_capable = !!(flags & PCI_HOST_PME_D3COLD_CAPABLE); - return d3cold_allow; + return !!(flags & PCI_HOST_D3COLD_ALLOWED); } -EXPORT_SYMBOL_GPL(pci_host_common_can_enter_d3cold); +EXPORT_SYMBOL_GPL(pci_host_common_d3cold_possible); MODULE_DESCRIPTION("Common library for PCI host controller drivers"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/controller/pci-host-common.h index 18a731bca0588..7eb5599b9ce4f 100644 --- a/drivers/pci/controller/pci-host-common.h +++ b/drivers/pci/controller/pci-host-common.h @@ -21,5 +21,5 @@ void pci_host_common_remove(struct platform_device *pdev); struct pci_config_window *pci_host_common_ecam_create(struct device *dev, struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops); -bool pci_host_common_can_enter_d3cold(struct pci_host_bridge *bridge); +bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge, bool *pme_capable); #endif From b11a6d32d4ab7f1846d16be07e36e53f6eaae7da Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 29 Apr 2026 12:12:25 +0530 Subject: [PATCH 0982/1330] FROMLIST: PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks Some Qcom PCIe controller variants bring the PHY out of test power-down (PHY_TEST_PWR_DOWN) during init. When the link is later transitioned towards D3cold and the driver disables PCIe clocks and/or regulators without explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain partially powered, leading to avoidable power leakage. Update the init-path comments to reflect that PARF_PHY_CTRL is used to power the PHY on. Also, for controller revisions that enable PHY power in init (2.3.2, 2.3.3, 2.4.0, 2.7.0 and 2.9.0), explicitly power the PHY down via PARF_PHY_CTRL in the deinit path before disabling clocks or regulators. This ensures the PHY is put into a defined low-power state prior to removing its supplies, preventing leakage when entering D3cold. Link: https://lore.kernel.org/r/20260429-d3cold-v5-3-89e9735b9df6@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang (cherry picked from commit c49333b62420f49dd4ea833e1be7bc2152edc0e6) --- drivers/pci/controller/dwc/pcie-qcom.c | 34 +++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 98499684ab410..6545286bd8754 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -519,7 +519,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) u32 val; int ret; - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -686,6 +686,12 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; + u32 val; + + /* Force PHY to lowest power state*/ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -718,7 +724,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) { u32 val; - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -782,6 +788,12 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; + u32 val; + + /* Force PHY to lowest power state*/ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); reset_control_bulk_assert(res->num_resets, res->resets); clk_bulk_disable_unprepare(res->num_clks, res->clks); @@ -850,6 +862,12 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; + u32 val; + + /* Force PHY to lowest power state */ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -905,6 +923,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1000,7 +1019,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1073,7 +1092,7 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; u32 val; - /* Disable PCIe clocks and resets */ + /* Force PHY to lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val |= PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1181,6 +1200,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; + u32 val; + + /* Force PHY to lowest power state */ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -1221,6 +1246,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) u32 val; int i; + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); From 4a45a6fc018bc7f6453f2aad5961bbad041c679f Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 14 May 2026 18:06:38 +0800 Subject: [PATCH 0983/1330] QCLINUX: qcom-dcc: add shikra register list and move config to header Add the DCC register capture list for the Shikra platform (SoC IDs 756, 758, 759) across two linked lists and move the configuration into a dedicated header qcom-dcc-shikra-config.h. Signed-off-by: Jie Gan (cherry picked from commit d2b684d4e5b36500580ec454a89441903f6ab329) --- drivers/misc/qcom-dcc-dev.c | 8 + drivers/misc/qcom-dcc-shikra-config.h | 677 ++++++++++++++++++++++++++ 2 files changed, 685 insertions(+) create mode 100644 drivers/misc/qcom-dcc-shikra-config.h diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c index a77b5bc144982..73994f39de30e 100644 --- a/drivers/misc/qcom-dcc-dev.c +++ b/drivers/misc/qcom-dcc-dev.c @@ -11,6 +11,7 @@ #include "qcom-dcc-lemans-config.h" #include "qcom-dcc-kodiak-config.h" #include "qcom-dcc-pakala-config.h" +#include "qcom-dcc-shikra-config.h" #define DEV_NAME "qcom-dcc" @@ -131,6 +132,13 @@ static int __init dcc_dev_init(void) goto fail; break; + case 756: + case 758: + case 759: + ret = platform_device_add_data(dcc_pdev, &shikra_pdata, sizeof(shikra_pdata)); + if (ret) + goto fail; + break; default: pr_err("DCC: Invalid SoC ID\n"); ret = -EINVAL; diff --git a/drivers/misc/qcom-dcc-shikra-config.h b/drivers/misc/qcom-dcc-shikra-config.h new file mode 100644 index 0000000000000..fdf3d0c34695c --- /dev/null +++ b/drivers/misc/qcom-dcc-shikra-config.h @@ -0,0 +1,677 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _QCOM_DCC_SHIKRA_CONFIG_H +#define _QCOM_DCC_SHIKRA_CONFIG_H + +#include "qcom-dcc.h" + +static const struct dcc_register_entry shikra_dcc_entries_ll2[] = { + /* timer */ + { "R 0x17421000 2" }, + /* clock */ + { "R 0x1400000 10" }, + { "R 0x1401000 10" }, + { "R 0x1402000 10" }, + { "R 0x1403000 10" }, + { "R 0x1404000 10" }, + { "R 0x1405000 10" }, + { "R 0x1406000 10" }, + { "R 0x1407000 10" }, + { "R 0x1408000 10" }, + { "R 0x1409000 9" }, + { "R 0x140a000 10" }, + { "R 0x140b000 10" }, + { "R 0x140c000 10" }, + { "R 0x141001c" }, + { "R 0x14103d0" }, + { "R 0x1414024" }, + { "R 0x1415034 2" }, + { "R 0x141f02c" }, + { "R 0x141f15c" }, + { "R 0x141f28c" }, + { "R 0x141f3bc" }, + { "R 0x141f4ec" }, + { "R 0x141f61c" }, + { "R 0x141f74c" }, + { "R 0x141f87c" }, + { "R 0x141f9ac" }, + { "R 0x141fadc" }, + { "R 0x141fc0c" }, + { "R 0x1427024" }, + { "R 0x1432034" }, + { "R 0x1434028" }, + { "R 0x1434154" }, + { "R 0x143c018" }, + { "R 0x1446024" }, + { "R 0x1446154" }, + { "R 0x1449018" }, + { "R 0x14b4014" }, + { "R 0x146b000 14" }, + { "R 0xfa80000 6" }, + { "R 0xfa8001c 2" }, + { "R 0xfa80028" }, + { "R 0xfa80034 2" }, + { "R 0xfa80080 3" }, + { "R 0xfa84000 6" }, + { "R 0xfa8401c 2" }, + { "R 0xfa84028" }, + { "R 0xfa84034 2" }, + { "R 0xfa84080 3" }, + { "R 0xfa88000 6" }, + { "R 0xfa8801c 2" }, + { "R 0xfa88028" }, + { "R 0xfa88034 2" }, + { "R 0xfa88080 3" }, + { "R 0x440c000" }, + { "R 0x440c008" }, + { "R 0x440c040 9" }, + { "R 0x440c068 2" }, + /* global_cpr */ + { "R 0x1648000 2" }, + { "R 0x16480e0" }, + { "R 0x1648100" }, + { "R 0x1648120" }, + { "R 0x1648140" }, + { "R 0x1648200" }, + { "R 0x164880c 4" }, + { "R 0x164c000 2" }, + { "R 0x164c0e0" }, + { "R 0x164c100" }, + { "R 0x164c120" }, + { "R 0x164c140" }, + { "R 0x164c200" }, + { "R 0x164c80c 4" }, + { "R 0x1b44268 7" }, + { "R 0x1b44288 11" }, + { "R 0x1b442d0" }, + /* cpr */ + { "R 0xfd9001c 3" }, + { "R 0xfd90090" }, + { "R 0xfd900b0 2" }, + { "R 0xfd900d8" }, + { "R 0xfd900e8" }, + { "R 0xfd90300" }, + { "R 0xfd90320" }, + { "R 0xfd90348 3" }, + { "R 0xfd90360" }, + { "R 0xfd90368 2" }, + { "R 0xfd9101c 3" }, + { "R 0xfd91090" }, + { "R 0xfd910b0 2" }, + { "R 0xfd910d8" }, + { "R 0xfd910e8" }, + { "R 0xfd91300" }, + { "R 0xfd91320" }, + { "R 0xfd91348 3" }, + { "R 0xfd91360" }, + { "R 0xfd91368 2" }, + { "R 0xfd9201c 3" }, + { "R 0xfd92090" }, + { "R 0xfd920b0 2" }, + { "R 0xfd920d8" }, + { "R 0xfd920e8" }, + { "R 0xfd92300" }, + { "R 0xfd92320" }, + { "R 0xfd92348 4" }, + { "R 0xfd92360" }, + { "R 0xfd92368 2" }, + { "R 0xfd98004" }, + { "R 0xfd98018 3" }, + { "R 0xf900c14 2" }, + { "R 0xfba0008" }, + { "R 0xfba0020 2" }, + { "R 0xfba0070" }, + { "R 0xfba0810" }, + { "R 0xfba3500" }, + { "R 0xfba3a84 2" }, + { "R 0xfa90004" }, + { "R 0xfa92004" }, + { "R 0xfa94004" }, + { "R 0xfba3a84 3" }, + { "R 0xfd90200 12" }, + { "R 0xfd91200 12" }, + { "R 0xfd92200 12" }, + { "R 0xfba3500 40" }, + /* cpucp */ + { "R 0xfd80110" }, + { "R 0xfd9001c" }, + { "R 0xfd90090" }, + { "R 0xfd900b0" }, + { "R 0xfd900d8" }, + { "R 0xfd900e8" }, + { "R 0xfd90300" }, + { "R 0xfd90320" }, + { "R 0xfd90348" }, + { "R 0xfd9101c" }, + { "R 0xfd91090" }, + { "R 0xfd910b0" }, + { "R 0xfd910d8" }, + { "R 0xfd910e8" }, + { "R 0xfd91300" }, + { "R 0xfd91320" }, + { "R 0xfd91348" }, + { "R 0xfd9201c" }, + { "R 0xfd92090" }, + { "R 0xfd920b0" }, + { "R 0xfd920d8" }, + { "R 0xfd920e8" }, + { "R 0xfd92300" }, + { "R 0xfd92320" }, + { "R 0xfd92348" }, + { "R 0xfd98004" }, + { "R 0xfd98018" }, + { "R 0xf900c00" }, + { "R 0xfb00000" }, + { "R 0xfba0000" }, + { "R 0xf800000" }, + { "R 0xf810000" }, + { "R 0xf820000" }, + { "R 0xf830000" }, + { "R 0xf840000" }, + { "R 0xf850000" }, + { "R 0xf860000" }, + { "R 0xf870000" }, + { "R 0xfd91000" }, + { "R 0xfd92000" }, + { "R 0xf880000" }, + { "R 0xfd90000" }, + { "R 0xf900c18" }, + { "R 0xfd9134c" }, + { "R 0xfd9234c" }, + { "R 0xfd9034c" }, + { "R 0xfba3a84" }, + { "R 0xfba3a88" }, + { "R 0xfba3a8c" }, + { "R 0xfd91020" }, + { "R 0xfd92020" }, + { "R 0xfd90020" }, + /* modem */ + { "R 0x6080400 3" }, + { "R 0x6080410 2" }, + { "R 0x6080060 5" }, + { "R 0x61f100c" }, + { "R 0x143314c" }, + { "R 0x6140400 3" }, + { "R 0x6082028" }, + { "R 0x6080304" }, + { "R 0xd2f010" }, + { "R 0x6104000 8" }, + { "R 0x6140208 3" }, + { "R 0x6140228 3" }, + { "R 0x6140248 3" }, + { "R 0x6140268 3" }, + { "R 0x6140288 3" }, + { "R 0x6140400 3" }, + { "R 0x6082028" }, + { "R 0x6080304" }, + { "R 0x6140200" }, + { "R 0x6140404" }, + { "R 0x608030c" }, + /* ICB - SYSTEM_NOC */ + { "R 0x1880000" }, + { "R 0x1880004" }, + { "R 0x1880008" }, + { "R 0x1880010" }, + { "R 0x1880020" }, + { "R 0x1880024" }, + { "R 0x1880028" }, + { "R 0x188002c" }, + { "R 0x1880030" }, + { "R 0x1880034" }, + { "R 0x1880038" }, + { "R 0x188003c" }, + { "R 0x1880240" }, + { "R 0x1880248" }, + { "R 0x1881018" }, + { "R 0x1881008" }, + { "R 0x1881010 2" }, + { "R 0x1881098" }, + { "R 0x1881088" }, + { "R 0x1881090 2" }, + { "R 0x1881118" }, + { "R 0x1881108" }, + { "R 0x1881110 2" }, + { "R 0x1881198" }, + { "R 0x1881188" }, + { "R 0x1881190 2" }, + { "R 0x1881218" }, + { "R 0x1881208" }, + { "R 0x1881210 2" }, + /* ICB - CONFIG_NOC */ + { "R 0x1900000" }, + { "R 0x1900004" }, + { "R 0x1900008" }, + { "R 0x1900010" }, + { "R 0x1900020" }, + { "R 0x1900024" }, + { "R 0x1900028" }, + { "R 0x190002c" }, + { "R 0x1900030" }, + { "R 0x1900034" }, + { "R 0x1900038" }, + { "R 0x190003c" }, + { "R 0x1900240" }, + { "R 0x1900244" }, + { "R 0x1900248" }, + { "R 0x190024c" }, + { "R 0x1901018" }, + { "R 0x1901008" }, + { "R 0x1901010 2" }, + { "R 0x1901118" }, + { "R 0x1901108" }, + { "R 0x1901110 2" }, + { "R 0x1901218" }, + { "R 0x1901208" }, + { "R 0x1901210 2" }, + { "R 0x1901318" }, + { "R 0x1901308" }, + { "R 0x1901310 2" }, + /* ICB - MEMNOC */ + { "R 0xd00000" }, + { "R 0xd00004" }, + { "R 0xd00008" }, + { "R 0xd00010" }, + { "R 0xd00020" }, + { "R 0xd00024" }, + { "R 0xd00028" }, + { "R 0xd0002c" }, + { "R 0xd00030" }, + { "R 0xd00034" }, + { "R 0xd00038" }, + { "R 0xd0003c" }, + { "R 0xd40000" }, + { "R 0xd40004" }, + { "R 0xd40008" }, + { "R 0xd40010" }, + { "R 0xd40020" }, + { "R 0xd40024" }, + { "R 0xd40028" }, + { "R 0xd4002c" }, + { "R 0xd40030" }, + { "R 0xd40034" }, + { "R 0xd40038" }, + { "R 0xd4003c" }, + { "R 0xd00240" }, + { "R 0xd00248" }, + { "R 0xd40440" }, + { "R 0xd40448" }, + { "R 0xd41018" }, + { "R 0xd41008" }, + { "R 0xd41010 2" }, + { "R 0xd01018" }, + { "R 0xd01008" }, + { "R 0xd01010 2" }, + /* ICB - DC_NOC */ + { "R 0xce5018" }, + { "R 0xce5008" }, + { "R 0xce5010 2" }, + { "R 0xce0010" }, + { "R 0xce0020 8" }, + { "R 0xce0248" }, + /* ICB - QoS - system noc */ + { "R 0x18d1010" }, + { "R 0x18d2010" }, + { "R 0x18d3010" }, + { "R 0x18d4010" }, + { "R 0x18d5010" }, + { "R 0x18d6010" }, + { "R 0x18d7010" }, + { "R 0x18d8010" }, + { "R 0x18d9010" }, + { "R 0x18da010" }, + { "R 0x18db010" }, + { "R 0x18dc010" }, + { "R 0x18dd010" }, + { "R 0x18de010" }, + { "R 0x18df010" }, + { "R 0x18e0010" }, + { "R 0x18e1010" }, + { "R 0x18e2010" }, + { "R 0x18e3010" }, + { "R 0x18e4010" }, + { "R 0x18e5010" }, + { "R 0x18e6010" }, + { "R 0x18e7010" }, + { "R 0x18e8010" }, + { "R 0x18e9010" }, + { "R 0x18ea010" }, + /* ICB - QoS - mem noc */ + { "R 0xd28010" }, + { "R 0xd2a010" }, + { "R 0xd2b010" }, + { "R 0xd2c010" }, + { "R 0xd2d010" }, + { "R 0xd2e010" }, + { "R 0xd2f010" }, + /* ddr */ + { "R 0x1089180 2" }, + { "R 0x10804d4" }, + { "R 0x10804b8 2" }, + { "R 0x1089100" }, + { "R 0x1089110" }, + { "R 0x1089120" }, + { "R 0x10891a0" }, + { "R 0x108340c" }, + { "R 0x1083404" }, + { "R 0x1083410" }, + { "R 0x1083408" }, + { "R 0x1083400" }, + { "R 0x1086418" }, + { "R 0x1086400" }, + { "R 0x1086420" }, + { "R 0x1086410" }, + { "R 0x10891c0" }, + { "R 0x10891e0" }, + { "R 0x1085b14" }, + { "R 0x1085b10" }, + { "R 0x1085b0c" }, + { "R 0x1085b00" }, + { "R 0x10853b0" }, + { "R 0x1085b1c" }, + { "R 0x1085b08" }, + { "R 0x1085b38" }, + { "R 0x1085b30" }, + { "R 0x1085b2c" }, + { "R 0x1085804" }, + { "R 0x1085b28" }, + { "R 0x1085b18" }, + { "R 0x1085230" }, + { "R 0x1085210" }, + { "R 0xc800b0 2" }, + { "R 0xcb6000" }, + { "R 0x1286074 5" }, + { "R 0x1286260 5" }, + { "R 0xc80018" }, + { "R 0xc80108" }, + { "R 0xc840e0 2" }, + { "R 0xcba070 2" }, + { "R 0xcba054" }, + { "R 0xcba078 2" }, + { "R 0xcba058" }, + { "R 0xcba080" }, + { "R 0xcba084" }, + { "R 0xcba05c" }, + { "R 0xcba088" }, + { "R 0xcba08c" }, + { "R 0xcba060" }, + { "R 0xcba090 2" }, + { "R 0xcba064" }, + { "R 0xcba098 2" }, + { "R 0x1090018" }, + { "R 0x1090110 4" }, + { "R 0x1090004" }, + { "R 0x10900a0" }, + { "R 0x1090170" }, + { "R 0x1090180 4" }, + { "R 0x1090078" }, + { "R 0x1090150 4" }, + { "R 0x1090080" }, + { "R 0x1090088" }, + { "R 0x1090090" }, + { "R 0x1090070 2" }, + { "R 0x10900b0" }, + { "R 0x1090130" }, + { "R 0x1090140" }, + { "R 0x1090030 3" }, + { "R 0x1090044" }, + { "R 0x1090144" }, + { "R 0x1090040 3" }, + { "R 0x10900c8 2" }, + { "R 0x1090050" }, + { "R 0x1090128 2" }, + { "R 0x10900e4 5" }, + { "R 0x1090124" }, + { "R 0x1090100" }, + { "R 0xe90018" }, + { "R 0xe90110 4" }, + { "R 0xe90004" }, + { "R 0xe900a0" }, + { "R 0xe90170" }, + { "R 0xe90180 4" }, + { "R 0xe90078" }, + { "R 0xe90150" }, + { "R 0xe90080" }, + { "R 0xe90154" }, + { "R 0xe90088" }, + { "R 0xe90158" }, + { "R 0xe90090" }, + { "R 0xe9015c" }, + { "R 0xe90070 2" }, + { "R 0xe900b0" }, + { "R 0xe90130" }, + { "R 0xe90034" }, + { "R 0xe90140" }, + { "R 0xe90038" }, + { "R 0xe90030" }, + { "R 0xe90044" }, + { "R 0xe90144" }, + { "R 0xe90048" }, + { "R 0xe90040" }, + { "R 0xe900c8 2" }, + { "R 0xe90050" }, + { "R 0xe90128 2" }, + { "R 0xe900e4 3" }, + { "R 0xe900f0 2" }, + { "R 0xe90124" }, + { "R 0xe90100" }, + { "R 0xf90018" }, + { "R 0xf90110 4" }, + { "R 0xf90004" }, + { "R 0xf900a0" }, + { "R 0xf90170" }, + { "R 0xf90180 4" }, + { "R 0xf90078" }, + { "R 0xf90150 4" }, + { "R 0xf90080" }, + { "R 0xf90088" }, + { "R 0xf90090" }, + { "R 0xf90070 2" }, + { "R 0xf900b0" }, + { "R 0xf90130 2" }, + { "R 0xf90140" }, + { "R 0xf90038" }, + { "R 0xf90030" }, + { "R 0xf90044" }, + { "R 0xf90144" }, + { "R 0xf90048" }, + { "R 0xf90040" }, + { "R 0xf900c8 2" }, + { "R 0xf90050" }, + { "R 0xf90128 2" }, + { "R 0xf900e4 5" }, + { "R 0xf90124" }, + { "R 0xf90100" }, + { "R 0xcba218" }, + { "R 0xcba050" }, + { "R 0xcba210" }, + { "R 0xcba280" }, + { "R 0xcba180 4" }, + { "R 0xcba214" }, + { "R 0xcba004" }, + { "R 0xcba000" }, + { "R 0xcba014 2" }, + { "R 0xcba020 2" }, + { "R 0xcba010" }, + { "R 0xcba288 7" }, + { "R 0xcba150 2" }, + { "R 0xcba200" }, + { "R 0xcba140 2" }, + { "R 0xcba230 2" }, + { "R 0xcba0c8 2" }, + { "R 0xcba0b0 4" }, + { "R 0xcba240 2" }, + { "R 0xcba250 4" }, + { "R 0xcba100 5" }, + { "R 0xcba120 3" }, + { "R 0xcba130" }, + { "R 0xcba134" }, + { "R 0xcba270" }, + { "R 0xc35008" }, + { "R 0xc350b4" }, + { "R 0xc35100" }, + { "R 0x1059070" }, + { "R 0x103801c 7" }, + { "R 0x1023318" }, + { "R 0x1020488" }, + { "R 0x1020480" }, + { "R 0x1023594" }, + { "R 0x102358c" }, + { "R 0x10223a0" }, + { "R 0x1022398" }, + { "R 0x10223ac" }, + { "R 0x10223a4" }, + { "R 0x128007c" }, + { "R 0x128107c" }, + { "R 0x128207c" }, + { "R 0x128307c" }, + { "R 0x128407c" }, + { "R 0x128507c" }, + { "R 0x12800a4" }, + { "R 0x12810a4" }, + { "R 0x12820a4" }, + { "R 0x12830a4" }, + { "R 0x12840a4" }, + { "R 0x12850a4" }, + { "R 0x1280100" }, + { "R 0x1281100" }, + { "R 0x1282100" }, + { "R 0x1283100" }, + { "R 0x1284100" }, + { "R 0x1285100" }, + { "R 0x128011c" }, + { "R 0x128111c" }, + { "R 0x128211c" }, + { "R 0x128311c" }, + { "R 0x128411c" }, + { "R 0x128511c" }, + { "R 0x1280568" }, + { "R 0x1281568" }, + { "R 0x1282568" }, + { "R 0x1283568" }, + { "R 0x1284568" }, + { "R 0x1285568" }, + { "R 0x128082c" }, + { "R 0x128182c" }, + { "R 0x128282c" }, + { "R 0x128382c" }, + { "R 0x128482c" }, + { "R 0x128582c" }, + { "R 0x128007c" }, + { "R 0x128107c" }, + { "R 0x128207c" }, + { "R 0x128307c" }, + { "R 0x128407c" }, + { "R 0x128507c" }, + { "R 0x12800a4" }, + { "R 0x12810a4" }, + { "R 0x12820a4" }, + { "R 0x12830a4" }, + { "R 0x12840a4" }, + { "R 0x12850a4" }, + { "R 0xc80058 2" }, + { "R 0xc800c8" }, + { "R 0xc800d4" }, + { "R 0xc80114" }, + { "R 0xc80104 2" }, + { "R 0xc800b0 2" }, + { "R 0xc80098" }, + { "R 0xd00248" }, +}; + +static const struct dcc_register_entry shikra_dcc_entries_ll3[] = { + /* gpu */ + { "R 0x599106c" }, + { "R 0x599100c" }, + { "R 0x59910a4" }, + { "R 0x5991054" }, + { "R 0x5991098 2" }, + { "R 0x5991078" }, + { "R 0x5991508" }, + { "R 0x599150c" }, + { "R 0x143600c" }, + { "R 0x1471000" }, + { "R 0x1436018" }, + /* cdsp */ + { "R 0xb3b0208 3" }, + { "R 0xb3b0228 3" }, + { "R 0xb3b0248 3" }, + { "R 0xb3b0268 3" }, + { "R 0xb3b0290" }, + { "R 0xb3b02b0" }, + { "R 0xb3b0400 3" }, + { "R 0xb302028" }, + { "R 0xb300304" }, + { "R 0xb3b0200" }, + { "R 0xb3b0404" }, + { "R 0x608030c" }, + /* apps_pcu */ + { "R 0xf800024" }, + { "R 0xf800040" }, + { "R 0xf80004c" }, + { "R 0xf800054" }, + { "R 0xf810024" }, + { "R 0xf810040" }, + { "R 0xf81004c" }, + { "R 0xf810054" }, + { "R 0xf820024" }, + { "R 0xf820040" }, + { "R 0xf82004c" }, + { "R 0xf820054" }, + { "R 0xf830024" }, + { "R 0xf830040" }, + { "R 0xf83004c" }, + { "R 0xf830054" }, + { "R 0xf880024" }, + { "R 0xf880040" }, + { "R 0xf880098" }, + { "R 0xfa80000 2" }, + { "R 0xfa84000 2" }, + { "R 0xfa88000 2" }, + { "R 0xf880200" }, + { "R 0xf8801b4 3" }, + { "R 0xf880044 3" }, + { "R 0xf880054" }, + { "R 0xf88006c" }, + { "R 0xf880070 4" }, + { "R 0xfd90348 2" }, + { "R 0xfd91348 2" }, + { "R 0xfd92348 2" }, + { "R 0xfd800fc" }, + { "R 0xfd800ec" }, + { "R 0xfd8010c" }, + { "R 0xfd91060 8" }, + { "R 0xfd92064 8" }, +}; + +static const struct dcc_link_config shikra_link_configs[] = { + { + .link_list = 2, + .entries = shikra_dcc_entries_ll2, + .num_entries = ARRAY_SIZE(shikra_dcc_entries_ll2), + }, + { + .link_list = 3, + .entries = shikra_dcc_entries_ll3, + .num_entries = ARRAY_SIZE(shikra_dcc_entries_ll3), + }, +}; + +static const struct dcc_config shikra_config = { + .lists = shikra_link_configs, + .num_lists = ARRAY_SIZE(shikra_link_configs), +}; + +static const struct dcc_pdata shikra_pdata = { + .base = 0x080ff000, + .size = 0x00001000, + .ram_base = 0x08086000, + .ram_size = 0x00002000, + .dcc_offset = 0x6000, + .map_ver = 0x3, + .config = &shikra_config, +}; + +#endif /* _QCOM_DCC_SHIKRA_CONFIG_H */ From 0eee83266e4d0ff906d9fe443e9964e7745cddf3 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Wed, 13 May 2026 00:51:18 +0530 Subject: [PATCH 0984/1330] FROMLIST: drm/msm/a8xx: Fix RSCC offset In A8xx, the RSCC block is part of GPU's register space. Update the virtual base address of rscc to point to the correct address. Link: https://lore.kernel.org/all/20260512-glymur-gpu-dt-v3-1-84232dc21c03@oss.qualcomm.com/ Fixes: 50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x GMU") Signed-off-by: Akhil P Oommen (cherry picked from commit d55c4cc90b8a3cc682f076e7a1f04e69f376805c) --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 1b44b9e21ad86..cab4c46c6cf2e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2357,7 +2357,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_mmio; } } else if (adreno_is_a8xx(adreno_gpu)) { - gmu->rscc = gmu->mmio + 0x19000; + /* + * On a8xx , RSCC lives at GPU base + 0x50000, which falls + * inside the GPU's kgsl_3d0_reg_memory range rather than the + * GMU's. + */ + gmu->rscc = gpu->mmio + 0x50000; } else { gmu->rscc = gmu->mmio + 0x23000; } From cb2277a88fe64f42f220a266ccc9e43d2fd3fdbe Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Wed, 13 May 2026 00:51:19 +0530 Subject: [PATCH 0985/1330] FROMLIST: dt-bindings: display/msm: gpu: Document Adreno X2-185 Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family. It features a new slice architecture with 4 slices, significantly higher bandwidth throughput compared to mobile counterparts, raytracing support, and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other improvements. Update the dt bindings documentation to describe this GPU. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-2-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen (cherry picked from commit 689314d2e17fd735f296ea7e9bf2c51aab3203f6) --- .../devicetree/bindings/display/msm/gpu.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index ec84b64d4c00b..a5f4f79432c8f 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -411,6 +411,22 @@ allOf: - clocks - clock-names + - if: + properties: + compatible: + contains: + const: qcom,adreno-44070001 + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - if: properties: compatible: @@ -434,6 +450,7 @@ allOf: - qcom,adreno-43050a01 - qcom,adreno-43050c01 - qcom,adreno-43051401 + - qcom,adreno-44070001 then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: From 016a4e287ccb1bcf99321f3f7954d435705a6e77 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Wed, 13 May 2026 00:51:20 +0530 Subject: [PATCH 0986/1330] FROMLIST: dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU Add interconnects property to the common SMMU properties and extend the sm8750 clock description section to also cover Glymur since it uses the same single "hlos" vote clock. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-3-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen (cherry picked from commit 8a269bc8a41bf66243ecfba0a7f4f70a0f922f8c) --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index af9fa49706b54..97f1c6498b18a 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -566,7 +566,9 @@ allOf: properties: compatible: items: - - const: qcom,sm8750-smmu-500 + - enum: + - qcom,glymur-smmu-500 + - qcom,sm8750-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 From 7507b1ee7b855e6585b76beeaee83a77dcea50a0 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 13 May 2026 00:51:21 +0530 Subject: [PATCH 0987/1330] FROMLIST: arm64: dts: qcom: glymur: Add GPU smmu node Add the nodes to describe the GPU SMMU node. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-4-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Rajendra Nayak Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen (cherry picked from commit a22f5dd6eb6ff027c2c5f95a3f65a9124f56b096) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index f38fe52a97dad..d31144794d4ca 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4361,7 +4361,6 @@ clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; clock-names = "hlos"; power-domains = <&gpucc GPU_CC_CX_GDSC>; - interconnects = <&hsc_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; dma-coherent; }; From 76235e6db3ec0775b3396eea98857d040f8199ae Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Wed, 13 May 2026 00:51:22 +0530 Subject: [PATCH 0988/1330] FROMLIST: arm64: dts: qcom: Add GPU support for Glymur The Adreno X2 series GPU present in Glymur SoC belongs to the A8x family. It is a new HW IP with architectural improvements as well as different set of hw configs like GMEM, num SPs, Caches sizes etc. Add the GPU and GMU nodes to describe this hardware. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-5-f83832c3bc9a@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen (cherry picked from commit 329c83fe73857bc62a99b9d98efe4bdea64577d8) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 182 +++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index d31144794d4ca..7fc54f1179351 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4121,6 +4121,129 @@ #interconnect-cells = <2>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-44070001", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x6c000>, + <0x0 0x03d9e000 0x0 0x2000>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + opp-peak-kBps = <2136719>; + opp-supported-hw = <0xf>; + /* ACD is disabled */ + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + opp-level = ; + opp-peak-kBps = <6074219>; + opp-supported-hw = <0xf>; + /* ACD is disabled */ + }; + + opp-572000000 { + opp-hz = /bits/ 64 <572000000>; + opp-level = ; + opp-peak-kBps = <12449219>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0xe02d5ffd>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-level = ; + opp-peak-kBps = <12449219>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0xa82e5ffd>; + }; + + opp-915000000 { + opp-hz = /bits/ 64 <915000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0x882d5ffd>; + }; + + opp-1070000000 { + opp-hz = /bits/ 64 <1070000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0x882b5ffd>; + }; + + opp-1185000000 { + opp-hz = /bits/ 64 <1185000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-level = ; + opp-peak-kBps = <18597657>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1550000000 { + opp-hz = /bits/ 64 <1550000000>; + opp-level = ; + opp-peak-kBps = <18597657>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0xa8295ffd>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-level = ; + opp-peak-kBps = <18597657>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0x88295ffd>; + }; + + opp-1850000000 { + opp-hz = /bits/ 64 <1850000000>; + opp-level = ; + opp-peak-kBps = <18597657>; + opp-supported-hw = <0x3>; + qcom,opp-acd-level = <0x88285ffd>; + }; + }; + }; + gxclkctl: clock-controller@3d64000 { compatible = "qcom,glymur-gxclkctl"; reg = <0x0 0x03d64000 0x0 0x6000>; @@ -4132,6 +4255,65 @@ #power-domain-cells = <1>; }; + gmu: gmu@3d6c000 { + compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"; + + reg = <0x0 0x03d6c000 0x0 0x32000>; + reg-names = "gmu"; + + interrupts = , + ; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_RSCC_HUB_AON_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "memnoc", + "hub", + "rscc"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + opp-level = ; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + }; + + opp-725000000 { + opp-hz = /bits/ 64 <725000000>; + opp-level = ; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-level = ; + }; + }; + }; gpu: gpu@3d00000 { compatible = "qcom,adreno-44070001", "qcom,adreno"; From f6a4040d44127ca08ea710b743f3f8c47d21490f Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 13 May 2026 00:51:23 +0530 Subject: [PATCH 0989/1330] FROMLIST: arm64: dts: qcom: glymur: Add GPU cooling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when it reaches 95°C. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-6-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Akhil P Oommen (cherry picked from commit b9fa9c0477e82dcb2e3bba3fc143b231ec0fe755) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 239 ++++++++++++++++++++------- 1 file changed, 183 insertions(+), 56 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 7fc54f1179351..622184f98f279 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -25,6 +25,7 @@ #include #include #include +#include #include "glymur-ipcc.h" @@ -9484,13 +9485,22 @@ }; thermal_gpu_0_0: gpu-0-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 1>; + cooling-maps { + map0 { + trip = <&gpu00_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu00_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-0-0-critical { @@ -9502,13 +9512,22 @@ }; thermal_gpu_0_1: gpu-0-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 2>; + cooling-maps { + map0 { + trip = <&gpu01_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu01_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-0-1-critical { @@ -9520,13 +9539,22 @@ }; thermal_gpu_0_2: gpu-0-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 3>; + cooling-maps { + map0 { + trip = <&gpu02_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu02_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-0-2-critical { @@ -9538,13 +9566,22 @@ }; thermal_gpu_1_0: gpu-1-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 4>; + cooling-maps { + map0 { + trip = <&gpu10_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu10_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-1-0-critical { @@ -9556,13 +9593,22 @@ }; thermal_gpu_1_1: gpu-1-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 5>; + cooling-maps { + map0 { + trip = <&gpu11_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu11_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-1-1-critical { @@ -9574,13 +9620,22 @@ }; thermal_gpu_1_2: gpu-1-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 6>; + cooling-maps { + map0 { + trip = <&gpu12_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu12_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-1-2-critical { @@ -9592,13 +9647,22 @@ }; thermal_gpu_2_0: gpu-2-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 7>; + cooling-maps { + map0 { + trip = <&gpu20_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu20_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-2-0-critical { @@ -9610,13 +9674,22 @@ }; thermal_gpu_2_1: gpu-2-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 8>; + cooling-maps { + map0 { + trip = <&gpu21_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu21_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-2-1-critical { @@ -9628,13 +9701,22 @@ }; thermal_gpu_2_2: gpu-2-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 9>; + cooling-maps { + map0 { + trip = <&gpu22_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu22_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-2-2-critical { @@ -9646,13 +9728,22 @@ }; thermal_gpu_3_0: gpu-3-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 10>; + cooling-maps { + map0 { + trip = <&gpu30_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu30_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-3-0-critical { @@ -9664,13 +9755,22 @@ }; thermal_gpu_3_1: gpu-3-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 11>; + cooling-maps { + map0 { + trip = <&gpu31_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu31_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-3-1-critical { @@ -9682,13 +9782,22 @@ }; thermal_gpu_3_2: gpu-3-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 12>; + cooling-maps { + map0 { + trip = <&gpu32_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu32_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-3-2-critical { @@ -9700,13 +9809,22 @@ }; thermal_gpuss_0: gpuss-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 13>; + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpuss0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpuss-0-critical { @@ -9718,13 +9836,22 @@ }; thermal_gpuss_1: gpuss-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 14>; + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpuss1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpuss-1-critical { From 68b76a0a46e604e68a683acb16d9b0f18df92b12 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 18 May 2026 14:14:20 +0800 Subject: [PATCH 0990/1330] PENDING: arm64: dts: qcom: hamoa: add TGU in staging dtso Add TGU devices for supporting IPCB feature in staging dtso file. Signed-off-by: Jie Gan (cherry picked from commit 519c1e08a87cde161e047df16c229a6675e262ef) --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/hamoa-staging.dtso | 35 +++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/hamoa-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b1b452d7cbd5f..60d5a89381277 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -574,3 +574,5 @@ dtb-$(CONFIG_ARCH_QCOM) += talos-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += kodiak-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += glymur-staging.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += hamoa-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/hamoa-staging.dtso b/arch/arm64/boot/dts/qcom/hamoa-staging.dtso new file mode 100644 index 0000000000000..feb3c7c5ccd82 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-staging.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Hamoa staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +&soc { + tgu@10b0e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b0e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@10b0f000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b0f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@10b10000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b10000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; From ceedfcc363ae111f4e372b27e6a6baa4de97a912 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 18 May 2026 14:18:09 +0800 Subject: [PATCH 0991/1330] PENDING: arm64: dts: qcom: sm8750: add TGU in staging dtso Add TGU devices for supporting IPCB feature in staging dtso file. Signed-off-by: Jie Gan (cherry picked from commit 3ab725095db243301f6814c647a1c75ffb3b51ea) --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/sm8750-staging.dtso | 35 ++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8750-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 60d5a89381277..f0377f51a4977 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -576,3 +576,5 @@ dtb-$(CONFIG_ARCH_QCOM) += kodiak-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += glymur-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-staging.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += sm8750-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/sm8750-staging.dtso b/arch/arm64/boot/dts/qcom/sm8750-staging.dtso new file mode 100644 index 0000000000000..68c477c63a328 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8750-staging.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SM8750 staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +&soc { + tgu@10b0e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b0e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@10b0f000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b0f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@10b10000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b10000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; From 0bcd2baad38ddebe6aa89583c8518e90397525cf Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 18 May 2026 14:21:04 +0800 Subject: [PATCH 0992/1330] PENDING: arm64: dts: qcom: kaanapali: add TGU in staging dtso Add TGU devices for supporting IPCB feature in staging dtso file. Signed-off-by: Jie Gan (cherry picked from commit c6232b6ea8c849e2af086b9c4449c88988c581d5) --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/kaanapali-staging.dtso | 43 +++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kaanapali-staging.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f0377f51a4977..bccb6cede6746 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -578,3 +578,5 @@ dtb-$(CONFIG_ARCH_QCOM) += glymur-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += sm8750-staging.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += kaanapali-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/kaanapali-staging.dtso b/arch/arm64/boot/dts/qcom/kaanapali-staging.dtso new file mode 100644 index 0000000000000..d7a5b0b084872 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-staging.dtso @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Kaanapali staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +&soc { + tgu@11301000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x11301000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@1130e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x1130e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@1130f000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x1130f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@11310000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x11310000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; From 90886fc7ae8336156ae44b0cc2cd49c8e5e33198 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Wed, 15 Apr 2026 12:10:46 +0530 Subject: [PATCH 0993/1330] FROMLIST: arm64: dts: qcom: monaco: add GDSP fastrpc-compute-cb nodes Add GDSP fastrpc compute-cb nodes for monaco SoC. Link: https://lore.kernel.org/all/20260415-monacogdsp-v1-1-077ded36c7fc@oss.qualcomm.com/ Signed-off-by: Ekansh Gupta Reviewed-by: Konrad Dybcio Signed-off-by: Vinayak Katoch (cherry picked from commit ffd35fec5e1b2ef8197f59f8bdfbcdd9f1931df6) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index bc7fe82e236c0..a67d95a70ecef 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -7658,6 +7658,35 @@ label = "gpdsp"; qcom,remote-pid = <17>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "gdsp0"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x28a1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x28a2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x28a3 0x0>; + dma-coherent; + }; + }; }; }; From 4c125c85f3316347b86b38605a99bea50ce54182 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 15 May 2026 00:31:40 +0530 Subject: [PATCH 0994/1330] FROMLIST: arm64: dts: qcom: shikra: Add qcrypto node support Add qcrypto and cryptobam support for shikra target. Link: https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-3-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh (cherry picked from commit e40dfa6dc3f7d594719a862aac0b8b876dd8a692) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 9a27b9ee5c15c..1bcb2c269bb48 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -955,6 +955,41 @@ #interconnect-cells = <2>; }; + cryptobam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01b04000 0x0 0x24000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu 0x84 0x0011>, + <&apps_smmu 0x86 0x0011>, + <&apps_smmu 0x92 0x0>, + <&apps_smmu 0x94 0x0011>, + <&apps_smmu 0x96 0x0011>, + <&apps_smmu 0x98 0x0001>, + <&apps_smmu 0x9F 0x0>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <16>; + qcom,num-ees = <4>; + }; + + crypto: crypto@1b3a000 { + compatible = "qcom,shikra-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01b3a000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x84 0x0011>, + <&apps_smmu 0x86 0x0011>, + <&apps_smmu 0x92 0x0>, + <&apps_smmu 0x94 0x0011>, + <&apps_smmu 0x96 0x0011>, + <&apps_smmu 0x98 0x0001>, + <&apps_smmu 0x9F 0x0>; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 0 + &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "memory"; + }; + qfprom: efuse@1b40000 { compatible = "qcom,shikra-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; From aa5f70df507e1dd66189aeb8167ab3c36534c361 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 14 May 2026 18:29:49 +0530 Subject: [PATCH 0995/1330] FROMLIST: arm64: dts: qcom: shikra: Add TRNG support Add True Random Number Generator(TRNG) node for shikra. Link: https://lore.kernel.org/lkml/20260514-shikra_rng-v1-2-4ea721a1429a@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh (cherry picked from commit f338615753fcafae4139e0102482e21b2ed8931b) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 1bcb2c269bb48..ad82e80f8e58f 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1041,6 +1041,11 @@ #thermal-sensor-cells = <1>; }; + rng: rng@4454000 { + compatible = "qcom,shikra-trng", "qcom,trng"; + reg = <0 0x04454000 0 0x1000>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x0 0x045f0000 0x0 0x7000>; From 8ab3aaaa714179aa4a211dc2c2d7032c3c9eb665 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 13 May 2026 18:10:02 +0530 Subject: [PATCH 0996/1330] FROMLIST: arm64: dts: qcom: shikra: Enable ice support Add UFS inline crypto engine(ICE) support for shikra. Link: https://lore.kernel.org/lkml/20260515-shikra_ice_ufs-v1-2-b1b6ced70559@oss.qualcomm.com Signed-off-by: Kuldeep Singh (cherry picked from commit 3f93bc1b28abbe7b28b2510ea80b8d8976ca59b8) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index ad82e80f8e58f..45d10d4fa7727 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1107,6 +1107,7 @@ mmc-hs400-enhanced-strobe; resets = <&gcc GCC_SDCC1_BCR>; + qcom,ice = <&sdhc_ice>; status = "disabled"; @@ -1788,6 +1789,17 @@ iommus = <&apps_smmu 0xf6 0x0>; }; + sdhc_ice: crypto@4748000 { + compatible = "qcom,shikra-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x04748000 0x0 0x18000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&rpmpd RPMHPD_CX>; + }; + qupv3_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x04ac0000 0x0 0x2000>; From 5bf52950b2f09c729fb3549bc82f575221f87dc7 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Thu, 14 May 2026 16:35:39 +0530 Subject: [PATCH 0997/1330] arm64: dts: qcom: shikra: Add pm4125 s1 regulator Add pm4125_s1 regulator node at fixed 1.396V to both shikra-cqm-som and shikra-cqs-som. This rail is used by the audio subsystem. Signed-off-by: Rakesh Kota (cherry picked from commit 177f6d9fc4c818f0fb5b539d3a807d6a8eb32566) --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 5 +++++ arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 107dcb442f0d8..047e93245def4 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -176,6 +176,11 @@ regulators { compatible = "qcom,rpm-pm2250-regulators"; + pm4125_s1: s1 { + regulator-min-microvolt = <1396000>; + regulator-max-microvolt = <1396000>; + }; + pm4125_s2: s2 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi index 8094df7e607e1..89580d7699118 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi @@ -177,6 +177,11 @@ regulators { compatible = "qcom,rpm-pm2250-regulators"; + pm4125_s1: s1 { + regulator-min-microvolt = <1396000>; + regulator-max-microvolt = <1396000>; + }; + pm4125_s2: s2 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; From b9ae9dd8a2cc00ff2155920a30396ac82b1db817 Mon Sep 17 00:00:00 2001 From: Yepuri Siddu Date: Thu, 14 May 2026 20:08:12 +0530 Subject: [PATCH 0998/1330] arm64: dts: qcom: Add dedicated BT 3.3V dummy regulator. Add a separate fixed dummy regulator for Bluetooth. Signed-off-by: Yepuri Siddu (cherry picked from commit 9dced9856a781eeb7871c3eb54ce20c0a30d7bc4) --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index fb60b0a5ba0ab..63136008f410b 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -34,6 +34,14 @@ regulator-always-on; }; }; + + vreg_bt_3p3_dummy: regulator-bt-3p3-dummy { + compatible = "regulator-fixed"; + regulator-name = "bt_3p3_dummy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &remoteproc_cdsp { @@ -92,7 +100,7 @@ vddio-supply = <&pm8150_s4>; vddxo-supply = <&pm8150_l12>; vddrf-supply = <&pm8150_l8>; - vddch0-supply = <&vreg_wlan_3p3_dummy>; + vddch0-supply = <&vreg_bt_3p3_dummy>; }; }; From c02b2a7316b258c9bbdceba8cebf2f6a6df9ec15 Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Fri, 15 May 2026 15:09:42 +0530 Subject: [PATCH 0999/1330] arm64: dts: qcom: shikra-cqs-evk: Enable display Enable the DLC0697 MIPI DSI display panel on the Shikra CQS EVK. Signed-off-by: Mahadevan P (cherry picked from commit aaca6ad047e95d1df41580246fbbf2f5b3da2be8) --- arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 95 ++++++++++++++++++++- 1 file changed, 92 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index d12c897a9e71f..41e77f0601ce6 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -24,12 +24,70 @@ chosen { stdout-path = "serial0:115200n8"; }; + + lcd_bias: regulator-lcd-bias { + compatible = "regulator-fixed"; + regulator-name = "lcd_bias"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pm4125_l17>; + gpio = <&tlmm 151 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_bias_en>; + pinctrl-names = "default"; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm4125_l5>; + status = "okay"; + + panel@0 { + compatible = "dlc,dlc0697"; + reg = <0>; + + reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&pm4125_l15>; + bias-supply = <&lcd_bias>; + + pinctrl-0 = <&panel_rst_n &panel_te_pin>; + pinctrl-1 = <&panel_rst_n_suspend>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; }; &pm4125_hs_in { remote-endpoint = <&usb_1_dwc3_hs>; }; +&pm4125_l5 { + /* DSI VDDA - must be at NOM voltage for PHY PLL lock */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + regulator-allow-set-load; +}; + &pm4125_ss_in { remote-endpoint = <&usb_qmpphy_out>; }; @@ -79,6 +137,36 @@ status = "okay"; }; +&tlmm { + lcd_bias_en: lcd-bias-en-state { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + panel_rst_n: panel-rst-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_rst_n_suspend: panel-rst-n-suspend-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + panel_te_pin: panel-te-pin-state { + pins = "gpio86"; + function = "mdp_vsync_p"; + drive-strength = <2>; + bias-pull-down; + }; +}; + &uart0 { status = "okay"; }; @@ -119,6 +207,10 @@ status = "okay"; }; +&usb_qmpphy_out { + remote-endpoint = <&pm4125_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; @@ -130,6 +222,3 @@ status = "okay"; }; -&usb_qmpphy_out { - remote-endpoint = <&pm4125_ss_in>; -}; From 600f3dcf2a5f2c6f29061dcb3934fd822d25192c Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 7 May 2026 14:04:46 +0530 Subject: [PATCH 1000/1330] arm64: dts: qcom: Add AudioCoreCC node support on Shikra Enable AudioCore Clock Controller (AudioCoreCC) support on Shikra platform. The Shikra CQM variant requires both clock and reset support, while the Shikra CQS variant requires only reset support. Hence, add support to configure the respective device tree nodes accordingly. Signed-off-by: Imran Shaik (cherry picked from commit 4458857fd79849d2e1b9895c437f28d70f50d9c6) --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi | 5 +++++ arch/arm64/boot/dts/qcom/shikra.dtsi | 13 +++++++++++++ 3 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 047e93245def4..03e04ce05efe1 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -53,6 +53,10 @@ }; }; +&audiocorecc { + status = "okay"; +}; + &pm4125_adc { pinctrl-0 = <&pm4125_adc_gpio5_default>, <&pm4125_adc_gpio6_default>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi index 89580d7699118..2c1788c3b88bd 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi @@ -54,6 +54,11 @@ }; }; +&audiocorecc { + compatible = "qcom,shikra-cqs-audiocorecc"; + status = "okay"; +}; + &pm4125_adc { pinctrl-0 = <&pm4125_adc_gpio5_default>, <&pm4125_adc_gpio6_default>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 45d10d4fa7727..f4ee08cf720a2 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -3797,6 +3798,18 @@ label = "cti_apss_2"; }; + audiocorecc: clock-controller@a0a0000 { + compatible = "qcom,shikra-cqm-audiocorecc"; + reg = <0x0 0x0a0a0000 0x0 0x10000>, + <0x0 0x0a0b4000 0x0 0x1000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + status = "disabled"; + }; + remoteproc_cdsp: remoteproc@b300000 { compatible = "qcom,shikra-cdsp-pas"; reg = <0x0 0x0b300000 0x0 0x100000>; From 9a038864182da873d27645433ae294b06591bef1 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 18 May 2026 11:42:17 +0530 Subject: [PATCH 1001/1330] arm64: dts: qcom: Fix pm4125 vbus regulator compatible and constraints Remove pm8150b fallback compatible from pm4125_vbus and fix regulator constraints in shikra SOM DTS files to use microvolt instead of microamp. Signed-off-by: Rakesh Kota (cherry picked from commit 919fd6caf1f2c9a69bf6edcb6acd24a592cd74e3) --- arch/arm64/boot/dts/qcom/pm4125.dtsi | 2 +- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm4125.dtsi b/arch/arm64/boot/dts/qcom/pm4125.dtsi index ad410b8c4f6be..ca900948c0b3e 100644 --- a/arch/arm64/boot/dts/qcom/pm4125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm4125.dtsi @@ -37,7 +37,7 @@ }; pm4125_vbus: usb-vbus-regulator@1100 { - compatible = "qcom,pm4125-vbus-reg", "qcom,pm8150b-vbus-reg"; + compatible = "qcom,pm4125-vbus-reg"; reg = <0x1100>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 03e04ce05efe1..1bf69cb7d1058 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -167,8 +167,8 @@ }; &pm4125_vbus { - regulator-min-microamp = <500000>; - regulator-max-microamp = <500000>; + regulator-min-microvolt = <4250000>; + regulator-max-microvolt = <5000000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi index 2c1788c3b88bd..e46dcf401d7c5 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-som.dtsi @@ -169,8 +169,8 @@ }; &pm4125_vbus { - regulator-min-microamp = <500000>; - regulator-max-microamp = <500000>; + regulator-min-microvolt = <4250000>; + regulator-max-microvolt = <5000000>; status = "okay"; }; From 2c7fe04d0037e55904f1b4cf927f1efcaf366968 Mon Sep 17 00:00:00 2001 From: Hangtian Zhu Date: Tue, 12 May 2026 10:17:08 +0800 Subject: [PATCH 1002/1330] FROMLIST: genirq: export irq_can_set_affinity() for module drivers Export irq_can_set_affinity() for loadable drivers that need a runtime check for IRQ affinity capability. In hierarchical IRQ setups where the effective irqchip path lacks .irq_set_affinity(), drivers may need to switch to a fallback policy. Without this export, module drivers cannot use the core helper and have to open-code equivalent checks. Signed-off-by: Hangtian Zhu Link: https://lore.kernel.org/all/20260519011627.713068-1-hangtian.zhu@oss.qualcomm.com/ (cherry picked from commit f5f5360ce89b10b08ae9371d74b5970a53e8ff4a) --- kernel/irq/manage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 2e80724378267..c3aa33ef4be90 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -171,6 +171,7 @@ int irq_can_set_affinity(unsigned int irq) { return __irq_can_set_affinity(irq_to_desc(irq)); } +EXPORT_SYMBOL_GPL(irq_can_set_affinity); /** * irq_can_set_affinity_usr - Check if affinity of a irq can be set from user space From 5d26cf4491f24a2e64368ae47ee6892ed2f95a58 Mon Sep 17 00:00:00 2001 From: Hangtian Zhu Date: Tue, 12 May 2026 10:17:08 +0800 Subject: [PATCH 1003/1330] FROMLIST: wifi: ath12k: enable threaded NAPI when DP IRQ affinity is unavailable Determine threaded NAPI policy from runtime IRQ capability of the DP MSI IRQ. If irq_can_set_affinity() reports that affinity cannot be set, enable threaded NAPI for DP interrupt groups so datapath processing is not constrained by a single-CPU softirq context. On RB3Gen2, where IRQ affinity is unavailable in the effective IRQ path, EHT160 UDP downlink throughput improved from 802 Mbps to 2.58 Gbps after enabling threaded NAPI. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0.c2-00074-QCACOLSWPL_V1_TO_SILICONZ-1 Signed-off-by: Hangtian Zhu Link: https://lore.kernel.org/all/20260519011627.713068-1-hangtian.zhu@oss.qualcomm.com/ (cherry picked from commit 850c3c0a83b47e345f1abf5bea36d21044da79cd) --- drivers/net/wireless/ath/ath12k/pci.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c index 9efc9396c90b7..3a61ace00db9c 100644 --- a/drivers/net/wireless/ath/ath12k/pci.c +++ b/drivers/net/wireless/ath/ath12k/pci.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -537,6 +538,8 @@ static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) int i, j, n, ret, num_vectors = 0; u32 user_base_data = 0, base_vector = 0, base_idx; struct ath12k_ext_irq_grp *irq_grp; + bool threaded_napi = false; + int irq; base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; ret = ath12k_pci_get_user_msi_assignment(ab, "DP", @@ -546,6 +549,10 @@ static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) if (ret < 0) return ret; + irq = ath12k_pci_get_msi_irq(ab->dev, base_vector); + if (irq >= 0) + threaded_napi = !irq_can_set_affinity(irq); + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { irq_grp = &ab->ext_irq_grp[i]; u32 num_irq = 0; @@ -560,6 +567,8 @@ static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) netif_napi_add(irq_grp->napi_ndev, &irq_grp->napi, ath12k_pci_ext_grp_napi_poll); + if (threaded_napi) + netif_threaded_enable(irq_grp->napi_ndev); if (ab->hw_params->ring_mask->tx[i] || ab->hw_params->ring_mask->rx[i] || @@ -578,7 +587,7 @@ static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) for (j = 0; j < irq_grp->num_irq; j++) { int irq_idx = irq_grp->irqs[j]; int vector = (i % num_vectors) + base_vector; - int irq = ath12k_pci_get_msi_irq(ab->dev, vector); + irq = ath12k_pci_get_msi_irq(ab->dev, vector); ab->irq_num[irq_idx] = irq; From 92324f2abcbcd74e72f57b06ec5043b1b0a03e36 Mon Sep 17 00:00:00 2001 From: Saurabh Anand Date: Fri, 15 May 2026 11:44:51 +0530 Subject: [PATCH 1004/1330] FROMLIST: arm64: dts: qcom: sm8750: allow mode-switch events to reach the QMP Combo PHY Allow mode-switch events to reach the QMP Combo PHY to support setting the QMP Combo PHY in DP 4Lanes Altmode. Signed-off-by: Saurabh Anand Link: https://lore.kernel.org/all/20260515071448.1845500-1-saurabh.anand@oss.qualcomm.com/ (cherry picked from commit 5f4b94d17978a8c5cf97ba76a3b45c26c59b6b12) --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 961342779e33f..6cf1f6cd31c85 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2796,6 +2796,7 @@ #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From 7595c57b9b4aade3c95a3d61be9d7af0c8f0d8d0 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 18 May 2026 15:26:51 +0800 Subject: [PATCH 1005/1330] PENDING: arm64: dts: qcom: glymur: add Coresight devices for APSS debug block Add the following devices that are part of the APSS debug block to enable debug features, including ETM, replicator, funnel, and TMC ETF. Signed-off-by: Jie Gan (cherry picked from commit bc664592261b19a8dac0e6ce3c3dd907a225b3e7) --- arch/arm64/boot/dts/qcom/glymur-staging.dtso | 1248 ++++++++++++++++++ 1 file changed, 1248 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-staging.dtso b/arch/arm64/boot/dts/qcom/glymur-staging.dtso index 0b95e568e1c00..eb928fca1a371 100644 --- a/arch/arm64/boot/dts/qcom/glymur-staging.dtso +++ b/arch/arm64/boot/dts/qcom/glymur-staging.dtso @@ -8,6 +8,315 @@ /dts-v1/; /plugin/; +&{/} { + ete-0 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&ncc0_0_rep_in>; + }; + }; + }; + }; + + ete-1 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&ncc0_1_rep_in>; + }; + }; + }; + }; + + ete-2 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&ncc0_2_rep_in>; + }; + }; + }; + }; + + ete-3 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&ncc0_3_rep_in>; + }; + }; + }; + }; + + ete-4 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&ncc0_4_rep_in>; + }; + }; + }; + }; + + ete-5 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&ncc0_5_rep_in>; + }; + }; + }; + }; + + ete-6 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&ncc1_0_rep_in>; + }; + }; + }; + }; + + ete-7 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&ncc1_1_rep_in>; + }; + }; + }; + }; + + ete-8 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu8>; + qcom,skip-power-up; + + out-ports { + port { + etm8_out: endpoint { + remote-endpoint = <&ncc1_2_rep_in>; + }; + }; + }; + }; + + ete-9 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu9>; + qcom,skip-power-up; + + out-ports { + port { + etm9_out: endpoint { + remote-endpoint = <&ncc1_3_rep_in>; + }; + }; + }; + }; + + ete-10 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu10>; + qcom,skip-power-up; + + out-ports { + port { + etm10_out: endpoint { + remote-endpoint = <&ncc1_4_rep_in>; + }; + }; + }; + }; + + ete-11 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu11>; + qcom,skip-power-up; + + out-ports { + port { + etm11_out: endpoint { + remote-endpoint = <&ncc1_5_rep_in>; + }; + }; + }; + }; + + ete-12 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu12>; + qcom,skip-power-up; + + out-ports { + port { + etm12_out: endpoint { + remote-endpoint = <&ncc2_0_rep_in>; + }; + }; + }; + }; + + ete-13 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu13>; + qcom,skip-power-up; + + out-ports { + port { + etm13_out: endpoint { + remote-endpoint = <&ncc2_1_rep_in>; + }; + }; + }; + }; + + ete-14 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu14>; + qcom,skip-power-up; + + out-ports { + port { + etm14_out: endpoint { + remote-endpoint = <&ncc2_2_rep_in>; + }; + }; + }; + }; + + ete-15 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu15>; + qcom,skip-power-up; + + out-ports { + port { + etm15_out: endpoint { + remote-endpoint = <&ncc2_3_rep_in>; + }; + }; + }; + }; + + ete-16 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu16>; + qcom,skip-power-up; + + out-ports { + port { + etm16_out: endpoint { + remote-endpoint = <&ncc2_4_rep_in>; + }; + }; + }; + }; + + ete-17 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + cpu = <&cpu17>; + qcom,skip-power-up; + + out-ports { + port { + etm17_out: endpoint { + remote-endpoint = <&ncc2_5_rep_in>; + }; + }; + }; + }; + +}; + &soc { ctcu@10001000 { compatible = "qcom,glymur-ctcu", "qcom,sa8775p-ctcu"; @@ -155,6 +464,21 @@ }; }; + tn@11200000 { + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@36 { + reg = <0x36>; + + tn_ag_in54: endpoint { + remote-endpoint = <&apss_funnel_out>; + }; + }; + }; + }; + tgu@11c02000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x11c02000 0x0 0x1000>; @@ -198,4 +522,928 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; + + apss_funnel: funnel@12080000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x12080000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + apss_funnel_in0: endpoint { + remote-endpoint = <&ncc0_etf_out>; + }; + }; + + port@1 { + reg = <1>; + + apss_funnel_in1: endpoint { + remote-endpoint = <&ncc1_etf_out>; + }; + }; + + port@2 { + reg = <2>; + + apss_funnel_in2: endpoint { + remote-endpoint = <&ncc2_etf_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = <&tn_ag_in54>; + }; + }; + }; + }; + + funnel@1d021000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x1d021000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + ncc0_2_funnel_in2: endpoint { + remote-endpoint = <&ncc0_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc0_2_funnel_out: endpoint { + remote-endpoint = <&ncc0_etf_in>; + }; + }; + }; + }; + + tmc@1d029000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x0 0x1d029000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_etf_in: endpoint { + remote-endpoint = <&ncc0_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc0_etf_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + funnel@1d081000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x1d081000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ncc0_1_funnel_in0: endpoint { + remote-endpoint = <&ncc0_0_rep_out>; + }; + }; + + port@1 { + reg = <1>; + + ncc0_1_funnel_in1: endpoint { + remote-endpoint = <&ncc0_1_rep_out>; + }; + }; + + port@2 { + reg = <2>; + + ncc0_1_funnel_in2: endpoint { + remote-endpoint = <&ncc0_2_rep_out>; + }; + }; + + port@3 { + reg = <3>; + + ncc0_1_funnel_in3: endpoint { + remote-endpoint = <&ncc0_3_rep_out>; + }; + }; + + port@4 { + reg = <4>; + + ncc0_1_funnel_in4: endpoint { + remote-endpoint = <&ncc0_4_rep_out>; + }; + }; + + port@5 { + reg = <5>; + + ncc0_1_funnel_in5: endpoint { + remote-endpoint = <&ncc0_5_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc0_1_funnel_out: endpoint { + remote-endpoint = <&ncc0_2_funnel_in2>; + }; + }; + }; + }; + + replicator@1d090000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d090000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_0_rep_in: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + }; + + out-ports { + port { + ncc0_0_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in0>; + }; + }; + }; + }; + + replicator@1d0a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d0a0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_1_rep_in: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; + + out-ports { + port { + ncc0_1_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in1>; + }; + }; + }; + }; + + replicator@1d0b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d0b0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_2_rep_in: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + }; + + out-ports { + port { + ncc0_2_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in2>; + }; + }; + }; + }; + + replicator@1d0c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d0c0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_3_rep_in: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + ncc0_3_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in3>; + }; + }; + }; + }; + + replicator@1d0d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d0d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_4_rep_in: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + }; + + out-ports { + port { + ncc0_4_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in4>; + }; + }; + }; + }; + + replicator@1d0e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d0e0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster0_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_5_rep_in: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + }; + + out-ports { + port { + ncc0_5_rep_out: endpoint { + remote-endpoint = <&ncc0_1_funnel_in5>; + }; + }; + }; + }; + + funnel@1d121000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x1d121000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + ncc1_2_funnel_in2: endpoint { + remote-endpoint = <&ncc1_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc1_2_funnel_out: endpoint { + remote-endpoint = <&ncc1_etf_in>; + }; + }; + }; + }; + + tmc@1d129000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x0 0x1d129000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_etf_in: endpoint { + remote-endpoint = <&ncc1_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc1_etf_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + funnel@1d181000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x1d181000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ncc1_1_funnel_in0: endpoint { + remote-endpoint = <&ncc1_0_rep_out>; + }; + }; + + port@1 { + reg = <1>; + + ncc1_1_funnel_in1: endpoint { + remote-endpoint = <&ncc1_1_rep_out>; + }; + }; + + port@2 { + reg = <2>; + + ncc1_1_funnel_in2: endpoint { + remote-endpoint = <&ncc1_2_rep_out>; + }; + }; + + port@3 { + reg = <3>; + + ncc1_1_funnel_in3: endpoint { + remote-endpoint = <&ncc1_3_rep_out>; + }; + }; + + port@4 { + reg = <4>; + + ncc1_1_funnel_in4: endpoint { + remote-endpoint = <&ncc1_4_rep_out>; + }; + }; + + port@5 { + reg = <5>; + + ncc1_1_funnel_in5: endpoint { + remote-endpoint = <&ncc1_5_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc1_1_funnel_out: endpoint { + remote-endpoint = <&ncc1_2_funnel_in2>; + }; + }; + }; + }; + + replicator@1d190000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d190000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_0_rep_in: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + }; + + out-ports { + port { + ncc1_0_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in0>; + }; + }; + }; + }; + + replicator@1d1a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d1a0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_1_rep_in: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + + out-ports { + port { + ncc1_1_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in1>; + }; + }; + }; + }; + + replicator@1d1b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d1b0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_2_rep_in: endpoint { + remote-endpoint = <&etm8_out>; + }; + }; + }; + + out-ports { + port { + ncc1_2_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in2>; + }; + }; + }; + }; + + replicator@1d1c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d1c0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_3_rep_in: endpoint { + remote-endpoint = <&etm9_out>; + }; + }; + }; + + out-ports { + port { + ncc1_3_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in3>; + }; + }; + }; + }; + + replicator@1d1d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d1d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_4_rep_in: endpoint { + remote-endpoint = <&etm10_out>; + }; + }; + }; + + out-ports { + port { + ncc1_4_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in4>; + }; + }; + }; + }; + + replicator@1d1e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d1e0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster1_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_5_rep_in: endpoint { + remote-endpoint = <&etm11_out>; + }; + }; + }; + + out-ports { + port { + ncc1_5_rep_out: endpoint { + remote-endpoint = <&ncc1_1_funnel_in5>; + }; + }; + }; + }; + + funnel@1d221000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x1d221000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + ncc2_2_funnel_in2: endpoint { + remote-endpoint = <&ncc2_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc2_2_funnel_out: endpoint { + remote-endpoint = <&ncc2_etf_in>; + }; + }; + }; + }; + + tmc@1d229000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x0 0x1d229000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_etf_in: endpoint { + remote-endpoint = <&ncc2_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc2_etf_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + funnel@1d281000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x0 0x1d281000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ncc2_1_funnel_in0: endpoint { + remote-endpoint = <&ncc2_0_rep_out>; + }; + }; + + port@1 { + reg = <1>; + + ncc2_1_funnel_in1: endpoint { + remote-endpoint = <&ncc2_1_rep_out>; + }; + }; + + port@2 { + reg = <2>; + + ncc2_1_funnel_in2: endpoint { + remote-endpoint = <&ncc2_2_rep_out>; + }; + }; + + port@3 { + reg = <3>; + + ncc2_1_funnel_in3: endpoint { + remote-endpoint = <&ncc2_3_rep_out>; + }; + }; + + port@4 { + reg = <4>; + + ncc2_1_funnel_in4: endpoint { + remote-endpoint = <&ncc2_4_rep_out>; + }; + }; + + port@5 { + reg = <5>; + + ncc2_1_funnel_in5: endpoint { + remote-endpoint = <&ncc2_5_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc2_1_funnel_out: endpoint { + remote-endpoint = <&ncc2_2_funnel_in2>; + }; + }; + }; + }; + + replicator@1d290000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d290000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_0_rep_in: endpoint { + remote-endpoint = <&etm12_out>; + }; + }; + }; + + out-ports { + port { + ncc2_0_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in0>; + }; + }; + }; + }; + + replicator@1d2a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d2a0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_1_rep_in: endpoint { + remote-endpoint = <&etm13_out>; + }; + }; + }; + + out-ports { + port { + ncc2_1_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in1>; + }; + }; + }; + }; + + replicator@1d2b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d2b0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_2_rep_in: endpoint { + remote-endpoint = <&etm14_out>; + }; + }; + }; + + out-ports { + port { + ncc2_2_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in2>; + }; + }; + }; + }; + + replicator@1d2c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d2c0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_3_rep_in: endpoint { + remote-endpoint = <&etm15_out>; + }; + }; + }; + + out-ports { + port { + ncc2_3_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in3>; + }; + }; + }; + }; + + replicator@1d2d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d2d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_4_rep_in: endpoint { + remote-endpoint = <&etm16_out>; + }; + }; + }; + + out-ports { + port { + ncc2_4_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in4>; + }; + }; + }; + }; + + replicator@1d2e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x0 0x1d2e0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + power-domains = <&cluster2_pd>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_5_rep_in: endpoint { + remote-endpoint = <&etm17_out>; + }; + }; + }; + + out-ports { + port { + ncc2_5_rep_out: endpoint { + remote-endpoint = <&ncc2_1_funnel_in5>; + }; + }; + }; + }; }; From b31fa873cb1284d7a9bb29ca01a635a20c88a8dd Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Tue, 19 May 2026 13:34:46 +0530 Subject: [PATCH 1006/1330] WORKAROUND:arm64: dts: glymur-crd: Reset gpio added to touchscreen node Reset gpio added to touchscreen Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 29aa2aba8e767e1057666a6483923c8da2edd816) --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index d35530ed09df5..e80990181f74a 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -667,6 +667,9 @@ vdd-supply = <&vreg_misc_3p3>; vddl-supply = <&vreg_l15b_e0_1p8>; + reset-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + pinctrl-0 = <&ts0_default>; pinctrl-names = "default"; }; From 9a79ddf95a74adbc8127fc45cf6be5a95449a5d2 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 4 May 2026 17:37:47 +0530 Subject: [PATCH 1007/1330] FROMLIST: arm64: dts: qcom: sm8750: wire UFS to ice instance The Inline Crypto Engine (ICE) exists as a standalone DT node, but the UFS node lacks the required qcom,ice phandle reference. Add the qcom,ice property to explicitly associate the UFS controller with its ICE instance. Fixes: d288abc3a70e ("arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC") Signed-off-by: Kuldeep Singh Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/lkml/20260429-sm8750_ice_dt_fix-v1-1-2540dc337082@oss.qualcomm.com/ Signed-off-by: Kumar Kartik (cherry picked from commit fee7c34a4bbc61e8af1b65b450337beca2396f27) --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 6cf1f6cd31c85..bb7a8bfb05561 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5579,6 +5579,7 @@ phy-names = "ufsphy"; #reset-cells = <1>; + qcom,ice = <&ice>; status = "disabled"; From 5e79e90aca398b205b1860ad45764bb63e784e33 Mon Sep 17 00:00:00 2001 From: Raj Aryan Date: Mon, 20 Apr 2026 10:27:00 +0530 Subject: [PATCH 1008/1330] FROMLIST: soc: qcom: spmi-pmic: add SUBTYPEs for Glymur/Kaanapali/SM8750 PMICs On Glymur, Kaanapali, and SM8750, PMIC info is not being properly populated in qcom_socinfo. Its shows `unknown` as PMIC subtypes are not updated in the socinfo. root@glymur-crd:/sys/kernel/debug/qcom_socinfo# cat pmic_model unknown (92) root@glymur-crd:/sys/kernel/debug/qcom_socinfo# cat pmic_model_array unknown (92) unknown (93) unknown (98) unknown (98) unknown (97) unknown (97) unknown (96) unknown (96) Update the SUBTYPE info for PMICs present on Glymur,Kaanapali and SM8750 boards, to fix this issue. Also, there are some PMIC subtypes present in the socinfo but not present in the spmi header file, add these entries to keep both definitions aligned. Link: https://lore.kernel.org/all/20260507-fury-v1-1-d24e4bb5b774@qti.qualcomm.com/ Signed-off-by: Raj Aryan (cherry picked from commit 0ce73133945c15ce77f08151f682b00557217455) --- drivers/soc/qcom/socinfo.c | 8 ++++++++ include/soc/qcom/qcom-spmi-pmic.h | 15 ++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 17bc07f9aaf6d..24c18c72e98b6 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -187,7 +187,15 @@ static const char *const pmic_models[] = { [80] = "PM7550", [82] = "PMC8380", [83] = "SMB2360", + [86] = "PM8750B", + [87] = "PMD8028", [91] = "PMIV0108", + [92] = "PMK8850", + [93] = "PMH0101", + [95] = "SMB2370", + [96] = "PMH0104", + [97] = "PMH0110", + [98] = "PMCX0102", }; struct socinfo_params { diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h index 2cf9e2d8cd55f..997fa18d70fe8 100644 --- a/include/soc/qcom/qcom-spmi-pmic.h +++ b/include/soc/qcom/qcom-spmi-pmic.h @@ -50,9 +50,22 @@ #define PMR735B_SUBTYPE 0x34 #define PM6350_SUBTYPE 0x36 #define PM4125_SUBTYPE 0x37 +#define PM8010_SUBTYPE 0x41 +#define PM8550VS_SUBTYPE 0x45 +#define PM8550VE_SUBTYPE 0x46 +#define PMR735D_SUBTYPE 0x48 +#define PM8550_SUBTYPE 0x49 +#define PMK8550_SUBTYPE 0x4a #define PMM8650AU_SUBTYPE 0x4e #define PMM8650AU_PSAIL_SUBTYPE 0x4f - +#define PM8750B_SUBTYPE 0x56 +#define PMD8028_SUBTYPE 0x57 +#define PMK8850_SUBTYPE 0x5c +#define PMH0101_SUBTYPE 0x5d +#define SMB2370_SUBTYPE 0x5f +#define PMH0104_SUBTYPE 0x60 +#define PMH0110_SUBTYPE 0x61 +#define PMCX0102_SUBTYPE 0x62 #define PMI8998_FAB_ID_SMIC 0x11 #define PMI8998_FAB_ID_GF 0x30 From b01417935cdfa3738c05d5fdae413e1f09ef1a05 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 19 May 2026 16:19:49 +0530 Subject: [PATCH 1009/1330] FROMLIST: dt-bindings: power: limits: Describe Qualcomm SPEL hardware The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware based power monitoring and limiting capabilities for various domains. Add a DeviceTree binding to describe the SPEL block on Qualcomm's SoC. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://patch.msgid.link/20260519-qcom_spel_driver_upstream-v1-1-75356d1b7f94@oss.qualcomm.com (cherry picked from commit 086796ef8d7ec36f6493883d706a0b8f621b07a5) --- .../bindings/power/limits/qcom,spel.yaml | 47 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/limits/qcom,spel.yaml diff --git a/Documentation/devicetree/bindings/power/limits/qcom,spel.yaml b/Documentation/devicetree/bindings/power/limits/qcom,spel.yaml new file mode 100644 index 0000000000000..e9bb70c3a3aa4 --- /dev/null +++ b/Documentation/devicetree/bindings/power/limits/qcom,spel.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/limits/qcom,spel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoC Power and Electrical Limits (SPEL) + +maintainers: + - Manaf Meethalavalappu Pallikunhi + +description: + The Qualcomm SPEL (SoC Power and Electrical Limits) provides hardware-based + power monitoring and limiting capabilities for various power domains in + Qualcomm SoCs. + +properties: + compatible: + const: qcom,spel + + reg: + maxItems: 3 + + reg-names: + items: + - const: nodes + - const: constraints + - const: config + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + power-controller@ef3b000 { + compatible = "qcom,spel"; + reg = <0x0ef3e000 0x1000>, + <0x0ef3d000 0x1000>, + <0x0ef3b000 0x1000>; + reg-names = "nodes", + "constraints", + "config"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index b532de78a5aeb..2054f89289d01 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21902,6 +21902,12 @@ S: Maintained F: Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml F: drivers/power/supply/qcom_smbx.c +QUALCOMM SPEL POWERCAP DRIVER +M: Manaf Meethalavalappu Pallikunhi +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/power/limits/qcom,spel.yaml + QUALCOMM PPE DRIVER M: Luo Jie L: netdev@vger.kernel.org From 95632bf05626088009f51d5228a44153ea256404 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 19 May 2026 16:19:50 +0530 Subject: [PATCH 1010/1330] FROMLIST: powercap: qcom: Add SPEL powercap driver The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware based power monitoring and limiting capabilities for various power domains including System, SoC, CPU clusters, GPU, and various other subsystems. The driver integrates with the Linux powercap framework, exposing SPEL capabilities through powercap sysfs interfaces. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://patch.msgid.link/20260519-qcom_spel_driver_upstream-v1-2-75356d1b7f94@oss.qualcomm.com (cherry picked from commit 3f033cbfa8a76a10568dbbe3d1699852f6288851) --- MAINTAINERS | 1 + drivers/powercap/Kconfig | 13 + drivers/powercap/Makefile | 1 + drivers/powercap/qcom_spel.c | 787 +++++++++++++++++++++++++++++++++++ 4 files changed, 802 insertions(+) create mode 100644 drivers/powercap/qcom_spel.c diff --git a/MAINTAINERS b/MAINTAINERS index 2054f89289d01..d10d5ccdb5e60 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21907,6 +21907,7 @@ M: Manaf Meethalavalappu Pallikunhi L: linux-arm-msm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/power/limits/qcom,spel.yaml +F: drivers/powercap/qcom_spel.c QUALCOMM PPE DRIVER M: Luo Jie diff --git a/drivers/powercap/Kconfig b/drivers/powercap/Kconfig index 03c4c796d9931..e3a47c6534999 100644 --- a/drivers/powercap/Kconfig +++ b/drivers/powercap/Kconfig @@ -93,4 +93,17 @@ config DTPM_DEVFREQ help This enables support for device power limitation based on energy model. + +config QCOM_SPEL + tristate "Qualcomm SPEL Powercap driver" + depends on ARM64 || COMPILE_TEST + help + This enables support for the Qualcomm SoC Power and Electrical + Limits (SPEL) hardware, which allows power limits to be + enforced and monitored on Qualcomm SoCs. + + SPEL provides energy monitoring and power capping for multiple + domains including system, SoC, CPU clusters, GPU, and various + other subsystems. + endif diff --git a/drivers/powercap/Makefile b/drivers/powercap/Makefile index 5ab0dce565b9a..8235fb9d3df60 100644 --- a/drivers/powercap/Makefile +++ b/drivers/powercap/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_INTEL_RAPL) += intel_rapl_msr.o obj-$(CONFIG_INTEL_RAPL_TPMI) += intel_rapl_tpmi.o obj-$(CONFIG_IDLE_INJECT) += idle_inject.o obj-$(CONFIG_ARM_SCMI_POWERCAP) += arm_scmi_powercap.o +obj-$(CONFIG_QCOM_SPEL) += qcom_spel.o diff --git a/drivers/powercap/qcom_spel.c b/drivers/powercap/qcom_spel.c new file mode 100644 index 0000000000000..fed5647959a53 --- /dev/null +++ b/drivers/powercap/qcom_spel.c @@ -0,0 +1,787 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Qualcomm SPEL (SoC Power and Electrical Limits) Driver + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SPEL register bitmasks */ +#define ENERGY_STATUS_MASK 0xFFFFFFFF + +#define POWER_LIMIT_MASK 0x00007FFF +#define POWER_LIMIT_ENABLE BIT(31) + +#define TIME_WINDOW_MASK_L 0x00007FFF /* bits [14:0] */ +#define TIME_WINDOW_MASK_H 0x007F0000 /* bits [22:16] */ + +#define ENERGY_UNIT_OFFSET 16 +#define ENERGY_UNIT_MASK 0xF0000 + +#define TIME_UNIT_OFFSET 8 +#define TIME_UNIT_MASK 0xF00 + +#define POWER_UNIT_OFFSET 0 +#define POWER_UNIT_MASK 0x7 + +#define LIMITS_CAPABILITY_OFFSET 0x20 +#define ENERGY_RPT_UNIT_OFFSET 0x04 + +#define ENERGY_UNIT_SCALE 1000 + +#define SPEL_DOMAIN_NAME_LENGTH 16 + +/* Domain types */ +enum spel_domain_type { + SPEL_DOMAIN_SYS, + SPEL_DOMAIN_SOC, + SPEL_DOMAIN_CL0, + SPEL_DOMAIN_CL1, + SPEL_DOMAIN_CL2, + SPEL_DOMAIN_IGPU, + SPEL_DOMAIN_DGPU, + SPEL_DOMAIN_NSP, + SPEL_DOMAIN_MMCX, + SPEL_DOMAIN_INFRA, + SPEL_DOMAIN_DRAM, + SPEL_DOMAIN_MDM, + SPEL_DOMAIN_WLAN, + SPEL_DOMAIN_USB1, + SPEL_DOMAIN_USB2, + SPEL_DOMAIN_USB3, + SPEL_DOMAIN_MAX, +}; + +/* Power limit IDs */ +enum spel_power_limit_id { + POWER_LIMIT1, + POWER_LIMIT2, + POWER_LIMIT3, + POWER_LIMIT4, + NR_POWER_LIMITS, +}; + +/* Unit types for conversion */ +enum unit_type { + POWER_UNIT, + ENERGY_UNIT, + TIME_UNIT, +}; + +/* Power limit operation types */ +enum pl_ops_type { + PL_LIMIT, + PL_TIME_WINDOW, +}; + +static const char *pl_names[NR_POWER_LIMITS] = { + [POWER_LIMIT1] = "pl1", + [POWER_LIMIT2] = "pl2", + [POWER_LIMIT3] = "pl3", + [POWER_LIMIT4] = "pl4", +}; + +static const char *const spel_domain_names[] = { + "sys", "soc", "cl0", "cl1", "cl2", "igpu", "dgpu", "nsp", + "mmcx", "infra", "dram", "mdm", "wlan", "usb1", "usb2", "usb3", +}; + +/* Domain register offsets in node base */ +static const u32 domain_offsets[SPEL_DOMAIN_MAX] = { + [SPEL_DOMAIN_SYS] = 0x40, + [SPEL_DOMAIN_SOC] = 0x00, + [SPEL_DOMAIN_CL0] = 0x5C, + [SPEL_DOMAIN_CL1] = 0x60, + [SPEL_DOMAIN_CL2] = 0x64, + [SPEL_DOMAIN_IGPU] = 0x08, + [SPEL_DOMAIN_DGPU] = 0x44, + [SPEL_DOMAIN_NSP] = 0x0C, + [SPEL_DOMAIN_MMCX] = 0x10, + [SPEL_DOMAIN_INFRA] = 0x18, + [SPEL_DOMAIN_DRAM] = 0x1C, + [SPEL_DOMAIN_MDM] = 0x48, + [SPEL_DOMAIN_WLAN] = 0x4C, + [SPEL_DOMAIN_USB1] = 0x50, + [SPEL_DOMAIN_USB2] = 0x54, + [SPEL_DOMAIN_USB3] = 0x58, +}; + +/** + * struct spel_constraint_info - Power limit constraint information + * @limit_offset: Register offset for power limit value + * @time_window_offset: Register offset for time window + * @supported_mask: Bit mask in capability register + * @domain_id: Domain this constraint applies to + * @pl_id: Power limit ID (PL1, PL2, etc.) + */ +struct spel_constraint_info { + u32 limit_offset; + u32 time_window_offset; + u32 supported_mask; + enum spel_domain_type domain_id; + int pl_id; +}; + +/* Constraint configuration */ +static struct spel_constraint_info constraints[] = { + /* SYS domain constraints */ + { 0x10, 0x70, BIT(0), SPEL_DOMAIN_SYS, POWER_LIMIT1 }, + { 0x14, 0x74, BIT(1), SPEL_DOMAIN_SYS, POWER_LIMIT2 }, + { 0x18, 0x78, BIT(2), SPEL_DOMAIN_SYS, POWER_LIMIT3 }, + { 0x1C, 0x7C, BIT(3), SPEL_DOMAIN_SYS, POWER_LIMIT4 }, + /* SOC domain constraints */ + { 0x00, 0x60, BIT(4), SPEL_DOMAIN_SOC, POWER_LIMIT1 }, + { 0x04, 0x64, BIT(5), SPEL_DOMAIN_SOC, POWER_LIMIT2 }, + { 0x08, 0x68, BIT(6), SPEL_DOMAIN_SOC, POWER_LIMIT3 }, + { 0x0C, 0x6C, BIT(7), SPEL_DOMAIN_SOC, POWER_LIMIT4 }, +}; + +struct spel_system; + +/** + * struct spel_domain - SPEL power domain + * @power_zone: Powercap zone + * @lock: Mutex protecting register access + * @sp: Parent system + * @status_reg: Energy counter register + * @pl_name: Power limit names + * @name: Domain name + * @id: Domain type ID + */ +struct spel_domain { + struct powercap_zone power_zone; + struct mutex lock; /* Protects register read/write operations */ + struct spel_system *sp; + void __iomem *status_reg; + const char *pl_name[NR_POWER_LIMITS]; + char name[SPEL_DOMAIN_NAME_LENGTH]; + enum spel_domain_type id; +}; + +/** + * struct spel_system - SPEL system + * @domains: Array of domains + * @power_zone: Parent powercap zone + * @node_base: Base address for node registers + * @constraint_base: Base address for constraint registers + * @config_base: Base address for config registers + * @control_type: Powercap control type + * @dev: Device pointer for logging + * @limits: Supported power limits per domain + * @power_unit: Power unit in microWatts (common for all domains) + * @energy_unit: Energy unit in nanoJoules (common for all domains) + * @time_unit: Time unit in microseconds (common for all domains) + */ +struct spel_system { + struct spel_domain *domains; + struct powercap_zone *power_zone; + void __iomem *node_base; + void __iomem *constraint_base; + void __iomem *config_base; + struct powercap_control_type *control_type; + struct device *dev; + int limits[SPEL_DOMAIN_MAX]; + unsigned int power_unit; + unsigned int energy_unit; + unsigned int time_unit; +}; + +#define power_zone_to_spel_domain(_zone) \ + container_of(_zone, struct spel_domain, power_zone) + +/* Helper functions */ +static bool is_pl_valid(struct spel_domain *sd, int pl) +{ + if (pl < POWER_LIMIT1 || pl >= NR_POWER_LIMITS) + return false; + return sd->pl_name[pl] ? true : false; +} + +static int get_pl_ops_offset(struct spel_domain *sd, int pl, enum pl_ops_type pl_op) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(constraints); i++) { + struct spel_constraint_info *ci = &constraints[i]; + + if (ci->domain_id == sd->id && ci->pl_id == pl) { + switch (pl_op) { + case PL_LIMIT: + return ci->limit_offset; + case PL_TIME_WINDOW: + return ci->time_window_offset; + default: + return -EOPNOTSUPP; + } + } + } + + return -EOPNOTSUPP; +} + +static u64 spel_unit_xlate(struct spel_domain *sd, enum unit_type type, + u64 value, int to_raw) +{ + struct spel_system *sp = sd->sp; + u64 units = 1; + u64 scale = 1; + + switch (type) { + case POWER_UNIT: + units = sp->power_unit; + break; + case ENERGY_UNIT: + scale = ENERGY_UNIT_SCALE; + units = sp->energy_unit; + break; + case TIME_UNIT: + units = sp->time_unit; + break; + default: + return value; + } + + if (to_raw) + return div64_u64(value * scale, units); + + value *= units; + return div64_u64(value, scale); +} + +/* Power limit data access */ +static int spel_read_pl_data(struct spel_domain *sd, int pl, + enum pl_ops_type pl_op, bool xlate, u64 *data) +{ + struct spel_system *sp = sd->sp; + void __iomem *reg_addr; + u64 value; + int offset; + + if (!is_pl_valid(sd, pl)) + return -EINVAL; + + offset = get_pl_ops_offset(sd, pl, pl_op); + if (offset < 0) + return offset; + + guard(mutex)(&sd->lock); + + reg_addr = sp->constraint_base + offset; + value = readl(reg_addr); + + switch (pl_op) { + case PL_LIMIT: + value &= POWER_LIMIT_MASK; + if (xlate) + *data = spel_unit_xlate(sd, POWER_UNIT, value, 0); + else + *data = value; + break; + case PL_TIME_WINDOW: + /* Decode time window: bits [22:16] are upper 7 bits, [14:0] are lower 15 bits */ + value = ((value & TIME_WINDOW_MASK_H) >> 16 << 15) | + (value & TIME_WINDOW_MASK_L); + if (xlate) + *data = spel_unit_xlate(sd, TIME_UNIT, value, 0); + else + *data = value; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int spel_write_pl_data(struct spel_domain *sd, int pl, + enum pl_ops_type pl_op, unsigned long long value) +{ + struct spel_system *sp = sd->sp; + void __iomem *reg_addr; + u64 reg_val, new_val; + int offset; + + if (!is_pl_valid(sd, pl)) + return -EINVAL; + + offset = get_pl_ops_offset(sd, pl, pl_op); + if (offset < 0) + return offset; + + guard(mutex)(&sd->lock); + + reg_addr = sp->constraint_base + offset; + reg_val = readl(reg_addr); + + switch (pl_op) { + case PL_LIMIT: + new_val = spel_unit_xlate(sd, POWER_UNIT, value, 1); + if (new_val > POWER_LIMIT_MASK) + return -EINVAL; + reg_val = (reg_val & ~POWER_LIMIT_MASK) | new_val; + + /* + * Enable/Disable PL based on the value: + * - If value is 0, disable the PL (clear enable bit) + * - If value is non-zero, enable the PL (set enable bit) + */ + if (new_val == 0) + reg_val &= ~POWER_LIMIT_ENABLE; + else + reg_val |= POWER_LIMIT_ENABLE; + break; + case PL_TIME_WINDOW: + /* + * Encode time window: upper 7 bits to [22:16], lower 15 bits to [14:0] + * Time window register is separate from limit register (different offset), + * so we write only the time window bits without preserving any enable bit. + */ + new_val = spel_unit_xlate(sd, TIME_UNIT, value, 1); + reg_val = (((new_val >> 15) & 0x7F) << 16) | + (new_val & 0x7FFF); + break; + default: + return -EINVAL; + } + + writel(reg_val, reg_addr); + return 0; +} + +/* Powercap zone operations */ +static int spel_get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + u64 value; + + value = readl(sd->status_reg); + *energy_raw = spel_unit_xlate(sd, ENERGY_UNIT, value, 0); + + return 0; +} + +static int spel_get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) +{ + struct spel_domain *sd = power_zone_to_spel_domain(pcd_dev); + + *energy = spel_unit_xlate(sd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); + return 0; +} + +static int spel_release_zone(struct powercap_zone *power_zone) +{ + return 0; +} + +static int spel_find_nr_power_limit(struct spel_domain *sd) +{ + int i, nr_pl = 0; + + for (i = 0; i < NR_POWER_LIMITS; i++) { + if (is_pl_valid(sd, i)) + nr_pl++; + } + + return nr_pl; +} + +static const struct powercap_zone_ops zone_ops = { + .get_energy_uj = spel_get_energy_counter, + .get_max_energy_range_uj = spel_get_max_energy_counter, + .release = spel_release_zone, +}; + +/* Constraint operations */ +static int spel_constraint_to_pl(struct spel_domain *sd, int cid) +{ + int i, j; + + for (i = POWER_LIMIT1, j = 0; i < NR_POWER_LIMITS; i++) { + if (is_pl_valid(sd, i) && j++ == cid) + return i; + } + + return -EINVAL; +} + +static int spel_set_power_limit(struct powercap_zone *power_zone, int cid, + u64 power_limit) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + int id; + + id = spel_constraint_to_pl(sd, cid); + if (id < 0) + return id; + + return spel_write_pl_data(sd, id, PL_LIMIT, power_limit); +} + +static int spel_get_power_limit(struct powercap_zone *power_zone, int cid, + u64 *data) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + u64 val; + int ret, id; + + id = spel_constraint_to_pl(sd, cid); + if (id < 0) + return id; + + ret = spel_read_pl_data(sd, id, PL_LIMIT, true, &val); + if (!ret) + *data = val; + + return ret; +} + +static int spel_set_time_window(struct powercap_zone *power_zone, int cid, + u64 window) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + int id; + + id = spel_constraint_to_pl(sd, cid); + if (id < 0) + return id; + + return spel_write_pl_data(sd, id, PL_TIME_WINDOW, window); +} + +static int spel_get_time_window(struct powercap_zone *power_zone, int cid, + u64 *data) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + u64 val; + int ret, id; + + id = spel_constraint_to_pl(sd, cid); + if (id < 0) + return id; + + ret = spel_read_pl_data(sd, id, PL_TIME_WINDOW, true, &val); + if (!ret) + *data = val; + + return ret; +} + +static const char *spel_get_constraint_name(struct powercap_zone *power_zone, + int cid) +{ + struct spel_domain *sd = power_zone_to_spel_domain(power_zone); + int id; + + id = spel_constraint_to_pl(sd, cid); + if (id >= 0) + return sd->pl_name[id]; + + return NULL; +} + +static const struct powercap_zone_constraint_ops constraint_ops = { + .set_power_limit_uw = spel_set_power_limit, + .get_power_limit_uw = spel_get_power_limit, + .set_time_window_us = spel_set_time_window, + .get_time_window_us = spel_get_time_window, + .get_name = spel_get_constraint_name, +}; + +static void spel_init_domains(struct spel_system *sp) +{ + unsigned int i; + + for (i = 0; i < SPEL_DOMAIN_MAX; i++) { + struct spel_domain *sd = &sp->domains[i]; + + sd->sp = sp; + snprintf(sd->name, SPEL_DOMAIN_NAME_LENGTH, "%s", + spel_domain_names[i]); + sd->id = i; + sd->status_reg = sp->node_base + domain_offsets[i]; + + /* PL1 is always supported (required for powercap registration) */ + sp->limits[i] = BIT(POWER_LIMIT1); + sd->pl_name[POWER_LIMIT1] = pl_names[POWER_LIMIT1]; + } +} + +static int spel_check_unit(struct spel_system *sp) +{ + u32 value, shift; + + /* Read power_unit and time_unit from offset 0x0 */ + value = readl(sp->config_base); + + /* + * Unit calculation: 1 / (2^shift) + * Masks limit: TIME_UNIT (4 bits, max 15), POWER_UNIT (3 bits, max 7). + */ + shift = (value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; + sp->power_unit = 1000000 / (1 << shift); + + shift = (value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; + sp->time_unit = 1000000 / (1 << shift); + + /* Read energy_unit from ENERGY_RPT_UNIT_OFFSET */ + value = readl(sp->config_base + ENERGY_RPT_UNIT_OFFSET); + + /* + * Unit calculation: 1 / (2^shift) + * Masks limit: ENERGY_UNIT (4 bits, max 15). + */ + shift = (value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; + sp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << shift); + + dev_dbg(sp->dev, "Units: energy=%dnJ, time=%dus, power=%duW\n", + sp->energy_unit, sp->time_unit, sp->power_unit); + + return 0; +} + +static void spel_detect_powerlimit(struct spel_domain *sd) +{ + struct spel_system *sp = sd->sp; + u32 capabilities; + int i, j; + + capabilities = readl(sp->config_base + LIMITS_CAPABILITY_OFFSET); + + /* Detect power limits from hardware capabilities */ + for (i = POWER_LIMIT2; i < NR_POWER_LIMITS; i++) { + for (j = 0; j < ARRAY_SIZE(constraints); j++) { + struct spel_constraint_info *ci = &constraints[j]; + + if (ci->domain_id == sd->id && ci->pl_id == i) { + if (capabilities & ci->supported_mask) { + sp->limits[sd->id] |= BIT(i); + sd->pl_name[i] = pl_names[i]; + } + break; + } + } + } +} + +static int spel_init_system(struct spel_system *sp, struct device *dev) +{ + int i, ret; + + /* Read unit configuration (common for all domains) */ + ret = spel_check_unit(sp); + if (ret) { + dev_err(dev, "Failed to read unit config\n"); + return ret; + } + + sp->domains = devm_kcalloc(dev, SPEL_DOMAIN_MAX, + sizeof(struct spel_domain), GFP_KERNEL); + if (!sp->domains) + return -ENOMEM; + + spel_init_domains(sp); + + for (i = 0; i < SPEL_DOMAIN_MAX; i++) { + struct spel_domain *sd = &sp->domains[i]; + + ret = devm_mutex_init(dev, &sd->lock); + if (ret) { + dev_err(dev, "Failed to initialize mutex for domain %s\n", sd->name); + return ret; + } + + spel_detect_powerlimit(sd); + } + + return 0; +} + +static int spel_register_powercap(struct spel_system *sp) +{ + struct spel_domain *sd; + struct powercap_zone *power_zone = NULL; + int nr_pl, ret, i; + + /* Register SYS domain as parent zone */ + for (sd = sp->domains; sd < sp->domains + SPEL_DOMAIN_MAX; sd++) { + if (sd->id == SPEL_DOMAIN_SYS) { + nr_pl = spel_find_nr_power_limit(sd); + + power_zone = powercap_register_zone(&sd->power_zone, + sp->control_type, sd->name, + NULL, &zone_ops, nr_pl, + &constraint_ops); + if (IS_ERR(power_zone)) { + dev_err(sp->dev, "Failed to register power zone %s\n", + sd->name); + return PTR_ERR(power_zone); + } + sp->power_zone = power_zone; + break; + } + } + + if (!power_zone) { + dev_err(sp->dev, "No SYS domain found\n"); + return -ENODEV; + } + + /* Register other domains as children */ + for (sd = sp->domains; sd < sp->domains + SPEL_DOMAIN_MAX; sd++) { + struct powercap_zone *parent = sp->power_zone; + + if (sd->id == SPEL_DOMAIN_SYS) + continue; + + /* SOC is child of SYS, others are children of SOC */ + if (sd->id != SPEL_DOMAIN_SOC) { + for (i = 0; i < SPEL_DOMAIN_MAX; i++) { + if (sp->domains[i].id == SPEL_DOMAIN_SOC) { + parent = &sp->domains[i].power_zone; + break; + } + } + } + + nr_pl = spel_find_nr_power_limit(sd); + power_zone = powercap_register_zone(&sd->power_zone, + sp->control_type, + sd->name, parent, + &zone_ops, nr_pl, + &constraint_ops); + + if (IS_ERR(power_zone)) { + dev_err(sp->dev, "Failed to register power_zone %s\n", + sd->name); + ret = PTR_ERR(power_zone); + goto err_cleanup; + } + } + + return 0; + +err_cleanup: + /* Unregister in reverse order: children first, then SOC, then SYS */ + for (i = (int)(sd - sp->domains) - 1; i >= 0; i--) + powercap_unregister_zone(sp->control_type, &sp->domains[i].power_zone); + + return ret; +} + +static int spel_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spel_system *sp; + struct resource *res; + int ret; + + sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); + if (!sp) + return -ENOMEM; + + sp->dev = dev; + + /* Map spel domain registers (energy counters) */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nodes"); + if (!res) { + dev_err(dev, "Failed to get nodes resource\n"); + return -EINVAL; + } + sp->node_base = devm_ioremap_resource(dev, res); + if (IS_ERR(sp->node_base)) + return PTR_ERR(sp->node_base); + + /* Map constraint registers (power limits) */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "constraints"); + if (!res) { + dev_err(dev, "Failed to get constraints resource\n"); + return -EINVAL; + } + sp->constraint_base = devm_ioremap_resource(dev, res); + if (IS_ERR(sp->constraint_base)) + return PTR_ERR(sp->constraint_base); + + /* Map config registers (units, capabilities) */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + if (!res) { + dev_err(dev, "Failed to get config resource\n"); + return -EINVAL; + } + sp->config_base = devm_ioremap_resource(dev, res); + if (IS_ERR(sp->config_base)) + return PTR_ERR(sp->config_base); + + sp->control_type = powercap_register_control_type(NULL, "qcom-spel", + NULL); + if (IS_ERR(sp->control_type)) { + dev_err(dev, "Failed to register control type\n"); + return PTR_ERR(sp->control_type); + } + + /* Initialize system and domains */ + ret = spel_init_system(sp, dev); + if (ret) { + dev_err(dev, "Failed to initialize system\n"); + goto err_unregister_control; + } + + ret = spel_register_powercap(sp); + if (ret) { + dev_err(dev, "Failed to register powercap zones\n"); + goto err_unregister_control; + } + + platform_set_drvdata(pdev, sp); + + return 0; + +err_unregister_control: + powercap_unregister_control_type(sp->control_type); + return ret; +} + +static void spel_remove(struct platform_device *pdev) +{ + struct spel_system *sp = platform_get_drvdata(pdev); + int i; + + if (!sp) + return; + + /* Unregister in reverse order: children first, then SOC, then SYS */ + for (i = SPEL_DOMAIN_MAX - 1; i >= 0; i--) + powercap_unregister_zone(sp->control_type, &sp->domains[i].power_zone); + + powercap_unregister_control_type(sp->control_type); +} + +static const struct of_device_id spel_of_match[] = { + { .compatible = "qcom,spel" }, + { } +}; +MODULE_DEVICE_TABLE(of, spel_of_match); + +static struct platform_driver spel_driver = { + .probe = spel_probe, + .remove = spel_remove, + .driver = { + .name = "qcom_spel", + .of_match_table = spel_of_match, + }, +}; + +module_platform_driver(spel_driver); + +MODULE_DESCRIPTION("Qualcomm SPEL Powercap Driver"); +MODULE_LICENSE("GPL"); From 41ab5c43a6c7dda283ae0c0b3b6c35ca63787101 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Thu, 30 Apr 2026 14:28:57 +0530 Subject: [PATCH 1011/1330] FROMLIST: arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au Add ADC nodes for the four PMM8654au PMICs (pmm8654au_0 through pmm8654au_3) on the Lemans platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Also add the io-channels and io-channel-names properties under the temp-alarm nodes so that they can get temperature reading from the ADC die_temp channels. Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-2-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Ayyagari Ushasreevalli Signed-off-by: Jishnu Prakash (cherry picked from commit 3843ab50c3f31b575d4fcc780e387159d2cca3dc) --- arch/arm64/boot/dts/qcom/lemans-pmics.dtsi | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi index 341119fc82440..6caec3e4df4bb 100644 --- a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi @@ -5,6 +5,7 @@ #include #include +#include "qcom-adc5-gen3.h" / { thermal-zones { @@ -110,6 +111,8 @@ reg = <0xa00>; interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_0_adc ADC5_GEN3_DIE_TEMP(0)>; + io-channel-names = "thermal"; }; pmm8654au_0_pon: pon@1200 { @@ -141,6 +144,27 @@ interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; }; + pmm8654au_0_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + + channel@3 { + reg = ; + label = "pmm8654au_0_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@8e { + reg = ; + label = "pmm8654au_0_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8654au_0_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; @@ -176,6 +200,29 @@ reg = <0xa00>; interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_1_adc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; + }; + + pmm8654au_1_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + + channel@203 { + reg = ; + label = "pmm8654au_1_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@28e { + reg = ; + label = "pmm8654au_1_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_1_gpios: gpio@8800 { @@ -200,6 +247,29 @@ reg = <0xa00>; interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_2_adc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; + }; + + pmm8654au_2_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + + channel@403 { + reg = ; + label = "pmm8654au_2_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@48e { + reg = ; + label = "pmm8654au_2_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_2_gpios: gpio@8800 { @@ -224,6 +294,29 @@ reg = <0xa00>; interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_3_adc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; + }; + + pmm8654au_3_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + + channel@603 { + reg = ; + label = "pmm8654au_3_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@68e { + reg = ; + label = "pmm8654au_3_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_3_gpios: gpio@8800 { From 0c6b134c2df20855166f34944f8709e378c02797 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 20 May 2026 14:16:19 +0800 Subject: [PATCH 1012/1330] FROMLIST: arm64: dts: qcom: kaanapali: add the GPU SMMU node Add the Adreno GPU SMMU node for kaanapali platform. Link: https://lore.kernel.org/r/20260512-kaana-gpu-dt-v1-3-13e1c07c2050@oss.qualcomm.com Signed-off-by: Qingqing Zhou Signed-off-by: Akhil P Oommen Signed-off-by: Yijie Yang (cherry picked from commit cd4fdfb33dfd1fcf60b41397f05dd0a6cd85bbc5) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 89451e7b49ab2..a4454d5df20e3 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2954,11 +2954,9 @@ dma-coherent; power-domains = <&gpucc GPU_CC_CX_GDSC>; - interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; - clock-names = "gpu_cc_gpu_smmu_vote_clk"; + clock-names = "hlos"; interrupts = , , From 8d392ad6eada7081feed19f2af7c2ca6b0808635 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 20 May 2026 14:16:19 +0800 Subject: [PATCH 1013/1330] FROMLIST: arm64: dts: qcom: Add GPU support for Kaanapali Adreno 840 present in Kaanapali SoC is the second generation GPU in A8x family. It is based on the new slice architecture with 3 slices, higher GMEM/caches etc. There is some re-arrangement in the reglist to properly cover maximum register region. Other than this, the DT description is mostly similar to the existing chipsets except the OPP tables. Link: https://lore.kernel.org/r/20260512-kaana-gpu-dt-v1-5-13e1c07c2050@oss.qualcomm.com Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov Signed-off-by: Yijie Yang (cherry picked from commit 1d47d861498567cd2c8b9f7d249d99d2f5446a0a) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 52 ++++++++++++++++++++----- 1 file changed, 43 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index a4454d5df20e3..ad32ad4f782d6 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2725,12 +2725,10 @@ gpu: gpu@3d00000 { compatible = "qcom,adreno-44050a01", "qcom,adreno"; - reg = <0x0 0x03d00000 0x0 0x40000>, - <0x0 0x03d9e000 0x0 0x2000>, - <0x0 0x03d61000 0x0 0x800>; + reg = <0x0 0x03d00000 0x0 0x6c000>, + <0x0 0x03d9e000 0x0 0x2000>; reg-names = "kgsl_3d0_reg_memory", - "cx_mem", - "cx_dbgc"; + "cx_mem"; interrupts = ; @@ -2742,6 +2740,9 @@ qcom,gmu = <&gmu>; #cooling-cells = <2>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "gfx-mem"; @@ -2758,12 +2759,15 @@ opp-hz = /bits/ 64 <222000000>; opp-level = ; opp-peak-kBps = <2136718>; + opp-supported-hw = <0x0f>; + /* ACD is disabled */ }; opp-282000000 { opp-hz = /bits/ 64 <282000000>; opp-level = ; opp-peak-kBps = <5285156>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xca2e5ffd>; }; @@ -2771,6 +2775,7 @@ opp-hz = /bits/ 64 <342000000>; opp-level = ; opp-peak-kBps = <5285156>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xe22a5ffd>; }; @@ -2778,6 +2783,7 @@ opp-hz = /bits/ 64 <382000000>; opp-level = ; opp-peak-kBps = <5285156>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xa22c5ffd>; }; @@ -2785,6 +2791,7 @@ opp-hz = /bits/ 64 <422000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xa22c5ffd>; }; @@ -2792,6 +2799,7 @@ opp-hz = /bits/ 64 <461000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xe82e5ffd>; }; @@ -2799,6 +2807,7 @@ opp-hz = /bits/ 64 <500000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xe82c5ffd>; }; @@ -2806,6 +2815,7 @@ opp-hz = /bits/ 64 <539000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xc82b5ffd>; }; @@ -2813,6 +2823,7 @@ opp-hz = /bits/ 64 <578000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xc02c5ffd>; }; @@ -2820,6 +2831,7 @@ opp-hz = /bits/ 64 <646000000>; opp-level = ; opp-peak-kBps = <8171875>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xc02c5ffd>; }; @@ -2827,6 +2839,7 @@ opp-hz = /bits/ 64 <726000000>; opp-level = ; opp-peak-kBps = <8171875>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0x882f5ffd>; }; @@ -2834,6 +2847,7 @@ opp-hz = /bits/ 64 <826000000>; opp-level = ; opp-peak-kBps = <12449218>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xa82c5ffd>; }; @@ -2841,6 +2855,7 @@ opp-hz = /bits/ 64 <902000000>; opp-level = ; opp-peak-kBps = <12449218>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0xa82b5ffd>; }; @@ -2848,22 +2863,40 @@ opp-hz = /bits/ 64 <967000000>; opp-level = ; opp-peak-kBps = <12449218>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0x882a5ffd>; }; - opp-105000000 { - opp-hz = /bits/ 64 <105000000>; + opp-1050000000 { + opp-hz = /bits/ 64 <1050000000>; opp-level = ; opp-peak-kBps = <20832031>; + opp-supported-hw = <0x0f>; qcom,opp-acd-level = <0x88295ffd>; }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-level = ; + opp-peak-kBps = <20832031>; + opp-supported-hw = <0x07>; + qcom,opp-acd-level = <0xa02e5ffd>; + }; + + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-level = ; + opp-peak-kBps = <20832031>; + opp-supported-hw = <0x03>; + qcom,opp-acd-level = <0x802d5ffd>; + }; }; }; - gmu: gmu@3d6a000 { + gmu: gmu@3d6c000 { compatible = "qcom,adreno-gmu-840.1", "qcom,adreno-gmu"; - reg = <0x0 0x03d37000 0x0 0x68000>; + reg = <0x0 0x03d6c000 0x0 0x68000>; reg-names = "gmu"; interrupts = , @@ -2889,6 +2922,7 @@ iommus = <&adreno_smmu 5 0x0>; qcom,qmp = <&aoss_qmp>; + operating-points-v2 = <&gmu_opp_table>; gmu_opp_table: opp-table { From 50313eee120edc1107ad57c982dabc03f9b29d87 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Thu, 30 Apr 2026 14:28:58 +0530 Subject: [PATCH 1014/1330] FROMLIST: arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Add ADC nodes for PMM8620AU PMIC instances (SID 0 and SID 2) present on the Monaco platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-3-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Ayyagari Ushasreevalli Signed-off-by: Jishnu Prakash (cherry picked from commit ee32a8c23d8ea363b214127b66f1cb16a4432953) --- arch/arm64/boot/dts/qcom/monaco-pmics.dtsi | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi index e990d7367719b..232bcb942b54c 100644 --- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi @@ -5,6 +5,7 @@ #include #include +#include "qcom-adc5-gen3.h" &spmi_bus { pmm8620au_0: pmic@0 { @@ -20,6 +21,27 @@ interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; }; + pmm8620au_0_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + + channel@3 { + reg = ; + label = "pmm8620au_0_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@8e { + reg = ; + label = "pmm8620au_0_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8620au_0_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; @@ -37,6 +59,27 @@ #address-cells = <1>; #size-cells = <0>; + pmm8650au_1_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + + channel@203 { + reg = ; + label = "pmm8650au_1_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@28e { + reg = ; + label = "pmm8650au_1_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8650au_1_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; From 9b4dd8db20754bd6a6488d0c0ccfb67e5e643f25 Mon Sep 17 00:00:00 2001 From: Shivam Rawat Date: Tue, 12 May 2026 03:53:18 +0530 Subject: [PATCH 1015/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add qfprom node Add the qfprom node and gpu related subnodes on Kaanapali SoC. Link: https://lore.kernel.org/all/20260512-kaana-gpu-dt-v1-4-13e1c07c2050@oss.qualcomm.com/ Signed-off-by: Jingyi Wang Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Shivam Rawat (cherry picked from commit 3bfffd56e9eeeaa20497fe69a3a4887f2165d78e) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index ad32ad4f782d6..92570a5e21268 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -6096,6 +6096,18 @@ }; }; + efuse@221c8000 { + compatible = "qcom,kaanapali-qfprom", "qcom,qfprom"; + reg = <0x0 0x221c8000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@142 { + reg = <0x142 0x2>; + bits = <3 9>; + }; + }; + nsp_noc: interconnect@260c0000 { compatible = "qcom,kaanapali-nsp-noc"; reg = <0x0 0x260c0000 0x0 0x21280>; From 4b631ca77f149582907218ac8b713ff884cf15fa Mon Sep 17 00:00:00 2001 From: Shivam Rawat Date: Tue, 12 May 2026 03:53:20 +0530 Subject: [PATCH 1016/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add GPU cooling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when reaching 105°C. Link: https://lore.kernel.org/all/20260512-kaana-gpu-dt-v1-6-13e1c07c2050@oss.qualcomm.com/ Signed-off-by: Gaurav Kohli Signed-off-by: Akhil P Oommen Signed-off-by: Shivam Rawat (cherry picked from commit 33d3cd72cd0ee06579a99577fa5a913b58db65c6) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 165 +++++++++++++++++++----- 1 file changed, 135 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 92570a5e21268..f4c7ca80641f7 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -26,6 +26,7 @@ #include #include #include +#include #include "kaanapali-ipcc.h" @@ -7195,13 +7196,15 @@ }; gpuss-0-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 0>; trips { - gpuss-0-hot { - temperature = <120000>; + gpuss_0_alert0: gpuss-0-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-0-critical { @@ -7210,16 +7213,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-1-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 1>; trips { - gpuss-1-hot { - temperature = <120000>; + gpuss_1_alert0: gpuss-1-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-1-critical { @@ -7228,16 +7240,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-2-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 2>; trips { - gpuss-2-hot { - temperature = <120000>; + gpuss_2_alert0: gpuss-2-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-2-critical { @@ -7246,16 +7267,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-3-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 3>; trips { - gpuss-3-hot { - temperature = <120000>; + gpuss_3_alert0: gpuss-3-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-3-critical { @@ -7264,16 +7294,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_3_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-4-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 4>; trips { - gpuss-4-hot { - temperature = <120000>; + gpuss_4_alert0: gpuss-4-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-4-critical { @@ -7282,16 +7321,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_4_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-5-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 5>; trips { - gpuss-5-hot { - temperature = <120000>; + gpuss_5_alert0: gpuss-5-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-5-critical { @@ -7300,16 +7348,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_5_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-6-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 6>; trips { - gpuss-6-hot { - temperature = <120000>; + gpuss_6_alert0: gpuss-6-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-6-critical { @@ -7318,16 +7375,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_6_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-7-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 7>; trips { - gpuss-7-hot { - temperature = <120000>; + gpuss_7_alert0: gpuss-7-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-7-critical { @@ -7336,16 +7402,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_7_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-8-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 8>; trips { - gpuss-8-hot { - temperature = <120000>; + gpuss_8_alert0: gpuss-8-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-8-critical { @@ -7354,16 +7429,25 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_8_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-9-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 9>; trips { - gpuss-9-hot { - temperature = <120000>; + gpuss_9_alert0: gpuss-9-alert0 { + temperature = <105000>; hysteresis = <5000>; - type = "hot"; + type = "passive"; }; gpuss-9-critical { @@ -7372,12 +7456,26 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_9_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss-10-thermal { + polling-delay-passive = <200>; + thermal-sensors = <&tsens5 10>; trips { + gpuss_10_alert0: gpuss-10-alert0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; gpuss-10-hot { temperature = <120000>; hysteresis = <5000>; @@ -7390,6 +7488,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_10_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; ddr-thermal { From 84fa2bd60bb37c60dc4082a582dc14951f77da7e Mon Sep 17 00:00:00 2001 From: Karthik S Date: Wed, 20 May 2026 13:04:46 +0530 Subject: [PATCH 1017/1330] FROMLIST: arm64: dts: qcom: Enable secondary mi2s Enable secondary mi2s to support HDMI audio. Link: https://lore.kernel.org/all/20260413091937.134469-2-kumar.singh@oss.qualcomm.com/ Signed-off-by: Karthik S (cherry picked from commit 53cf71070aa839a2ad9c817c2b2368246b1c2afc) --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 5 +++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 43 ++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index cc61b1d89363a..572a849d01910 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -5898,6 +5898,11 @@ function = "mi2s1_ws"; }; + mi2s1_mclk: mi2s1-mclk-state { + pins = "gpio105"; + function = "sec_mi2s"; + }; + pcie0_clkreq_n: pcie0-clkreq-n-state { pins = "gpio88"; function = "pcie0_clkreqn"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 52095082bf876..7744b2df7a9cd 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -679,6 +679,7 @@ lt9611_codec: hdmi-bridge@2b { compatible = "lontium,lt9611uxc"; reg = <0x2b>; + #sound-dai-cells = <1>; interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>; reset-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; @@ -1124,6 +1125,9 @@ compatible = "qcom,qcs6490-rb3gen2-sndcard"; model = "QCS6490-RB3Gen2"; + pinctrl-0 = <&mi2s1_data0>, <&mi2s1_mclk>, <&mi2s1_sclk>, <&mi2s1_ws>; + pinctrl-names = "default"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", "SpkrRight IN", "WSA_SPK2 OUT", "VA DMIC0", "vdd-micb", @@ -1163,6 +1167,22 @@ sound-dai = <&q6apm>; }; }; + + mi2s1-playback-dai-link { + link-name = "Secondary MI2S Playback"; + + codec { + sound-dai = <<9611_codec 0>; + }; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; &spi3 { @@ -1465,3 +1485,26 @@ compatible = "qcom,qcm6490-lpassaudiocc"; /delete-property/ power-domains; }; + +&mi2s1_data0 { + drive-strength = <8>; + bias-disable; +}; + +&mi2s1_mclk { + drive-strength = <8>; + bias-disable; + output-high; +}; + +&mi2s1_sclk { + drive-strength = <8>; + bias-disable; + output-high; +}; + +&mi2s1_ws { + drive-strength = <8>; + bias-disable; + output-high; +}; From 089794bb3bdfd08ead035fa00da4031662abc7a8 Mon Sep 17 00:00:00 2001 From: Karthik S Date: Wed, 20 May 2026 13:05:53 +0530 Subject: [PATCH 1018/1330] FROMLIST: arm64: dts: qcom: qcs6490: Enable DP audio Add new dai link to enable DP audio. Link: https://lore.kernel.org/all/20260413091937.134469-3-kumar.singh@oss.qualcomm.com/ Signed-off-by: Karthik S (cherry picked from commit 74641f34587334a71d2dcdf5dca1dff8249e3eb7) --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 7744b2df7a9cd..63966abd94446 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1183,6 +1183,22 @@ sound-dai = <&q6apm>; }; }; + + dp-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; &spi3 { From 0a5b37674b6ecc30196dfb59bee408069148715d Mon Sep 17 00:00:00 2001 From: Karthik S Date: Wed, 20 May 2026 12:35:59 +0530 Subject: [PATCH 1019/1330] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Add WCD headset playback and record for qcs6490-rb3gen2 industrial mezzanine Add WCD playback and capture DAI link to sound node. Add WCD codec node and corresponding soundwire nodes to perform headset playback and record. Link: https://lore.kernel.org/all/20260423071951.3181130-1-karthik.s@oss.qualcomm.com/#t Signed-off-by: Karthik S (cherry picked from commit 58c1242600cda87a8c2e7a4937dca96b0d7d8e2d) --- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index b37fb86108f67..b46111115fa21 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -6,10 +6,34 @@ /dts-v1/; /plugin/; #include +#include #include #include / { + wcd9370: audio-codec { + compatible = "qcom,wcd9370-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; + vdd-buck-supply = <&vph_pwr>; + vdd-rxtx-supply = <&vph_pwr>; + vdd-px-supply = <&vph_pwr>; + vdd-mic-bias-supply = <&vph_pwr>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,hphl-jack-type-normally-closed = <1>; + qcom,ground-jack-type-normally-closed = <1>; + qcom,rx-device = <&wcd937x_rx>; + qcom,tx-device = <&wcd937x_tx>; + + #sound-dai-cells = <1>; + }; + hdmi-connector { status = "disabled"; @@ -142,6 +166,14 @@ status = "disabled"; }; +&lpass_rx_macro { + status = "okay"; +}; + +&lpass_tx_macro { + status = "okay"; +}; + &mdss_dsi0_out { remote-endpoint = <<9211c_in>; }; @@ -349,6 +381,101 @@ }; }; +&sound { + model = "qcs6490-rb3gen2-ia-snd-card"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_ADC1", "ADC2_OUTPUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd9370 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd9370 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + +&swr0 { + status = "okay"; + + wcd937x_rx: codec@0,4 { + compatible = "sdw20217010a00"; + reg = <0 4>; + + /* + * WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R) + * WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH) + * WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R) + * WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO) + * WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD) + */ + qcom,rx-port-mapping = <1 2 3 4 5>; + + /* + * Static channels mapping between slave and master rx port channels. + * In the order of slave port channels, which is + * hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. + */ + qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>; + }; +}; + +&swr1 { + status = "okay"; + wcd937x_tx: codec@0,3 { + compatible = "sdw20217010a00"; + reg = <0 3>; + + /* + * WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2 + * WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2 + * WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 + * WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 + */ + qcom,tx-port-mapping = <1 1 2 3>; + + /* + * Static channel mapping between slave and master tx port channels. + * In the order of slave port channels which is adc1, adc2, adc3, + * mic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. + */ + qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>; + }; +}; + + &tlmm { pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { pins = "gpio78"; @@ -370,4 +497,10 @@ power-source = <0>; }; + wcd_default: wcd-reset-n-active-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; From 430eb4178a77ccd1fc153f309a6267097effab75 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Mon, 27 Apr 2026 12:08:59 +0530 Subject: [PATCH 1020/1330] FROMLIST: drm/msm/a8xx: Make a8xx_recover IFPC safe Similar to a6xx_recover(), check the GX power domain status before accessing mmio in GX domain a8xx_recover(). Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support") Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-5-797e54b3d464@oss.qualcomm.com (cherry picked from commit a82f6f10d55258cb0ef0ca6a2f7912e9fdae3b85) --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index fafeac62aebf5..91bd4da3cdffc 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -748,17 +748,22 @@ void a8xx_recover(struct msm_gpu *gpu) adreno_dump_info(gpu); - if (hang_debug) - a8xx_dump(gpu); - /* * To handle recovery specific sequences during the rpm suspend we are * about to trigger */ a6xx_gpu->hung = true; - /* Halt SQE first */ - gpu_write(gpu, REG_A8XX_CP_SQE_CNTL, 3); + if (adreno_gpu->funcs->gx_is_on(adreno_gpu)) { + /* + * Sometimes crashstate capture is skipped, so SQE should be + * halted here again + */ + gpu_write(gpu, REG_A8XX_CP_SQE_CNTL, 3); + + if (hang_debug) + a8xx_dump(gpu); + } pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); From 9e64b593ff664265d8e7b795e486b03d47e9b2e2 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Mon, 27 Apr 2026 12:09:00 +0530 Subject: [PATCH 1021/1330] FROMLIST: drm/msm/a6xx: Limit GXPD votes to recovery in A8x In A8x GPUs, the GX GDSC is moved to a separate block called GXCLKCTL which is under the GX power domain. Due to the way the support for this block is implemented in its driver, pm_runtime votes result in a vote on GX/GMxC/MxC rails from the APPS RSC. This is against the Adreno architecture which require GMU to be the sole voter of these collapsible rails on behalf of GPU, except during the GPU/GMU recovery. To align with this architectural requirement and to realize the power benefits of the IFPC feature, remove the GXPD votes during gmu resume and suspend. And during the recovery sequence, enable/disable the GXPD along with the 'synced_poweroff' genpd hint to force collapse this GDSC. Signed-off-by: Akhil P Oommen Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-6-797e54b3d464@oss.qualcomm.com (cherry picked from commit cee779428b078ee0bf0cad246cb92d692e5e4a41) --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 64 ++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index cab4c46c6cf2e..616198a836a4d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1250,6 +1250,56 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu) return 0; } +static int a6xx_gmu_gxpd_get(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + + if (IS_ERR_OR_NULL(gmu->gxpd)) + return 0; + + /* + * On A8xx HW, GX GDSC is moved to a new clk controller block under GX + * power domain. The clock driver for this new block keeps the GX rail + * voted when gxpd is voted. So, use the gxpd only during gpu recovery. + */ + if (adreno_gpu->info->family >= ADRENO_8XX_GEN1) + return 0; + + /* + * On A6x/A7x, "enable" the GX power domain which won't actually do + * anything but it will make sure that the refcounting is correct in + * case we need to bring down the GX after a GMU failure + */ + return pm_runtime_get_sync(gmu->gxpd); +} + +static int a6xx_gmu_gxpd_put(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + + if (IS_ERR_OR_NULL(gmu->gxpd)) + return 0; + + if (adreno_gpu->info->family < ADRENO_8XX_GEN1) + return pm_runtime_put_sync(gmu->gxpd); + + /* + * On A8x, GX GDSC collapse should be triggered only when it is stuck ON + */ + if (adreno_gpu->funcs->gx_is_on(adreno_gpu)) { + pm_runtime_get_sync(gmu->gxpd); + /* + * Hint to gfxclkctl driver to do a hw collapse during the next + * RPM PUT. This is a special behavior in the gfxclkctl driver + */ + dev_pm_genpd_synced_poweroff(gmu->gxpd); + pm_runtime_put_sync(gmu->gxpd); + } + + return 0; +} int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { @@ -1266,13 +1316,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Turn on the resources */ pm_runtime_get_sync(gmu->dev); - /* - * "enable" the GX power domain which won't actually do anything but it - * will make sure that the refcounting is correct in case we need to - * bring down the GX after a GMU failure - */ - if (!IS_ERR_OR_NULL(gmu->gxpd)) - pm_runtime_get_sync(gmu->gxpd); + a6xx_gmu_gxpd_get(gmu); /* Use a known rate to bring up the GMU */ clk_set_rate(gmu->core_clk, 200000000); @@ -1339,7 +1383,8 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) disable_clk: clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); rpm_put: - pm_runtime_put(gmu->gxpd); + a6xx_gmu_gxpd_put(gmu); + pm_runtime_put(gmu->dev); return ret; @@ -1455,8 +1500,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) * domain. Usually the GMU does this but only if the shutdown sequence * was successful */ - if (!IS_ERR_OR_NULL(gmu->gxpd)) - pm_runtime_put_sync(gmu->gxpd); + a6xx_gmu_gxpd_put(gmu); clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); From 0b3f2c35018680bc3a74fb07cca2c55a72d265a7 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 19 May 2026 16:19:51 +0530 Subject: [PATCH 1022/1330] FROMLIST: arm64: dts: qcom: glymur: Enable SPEL powercap driver The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware based power monitoring and limiting capabilities for various power domains including System, SoC, CPU clusters, GPU, and various other subsystems for glymur. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://patch.msgid.link/20260519-qcom_spel_driver_upstream-v1-3-75356d1b7f94@oss.qualcomm.com (cherry picked from commit 1784993e8d6760195bf7dde5c36e94a2486e8382) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 622184f98f279..2224e6c025396 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -6208,6 +6208,16 @@ }; }; + power-controller@ef3b000 { + compatible = "qcom,spel"; + reg = <0x0 0x0ef3e000 0x0 0x1000>, + <0x0 0x0ef3d000 0x0 0x1000>, + <0x0 0x0ef3b000 0x0 0x1000>; + reg-names = "nodes", + "constraints", + "config"; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,glymur-tlmm"; reg = <0x0 0x0f100000 0x0 0xf00000>; From 830d2e3b836e123accc59e7c1c382f910ccc1dad Mon Sep 17 00:00:00 2001 From: Aastha Pandey Date: Tue, 19 May 2026 19:17:34 +0530 Subject: [PATCH 1023/1330] QCLINUX: defconfig: Enable Qualcomm SPEL driver The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware based power monitoring and limiting capabilities for various power domains including System, SoC, CPU clusters, GPU, and various other subsystems. The driver integrates with the Linux powercap framework, exposing SPEL capabilities through powercap sysfs interfaces. This allows userspace applications and thermal management daemons to monitor energy consumption and configure power limits for optimal power/performance balance. Signed-off-by: Aastha Pandey (cherry picked from commit 72667367aaaaaf23697a1db00a300f8496e2cbf0) --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 9de3118a8f584..3cfe0efb06c86 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -49,6 +49,7 @@ CONFIG_POWERCAP=y CONFIG_PROC_EVENTS=y CONFIG_QCA808X_PHY=m CONFIG_QCOM_QMI_COOLING=y +CONFIG_QCOM_SPEL=m CONFIG_QCOM_TGU=m CONFIG_REMOTEPROC_THERMAL=y CONFIG_SCHED_DEBUG=y From ee31bd421446e50abe6f06fbbedf382c3d48f679 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 20 May 2026 16:26:37 +0800 Subject: [PATCH 1024/1330] QCLINUX: memory-dump: add memory dump table for Shikra Add memory dump table configuration to enable memory dump function on Shikra platform. Signed-off-by: Jie Gan (cherry picked from commit cbdd4bbfa24a682d76769d4c1c66bb67b262ae4d) --- drivers/firmware/qcom/memory_dump_dev.c | 46 +++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c index 0845aa152dc2f..fb9d4dc0dceab 100644 --- a/drivers/firmware/qcom/memory_dump_dev.c +++ b/drivers/firmware/qcom/memory_dump_dev.c @@ -355,6 +355,37 @@ static const struct dump_item hamoa_items[] = { { ETFSWAO_REG, 0x1000, "etfswao-reg" }, }; +static const struct dump_item shikra_items[] = { + { C0_CONTEXT, 0x800, "c0-context" }, + { C100_CONTEXT, 0x800, "c100-context" }, + { C200_CONTEXT, 0x800, "c200-context" }, + { C300_CONTEXT, 0x800, "c300-context" }, + { C0_SCANDUMP, 0x10000, "c0-scandump" }, + { C100_SCANDUMP, 0x10000, "c100-scandump" }, + { C200_SCANDUMP, 0x10000, "c200-scandump" }, + { C300_SCANDUMP, 0x40000, "c300-scandump" }, + { L1_ICACHE0, 0x8900, "l1-icache0" }, + { L1_ICACHE100, 0x8900, "l1-icache100" }, + { L1_ICACHE200, 0x8900, "l1-icache200" }, + { L1_ICACHE300, 0x8900, "l1-icache300" }, + { L1_DCACHE0, 0x9100, "l1-dcache0" }, + { L1_DCACHE100, 0x9100, "l1-dcache100" }, + { L1_DCACHE200, 0x9100, "l1-dcache200" }, + { L1_DCACHE300, 0x9100, "l1-dcache300" }, + { L2_TLB0, 0x2100, "l2-tlb0" }, + { L2_TLB100, 0x2100, "l2-tlb100" }, + { L2_TLB200, 0x2100, "l2-tlb200" }, + { L2_TLB300, 0x2100, "l2-tlb300" }, + { RPM_SW, 0x30000, "rpm-sw" }, + { PMIC, 0x40000, "pmic" }, + { FCM, 0x8400, "fcm" }, + { TMC_ETF, 0x8000, "tmc-etf" }, + { ETR_REG, 0x1000, "etr-reg" }, + { ETF_REG, 0x1000, "etf-reg" }, + { MISC_DATA, 0x1000, "misc-data" }, + { ETF_LPASS, 0x8000, "etf-lpass" }, +}; + static const struct dump_table lemans_dump_table = { .items = lemans_items, .num_of_items = ARRAY_SIZE(lemans_items), @@ -397,6 +428,13 @@ static const struct dump_table hamoa_dump_table = { .imem_size = 0x8, }; +static const struct dump_table shikra_dump_table = { + .items = shikra_items, + .num_of_items = ARRAY_SIZE(shikra_items), + .imem_base = 0xc11e010, + .imem_size = 0x8, +}; + static int __init mem_dump_dev_init(void) { int ret; @@ -486,6 +524,14 @@ static int __init mem_dump_dev_init(void) goto fail; break; + case 756: + case 758: + case 759: + ret = platform_device_add_data(mem_dump_pdev, + &shikra_dump_table, sizeof(shikra_dump_table)); + if (ret) + goto fail; + break; default: dev_err(&mem_dump_pdev->dev, "Invalid SoC ID\n"); ret = -EINVAL; From 8d0b92a88e4c044da193f23ec387800fec055095 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Mon, 18 May 2026 18:39:34 +0530 Subject: [PATCH 1025/1330] arm64: dts: qcom: shikra: Enable MPSS remoteproc Enable the Modem Processor SubSystem (MPSS) remoteproc on Shikra CQS and IQS EVK boards Signed-off-by: Anurag Pateriya (cherry picked from commit e6d54f66afa74ce34004f97ce58d7b0c6048d2c9) --- arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 6 ++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 41e77f0601ce6..f8d9d4ad81f80 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -105,6 +105,12 @@ status = "okay"; }; +&remoteproc_mpss { + firmware-name = "qcom/shikra/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 63136008f410b..388b006a854b5 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -57,6 +57,12 @@ status = "okay"; }; +&remoteproc_mpss { + firmware-name = "qcom/shikra/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm8150_l17>; vqmmc-supply = <&pm8150_s4>; From 9e7728227b726439789a56d78c28a31319447b1d Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 20 May 2026 15:46:08 +0530 Subject: [PATCH 1026/1330] arm64: dts: qcom: shikra: Add DDR BWMON support Add CPU-to-DDR BWMON nodes and their corresponding opp tables for Shikra SoC. This is necessary to enable power management and optimize system performance from the perspective of dynamically changing DDR frequencies. Signed-off-by: Sayantan Chakraborty Signed-off-by: Komal Bajaj (cherry picked from commit 9963a935fd6b563bd48d2b5d71625472ae38f835) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index f4ee08cf720a2..56d94700bceca 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -818,6 +818,46 @@ }; }; + pmu@c91000 { + compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x00c91000 0x0 0x1000>; + + interrupts = ; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <1200000>; + }; + + opp-1 { + opp-peak-kBps = <2188000>; + }; + + opp-2 { + opp-peak-kBps = <3072000>; + }; + + opp-3 { + opp-peak-kBps = <4068000>; + }; + + opp-4 { + opp-peak-kBps = <6220000>; + }; + + opp-5 { + opp-peak-kBps = <7216000>; + }; + }; + }; + mem_noc: interconnect@d00000 { compatible = "qcom,shikra-mem-noc-core"; reg = <0x0 0x00d00000 0x0 0x43080>; From 3c5b0384a55bd737b4bd9a91a105d3ae72acb378 Mon Sep 17 00:00:00 2001 From: Ignatius Michael Jihan Date: Fri, 15 May 2026 19:02:44 +0530 Subject: [PATCH 1027/1330] arm64: dts: qcom: hamoa: add CAMX EL2 overlay Add a device tree overlay to enable EL2 boot support for the Hamoa platform with CAMX configuration. CRs-Fixed: 4538425 Signed-off-by: Ignatius Michael Jihan (cherry picked from commit a7c58823f27f3ed7f06cfa93098fe018e41176d4) --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ arch/arm64/boot/dts/qcom/hamoa-camx-el2.dtso | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/hamoa-camx-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index bccb6cede6746..c11582e565f52 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -491,6 +491,10 @@ hamoa-evk-camx-dtbs := hamoa-iot-evk.dtb hamoa-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-evk-camx.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-evk-camx.dtbo +hamoa-camx-el2-dtbs := hamoa-iot-evk-el2.dtb hamoa-evk-camx.dtbo hamoa-camx-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += hamoa-camx-el2.dtb + lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/hamoa-camx-el2.dtso b/arch/arm64/boot/dts/qcom/hamoa-camx-el2.dtso new file mode 100644 index 0000000000000..5584660dbcfd6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-camx-el2.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path = "/soc@0/qcom,cam-icp"; + __overlay__ { + camera-firmware { + iommus = <&apps_smmu 0x1901 0x0>; + }; + }; + }; +}; From becbd2aaaf9d5831ee357b2d9aec8f353d687b45 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 20 May 2026 19:47:15 +0530 Subject: [PATCH 1028/1330] arm64: dts: qcom: shikra: Add EPSS L3 interconnect provider node Add Epoch Subsystem (EPSS) L3 interconnect provider node for Shikra SoC. Signed-off-by: Raviteja Laggyshetty (cherry picked from commit 4150e4c321c533e46918c69757bac3c844883b8a) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 56d94700bceca..aceca378ccf9b 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -3976,6 +3977,14 @@ }; }; + epss_l3: interconnect@fd90000 { + compatible = "qcom,shikra-epss-l3"; + reg = <0x0 0x0fd90000 0x0 0x1000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@fd91000 { compatible = "qcom,shikra-cpufreq-rimps", "qcom,cpufreq-rimps"; reg = <0x0 0x0fd91000 0x0 0x1000>, From be11a1a3094b64fc74c381d509e8a3f83d6220ff Mon Sep 17 00:00:00 2001 From: Saurabh Anand Date: Thu, 21 May 2026 16:52:11 +0530 Subject: [PATCH 1029/1330] FROMLIST: arm64: dts: qcom: glymur: Configure DP endpoints for 2-lane operation Add explicit data-lanes to the MDSS DP output endpoints to enable display port in 2 lanes configuration and disable the mode-switch property from the USB QMP PHY node. Signed-off-by: Saurabh Anand Link: https://lore.kernel.org/all/20260521120058.2966709-1-saurabh.anand@oss.qualcomm.com/ (cherry picked from commit c2152916f4ff3c6039adc687655848920f3bdf58) --- arch/arm64/boot/dts/qcom/glymur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 2224e6c025396..0f8bb20fbcbf7 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2509,7 +2509,6 @@ #clock-cells = <1>; #phy-cells = <1>; - mode-switch; orientation-switch; status = "disabled"; @@ -2583,7 +2582,6 @@ #clock-cells = <1>; #phy-cells = <1>; - mode-switch; orientation-switch; status = "disabled"; @@ -5725,6 +5723,7 @@ reg = <1>; mdss_dp0_out: endpoint { + data-lanes = <0 1>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; @@ -5816,6 +5815,7 @@ reg = <1>; mdss_dp1_out: endpoint { + data-lanes = <0 1>; remote-endpoint = <&usb_1_qmpphy_dp_in>; }; }; From 057c7d662629536e0758e5c26efe5cf57871fa02 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Thu, 12 Feb 2026 21:35:24 +0530 Subject: [PATCH 1030/1330] FROMLIST: arm64: dts: qcom: monaco: Move eMMC CQE support from SoC to board DT The Monaco SoC SDHC controller supports both eMMC and SD cards. However, the 'supports-cqe' property (Command Queue Engine) is specific to eMMC and conflicts with SD card operation. Remove 'supports-cqe' from the SoC device tree to ensure compatibility with SD cards. Simultaneously, add the property explicitly to the qcs8300-ride board device tree, as this board uses the controller in eMMC mode. This ensures the SoC definition remains generic while enabling features correctly at the board level. Link: https://lore.kernel.org/all/20260227105055.2364348-1-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara (cherry picked from commit c9fed4e02040ebd57d04ca20bbec1034614391c4) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index a67d95a70ecef..3984252777c45 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4846,7 +4846,7 @@ qcom,dll-config = <0x000f64ee>; qcom,ddr-config = <0x80040868>; - supports-cqe; + bus-width = <8>; dma-coherent; qcom,ice = <&sdhc_ice>; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 2b9bfba793b34..844b513743cb1 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -722,6 +722,7 @@ vmmc-supply = <&vreg_l8a>; vqmmc-supply = <&vreg_s4a>; + supports-cqe; non-removable; no-sd; no-sdio; From 0a14beb6dd9f1f50c7249805a6d31c0799718f07 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Thu, 12 Feb 2026 21:55:08 +0530 Subject: [PATCH 1031/1330] FROMLIST: arm64: dts: qcom: monaco-evk: Enable SDHCI for SD Card via overlay The monaco EVK board supports either eMMC or SD-card, but only one can be active at a time. Enable the SD Host Controller Interface (SDHCI) on the monaco EVK board to support SD Card for storage via a device tree overlay. This allows eMMC support to be enabled through a separate overlay when required. Link: https://lore.kernel.org/all/20260227105055.2364348-1-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara (cherry picked from commit daa1cfdb843dab7d2b3cc9997aec2fea6e9a4b9d) --- arch/arm64/boot/dts/qcom/Makefile | 5 +- .../boot/dts/qcom/monaco-evk-sd-card.dtso | 72 +++++++++++++++++++ 2 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index c11582e565f52..17dc0d1b97c8b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -77,7 +77,10 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb -dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtbo + +monaco-evk-sd-card-dtbs := monaco-evk.dtb monaco-evk-sd-card.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-sd-card.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso new file mode 100644 index 0000000000000..bc4ea12587a2e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + vmmc_sdc: regulator-mmc-sdc { + compatible = "regulator-fixed"; + + regulator-name = "vmmc_sdc"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + vreg_sdc: regulator-sdc { + compatible = "regulator-gpio"; + + regulator-name = "vreg_sdc"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + gpios = <&expander1 7 GPIO_ACTIVE_HIGH>; + states = <1800000 1>, <2950000 0>; + + startup-delay-us = <100>; + }; +}; + +&sdhc_1 { + vmmc-supply = <&vmmc_sdc>; + vqmmc-supply = <&vreg_sdc>; + + pinctrl-0 = <&sdc1_state_on>, <&sd_cd>; + pinctrl-1 = <&sdc1_state_off>, <&sd_cd>; + pinctrl-names = "default", "sleep"; + + cap-sd-highspeed; + no-1-8-v; + + bus-width = <4>; + cd-gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + + status = "okay"; +}; + +&sdhc1_opp_table { + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; +}; + +&tlmm { + sd_cd: sd-cd-state { + pins = "gpio11"; + function = "gpio"; + bias-pull-up; + }; +}; From e0dae725569dd73631cb8cfd17dcbf0f78dfdf7f Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Wed, 25 Feb 2026 17:08:59 +0530 Subject: [PATCH 1032/1330] FROMLIST: arm64: dts: qcom: monaco-evk: Add SDHCI support for eMMC via overlay Enable the SDHCI controller for eMMC functionality on the Monaco EVK using a device tree overlay. Configure the corresponding VCC regulator parameters to support the eMMC interface. Link: https://lore.kernel.org/all/20260227105055.2364348-1-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara (cherry picked from commit c07593b6dabf6afc7a0fbe6db43321a8751098c4) --- arch/arm64/boot/dts/qcom/Makefile | 3 ++ arch/arm64/boot/dts/qcom/monaco-evk-emmc.dtso | 42 +++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-emmc.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 17dc0d1b97c8b..42be4d2d719eb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -81,6 +81,9 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb monaco-evk-sd-card-dtbs := monaco-evk.dtb monaco-evk-sd-card.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-sd-card.dtb +monaco-evk-emmc-dtbs := monaco-evk.dtb monaco-evk-emmc.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-emmc.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-emmc.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-emmc.dtso new file mode 100644 index 0000000000000..cfa8464455ba0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-emmc.dtso @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +/ { + vreg_s2s: regulator-vreg-s2s { + compatible = "regulator-fixed"; + regulator-name = "regulator-s2s"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; + + supports-cqe; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + + pinctrl-names = "default", "sleep"; + + non-removable; + + bus-width = <8>; + no-sd; + no-sdio; + + status = "okay"; +}; + +&vreg_l8a { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; +}; From f8c8a54ee47c230e47adb8b4852714c6cb99baf4 Mon Sep 17 00:00:00 2001 From: Jianping Li Date: Wed, 1 Apr 2026 16:14:37 +0800 Subject: [PATCH 1033/1330] FROMLIST: arm64: dts: qcom: kodiak: increase fastrpc compute-cb session slots Some workloads on Kodiak can exhaust FastRPC sessions when multiple compute clients open contexts concurrently, leading to -EBUSY failures. Describe the compute context bank with qcom,nsessions = <5> so the driver can provision enough session slots for the compute-cb instance. Link: https://lore.kernel.org/all/20260401073345.478-1-jianping.li@oss.qualcomm.com/ Signed-off-by: Jianping Li (cherry picked from commit da803bfa8902b323dbb336594b7749f332183365) --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 572a849d01910..b64665a86a627 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -4521,6 +4521,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x1805 0x0>; + qcom,nsessions = <5>; dma-coherent; }; }; From 38911a3d9cc698dc9b6e8f25f448d3c8dc5fe9bc Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Tue, 19 May 2026 12:21:14 +0530 Subject: [PATCH 1034/1330] arm64: dts: qcom: shikra: Add BAM-DMUX support Add required nodes to enable the upstream BAM-DMUX WWAN driver on Shikra. The SMSM (Shared Memory State Machine) node provides the power control signaling between the AP and modem for BAM-DMUX. The BAM DMA controller node describes the A2 modem BAM hardware as a standard DMA controller. The BAM-DMUX node references the DMA channels and the pc/pc-ack interrupt lines from the modem SMSM entry for power control signaling. Signed-off-by: Vishnu Santhosh (cherry picked from commit fd45a66c40f3aa463e7cf1d5778f5394de0b4586) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index aceca378ccf9b..31fe89a9eb2bb 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -24,6 +24,23 @@ #address-cells = <2>; #size-cells = <2>; + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupts-extended = + <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>, + <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = + <&apps_smsm 1>, + <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; @@ -426,6 +443,28 @@ }; }; + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + mboxes = <0>, <&apcs_glb 13>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -2554,6 +2593,18 @@ }; }; + bam_dmux_dma: dma-controller@6044000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x06044000 0x0 0x19000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + remoteproc_mpss: remoteproc@6080000 { compatible = "qcom,shikra-mpss-pas"; reg = <0x0 0x06080000 0x0 0x100>; From f4587f59ed590e0d0d864dfac26bc7b5319efb2d Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Tue, 12 May 2026 12:17:18 +0530 Subject: [PATCH 1035/1330] arm64: dts: qcom: shikra: Add CAMSS node Add node for the Shikra camera subsystem. Co-developed-by: Vikram Sharma Signed-off-by: Vikram Sharma Signed-off-by: Nihal Kumar Gupta (cherry picked from commit 1063df9bf1bbdabb52fc43f5b2ffff0ec143f640) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 100 +++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 31fe89a9eb2bb..cbc6120d5a8e9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1429,6 +1429,106 @@ }; }; + camss: camss@5c11000 { + compatible = "qcom,shikra-camss"; + + reg = <0x0 0x05c11000 0x0 0x1000>, + <0x0 0x05c6e000 0x0 0x1000>, + <0x0 0x05c75000 0x0 0x1000>, + <0x0 0x05c52000 0x0 0x1000>, + <0x0 0x05c53000 0x0 0x1000>, + <0x0 0x05c66000 0x0 0x400>, + <0x0 0x05c68000 0x0 0x400>, + <0x0 0x05c6f000 0x0 0x4000>, + <0x0 0x05c76000 0x0 0x4000>; + reg-names = "top", + "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; + clock-names = "ahb", + "axi", + "camnoc_nrt_axi", + "camnoc_rt_axi", + "csi0", + "csi1", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "top_ahb", + "vfe0", + "vfe0_cphy_rx", + "vfe1", + "vfe1_cphy_rx"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, + <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc"; + + iommus = <&apps_smmu 0x400 0x0>; + + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,shikra-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; From dd8bceb2e5612d359272c4ce708990ec50c3fece Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Tue, 12 May 2026 13:42:31 +0530 Subject: [PATCH 1036/1330] arm64: dts: qcom: shikra: Add CCI definitions Qualcomm Shikra SoC has one Camera Control Interface (CCI) containing two I2C hosts. Signed-off-by: Nihal Kumar Gupta (cherry picked from commit 5518ed971462f9817095de1352d08d6b9c4e7ad4) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 67 ++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index cbc6120d5a8e9..7567c411291e9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -499,6 +499,38 @@ gpio-ranges = <&tlmm 0 0 185>; wakeup-parent = <&mpm>; + cci_i2c0_default: cci-i2c0-default-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "cci_i2c0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci_i2c0_sleep: cci-i2c0-sleep-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "cci_i2c0"; + drive-strength = <2>; + bias-pull-down; + }; + + cci_i2c1_default: cci-i2c1-default-state { + /* SDA, SCL */ + pins = "gpio41", "gpio42"; + function = "cci_i2c1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci_i2c1_sleep: cci-i2c1-sleep-state { + /* SDA, SCL */ + pins = "gpio41", "gpio42"; + function = "cci_i2c1"; + drive-strength = <2>; + bias-pull-down; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio2", "gpio3"; @@ -1529,6 +1561,41 @@ }; }; + cci: cci@5c1b000 { + compatible = "qcom,shikra-cci", "qcom,msm8996-cci"; + + reg = <0x0 0x05c1b000 0x0 0x1000>; + interrupts = ; + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_0_CLK>; + clock-names = "ahb", + "cci"; + + pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; + pinctrl-1 = <&cci_i2c0_sleep &cci_i2c1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,shikra-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; From 1cfa9b9a47f46a2d7724766e118f13a5e94a118d Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Tue, 12 May 2026 14:08:40 +0530 Subject: [PATCH 1037/1330] arm64: dts: qcom: shikra: Add pin configuration for mclks Add pinctrl configuration for the four available camera master clocks. Signed-off-by: Nihal Kumar Gupta (cherry picked from commit 3cc0b32f7946f78b8e0bab3203d8a8b91edfeb49) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 7567c411291e9..c692dc32e4e21 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -531,6 +531,34 @@ bias-pull-down; }; + mclk0_default: mclk0-default-state { + pins = "gpio34"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk1_default: mclk1-default-state { + pins = "gpio35"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk2_default: mclk2-default-state { + pins = "gpio96"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk3_default: mclk3-default-state { + pins = "gpio98"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio2", "gpio3"; From b38518221543d548b1444023631e1f11cb5e7b55 Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Fri, 22 May 2026 12:24:49 +0530 Subject: [PATCH 1038/1330] arm64: dts: qcom: shikra-cqm-evk-imx577-camera: Add DT overlay Shikra CQM and CQS are retail variants sharing the same PM4125 PMIC and identical camera supply rails. The only difference between them is the integrated modem on CQM, which does not affect camera hardware. Add a shared overlay for optional IMX577 integration via CSIPHY1, used by both CQM and CQS EVK boards. Signed-off-by: Nihal Kumar Gupta (cherry picked from commit 3362915a6fcd6683a5e5f0e74dd50d56df6cff5d) --- arch/arm64/boot/dts/qcom/Makefile | 6 ++ .../qcom/shikra-cqm-evk-imx577-camera.dtso | 63 +++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra-cqm-evk-imx577-camera.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 42be4d2d719eb..b129dfb5e1199 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -359,6 +359,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk.dtb + +shikra-cqm-evk-imx577-camera-dtbs := shikra-cqm-evk.dtb shikra-cqm-evk-imx577-camera.dtbo +shikra-cqs-evk-imx577-camera-dtbs := shikra-cqs-evk.dtb shikra-cqm-evk-imx577-camera.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk-imx577-camera.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk-imx577-camera.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk-imx577-camera.dtso b/arch/arm64/boot/dts/qcom/shikra-cqm-evk-imx577-camera.dtso new file mode 100644 index 0000000000000..a42a034b92adf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk-imx577-camera.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdd-csiphy-1p2-supply = <&pm4125_l5>; + vdd-csiphy-1p8-supply = <&pm4125_l13>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&mclk1_default>; + pinctrl-names = "default"; + + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + assigned-clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&pm4125_l15>; + + port { + imx577_ep1: endpoint { + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; From 6bd26b8b50777451b5b90b64c31aca6cd3d555de Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Fri, 22 May 2026 12:24:57 +0530 Subject: [PATCH 1039/1330] arm64: dts: qcom: shikra-iqs-evk-imx577-camera: Add DT overlay Shikra IQS is an industrial-grade variant using PM8150 PMIC, requiring different CSIPHY and sensor supply rails compared to the retail boards (CQM and CQS) which use PM4125. Add a dedicated overlay for optional IMX577 integration via CSIPHY1. Signed-off-by: Nihal Kumar Gupta (cherry picked from commit 0540e2bf6d1abb665a5fc3180a65b1ac43b220e7) --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/shikra-iqs-evk-imx577-camera.dtso | 63 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra-iqs-evk-imx577-camera.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b129dfb5e1199..e8318f2e7a170 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -362,9 +362,11 @@ dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk.dtb shikra-cqm-evk-imx577-camera-dtbs := shikra-cqm-evk.dtb shikra-cqm-evk-imx577-camera.dtbo shikra-cqs-evk-imx577-camera-dtbs := shikra-cqs-evk.dtb shikra-cqm-evk-imx577-camera.dtbo +shikra-iqs-evk-imx577-camera-dtbs := shikra-iqs-evk.dtb shikra-iqs-evk-imx577-camera.dtbo dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk-imx577-camera.dtb dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk-imx577-camera.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk-imx577-camera.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk-imx577-camera.dtso b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-imx577-camera.dtso new file mode 100644 index 0000000000000..f0423f1ab4e93 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-imx577-camera.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdd-csiphy-1p2-supply = <&pm8150_l11>; + vdd-csiphy-1p8-supply = <&pm8150_l12>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&mclk1_default>; + pinctrl-names = "default"; + + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + assigned-clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&pm8150_l15>; + + port { + imx577_ep1: endpoint { + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; From e25f6ed44acc063b8bc45c4801600a24367910df Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 22 May 2026 17:22:05 +0530 Subject: [PATCH 1040/1330] arm64: dts: qcom: shikra: Add CPU OPP tables to scale DDR/L3 Add OPP tables required to scale DDR and L3 per freq-domain on Shikra SoC. Signed-off-by: Sayantan Chakraborty Signed-off-by: Komal Bajaj (cherry picked from commit aecde298c64bd17bf270e588c2fa52201058353e) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 85 ++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index c692dc32e4e21..a555cd818dbda 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -69,6 +69,11 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu1: cpu@100 { @@ -81,6 +86,11 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu2: cpu@200 { @@ -93,6 +103,11 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu3: cpu@300 { @@ -105,6 +120,11 @@ dynamic-power-coefficient = <486>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; @@ -187,6 +207,71 @@ }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp_768mhz: opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <1200000 17817600>; + }; + + cpu0_opp_1017mhz: opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <2188000 25804800>; + }; + + cpu0_opp_1094mhz: opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-peak-kBps = <3072000 30105600>; + }; + + cpu0_opp_1497mhz: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <4068000 38707200>; + }; + + cpu0_opp_1612mhz: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + cpu0_opp_1804mhz: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <7216000 43622400>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible = "operating-points-v2"; + opp-shared; + + cpu3_opp_1017mhz: opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <2188000 25804800>; + }; + + cpu3_opp_1190mhz: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <3072000 30105600>; + }; + + cpu3_opp_1497mhz: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <4068000 38707200>; + }; + + cpu3_opp_1708mhz: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + cpu3_opp_1900mhz: opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <7216000 43622400>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; From 0293d1d70f162de21fb943a11ec07fbcc7ced5c8 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 21 May 2026 17:21:48 +0530 Subject: [PATCH 1041/1330] arm64: dts: qcom: Update cpufreq node for Shikra SoC Update the cpufreq sclaing node compatible as per the latest bindings. Signed-off-by: Imran Shaik (cherry picked from commit 031b7b80f10d65ccde6e936d02a93fc7a6ffac86) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a555cd818dbda..b262bdec5b3a4 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -67,6 +67,7 @@ next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; operating-points-v2 = <&cpu0_opp_table>; @@ -84,6 +85,7 @@ next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; operating-points-v2 = <&cpu0_opp_table>; @@ -101,6 +103,7 @@ next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; operating-points-v2 = <&cpu0_opp_table>; @@ -118,6 +121,7 @@ next-level-cache = <&l2_3>; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <486>; + clocks = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; operating-points-v2 = <&cpu3_opp_table>; @@ -4317,7 +4321,7 @@ }; cpufreq_hw: cpufreq@fd91000 { - compatible = "qcom,shikra-cpufreq-rimps", "qcom,cpufreq-rimps"; + compatible = "qcom,shikra-epss"; reg = <0x0 0x0fd91000 0x0 0x1000>, <0x0 0x0fd92000 0x0 0x1000>; reg-names = "freq-domain0", @@ -4332,6 +4336,7 @@ "dcvsh-irq-1"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; From 35fa519ca580ed4b4b57cc52041145ea28287f03 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Tue, 28 Apr 2026 15:20:41 +0530 Subject: [PATCH 1042/1330] QCLINUX: arm64: configs: Add Linux software RAID support Enable Linux software RAID support using MD framework. Signed-off-by: Monish Chunara Signed-off-by: Shubham Chouhan (cherry picked from commit 368b163b64fa5087e96efa18d2ff5966162fa269) --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a943d6c7d677e..ae66ecf7fee97 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -341,6 +341,10 @@ CONFIG_PATA_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y CONFIG_MD=y CONFIG_BLK_DEV_MD=m +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y CONFIG_BLK_DEV_DM=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m From ea62f8c8a2330e596b4962ef65ec503920fe4eef Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Wed, 15 Apr 2026 15:23:54 +0530 Subject: [PATCH 1043/1330] QCLINUX: arm64: configs: Enable SmartPQI support Enable SmartPQI support in arm64 configs to provide HW RAID support for systems using SmartPQI-based RAID controllers. Signed-off-by: Monish Chunara Signed-off-by: Sayali Lokhande (cherry picked from commit 6f833a519a5d943447cc937c3f637d9751ebec2c) --- arch/arm64/configs/qcom.config | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 3cfe0efb06c86..60b55f3d2e0a8 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -104,6 +104,18 @@ CONFIG_SCSI_UFS_CRYPTO=y CONFIG_MMC_CRYPTO=y CONFIG_FS_ENCRYPTION=y +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=m +CONFIG_BLK_DEV_BSG=y +# +# SCSI Transports +# +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_SMARTPQI=m + # Support performance profiling CONFIG_FTRACE=y From a0bf5ddbd440b37bd3d563b768b2079dcc899781 Mon Sep 17 00:00:00 2001 From: Aditya Sherawat Date: Mon, 27 Apr 2026 13:34:42 +0530 Subject: [PATCH 1044/1330] ARM: dts: msm: Add support for shikra GPU Add the A704 GPU and GMU wrapper device tree nodes to shikra.dtsi, including register mappings, clock, interconnect, IOMMU, OPP table, and zap shader region. Enable the GPU and set the zap shader firmaware path on all three Shikra board variants (cqm-evk, cqs-evk, iqs-evk). Signed-off-by: Aditya Sherawat (cherry picked from commit 49c407d9328a5949997246857d1860afd8dee1f4) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 8 ++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 8 ++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 8 ++ arch/arm64/boot/dts/qcom/shikra.dtsi | 98 +++++++++++++++++++++ 4 files changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index a8f6d64ea57df..3bd62ba3221d9 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -39,6 +39,14 @@ }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/shikra/a704_zap.mbn"; +}; + &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index f8d9d4ad81f80..8d87a78bd8782 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -38,6 +38,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/shikra/a704_zap.mbn"; +}; + &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 388b006a854b5..687c978be5bfb 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -44,6 +44,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/shikra/a704_zap.mbn"; +}; + &remoteproc_cdsp { firmware-name = "qcom/shikra/cdsp.mbn"; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index b262bdec5b3a4..28176b082e470 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1477,6 +1477,104 @@ }; }; + gpu: gpu@5900000 { + compatible = "qcom,adreno-07000400", "qcom,adreno"; + reg = <0x0 0x05900000 0x0 0x40000>, + <0x0 0x0599e000 0x0 0x1000>, + <0x0 0x05961000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interconnects = <&mem_noc MASTER_GRAPHICS_3D RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0 1>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + qcom,gmu = <&gmu_wrapper>; + + #cooling-cells = <2>; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1142400000 { + opp-hz = /bits/ 64 <1142400000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-peak-kBps = <8171875>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + required-opps = <&rpmpd_opp_turbo>; + opp-peak-kBps = <8171875>; + }; + + opp-921600000 { + opp-hz = /bits/ 64 <921600000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-peak-kBps = <7046875>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <6074218>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + required-opps = <&rpmpd_opp_svs_plus>; + opp-peak-kBps = <5285156>; + }; + + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + required-opps = <&rpmpd_opp_svs>; + opp-peak-kBps = <3972656>; + }; + + opp-355200000 { + opp-hz = /bits/ 64 <355200000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <2136718>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0 0x0596a000 0x0 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + }; + gpucc: clock-controller@5990000 { compatible = "qcom,shikra-gpucc"; reg = <0x0 0x05990000 0x0 0x9000>; From bf1c8ac35d48c1edb1ff5d3e4d8332d4cc6f0b43 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 11 May 2026 16:30:00 +0530 Subject: [PATCH 1045/1330] dt-bindings: regulator: qcom,usb-vbus-regulator: add qcom,pm4125-vbus-reg The pm4125 PMIC uses a different USB VBUS register layout than pm8150b. It uses a 2-bit VBOOST voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V and 5.0 V, instead of a current-limit selector. Move qcom,pm4125-vbus-reg from the pm8150b fallback items list into the standalone enum since the driver handles it with its own match-data and register layout. Make regulator-min/max-microamp conditional so they are only required for current-limit variants (pm8150b, pm6150, pm7250b, pmi632). Add an if/then condition for qcom,pm4125-vbus-reg requiring regulator-min/ max-microvolt instead, and update the pm4125 example accordingly. Signed-off-by: Rakesh Kota (cherry picked from commit a2130ade3dade3c7bf5910ac71f856593975d80c) --- .../regulator/qcom,usb-vbus-regulator.yaml | 47 +++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml index fcefc722ee2a4..d34b378517378 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml @@ -14,6 +14,13 @@ description: | regulator will be enabled in situations where the device is required to provide power to the connected peripheral. + The pm8150b variant uses an OTG current-limit selector, supporting limits + of 500 mA, 1000 mA, 1500 mA, 2000 mA, 2500 mA and 3000 mA. + + The pm4125 variant uses a different register layout with a 2-bit VBOOST + voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V + and 5.0 V. + allOf: - $ref: regulator.yaml# @@ -22,9 +29,9 @@ properties: oneOf: - enum: - qcom,pm8150b-vbus-reg + - qcom,pm4125-vbus-reg - items: - enum: - - qcom,pm4125-vbus-reg - qcom,pm6150-vbus-reg - qcom,pm7250b-vbus-reg - qcom,pmi632-vbus-reg @@ -34,11 +41,33 @@ properties: maxItems: 1 description: VBUS output base address +if: + properties: + compatible: + contains: + enum: + - qcom,pm8150b-vbus-reg + - qcom,pm6150-vbus-reg + - qcom,pm7250b-vbus-reg + - qcom,pmi632-vbus-reg +then: + required: + - regulator-min-microamp + - regulator-max-microamp + +if: + properties: + compatible: + contains: + const: qcom,pm4125-vbus-reg +then: + required: + - regulator-min-microvolt + - regulator-max-microvolt + required: - compatible - reg - - regulator-min-microamp - - regulator-max-microamp unevaluatedProperties: false @@ -55,4 +84,16 @@ examples: regulator-max-microamp = <3000000>; }; }; + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + usb-vbus-regulator@5000 { + compatible = "qcom,pm4125-vbus-reg"; + reg = <0x1100>; + regulator-min-microvolt = <4250000>; + regulator-max-microvolt = <5000000>; + }; + }; ... From 9afa2af9a3c7407e8c3eb4daa296030a8cbf5893 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 11 May 2026 16:32:16 +0530 Subject: [PATCH 1046/1330] regulator: qcom_usb_vbus: add support for qcom,pm4125-vbus-reg The PM4125 PMIC uses a different register layout for USB VBUS control compared to PM8150B. On PM4125, CMD_OTG is at offset 0x50, OTG_CFG is at 0x56, and offset 0x52 is a 2-bit VBOOST voltage selector rather than a current-limit selector. Introduce per-compatible regulator descriptor data to accommodate these differences. This keeps the existing PM8150B current-limit logic intact while adding a dedicated voltage-selector path for PM4125. Signed-off-by: Rakesh Kota (cherry picked from commit 646201a503eaa9eacca97a4370c008c4f7d98706) --- drivers/regulator/qcom_usb_vbus-regulator.c | 102 +++++++++++++++++--- 1 file changed, 88 insertions(+), 14 deletions(-) diff --git a/drivers/regulator/qcom_usb_vbus-regulator.c b/drivers/regulator/qcom_usb_vbus-regulator.c index cd94ed67621fe..3d425452a0b35 100644 --- a/drivers/regulator/qcom_usb_vbus-regulator.c +++ b/drivers/regulator/qcom_usb_vbus-regulator.c @@ -20,10 +20,35 @@ #define OTG_CFG 0x53 #define OTG_EN_SRC_CFG BIT(1) +#define PM4125_CMD_OTG 0x50 +#define PM4125_VBOOST_CFG 0x52 +#define PM4125_VBOOST_CFG_MASK GENMASK(1, 0) +#define PM4125_OTG_CFG 0x56 +#define PM4125_OTG_EN_SRC_CFG BIT(0) + +struct qcom_usb_vbus_reg_data { + u16 cmd_otg; + u16 otg_cfg; + u8 otg_en_src_cfg; + u16 csel_reg; + u8 csel_mask; + const unsigned int *curr_table; + unsigned int n_current_limits; + u16 vsel_reg; + u8 vsel_mask; + const unsigned int *volt_table; + unsigned int n_voltages; + const struct regulator_ops *ops; +}; + static const unsigned int curr_table[] = { 500000, 1000000, 1500000, 2000000, 2500000, 3000000, }; +static const unsigned int pm4125_vboost_table[] = { + 4250000, 4500000, 4750000, 5000000, +}; + static const struct regulator_ops qcom_usb_vbus_reg_ops = { .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, @@ -32,19 +57,43 @@ static const struct regulator_ops qcom_usb_vbus_reg_ops = { .set_current_limit = regulator_set_current_limit_regmap, }; -static struct regulator_desc qcom_usb_vbus_rdesc = { - .name = "usb_vbus", - .ops = &qcom_usb_vbus_reg_ops, - .owner = THIS_MODULE, - .type = REGULATOR_VOLTAGE, +static const struct regulator_ops qcom_usb_vbus_pm4125_reg_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .list_voltage = regulator_list_voltage_table, +}; + +static const struct qcom_usb_vbus_reg_data pm8150b_data = { + .cmd_otg = CMD_OTG, + .otg_cfg = OTG_CFG, + .otg_en_src_cfg = OTG_EN_SRC_CFG, + .csel_reg = OTG_CURRENT_LIMIT_CFG, + .csel_mask = OTG_CURRENT_LIMIT_MASK, .curr_table = curr_table, .n_current_limits = ARRAY_SIZE(curr_table), + .ops = &qcom_usb_vbus_reg_ops, +}; + +static const struct qcom_usb_vbus_reg_data pm4125_data = { + .cmd_otg = PM4125_CMD_OTG, + .otg_cfg = PM4125_OTG_CFG, + .otg_en_src_cfg = PM4125_OTG_EN_SRC_CFG, + .vsel_reg = PM4125_VBOOST_CFG, + .vsel_mask = PM4125_VBOOST_CFG_MASK, + .volt_table = pm4125_vboost_table, + .n_voltages = ARRAY_SIZE(pm4125_vboost_table), + .ops = &qcom_usb_vbus_pm4125_reg_ops, }; static int qcom_usb_vbus_regulator_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + const struct qcom_usb_vbus_reg_data *data; struct regulator_dev *rdev; + struct regulator_desc *rdesc; struct regmap *regmap; struct regulator_config config = { }; struct regulator_init_data *init_data; @@ -57,27 +106,51 @@ static int qcom_usb_vbus_regulator_probe(struct platform_device *pdev) return ret; } + data = of_device_get_match_data(dev); + if (!data) + return -EINVAL; + regmap = dev_get_regmap(dev->parent, NULL); if (!regmap) { dev_err(dev, "Failed to get regmap\n"); return -ENOENT; } - init_data = of_get_regulator_init_data(dev, dev->of_node, - &qcom_usb_vbus_rdesc); + rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); + if (!rdesc) + return -ENOMEM; + + rdesc->name = "usb_vbus"; + rdesc->ops = data->ops; + rdesc->owner = THIS_MODULE; + rdesc->type = REGULATOR_VOLTAGE; + rdesc->enable_reg = base + data->cmd_otg; + rdesc->enable_mask = OTG_EN; + + if (data->curr_table) { + rdesc->curr_table = data->curr_table; + rdesc->n_current_limits = data->n_current_limits; + rdesc->csel_reg = base + data->csel_reg; + rdesc->csel_mask = data->csel_mask; + } + + if (data->volt_table) { + rdesc->volt_table = data->volt_table; + rdesc->n_voltages = data->n_voltages; + rdesc->vsel_reg = base + data->vsel_reg; + rdesc->vsel_mask = data->vsel_mask; + } + + init_data = of_get_regulator_init_data(dev, dev->of_node, rdesc); if (!init_data) return -ENOMEM; - qcom_usb_vbus_rdesc.enable_reg = base + CMD_OTG; - qcom_usb_vbus_rdesc.enable_mask = OTG_EN; - qcom_usb_vbus_rdesc.csel_reg = base + OTG_CURRENT_LIMIT_CFG; - qcom_usb_vbus_rdesc.csel_mask = OTG_CURRENT_LIMIT_MASK; config.dev = dev; config.init_data = init_data; config.of_node = dev->of_node; config.regmap = regmap; - rdev = devm_regulator_register(dev, &qcom_usb_vbus_rdesc, &config); + rdev = devm_regulator_register(dev, rdesc, &config); if (IS_ERR(rdev)) { ret = PTR_ERR(rdev); dev_err(dev, "not able to register vbus reg %d\n", ret); @@ -85,13 +158,14 @@ static int qcom_usb_vbus_regulator_probe(struct platform_device *pdev) } /* Disable HW logic for VBUS enable */ - regmap_update_bits(regmap, base + OTG_CFG, OTG_EN_SRC_CFG, 0); + regmap_update_bits(regmap, base + data->otg_cfg, data->otg_en_src_cfg, 0); return 0; } static const struct of_device_id qcom_usb_vbus_regulator_match[] = { - { .compatible = "qcom,pm8150b-vbus-reg" }, + { .compatible = "qcom,pm8150b-vbus-reg", .data = &pm8150b_data }, + { .compatible = "qcom,pm4125-vbus-reg", .data = &pm4125_data }, { } }; MODULE_DEVICE_TABLE(of, qcom_usb_vbus_regulator_match); From 89b6be32594a45042dc6512a8d8a690763f0dd20 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 14 May 2026 18:29:02 +0530 Subject: [PATCH 1047/1330] FROMLIST: dt-bindings: crypto: qcom,prng: Document Shikra TRNG Document shikra compatible for the True Random Number Generator. Link: https://lore.kernel.org/lkml/20260514-shikra_rng-v1-1-4ea721a1429a@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh (cherry picked from commit c49a117e27d2ef929ca36cff97c7088de3a40b90) --- Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml index 498d6914135e8..e2430280b2a3b 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -28,6 +28,7 @@ properties: - qcom,sa8255p-trng - qcom,sa8775p-trng - qcom,sc7280-trng + - qcom,shikra-trng - qcom,sm8450-trng - qcom,sm8550-trng - qcom,sm8650-trng From f174f0808df1f3c1eec7b42d878b8f3758121890 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 15 May 2026 00:03:03 +0530 Subject: [PATCH 1048/1330] FROMLIST: dt-bindings: crypto: qcom-qce: Document the Shikra crypto engine Document the crypto engine on the Shikra platform. Link:https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-1-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh (cherry picked from commit 229f15f7bc8377a1c6675f8691a88ca4cecf4a7c) --- Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index 0b62271f8bfe5..07b2cc5c6a5b0 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -51,6 +51,7 @@ properties: - qcom,qcs8300-qce - qcom,sa8775p-qce - qcom,sc7280-qce + - qcom,shikra-qce - qcom,sm6350-qce - qcom,sm8250-qce - qcom,sm8350-qce From 8f065cf397834e6d1aaa8cffd03e19a6a5784567 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 15 May 2026 00:03:58 +0530 Subject: [PATCH 1049/1330] dt-bindings: bam-dma: Increase maxItems to seven for iommus Shikra bam dma engine support seven iommu entries. Increase maxItems property for iommus to pass dtbs_check errors. Link: https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-2-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh (cherry picked from commit ae135e78e720d433901be668a4848ab6c97d7fa5) --- Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 6493a6968bb4b..ffdb308352c3f 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -46,7 +46,7 @@ properties: iommus: minItems: 1 - maxItems: 6 + maxItems: 7 num-channels: $ref: /schemas/types.yaml#/definitions/uint32 From eb2add2e7c940f3da032c226681cdbbfc91ca294 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 13 May 2026 18:00:30 +0530 Subject: [PATCH 1050/1330] dt-bindings: crypto: qcom,inline-crypto-engine: Document Shikra ICE Document the Inline Crypto Engine (ICE) on the Shikra platform. Signed-off-by: Kuldeep Singh (cherry picked from commit 27e68f5e018f03c58d6f078e041402bbcded7441) --- .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index a87db21fc900d..79161c8e583d9 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -19,6 +19,7 @@ properties: - qcom,sa8775p-inline-crypto-engine - qcom,sc7180-inline-crypto-engine - qcom,sc7280-inline-crypto-engine + - qcom,shikra-inline-crypto-engine - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine From 833539a39f662c1f2869da4390f761440ab9a5c0 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 8 May 2026 17:21:41 +0530 Subject: [PATCH 1051/1330] clk: qcom: common: Register reset controller only when resets are present Some clock controller descriptors do not provide any reset lines. Avoid registering a reset controller when desc->num_resets is zero by making the registration conditional. Signed-off-by: Imran Shaik (cherry picked from commit b4453e43b8483d4db25a48f051306cda238a1959) --- drivers/clk/qcom/common.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 2c09abaf1d2a1..d6ff83045da8f 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -359,17 +359,19 @@ int qcom_cc_really_probe(struct device *dev, qcom_cc_clk_regs_configure(dev, desc->driver_data, regmap); } - reset = &cc->reset; - reset->rcdev.of_node = dev->of_node; - reset->rcdev.ops = &qcom_reset_ops; - reset->rcdev.owner = dev->driver->owner; - reset->rcdev.nr_resets = desc->num_resets; - reset->regmap = regmap; - reset->reset_map = desc->resets; - - ret = devm_reset_controller_register(dev, &reset->rcdev); - if (ret) - goto put_rpm; + if (desc->num_resets) { + reset = &cc->reset; + reset->rcdev.of_node = dev->of_node; + reset->rcdev.ops = &qcom_reset_ops; + reset->rcdev.owner = dev->driver->owner; + reset->rcdev.nr_resets = desc->num_resets; + reset->regmap = regmap; + reset->reset_map = desc->resets; + + ret = devm_reset_controller_register(dev, &reset->rcdev); + if (ret) + goto put_rpm; + } if (desc->gdscs && desc->num_gdscs) { scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); From 6dc743aca400aa57ba014cf05b7c1eddf9183fba Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Tue, 12 May 2026 18:41:56 +0530 Subject: [PATCH 1052/1330] clk: qcom: common: Skip NULL clock hw entries during registration Some Qualcomm clock controller descriptors may contain NULL entries in the clk_hws array. Skip such entries when registering clock hardware to avoid passing NULL pointers to the clock framework. Signed-off-by: Imran Shaik (cherry picked from commit 60f8617425f987fba5ef7c9e250d2dad16e4a271) --- drivers/clk/qcom/common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index d6ff83045da8f..23987130c23fa 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -408,6 +408,9 @@ int qcom_cc_really_probe(struct device *dev, qcom_cc_drop_protected(dev, cc); for (i = 0; i < num_clk_hws; i++) { + if (!clk_hws[i]) + continue; + ret = devm_clk_hw_register(dev, clk_hws[i]); if (ret) goto put_rpm; From d60401a3c307544bad74ec3762cdb80223aeed50 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 7 May 2026 14:05:07 +0530 Subject: [PATCH 1053/1330] dt-bindings: clock: qcom: Add GCC LPASS clocks support for Shikra Add GCC LPASS clocks support for Qualcomm Shikra SoC. Signed-off-by: Imran Shaik (cherry picked from commit c156bd1fb5290dca75491534e18b59e6af44667c) --- include/dt-bindings/clock/qcom,shikra-gcc.h | 203 ++++++++++---------- 1 file changed, 103 insertions(+), 100 deletions(-) diff --git a/include/dt-bindings/clock/qcom,shikra-gcc.h b/include/dt-bindings/clock/qcom,shikra-gcc.h index 2e88a9cd9f535..dc55e5652caae 100644 --- a/include/dt-bindings/clock/qcom,shikra-gcc.h +++ b/include/dt-bindings/clock/qcom,shikra-gcc.h @@ -119,106 +119,109 @@ #define GCC_GPU_CFG_AHB_CLK 109 #define GCC_GPU_GPLL0_CLK_SRC 110 #define GCC_GPU_GPLL0_DIV_CLK_SRC 111 -#define GCC_GPU_MEMNOC_GFX_CLK 112 -#define GCC_GPU_SMMU_VOTE_CLK 113 -#define GCC_GPU_SNOC_DVM_GFX_CLK 114 -#define GCC_GPU_THROTTLE_CORE_CLK 115 -#define GCC_MMU_TCU_VOTE_CLK 116 -#define GCC_PCIE_AUX_CLK 117 -#define GCC_PCIE_AUX_CLK_SRC 118 -#define GCC_PCIE_AUX_PHY_CLK_SRC 119 -#define GCC_PCIE_CFG_AHB_CLK 120 -#define GCC_PCIE_CLKREF_EN 121 -#define GCC_PCIE_MSTR_AXI_CLK 122 -#define GCC_PCIE_PIPE_CLK 123 -#define GCC_PCIE_PIPE_CLK_SRC 124 -#define GCC_PCIE_RCHNG_PHY_CLK 125 -#define GCC_PCIE_RCHNG_PHY_CLK_SRC 126 -#define GCC_PCIE_SLEEP_CLK 127 -#define GCC_PCIE_SLV_AXI_CLK 128 -#define GCC_PCIE_SLV_Q2A_AXI_CLK 129 -#define GCC_PCIE_TBU_CLK 130 -#define GCC_PCIE_THROTTLE_CORE_CLK 131 -#define GCC_PCIE_THROTTLE_XO_CLK 132 -#define GCC_PCIE_TILE_AXI_SYS_NOC_CLK 133 -#define GCC_PDM2_CLK 134 -#define GCC_PDM2_CLK_SRC 135 -#define GCC_PDM_AHB_CLK 136 -#define GCC_PDM_XO4_CLK 137 -#define GCC_PWM0_XO512_CLK 138 -#define GCC_QMIP_CAMERA_NRT_AHB_CLK 139 -#define GCC_QMIP_CAMERA_RT_AHB_CLK 140 -#define GCC_QMIP_DISP_AHB_CLK 141 -#define GCC_QMIP_GPU_CFG_AHB_CLK 142 -#define GCC_QMIP_PCIE_CFG_AHB_CLK 143 -#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 144 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 145 -#define GCC_QUPV3_WRAP0_CORE_CLK 146 -#define GCC_QUPV3_WRAP0_S0_CLK 147 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 148 -#define GCC_QUPV3_WRAP0_S1_CLK 149 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 150 -#define GCC_QUPV3_WRAP0_S2_CLK 151 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 152 -#define GCC_QUPV3_WRAP0_S3_CLK 153 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 154 -#define GCC_QUPV3_WRAP0_S4_CLK 155 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 156 -#define GCC_QUPV3_WRAP0_S5_CLK 157 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 158 -#define GCC_QUPV3_WRAP0_S6_CLK 159 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 160 -#define GCC_QUPV3_WRAP0_S7_CLK 161 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 162 -#define GCC_QUPV3_WRAP0_S8_CLK 163 -#define GCC_QUPV3_WRAP0_S8_CLK_SRC 164 -#define GCC_QUPV3_WRAP0_S9_CLK 165 -#define GCC_QUPV3_WRAP0_S9_CLK_SRC 166 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 167 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 168 -#define GCC_SDCC1_AHB_CLK 169 -#define GCC_SDCC1_APPS_CLK 170 -#define GCC_SDCC1_APPS_CLK_SRC 171 -#define GCC_SDCC1_ICE_CORE_CLK 172 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 -#define GCC_SDCC2_AHB_CLK 174 -#define GCC_SDCC2_APPS_CLK 175 -#define GCC_SDCC2_APPS_CLK_SRC 176 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 177 -#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 178 -#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 179 -#define GCC_TSCSS_AHB_CLK 180 -#define GCC_TSCSS_CLK_SRC 181 -#define GCC_TSCSS_CNTR_CLK 182 -#define GCC_TSCSS_ETU_CLK 183 -#define GCC_UFS_CLKREF_EN 184 -#define GCC_USB20_MASTER_CLK 185 -#define GCC_USB20_MASTER_CLK_SRC 186 -#define GCC_USB20_MOCK_UTMI_CLK 187 -#define GCC_USB20_MOCK_UTMI_CLK_SRC 188 -#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 189 -#define GCC_USB20_SLEEP_CLK 190 -#define GCC_USB30_PRIM_MASTER_CLK 191 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 192 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 193 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 194 -#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 195 -#define GCC_USB30_PRIM_SLEEP_CLK 196 -#define GCC_USB3_PRIM_CLKREF_EN 197 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 198 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 199 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 200 -#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 201 -#define GCC_VCODEC0_AXI_CLK 202 -#define GCC_VENUS_AHB_CLK 203 -#define GCC_VENUS_CTL_AXI_CLK 204 -#define GCC_VIDEO_AHB_CLK 205 -#define GCC_VIDEO_AXI0_CLK 206 -#define GCC_VIDEO_THROTTLE_CORE_CLK 207 -#define GCC_VIDEO_VCODEC0_SYS_CLK 208 -#define GCC_VIDEO_VENUS_CLK_SRC 209 -#define GCC_VIDEO_VENUS_CTL_CLK 210 -#define GCC_VIDEO_XO_CLK 211 +#define GCC_GPU_IREF_CLK 112 +#define GCC_GPU_MEMNOC_GFX_CLK 113 +#define GCC_GPU_SMMU_VOTE_CLK 114 +#define GCC_GPU_SNOC_DVM_GFX_CLK 115 +#define GCC_GPU_THROTTLE_CORE_CLK 116 +#define GCC_LPASS_CONFIG_CLK 117 +#define GCC_LPASS_CORE_AXIM_CLK 118 +#define GCC_MMU_TCU_VOTE_CLK 119 +#define GCC_PCIE_AUX_CLK 120 +#define GCC_PCIE_AUX_CLK_SRC 121 +#define GCC_PCIE_AUX_PHY_CLK_SRC 122 +#define GCC_PCIE_CFG_AHB_CLK 123 +#define GCC_PCIE_CLKREF_EN 124 +#define GCC_PCIE_MSTR_AXI_CLK 125 +#define GCC_PCIE_PIPE_CLK 126 +#define GCC_PCIE_PIPE_CLK_SRC 127 +#define GCC_PCIE_RCHNG_PHY_CLK 128 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 129 +#define GCC_PCIE_SLEEP_CLK 130 +#define GCC_PCIE_SLV_AXI_CLK 131 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 132 +#define GCC_PCIE_TBU_CLK 133 +#define GCC_PCIE_THROTTLE_CORE_CLK 134 +#define GCC_PCIE_THROTTLE_XO_CLK 135 +#define GCC_PCIE_TILE_AXI_SYS_NOC_CLK 136 +#define GCC_PDM2_CLK 137 +#define GCC_PDM2_CLK_SRC 138 +#define GCC_PDM_AHB_CLK 139 +#define GCC_PDM_XO4_CLK 140 +#define GCC_PWM0_XO512_CLK 141 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 142 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 143 +#define GCC_QMIP_DISP_AHB_CLK 144 +#define GCC_QMIP_GPU_CFG_AHB_CLK 145 +#define GCC_QMIP_PCIE_CFG_AHB_CLK 146 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 147 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 148 +#define GCC_QUPV3_WRAP0_CORE_CLK 149 +#define GCC_QUPV3_WRAP0_S0_CLK 150 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 151 +#define GCC_QUPV3_WRAP0_S1_CLK 152 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 153 +#define GCC_QUPV3_WRAP0_S2_CLK 154 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 155 +#define GCC_QUPV3_WRAP0_S3_CLK 156 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 157 +#define GCC_QUPV3_WRAP0_S4_CLK 158 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 159 +#define GCC_QUPV3_WRAP0_S5_CLK 160 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 161 +#define GCC_QUPV3_WRAP0_S6_CLK 162 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 163 +#define GCC_QUPV3_WRAP0_S7_CLK 164 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 165 +#define GCC_QUPV3_WRAP0_S8_CLK 166 +#define GCC_QUPV3_WRAP0_S8_CLK_SRC 167 +#define GCC_QUPV3_WRAP0_S9_CLK 168 +#define GCC_QUPV3_WRAP0_S9_CLK_SRC 169 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 170 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 171 +#define GCC_SDCC1_AHB_CLK 172 +#define GCC_SDCC1_APPS_CLK 173 +#define GCC_SDCC1_APPS_CLK_SRC 174 +#define GCC_SDCC1_ICE_CORE_CLK 175 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 176 +#define GCC_SDCC2_AHB_CLK 177 +#define GCC_SDCC2_APPS_CLK 178 +#define GCC_SDCC2_APPS_CLK_SRC 179 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 180 +#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 181 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 182 +#define GCC_TSCSS_AHB_CLK 183 +#define GCC_TSCSS_CLK_SRC 184 +#define GCC_TSCSS_CNTR_CLK 185 +#define GCC_TSCSS_ETU_CLK 186 +#define GCC_UFS_CLKREF_EN 187 +#define GCC_USB20_MASTER_CLK 188 +#define GCC_USB20_MASTER_CLK_SRC 189 +#define GCC_USB20_MOCK_UTMI_CLK 190 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 191 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 192 +#define GCC_USB20_SLEEP_CLK 193 +#define GCC_USB30_PRIM_MASTER_CLK 194 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 195 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 196 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 197 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 198 +#define GCC_USB30_PRIM_SLEEP_CLK 199 +#define GCC_USB3_PRIM_CLKREF_EN 200 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 201 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 202 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 203 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 204 +#define GCC_VCODEC0_AXI_CLK 205 +#define GCC_VENUS_AHB_CLK 206 +#define GCC_VENUS_CTL_AXI_CLK 207 +#define GCC_VIDEO_AHB_CLK 208 +#define GCC_VIDEO_AXI0_CLK 209 +#define GCC_VIDEO_THROTTLE_CORE_CLK 210 +#define GCC_VIDEO_VCODEC0_SYS_CLK 211 +#define GCC_VIDEO_VENUS_CLK_SRC 212 +#define GCC_VIDEO_VENUS_CTL_CLK 213 +#define GCC_VIDEO_XO_CLK 214 /* GCC power domains */ #define GCC_CAMSS_TOP_GDSC 0 From 62d08bed5142496e1a5f1aba8c3eca6e90c3a8e1 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 7 May 2026 14:05:30 +0530 Subject: [PATCH 1054/1330] clk: qcom: gcc-shikra: Mark GCC LPASS clocks as critical The GCC LPASS clocks must be enabled to access audio core clock controller registers. Hence, mark them as critical on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik (cherry picked from commit d50c17ecd4f43acf04e58f48d0a6b101da77a9b5) --- drivers/clk/qcom/gcc-shikra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/gcc-shikra.c b/drivers/clk/qcom/gcc-shikra.c index 8834618354882..65cd42e0334de 100644 --- a/drivers/clk/qcom/gcc-shikra.c +++ b/drivers/clk/qcom/gcc-shikra.c @@ -4347,6 +4347,8 @@ static u32 gcc_shikra_critical_cbcrs[] = { 0x1702c, /* GCC_DISP_XO_CLK */ 0x36004, /* GCC_GPU_CFG_AHB_CLK */ 0x36100, /* GCC_GPU_IREF_CLK */ + 0x3a00c, /* GCC_LPASS_CONFIG_CLK */ + 0x3a008, /* GCC_LPASS_CORE_AXIM_CLK */ 0x79004, /* GCC_SYS_NOC_CPUSS_AHB_CLK */ 0x17004, /* GCC_VIDEO_AHB_CLK */ 0x17024, /* GCC_VIDEO_XO_CLK */ From a4f7e26d8ad394a021021b801d28be60f36eac47 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 7 May 2026 14:35:05 +0530 Subject: [PATCH 1055/1330] dt-bindings: clock: qcom: Add Qualcomm Shikra Audio Core Clock Controller Add device tree bindings for the Audio Core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik (cherry picked from commit e9a447d1963eaaa9e9c4f79fd0cf092d1eb8f37e) --- .../clock/qcom,shikra-audiocorecc.yaml | 62 +++++++++++++++++++ .../clock/qcom,shikra-audiocorecc.h | 49 +++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml create mode 100644 include/dt-bindings/clock/qcom,shikra-audiocorecc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml new file mode 100644 index 0000000000000..2ed1d9d871175 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-audiocorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio Core Clock & Reset Controller for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + +description: | + Audio core clock control module provides the clocks and resets + on Qualcomm Shikra SoC platform. + + See also: + - include/dt-bindings/clock/qcom,shikra-audiocorecc.h + +properties: + compatible: + enum: + - qcom,shikra-cqm-audiocorecc + - qcom,shikra-cqs-audiocorecc + + clocks: + items: + - description: Board XO source + - description: Board sleep clock + - description: Audio ref clock source + + reg: + maxItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + #include + clock-controller@a0a0000 { + compatible = "qcom,shikra-cqm-audiocorecc"; + reg = <0x0a0a0000 0x10000>, + <0x0a0b4000 0x1000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&aud_ref_clk_src>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,shikra-audiocorecc.h b/include/dt-bindings/clock/qcom,shikra-audiocorecc.h new file mode 100644 index 0000000000000..bc77d7a3946ea --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-audiocorecc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H + +/* AUDIO_CORE_CC clocks */ +#define AUDIO_CORE_CC_DIG_PLL 0 +#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX 1 +#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX2 2 +#define AUDIO_CORE_CC_AIF_IF0_CLK_SRC 3 +#define AUDIO_CORE_CC_AIF_IF0_EBIT_CLK 4 +#define AUDIO_CORE_CC_AIF_IF0_IBIT_CLK 5 +#define AUDIO_CORE_CC_AIF_IF1_CLK_SRC 6 +#define AUDIO_CORE_CC_AIF_IF1_EBIT_CLK 7 +#define AUDIO_CORE_CC_AIF_IF1_IBIT_CLK 8 +#define AUDIO_CORE_CC_AIF_IF2_CLK_SRC 9 +#define AUDIO_CORE_CC_AIF_IF2_EBIT_CLK 10 +#define AUDIO_CORE_CC_AIF_IF2_IBIT_CLK 11 +#define AUDIO_CORE_CC_AIF_IF3_CLK_SRC 12 +#define AUDIO_CORE_CC_AIF_IF3_EBIT_CLK 13 +#define AUDIO_CORE_CC_AIF_IF3_IBIT_CLK 14 +#define AUDIO_CORE_CC_AUD_DMA_CLK 15 +#define AUDIO_CORE_CC_AUD_DMA_CLK_SRC 16 +#define AUDIO_CORE_CC_AUD_DMA_MEM_CLK 17 +#define AUDIO_CORE_CC_BUS_CLK 18 +#define AUDIO_CORE_CC_BUS_CLK_SRC 19 +#define AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC 20 +#define AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC 21 +#define AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK 22 +#define AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC 23 +#define AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK 24 +#define AUDIO_CORE_CC_IM_SLEEP_CLK 25 +#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK 26 +#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC 27 +#define AUDIO_CORE_CC_RX_MCLK_2X_CLK 28 +#define AUDIO_CORE_CC_RX_MCLK_CLK 29 +#define AUDIO_CORE_CC_SAMPLING_CLK 30 +#define AUDIO_CORE_CC_TX_MCLK_2X_CLK 31 +#define AUDIO_CORE_CC_TX_MCLK_CLK 32 +#define AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC 33 + +/* AUDIO_CORE_CC resets */ +#define AUDIO_CORE_CSR_RX_SWR_CGCR 0 +#define AUDIO_CORE_CSR_TX_SWR_CGCR 1 + +#endif From 57af51c95842c568635687f4740dac0764785a20 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Wed, 6 May 2026 16:57:36 +0530 Subject: [PATCH 1056/1330] clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC Add support for Audio core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik (cherry picked from commit 69178895bed538d722366692f8a4d5b6cdc40327) --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/audiocorecc-shikra.c | 815 ++++++++++++++++++++++++++ 3 files changed, 827 insertions(+) create mode 100644 drivers/clk/qcom/audiocorecc-shikra.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index f6ac47a88f21f..775ee9a9c4ae2 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -165,6 +165,17 @@ config CLK_NORD_GCC SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination of GCC, SE_GCC, NE_GCC and NW_GCC. +config CLK_SHIKRA_AUDIOCORECC + tristate "Shikra Audio Core Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_SHIKRA_GCC + default m if ARCH_QCOM + help + Support for the Audio Core clock controller on Qualcomm Technologies, Inc + Shikra devices. + Say Y if you want to use AudioCoreCC clocks required to support audio + devices and it's functionality. + config CLK_SHIKRA_DISPCC tristate "Shikra Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 412b87dac32e7..343da4e9113aa 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o +obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) += audiocorecc-shikra.o obj-$(CONFIG_CLK_SHIKRA_DISPCC) += dispcc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GPUCC) += gpucc-shikra.o diff --git a/drivers/clk/qcom/audiocorecc-shikra.c b/drivers/clk/qcom/audiocorecc-shikra.c new file mode 100644 index 0000000000000..f7655b2cbd458 --- /dev/null +++ b/drivers/clk/qcom/audiocorecc-shikra.c @@ -0,0 +1,815 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_AUD_REF_CLK_SRC, +}; + +enum { + P_AUD_REF_CLK_SRC, + P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, + P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, + P_BI_TCXO, + P_SLEEP_CLK, +}; + +static const struct pll_vco spark_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +/* 614.4 MHz Configuration */ +static const struct alpha_pll_config audio_core_cc_dig_pll_config = { + .l = 0x20, + .alpha = 0x0, + .vco_val = BIT(21), + .post_div_val = 0x28100, + .post_div_mask = GENMASK(17, 8), + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .aux2_output_mask = BIT(2), + .config_ctl_val = 0x4001055b, + .test_ctl_hi_val = 0x1, + .test_ctl_hi_mask = 0x1, +}; + +static struct clk_alpha_pll audio_core_cc_dig_pll = { + .offset = 0x0, + .config = &audio_core_cc_dig_pll_config, + .vco_table = spark_vco, + .num_vco = ARRAY_SIZE(spark_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_dig_pll", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux = { + .mult = 1, + .div = 5, + .hw.init = &(struct clk_init_data) { + .name = "audio_core_cc_dig_pll_out_aux", + .parent_data = &(const struct clk_parent_data) { + .hw = &audio_core_cc_dig_pll.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data) { + .name = "audio_core_cc_dig_pll_out_aux2", + .parent_data = &(const struct clk_parent_data) { + .hw = &audio_core_cc_dig_pll.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, + }, +}; + +static const struct parent_map audio_core_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_AUD_REF_CLK_SRC, 1 }, + { P_SLEEP_CLK, 2 }, + { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4 }, + { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 6 }, +}; + +static const struct clk_parent_data audio_core_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_AUD_REF_CLK_SRC }, + { .index = DT_SLEEP_CLK }, + { .hw = &audio_core_cc_dig_pll_out_aux.hw }, + { .hw = &audio_core_cc_dig_pll_out_aux2.hw }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aif_if0_clk_src[] = { + F(240000, P_BI_TCXO, 10, 1, 8), + F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32), + F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16), + F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16), + F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8), + F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8), + F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4), + F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4), + F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2), + F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2), + F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0), + F(9600000, P_BI_TCXO, 2, 0, 0), + F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aif_if0_clk_src = { + .cmd_rcgr = 0x104c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if0_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_aif_if1_clk_src = { + .cmd_rcgr = 0x10b0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if1_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_aif_if2_clk_src = { + .cmd_rcgr = 0x1114, + .mnd_width = 16, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if2_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aif_if3_clk_src[] = { + F(240000, P_BI_TCXO, 10, 1, 8), + F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32), + F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16), + F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16), + F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8), + F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8), + F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4), + F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4), + F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2), + F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2), + F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0), + F(9600000, P_BI_TCXO, 2, 0, 0), + F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + F(49152000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aif_if3_clk_src = { + .cmd_rcgr = 0x1178, + .mnd_width = 16, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_aif_if3_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if3_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aud_dma_clk_src[] = { + F(102400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 3, 0, 0), + F(153600000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 2, 0, 0), + F(307200000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 1, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aud_dma_clk_src = { + .cmd_rcgr = 0x1028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_aud_dma_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aud_dma_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_bus_clk_src[] = { + F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0), + F(76800000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 4, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_bus_clk_src = { + .cmd_rcgr = 0x1008, + .mnd_width = 0, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_bus_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_bus_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_ext_mclka_clk_src = { + .cmd_rcgr = 0x123c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_ext_mclka_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_ext_mclkb_clk_src = { + .cmd_rcgr = 0x125c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_ext_mclkb_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_lpaif_pcmoe_clk_src[] = { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(15360000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 8, 0, 0), + F(30720000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4, 0, 0), + F(61440000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_lpaif_pcmoe_clk_src = { + .cmd_rcgr = 0x12ac, + .mnd_width = 8, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_lpaif_pcmoe_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_lpaif_pcmoe_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_tx_mclk_rcg_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_tx_mclk_rcg_clk_src = { + .cmd_rcgr = 0x127c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = audio_core_cc_parent_map_0, + .freq_tbl = ftbl_audio_core_cc_tx_mclk_rcg_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_tx_mclk_rcg_clk_src", + .parent_data = audio_core_cc_parent_data_0, + .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div audio_core_cc_cdiv_tx_mclk_div_clk_src = { + .reg = 0x129c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_cdiv_tx_mclk_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch audio_core_cc_aif_if0_ebit_clk = { + .halt_reg = 0x1068, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if0_ebit_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if0_ibit_clk = { + .halt_reg = 0x1064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if0_ibit_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_aif_if0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if1_ebit_clk = { + .halt_reg = 0x10cc, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if1_ebit_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if1_ibit_clk = { + .halt_reg = 0x10c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10c8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if1_ibit_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_aif_if1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if2_ebit_clk = { + .halt_reg = 0x1130, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if2_ebit_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if2_ibit_clk = { + .halt_reg = 0x112c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x112c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if2_ibit_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_aif_if2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if3_ebit_clk = { + .halt_reg = 0x1194, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1194, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if3_ebit_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if3_ibit_clk = { + .halt_reg = 0x1190, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1190, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aif_if3_ibit_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_aif_if3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aud_dma_clk = { + .halt_reg = 0x1040, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aud_dma_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_aud_dma_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aud_dma_mem_clk = { + .halt_reg = 0x1044, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1044, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_aud_dma_mem_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_aud_dma_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_bus_clk = { + .halt_reg = 0x1020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_bus_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_bus_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_ext_mclka_out_clk = { + .halt_reg = 0x1254, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1254, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_ext_mclka_out_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_ext_mclka_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_ext_mclkb_out_clk = { + .halt_reg = 0x1274, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1274, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_ext_mclkb_out_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_ext_mclkb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_im_sleep_clk = { + .halt_reg = 0x12cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_im_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_lpaif_pcmoe_clk = { + .halt_reg = 0x12c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12c4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_lpaif_pcmoe_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_lpaif_pcmoe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_rx_mclk_2x_clk = { + .halt_reg = 0x1298, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1298, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_rx_mclk_2x_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_rx_mclk_clk = { + .halt_reg = 0x12a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_rx_mclk_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_sampling_clk = { + .halt_reg = 0x1000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_sampling_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_tx_mclk_2x_clk = { + .halt_reg = 0x1294, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1294, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_tx_mclk_2x_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_tx_mclk_clk = { + .halt_reg = 0x12a0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "audio_core_cc_tx_mclk_clk", + .parent_hws = (const struct clk_hw*[]) { + &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_hw *audio_core_cc_shikra_hws[] = { + [AUDIO_CORE_CC_DIG_PLL_OUT_AUX] = &audio_core_cc_dig_pll_out_aux.hw, + [AUDIO_CORE_CC_DIG_PLL_OUT_AUX2] = &audio_core_cc_dig_pll_out_aux2.hw, +}; + +static struct clk_regmap *audio_core_cc_shikra_clocks[] = { + [AUDIO_CORE_CC_AIF_IF0_CLK_SRC] = &audio_core_cc_aif_if0_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF0_EBIT_CLK] = &audio_core_cc_aif_if0_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF0_IBIT_CLK] = &audio_core_cc_aif_if0_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF1_CLK_SRC] = &audio_core_cc_aif_if1_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF1_EBIT_CLK] = &audio_core_cc_aif_if1_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF1_IBIT_CLK] = &audio_core_cc_aif_if1_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF2_CLK_SRC] = &audio_core_cc_aif_if2_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF2_EBIT_CLK] = &audio_core_cc_aif_if2_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF2_IBIT_CLK] = &audio_core_cc_aif_if2_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF3_CLK_SRC] = &audio_core_cc_aif_if3_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF3_EBIT_CLK] = &audio_core_cc_aif_if3_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF3_IBIT_CLK] = &audio_core_cc_aif_if3_ibit_clk.clkr, + [AUDIO_CORE_CC_AUD_DMA_CLK] = &audio_core_cc_aud_dma_clk.clkr, + [AUDIO_CORE_CC_AUD_DMA_CLK_SRC] = &audio_core_cc_aud_dma_clk_src.clkr, + [AUDIO_CORE_CC_AUD_DMA_MEM_CLK] = &audio_core_cc_aud_dma_mem_clk.clkr, + [AUDIO_CORE_CC_BUS_CLK] = &audio_core_cc_bus_clk.clkr, + [AUDIO_CORE_CC_BUS_CLK_SRC] = &audio_core_cc_bus_clk_src.clkr, + [AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC] = &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr, + [AUDIO_CORE_CC_DIG_PLL] = &audio_core_cc_dig_pll.clkr, + [AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC] = &audio_core_cc_ext_mclka_clk_src.clkr, + [AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK] = &audio_core_cc_ext_mclka_out_clk.clkr, + [AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC] = &audio_core_cc_ext_mclkb_clk_src.clkr, + [AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK] = &audio_core_cc_ext_mclkb_out_clk.clkr, + [AUDIO_CORE_CC_IM_SLEEP_CLK] = &audio_core_cc_im_sleep_clk.clkr, + [AUDIO_CORE_CC_LPAIF_PCMOE_CLK] = &audio_core_cc_lpaif_pcmoe_clk.clkr, + [AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC] = &audio_core_cc_lpaif_pcmoe_clk_src.clkr, + [AUDIO_CORE_CC_RX_MCLK_2X_CLK] = &audio_core_cc_rx_mclk_2x_clk.clkr, + [AUDIO_CORE_CC_RX_MCLK_CLK] = &audio_core_cc_rx_mclk_clk.clkr, + [AUDIO_CORE_CC_SAMPLING_CLK] = &audio_core_cc_sampling_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_2X_CLK] = &audio_core_cc_tx_mclk_2x_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_CLK] = &audio_core_cc_tx_mclk_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC] = &audio_core_cc_tx_mclk_rcg_clk_src.clkr, +}; + +static struct clk_alpha_pll *audio_core_cc_shikra_plls[] = { + &audio_core_cc_dig_pll, +}; + +static const struct regmap_config audio_core_cc_shikra_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x305c, + .fast_io = true, +}; + +static const struct qcom_reset_map audio_core_cc_shikra_resets[] = { + [AUDIO_CORE_CSR_RX_SWR_CGCR] = { 0x1c }, + [AUDIO_CORE_CSR_TX_SWR_CGCR] = { 0x30 }, +}; + +static const struct regmap_config audio_core_cc_shikra_reset_regmap_config = { + .name = "audio_core_cc_shikra_reset", + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, + .max_register = 0x34, +}; + +static struct qcom_cc_driver_data audio_core_cc_shikra_driver_data = { + .alpha_plls = audio_core_cc_shikra_plls, + .num_alpha_plls = ARRAY_SIZE(audio_core_cc_shikra_plls), +}; + +static const struct qcom_cc_desc audio_core_cc_shikra_reset_desc = { + .config = &audio_core_cc_shikra_reset_regmap_config, + .resets = audio_core_cc_shikra_resets, + .num_resets = ARRAY_SIZE(audio_core_cc_shikra_resets), +}; + +static const struct qcom_cc_desc audio_core_cc_shikra_desc = { + .config = &audio_core_cc_shikra_regmap_config, + .clk_hws = audio_core_cc_shikra_hws, + .num_clk_hws = ARRAY_SIZE(audio_core_cc_shikra_hws), + .clks = audio_core_cc_shikra_clocks, + .num_clks = ARRAY_SIZE(audio_core_cc_shikra_clocks), + .driver_data = &audio_core_cc_shikra_driver_data, +}; + +static const struct of_device_id audio_core_cc_shikra_match_table[] = { + { .compatible = "qcom,shikra-cqm-audiocorecc" }, + { .compatible = "qcom,shikra-cqs-audiocorecc" }, + { } +}; +MODULE_DEVICE_TABLE(of, audio_core_cc_shikra_match_table); + +static int audio_core_cc_shikra_probe(struct platform_device *pdev) +{ + int ret; + + ret = qcom_cc_probe_by_index(pdev, 1, &audio_core_cc_shikra_reset_desc); + if (ret) + return ret; + + if (device_is_compatible(&pdev->dev, "qcom,shikra-cqs-audiocorecc")) + return 0; + + return qcom_cc_probe(pdev, &audio_core_cc_shikra_desc); +} + +static struct platform_driver audio_core_cc_shikra_driver = { + .probe = audio_core_cc_shikra_probe, + .driver = { + .name = "audiocorecc-shikra", + .of_match_table = audio_core_cc_shikra_match_table, + }, +}; + +module_platform_driver(audio_core_cc_shikra_driver); + +MODULE_DESCRIPTION("QTI AUDIOCORECC Shikra Driver"); +MODULE_LICENSE("GPL"); From 750490d717995a579a95c78ab0c873d45cdfe813 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Fri, 15 May 2026 15:19:21 +0530 Subject: [PATCH 1057/1330] soc: qcom: rpmpd: Reuse sm6125 power domains for shikra Shikra shares the same power domain topology as sm6125. Remove the dedicated shikra_rpmpds[] and update shikra_desc to reuse sm6125_rpmpds[] with RPM_SMD_LEVEL_TURBO_NO_CPR. Signed-off-by: Rakesh Kota (cherry picked from commit 9199a9822ede124115e9161f6ffb227534b265cb) --- drivers/pmdomain/qcom/rpmpd.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index 526f1e7d6a0d9..5ce35b5b5baef 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -863,21 +863,6 @@ static const struct rpmpd_desc sdm660_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; -static struct rpmpd *shikra_rpmpds[] = { - [RPMPD_VDDCX] = &cx_rwcx0_lvl, - [RPMPD_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [RPMPD_VDDCX_VFL] = &cx_rwcx0_vfl, - [RPMPD_VDDMX] = &mx_rwmx0_lvl, - [RPMPD_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [RPMPD_VDDMX_VFL] = &mx_rwmx0_vfl, -}; - -static const struct rpmpd_desc shikra_desc = { - .rpmpds = shikra_rpmpds, - .num_pds = ARRAY_SIZE(shikra_rpmpds), - .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, -}; - static struct rpmpd *sm6115_rpmpds[] = { [SM6115_VDDCX] = &cx_rwcx0_lvl, [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, @@ -910,6 +895,12 @@ static const struct rpmpd_desc sm6125_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; +static const struct rpmpd_desc shikra_desc = { + .rpmpds = sm6125_rpmpds, + .num_pds = ARRAY_SIZE(sm6125_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, +}; + static struct rpmpd *sm6375_rpmpds[] = { [SM6375_VDDCX] = &cx_rwcx0_lvl, [SM6375_VDDCX_AO] = &cx_rwcx0_lvl_ao, From 15bdb95e217800ceda49bc755e8d2b5fc3bf0bff Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Fri, 15 May 2026 14:37:22 +0530 Subject: [PATCH 1058/1330] soc: qcom: pd-mapper: Add shikra PD support for CQM/CQS/IQS All Shikra SoC variants (CQM, CQS, IQS) share the same protection domain requirements: mpss_wlan_pd only. audio_pd is not required on any of these variants. Introduce shikra_cqm_domains with mpss_wlan_pd and wire all three compatibles (qcom,shikra-cqm, qcom,shikra-cqs, qcom,shikra-iqs) to it. Signed-off-by: Anurag Pateriya (cherry picked from commit ee75fc00a51034c29d486fe5c3b11f85ded751c7) --- drivers/soc/qcom/qcom_pd_mapper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c index e46273bf4263a..b1b983ad809d5 100644 --- a/drivers/soc/qcom/qcom_pd_mapper.c +++ b/drivers/soc/qcom/qcom_pd_mapper.c @@ -484,6 +484,11 @@ static const struct qcom_pdm_domain_data *sc8280xp_domains[] = { NULL, }; +static const struct qcom_pdm_domain_data *shikra_cqm_domains[] = { + &mpss_wlan_pd, + NULL, +}; + /* Unlike SDM660, SDM630/636 lack CDSP */ static const struct qcom_pdm_domain_data *sdm630_domains[] = { &adsp_audio_pd, @@ -626,6 +631,9 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,sc7280", .data = sc7280_domains, }, { .compatible = "qcom,sc8180x", .data = sc8180x_domains, }, { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, }, + { .compatible = "qcom,shikra-cqm", .data = shikra_cqm_domains, }, + { .compatible = "qcom,shikra-cqs", .data = shikra_cqm_domains, }, + { .compatible = "qcom,shikra-iqs", .data = shikra_cqm_domains, }, { .compatible = "qcom,sdm630", .data = sdm630_domains, }, { .compatible = "qcom,sdm636", .data = sdm630_domains, }, { .compatible = "qcom,sda660", .data = sdm660_domains, }, From fa62925a170a2000f1e63a1805c33045624326ed Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Wed, 20 May 2026 11:18:36 +0530 Subject: [PATCH 1059/1330] soc: qcom: pd-mapper: Fix shikra compatible strings to use -som suffix The Shikra SoC board compatibles use a `-som` suffix (qcom,shikra-cqm-som, qcom,shikra-cqs-som, qcom,shikra-iqs-som). Update the pd-mapper entries added in the previous commit to match. Fixes: 3aa65ff0ed32 ("soc: qcom: pd-mapper: Add shikra PD support for CQM/CQS/IQS") Co-Authored-By: Claude Sonnet 4.6 (1M context) Signed-off-by: Anurag Pateriya (cherry picked from commit 0e4614022cee12a51102cfa75bfb94f8b007d759) --- drivers/soc/qcom/qcom_pd_mapper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c index b1b983ad809d5..5b5b5bd9ec2f3 100644 --- a/drivers/soc/qcom/qcom_pd_mapper.c +++ b/drivers/soc/qcom/qcom_pd_mapper.c @@ -631,9 +631,9 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,sc7280", .data = sc7280_domains, }, { .compatible = "qcom,sc8180x", .data = sc8180x_domains, }, { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, }, - { .compatible = "qcom,shikra-cqm", .data = shikra_cqm_domains, }, - { .compatible = "qcom,shikra-cqs", .data = shikra_cqm_domains, }, - { .compatible = "qcom,shikra-iqs", .data = shikra_cqm_domains, }, + { .compatible = "qcom,shikra-cqm-som", .data = shikra_cqm_domains, }, + { .compatible = "qcom,shikra-cqs-som", .data = shikra_cqm_domains, }, + { .compatible = "qcom,shikra-iqs-som", .data = shikra_cqm_domains, }, { .compatible = "qcom,sdm630", .data = sdm630_domains, }, { .compatible = "qcom,sdm636", .data = sdm630_domains, }, { .compatible = "qcom,sda660", .data = sdm660_domains, }, From 59c1bcb8b97a4d175f3f96feefe4640906a1353e Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 20 May 2026 18:08:05 +0530 Subject: [PATCH 1060/1330] dt-bindings: regulator: qcom,usb-vbus-regulator: fix allOf schema Consolidate $ref and if/then blocks under a single allOf to ensure all schema constraints are correctly enforced. Signed-off-by: Rakesh Kota (cherry picked from commit 9af492ba7d2ff267a42dc40f1c05384f5d22edab) --- .../regulator/qcom,usb-vbus-regulator.yaml | 51 +++++++++---------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml index d34b378517378..024b34d0eb1a6 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml @@ -21,9 +21,6 @@ description: | voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V and 5.0 V. -allOf: - - $ref: regulator.yaml# - properties: compatible: oneOf: @@ -41,29 +38,31 @@ properties: maxItems: 1 description: VBUS output base address -if: - properties: - compatible: - contains: - enum: - - qcom,pm8150b-vbus-reg - - qcom,pm6150-vbus-reg - - qcom,pm7250b-vbus-reg - - qcom,pmi632-vbus-reg -then: - required: - - regulator-min-microamp - - regulator-max-microamp +allOf: + - $ref: regulator.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8150b-vbus-reg + - qcom,pm6150-vbus-reg + - qcom,pm7250b-vbus-reg + - qcom,pmi632-vbus-reg + then: + required: + - regulator-min-microamp + - regulator-max-microamp -if: - properties: - compatible: - contains: - const: qcom,pm4125-vbus-reg -then: - required: - - regulator-min-microvolt - - regulator-max-microvolt + - if: + properties: + compatible: + contains: + const: qcom,pm4125-vbus-reg + then: + required: + - regulator-min-microvolt + - regulator-max-microvolt required: - compatible @@ -89,7 +88,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - usb-vbus-regulator@5000 { + usb-vbus-regulator@1100 { compatible = "qcom,pm4125-vbus-reg"; reg = <0x1100>; regulator-min-microvolt = <4250000>; From db7d3d25953feaaa0eb3cb78355523910473c110 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 20 May 2026 15:53:31 +0530 Subject: [PATCH 1061/1330] dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR bandwidth monitor. Shikra has a BWMONv5 for CPU. Signed-off-by: Sayantan Chakraborty Signed-off-by: Komal Bajaj (cherry picked from commit 41ec05ed9ad5f9927ae37def75852be087e5307d) --- .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index ce79521bb1ef2..5c4918bf51bde 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -50,6 +50,7 @@ properties: - qcom,sa8775p-llcc-bwmon - qcom,sc7180-llcc-bwmon - qcom,sc8280xp-llcc-bwmon + - qcom,shikra-cpu-bwmon - qcom,sm6350-cpu-bwmon - qcom,sm8250-llcc-bwmon - qcom,sm8550-llcc-bwmon From 2c56b11203da10d7e7372a6175fa1237958407c5 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 20 May 2026 18:34:19 +0530 Subject: [PATCH 1062/1330] dt-bindings: interconnect: qcom,shikra-epss-l3: Add EPSS L3 DT binding Document the EPSS L3 interconnect provider binding for Qualcomm Shikra SoC. The Shikra EPSS L3 block is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Introduce Shikra specific bindings to represent this constrained EPSS variant. Signed-off-by: Raviteja Laggyshetty (cherry picked from commit 6312a7ddcabd6a3cd9e541caf934128d26411126) --- .../interconnect/qcom,shikra-epss-l3.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,shikra-epss-l3.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,shikra-epss-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,shikra-epss-l3.yaml new file mode 100644 index 0000000000000..9cb68a90fa5e1 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,shikra-epss-l3.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,shikra-epss-l3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Operating State Manager (OSM) L3 Shikra Interconnect Provider + +maintainers: + - Raviteja Laggyshetty + +description: + L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. + The OSM L3 interconnect provider aggregates the L3 bandwidth requests + from CPU/GPU and relays it to the OSM. + +properties: + compatible: + enum: + - qcom,shikra-epss-l3 + + reg: + maxItems: 1 + + clocks: + items: + - description: xo clock + - description: alternate clock + + clock-names: + items: + - const: xo + - const: alternate + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + + #define GPLL0 165 + #define RPMH_CXO_CLK 0 + + epss_l3: interconnect@fd90000 { + compatible = "qcom,shikra-epss-l3"; + reg = <0xfd90000 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; From 80073f4369d6588b41eee27a27cc43083aa2c08a Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 20 May 2026 18:56:15 +0530 Subject: [PATCH 1063/1330] interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC Add Epoch Subsystem (EPSS) L3 interconnect provider support on Qualcomm Shikra SoC. The EPSS L3 block on Shikra SoC is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Reading beyond the supported LUT entries can expose incorrect frequencies. Add shikra-specifc EPSS descriptor shikra_epss_l3_perf_state that reuses existing EPSS configuration with appropriate LUT entries limit. Signed-off-by: Raviteja Laggyshetty (cherry picked from commit c49483c931fd34c2df0185bb10284136c568243e) --- drivers/interconnect/qcom/osm-l3.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index b33f00da1880d..ecad636b53e06 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -60,6 +60,7 @@ struct qcom_osm_l3_desc { unsigned int lut_row_size; unsigned int reg_freq_lut; unsigned int reg_perf_state; + unsigned int lut_max_entries; }; #define DEFINE_QNODE(_name, _buswidth) \ @@ -90,6 +91,7 @@ static const struct qcom_osm_l3_desc osm_l3 = { .lut_row_size = OSM_LUT_ROW_SIZE, .reg_freq_lut = OSM_REG_FREQ_LUT, .reg_perf_state = OSM_REG_PERF_STATE, + .lut_max_entries = LUT_MAX_ENTRIES, }; static const struct qcom_osm_l3_desc epss_l3_perf_state = { @@ -98,6 +100,16 @@ static const struct qcom_osm_l3_desc epss_l3_perf_state = { .lut_row_size = EPSS_LUT_ROW_SIZE, .reg_freq_lut = EPSS_REG_FREQ_LUT, .reg_perf_state = EPSS_REG_PERF_STATE, + .lut_max_entries = LUT_MAX_ENTRIES, +}; + +static const struct qcom_osm_l3_desc shikra_epss_l3_perf_state = { + .nodes = epss_l3_nodes, + .num_nodes = ARRAY_SIZE(epss_l3_nodes), + .lut_row_size = EPSS_LUT_ROW_SIZE, + .reg_freq_lut = EPSS_REG_FREQ_LUT, + .reg_perf_state = EPSS_REG_PERF_STATE, + .lut_max_entries = 12, }; static const struct qcom_osm_l3_desc epss_l3_l3_vote = { @@ -106,6 +118,7 @@ static const struct qcom_osm_l3_desc epss_l3_l3_vote = { .lut_row_size = EPSS_LUT_ROW_SIZE, .reg_freq_lut = EPSS_REG_FREQ_LUT, .reg_perf_state = EPSS_REG_L3_VOTE, + .lut_max_entries = LUT_MAX_ENTRIES, }; static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) @@ -189,7 +202,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) qp->reg_perf_state = desc->reg_perf_state; - for (i = 0; i < LUT_MAX_ENTRIES; i++) { + for (i = 0; i < desc->lut_max_entries; i++) { info = readl_relaxed(qp->base + desc->reg_freq_lut + i * desc->lut_row_size); src = FIELD_GET(LUT_SRC, info); @@ -272,6 +285,7 @@ static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 }, + { .compatible = "qcom,shikra-epss-l3", .data = &shikra_epss_l3_perf_state }, { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state }, From 2d02bace1ee02cf6fd6f4cb63bbd4d8bbb54ffb8 Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Tue, 12 May 2026 12:03:19 +0530 Subject: [PATCH 1064/1330] dt-bindings: media: qcom: Add Shikra CAMSS compatible Shikra uses the same CAMSS IP as QCM2290. Extend the existing qcom,qcm2290-camss binding to add the qcom,shikra-camss compatible string. Co-developed-by: Vikram Sharma Signed-off-by: Vikram Sharma Signed-off-by: Nihal Kumar Gupta (cherry picked from commit a6dc261317abadd483d61bdcf24ef4ef221c50a8) --- .../devicetree/bindings/media/qcom,qcm2290-camss.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml index 391d0f6f67ef5..7b1469d6a1601 100644 --- a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml @@ -8,13 +8,16 @@ title: Qualcomm QCM2290 Camera Subsystem (CAMSS) maintainers: - Loic Poulain + - Nihal Kumar Gupta description: The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. properties: compatible: - const: qcom,qcm2290-camss + enum: + - qcom,qcm2290-camss + - qcom,shikra-camss reg: maxItems: 9 @@ -76,6 +79,7 @@ properties: - const: sf_mnoc iommus: + minItems: 1 maxItems: 4 power-domains: From cba7d127a6e4713737c9459c2a5e169fe9305a1a Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Tue, 12 May 2026 12:33:39 +0530 Subject: [PATCH 1065/1330] dt-bindings: i2c: qcom-cci: Document Shikra compatible Add Shikra compatible consistent with CAMSS CCI interfaces. It requires only two clocks. Signed-off-by: Nihal Kumar Gupta (cherry picked from commit 9a18e4119f1c7f8e12723f292c6b023928decb61) --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 35d3a0685ac44..0c13841b87622 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -34,6 +34,7 @@ properties: - qcom,sc8280xp-cci - qcom,sdm670-cci - qcom,sdm845-cci + - qcom,shikra-cci - qcom,sm6150-cci - qcom,sm6350-cci - qcom,sm8250-cci @@ -136,6 +137,7 @@ allOf: - qcom,kaanapali-cci - qcom,qcm2290-cci - qcom,qcs8300-cci + - qcom,shikra-cci - qcom,sm8750-cci then: properties: From ac96652071fba0d428a469b23af70d3e2ee198f1 Mon Sep 17 00:00:00 2001 From: Prashant Shrotriya Date: Fri, 15 May 2026 19:16:22 +0530 Subject: [PATCH 1066/1330] media: qcom: camss: add support for QCM2390 camss Add CAMSS driver support for Shikra SoC. Add high level resource definitions for 2 CSIPHY, 2 CSID and 2 VFE instances along with the interconnect bandwidth votes for AHB, HF and SF MNOC paths. Co-developed-by: Vikram Sharma Signed-off-by: Vikram Sharma Signed-off-by: Prashant Shrotriya (cherry picked from commit 45fa97cf9097a8a17e7ada36e3d6b0ef61abc856) --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 ++ drivers/media/platform/qcom/camss/camss-vfe.c | 1 + drivers/media/platform/qcom/camss/camss.c | 13 +++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 4 files changed, 17 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 8132f8da7849b..c7ddd8a4d8f57 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1127,6 +1127,7 @@ static bool csiphy_is_gen2(u32 version) switch (version) { case CAMSS_2290: + case CAMSS_2390: case CAMSS_6150: case CAMSS_7280: case CAMSS_8250: @@ -1221,6 +1222,7 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845); break; case CAMSS_2290: + case CAMSS_2390: case CAMSS_6150: regs->lane_regs = &lane_regs_qcm2290[0]; regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290); diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 8dd39c7312f7b..5d1e7375ac4a1 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -342,6 +342,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, break; case CAMSS_660: case CAMSS_2290: + case CAMSS_2390: case CAMSS_6150: case CAMSS_7280: case CAMSS_8x96: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 6a48487181c0f..ceaf2dda54006 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -6136,6 +6136,18 @@ static const struct camss_resources qcm2290_resources = { .vfe_num = ARRAY_SIZE(vfe_res_2290), }; +static const struct camss_resources qcm2390_resources = { + .version = CAMSS_2390, + .csiphy_res = csiphy_res_2290, + .csid_res = csid_res_2290, + .vfe_res = vfe_res_2290, + .icc_res = icc_res_2290, + .icc_path_num = ARRAY_SIZE(icc_res_2290), + .csiphy_num = ARRAY_SIZE(csiphy_res_2290), + .csid_num = ARRAY_SIZE(csid_res_2290), + .vfe_num = ARRAY_SIZE(vfe_res_2290), +}; + static const struct camss_resources qcs8300_resources = { .version = CAMSS_8300, .pd_name = "top", @@ -6351,6 +6363,7 @@ static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, { .compatible = "qcom,sdm670-camss", .data = &sdm670_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, + { .compatible = "qcom,shikra-camss", .data = &qcm2390_resources }, { .compatible = "qcom,sm6150-camss", .data = &sm6150_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 381dcd816d841..cf9fc629e5997 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -82,6 +82,7 @@ enum pm_domain { enum camss_version { CAMSS_660, CAMSS_2290, + CAMSS_2390, CAMSS_6150, CAMSS_7280, CAMSS_8x16, From 83c89b7da6eef7022ae2abdcaa36e4a88e776ddb Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Tue, 19 May 2026 16:07:59 +0530 Subject: [PATCH 1067/1330] soc: qcom: smsm: Increase default num_hosts to 5 for Shikra SMEM_SMSM_SIZE_INFO (id 419) is not populated by the boot firmware on Shikra. The SMSM driver falls back to SMSM_DEFAULT_NUM_HOSTS when this segment is absent, which causes SMEM_SMSM_CPU_INTR_MASK (id 333) to be allocated with the wrong size. The upstream default of 3 allocates 8*3*4 = 96 bytes. Shikra modem firmware expects 8*5*4 = 160 bytes, matching the num_hosts=5 used by the downstream kernel. The size mismatch causes the modem to crash on boot with "smsm.c: Bad pointer from smem_alloc". Increasing the host count only results in a larger allocation, so this change is safe for existing platforms. Increase the default to 5 to match the modem firmware expectation. Signed-off-by: Vishnu Santhosh (cherry picked from commit d2a3f3aea2006f4275c395debf869dc3c22d97df) --- drivers/soc/qcom/smsm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 021e9d1f61dc5..7d1823ab4198b 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -54,7 +54,7 @@ * Default sizes, in case SMEM_SMSM_SIZE_INFO is not found. */ #define SMSM_DEFAULT_NUM_ENTRIES 8 -#define SMSM_DEFAULT_NUM_HOSTS 3 +#define SMSM_DEFAULT_NUM_HOSTS 5 struct smsm_entry; struct smsm_host; From 6b184f6880a4a4a3957754501ef8feea8aa0bb2a Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Wed, 20 May 2026 10:26:48 +0530 Subject: [PATCH 1068/1330] dmaengine: qcom: bam_dma: Defer IRQ trigger type to device tree The driver hardcodes IRQF_TRIGGER_HIGH when registering the BAM interrupt, which overrides the trigger type specified in the device tree. This is incorrect for platforms like Shikra where the A2 BAM requires edge-triggered interrupts. Use IRQF_TRIGGER_NONE instead, which causes the kernel to use the trigger type already configured by platform_get_irq() when it parsed the device tree interrupts property. This makes the driver platform-agnostic. Signed-off-by: Vishnu Santhosh (cherry picked from commit 410819e845aef56a5894820480621e075062660d) --- drivers/dma/qcom/bam_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 04728880df3a8..8a5f765a03cc4 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -1353,7 +1353,7 @@ static int bam_dma_probe(struct platform_device *pdev) bam_channel_init(bdev, &bdev->channels[i], i); ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq, - IRQF_TRIGGER_HIGH, "bam_dma", bdev); + IRQF_TRIGGER_NONE, "bam_dma", bdev); if (ret) goto err_bam_channel_exit; From 86ee448a69a0f4cfdc7a98817a3162903516e2e3 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Tue, 19 May 2026 16:37:43 +0530 Subject: [PATCH 1069/1330] arm64: defconfig: Enable Qualcomm BAM-DMUX WWAN driver This driver provides access to modem data channels on platforms using the A2 BAM hardware, including Shikra. Signed-off-by: Vishnu Santhosh (cherry picked from commit 072917fece4c997a5b03f49e7c1a985ef7ba0250) --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ae66ecf7fee97..8db2f38dc16e3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -472,6 +472,7 @@ CONFIG_WLCORE_SDIO=m CONFIG_WWAN=m CONFIG_MHI_WWAN_CTRL=m CONFIG_MHI_WWAN_MBIM=m +CONFIG_QCOM_BAM_DMUX=m CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_ADC=m CONFIG_KEYBOARD_GPIO=y From c9d0a73168410cf33f03873de9990b42d52e5af2 Mon Sep 17 00:00:00 2001 From: Aditya Sherawat Date: Tue, 21 Apr 2026 13:03:05 +0530 Subject: [PATCH 1070/1330] drm/msm/adreno: Add support for A704 GPU Add support for the Adreno A704 GPU (chip ID 0x07000400). It belongs to the A610 family and shares its configuration with the A702, including HWCG, UBWC settings, and CP memory pool size. Introduce adreno_is_a704() and include A704 in adreno_is_a610_family(). Signed-off-by: Aditya Sherawat (cherry picked from commit 0084527ac646fd6ed0dbd287e07b6f631f7b7e14) --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 +++++++- 3 files changed, 35 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 38561f26837e3..963015b27c529 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1477,6 +1477,23 @@ static const struct adreno_info a7xx_gpus[] = { { 178, 2 }, { 142, 3 }, ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x07000400), + .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ + .fw = { + [ADRENO_FW_SQE] = "a702_sqe.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .funcs = &a6xx_gmuwrapper_funcs, + .a6xx = &(const struct a6xx_info) { + .hwcg = a702_hwcg, + .protect = &a650_protect, + .gbif_cx = a640_gbif, + .gmu_cgc_mode = 0x00020202, + .prim_fifo_threshold = 0x0000c000, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x07030001), .family = ADRENO_7XX_GEN1, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 3e26b60d7f678..673e4216db391 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -640,7 +640,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) clock_cntl_on = 0x8aa8aa02; else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) clock_cntl_on = 0xaaa8aa82; - else if (adreno_is_a702(adreno_gpu)) + else if (adreno_is_a702(adreno_gpu) || adreno_is_a704(adreno_gpu)) clock_cntl_on = 0xaaaaaa82; else clock_cntl_on = 0x8aa8aa82; @@ -790,7 +790,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (adreno_is_7c3(gpu)) cfg->highest_bank_bit = 14; - if (adreno_is_a702(gpu)) + if (adreno_is_a702(gpu) || adreno_is_a704(gpu)) cfg->highest_bank_bit = 14; if (cfg->highest_bank_bit != common_cfg->highest_bank_bit) @@ -829,7 +829,8 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) uavflagprd_inv = 2; - if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) + if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu) || + adreno_is_a704(adreno_gpu)) min_acc_len_64b = true; gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, @@ -1064,7 +1065,8 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, return false; /* A7xx is safe! */ - if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu) || + adreno_is_a704(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) return true; /* @@ -1347,6 +1349,7 @@ static int hw_init(struct msm_gpu *gpu) if (!(adreno_is_a650_family(adreno_gpu) || adreno_is_a702(adreno_gpu) || + adreno_is_a704(adreno_gpu) || adreno_is_a730(adreno_gpu))) { gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M; @@ -1382,7 +1385,7 @@ static int hw_init(struct msm_gpu *gpu) if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); - } else if (adreno_is_a702(adreno_gpu)) { + } else if (adreno_is_a702(adreno_gpu) || adreno_is_a704(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); } else if (!adreno_is_a7xx(adreno_gpu)) @@ -1420,7 +1423,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); else if (adreno_is_a619(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); - else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) + else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu) || + adreno_is_a704(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); @@ -1456,7 +1460,7 @@ static int hw_init(struct msm_gpu *gpu) else gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); - } else if (adreno_is_a702(adreno_gpu)) { + } else if (adreno_is_a702(adreno_gpu) || adreno_is_a704(adreno_gpu)) { /* Something to do with the HLSQ cluster */ gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 044ed4d49aa7a..e9365533be2a9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -504,13 +504,19 @@ static inline int adreno_is_a702(const struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x07000200; } +static inline int adreno_is_a704(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x07000400; +} + static inline int adreno_is_a610_family(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; return adreno_is_a610(gpu) || adreno_is_a612(gpu) || - adreno_is_a702(gpu); + adreno_is_a702(gpu) || + adreno_is_a704(gpu); } /* TODO: 615/616 */ From aa3f347fac9604258fab45387a652d0592fa248f Mon Sep 17 00:00:00 2001 From: Aditya Sherawat Date: Thu, 14 May 2026 14:33:01 +0530 Subject: [PATCH 1071/1330] dt-bindings: display/msm/gpu: Add support for A704 shikra GPU The Shikra SoC uses an Adreno A704 GPU identified by chip ID 0x07000400. Signed-off-by: Aditya Sherawat (cherry picked from commit 95d1d482a0fa8eda19bd7ca4e89263dc3eedebc7) --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index a5f4f79432c8f..276313abb8647 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -357,6 +357,7 @@ allOf: - qcom,adreno-610.0 - qcom,adreno-619.1 - qcom,adreno-07000200 + - qcom,adreno-07000400 then: properties: clocks: From 03de7b7727e431222dc1079d3a84f53771afbe76 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 21 May 2026 17:05:47 +0530 Subject: [PATCH 1072/1330] dt-bindings: cpufreq: qcom-hw: Update Shikra CPUFREQ bindings Drop generic compatible approach, and add Shikra specific bindings. Signed-off-by: Imran Shaik (cherry picked from commit 1307dc19fc1eb6ad76e4b37e1ada0d3c0a6b392e) --- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 7 -- .../bindings/cpufreq/qcom,shikra-epss.yaml | 96 +++++++++++++++++++ 2 files changed, 96 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 2162110183de8..22eeaef14f557 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -53,12 +53,6 @@ properties: - qcom,sm8650-cpufreq-epss - const: qcom,cpufreq-epss - - description: RIMPS CPUFREQ HW - items: - - enum: - - qcom,shikra-cpufreq-rimps - - const: qcom,cpufreq-rimps - reg: minItems: 1 items: @@ -149,7 +143,6 @@ allOf: - qcom,sc8280xp-cpufreq-epss - qcom,sdm670-cpufreq-hw - qcom,sdm845-cpufreq-hw - - qcom,shikra-cpufreq-rimps - qcom,sm4450-cpufreq-epss - qcom,sm6115-cpufreq-hw - qcom,sm6350-cpufreq-hw diff --git a/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml b/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml new file mode 100644 index 0000000000000..8543fd00d82ac --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/qcom,shikra-epss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CPUFREQ HW for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + CPUFREQ HW is a hardware engine used by some Qualcomm SoCs to manage + frequency in hardware. It is capable of controlling frequency for + multiple clusters. + + The Qualcomm Shikra CPUFREQ HW supports up to 12 frequency lookup table + (LUT) entries. + +properties: + compatible: + enum: + - qcom,shikra-epss + + reg: + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + + reg-names: + items: + - const: freq-domain0 + - const: freq-domain1 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + interrupts: + items: + - description: IRQ line for DCVSH 0 + - description: IRQ line for DCVSH 1 + + interrupt-names: + items: + - const: dcvsh-irq-0 + - const: dcvsh-irq-1 + + '#freq-domain-cells': + const: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - '#freq-domain-cells' + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + cpufreq@fd91000 { + compatible = "qcom,shikra-epss"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gpll0>; + clock-names = "xo", "alternate"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; +... From 612a2bef9d841c52660bdd51959c55f27105efc8 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 21 May 2026 17:07:29 +0530 Subject: [PATCH 1073/1330] cpufreq: qcom-cpufreq-hw: Update qcom,shikra-epss compatible Update the compatible string to "qcom,shikra-epss" as per the latest bindings. Signed-off-by: Imran Shaik (cherry picked from commit 91c68036633225518db862ad3d717edb0f18f6ad) --- drivers/cpufreq/qcom-cpufreq-hw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 1fad60e3a627e..3d5a865fb8a35 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -422,7 +422,7 @@ static const struct qcom_cpufreq_soc_data epss_soc_data = { .lut_max_entries = LUT_MAX_ENTRIES, }; -static const struct qcom_cpufreq_soc_data rimps_soc_data = { +static const struct qcom_cpufreq_soc_data shikra_epss_soc_data = { .reg_enable = 0x0, .reg_domain_state = 0x20, .reg_dcvs_ctrl = 0xb0, @@ -437,7 +437,7 @@ static const struct qcom_cpufreq_soc_data rimps_soc_data = { static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, - { .compatible = "qcom,cpufreq-rimps", .data = &rimps_soc_data }, + { .compatible = "qcom,shikra-epss", .data = &shikra_epss_soc_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); From fb23422a8e88fe3ed32b6b525e4a7cbc055e695f Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Wed, 20 May 2026 15:44:29 +0530 Subject: [PATCH 1074/1330] soc: qcom: smsm: Add trace events Add ftrace tracepoints to SMSM for observability of state bit updates, IPC kicks, interrupt handling, and IRQ mask/unmask operations. Introduce a trace header and wire CFLAGS_smsm.o so the trace header is found via -I$(src). Signed-off-by: Vishnu Santhosh (cherry picked from commit 4fc7567e7a80c93a5cbf72ba3b9d5e02525ecd22) --- drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/smsm.c | 18 ++++- drivers/soc/qcom/trace-smsm.h | 143 ++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/qcom/trace-smsm.h diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index a3fa2b8eebfc7..270cf0bf3b6ad 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_QCOM_SMEM) += qcom_smem.o obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o CFLAGS_smp2p.o := -I$(src) obj-$(CONFIG_QCOM_SMP2P) += smp2p.o +CFLAGS_smsm.o := -I$(src) obj-$(CONFIG_QCOM_SMSM) += smsm.o obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o obj-$(CONFIG_QCOM_SPM) += spm.o diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 7d1823ab4198b..5d62076024567 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -15,6 +15,9 @@ #include #include +#define CREATE_TRACE_POINTS +#include "trace-smsm.h" + /* * This driver implements the Qualcomm Shared Memory State Machine, a mechanism * for communicating single bit state information to remote processors. @@ -162,6 +165,9 @@ static int smsm_update_bits(void *data, u32 mask, u32 value) /* Don't signal if we didn't change the value */ changes = val ^ orig; + + trace_smsm_update_bits(smsm->dev, mask, value, orig, val, changes); + if (!changes) { spin_unlock_irqrestore(&smsm->lock, flags); goto done; @@ -182,6 +188,8 @@ static int smsm_update_bits(void *data, u32 mask, u32 value) if (!(val & changes)) continue; + trace_smsm_ipc_kick(smsm->dev, host, val); + if (hostp->mbox_chan) { mbox_send_message(hostp->mbox_chan, NULL); mbox_client_txdone(hostp->mbox_chan, 0); @@ -214,10 +222,14 @@ static irqreturn_t smsm_intr(int irq, void *data) unsigned i; int irq_pin; u32 changed; + u32 old; u32 val; val = readl(entry->remote_state); - changed = val ^ xchg(&entry->last_value, val); + old = xchg(&entry->last_value, val); + changed = val ^ old; + + trace_smsm_intr(irq, old, val, changed); for_each_set_bit(i, entry->irq_enabled, 32) { if (!(changed & BIT(i))) @@ -226,11 +238,13 @@ static irqreturn_t smsm_intr(int irq, void *data) if (val & BIT(i)) { if (test_bit(i, entry->irq_rising)) { irq_pin = irq_find_mapping(entry->domain, i); + trace_smsm_irq_cascade(irq_pin, i, true); handle_nested_irq(irq_pin); } } else { if (test_bit(i, entry->irq_falling)) { irq_pin = irq_find_mapping(entry->domain, i); + trace_smsm_irq_cascade(irq_pin, i, false); handle_nested_irq(irq_pin); } } @@ -257,6 +271,7 @@ static void smsm_mask_irq(struct irq_data *irqd) val = readl(entry->subscription + smsm->local_host); val &= ~BIT(irq); writel(val, entry->subscription + smsm->local_host); + trace_smsm_irq_mask(irq, true, val); } clear_bit(irq, entry->irq_enabled); @@ -288,6 +303,7 @@ static void smsm_unmask_irq(struct irq_data *irqd) val = readl(entry->subscription + smsm->local_host); val |= BIT(irq); writel(val, entry->subscription + smsm->local_host); + trace_smsm_irq_mask(irq, false, val); } } diff --git a/drivers/soc/qcom/trace-smsm.h b/drivers/soc/qcom/trace-smsm.h new file mode 100644 index 0000000000000..8b8c79972130f --- /dev/null +++ b/drivers/soc/qcom/trace-smsm.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM qcom_smsm + +#if !defined(__QCOM_SMSM_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) +#define __QCOM_SMSM_TRACE_H__ + +#include +#include + +/* + * Fired on every call to smsm_update_bits(), whether or not the state + * actually changed. changes == 0 indicates the write was a no-op because + * the bits were already in the requested state. + */ +TRACE_EVENT(smsm_update_bits, + TP_PROTO(const struct device *dev, u32 mask, u32 value, + u32 orig, u32 val, u32 changes), + TP_ARGS(dev, mask, value, orig, val, changes), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(u32, mask) + __field(u32, value) + __field(u32, orig) + __field(u32, val) + __field(u32, changes) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->mask = mask; + __entry->value = value; + __entry->orig = orig; + __entry->val = val; + __entry->changes = changes; + ), + TP_printk("%s: mask:0x%08x value:0x%08x 0x%08x->0x%08x changed:0x%08x", + __get_str(dev_name), + __entry->mask, __entry->value, + __entry->orig, __entry->val, + __entry->changes) +); + +/* + * Fired for each remote host that is subscribed to the changed bits and + * is about to receive an IPC kick. + */ +TRACE_EVENT(smsm_ipc_kick, + TP_PROTO(const struct device *dev, u32 host, u32 subscription), + TP_ARGS(dev, host, subscription), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(u32, host) + __field(u32, subscription) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->host = host; + __entry->subscription = subscription; + ), + TP_printk("%s: kick host %u subscription:0x%08x", + __get_str(dev_name), __entry->host, __entry->subscription) +); + +/* + * Fired at the top of smsm_intr() after reading the remote state and + * computing the changed bits. + */ +TRACE_EVENT(smsm_intr, + TP_PROTO(int irq, u32 old_state, u32 new_state, u32 changed), + TP_ARGS(irq, old_state, new_state, changed), + TP_STRUCT__entry( + __field(int, irq) + __field(u32, old_state) + __field(u32, new_state) + __field(u32, changed) + ), + TP_fast_assign( + __entry->irq = irq; + __entry->old_state = old_state; + __entry->new_state = new_state; + __entry->changed = changed; + ), + TP_printk("IRQ %d: 0x%08x->0x%08x changed:0x%08x", + __entry->irq, + __entry->old_state, __entry->new_state, + __entry->changed) +); + +/* + * Fired for each cascaded (per-bit) IRQ that is about to be dispatched + * to a downstream consumer (e.g. the BAM DMUX pc/pc-ack handler). + */ +TRACE_EVENT(smsm_irq_cascade, + TP_PROTO(int irq_pin, unsigned int bit, bool rising), + TP_ARGS(irq_pin, bit, rising), + TP_STRUCT__entry( + __field(int, irq_pin) + __field(unsigned int, bit) + __field(bool, rising) + ), + TP_fast_assign( + __entry->irq_pin = irq_pin; + __entry->bit = bit; + __entry->rising = rising; + ), + TP_printk("IRQ %d bit %u %s", + __entry->irq_pin, __entry->bit, + __entry->rising ? "rising" : "falling") +); + +/* + * Fired when a cascaded per-bit IRQ is masked or unmasked, recording the + * resulting subscription bitmap written to shared memory. + */ +TRACE_EVENT(smsm_irq_mask, + TP_PROTO(unsigned long irq, bool mask, u32 subscription), + TP_ARGS(irq, mask, subscription), + TP_STRUCT__entry( + __field(unsigned long, irq) + __field(bool, mask) + __field(u32, subscription) + ), + TP_fast_assign( + __entry->irq = irq; + __entry->mask = mask; + __entry->subscription = subscription; + ), + TP_printk("IRQ %lu %s subscription:0x%08x", + __entry->irq, + __entry->mask ? "masked" : "unmasked", + __entry->subscription) +); + +#endif /* __QCOM_SMSM_TRACE_H__ */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . + +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE trace-smsm + +#include From 015785a8a53e417696fbf15819c1cc15706bd443 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Wed, 20 May 2026 15:46:36 +0530 Subject: [PATCH 1075/1330] net: wwan: qcom_bam_dmux: Add trace events Add ftrace tracepoints to the BAM-DMUX driver for observability of channel open/close (local and remote), RX callbacks, power on/off transitions, power control IRQs, and each step of the runtime resume sequence. Introduce a trace header and wire CFLAGS_qcom_bam_dmux.o so the trace header is found via -I$(src). Signed-off-by: Vishnu Santhosh (cherry picked from commit a34947dc1449769d07054e56f386687fef5540b0) --- drivers/net/wwan/Makefile | 1 + drivers/net/wwan/qcom_bam_dmux.c | 33 +++++- drivers/net/wwan/trace-bam-dmux.h | 169 ++++++++++++++++++++++++++++++ 3 files changed, 200 insertions(+), 3 deletions(-) create mode 100644 drivers/net/wwan/trace-bam-dmux.h diff --git a/drivers/net/wwan/Makefile b/drivers/net/wwan/Makefile index 3960c0ae2445c..b6c6fc9ce0f5f 100644 --- a/drivers/net/wwan/Makefile +++ b/drivers/net/wwan/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_WWAN_HWSIM) += wwan_hwsim.o obj-$(CONFIG_MHI_WWAN_CTRL) += mhi_wwan_ctrl.o obj-$(CONFIG_MHI_WWAN_MBIM) += mhi_wwan_mbim.o +CFLAGS_qcom_bam_dmux.o := -I$(src) obj-$(CONFIG_QCOM_BAM_DMUX) += qcom_bam_dmux.o obj-$(CONFIG_RPMSG_WWAN_CTRL) += rpmsg_wwan_ctrl.o obj-$(CONFIG_IOSM) += iosm/ diff --git a/drivers/net/wwan/qcom_bam_dmux.c b/drivers/net/wwan/qcom_bam_dmux.c index 6a5b22589af48..0d3865f612157 100644 --- a/drivers/net/wwan/qcom_bam_dmux.c +++ b/drivers/net/wwan/qcom_bam_dmux.c @@ -22,6 +22,9 @@ #include #include +#define CREATE_TRACE_POINTS +#include "trace-bam-dmux.h" + #define BAM_DMUX_BUFFER_SIZE SZ_2K #define BAM_DMUX_HDR_SIZE sizeof(struct bam_dmux_hdr) #define BAM_DMUX_MAX_DATA_SIZE (BAM_DMUX_BUFFER_SIZE - BAM_DMUX_HDR_SIZE) @@ -278,6 +281,7 @@ static int bam_dmux_netdev_open(struct net_device *netdev) struct bam_dmux_netdev *bndev = netdev_priv(netdev); int ret; + trace_bam_dmux_channel(bndev->dmux->dev, bndev->ch, "local_open"); ret = bam_dmux_send_cmd(bndev, BAM_DMUX_CMD_OPEN); if (ret) return ret; @@ -290,6 +294,7 @@ static int bam_dmux_netdev_stop(struct net_device *netdev) { struct bam_dmux_netdev *bndev = netdev_priv(netdev); + trace_bam_dmux_channel(bndev->dmux->dev, bndev->ch, "local_close"); netif_stop_queue(netdev); bam_dmux_send_cmd(bndev, BAM_DMUX_CMD_CLOSE); return 0; @@ -542,6 +547,7 @@ static void bam_dmux_cmd_open(struct bam_dmux *dmux, struct bam_dmux_hdr *hdr) struct net_device *netdev = dmux->netdevs[hdr->ch]; dev_dbg(dmux->dev, "open channel: %u\n", hdr->ch); + trace_bam_dmux_channel(dmux->dev, hdr->ch, "remote_open"); if (__test_and_set_bit(hdr->ch, dmux->remote_channels)) { dev_warn(dmux->dev, "Channel already open: %u\n", hdr->ch); @@ -561,6 +567,7 @@ static void bam_dmux_cmd_close(struct bam_dmux *dmux, struct bam_dmux_hdr *hdr) struct net_device *netdev = dmux->netdevs[hdr->ch]; dev_dbg(dmux->dev, "close channel: %u\n", hdr->ch); + trace_bam_dmux_channel(dmux->dev, hdr->ch, "remote_close"); if (!__test_and_clear_bit(hdr->ch, dmux->remote_channels)) { dev_err(dmux->dev, "Channel not open: %u\n", hdr->ch); @@ -590,6 +597,8 @@ static void bam_dmux_rx_callback(void *data) goto out; } + trace_bam_dmux_rx(dmux->dev, hdr->ch, hdr->cmd, hdr->len); + switch (hdr->cmd) { case BAM_DMUX_CMD_DATA: bam_dmux_cmd_data(skb_dma); @@ -624,16 +633,20 @@ static bool bam_dmux_power_on(struct bam_dmux *dmux) if (IS_ERR(dmux->rx)) { dev_err(dev, "Failed to request RX DMA channel: %pe\n", dmux->rx); dmux->rx = NULL; + trace_bam_dmux_power(dev, true, false); return false; } dmaengine_slave_config(dmux->rx, &dma_rx_conf); for (i = 0; i < BAM_DMUX_NUM_SKB; i++) { - if (!bam_dmux_skb_dma_queue_rx(&dmux->rx_skbs[i], GFP_KERNEL)) + if (!bam_dmux_skb_dma_queue_rx(&dmux->rx_skbs[i], GFP_KERNEL)) { + trace_bam_dmux_power(dev, true, false); return false; + } } dma_async_issue_pending(dmux->rx); + trace_bam_dmux_power(dev, true, true); return true; } @@ -669,6 +682,7 @@ static void bam_dmux_power_off(struct bam_dmux *dmux) } bam_dmux_free_skbs(dmux->rx_skbs, DMA_FROM_DEVICE); + trace_bam_dmux_power(dmux->dev, false, true); } static irqreturn_t bam_dmux_pc_irq(int irq, void *data) @@ -677,6 +691,7 @@ static irqreturn_t bam_dmux_pc_irq(int irq, void *data) bool new_state = !dmux->pc_state; dev_dbg(dmux->dev, "pc: %u\n", new_state); + trace_bam_dmux_pc(dmux->dev, dmux->pc_state, new_state); if (new_state) { if (bam_dmux_power_on(dmux)) @@ -722,8 +737,11 @@ static int __maybe_unused bam_dmux_runtime_resume(struct device *dev) /* Wait until previous power down was acked */ if (!wait_for_completion_timeout(&dmux->pc_ack_completion, - BAM_DMUX_REMOTE_TIMEOUT)) + BAM_DMUX_REMOTE_TIMEOUT)) { + trace_bam_dmux_resume_step(dev, "prev_ack", -ETIMEDOUT); return -ETIMEDOUT; + } + trace_bam_dmux_resume_step(dev, "prev_ack", 0); /* Vote for power state */ bam_dmux_pc_vote(dmux, true); @@ -732,33 +750,42 @@ static int __maybe_unused bam_dmux_runtime_resume(struct device *dev) if (!wait_for_completion_timeout(&dmux->pc_ack_completion, BAM_DMUX_REMOTE_TIMEOUT)) { bam_dmux_pc_vote(dmux, false); + trace_bam_dmux_resume_step(dev, "ack", -ETIMEDOUT); return -ETIMEDOUT; } + trace_bam_dmux_resume_step(dev, "ack", 0); /* Wait until we're up */ if (!wait_event_timeout(dmux->pc_wait, dmux->pc_state, BAM_DMUX_REMOTE_TIMEOUT)) { bam_dmux_pc_vote(dmux, false); + trace_bam_dmux_resume_step(dev, "bam_up", -ETIMEDOUT); return -ETIMEDOUT; } + trace_bam_dmux_resume_step(dev, "bam_up", 0); /* Ensure that we actually initialized successfully */ if (!dmux->rx) { bam_dmux_pc_vote(dmux, false); + trace_bam_dmux_resume_step(dev, "bam_up", -ENXIO); return -ENXIO; } /* Request TX channel if necessary */ - if (dmux->tx) + if (dmux->tx) { + trace_bam_dmux_resume_step(dev, "tx_chan", 0); return 0; + } dmux->tx = dma_request_chan(dev, "tx"); if (IS_ERR(dmux->tx)) { dev_err(dev, "Failed to request TX DMA channel: %pe\n", dmux->tx); dmux->tx = NULL; bam_dmux_runtime_suspend(dev); + trace_bam_dmux_resume_step(dev, "tx_chan", -ENXIO); return -ENXIO; } + trace_bam_dmux_resume_step(dev, "tx_chan", 0); return 0; } diff --git a/drivers/net/wwan/trace-bam-dmux.h b/drivers/net/wwan/trace-bam-dmux.h new file mode 100644 index 0000000000000..b9a2b4b534e79 --- /dev/null +++ b/drivers/net/wwan/trace-bam-dmux.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM qcom_bam_dmux + +#if !defined(__QCOM_BAM_DMUX_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) +#define __QCOM_BAM_DMUX_TRACE_H__ + +#include +#include + +/* + * Fired at the top of bam_dmux_pc_irq() when the modem toggles its BAM + * power-control SMSM bit. + * old_state: dmux->pc_state before the edge (0 = BAM was off) + * new_state: !old_state (what we are transitioning to) + * + * Downstream equivalent (BAM_DMUX_LOG): + * "bam_dmux_smsm_cb: 0x%08x -> 0x%08x" + "reconnect / disconnect / init" + */ +TRACE_EVENT(bam_dmux_pc, + TP_PROTO(const struct device *dev, bool old_state, bool new_state), + TP_ARGS(dev, old_state, new_state), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(bool, old_state) + __field(bool, new_state) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->old_state = old_state; + __entry->new_state = new_state; + ), + TP_printk("%s: pc %s -> %s", + __get_str(dev_name), + __entry->old_state ? "on" : "off", + __entry->new_state ? "on" : "off") +); + +/* + * Fired at the end of bam_dmux_power_on() and bam_dmux_power_off() to + * record whether the BAM DMA channel setup/teardown succeeded. + * on: true = power_on, false = power_off + * success: only meaningful when on=true; false means DMA channel + * request or RX buffer queueing failed + * + * Downstream equivalent: + * "reconnect_to_bam: disconnect tx/rx, device reset, sps_connect tx/rx" + * "disconnect_to_bam: disconnect tx, disconnect rx, device reset" + */ +TRACE_EVENT(bam_dmux_power, + TP_PROTO(const struct device *dev, bool on, bool success), + TP_ARGS(dev, on, success), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(bool, on) + __field(bool, success) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->on = on; + __entry->success = success; + ), + TP_printk("%s: power %s%s", + __get_str(dev_name), + __entry->on ? "on" : "off", + __entry->on ? (__entry->success ? " ok" : " failed") : "") +); + +/* + * Fired at the completion of each step inside bam_dmux_runtime_resume(). + * result=0 means the step passed; negative errno means it failed/timed out. + * + * Steps in order: + * "prev_ack" - waited for previous power-down to be acked by modem + * "ack" - voted for power and waited for modem's ack + * "bam_up" - waited for modem to signal BAM is powered (pc_state=true) + * "tx_chan" - requested TX DMA channel + * + * Downstream equivalent (BAM_DMUX_LOG): + * "ul_wakeup waiting for previous ack" + * "ul_wakeup waiting for wakeup ack" + * "ul_wakeup waiting completion" + * "ul_wakeup complete" + */ +TRACE_EVENT(bam_dmux_resume_step, + TP_PROTO(const struct device *dev, const char *step, int result), + TP_ARGS(dev, step, result), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __string(step, step) + __field(int, result) + ), + TP_fast_assign( + __assign_str(dev_name); + __assign_str(step); + __entry->result = result; + ), + TP_printk("%s: resume %s: %d", + __get_str(dev_name), __get_str(step), __entry->result) +); + +/* + * Fired on every channel open and close event, from both the modem side + * (CMD_OPEN/CMD_CLOSE) and the local netdev side (ndo_open/ndo_stop). + * + * event: "remote_open" - modem sent CMD_OPEN + * "remote_close" - modem sent CMD_CLOSE + * "local_open" - AP opened the netdev (sent CMD_OPEN to modem) + * "local_close" - AP stopped the netdev (sent CMD_CLOSE to modem) + * + * Downstream equivalent (BAM_DMUX_LOG / BAM_DMUX_INFO): + * "handle_bam_mux_cmd: opening cid N PC enabled" + * "msm_bam_dmux_open: opening/opened ch N" + * "msm_bam_dmux_close: closing/closed ch N" + */ +TRACE_EVENT(bam_dmux_channel, + TP_PROTO(const struct device *dev, u8 ch, const char *event), + TP_ARGS(dev, ch, event), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(u8, ch) + __string(event, event) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->ch = ch; + __assign_str(event); + ), + TP_printk("%s: ch %u %s", + __get_str(dev_name), __entry->ch, __get_str(event)) +); + +/* + * Fired in bam_dmux_rx_callback() for every valid inbound packet after + * magic and channel validation. For data packets, len is the payload + * length. For control packets (OPEN/CLOSE), len is 0. + * + * Downstream equivalent (BAM_DMUX_INFO via handle_bam_mux_cmd): + * "handle_bam_mux_cmd: magic 33fc signal %x cmd %d pad %d ch %d len %d" + */ +TRACE_EVENT(bam_dmux_rx, + TP_PROTO(const struct device *dev, u8 ch, u8 cmd, u16 len), + TP_ARGS(dev, ch, cmd, len), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(u8, ch) + __field(u8, cmd) + __field(u16, len) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->ch = ch; + __entry->cmd = cmd; + __entry->len = len; + ), + TP_printk("%s: rx ch %u cmd %u len %u", + __get_str(dev_name), __entry->ch, __entry->cmd, __entry->len) +); + +#endif /* __QCOM_BAM_DMUX_TRACE_H__ */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . + +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE trace-bam-dmux + +#include From fc441badecf2aefbc0b9760bb6a296f54aba0320 Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:41 +0800 Subject: [PATCH 1076/1330] FROMLIST: ACPI/AEST: Parse the AEST table This patch introduces the creation of AEST platform devices, where each device represents a logical "error node device" grouping one or more AEST nodes from the ACPI table. Instead of relying on the optional 'error_node_device' field in the AEST table[1], this commit uses the interrupt number as the sole identifier for the parent device. This design simplifies the driver logic by providing a single, consistent mechanism for grouping nodes. The 'error_node_device' field can be unspecified, but an AEST node is always physically associated with a parent component. The interrupt number serves as a reliable proxy for this association. This approach is based on the safe assumption that distinct hardware components (e.g., SMMU, CMN, GIC) are assigned unique error interrupts and do not share them. [1]: https://developer.arm.com/documentation/den0085/latest Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-2-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit c1d94cc19c0c63d78ffc8dd0cdfd35f12790ccde) --- MAINTAINERS | 8 + arch/arm64/include/asm/ras.h | 15 ++ drivers/acpi/arm64/Kconfig | 11 ++ drivers/acpi/arm64/Makefile | 1 + drivers/acpi/arm64/aest.c | 311 +++++++++++++++++++++++++++++++++++ include/linux/acpi_aest.h | 56 +++++++ 6 files changed, 402 insertions(+) create mode 100644 arch/arm64/include/asm/ras.h create mode 100644 drivers/acpi/arm64/aest.c create mode 100644 include/linux/acpi_aest.h diff --git a/MAINTAINERS b/MAINTAINERS index d10d5ccdb5e60..c06a570efa586 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -356,6 +356,14 @@ S: Maintained F: drivers/acpi/arm64 F: include/linux/acpi_iort.h +ACPI AEST +M: Ruidong Tian +L: linux-acpi@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org +S: Supported +F: drivers/acpi/arm64/aest.c +F: include/linux/acpi_aest.h + ACPI FOR RISC-V (ACPI/riscv) M: Sunil V L L: linux-acpi@vger.kernel.org diff --git a/arch/arm64/include/asm/ras.h b/arch/arm64/include/asm/ras.h new file mode 100644 index 0000000000000..b6640b9972bfb --- /dev/null +++ b/arch/arm64/include/asm/ras.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_RAS_H +#define __ASM_RAS_H + +#include + +struct ras_ext_regs { + u64 err_fr; + u64 err_ctlr; + u64 err_status; + u64 err_addr; + u64 err_misc[4]; +}; + +#endif /* __ASM_RAS_H */ diff --git a/drivers/acpi/arm64/Kconfig b/drivers/acpi/arm64/Kconfig index f2fd79f22e7d8..52df190356c82 100644 --- a/drivers/acpi/arm64/Kconfig +++ b/drivers/acpi/arm64/Kconfig @@ -24,3 +24,14 @@ config ACPI_APMT config ACPI_MPAM bool + +config ACPI_AEST + bool "ARM Error Source Table Support" + depends on ARM64_RAS_EXTN + + help + The Arm Error Source Table (AEST) provides details on ACPI + extensions that enable kernel-first handling of errors in a + system that supports the Armv8 RAS extensions. + + If set, the kernel will report and log hardware errors. diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile index 9390b57cb5648..bad77fdbf8dd0 100644 --- a/drivers/acpi/arm64/Makefile +++ b/drivers/acpi/arm64/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_ACPI_IORT) += iort.o obj-$(CONFIG_ACPI_MPAM) += mpam.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o obj-$(CONFIG_ARM_AMBA) += amba.o +obj-$(CONFIG_ACPI_AEST) += aest.o obj-y += dma.o init.o obj-y += thermal_cpufreq.o diff --git a/drivers/acpi/arm64/aest.c b/drivers/acpi/arm64/aest.c new file mode 100644 index 0000000000000..b8359b95f40f9 --- /dev/null +++ b/drivers/acpi/arm64/aest.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Error Source Table Support + * + * Copyright (c) 2025, Alibaba Group. + */ + +#include +#include +#include + +#include "init.h" + +#undef pr_fmt +#define pr_fmt(fmt) "ACPI AEST: " fmt + +static struct xarray *aest_array; + +static void __init aest_init_interface(struct acpi_aest_hdr *hdr, + struct acpi_aest_node *node) +{ + struct acpi_aest_node_interface_header *interface; + + interface = ACPI_ADD_PTR(struct acpi_aest_node_interface_header, hdr, + hdr->node_interface_offset); + + node->type = hdr->type; + node->interface_hdr = interface; + + switch (interface->group_format) { + case ACPI_AEST_NODE_GROUP_FORMAT_4K: { + struct acpi_aest_node_interface_4k *interface_4k = + (struct acpi_aest_node_interface_4k *)(interface + 1); + + node->common = &interface_4k->common; + node->record_implemented = + (unsigned long *)&interface_4k->error_record_implemented; + node->status_reporting = + (unsigned long *)&interface_4k->error_status_reporting; + node->addressing_mode = + (unsigned long *)&interface_4k->addressing_mode; + break; + } + case ACPI_AEST_NODE_GROUP_FORMAT_16K: { + struct acpi_aest_node_interface_16k *interface_16k = + (struct acpi_aest_node_interface_16k *)(interface + 1); + + node->common = &interface_16k->common; + node->record_implemented = + (unsigned long *)interface_16k->error_record_implemented; + node->status_reporting = + (unsigned long *)interface_16k->error_status_reporting; + node->addressing_mode = + (unsigned long *)interface_16k->addressing_mode; + break; + } + case ACPI_AEST_NODE_GROUP_FORMAT_64K: { + struct acpi_aest_node_interface_64k *interface_64k = + (struct acpi_aest_node_interface_64k *)(interface + 1); + + node->common = &interface_64k->common; + node->record_implemented = + (unsigned long *)interface_64k->error_record_implemented; + node->status_reporting = + (unsigned long *)interface_64k->error_status_reporting; + node->addressing_mode = + (unsigned long *)interface_64k->addressing_mode; + break; + } + default: + pr_err("invalid group format: %d\n", interface->group_format); + } + + node->interrupt = ACPI_ADD_PTR(struct acpi_aest_node_interrupt_v2, hdr, + hdr->node_interrupt_offset); + + node->interrupt_count = hdr->node_interrupt_count; +} + +static struct aest_hnode *__init +acpi_aest_alloc_ahnode(struct acpi_aest_node *node, u64 error_device_id) +{ + struct aest_hnode *ahnode __free(kfree) = NULL; + + ahnode = kzalloc(sizeof(*ahnode), GFP_KERNEL); + if (!ahnode) + return NULL; + + INIT_LIST_HEAD(&ahnode->list); + ahnode->id = error_device_id; + ahnode->count = 0; + ahnode->type = node->type; + + return_ptr(ahnode); +} +static int __init acpi_aest_init_node(struct acpi_aest_hdr *aest_hdr) +{ + struct aest_hnode *ahnode; + u64 error_device_id; + struct acpi_aest_node *node; + + node = kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) + return -ENOMEM; + + node->spec_pointer = + ACPI_ADD_PTR(void, aest_hdr, aest_hdr->node_specific_offset); + if (aest_hdr->type == ACPI_AEST_PROCESSOR_ERROR_NODE) + node->processor_spec_pointer = + ACPI_ADD_PTR(void, node->spec_pointer, + sizeof(struct acpi_aest_processor)); + + aest_init_interface(aest_hdr, node); + + if (node->interrupt_count <= 0) + return -EINVAL; + + error_device_id = node->interrupt[0].gsiv; + ahnode = xa_load(aest_array, error_device_id); + if (!ahnode) { + ahnode = acpi_aest_alloc_ahnode(node, error_device_id); + if (!ahnode) + return -ENOMEM; + xa_store(aest_array, error_device_id, ahnode, GFP_KERNEL); + } + + list_add_tail(&node->list, &ahnode->list); + ahnode->count++; + + return 0; +} + +static int __init acpi_aest_init_nodes(struct acpi_table_header *aest_table) +{ + struct acpi_aest_hdr *aest_node, *aest_end; + struct acpi_table_aest *aest; + int rc; + + aest = (struct acpi_table_aest *)aest_table; + aest_node = ACPI_ADD_PTR(struct acpi_aest_hdr, aest, + sizeof(struct acpi_table_header)); + aest_end = ACPI_ADD_PTR(struct acpi_aest_hdr, aest, aest_table->length); + + while (aest_node < aest_end) { + if (((u64)aest_node + aest_node->length) > (u64)aest_end) { + pr_warn(FW_WARN + "AEST node pointer overflow, bad table.\n"); + return -EINVAL; + } + + rc = acpi_aest_init_node(aest_node); + if (rc) + return rc; + + aest_node = ACPI_ADD_PTR(struct acpi_aest_hdr, aest_node, + aest_node->length); + } + + return 0; +} + +static int acpi_aest_parse_irqs(struct platform_device *pdev, + struct acpi_aest_node *anode, + struct resource *res, int *res_idx, int irqs[2]) +{ + int i; + struct acpi_aest_node_interrupt_v2 *interrupt; + int trigger, irq; + + for (i = 0; i < anode->interrupt_count; i++) { + interrupt = &anode->interrupt[i]; + if (irqs[interrupt->type]) + continue; + + trigger = (interrupt->flags & AEST_INTERRUPT_MODE) ? + ACPI_LEVEL_SENSITIVE : + ACPI_EDGE_SENSITIVE; + + irq = acpi_register_gsi(&pdev->dev, interrupt->gsiv, trigger, + ACPI_ACTIVE_HIGH); + if (irq <= 0) { + pr_err("failed to map AEST GSI %d\n", interrupt->gsiv); + return irq; + } + + res[*res_idx].start = irq; + res[*res_idx].end = irq; + res[*res_idx].flags = IORESOURCE_IRQ; + res[*res_idx].name = interrupt->type ? AEST_ERI_NAME : + AEST_FHI_NAME; + + (*res_idx)++; + + irqs[interrupt->type] = irq; + } + + return 0; +} + +DEFINE_FREE(res, struct resource *, if (_T) kfree(_T)) +static struct platform_device *__init +acpi_aest_alloc_pdev(struct aest_hnode *ahnode, int index) +{ + struct platform_device *pdev __free(platform_device_put) = + platform_device_alloc("AEST", index++); + struct resource *res __free(res); + struct acpi_aest_node *anode; + int ret, size, j, irq[AEST_MAX_INTERRUPT_PER_NODE] = { 0 }; + + if (!pdev) + return ERR_PTR(-ENOMEM); + + res = kcalloc(ahnode->count + AEST_MAX_INTERRUPT_PER_NODE, sizeof(*res), + GFP_KERNEL); + if (!res) + return ERR_PTR(-ENOMEM); + + j = 0; + list_for_each_entry(anode, &ahnode->list, list) { + if (anode->interface_hdr->type != + ACPI_AEST_NODE_SYSTEM_REGISTER) { + res[j].name = AEST_NODE_NAME; + res[j].start = anode->interface_hdr->address; + switch (anode->interface_hdr->group_format) { + case ACPI_AEST_NODE_GROUP_FORMAT_4K: + size = 4 * KB; + break; + case ACPI_AEST_NODE_GROUP_FORMAT_16K: + size = 16 * KB; + break; + case ACPI_AEST_NODE_GROUP_FORMAT_64K: + size = 64 * KB; + break; + default: + size = 4 * KB; + } + res[j].end = res[j].start + size - 1; + res[j].flags = IORESOURCE_MEM; + } + + ret = acpi_aest_parse_irqs(pdev, anode, res, &j, irq); + if (ret) + return ERR_PTR(ret); + } + + ret = platform_device_add_resources(pdev, res, j); + if (ret) + return ERR_PTR(ret); + + ret = platform_device_add_data(pdev, &ahnode, sizeof(ahnode)); + if (ret) + return ERR_PTR(ret); + + ret = platform_device_add(pdev); + if (ret) + return ERR_PTR(ret); + + return_ptr(pdev); +} +static int __init acpi_aest_alloc_pdevs(void) +{ + int ret = 0, index = 0; + struct aest_hnode *ahnode = NULL; + unsigned long i; + + xa_for_each(aest_array, i, ahnode) { + struct platform_device *pdev = + acpi_aest_alloc_pdev(ahnode, index++); + + if (IS_ERR(pdev)) { + ret = PTR_ERR(pdev); + break; + } + } + + return ret; +} + +static int __init acpi_aest_init(void) +{ + int ret; + + if (acpi_disabled) + return 0; + + struct acpi_table_header *aest_table __free(acpi_put_table) = + acpi_get_table_pointer(ACPI_SIG_AEST, 0); + if (IS_ERR(aest_table)) + return 0; + + aest_array = kzalloc(sizeof(struct xarray), GFP_KERNEL); + if (!aest_array) + return -ENOMEM; + + xa_init(aest_array); + + ret = acpi_aest_init_nodes(aest_table); + if (ret) { + pr_err("Failed init aest node %d\n", ret); + return ret; + } + + ret = acpi_aest_alloc_pdevs(); + if (ret) { + pr_err("Failed alloc pdev %d\n", ret); + return ret; + } + + return 0; +} +subsys_initcall_sync(acpi_aest_init); diff --git a/include/linux/acpi_aest.h b/include/linux/acpi_aest.h new file mode 100644 index 0000000000000..53c1970e7583b --- /dev/null +++ b/include/linux/acpi_aest.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ACPI_AEST_H__ +#define __ACPI_AEST_H__ + +#include +#include + +/* AEST resource name */ +#define AEST_NODE_NAME "AEST:NODE" +#define AEST_FHI_NAME "AEST:FHI" +#define AEST_ERI_NAME "AEST:ERI" + +/* AEST interrupt */ +#define AEST_INTERRUPT_MODE BIT(0) + +#define AEST_MAX_INTERRUPT_PER_NODE 2 + +#define KB 1024 +#define MB (1024 * KB) +#define GB (1024 * MB) + +struct aest_hnode { + struct list_head list; + int count; + u32 id; + int type; +}; + +struct acpi_aest_node { + struct list_head list; + int type; + struct acpi_aest_node_interface_header *interface_hdr; + unsigned long *record_implemented; + unsigned long *status_reporting; + unsigned long *addressing_mode; + struct acpi_aest_node_interface_common *common; + union { + struct acpi_aest_processor *processor; + struct acpi_aest_memory *memory; + struct acpi_aest_smmu *smmu; + struct acpi_aest_vendor_v2 *vendor; + struct acpi_aest_gic *gic; + struct acpi_aest_pcie *pcie; + struct acpi_aest_proxy *proxy; + void *spec_pointer; + }; + union { + struct acpi_aest_processor_cache *cache; + struct acpi_aest_processor_tlb *tlb; + struct acpi_aest_processor_generic *generic; + void *processor_spec_pointer; + }; + struct acpi_aest_node_interrupt_v2 *interrupt; + int interrupt_count; +}; +#endif /* __ACPI_AEST_H__ */ From 8b8a69b39b7c161f226a0df97298eddd0e3c680c Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:42 +0800 Subject: [PATCH 1077/1330] FROMLIST: ras: AEST: Add probe/remove for AEST driver Parse register information from the AEST table in the probe function, create corresponding structures, and mappings AEST record. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-3-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 7530c56275309565d43b56a1db6fb6df4326fab8) --- MAINTAINERS | 2 + drivers/ras/Kconfig | 1 + drivers/ras/Makefile | 1 + drivers/ras/aest/Kconfig | 17 +++ drivers/ras/aest/Makefile | 5 + drivers/ras/aest/aest-core.c | 217 +++++++++++++++++++++++++++++++++++ drivers/ras/aest/aest.h | 124 ++++++++++++++++++++ include/linux/acpi_aest.h | 9 ++ 8 files changed, 376 insertions(+) create mode 100644 drivers/ras/aest/Kconfig create mode 100644 drivers/ras/aest/Makefile create mode 100644 drivers/ras/aest/aest-core.c create mode 100644 drivers/ras/aest/aest.h diff --git a/MAINTAINERS b/MAINTAINERS index c06a570efa586..936d39d07d9dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -361,7 +361,9 @@ M: Ruidong Tian L: linux-acpi@vger.kernel.org L: linux-arm-kernel@lists.infradead.org S: Supported +F: arch/arm64/include/asm/ras.h F: drivers/acpi/arm64/aest.c +F: drivers/ras/aest/ F: include/linux/acpi_aest.h ACPI FOR RISC-V (ACPI/riscv) diff --git a/drivers/ras/Kconfig b/drivers/ras/Kconfig index fc4f4bb94a4c6..61a2a05d9c949 100644 --- a/drivers/ras/Kconfig +++ b/drivers/ras/Kconfig @@ -33,6 +33,7 @@ if RAS source "arch/x86/ras/Kconfig" source "drivers/ras/amd/atl/Kconfig" +source "drivers/ras/aest/Kconfig" config RAS_FMPM tristate "FRU Memory Poison Manager" diff --git a/drivers/ras/Makefile b/drivers/ras/Makefile index 11f95d59d3972..72411ee9deafd 100644 --- a/drivers/ras/Makefile +++ b/drivers/ras/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_RAS_CEC) += cec.o obj-$(CONFIG_RAS_FMPM) += amd/fmpm.o obj-y += amd/atl/ +obj-y += aest/ diff --git a/drivers/ras/aest/Kconfig b/drivers/ras/aest/Kconfig new file mode 100644 index 0000000000000..0b09a5d5acce3 --- /dev/null +++ b/drivers/ras/aest/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# ARM Error Source Table Support +# +# Copyright (c) 2025, Alibaba Group. +# + +config AEST + tristate "ARM AEST Driver" + depends on ACPI_AEST && RAS + + help + The Arm Error Source Table (AEST) provides details on ACPI + extensions that enable kernel-first handling of errors in a + system that supports the Armv8 RAS extensions. + + If set, the kernel will report and log hardware errors. diff --git a/drivers/ras/aest/Makefile b/drivers/ras/aest/Makefile new file mode 100644 index 0000000000000..a6ba7e36fb432 --- /dev/null +++ b/drivers/ras/aest/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_AEST) += aest.o + +aest-y := aest-core.o diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c new file mode 100644 index 0000000000000..c7ef6c13fd440 --- /dev/null +++ b/drivers/ras/aest/aest-core.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Error Source Table Support + * + * Copyright (c) 2025, Alibaba Group. + */ + +#include +#include +#include + +#include "aest.h" + +DEFINE_PER_CPU(struct aest_device, percpu_adev); + +#undef pr_fmt +#define pr_fmt(fmt) "AEST: " fmt + +static int aest_init_record(struct aest_record *record, int i, + struct aest_node *node) +{ + struct device *dev = node->adev->dev; + + record->name = devm_kasprintf(dev, GFP_KERNEL, "record%d", i); + if (!record->name) + return -ENOMEM; + + if (node->base) + record->regs_base = + node->base + sizeof(struct ras_ext_regs) * i; + + record->addressing_mode = test_bit(i, node->info->addressing_mode); + record->index = i; + record->node = node; + + aest_record_dbg(record, "base: %p, index: %d, address mode: %x\n", + record->regs_base, record->index, + record->addressing_mode); + return 0; +} + +static void aest_device_remove(struct platform_device *pdev) +{ + platform_set_drvdata(pdev, NULL); +} + +static char *alloc_aest_node_name(struct aest_node *node) +{ + char *name; + + switch (node->type) { + case ACPI_AEST_PROCESSOR_ERROR_NODE: + name = devm_kasprintf(node->adev->dev, GFP_KERNEL, "%s.%d", + aest_node_name[node->type], + node->info->processor->processor_id); + break; + case ACPI_AEST_MEMORY_ERROR_NODE: + case ACPI_AEST_SMMU_ERROR_NODE: + case ACPI_AEST_VENDOR_ERROR_NODE: + case ACPI_AEST_GIC_ERROR_NODE: + case ACPI_AEST_PCIE_ERROR_NODE: + case ACPI_AEST_PROXY_ERROR_NODE: + name = devm_kasprintf(node->adev->dev, GFP_KERNEL, "%s.%llx", + aest_node_name[node->type], + node->info->interface_hdr->address); + break; + default: + name = devm_kasprintf(node->adev->dev, GFP_KERNEL, "Unknown"); + } + + return name; +} + +static int aest_node_set_errgsr(struct aest_device *adev, + struct aest_node *node) +{ + struct acpi_aest_node *anode = node->info; + u64 errgsr_base = anode->common->error_group_register_base; + + if (anode->interface_hdr->type != ACPI_AEST_NODE_MEMORY_MAPPED) + return 0; + + if (!node->base) + return 0; + + if (!(anode->interface_hdr->flags & AEST_XFACE_FLAG_ERROR_GROUP)) { + node->errgsr = node->base + ERXGROUP; + return 0; + } + + if (!errgsr_base) + return -EINVAL; + + node->errgsr = devm_ioremap(adev->dev, errgsr_base, PAGE_SIZE); + if (!node->errgsr) + return -ENOMEM; + + return 0; +} + +static int aest_init_node(struct aest_device *adev, struct aest_node *node, + struct acpi_aest_node *anode) +{ + int i, ret; + u64 address; + + node->adev = adev; + node->info = anode; + node->type = anode->type; + node->name = alloc_aest_node_name(node); + if (!node->name) + return -ENOMEM; + node->record_implemented = anode->record_implemented; + node->status_reporting = anode->status_reporting; + + address = anode->interface_hdr->address; + if (address) { + node->base = devm_ioremap(adev->dev, address, PAGE_SIZE); + if (!node->base) + return -ENOMEM; + } + + ret = aest_node_set_errgsr(adev, node); + if (ret) + return ret; + + node->record_count = anode->interface_hdr->error_record_count; + node->records = devm_kcalloc(adev->dev, node->record_count, + sizeof(struct aest_record), GFP_KERNEL); + if (!node->records) + return -ENOMEM; + + for (i = 0; i < node->record_count; i++) { + ret = aest_init_record(&node->records[i], i, node); + if (ret) + return ret; + } + aest_node_dbg(node, "%d records, base: %llx, errgsr: %llx\n", + node->record_count, (u64)node->base, (u64)node->errgsr); + return 0; +} + +static int aest_init_nodes(struct aest_device *adev, struct aest_hnode *ahnode) +{ + struct acpi_aest_node *anode; + struct aest_node *node; + int ret, i = 0; + + adev->node_cnt = ahnode->count; + adev->nodes = devm_kcalloc(adev->dev, adev->node_cnt, + sizeof(struct aest_node), GFP_KERNEL); + if (!adev->nodes) + return -ENOMEM; + + list_for_each_entry(anode, &ahnode->list, list) { + adev->type = anode->type; + + node = &adev->nodes[i++]; + ret = aest_init_node(adev, node, anode); + if (ret) + return ret; + } + + return 0; +} + +static int aest_device_probe(struct platform_device *pdev) +{ + int ret; + struct aest_device *adev; + struct aest_hnode *ahnode; + + ahnode = *((struct aest_hnode **)pdev->dev.platform_data); + if (!ahnode) + return -ENODEV; + + adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); + if (!adev) + return -ENOMEM; + + adev->dev = &pdev->dev; + adev->id = pdev->id; + aest_set_name(adev, ahnode); + ret = aest_init_nodes(adev, ahnode); + if (ret) + return ret; + + platform_set_drvdata(pdev, adev); + + aest_dev_dbg(adev, "Node cnt: %x, id: %x\n", adev->node_cnt, adev->id); + + return 0; +} + +static struct platform_driver aest_driver = { + .driver = { + .name = "AEST", + }, + .probe = aest_device_probe, + .remove = aest_device_remove, +}; + +static int __init aest_init(void) +{ + return platform_driver_register(&aest_driver); +} +module_init(aest_init); + +static void __exit aest_exit(void) +{ + platform_driver_unregister(&aest_driver); +} +module_exit(aest_exit); + +MODULE_DESCRIPTION("ARM AEST Driver"); +MODULE_AUTHOR("Ruidong Tian "); +MODULE_LICENSE("GPL"); diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h new file mode 100644 index 0000000000000..d918240c3f57e --- /dev/null +++ b/drivers/ras/aest/aest.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ARM Error Source Table Support + * + * Copyright (c) 2025, Alibaba Group. + */ + +#include +#include + +#define MAX_GSI_PER_NODE 2 + +#define aest_dev_err(__adev, format, ...) \ + dev_err((__adev)->dev, format, ##__VA_ARGS__) +#define aest_dev_info(__adev, format, ...) \ + dev_info((__adev)->dev, format, ##__VA_ARGS__) +#define aest_dev_dbg(__adev, format, ...) \ + dev_dbg((__adev)->dev, format, ##__VA_ARGS__) + +#define aest_node_err(__node, format, ...) \ + dev_err((__node)->adev->dev, "%s: " format, (__node)->name, \ + ##__VA_ARGS__) +#define aest_node_info(__node, format, ...) \ + dev_info((__node)->adev->dev, "%s: " format, (__node)->name, \ + ##__VA_ARGS__) +#define aest_node_dbg(__node, format, ...) \ + dev_dbg((__node)->adev->dev, "%s: " format, (__node)->name, \ + ##__VA_ARGS__) + +#define aest_record_err(__record, format, ...) \ + dev_err((__record)->node->adev->dev, "%s: %s: " format, \ + (__record)->node->name, (__record)->name, ##__VA_ARGS__) +#define aest_record_info(__record, format, ...) \ + dev_info((__record)->node->adev->dev, "%s: %s: " format, \ + (__record)->node->name, (__record)->name, ##__VA_ARGS__) +#define aest_record_dbg(__record, format, ...) \ + dev_dbg((__record)->node->adev->dev, "%s: %s: " format, \ + (__record)->node->name, (__record)->name, ##__VA_ARGS__) + +#define ERXGROUP 0xE00 + +struct aest_record { + char *name; + int index; + void __iomem *regs_base; + + /* + * This bit specifies the addressing mode to populate the ERR_ADDR + * register: + * 0b: Error record reports System Physical Addresses (SPA) in + * the ERR_ADDR register. + * 1b: Error record reports error node-specific Logical Addresses(LA) + * in the ERR_ADD register. OS must use other means to translate + * the reported LA into SPA + */ + int addressing_mode; + struct aest_node *node; +}; + +struct aest_node { + char *name; + u8 type; + void *errgsr; + void *base; + + /* + * This bitmap indicates which of the error records within this error + * node must be polled for error status. + * Bit[n] of this field pertains to error record corresponding to + * index n in this error group. + * Bit[n] = 0b: Error record at index n needs to be polled. + * Bit[n] = 1b: Error record at index n do not needs to be polled. + */ + unsigned long *record_implemented; + /* + * This bitmap indicates which of the error records within this error + * node support error status reporting using ERRGSR register. + * Bit[n] of this field pertains to error record corresponding to + * index n in this error group. + * Bit[n] = 0b: Error record at index n supports error status reporting + * through ERRGSR.S. + * Bit[n] = 1b: Error record at index n does not support error reporting + * through the ERRGSR.S bit If this error record is + * implemented, then it must be polled explicitly for + * error events. + */ + unsigned long *status_reporting; + + struct aest_device *adev; + struct acpi_aest_node *info; + + int record_count; + struct aest_record *records; +}; + +struct aest_device { + struct device *dev; + u32 type; + int node_cnt; + struct aest_node *nodes; + u32 id; +}; + +static const char *const aest_node_name[] = { + [ACPI_AEST_PROCESSOR_ERROR_NODE] = "processor", + [ACPI_AEST_MEMORY_ERROR_NODE] = "memory", + [ACPI_AEST_SMMU_ERROR_NODE] = "smmu", + [ACPI_AEST_VENDOR_ERROR_NODE] = "vendor", + [ACPI_AEST_GIC_ERROR_NODE] = "gic", + [ACPI_AEST_PCIE_ERROR_NODE] = "pcie", + [ACPI_AEST_PROXY_ERROR_NODE] = "proxy", +}; + +static inline int aest_set_name(struct aest_device *adev, + struct aest_hnode *ahnode) +{ + adev->dev->init_name = devm_kasprintf(adev->dev, GFP_KERNEL, "%s%d", + aest_node_name[ahnode->type], + adev->id); + if (!adev->dev->init_name) + return -ENOMEM; + + return 0; +} diff --git a/include/linux/acpi_aest.h b/include/linux/acpi_aest.h index 53c1970e7583b..77187ce43d44b 100644 --- a/include/linux/acpi_aest.h +++ b/include/linux/acpi_aest.h @@ -15,6 +15,15 @@ #define AEST_MAX_INTERRUPT_PER_NODE 2 +/* AEST interface */ +#define AEST_XFACE_FLAG_SHARED (1 << 0) +#define AEST_XFACE_FLAG_CLEAR_MISC (1 << 1) +#define AEST_XFACE_FLAG_ERROR_DEVICE (1 << 2) +#define AEST_XFACE_FLAG_AFFINITY (1 << 3) +#define AEST_XFACE_FLAG_ERROR_GROUP (1 << 4) +#define AEST_XFACE_FLAG_FAULT_INJECT (1 << 5) +#define AEST_XFACE_FLAG_INT_CONFIG (1 << 6) + #define KB 1024 #define MB (1024 * KB) #define GB (1024 * MB) From eb1a08b0bef910beb51fd7d3700c4aa5fe478c0e Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:43 +0800 Subject: [PATCH 1078/1330] FROMLIST: ras: AEST: support different group format Support for various AEST group formats allows for flexible configuration of AEST node address space sizes and maximum record counts per group. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-4-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 7da73d25db320395408f576490f3dc1018124eda) --- drivers/ras/aest/aest-core.c | 6 ++++-- drivers/ras/aest/aest.h | 39 +++++++++++++++++++++++++++++++++++- 2 files changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index c7ef6c13fd440..acebb293ac75a 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -84,7 +84,7 @@ static int aest_node_set_errgsr(struct aest_device *adev, return 0; if (!(anode->interface_hdr->flags & AEST_XFACE_FLAG_ERROR_GROUP)) { - node->errgsr = node->base + ERXGROUP; + node->errgsr = node->base + node->group->errgsr_offset; return 0; } @@ -112,10 +112,12 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node, return -ENOMEM; node->record_implemented = anode->record_implemented; node->status_reporting = anode->status_reporting; + node->group = &aest_group_config[anode->interface_hdr->group_format]; address = anode->interface_hdr->address; if (address) { - node->base = devm_ioremap(adev->dev, address, PAGE_SIZE); + node->base = + devm_ioremap(adev->dev, address, node->group->size); if (!node->base) return -ENOMEM; } diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index d918240c3f57e..3250675e99b77 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -37,7 +37,15 @@ dev_dbg((__record)->node->adev->dev, "%s: %s: " format, \ (__record)->node->name, (__record)->name, ##__VA_ARGS__) -#define ERXGROUP 0xE00 +#define ERXGROUP_4K_OFFSET 0xE00 +#define ERXGROUP_16K_OFFSET 0x3800 +#define ERXGROUP_64K_OFFSET 0xE000 +#define ERXGROUP_4K_SIZE (4 * KB) +#define ERXGROUP_16K_SIZE (16 * KB) +#define ERXGROUP_64K_SIZE (64 * KB) +#define ERXGROUP_4K_ERRGSR_NUM 1 +#define ERXGROUP_16K_ERRGSR_NUM 4 +#define ERXGROUP_64K_ERRGSR_NUM 14 struct aest_record { char *name; @@ -57,6 +65,34 @@ struct aest_record { struct aest_node *node; }; +struct aest_group { + int type; + int errgsr_num; + size_t size; + u64 errgsr_offset; +}; + +static const struct aest_group aest_group_config[] = { + [ACPI_AEST_NODE_GROUP_FORMAT_4K] = { + .type = ACPI_AEST_NODE_GROUP_FORMAT_4K, + .errgsr_num = ERXGROUP_4K_ERRGSR_NUM, + .size = ERXGROUP_4K_SIZE, + .errgsr_offset = ERXGROUP_4K_OFFSET, + }, + [ACPI_AEST_NODE_GROUP_FORMAT_16K] = { + .type = ACPI_AEST_NODE_GROUP_FORMAT_16K, + .errgsr_num = ERXGROUP_16K_ERRGSR_NUM, + .size = ERXGROUP_16K_SIZE, + .errgsr_offset = ERXGROUP_16K_OFFSET, + }, + [ACPI_AEST_NODE_GROUP_FORMAT_64K] = { + .type = ACPI_AEST_NODE_GROUP_FORMAT_64K, + .errgsr_num = ERXGROUP_64K_ERRGSR_NUM, + .size = ERXGROUP_64K_SIZE, + .errgsr_offset = ERXGROUP_64K_OFFSET, + }, +}; + struct aest_node { char *name; u8 type; @@ -86,6 +122,7 @@ struct aest_node { */ unsigned long *status_reporting; + const struct aest_group *group; struct aest_device *adev; struct acpi_aest_node *info; From 6d9561eaac8206db67bb779ca96e06c779421dfd Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:44 +0800 Subject: [PATCH 1079/1330] FROMLIST: ras: AEST: Unify the read/write interface for system and MMIO register Use record_read/write to simultaneously read and write system registers and MMIO registers while maintaining code conciseness. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-5-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 0a2c44115f9a2e9f86f3f5684ad71e1b4206872c) --- drivers/ras/aest/aest-core.c | 1 + drivers/ras/aest/aest.h | 94 ++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index acebb293ac75a..f4a5119dc513b 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -29,6 +29,7 @@ static int aest_init_record(struct aest_record *record, int i, record->regs_base = node->base + sizeof(struct ras_ext_regs) * i; + record->access = &aest_access[node->info->interface_hdr->type]; record->addressing_mode = test_bit(i, node->info->addressing_mode); record->index = i; record->node = node; diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 3250675e99b77..31131cce99281 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -10,6 +10,11 @@ #define MAX_GSI_PER_NODE 2 +#define record_read(record, offset) \ + record->access->read(record->regs_base, offset) +#define record_write(record, offset, val) \ + record->access->write(record->regs_base, offset, val) + #define aest_dev_err(__adev, format, ...) \ dev_err((__adev)->dev, format, ##__VA_ARGS__) #define aest_dev_info(__adev, format, ...) \ @@ -47,6 +52,20 @@ #define ERXGROUP_16K_ERRGSR_NUM 4 #define ERXGROUP_64K_ERRGSR_NUM 14 +#define ERXFR 0x0 +#define ERXCTLR 0x8 +#define ERXSTATUS 0x10 +#define ERXADDR 0x18 +#define ERXMISC0 0x20 +#define ERXMISC1 0x28 +#define ERXMISC2 0x30 +#define ERXMISC3 0x38 + +struct aest_access { + u64 (*read)(void *base, u32 offset); + void (*write)(void *base, u32 offset, u64 val); +}; + struct aest_record { char *name; int index; @@ -63,6 +82,7 @@ struct aest_record { */ int addressing_mode; struct aest_node *node; + const struct aest_access *access; }; struct aest_group { @@ -159,3 +179,77 @@ static inline int aest_set_name(struct aest_device *adev, return 0; } + +#define CASE_READ(res, x) \ + case (x): { \ + res = read_sysreg_s(SYS_##x##_EL1); \ + break; \ + } + +#define CASE_WRITE(val, x) \ + case (x): { \ + write_sysreg_s((val), SYS_##x##_EL1); \ + break; \ + } + +static inline u64 aest_sysreg_read(void *__unused, u32 offset) +{ + u64 res; + + switch (offset) { + CASE_READ(res, ERXFR) + CASE_READ(res, ERXCTLR) + CASE_READ(res, ERXSTATUS) + CASE_READ(res, ERXADDR) + CASE_READ(res, ERXMISC0) + CASE_READ(res, ERXMISC1) + CASE_READ(res, ERXMISC2) + CASE_READ(res, ERXMISC3) + default : + res = 0; + } + return res; +} + +static inline void aest_sysreg_write(void *base, u32 offset, u64 val) +{ + switch (offset) { + CASE_WRITE(val, ERXFR) + CASE_WRITE(val, ERXCTLR) + CASE_WRITE(val, ERXSTATUS) + CASE_WRITE(val, ERXADDR) + CASE_WRITE(val, ERXMISC0) + CASE_WRITE(val, ERXMISC1) + CASE_WRITE(val, ERXMISC2) + CASE_WRITE(val, ERXMISC3) + default : + return; + } +} + +static inline u64 aest_iomem_read(void *base, u32 offset) +{ + return readq_relaxed(base + offset); +} + +static inline void aest_iomem_write(void *base, u32 offset, u64 val) +{ + writeq_relaxed(val, base + offset); +} + +/* access type is decided by AEST interface type. */ +static const struct aest_access aest_access[] = { + [ACPI_AEST_NODE_SYSTEM_REGISTER] = { + .read = aest_sysreg_read, + .write = aest_sysreg_write, + }, + [ACPI_AEST_NODE_MEMORY_MAPPED] = { + .read = aest_iomem_read, + .write = aest_iomem_write, + }, + [ACPI_AEST_NODE_SINGLE_RECORD_MEMORY_MAPPED] = { + .read = aest_iomem_read, + .write = aest_iomem_write, + }, + { } +}; From 8ff6e08d06a358d9f359f007ce2f2ea464061eca Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:45 +0800 Subject: [PATCH 1080/1330] FROMLIST: ras: AEST: Probe RAS system architecture version The RAS version of a component can be probed via its ERRDEVARCH register. In cases where a component (e.g., SMMU) does not implement an ERRDEVARCH register, the driver falls back to using the RAS version of the Processing Element (PE). Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-6-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 53f61f152922baf7cab5f563c80bd2cba7fa88a5) --- arch/arm64/include/asm/ras.h | 3 +++ drivers/ras/aest/aest-core.c | 22 ++++++++++++++++++++++ drivers/ras/aest/aest.h | 3 +++ 3 files changed, 28 insertions(+) diff --git a/arch/arm64/include/asm/ras.h b/arch/arm64/include/asm/ras.h index b6640b9972bfb..da7c441252feb 100644 --- a/arch/arm64/include/asm/ras.h +++ b/arch/arm64/include/asm/ras.h @@ -4,6 +4,9 @@ #include +/* ERRDEVARCH */ +#define ERRDEVARCH_REV GENMASK(19, 16) + struct ras_ext_regs { u64 err_fr; u64 err_ctlr; diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index f4a5119dc513b..84b2fb8127ffc 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -16,6 +16,27 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); #undef pr_fmt #define pr_fmt(fmt) "AEST: " fmt +static int get_aest_node_ver(struct aest_node *node) +{ + u64 reg; + void *devarch_base; + + if (node->type == ACPI_AEST_GIC_ERROR_NODE) { + devarch_base = ioremap(node->info->interface_hdr->address + + GIC_ERRDEVARCH, + PAGE_SIZE); + if (!devarch_base) + return 0; + + reg = readl_relaxed(devarch_base); + iounmap(devarch_base); + + return FIELD_GET(ERRDEVARCH_REV, reg); + } + + return FIELD_GET(ID_AA64PFR0_EL1_RAS_MASK, read_cpuid(ID_AA64PFR0_EL1)); +} + static int aest_init_record(struct aest_record *record, int i, struct aest_node *node) { @@ -108,6 +129,7 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node, node->adev = adev; node->info = anode; node->type = anode->type; + node->version = get_aest_node_ver(node); node->name = alloc_aest_node_name(node); if (!node->name) return -ENOMEM; diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 31131cce99281..bf0b9a49fdaa2 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -61,6 +61,8 @@ #define ERXMISC2 0x30 #define ERXMISC3 0x38 +#define GIC_ERRDEVARCH 0xFFBC + struct aest_access { u64 (*read)(void *base, u32 offset); void (*write)(void *base, u32 offset, u64 val); @@ -141,6 +143,7 @@ struct aest_node { * error events. */ unsigned long *status_reporting; + int version; const struct aest_group *group; struct aest_device *adev; From 167047fa58adf543eae81c6d565e85f89d9bd9c2 Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:46 +0800 Subject: [PATCH 1081/1330] FROMLIST: ras: AEST: Support RAS Common Fault Injection Model Extension Add inject register descripted in Common Fault Injection Model Extension. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-7-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 4425653637bbf9c36ece49d1bc2e10f3fff18646) --- drivers/ras/aest/aest-core.c | 15 ++++++++++++++- drivers/ras/aest/aest.h | 10 ++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 84b2fb8127ffc..1218ae51079cf 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -124,7 +124,7 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node, struct acpi_aest_node *anode) { int i, ret; - u64 address; + u64 address, flags; node->adev = adev; node->info = anode; @@ -145,6 +145,19 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node, return -ENOMEM; } + flags = anode->interface_hdr->flags; + address = node->info->common->fault_inject_register_base; + if ((flags & AEST_XFACE_FLAG_FAULT_INJECT) && address) { + if (address - anode->interface_hdr->address < node->group->size) + node->inj = node->base + + (address - anode->interface_hdr->address); + else { + node->inj = devm_ioremap(adev->dev, address, PAGE_SIZE); + if (!node->inj) + return -ENOMEM; + } + } + ret = aest_node_set_errgsr(adev, node); if (ret) return ret; diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index bf0b9a49fdaa2..505ecd9635bcb 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -60,6 +60,9 @@ #define ERXMISC1 0x28 #define ERXMISC2 0x30 #define ERXMISC3 0x38 +#define ERXPFGF 0x800 +#define ERXPFGCTL 0x808 +#define ERXPFGCDN 0x810 #define GIC_ERRDEVARCH 0xFFBC @@ -120,6 +123,7 @@ struct aest_node { u8 type; void *errgsr; void *base; + void *inj; /* * This bitmap indicates which of the error records within this error @@ -208,6 +212,9 @@ static inline u64 aest_sysreg_read(void *__unused, u32 offset) CASE_READ(res, ERXMISC1) CASE_READ(res, ERXMISC2) CASE_READ(res, ERXMISC3) + CASE_READ(res, ERXPFGF) + CASE_READ(res, ERXPFGCTL) + CASE_READ(res, ERXPFGCDN) default : res = 0; } @@ -225,6 +232,9 @@ static inline void aest_sysreg_write(void *base, u32 offset, u64 val) CASE_WRITE(val, ERXMISC1) CASE_WRITE(val, ERXMISC2) CASE_WRITE(val, ERXMISC3) + CASE_WRITE(val, ERXPFGF) + CASE_WRITE(val, ERXPFGCTL) + CASE_WRITE(val, ERXPFGCDN) default : return; } From 48638e846f865daba447a6320210b01c397a246a Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:47 +0800 Subject: [PATCH 1082/1330] FROMLIST: ras: AEST: Support CE threshold of error record The CE threshold defines the number of Correctable Errors (CE) that must occur in a record before triggering an interrupt. Error records support multiple threshold configurations, including 8B, 16B, and 32B. This patch detects the supported threshold settings for error records and sets the default threshold to 1, ensuring an interrupt is generated for every CE occurrence. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-8-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 8dcb893bc634dce1c38a0401c0159867de5aac24) --- arch/arm64/include/asm/ras.h | 41 ++++++++++++++++++++ drivers/ras/aest/aest-core.c | 74 ++++++++++++++++++++++++++++++++++++ drivers/ras/aest/aest.h | 17 +++++++++ include/linux/acpi_aest.h | 3 ++ 4 files changed, 135 insertions(+) diff --git a/arch/arm64/include/asm/ras.h b/arch/arm64/include/asm/ras.h index da7c441252feb..6c51d27520c00 100644 --- a/arch/arm64/include/asm/ras.h +++ b/arch/arm64/include/asm/ras.h @@ -4,9 +4,50 @@ #include +/* ERRFR */ +#define ERR_FR_CE GENMASK_ULL(54, 53) +#define ERR_FR_RP BIT(15) +#define ERR_FR_CEC GENMASK_ULL(14, 12) + +#define ERR_FR_RP_SINGLE_COUNTER 0 +#define ERR_FR_RP_DOUBLE_COUNTER 1 + +#define ERR_FR_CEC_0B_COUNTER 0 +#define ERR_FR_CEC_8B_COUNTER BIT(1) +#define ERR_FR_CEC_16B_COUNTER BIT(2) + +/* ERRMISC0 */ + +/* ERRFR.CEC == 0b010, ERRFR.RP == 0 */ +#define ERR_MISC0_8B_OF BIT(39) +#define ERR_MISC0_8B_CEC GENMASK_ULL(38, 32) + +/* ERRFR.CEC == 0b100, ERRFR.RP == 0 */ +#define ERR_MISC0_16B_OF BIT(47) +#define ERR_MISC0_16B_CEC GENMASK_ULL(46, 32) + +#define ERR_MISC0_CEC_SHIFT 31 + +#define ERR_8B_CEC_MAX (ERR_MISC0_8B_CEC >> ERR_MISC0_CEC_SHIFT) +#define ERR_16B_CEC_MAX (ERR_MISC0_16B_CEC >> ERR_MISC0_CEC_SHIFT) + +/* ERRFR.CEC == 0b100, ERRFR.RP == 1 */ +#define ERR_MISC0_16B_OFO BIT(63) +#define ERR_MISC0_16B_CECO GENMASK_ULL(62, 48) +#define ERR_MISC0_16B_OFR BIT(47) +#define ERR_MISC0_16B_CECR GENMASK_ULL(46, 32) + /* ERRDEVARCH */ #define ERRDEVARCH_REV GENMASK(19, 16) +enum ras_ce_threshold { + RAS_CE_THRESHOLD_0B, + RAS_CE_THRESHOLD_8B, + RAS_CE_THRESHOLD_16B, + RAS_CE_THRESHOLD_32B, + UNKNOWN, +}; + struct ras_ext_regs { u64 err_fr; u64 err_ctlr; diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 1218ae51079cf..5cfe91a6d72a9 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -16,6 +16,79 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); #undef pr_fmt #define pr_fmt(fmt) "AEST: " fmt +static enum ras_ce_threshold aest_get_ce_threshold(struct aest_record *record) +{ + u64 err_fr, err_fr_cec, err_fr_rp = -1; + + err_fr = record_read(record, ERXFR); + err_fr_cec = FIELD_GET(ERR_FR_CEC, err_fr); + err_fr_rp = FIELD_GET(ERR_FR_RP, err_fr); + + if (err_fr_cec == ERR_FR_CEC_0B_COUNTER) + return RAS_CE_THRESHOLD_0B; + else if (err_fr_rp == ERR_FR_RP_DOUBLE_COUNTER) + return RAS_CE_THRESHOLD_32B; + else if (err_fr_cec == ERR_FR_CEC_8B_COUNTER) + return RAS_CE_THRESHOLD_8B; + else if (err_fr_cec == ERR_FR_CEC_16B_COUNTER) + return RAS_CE_THRESHOLD_16B; + else + return UNKNOWN; +} + +static const struct ce_threshold_info ce_info[] = { + [RAS_CE_THRESHOLD_0B] = { 0 }, + [RAS_CE_THRESHOLD_8B] = { + .max_count = ERR_8B_CEC_MAX, + .mask = ERR_MISC0_8B_CEC, + .shift = ERR_MISC0_CEC_SHIFT, + }, + [RAS_CE_THRESHOLD_16B] = { + .max_count = ERR_16B_CEC_MAX, + .mask = ERR_MISC0_16B_CEC, + .shift = ERR_MISC0_CEC_SHIFT, + }, +}; + +static void aest_set_ce_threshold(struct aest_record *record) +{ + u64 err_misc0; + struct ce_threshold *ce = &record->ce; + const struct ce_threshold_info *info; + + record->threshold_type = aest_get_ce_threshold(record); + + switch (record->threshold_type) { + case RAS_CE_THRESHOLD_0B: + aest_record_dbg(record, "do not support CE threshold!\n"); + return; + case RAS_CE_THRESHOLD_8B: + aest_record_dbg(record, "support 8 bit CE threshold!\n"); + break; + case RAS_CE_THRESHOLD_16B: + aest_record_dbg(record, "support 16 bit CE threshold!\n"); + break; + case RAS_CE_THRESHOLD_32B: + aest_record_dbg(record, "not support 32 bit CE threshold!\n"); + break; + default: + aest_record_dbg(record, "Unknown misc0 ce threshold!\n"); + } + + err_misc0 = record_read(record, ERXMISC0); + info = &ce_info[record->threshold_type]; + ce->info = info; + + // Default CE threshold is 1. + ce->count = info->max_count; + ce->threshold = DEFAULT_CE_THRESHOLD; + ce->reg_val = err_misc0 | info->mask; + + record_write(record, ERXMISC0, ce->reg_val); + aest_record_dbg(record, "CE threshold is %llx, controlled by Kernel", + ce->threshold); +} + static int get_aest_node_ver(struct aest_node *node) { u64 reg; @@ -54,6 +127,7 @@ static int aest_init_record(struct aest_record *record, int i, record->addressing_mode = test_bit(i, node->info->addressing_mode); record->index = i; record->node = node; + aest_set_ce_threshold(record); aest_record_dbg(record, "base: %p, index: %d, address mode: %x\n", record->regs_base, record->index, diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 505ecd9635bcb..85eeed79bcbee 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -9,6 +9,7 @@ #include #define MAX_GSI_PER_NODE 2 +#define DEFAULT_CE_THRESHOLD 1 #define record_read(record, offset) \ record->access->read(record->regs_base, offset) @@ -71,6 +72,19 @@ struct aest_access { void (*write)(void *base, u32 offset, u64 val); }; +struct ce_threshold_info { + const u64 max_count; + const u64 mask; + const u64 shift; +}; + +struct ce_threshold { + const struct ce_threshold_info *info; + u64 count; + u64 threshold; + u64 reg_val; +}; + struct aest_record { char *name; int index; @@ -88,6 +102,9 @@ struct aest_record { int addressing_mode; struct aest_node *node; const struct aest_access *access; + + struct ce_threshold ce; + enum ras_ce_threshold threshold_type; }; struct aest_group { diff --git a/include/linux/acpi_aest.h b/include/linux/acpi_aest.h index 77187ce43d44b..a7898c643896e 100644 --- a/include/linux/acpi_aest.h +++ b/include/linux/acpi_aest.h @@ -13,6 +13,9 @@ /* AEST interrupt */ #define AEST_INTERRUPT_MODE BIT(0) +#define AEST_INTERRUPT_FHI_UE_SUPPORT BIT(0) +#define AEST_INTERRUPT_FHI_UE_NO_SUPPORT BIT(1) + #define AEST_MAX_INTERRUPT_PER_NODE 2 /* AEST interface */ From 164833f872c6cf4f7d731fcb2f3e6c9b9c18c256 Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:48 +0800 Subject: [PATCH 1083/1330] FROMLIST: ras: AEST: Enable and register IRQs The interrupt numbers for certain error records may be explicitly programmed into their configuration register. And for PPIs, each core will maintains its own copy of the aest_device structure. Given that handling RAS errors entails complex processes such as EDAC and memory_failure, all handling is deferred to and handled within a bottom-half context. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-9-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 73c5b35a2d45dceccfe6adcebe06076288f33296) --- arch/arm64/include/asm/ras.h | 36 +++ drivers/ras/aest/aest-core.c | 531 ++++++++++++++++++++++++++++++++++- drivers/ras/aest/aest.h | 56 ++++ include/linux/acpi_aest.h | 7 + include/linux/ras.h | 8 + 5 files changed, 637 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/ras.h b/arch/arm64/include/asm/ras.h index 6c51d27520c00..02cf15278d9ff 100644 --- a/arch/arm64/include/asm/ras.h +++ b/arch/arm64/include/asm/ras.h @@ -2,6 +2,7 @@ #ifndef __ASM_RAS_H #define __ASM_RAS_H +#include #include /* ERRFR */ @@ -37,6 +38,41 @@ #define ERR_MISC0_16B_OFR BIT(47) #define ERR_MISC0_16B_CECR GENMASK_ULL(46, 32) +/* ERRSTATUS */ +#define ERR_STATUS_AV BIT(31) +#define ERR_STATUS_V BIT(30) +#define ERR_STATUS_UE BIT(29) +#define ERR_STATUS_ER BIT(28) +#define ERR_STATUS_OF BIT(27) +#define ERR_STATUS_MV BIT(26) +#define ERR_STATUS_CE (BIT(25) | BIT(24)) +#define ERR_STATUS_DE BIT(23) +#define ERR_STATUS_PN BIT(22) +#define ERR_STATUS_UET (BIT(21) | BIT(20)) +#define ERR_STATUS_CI BIT(19) +#define ERR_STATUS_IERR GENMASK_ULL(15, 8) +#define ERR_STATUS_SERR GENMASK_ULL(7, 0) + +/* Theses bits are write-one-to-clear */ +#define ERR_STATUS_W1TC \ + (ERR_STATUS_AV | ERR_STATUS_V | ERR_STATUS_UE | ERR_STATUS_ER | \ + ERR_STATUS_OF | ERR_STATUS_MV | ERR_STATUS_CE | ERR_STATUS_DE | \ + ERR_STATUS_PN | ERR_STATUS_UET | ERR_STATUS_CI) + +#define ERR_STATUS_UET_UC 0 +#define ERR_STATUS_UET_UEU 1 +#define ERR_STATUS_UET_UEO 2 +#define ERR_STATUS_UET_UER 3 + +/* ERRADDR */ +#define ERR_ADDR_AI BIT(61) +#define ERR_ADDR_PADDR GENMASK_ULL(55, 0) + +/* ERRCTLR */ +#define ERR_CTLR_CFI BIT(8) +#define ERR_CTLR_FI BIT(3) +#define ERR_CTLR_UI BIT(2) + /* ERRDEVARCH */ #define ERRDEVARCH_REV GENMASK(19, 16) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 5cfe91a6d72a9..5ec0ba38f51b4 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -5,8 +5,11 @@ * Copyright (c) 2025, Alibaba Group. */ +#include +#include #include #include +#include #include #include "aest.h" @@ -16,6 +19,439 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); #undef pr_fmt #define pr_fmt(fmt) "AEST: " fmt +/* + * This memory pool is only to be used to save AEST node in AEST irq context. + * There can be 500 AEST node at most. + */ +#define AEST_NODE_ALLOCED_MAX 500 + +#define AEST_LOG_PREFIX_BUFFER 64 + +BLOCKING_NOTIFIER_HEAD(aest_decoder_chain); + +static void aest_print(struct aest_event *event) +{ + static atomic_t seqno = { 0 }; + unsigned int curr_seqno; + char pfx_seq[AEST_LOG_PREFIX_BUFFER]; + int index; + struct ras_ext_regs *regs; + + curr_seqno = atomic_inc_return(&seqno); + snprintf(pfx_seq, sizeof(pfx_seq), "{%u}" HW_ERR, curr_seqno); + pr_info("%sHardware error from AEST %s\n", pfx_seq, event->node_name); + + switch (event->type) { + case ACPI_AEST_PROCESSOR_ERROR_NODE: + pr_err("%s Error from CPU%d\n", pfx_seq, event->id0); + break; + case ACPI_AEST_MEMORY_ERROR_NODE: + pr_err("%s Error from memory at SRAT proximity domain %#x\n", + pfx_seq, event->id0); + break; + case ACPI_AEST_SMMU_ERROR_NODE: + pr_err("%s Error from SMMU IORT node %#x subcomponent %#x\n", + pfx_seq, event->id0, event->id1); + break; + case ACPI_AEST_VENDOR_ERROR_NODE: + pr_err("%s Error from vendor hid %8.8s uid %#x\n", pfx_seq, + event->hid, event->id1); + break; + case ACPI_AEST_GIC_ERROR_NODE: + pr_err("%s Error from GIC type %#x instance %#x\n", pfx_seq, + event->id0, event->id1); + break; + default: + pr_err("%s Unknown AEST node type\n", pfx_seq); + return; + } + + index = event->index; + regs = &event->regs; + + pr_err("%s ERR%dFR: 0x%llx\n", pfx_seq, index, regs->err_fr); + pr_err("%s ERR%dCTRL: 0x%llx\n", pfx_seq, index, regs->err_ctlr); + pr_err("%s ERR%dSTATUS: 0x%llx\n", pfx_seq, index, regs->err_status); + if (regs->err_status & ERR_STATUS_AV) + pr_err("%s ERR%dADDR: 0x%llx\n", pfx_seq, index, + regs->err_addr); + + if (regs->err_status & ERR_STATUS_MV) { + pr_err("%s ERR%dMISC0: 0x%llx\n", pfx_seq, index, + regs->err_misc[0]); + pr_err("%s ERR%dMISC1: 0x%llx\n", pfx_seq, index, + regs->err_misc[1]); + pr_err("%s ERR%dMISC2: 0x%llx\n", pfx_seq, index, + regs->err_misc[2]); + pr_err("%s ERR%dMISC3: 0x%llx\n", pfx_seq, index, + regs->err_misc[3]); + } +} + +static void aest_handle_memory_failure(u64 addr) +{ + unsigned long pfn; + + pfn = PHYS_PFN(addr); + + if (!pfn_valid(pfn)) { + pr_warn(HW_ERR "Invalid physical address: %#llx\n", addr); + return; + } + +#ifdef CONFIG_MEMORY_FAILURE + memory_failure(pfn, 0); +#endif +} + +static void init_aest_event(struct aest_event *event, + struct aest_record *record, + struct ras_ext_regs *regs) +{ + struct aest_node *node = record->node; + struct acpi_aest_node *info = node->info; + + event->type = node->type; + event->node_name = node->name; + switch (node->type) { + case ACPI_AEST_PROCESSOR_ERROR_NODE: + if (info->processor->flags & + (ACPI_AEST_PROC_FLAG_SHARED | ACPI_AEST_PROC_FLAG_GLOBAL)) + event->id0 = smp_processor_id(); + else + event->id0 = get_cpu_for_acpi_id( + info->processor->processor_id); + + event->id1 = info->processor->resource_type; + break; + case ACPI_AEST_MEMORY_ERROR_NODE: + event->id0 = info->memory->srat_proximity_domain; + break; + case ACPI_AEST_SMMU_ERROR_NODE: + event->id0 = info->smmu->iort_node_reference; + event->id1 = info->smmu->subcomponent_reference; + break; + case ACPI_AEST_VENDOR_ERROR_NODE: + event->id0 = 0; + event->id1 = info->vendor->acpi_uid; + event->hid = info->vendor->acpi_hid; + break; + case ACPI_AEST_GIC_ERROR_NODE: + event->id0 = info->gic->interface_type; + event->id1 = info->gic->instance_id; + break; + default: + event->id0 = 0; + event->id1 = 0; + } + + memcpy(&event->regs, regs, sizeof(*regs)); + event->index = record->index; + event->addressing_mode = record->addressing_mode; +} + +static int aest_node_gen_pool_add(struct aest_device *adev, + struct aest_record *record, + struct ras_ext_regs *regs) +{ + struct aest_event *event; + + if (!adev->pool) + return -EINVAL; + + event = (void *)gen_pool_alloc(adev->pool, sizeof(*event)); + if (!event) + return -ENOMEM; + + init_aest_event(event, record, regs); + llist_add(&event->llnode, &adev->event_list); + + return 0; +} + +static void aest_log(struct aest_record *record, struct ras_ext_regs *regs) +{ + struct aest_device *adev = record->node->adev; + + if (!aest_node_gen_pool_add(adev, record, regs)) + schedule_work(&adev->aest_work); +} + +void aest_register_decode_chain(struct notifier_block *nb) +{ + blocking_notifier_chain_register(&aest_decoder_chain, nb); +} +EXPORT_SYMBOL_GPL(aest_register_decode_chain); + +void aest_unregister_decode_chain(struct notifier_block *nb) +{ + blocking_notifier_chain_unregister(&aest_decoder_chain, nb); +} +EXPORT_SYMBOL_GPL(aest_unregister_decode_chain); + +static void aest_node_pool_process(struct work_struct *work) +{ + struct llist_node *head; + struct aest_event *event; + struct aest_device *adev = + container_of(work, struct aest_device, aest_work); + u64 status, addr; + + head = llist_del_all(&adev->event_list); + if (!head) + return; + + head = llist_reverse_order(head); + llist_for_each_entry(event, head, llnode) { + aest_print(event); + + status = event->regs.err_status; + if (!(event->regs.err_addr & ERR_ADDR_AI) && + (status & (ERR_STATUS_UE | ERR_STATUS_DE))) { + if (event->addressing_mode == AEST_ADDREESS_SPA) + addr = event->regs.err_addr & PHYS_MASK; + aest_handle_memory_failure(addr); + } + + blocking_notifier_call_chain(&aest_decoder_chain, 0, event); + gen_pool_free(adev->pool, (unsigned long)event, sizeof(*event)); + } +} + +static int aest_node_pool_init(struct aest_device *adev) +{ + unsigned long addr, size; + + size = ilog2(sizeof(struct aest_event)); + adev->pool = + devm_gen_pool_create(adev->dev, size, -1, dev_name(adev->dev)); + if (!adev->pool) + return -ENOMEM; + + size = PAGE_ALIGN(size * AEST_NODE_ALLOCED_MAX); + addr = (unsigned long)devm_kzalloc(adev->dev, size, GFP_KERNEL); + if (!addr) + return -ENOMEM; + + return gen_pool_add(adev->pool, addr, size, -1); +} + +static void aest_panic(struct aest_record *record, struct ras_ext_regs *regs, + char *msg) +{ + struct aest_event event = { 0 }; + + init_aest_event(&event, record, regs); + + aest_print(&event); + + panic(msg); +} + +static void aest_proc_record(struct aest_record *record, void *data) +{ + struct ras_ext_regs regs = { 0 }; + int *count = data; + u64 ue; + + regs.err_status = record_read(record, ERXSTATUS); + if (!(regs.err_status & ERR_STATUS_V)) + return; + + (*count)++; + + if (regs.err_status & ERR_STATUS_AV) + regs.err_addr = record_read(record, ERXADDR); + + regs.err_fr = record_read(record, ERXFR); + regs.err_ctlr = record_read(record, ERXCTLR); + + if (regs.err_status & ERR_STATUS_MV) { + regs.err_misc[0] = record_read(record, ERXMISC0); + regs.err_misc[1] = record_read(record, ERXMISC1); + if (record->node->version >= ID_AA64PFR0_EL1_RAS_V1P1) { + regs.err_misc[2] = record_read(record, ERXMISC2); + regs.err_misc[3] = record_read(record, ERXMISC3); + } + + if (record->node->info->interface_hdr->flags & + AEST_XFACE_FLAG_CLEAR_MISC) { + record_write(record, ERXMISC0, 0); + record_write(record, ERXMISC1, 0); + if (record->node->version >= ID_AA64PFR0_EL1_RAS_V1P1) { + record_write(record, ERXMISC2, 0); + record_write(record, ERXMISC3, 0); + } + /* ce count is 0 if record do not support ce */ + } else if (record->ce.count > 0) + record_write(record, ERXMISC0, record->ce.reg_val); + } + + /* panic if unrecoverable and uncontainable error encountered */ + ue = FIELD_GET(ERR_STATUS_UET, regs.err_status); + if ((regs.err_status & ERR_STATUS_UE) && + (ue == ERR_STATUS_UET_UC || ue == ERR_STATUS_UET_UEU)) + aest_panic(record, ®s, + "AEST: unrecoverable error encountered"); + + aest_log(record, ®s); + + /* Write-one-to-clear the bits we've seen */ + regs.err_status &= ERR_STATUS_W1TC; + + /* Multi bit filed need to write all-ones to clear. */ + if (regs.err_status & ERR_STATUS_CE) + regs.err_status |= ERR_STATUS_CE; + + /* Multi bit filed need to write all-ones to clear. */ + if (regs.err_status & ERR_STATUS_UET) + regs.err_status |= ERR_STATUS_UET; + + record_write(record, ERXSTATUS, regs.err_status); +} + +static void aest_node_foreach_record(void (*func)(struct aest_record *, void *), + struct aest_node *node, void *data, + unsigned long *bitmap) +{ + int i; + + for_each_clear_bit(i, bitmap, node->record_count) { + aest_select_record(node, i); + + func(&node->records[i], data); + + aest_sync(node); + } +} + +static int aest_proc(struct aest_node *node) +{ + int count = 0, i, j, size = node->record_count; + u64 err_group = 0; + + aest_node_dbg(node, "Poll bitmap %*pb\n", size, + node->record_implemented); + aest_node_foreach_record(aest_proc_record, node, &count, + node->record_implemented); + + if (!node->errgsr) + return count; + + aest_node_dbg(node, "Report bitmap %*pb\n", size, + node->status_reporting); + for (i = 0; i < BITS_TO_U64(size); i++) { + err_group = readq_relaxed((void *)node->errgsr + i * 8); + aest_node_dbg(node, "errgsr[%d]: 0x%llx\n", i, err_group); + + for_each_set_bit(j, (unsigned long *)&err_group, + BITS_PER_LONG) { + /* + * Error group base is only valid in Memory Map node, + * so driver do not need to write select register and + * sync. + */ + if (test_bit(i * BITS_PER_LONG + j, + node->status_reporting)) + continue; + aest_proc_record(&node->records[j], &count); + } + } + + return count; +} + +static irqreturn_t aest_irq_func(int irq, void *input) +{ + struct aest_device *adev = input; + int i; + + for (i = 0; i < adev->node_cnt; i++) + aest_proc(&adev->nodes[i]); + + return IRQ_HANDLED; +} + +static int aest_register_irq(struct aest_device *adev) +{ + int i, irq, ret; + char *irq_desc; + + irq_desc = devm_kasprintf(adev->dev, GFP_KERNEL, "%s.%s.", + dev_driver_string(adev->dev), + dev_name(adev->dev)); + if (!irq_desc) + return -ENOMEM; + + for (i = 0; i < MAX_GSI_PER_NODE; i++) { + irq = adev->irq[i]; + + if (!irq) + continue; + + if (irq_is_percpu_devid(irq)) { + ret = request_percpu_irq(irq, aest_irq_func, irq_desc, + adev->adev_oncore); + if (ret) + goto free; + } else { + ret = devm_request_irq(adev->dev, irq, aest_irq_func, 0, + irq_desc, adev); + if (ret) + return ret; + } + } + return 0; + +free: + for (; i >= 0; i--) { + irq = adev->irq[i]; + + if (irq_is_percpu_devid(irq)) + free_percpu_irq(irq, adev->adev_oncore); + } + + return ret; +} + +static void aest_enable_irq(struct aest_record *record) +{ + u64 err_ctlr; + struct aest_device *adev = record->node->adev; + + err_ctlr = record_read(record, ERXCTLR); + + if (adev->irq[ACPI_AEST_NODE_FAULT_HANDLING]) + err_ctlr |= (ERR_CTLR_FI | ERR_CTLR_CFI); + if (adev->irq[ACPI_AEST_NODE_ERROR_RECOVERY]) + err_ctlr |= ERR_CTLR_UI; + + record_write(record, ERXCTLR, err_ctlr); +} + +static void aest_config_irq(struct aest_node *node) +{ + int i; + struct acpi_aest_node_interrupt_v2 *interrupt; + + if (!node->irq_config) + return; + + for (i = 0; i < node->info->interrupt_count; i++) { + interrupt = &node->info->interrupt[i]; + + if (interrupt->type == ACPI_AEST_NODE_FAULT_HANDLING) + writeq_relaxed(interrupt->gsiv, node->irq_config); + + if (interrupt->type == ACPI_AEST_NODE_ERROR_RECOVERY) + writeq_relaxed(interrupt->gsiv, node->irq_config + 8); + + aest_node_dbg(node, "config irq type %d gsiv %d at %llx", + interrupt->type, interrupt->gsiv, + (u64)node->irq_config); + } +} + static enum ras_ce_threshold aest_get_ce_threshold(struct aest_record *record) { u64 err_fr, err_fr_cec, err_fr_rp = -1; @@ -128,6 +564,7 @@ static int aest_init_record(struct aest_record *record, int i, record->index = i; record->node = node; aest_set_ce_threshold(record); + aest_enable_irq(record); aest_record_dbg(record, "base: %p, index: %d, address mode: %x\n", record->regs_base, record->index, @@ -232,6 +669,21 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node, } } + address = node->info->common->interrupt_config_register_base; + if ((flags & AEST_XFACE_FLAG_INT_CONFIG) && address) { + if (address - anode->interface_hdr->address < node->group->size) + node->irq_config = + node->base + + (address - anode->interface_hdr->address); + else { + node->irq_config = + devm_ioremap(adev->dev, address, PAGE_SIZE); + if (!node->irq_config) + return -ENOMEM; + } + } + aest_config_irq(node); + ret = aest_node_set_errgsr(adev, node); if (ret) return ret; @@ -276,6 +728,66 @@ static int aest_init_nodes(struct aest_device *adev, struct aest_hnode *ahnode) return 0; } +static int __setup_ppi(struct aest_device *adev) +{ + int cpu, i; + struct aest_device *oncore_adev; + struct aest_node *oncore_node; + size_t size; + + adev->adev_oncore = &percpu_adev; + for_each_possible_cpu(cpu) { + oncore_adev = per_cpu_ptr(&percpu_adev, cpu); + memcpy(oncore_adev, adev, sizeof(struct aest_device)); + + oncore_adev->nodes = + devm_kcalloc(adev->dev, oncore_adev->node_cnt, + sizeof(struct aest_node), GFP_KERNEL); + if (!oncore_adev->nodes) + return -ENOMEM; + + size = adev->node_cnt * sizeof(struct aest_node); + memcpy(oncore_adev->nodes, adev->nodes, size); + for (i = 0; i < oncore_adev->node_cnt; i++) { + oncore_node = &oncore_adev->nodes[i]; + oncore_node->records = devm_kcalloc( + adev->dev, oncore_node->record_count, + sizeof(struct aest_record), GFP_KERNEL); + if (!oncore_node->records) + return -ENOMEM; + + size = oncore_node->record_count * + sizeof(struct aest_record); + memcpy(oncore_node->records, adev->nodes[i].records, + size); + } + + aest_dev_dbg(adev, "Init device on CPU%d.\n", cpu); + } + + return 0; +} + +static int aest_setup_irq(struct platform_device *pdev, + struct aest_device *adev) +{ + int fhi_irq, eri_irq; + + fhi_irq = platform_get_irq_byname_optional(pdev, AEST_FHI_NAME); + if (fhi_irq > 0) + adev->irq[0] = fhi_irq; + + eri_irq = platform_get_irq_byname_optional(pdev, AEST_ERI_NAME); + if (eri_irq > 0) + adev->irq[1] = eri_irq; + + /* Allocate and initialise the percpu device pointer for PPI */ + if (irq_is_percpu(fhi_irq) || irq_is_percpu(eri_irq)) + return __setup_ppi(adev); + + return 0; +} + static int aest_device_probe(struct platform_device *pdev) { int ret; @@ -289,14 +801,31 @@ static int aest_device_probe(struct platform_device *pdev) adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); if (!adev) return -ENOMEM; - adev->dev = &pdev->dev; adev->id = pdev->id; aest_set_name(adev, ahnode); + + INIT_WORK(&adev->aest_work, aest_node_pool_process); + ret = aest_node_pool_init(adev); + if (ret) { + aest_dev_err(adev, "Failed init aest node pool.\n"); + return ret; + } + init_llist_head(&adev->event_list); + ret = aest_init_nodes(adev, ahnode); if (ret) return ret; + ret = aest_setup_irq(pdev, adev); + if (ret) + return ret; + + ret = aest_register_irq(adev); + if (ret) { + aest_dev_err(adev, "register irq failed\n"); + return ret; + } platform_set_drvdata(pdev, adev); aest_dev_dbg(adev, "Node cnt: %x, id: %x\n", adev->node_cnt, adev->id); diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 85eeed79bcbee..a5e43b2a2e906 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -67,6 +67,34 @@ #define GIC_ERRDEVARCH 0xFFBC +struct aest_event { + struct llist_node llnode; + char *node_name; + u32 type; + /* + * Different nodes have different meanings: + * - Processor node : processor number. + * - Memory node : SRAT proximity domain. + * - SMMU node : IORT proximity domain. + * - GIC node : interface type. + */ + u32 id0; + /* + * Different nodes have different meanings: + * - Processor node : processor resource type. + * - Memory node : Non. + * - SMMU node : subcomponent reference. + * - Vendor node : Unique ID. + * - GIC node : instance identifier. + */ + u32 id1; + /* Vendor node : hardware ID. */ + char *hid; + u32 index; + int addressing_mode; + struct ras_ext_regs regs; +}; + struct aest_access { u64 (*read)(void *base, u32 offset); void (*write)(void *base, u32 offset, u64 val); @@ -141,6 +169,7 @@ struct aest_node { void *errgsr; void *base; void *inj; + void *irq_config; /* * This bitmap indicates which of the error records within this error @@ -172,6 +201,7 @@ struct aest_node { int record_count; struct aest_record *records; + struct aest_node __percpu *oncore_node; }; struct aest_device { @@ -180,6 +210,12 @@ struct aest_device { int node_cnt; struct aest_node *nodes; u32 id; + int irq[MAX_GSI_PER_NODE]; + + struct work_struct aest_work; + struct gen_pool *pool; + struct llist_head event_list; + struct aest_device __percpu *adev_oncore; }; static const char *const aest_node_name[] = { @@ -283,3 +319,23 @@ static const struct aest_access aest_access[] = { }, { } }; + +/* + * Each PE may has multi error record, you must selects an error + * record to be accessed through the Error Record System + * registers. + */ +static inline void aest_select_record(struct aest_node *node, int index) +{ + if (node->type == ACPI_AEST_PROCESSOR_ERROR_NODE) { + write_sysreg_s(index, SYS_ERRSELR_EL1); + isb(); + } +} + +/* Ensure all writes has taken effect. */ +static inline void aest_sync(struct aest_node *node) +{ + if (node->type == ACPI_AEST_PROCESSOR_ERROR_NODE) + isb(); +} diff --git a/include/linux/acpi_aest.h b/include/linux/acpi_aest.h index a7898c643896e..3a899f57f92fb 100644 --- a/include/linux/acpi_aest.h +++ b/include/linux/acpi_aest.h @@ -10,6 +10,13 @@ #define AEST_FHI_NAME "AEST:FHI" #define AEST_ERI_NAME "AEST:ERI" +/* AEST component */ +#define ACPI_AEST_PROC_FLAG_GLOBAL (1<<0) +#define ACPI_AEST_PROC_FLAG_SHARED (1<<1) + +#define AEST_ADDREESS_SPA 0 +#define AEST_ADDREESS_LA 1 + /* AEST interrupt */ #define AEST_INTERRUPT_MODE BIT(0) diff --git a/include/linux/ras.h b/include/linux/ras.h index 468941bfe855f..05096f049dacb 100644 --- a/include/linux/ras.h +++ b/include/linux/ras.h @@ -63,4 +63,12 @@ amd_convert_umc_mca_addr_to_sys_addr(struct atl_err *err) { return -EINVAL; } #define GET_LOGICAL_INDEX(mpidr) -EINVAL #endif /* CONFIG_ARM || CONFIG_ARM64 */ +#if IS_ENABLED(CONFIG_AEST) +void aest_register_decode_chain(struct notifier_block *nb); +void aest_unregister_decode_chain(struct notifier_block *nb); +#else +static inline void aest_register_decode_chain(struct notifier_block *nb) {} +static inline void aest_unregister_decode_chain(struct notifier_block *nb) {} +#endif /* CONFIG_AEST */ + #endif /* __RAS_H__ */ From dea3b05ea4695ff573543f59ed295a59a27f7788 Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:49 +0800 Subject: [PATCH 1084/1330] FROMLIST: ras: AEST: Add cpuhp callback Move the configuration of interrupts and CE thresholds into the CPU hotplug callbacks for the per-CPU AEST node. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-10-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 70005f68542182afc4fd2e863b30b0f6a23cfcf9) --- drivers/ras/aest/aest-core.c | 118 ++++++++++++++++++++++++++++++++++- drivers/ras/aest/aest.h | 5 ++ include/linux/cpuhotplug.h | 1 + 3 files changed, 121 insertions(+), 3 deletions(-) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 5ec0ba38f51b4..686dde6f2e680 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -5,6 +5,7 @@ * Copyright (c) 2025, Alibaba Group. */ +#include #include #include #include @@ -563,8 +564,6 @@ static int aest_init_record(struct aest_record *record, int i, record->addressing_mode = test_bit(i, node->info->addressing_mode); record->index = i; record->node = node; - aest_set_ce_threshold(record); - aest_enable_irq(record); aest_record_dbg(record, "base: %p, index: %d, address mode: %x\n", record->regs_base, record->index, @@ -572,9 +571,113 @@ static int aest_init_record(struct aest_record *record, int i, return 0; } +static void aest_online_record(struct aest_record *record, void *data) +{ + if (record_read(record, ERXFR) & ERR_FR_CE) + aest_set_ce_threshold(record); + + aest_enable_irq(record); +} + +static void aest_online_oncore_node(struct aest_node *node) +{ + int count; + + count = aest_proc(node); + aest_node_dbg(node, "Find %d error on CPU%d before AEST probe\n", count, + smp_processor_id()); + + aest_node_foreach_record(aest_online_record, node, NULL, + node->record_implemented); + + aest_node_foreach_record(aest_online_record, node, NULL, + node->status_reporting); +} + +static void aest_online_oncore_dev(void *data) +{ + int fhi_irq, eri_irq, i; + struct aest_device *adev = this_cpu_ptr(data); + + for (i = 0; i < adev->node_cnt; i++) + aest_online_oncore_node(&adev->nodes[i]); + + fhi_irq = adev->irq[ACPI_AEST_NODE_FAULT_HANDLING]; + if (fhi_irq > 0) + enable_percpu_irq(fhi_irq, IRQ_TYPE_NONE); + eri_irq = adev->irq[ACPI_AEST_NODE_ERROR_RECOVERY]; + if (eri_irq > 0) + enable_percpu_irq(eri_irq, IRQ_TYPE_NONE); +} + +static void aest_offline_oncore_dev(void *data) +{ + int fhi_irq, eri_irq; + struct aest_device *adev = this_cpu_ptr(data); + + fhi_irq = adev->irq[ACPI_AEST_NODE_FAULT_HANDLING]; + if (fhi_irq > 0) + disable_percpu_irq(fhi_irq); + eri_irq = adev->irq[ACPI_AEST_NODE_ERROR_RECOVERY]; + if (eri_irq > 0) + disable_percpu_irq(eri_irq); +} + +static void aest_online_dev(struct aest_device *adev) +{ + int count, i; + struct aest_node *node; + + for (i = 0; i < adev->node_cnt; i++) { + node = &adev->nodes[i]; + + if (!node->name) + continue; + + count = aest_proc(node); + aest_node_dbg(node, "Find %d error before AEST probe\n", count); + + aest_config_irq(node); + + aest_node_foreach_record(aest_online_record, node, NULL, + node->record_implemented); + aest_node_foreach_record(aest_online_record, node, NULL, + node->status_reporting); + } +} + +static int aest_starting_cpu(unsigned int cpu) +{ + pr_debug("CPU%d starting\n", cpu); + aest_online_oncore_dev(&percpu_adev); + + return 0; +} + +static int aest_dying_cpu(unsigned int cpu) +{ + pr_debug("CPU%d dying\n", cpu); + aest_offline_oncore_dev(&percpu_adev); + + return 0; +} + static void aest_device_remove(struct platform_device *pdev) { + struct aest_device *adev = platform_get_drvdata(pdev); + int i; + platform_set_drvdata(pdev, NULL); + + if (adev->type != ACPI_AEST_PROCESSOR_ERROR_NODE) + return; + + on_each_cpu(aest_offline_oncore_dev, adev->adev_oncore, 1); + + for (i = 0; i < MAX_GSI_PER_NODE; i++) { + if (adev->irq[i]) + free_percpu_irq(adev->irq[i], adev->adev_oncore); + } } static char *alloc_aest_node_name(struct aest_node *node) @@ -682,7 +785,6 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node, return -ENOMEM; } } - aest_config_irq(node); ret = aest_node_set_errgsr(adev, node); if (ret) @@ -826,6 +928,16 @@ static int aest_device_probe(struct platform_device *pdev) aest_dev_err(adev, "register irq failed\n"); return ret; } + + if (aest_dev_is_oncore(adev)) + ret = cpuhp_setup_state(CPUHP_AP_ARM_AEST_STARTING, + "drivers/acpi/arm64/aest:starting", + aest_starting_cpu, aest_dying_cpu); + else + aest_online_dev(adev); + if (ret) + return ret; + platform_set_drvdata(pdev, adev); aest_dev_dbg(adev, "Node cnt: %x, id: %x\n", adev->node_cnt, adev->id); diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index a5e43b2a2e906..f85e81ff35a6e 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -339,3 +339,8 @@ static inline void aest_sync(struct aest_node *node) if (node->type == ACPI_AEST_PROCESSOR_ERROR_NODE) isb(); } + +static inline bool aest_dev_is_oncore(struct aest_device *adev) +{ + return adev->type == ACPI_AEST_PROCESSOR_ERROR_NODE; +} diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 22ba327ec2278..e7b553241b305 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -178,6 +178,7 @@ enum cpuhp_state { CPUHP_AP_HYPERV_TIMER_STARTING, /* Must be the last timer callback */ CPUHP_AP_DUMMY_TIMER_STARTING, + CPUHP_AP_ARM_AEST_STARTING, CPUHP_AP_ARM_XEN_STARTING, CPUHP_AP_ARM_XEN_RUNSTATE_STARTING, CPUHP_AP_ARM_CORESIGHT_STARTING, From 2423c925026eaabb586216490c839c094e329a0c Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:50 +0800 Subject: [PATCH 1085/1330] FROMLIST: ras: AEST: Introduce AEST driver sysfs interface Exposes certain AEST driver information to userspace. Only ROOT can access these interface because it includes hardware-sensitive information: ls /sys/kernel/debug/aest/ memory smmu ... ls /sys/kernel/debug/aest/memory/ record0 record1 ... All details at: Documentation/ABI/testing/debugfs-aest Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-11-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 166ac6de5503aa748a50da36151cdf2a6b9c84f5) --- Documentation/ABI/testing/debugfs-aest | 32 +++++++ MAINTAINERS | 1 + drivers/ras/aest/Makefile | 1 + drivers/ras/aest/aest-core.c | 13 +++ drivers/ras/aest/aest-sysfs.c | 118 +++++++++++++++++++++++++ drivers/ras/aest/aest.h | 8 ++ 6 files changed, 173 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-aest create mode 100644 drivers/ras/aest/aest-sysfs.c diff --git a/Documentation/ABI/testing/debugfs-aest b/Documentation/ABI/testing/debugfs-aest new file mode 100644 index 0000000000000..8bacc6bb20b6d --- /dev/null +++ b/Documentation/ABI/testing/debugfs-aest @@ -0,0 +1,32 @@ +What: /sys/kernel/debug/aest/./ +Date: Dec 2025 +KernelVersion: 6.19 +Contact: Ruidong Tian +Description: + Directory represented a AEST device, means device type, + like: + + - processor + - memory + - smmu + - ... + + is the unique ID for this device. + +What: /sys/kernel/debug/aest/.//* +Date: Dec 2025 +KernelVersion: 6.19 +Contact: Ruidong Tian +Description: + Attibute for aest node which belong this device, the format + of node name is: - + + See more at: + https://developer.arm.com/documentation/den0085/latest/ + +What: /sys/kernel/debug/aest/.//record/err_* +Date: Dec 2025 +KernelVersion: 6.19 +Contact: Ruidong Tian +Description: + (RO) Read err_* register and return val. diff --git a/MAINTAINERS b/MAINTAINERS index 936d39d07d9dd..d75a832c09d3c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -361,6 +361,7 @@ M: Ruidong Tian L: linux-acpi@vger.kernel.org L: linux-arm-kernel@lists.infradead.org S: Supported +F: Documentation/ABI/testing/debugfs-aest F: arch/arm64/include/asm/ras.h F: drivers/acpi/arm64/aest.c F: drivers/ras/aest/ diff --git a/drivers/ras/aest/Makefile b/drivers/ras/aest/Makefile index a6ba7e36fb432..75495413d2b6e 100644 --- a/drivers/ras/aest/Makefile +++ b/drivers/ras/aest/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_AEST) += aest.o aest-y := aest-core.o +aest-y += aest-sysfs.o diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 686dde6f2e680..3bcc635cf8e4d 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -20,6 +20,9 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); #undef pr_fmt #define pr_fmt(fmt) "AEST: " fmt +#ifdef CONFIG_DEBUG_FS +struct dentry *aest_debugfs; +#endif /* * This memory pool is only to be used to save AEST node in AEST irq context. * There can be 500 AEST node at most. @@ -940,6 +943,8 @@ static int aest_device_probe(struct platform_device *pdev) platform_set_drvdata(pdev, adev); + aest_dev_init_debugfs(adev); + aest_dev_dbg(adev, "Node cnt: %x, id: %x\n", adev->node_cnt, adev->id); return 0; @@ -955,12 +960,20 @@ static struct platform_driver aest_driver = { static int __init aest_init(void) { +#ifdef CONFIG_DEBUG_FS + aest_debugfs = debugfs_create_dir("aest", NULL); +#endif + return platform_driver_register(&aest_driver); } module_init(aest_init); static void __exit aest_exit(void) { +#ifdef CONFIG_DEBUG_FS + debugfs_remove(aest_debugfs); +#endif + platform_driver_unregister(&aest_driver); } module_exit(aest_exit); diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c new file mode 100644 index 0000000000000..f3b5427ff4f0f --- /dev/null +++ b/drivers/ras/aest/aest-sysfs.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Error Source Table Support + * + * Copyright (c) 2025, Alibaba Group. + */ + +#include "aest.h" + +/******************************************************************************* + * + * Attribute for AEST record + * + ******************************************************************************/ + +#define DEFINE_AEST_DEBUGFS_ATTR(name, offset) \ +static int name##_get(void *data, u64 *val) \ +{ \ + struct aest_record *record = data; \ + *val = record_read(record, offset); \ + return 0; \ +} \ +static int name##_set(void *data, u64 val) \ +{ \ + struct aest_record *record = data; \ + record_write(record, offset, val); \ + return 0; \ +} \ +DEFINE_DEBUGFS_ATTRIBUTE(name##_ops, name##_get, name##_set, "%#llx\n") + +DEFINE_AEST_DEBUGFS_ATTR(err_fr, ERXFR); +DEFINE_AEST_DEBUGFS_ATTR(err_ctrl, ERXCTLR); +DEFINE_AEST_DEBUGFS_ATTR(err_status, ERXSTATUS); +DEFINE_AEST_DEBUGFS_ATTR(err_addr, ERXADDR); +DEFINE_AEST_DEBUGFS_ATTR(err_misc0, ERXMISC0); +DEFINE_AEST_DEBUGFS_ATTR(err_misc1, ERXMISC1); +DEFINE_AEST_DEBUGFS_ATTR(err_misc2, ERXMISC2); +DEFINE_AEST_DEBUGFS_ATTR(err_misc3, ERXMISC3); + +static void aest_record_init_debugfs(struct aest_record *record) +{ + debugfs_create_file("err_fr", 0600, record->debugfs, record, + &err_fr_ops); + debugfs_create_file("err_ctrl", 0600, record->debugfs, record, + &err_ctrl_ops); + debugfs_create_file("err_status", 0600, record->debugfs, record, + &err_status_ops); + debugfs_create_file("err_addr", 0600, record->debugfs, record, + &err_addr_ops); + debugfs_create_file("err_misc0", 0600, record->debugfs, record, + &err_misc0_ops); + debugfs_create_file("err_misc1", 0600, record->debugfs, record, + &err_misc1_ops); + debugfs_create_file("err_misc2", 0600, record->debugfs, record, + &err_misc2_ops); + debugfs_create_file("err_misc3", 0600, record->debugfs, record, + &err_misc3_ops); +} + +static void +aest_node_init_debugfs(struct aest_node *node) +{ + int i; + struct aest_record *record; + + for (i = 0; i < node->record_count; i++) { + record = &node->records[i]; + if (!record->name) + continue; + record->debugfs = debugfs_create_dir(record->name, + node->debugfs); + aest_record_init_debugfs(record); + } +} + +static void +aest_oncore_dev_init_debugfs(struct aest_device *adev) +{ + int cpu, i; + struct aest_node *node; + struct aest_device *percpu_dev; + char name[16]; + + for_each_possible_cpu(cpu) { + percpu_dev = this_cpu_ptr(adev->adev_oncore); + + snprintf(name, sizeof(name), "processor%u", cpu); + percpu_dev->debugfs = debugfs_create_dir(name, aest_debugfs); + + for (i = 0; i < adev->node_cnt; i++) { + node = &adev->nodes[i]; + + node->debugfs = debugfs_create_dir(node->name, + percpu_dev->debugfs); + aest_node_init_debugfs(node); + } + } +} + +void aest_dev_init_debugfs(struct aest_device *adev) +{ + int i; + struct aest_node *node; + + adev->debugfs = debugfs_create_dir(dev_name(adev->dev), aest_debugfs); + if (aest_dev_is_oncore(adev)) { + aest_oncore_dev_init_debugfs(adev); + return; + } + + for (i = 0; i < adev->node_cnt; i++) { + node = &adev->nodes[i]; + if (!node->name) + continue; + node->debugfs = debugfs_create_dir(node->name, adev->debugfs); + aest_node_init_debugfs(node); + } +} diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index f85e81ff35a6e..ceb9e32bcee3c 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -7,6 +7,7 @@ #include #include +#include #define MAX_GSI_PER_NODE 2 #define DEFAULT_CE_THRESHOLD 1 @@ -67,6 +68,8 @@ #define GIC_ERRDEVARCH 0xFFBC +extern struct dentry *aest_debugfs; + struct aest_event { struct llist_node llnode; char *node_name; @@ -133,6 +136,7 @@ struct aest_record { struct ce_threshold ce; enum ras_ce_threshold threshold_type; + struct dentry *debugfs; }; struct aest_group { @@ -201,6 +205,7 @@ struct aest_node { int record_count; struct aest_record *records; + struct dentry *debugfs; struct aest_node __percpu *oncore_node; }; @@ -215,6 +220,7 @@ struct aest_device { struct work_struct aest_work; struct gen_pool *pool; struct llist_head event_list; + struct dentry *debugfs; struct aest_device __percpu *adev_oncore; }; @@ -344,3 +350,5 @@ static inline bool aest_dev_is_oncore(struct aest_device *adev) { return adev->type == ACPI_AEST_PROCESSOR_ERROR_NODE; } + +void aest_dev_init_debugfs(struct aest_device *adev); From 89d529188ec11d786f9ed9b38743b7f732af1e1d Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:51 +0800 Subject: [PATCH 1086/1330] FROMLIST: ras: AEST: Add error count tracking and debugfs interface This commit introduces error counting functionality for AEST records. Previously, error statistics were not directly available for individual error records or AEST nodes. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-12-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 4b546221d48c26f969eb3b0a800188a9437144a0) --- Documentation/ABI/testing/debugfs-aest | 14 ++++++ drivers/ras/aest/aest-core.c | 21 +++++++++ drivers/ras/aest/aest-sysfs.c | 64 ++++++++++++++++++++++++++ drivers/ras/aest/aest.h | 10 ++++ 4 files changed, 109 insertions(+) diff --git a/Documentation/ABI/testing/debugfs-aest b/Documentation/ABI/testing/debugfs-aest index 8bacc6bb20b6d..295df9e9b4558 100644 --- a/Documentation/ABI/testing/debugfs-aest +++ b/Documentation/ABI/testing/debugfs-aest @@ -24,9 +24,23 @@ Description: See more at: https://developer.arm.com/documentation/den0085/latest/ +What: /sys/kernel/debug/aest/.//err_count +Date: Dec 2025 +KernelVersion 6.19 +Contact: Ruidong Tian +Description: + (RO) Outputs error statistics for all error records of this node. + What: /sys/kernel/debug/aest/.//record/err_* Date: Dec 2025 KernelVersion: 6.19 Contact: Ruidong Tian Description: (RO) Read err_* register and return val. + +What: /sys/kernel/debug/aest/.//record/err_count +Date: Dec 2025 +KernelVersion 6.19 +Contact: Ruidong Tian +Description: + (RO) Outputs error statistics for all this records. diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 3bcc635cf8e4d..75cca98024ad7 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -170,6 +170,27 @@ static int aest_node_gen_pool_add(struct aest_device *adev, init_aest_event(event, record, regs); llist_add(&event->llnode, &adev->event_list); + if (regs->err_status & ERR_STATUS_CE) + record->count.ce++; + if (regs->err_status & ERR_STATUS_DE) + record->count.de++; + if (regs->err_status & ERR_STATUS_UE) { + switch (regs->err_status & ERR_STATUS_UET) { + case ERR_STATUS_UET_UC: + record->count.uc++; + break; + case ERR_STATUS_UET_UEU: + record->count.ueu++; + break; + case ERR_STATUS_UET_UER: + record->count.uer++; + break; + case ERR_STATUS_UET_UEO: + record->count.ueo++; + break; + } + } + return 0; } diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c index f3b5427ff4f0f..b54e879506aa9 100644 --- a/drivers/ras/aest/aest-sysfs.c +++ b/drivers/ras/aest/aest-sysfs.c @@ -7,6 +7,46 @@ #include "aest.h" +static void +aest_error_count(struct aest_record *record, void *data) +{ + struct record_count *count = data; + + count->ce += record->count.ce; + count->de += record->count.de; + count->uc += record->count.uc; + count->ueu += record->count.ueu; + count->uer += record->count.uer; + count->ueo += record->count.ueo; +} + +/******************************************************************************* + * + * Debugfs for AEST node + * + ******************************************************************************/ + +static int aest_node_err_count_show(struct seq_file *m, void *data) +{ + struct aest_node *node = m->private; + struct record_count count = { 0 }; + int i; + + for (i = 0; i < node->record_count; i++) + aest_error_count(&node->records[i], &count); + + seq_printf(m, "CE: %llu\n" + "DE: %llu\n" + "UC: %llu\n" + "UEU: %llu\n" + "UEO: %llu\n" + "UER: %llu\n", + count.ce, count.de, count.uc, count.ueu, + count.uer, count.ueo); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(aest_node_err_count); + /******************************************************************************* * * Attribute for AEST record @@ -37,6 +77,25 @@ DEFINE_AEST_DEBUGFS_ATTR(err_misc1, ERXMISC1); DEFINE_AEST_DEBUGFS_ATTR(err_misc2, ERXMISC2); DEFINE_AEST_DEBUGFS_ATTR(err_misc3, ERXMISC3); +static int aest_record_err_count_show(struct seq_file *m, void *data) +{ + struct aest_record *record = m->private; + struct record_count count = { 0 }; + + aest_error_count(record, &count); + + seq_printf(m, "CE: %llu\n" + "DE: %llu\n" + "UC: %llu\n" + "UEU: %llu\n" + "UEO: %llu\n" + "UER: %llu\n", + count.ce, count.de, count.uc, count.ueu, + count.uer, count.ueo); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(aest_record_err_count); + static void aest_record_init_debugfs(struct aest_record *record) { debugfs_create_file("err_fr", 0600, record->debugfs, record, @@ -55,6 +114,8 @@ static void aest_record_init_debugfs(struct aest_record *record) &err_misc2_ops); debugfs_create_file("err_misc3", 0600, record->debugfs, record, &err_misc3_ops); + debugfs_create_file("err_count", 0400, record->debugfs, record, + &aest_record_err_count_fops); } static void @@ -63,6 +124,9 @@ aest_node_init_debugfs(struct aest_node *node) int i; struct aest_record *record; + debugfs_create_file("err_count", 0400, node->debugfs, node, + &aest_node_err_count_fops); + for (i = 0; i < node->record_count; i++) { record = &node->records[i]; if (!record->name) diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index ceb9e32bcee3c..802430857dc49 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -116,6 +116,15 @@ struct ce_threshold { u64 reg_val; }; +struct record_count { + u64 ce; + u64 de; + u64 uc; + u64 uer; + u64 ueo; + u64 ueu; +}; + struct aest_record { char *name; int index; @@ -136,6 +145,7 @@ struct aest_record { struct ce_threshold ce; enum ras_ce_threshold threshold_type; + struct record_count count; struct dentry *debugfs; }; From 8c70923841da8bf532c6233df6642662dd15522d Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:52 +0800 Subject: [PATCH 1087/1330] FROMLIST: ras: AEST: Allow configuring CE threshold via debugfs This commit introduces the ability to configure the Corrected Error (CE) threshold for AEST records through debugfs. This allows administrators to dynamically adjust the CE threshold for error reporting. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-13-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit cfc3c506c40440be6ba9ce856c7b921c13ff6ab4) --- Documentation/ABI/testing/debugfs-aest | 16 ++++++++++ drivers/ras/aest/aest-sysfs.c | 42 ++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/Documentation/ABI/testing/debugfs-aest b/Documentation/ABI/testing/debugfs-aest index 295df9e9b4558..4d160072d37a7 100644 --- a/Documentation/ABI/testing/debugfs-aest +++ b/Documentation/ABI/testing/debugfs-aest @@ -24,6 +24,14 @@ Description: See more at: https://developer.arm.com/documentation/den0085/latest/ +What: /sys/kernel/debug/aest/.//ce_threshold +Date: Dec 2025 +KernelVersion 6.19 +Contact: Ruidong Tian +Description: + (WO) Write the ce threshold to all records of this node. Failed + if input exceeded the maximum threshold + What: /sys/kernel/debug/aest/.//err_count Date: Dec 2025 KernelVersion 6.19 @@ -38,6 +46,14 @@ Contact: Ruidong Tian Description: (RO) Read err_* register and return val. +What: /sys/kernel/debug/aest/.//record/ce_threshold +Date: Dec 2025 +KernelVersion 6.19 +Contact: Ruidong Tian +Description: + (RW) Read and write the ce threshold to this record. Failed + if input exceeded the maximum threshold + What: /sys/kernel/debug/aest/.//record/err_count Date: Dec 2025 KernelVersion 6.19 diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c index b54e879506aa9..392e7ad8328ed 100644 --- a/drivers/ras/aest/aest-sysfs.c +++ b/drivers/ras/aest/aest-sysfs.c @@ -7,6 +7,25 @@ #include "aest.h" +static void +aest_store_threshold(struct aest_record *record, void *data) +{ + u64 err_misc0, *threshold = data; + struct ce_threshold *ce = &record->ce; + + if (*threshold > ce->info->max_count) + return; + + ce->threshold = *threshold; + ce->count = ce->info->max_count - ce->threshold + 1; + + err_misc0 = record_read(record, ERXMISC0); + ce->reg_val = (err_misc0 & ~ce->info->mask) | + (ce->count << ce->info->shift); + + record_write(record, ERXMISC0, ce->reg_val); +} + static void aest_error_count(struct aest_record *record, void *data) { @@ -77,6 +96,27 @@ DEFINE_AEST_DEBUGFS_ATTR(err_misc1, ERXMISC1); DEFINE_AEST_DEBUGFS_ATTR(err_misc2, ERXMISC2); DEFINE_AEST_DEBUGFS_ATTR(err_misc3, ERXMISC3); +static int record_ce_threshold_get(void *data, u64 *val) +{ + struct aest_record *record = data; + + *val = record->ce.threshold; + return 0; +} + +static int record_ce_threshold_set(void *data, u64 val) +{ + u64 threshold = val; + struct aest_record *record = data; + + aest_store_threshold(record, &threshold); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(record_ce_threshold_ops, record_ce_threshold_get, + record_ce_threshold_set, "%llu\n"); + static int aest_record_err_count_show(struct seq_file *m, void *data) { struct aest_record *record = m->private; @@ -116,6 +156,8 @@ static void aest_record_init_debugfs(struct aest_record *record) &err_misc3_ops); debugfs_create_file("err_count", 0400, record->debugfs, record, &aest_record_err_count_fops); + debugfs_create_file("ce_threshold", 0600, record->debugfs, record, + &record_ce_threshold_ops); } static void From bdd3a42f9e298a51485d0e26863802670b6dd6f8 Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:53 +0800 Subject: [PATCH 1088/1330] FROMLIST: ras: AEST: Introduce AEST inject interface to test AEST driver AEST offers both soft and hard injection. Soft injection simulates errors in software, providing flexibility to define the error register content. Hard injection, on the other hand, utilizes error injection registers to introduce hardware faults, strictly requiring values that adhere to their specifications. Read Documentation/ABI/testing/debugfs-aest to learn how to use them. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-14-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 4ab219a0f0530d127346d405dadd81243ea677a7) --- Documentation/ABI/testing/debugfs-aest | 37 +++++++ drivers/ras/aest/Makefile | 1 + drivers/ras/aest/aest-core.c | 24 +++-- drivers/ras/aest/aest-inject.c | 131 +++++++++++++++++++++++++ drivers/ras/aest/aest-sysfs.c | 8 +- drivers/ras/aest/aest.h | 2 + 6 files changed, 193 insertions(+), 10 deletions(-) create mode 100644 drivers/ras/aest/aest-inject.c diff --git a/Documentation/ABI/testing/debugfs-aest b/Documentation/ABI/testing/debugfs-aest index 4d160072d37a7..cc41ea7032c72 100644 --- a/Documentation/ABI/testing/debugfs-aest +++ b/Documentation/ABI/testing/debugfs-aest @@ -60,3 +60,40 @@ KernelVersion 6.19 Contact: Ruidong Tian Description: (RO) Outputs error statistics for all this records. + +What: /sys/kernel/debug/aest/.//record/inject/err_* +Date: Dec 2025 +KernelVersion 6.19 +Contact: Ruidong Tian +Description: + (RW) These registers are used to simulate soft injection errors + by holding error register values. You can write any values + to them. To trigger the injection, you need to write soft_inject + at last. The validity of the injected error depends on the + value written to err_status. + + Accepts values - any. + +What: /sys/kernel/debug/aest/.//record/inject/soft_inject +Date: Dec 2025 +KernelVersion 6.19 +Contact: Ruidong Tian +Description: + (WO) Write any value to this file to trigger the error + injection. Make sure you have specified all necessary error + parameters, i.e. this write should be the last step when + injecting errors. + + Accepts values - any. + +What: /sys/kernel/debug/aest/.//record/inject/hard_inject +Date: Dec 2025 +KernelVersion 6.19 +Contact: Ruidong Tian +Description: + (WO) If the AEST table provides error injection registers, + you can write to them via this interface. For instance, + values can be written to the ERXPFGCTL register. The post-injection + behavior is then determined by the hardware specification. + + Accepts values - any. diff --git a/drivers/ras/aest/Makefile b/drivers/ras/aest/Makefile index 75495413d2b6e..5ee10fc8b2e9d 100644 --- a/drivers/ras/aest/Makefile +++ b/drivers/ras/aest/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_AEST) += aest.o aest-y := aest-core.o aest-y += aest-sysfs.o +aest-y += aest-inject.o diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 75cca98024ad7..a290b482bf8b7 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -273,7 +273,7 @@ static void aest_panic(struct aest_record *record, struct ras_ext_regs *regs, panic(msg); } -static void aest_proc_record(struct aest_record *record, void *data) +void aest_proc_record(struct aest_record *record, void *data, bool fake) { struct ras_ext_regs regs = { 0 }; int *count = data; @@ -315,9 +315,15 @@ static void aest_proc_record(struct aest_record *record, void *data) /* panic if unrecoverable and uncontainable error encountered */ ue = FIELD_GET(ERR_STATUS_UET, regs.err_status); if ((regs.err_status & ERR_STATUS_UE) && - (ue == ERR_STATUS_UET_UC || ue == ERR_STATUS_UET_UEU)) - aest_panic(record, ®s, - "AEST: unrecoverable error encountered"); + (ue == ERR_STATUS_UET_UC || ue == ERR_STATUS_UET_UEU)) { + if (fake) + aest_record_info( + record, + "Simulated error! Skip panic due to fault injection\n"); + else + aest_panic(record, ®s, + "AEST: unrecoverable error encountered"); + } aest_log(record, ®s); @@ -335,7 +341,8 @@ static void aest_proc_record(struct aest_record *record, void *data) record_write(record, ERXSTATUS, regs.err_status); } -static void aest_node_foreach_record(void (*func)(struct aest_record *, void *), +static void aest_node_foreach_record(void (*func)(struct aest_record *, void *, + bool), struct aest_node *node, void *data, unsigned long *bitmap) { @@ -344,7 +351,7 @@ static void aest_node_foreach_record(void (*func)(struct aest_record *, void *), for_each_clear_bit(i, bitmap, node->record_count) { aest_select_record(node, i); - func(&node->records[i], data); + func(&node->records[i], data, false); aest_sync(node); } @@ -379,7 +386,7 @@ static int aest_proc(struct aest_node *node) if (test_bit(i * BITS_PER_LONG + j, node->status_reporting)) continue; - aest_proc_record(&node->records[j], &count); + aest_proc_record(&node->records[j], &count, false); } } @@ -595,7 +602,8 @@ static int aest_init_record(struct aest_record *record, int i, return 0; } -static void aest_online_record(struct aest_record *record, void *data) +static void aest_online_record(struct aest_record *record, void *data, + bool __unused) { if (record_read(record, ERXFR) & ERR_FR_CE) aest_set_ce_threshold(record); diff --git a/drivers/ras/aest/aest-inject.c b/drivers/ras/aest/aest-inject.c new file mode 100644 index 0000000000000..fe6ccac8338e4 --- /dev/null +++ b/drivers/ras/aest/aest-inject.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Error Source Table Support + * + * Copyright (c) 2024, Alibaba Group. + */ + +#include "aest.h" + +static struct ras_ext_regs regs_inj; + +struct inj_attr { + struct attribute attr; + ssize_t (*show)(struct aest_node *n, struct inj_attr *a, char *b); + ssize_t (*store)(struct aest_node *n, struct inj_attr *a, const char *b, + size_t c); +}; + +struct aest_inject { + struct aest_node *node; + struct kobject kobj; +}; + +#define to_inj(k) container_of(k, struct aest_inject, kobj) +#define to_inj_attr(a) container_of(a, struct inj_attr, attr) + +static u64 aest_sysreg_read_inject(void *__unused, u32 offset) +{ + u64 *p = (u64 *)®s_inj; + + return p[offset/8]; +} + +static void aest_sysreg_write_inject(void *base, u32 offset, u64 val) +{ + u64 *p = (u64 *)®s_inj; + + p[offset/8] = val; +} + +static u64 aest_iomem_read_inject(void *base, u32 offset) +{ + u64 *p = (u64 *)®s_inj; + + return p[offset/8]; +} + +static void aest_iomem_write_inject(void *base, u32 offset, u64 val) +{ + u64 *p = (u64 *)®s_inj; + + p[offset/8] = val; +} + +static struct aest_access aest_access_inject[] = { + [ACPI_AEST_NODE_SYSTEM_REGISTER] = { + .read = aest_sysreg_read_inject, + .write = aest_sysreg_write_inject, + }, + + [ACPI_AEST_NODE_MEMORY_MAPPED] = { + .read = aest_iomem_read_inject, + .write = aest_iomem_write_inject, + }, + [ACPI_AEST_NODE_SINGLE_RECORD_MEMORY_MAPPED] = { + .read = aest_iomem_read_inject, + .write = aest_iomem_write_inject, + }, + { } +}; + +static int soft_inject_store(void *data, u64 val) +{ + int count = 0; + struct aest_record record_inj, *record = data; + struct aest_node node_inj, *node = record->node; + + memcpy(&node_inj, node, sizeof(*node)); + node_inj.name = "AEST-injection"; + + record_inj.access = &aest_access_inject[node->info->interface_hdr->type]; + record_inj.node = &node_inj; + record_inj.index = record->index; + + regs_inj.err_status |= ERR_STATUS_V; + + aest_proc_record(&record_inj, &count, true); + + if (count != 1) + return -EIO; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(soft_inject_ops, NULL, soft_inject_store, "%llu\n"); + +static int hard_inject_store(void *data, u64 val) +{ + struct aest_record *record = data; + struct aest_node *node = record->node; + + if (!node->inj) + return -EPERM; + + aest_select_record(node, record->index); + record_write(record, ERXPFGCTL, val); + record_write(record, ERXPFGCDN, 0x100); + aest_sync(node); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(hard_inject_ops, NULL, hard_inject_store, "%llu\n"); + +void aest_inject_init_debugfs(struct aest_record *record) +{ + struct dentry *inj; + + inj = debugfs_create_dir("inject", record->debugfs); + + debugfs_create_u64("err_fr", 0600, inj, ®s_inj.err_fr); + debugfs_create_u64("err_ctrl", 0600, inj, ®s_inj.err_ctlr); + debugfs_create_u64("err_status", 0600, inj, ®s_inj.err_status); + debugfs_create_u64("err_addr", 0600, inj, ®s_inj.err_addr); + debugfs_create_u64("err_misc0", 0600, inj, ®s_inj.err_misc[0]); + debugfs_create_u64("err_misc1", 0600, inj, ®s_inj.err_misc[1]); + debugfs_create_u64("err_misc2", 0600, inj, ®s_inj.err_misc[2]); + debugfs_create_u64("err_misc3", 0600, inj, ®s_inj.err_misc[3]); + debugfs_create_file("soft_inject", 0400, inj, record, &soft_inject_ops); + + if (record->node->inj) + debugfs_create_file("hard_inject", 0400, inj, record, &hard_inject_ops); +} diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c index 392e7ad8328ed..66e9c1103f996 100644 --- a/drivers/ras/aest/aest-sysfs.c +++ b/drivers/ras/aest/aest-sysfs.c @@ -158,6 +158,7 @@ static void aest_record_init_debugfs(struct aest_record *record) &aest_record_err_count_fops); debugfs_create_file("ce_threshold", 0600, record->debugfs, record, &record_ce_threshold_ops); + aest_inject_init_debugfs(record); } static void @@ -190,8 +191,8 @@ aest_oncore_dev_init_debugfs(struct aest_device *adev) for_each_possible_cpu(cpu) { percpu_dev = this_cpu_ptr(adev->adev_oncore); - snprintf(name, sizeof(name), "processor%u", cpu); - percpu_dev->debugfs = debugfs_create_dir(name, aest_debugfs); + snprintf(name, sizeof(name), "processor%u%u", cpu); + percpu_dev->debugfs = debugfs_create_dir(name, adev->debugfs); for (i = 0; i < adev->node_cnt; i++) { node = &adev->nodes[i]; @@ -208,6 +209,9 @@ void aest_dev_init_debugfs(struct aest_device *adev) int i; struct aest_node *node; + if (!aest_debugfs) + dev_err(adev->dev, "debugfs not enabled\n"); + adev->debugfs = debugfs_create_dir(dev_name(adev->dev), aest_debugfs); if (aest_dev_is_oncore(adev)) { aest_oncore_dev_init_debugfs(adev); diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 802430857dc49..2f6a7b9ca4efd 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -362,3 +362,5 @@ static inline bool aest_dev_is_oncore(struct aest_device *adev) } void aest_dev_init_debugfs(struct aest_device *adev); +void aest_inject_init_debugfs(struct aest_record *record); +void aest_proc_record(struct aest_record *record, void *data, bool fake); From 64f2e4037cf0127068ae564a17db141f950dc78d Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:54 +0800 Subject: [PATCH 1089/1330] FROMLIST: ras: AEST: Add framework to process AEST vendor node AEST table include vendor error node to support the component that do not implement standard Arm RAS architecture[1]. Each vendor node may have their own initialize and interrupt handle function. This patch supply a framework to process vendor error nodes, the vendor process function is binded with vendor HID. [1]: https://developer.arm.com/documentation/ddi0587/latest/ Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-15-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit 7eafc168926815372d64f3db10a650b6c80f3d9c) --- drivers/ras/aest/aest-core.c | 28 +++++++++++++++++++++++++++- drivers/ras/aest/aest.h | 5 +++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index a290b482bf8b7..047c9a8cffe40 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -922,6 +922,29 @@ static int aest_setup_irq(struct platform_device *pdev, return 0; } +static struct aest_vendor_match vendor_match[] = { + { }, +}; + +static int +aest_vendor_probe(struct aest_device *adev, struct aest_hnode *ahnode) +{ + int i; + struct acpi_aest_node *anode; + + anode = list_first_entry(&ahnode->list, struct acpi_aest_node, list); + if (!anode) + return -ENODEV; + + aest_dev_dbg(adev, "Try to probe vendor node %s\n", anode->vendor->acpi_hid); + for (i = 0; i < ARRAY_SIZE(vendor_match); i++) { + if (!strncmp(vendor_match[i].hid, anode->vendor->acpi_hid, 8)) + return vendor_match[i].probe(adev, ahnode); + } + + return -ENODEV; +} + static int aest_device_probe(struct platform_device *pdev) { int ret; @@ -947,7 +970,10 @@ static int aest_device_probe(struct platform_device *pdev) } init_llist_head(&adev->event_list); - ret = aest_init_nodes(adev, ahnode); + if (ahnode->type == ACPI_AEST_VENDOR_ERROR_NODE) + ret = aest_vendor_probe(adev, ahnode); + else + ret = aest_init_nodes(adev, ahnode); if (ret) return ret; diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 2f6a7b9ca4efd..304c03839d31f 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -244,6 +244,11 @@ static const char *const aest_node_name[] = { [ACPI_AEST_PROXY_ERROR_NODE] = "proxy", }; +struct aest_vendor_match { + char hid[ACPI_ID_LEN]; + int (*probe)(struct aest_device *adev, struct aest_hnode *anode); +}; + static inline int aest_set_name(struct aest_device *adev, struct aest_hnode *ahnode) { From 06dff6e0ba92e419ad93cc9196a527280f2137ac Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:55 +0800 Subject: [PATCH 1090/1330] FROMLIST: ras: AEST: support vendor node CMN700 The CMN (Coherent Mesh Network) architecture incorporates five distinct device types. Each device type is associated with an error group register set. The struct aest_cmn_700 models a single CMN instance, while struct aest_cmn_700_child represents an individual CMN device. CMN's error records utilize a memory-mapped single error record view [1]. Critically, one error record corresponds to one AEST node, implying that a single CMN instance can generate hundreds of AEST nodes. To manage this scale, this driver introduces a virtual AEST node, which represents an entire CMN device, such as an HNI or HNF. This allows an HNF AEST node, for instance, to leverage its errgsr register to pinpoint which specific error record has reported an error. During the AEST probe phase, the CMN AEST driver identifies the CMN node type using the cmn_node_info register. It then reorganizes all AEST nodes belonging to the same CMN node type into a cohesive CMN AEST node structure. To locate the relevant CMN register addresses, the CMN's presence in the DSDT is required, along with the CMN node offset specified in the AEST vendor specification data [1]. [1]: https://developer.arm.com/documentation/102308/latest/ Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-16-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit f8822df5d85db1ae913455e3fba25b4e28402672) --- arch/arm64/include/asm/arm-cmn.h | 47 +++++ drivers/perf/arm-cmn.c | 37 +--- drivers/ras/aest/Makefile | 1 + drivers/ras/aest/aest-cmn.c | 330 +++++++++++++++++++++++++++++++ drivers/ras/aest/aest-core.c | 42 ++-- drivers/ras/aest/aest.h | 39 ++++ 6 files changed, 444 insertions(+), 52 deletions(-) create mode 100644 arch/arm64/include/asm/arm-cmn.h create mode 100644 drivers/ras/aest/aest-cmn.c diff --git a/arch/arm64/include/asm/arm-cmn.h b/arch/arm64/include/asm/arm-cmn.h new file mode 100644 index 0000000000000..1b9f506797944 --- /dev/null +++ b/arch/arm64/include/asm/arm-cmn.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2015 ARM Ltd. + */ +#ifndef __ASM_ARM_CMN_H +#define __ASM_ARM_CMN_H + +#include + +/* Common register stuff */ +#define CMN_NODE_INFO 0x0000 +#define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) +#define CMN_NI_NODE_ID GENMASK_ULL(31, 16) +#define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) + +enum cmn_node_type { + CMN_TYPE_INVALID, + CMN_TYPE_DVM, + CMN_TYPE_CFG, + CMN_TYPE_DTC, + CMN_TYPE_HNI, + CMN_TYPE_HNF, + CMN_TYPE_XP, + CMN_TYPE_SBSX, + CMN_TYPE_MPAM_S, + CMN_TYPE_MPAM_NS, + CMN_TYPE_RNI, + CMN_TYPE_RND = 0xd, + CMN_TYPE_RNSAM = 0xf, + CMN_TYPE_MTSX, + CMN_TYPE_HNP, + CMN_TYPE_CXRA = 0x100, + CMN_TYPE_CXHA, + CMN_TYPE_CXLA, + CMN_TYPE_CCRA, + CMN_TYPE_CCHA, + CMN_TYPE_CCLA, + CMN_TYPE_CCLA_RNI, + CMN_TYPE_HNS = 0x200, + CMN_TYPE_HNS_MPAM_S, + CMN_TYPE_HNS_MPAM_NS, + CMN_TYPE_APB = 0x1000, + /* Not a real node type */ + CMN_TYPE_WP = 0x7770 +}; + +#endif /* __ASM_ARM_CMN_H */ diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 40c05c519a1d9..33d182c400c0a 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -2,6 +2,7 @@ // Copyright (C) 2016-2020 Arm Limited // ARM CMN/CI interconnect PMU driver +#include #include #include #include @@ -19,11 +20,6 @@ #include /* Common register stuff */ -#define CMN_NODE_INFO 0x0000 -#define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) -#define CMN_NI_NODE_ID GENMASK_ULL(31, 16) -#define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) - #define CMN_CHILD_INFO 0x0080 #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0) #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16) @@ -242,37 +238,6 @@ enum cmn_revision { REV_CI700_R2P0, }; -enum cmn_node_type { - CMN_TYPE_INVALID, - CMN_TYPE_DVM, - CMN_TYPE_CFG, - CMN_TYPE_DTC, - CMN_TYPE_HNI, - CMN_TYPE_HNF, - CMN_TYPE_XP, - CMN_TYPE_SBSX, - CMN_TYPE_MPAM_S, - CMN_TYPE_MPAM_NS, - CMN_TYPE_RNI, - CMN_TYPE_RND = 0xd, - CMN_TYPE_RNSAM = 0xf, - CMN_TYPE_MTSX, - CMN_TYPE_HNP, - CMN_TYPE_CXRA = 0x100, - CMN_TYPE_CXHA, - CMN_TYPE_CXLA, - CMN_TYPE_CCRA, - CMN_TYPE_CCHA, - CMN_TYPE_CCLA, - CMN_TYPE_CCLA_RNI, - CMN_TYPE_HNS = 0x200, - CMN_TYPE_HNS_MPAM_S, - CMN_TYPE_HNS_MPAM_NS, - CMN_TYPE_APB = 0x1000, - /* Not a real node type */ - CMN_TYPE_WP = 0x7770 -}; - enum cmn_filter_select { SEL_NONE = -1, SEL_OCCUP1ID, diff --git a/drivers/ras/aest/Makefile b/drivers/ras/aest/Makefile index 5ee10fc8b2e9d..e5a45fde6d362 100644 --- a/drivers/ras/aest/Makefile +++ b/drivers/ras/aest/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_AEST) += aest.o aest-y := aest-core.o aest-y += aest-sysfs.o aest-y += aest-inject.o +aest-y += aest-cmn.o diff --git a/drivers/ras/aest/aest-cmn.c b/drivers/ras/aest/aest-cmn.c new file mode 100644 index 0000000000000..ad82ed163a8c5 --- /dev/null +++ b/drivers/ras/aest/aest-cmn.c @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Error Source Table CMN700 Support + * + * Copyright (c) 2025, Alibaba Inc + */ + +#include + +#include "aest.h" + +/* + * CMN include 5 device types, each device type has an error group register set + * which contains a set of error records. The struct aest_cmn_700 represents + * one CMN Instance, and the struct aest_cmn_700_child represent one CMN device. + * The error record of CMN use memory-mapped single error record view, so one + * record is correspond to one AEST node, it means there will be hundreds of + * AEST node of CMN. As described in chapters 2.6.3.4 of Arm ACPI Spec[1], we + * use vendor define data to recognize the device type of an AEST node. So AEST + * driver can enumerate all CMN AEST node to initialize struct aest_cmn_700 and + * aest_cmn_700_child with HID, UID and other CMN info described in AEST or CMN + * register. + * + * Each CMN Instance has their own error interrupt and the struct aest_cmn_700 + * is passed to interrupt context. OS check error group register set to locate + * record which report error. All procedure is similar with chapters 3.8 in + * Arm CMN Spec[2]. + * + * The CMN RAS architecture is showed as follow: + * + * +----+ + * -->|XP | ...... + * | +----+ + * | + * | +----+ ...... + * | |HNI | +----------------+ + * | +----+ ->|record/AEST node| + * | | +----------------+ + * +------------+ | +----+ | . + * |CMN Instance|--| |HNF |---| . + * +------------+ | +----+ | . + * | | +----------------+ + * | +----+ ->|record/AEST node| + * | |SBSX| +----------------+ + * | +----+ ...... + * | + * | +----+ + * -->|CCG | ...... + * +----+ + * + * [1]: https://developer.arm.com/documentation/den0093/latest + * [2]: https://developer.arm.com/documentation/102308/latest + */ + +#define CMN_RAS_DEV_NUM 6 +#define CMN700_ERRGSR_NUM 8 +#define CMN_MAX_UID 8 +#define CMN_ERRDEVARCH 0x3FB8 +#define CMN_ERRDEVARCH_REV GENMASK(19, 16) +#define CMN_ERRGSR_OFFSET 0x3000 + +struct cmn_vendor_data { + int node_type; + int node_id; + int logic_id; +}; + +struct cmn_config { + int errgsr_num; + int dev_num; + int ras_ver; + const int *node_id_map; + const char *const *node_name; + int (*errgsr_mapping)(int errgsr_bit); + u64 (*errgsr_offset)(u64 hnd_ofset, int node_idx); +}; + +static const char *const cmn700_node_name[] = { + [CMN_TYPE_HNI] = "HNI", [CMN_TYPE_HNF] = "HNF", + [CMN_TYPE_XP] = "XP", [CMN_TYPE_SBSX] = "SBSX", + [CMN_TYPE_CXRA] = "RND", [CMN_TYPE_MTSX] = "MTSX", +}; + +static const int cmn700_node_id_map[] = { + [CMN_TYPE_HNI] = 1, [CMN_TYPE_HNF] = 2, [CMN_TYPE_XP] = 0, + [CMN_TYPE_SBSX] = 3, [CMN_TYPE_CXRA] = 4, [CMN_TYPE_MTSX] = 5, +}; + +static u64 cmn_dev_array[CMN_MAX_UID]; +static struct cmn_config *cmn_config; + +static u64 cmn700_errgsr_offset(u64 hnd_offset, int node_idx) +{ + return hnd_offset + CMN_ERRGSR_OFFSET + + (node_idx * 2) * CMN700_ERRGSR_NUM * 8; +} + +static struct cmn_config cmn700_config = { + .errgsr_num = CMN700_ERRGSR_NUM, + .dev_num = CMN_RAS_DEV_NUM, + .ras_ver = 1, + .node_name = cmn700_node_name, + .node_id_map = cmn700_node_id_map, + .errgsr_mapping = cmn700_errgsr_mapping, + .errgsr_offset = cmn700_errgsr_offset, +}; + +static acpi_status aest_cmn_700_resource_ioremap(struct acpi_resource *res, + void *data) +{ + struct acpi_resource_address64 addr64; + u32 *uid = data; + acpi_status status; + + status = acpi_resource_to_address64(res, &addr64); + if (ACPI_FAILURE(status) || (addr64.resource_type != ACPI_MEMORY_RANGE)) + return AE_OK; + + cmn_dev_array[*uid] = (u64)ioremap(addr64.address.minimum, + addr64.address.address_length); + + pr_debug("CMN device resource [%llx-%llx] ioremap to %llx\n", + addr64.address.minimum, addr64.address.maximum, + cmn_dev_array[*uid]); + + return AE_CTRL_TERMINATE; +} + +static acpi_status aest_cmn_get_dev_by_uid(acpi_handle handle, u32 level, + void *data, void **return_value) +{ + u32 *match_uid = data; + acpi_status status; + unsigned long long uid; + + status = acpi_evaluate_integer(handle, METHOD_NAME__UID, NULL, &uid); + if (ACPI_FAILURE(status)) { + pr_err("Do not find devive\n"); + return_ACPI_STATUS(status); + } + + if (uid != *match_uid) + return AE_OK; + + pr_debug("CMN device instance %llx, walk through resource\n", uid); + + status = acpi_walk_resources(handle, METHOD_NAME__CRS, + aest_cmn_700_resource_ioremap, data); + + if (ACPI_FAILURE(status)) { + pr_err("Device do not have resource\n"); + return_ACPI_STATUS(status); + } + + return AE_CTRL_TERMINATE; +} + +static inline int aest_cmn_node_ver(void *base) +{ + return FIELD_GET(CMN_ERRDEVARCH_REV, + readl_relaxed(base + CMN_ERRDEVARCH)); +} + +static int aest_cmn_init_node(struct aest_device *adev, + struct aest_node *cmn_node, + struct acpi_aest_node *anode, u64 type, + u64 errgsr_addr) +{ + cmn_node->info = anode; + cmn_node->name = devm_kasprintf(adev->dev, GFP_KERNEL, "%s", + cmn_config->node_name[type]); + if (!cmn_node->name) + return -ENOMEM; + cmn_node->errgsr = (void *)errgsr_addr; + cmn_node->type = anode->type; + cmn_node->adev = adev; + cmn_node->version = cmn_config->ras_ver; + cmn_node->errgsr_num = cmn_config->errgsr_num; + cmn_node->errgsr_mapping = cmn_config->errgsr_mapping; + cmn_node->record_count = cmn_node->errgsr_num * BITS_PER_LONG / 2; + cmn_node->record_implemented = devm_bitmap_zalloc( + adev->dev, cmn_node->record_count, GFP_KERNEL); + if (!cmn_node->record_implemented) + return -ENOMEM; + bitmap_set(cmn_node->record_implemented, 0, cmn_node->record_count); + + cmn_node->status_reporting = devm_bitmap_zalloc( + adev->dev, cmn_node->record_count, GFP_KERNEL); + if (!cmn_node->status_reporting) + return -ENOMEM; + bitmap_set(cmn_node->status_reporting, 0, cmn_node->record_count); + + cmn_node->records = devm_kcalloc(adev->dev, cmn_node->record_count, + sizeof(struct aest_record), + GFP_KERNEL); + if (!cmn_node->records) + return -ENOMEM; + + aest_node_dbg(cmn_node, "Node init with errgsr %llx\n", errgsr_addr); + + return 0; +} + +static int aest_cmn_reorgnize_node(struct aest_device *adev, + struct acpi_aest_node *anode, u64 base) +{ + struct aest_node *cmn_node; + u64 hnd_offset, cmn_node_offset, reg, logic_id, type, node_id; + u64 errgsr_addr, hnd_base; + struct aest_record *record; + int ret, node_index; + struct cmn_vendor_data *vendor_data; + + if (anode->interface_hdr->type != + ACPI_AEST_NODE_SINGLE_RECORD_MEMORY_MAPPED) { + aest_dev_err(adev, "CMN just use single memory mapping\n"); + return -ENODEV; + } + + hnd_offset = *((u64 *)anode->vendor->vendor_specific_data); + cmn_node_offset = *((u64 *)&anode->vendor->vendor_specific_data[8]); + + reg = readq_relaxed((void *)base + cmn_node_offset + CMN_NODE_INFO); + + logic_id = FIELD_GET(CMN_NI_LOGICAL_ID, reg); + type = FIELD_GET(CMN_NI_NODE_TYPE, reg); + node_id = FIELD_GET(CMN_NI_NODE_ID, reg); + + hnd_base = base + hnd_offset; + node_index = cmn_config->node_id_map[type]; + errgsr_addr = base + cmn_config->errgsr_offset(hnd_offset, node_index); + + // node not register, create it + cmn_node = &adev->nodes[node_index]; + if (!cmn_node->errgsr) { + ret = aest_cmn_init_node(adev, cmn_node, anode, type, + errgsr_addr); + if (ret) + return -ENOMEM; + } + + aest_dev_dbg(adev, "node type %llx, id %llx, offset %llx\n", type, + logic_id, cmn_node_offset); + + if (!test_bit(0, anode->record_implemented)) + clear_bit(logic_id, cmn_node->record_implemented); + + if (!test_bit(0, anode->status_reporting)) + clear_bit(logic_id, cmn_node->status_reporting); + + record = &cmn_node->records[logic_id]; + record->name = + devm_kasprintf(adev->dev, GFP_KERNEL, "record%lld", logic_id); + if (!record->name) + return -ENOMEM; + record->regs_base = devm_ioremap( + adev->dev, (resource_size_t)anode->interface_hdr->address, + sizeof(struct ras_ext_regs)); + if (!record->regs_base) + return -ENOMEM; + record->addressing_mode = test_bit(0, anode->addressing_mode); + record->node = cmn_node; + record->index = logic_id; + record->access = &aest_access[anode->interface_hdr->type]; + + vendor_data = devm_kzalloc(adev->dev, sizeof(struct cmn_vendor_data), + GFP_KERNEL); + vendor_data->node_type = type; + vendor_data->node_id = node_id; + vendor_data->logic_id = logic_id; + + record->vendor_data = vendor_data; + record->vendor_data_size = sizeof(struct cmn_vendor_data); + + aest_record_dbg(record, "base %llx\n", anode->interface_hdr->address); + + return 0; +} + +// reorgnize cmn node +static int aest_cmn_probe(struct aest_device *adev, struct aest_hnode *ahnode) +{ + acpi_status status; + u64 base; + int ret = 0; + struct acpi_aest_node *anode; + char name[9]; + + anode = list_first_entry(&ahnode->list, struct acpi_aest_node, list); + if (!anode) + return -ENODEV; + + if (!cmn_dev_array[anode->vendor->acpi_uid]) { + snprintf(name, 9, "%s", anode->vendor->acpi_hid); + status = acpi_get_devices(name, aest_cmn_get_dev_by_uid, + &anode->vendor->acpi_uid, NULL); + if (ACPI_FAILURE(status)) { + aest_dev_err(adev, "Can not find base\n"); + return_ACPI_STATUS(status); + } + } + base = cmn_dev_array[anode->vendor->acpi_uid]; + if (!base) { + aest_dev_err(adev, "Device base invalid\n"); + return -ENODEV; + } + + adev->type = anode->type; + adev->node_cnt = cmn_config->dev_num; + adev->nodes = devm_kcalloc(adev->dev, adev->node_cnt, + sizeof(struct aest_node), GFP_KERNEL); + if (!adev->nodes) + return -ENOMEM; + aest_set_name(adev, ahnode); + + list_for_each_entry(anode, &ahnode->list, list) { + ret = aest_cmn_reorgnize_node(adev, anode, base); + if (ret) + return ret; + } + + return 0; +} + +int aest_cmn700_probe(struct aest_device *adev, struct aest_hnode *ahnode) +{ + cmn_config = &cmn700_config; + + return aest_cmn_probe(adev, ahnode); +} diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 047c9a8cffe40..bbf8b1142be75 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -152,6 +152,8 @@ static void init_aest_event(struct aest_event *event, memcpy(&event->regs, regs, sizeof(*regs)); event->index = record->index; event->addressing_mode = record->addressing_mode; + event->vendor_data_size = record->vendor_data_size; + event->vendor_data = record->vendor_data; } static int aest_node_gen_pool_add(struct aest_device *adev, @@ -341,10 +343,9 @@ void aest_proc_record(struct aest_record *record, void *data, bool fake) record_write(record, ERXSTATUS, regs.err_status); } -static void aest_node_foreach_record(void (*func)(struct aest_record *, void *, - bool), - struct aest_node *node, void *data, - unsigned long *bitmap) +void aest_node_foreach_record(void (*func)(struct aest_record *, void *, bool), + struct aest_node *node, void *data, + unsigned long *bitmap) { int i; @@ -359,7 +360,7 @@ static void aest_node_foreach_record(void (*func)(struct aest_record *, void *, static int aest_proc(struct aest_node *node) { - int count = 0, i, j, size = node->record_count; + int count = 0, i, j, size = node->record_count, record_idx; u64 err_group = 0; aest_node_dbg(node, "Poll bitmap %*pb\n", size, @@ -374,19 +375,21 @@ static int aest_proc(struct aest_node *node) node->status_reporting); for (i = 0; i < BITS_TO_U64(size); i++) { err_group = readq_relaxed((void *)node->errgsr + i * 8); - aest_node_dbg(node, "errgsr[%d]: 0x%llx\n", i, err_group); - for_each_set_bit(j, (unsigned long *)&err_group, BITS_PER_LONG) { + record_idx = + node->errgsr_mapping(i * BITS_PER_LONG + j); + aest_node_dbg(node, "errgsr[%d]: bit %d occur error\n", + i, record_idx); /* * Error group base is only valid in Memory Map node, * so driver do not need to write select register and * sync. */ - if (test_bit(i * BITS_PER_LONG + j, - node->status_reporting)) + if (test_bit(record_idx, node->status_reporting)) continue; - aest_proc_record(&node->records[j], &count, false); + aest_proc_record(&node->records[record_idx], &count, + false); } } @@ -398,8 +401,11 @@ static irqreturn_t aest_irq_func(int irq, void *input) struct aest_device *adev = input; int i; - for (i = 0; i < adev->node_cnt; i++) + for (i = 0; i < adev->node_cnt; i++) { + if (!adev->nodes[i].record_count) + continue; aest_proc(&adev->nodes[i]); + } return IRQ_HANDLED; } @@ -776,6 +782,7 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node, node->info = anode; node->type = anode->type; node->version = get_aest_node_ver(node); + node->errgsr_mapping = default_errgsr_mapping; node->name = alloc_aest_node_name(node); if (!node->name) return -ENOMEM; @@ -828,6 +835,7 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node, if (!node->records) return -ENOMEM; + node->errgsr_num = DIV_ROUND_UP(node->record_count, BITS_PER_LONG); for (i = 0; i < node->record_count; i++) { ret = aest_init_record(&node->records[i], i, node); if (ret) @@ -923,11 +931,12 @@ static int aest_setup_irq(struct platform_device *pdev, } static struct aest_vendor_match vendor_match[] = { - { }, + { "ARMHC700", &aest_cmn700_probe }, + {}, }; -static int -aest_vendor_probe(struct aest_device *adev, struct aest_hnode *ahnode) +static int aest_vendor_probe(struct aest_device *adev, + struct aest_hnode *ahnode) { int i; struct acpi_aest_node *anode; @@ -936,13 +945,14 @@ aest_vendor_probe(struct aest_device *adev, struct aest_hnode *ahnode) if (!anode) return -ENODEV; - aest_dev_dbg(adev, "Try to probe vendor node %s\n", anode->vendor->acpi_hid); + aest_dev_dbg(adev, "Try to probe vendor node %s\n", + anode->vendor->acpi_hid); for (i = 0; i < ARRAY_SIZE(vendor_match); i++) { if (!strncmp(vendor_match[i].hid, anode->vendor->acpi_hid, 8)) return vendor_match[i].probe(adev, ahnode); } - return -ENODEV; + return 0; } static int aest_device_probe(struct platform_device *pdev) diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 304c03839d31f..9d67d79eb4a2c 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -94,8 +94,16 @@ struct aest_event { /* Vendor node : hardware ID. */ char *hid; u32 index; + u64 ce_threshold; int addressing_mode; struct ras_ext_regs regs; + + /* + * This field is used to store vendor specific data for decoding error + * record by EDAC driver. + */ + void *vendor_data; + size_t vendor_data_size; }; struct aest_access { @@ -147,6 +155,9 @@ struct aest_record { enum ras_ce_threshold threshold_type; struct record_count count; struct dentry *debugfs; + + void *vendor_data; + size_t vendor_data_size; }; struct aest_group { @@ -208,6 +219,19 @@ struct aest_node { */ unsigned long *status_reporting; int version; + /* + * Usually bit[n] in errgsr indicates [n]th error record within this + * error node report error. But some compoent may have different rules. + * For example, CMN700 TRM 4.3.5.12 say: + * ``` Error occurs when the index is even and Fault + * occurs when the index is odd. ``` + * Bit[n]: record[n] report ERROR. + * Bit[n + 1]: record[n] report FAULT. + * errgsr_mapping function is used to map errgsr bit to record index + * for various components. + */ + int (*errgsr_mapping)(int errgsr_bit); + int errgsr_num; const struct aest_group *group; struct aest_device *adev; @@ -366,6 +390,21 @@ static inline bool aest_dev_is_oncore(struct aest_device *adev) return adev->type == ACPI_AEST_PROCESSOR_ERROR_NODE; } +static inline int default_errgsr_mapping(int errgsr_bit) +{ + return errgsr_bit; +} + +static inline int cmn700_errgsr_mapping(int errgsr_bit) +{ + return errgsr_bit / 2; +} + void aest_dev_init_debugfs(struct aest_device *adev); void aest_inject_init_debugfs(struct aest_record *record); void aest_proc_record(struct aest_record *record, void *data, bool fake); +void aest_node_foreach_record(void (*func)(struct aest_record *, void *, bool), + struct aest_node *node, void *data, + unsigned long *bitmap); + +int aest_cmn700_probe(struct aest_device *adev, struct aest_hnode *ahnode); From 04e602b323376d3e80b9d157f6ee0b81efafa6a5 Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 22 Jan 2026 17:46:56 +0800 Subject: [PATCH 1091/1330] FROMLIST: trace, ras: add ARM RAS extension trace event Add a trace event for hardware errors reported by the ARMv8 RAS extension registers. userspace app can monitor this trace event and decode error information. Signed-off-by: Ruidong Tian Link: https://patch.msgid.link/20260122094656.73399-17-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda (cherry picked from commit b5a45a89ed06f88be6554ab937a93a5ccea2a2ec) --- drivers/ras/aest/aest-core.c | 6 +++ drivers/ras/ras.c | 3 ++ include/ras/ras_event.h | 71 ++++++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index bbf8b1142be75..6a2d84b47721b 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -13,6 +13,8 @@ #include #include +#include + #include "aest.h" DEFINE_PER_CPU(struct aest_device, percpu_adev); @@ -90,6 +92,10 @@ static void aest_print(struct aest_event *event) pr_err("%s ERR%dMISC3: 0x%llx\n", pfx_seq, index, regs->err_misc[3]); } + + trace_arm_ras_ext_event(event->type, event->id0, event->id1, + event->index, event->hid, &event->regs, + event->vendor_data, event->vendor_data_size); } static void aest_handle_memory_failure(u64 addr) diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index 03df3db623346..c8858b745021c 100644 --- a/drivers/ras/ras.c +++ b/drivers/ras/ras.c @@ -115,6 +115,9 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(extlog_mem_event); EXPORT_TRACEPOINT_SYMBOL_GPL(mc_event); EXPORT_TRACEPOINT_SYMBOL_GPL(non_standard_event); EXPORT_TRACEPOINT_SYMBOL_GPL(arm_event); +#ifdef CONFIG_ARM64_RAS_EXTN +EXPORT_TRACEPOINT_SYMBOL_GPL(arm_ras_ext_event); +#endif static int __init parse_ras_param(char *str) { diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index fdb785fa4613a..c4063f7ad7342 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -381,6 +381,77 @@ TRACE_EVENT(aer_event, "Not available") ); #endif /* CONFIG_PCIEAER */ + +/* + * ARM RAS Extension Events Report + * + * This event is generated when an error reported by the ARM RAS extension + * hardware is detected. + */ + +#ifdef CONFIG_ARM64_RAS_EXTN +#include +TRACE_EVENT(arm_ras_ext_event, + + TP_PROTO(const u8 type, + const u32 id0, + const u32 id1, + const u32 index, + char *hid, + struct ras_ext_regs *regs, + const u8 *data, + const u32 len), + + TP_ARGS(type, id0, id1, index, hid, regs, data, len), + + TP_STRUCT__entry( + __field(u8, type) + __field(u32, id0) + __field(u32, id1) + __field(u32, index) + __field(char *, hid) + __field(u64, err_fr) + __field(u64, err_ctlr) + __field(u64, err_status) + __field(u64, err_addr) + __field(u64, err_misc0) + __field(u64, err_misc1) + __field(u64, err_misc2) + __field(u64, err_misc3) + __field(u32, len) + __dynamic_array(u8, buf, len) + ), + + TP_fast_assign( + __entry->type = type; + __entry->id0 = id0; + __entry->id1 = id1; + __entry->index = index; + __entry->hid = hid; + __entry->err_fr = regs->err_fr; + __entry->err_ctlr = regs->err_ctlr; + __entry->err_status = regs->err_status; + __entry->err_addr = regs->err_addr; + __entry->err_misc0 = regs->err_misc[0]; + __entry->err_misc1 = regs->err_misc[1]; + __entry->err_misc2 = regs->err_misc[2]; + __entry->err_misc3 = regs->err_misc[3]; + __entry->len = len; + memcpy(__get_dynamic_array(buf), data, len); + ), + + TP_printk("type: %d; id0: %d; id1: %d; index: %d; hid: %s; " + "ERR_FR: %llx; ERR_CTLR: %llx; ERR_STATUS: %llx; " + "ERR_ADDR: %llx; ERR_MISC0: %llx; ERR_MISC1: %llx; " + "ERR_MISC2: %llx; ERR_MISC3: %llx; data len:%d; raw data:%s", + __entry->type, __entry->id0, __entry->id1, __entry->index, + __entry->hid, __entry->err_fr, __entry->err_ctlr, + __entry->err_status, __entry->err_addr, __entry->err_misc0, + __entry->err_misc1, __entry->err_misc2, __entry->err_misc3, + __entry->len, + __print_hex(__get_dynamic_array(buf), __entry->len)) +); +#endif /* CONFIG_ARM64_RAS_EXTN */ #endif /* _TRACE_HW_EVENT_MC_H */ /* This part must be outside protection */ From d33ae98de5e8f418025f0959bfb93b649c623a14 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 5 May 2026 17:53:45 +0530 Subject: [PATCH 1092/1330] FROMLIST: ras: aest: Fix shared processor node handling and error log messages Two related fixes for processor nodes with ACPI_AEST_PROC_FLAG_SHARED or ACPI_AEST_PROC_FLAG_GLOBAL set (e.g. cluster L3 cache, DSU): 1. aest_dev_is_oncore() returns true for any PROCESSOR_ERROR_NODE, causing shared processor nodes (which use an SPI) to take the cpuhp/PPI path. cpuhp_setup_state() is called instead of aest_online_dev(), so aest_config_irq() is never called and the hardware IRQ-config register is never programmed. Fix aest_dev_is_oncore() to check irq_is_percpu() on the registered IRQ. Only nodes whose FHI or ERI is a per-CPU PPI take the oncore path, nodes with an SPI take aest_online_dev(). 2. alloc_aest_node_name() uses processor_id for the node name of all processor nodes. Shared/global nodes have processor_id=0 (the field is unused when SHARED/GLOBAL is set), so every shared node and the per-PE node for CPU 0 both got the name "processor.0", making error logs ambiguous. For shared/global nodes, build the name as "processor.." (e.g. "processor.cache.1") so each node has a unique, meaningful identifier. Per-PE nodes keep the original "processor." form. Also add proc_flags to struct aest_event so aest_print() can distinguish shared from per-PE nodes and print an appropriate message. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-1-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda (cherry picked from commit 3a8e45a9473d4fe10deb0aed6dcddd5459364d93) --- drivers/ras/aest/aest-core.c | 54 +++++++++++++++++++++++++++++++++--- drivers/ras/aest/aest.h | 15 +++++++++- 2 files changed, 64 insertions(+), 5 deletions(-) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 6a2d84b47721b..b4f4c975da1da 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -49,7 +49,19 @@ static void aest_print(struct aest_event *event) switch (event->type) { case ACPI_AEST_PROCESSOR_ERROR_NODE: - pr_err("%s Error from CPU%d\n", pfx_seq, event->id0); + /* + * For shared/global nodes (e.g. cluster L3 cache, DSU), + * id0 is the CPU that handled the interrupt — not the error + * source itself. The node_name already identifies the resource + * (e.g. "processor.cache.1"). Print a distinct message so the + * log is not confused with a per-PE CPU error. + */ + if (event->proc_flags & + (ACPI_AEST_PROC_FLAG_SHARED | ACPI_AEST_PROC_FLAG_GLOBAL)) + pr_err("%s Error from shared processor resource (interrupt handled on CPU%d)\n", + pfx_seq, event->id0); + else + pr_err("%s Error from CPU%d\n", pfx_seq, event->id0); break; case ACPI_AEST_MEMORY_ERROR_NODE: pr_err("%s Error from memory at SRAT proximity domain %#x\n", @@ -133,6 +145,7 @@ static void init_aest_event(struct aest_event *event, info->processor->processor_id); event->id1 = info->processor->resource_type; + event->proc_flags = info->processor->flags; break; case ACPI_AEST_MEMORY_ERROR_NODE: event->id0 = info->memory->srat_proximity_domain; @@ -175,6 +188,7 @@ static int aest_node_gen_pool_add(struct aest_device *adev, if (!event) return -ENOMEM; + memset(event, 0, sizeof(*event)); init_aest_event(event, record, regs); llist_add(&event->llnode, &adev->event_list); @@ -730,9 +744,41 @@ static char *alloc_aest_node_name(struct aest_node *node) switch (node->type) { case ACPI_AEST_PROCESSOR_ERROR_NODE: - name = devm_kasprintf(node->adev->dev, GFP_KERNEL, "%s.%d", - aest_node_name[node->type], - node->info->processor->processor_id); + /* + * Shared/global processor nodes (e.g. cluster L3 cache, DSU) + * have processor_id=0 and use smp_processor_id() at error-log + * time — using processor_id in the name would produce the same + * "processor.0" string for every shared node and every CPU0 + * per-PE node, making logs ambiguous. + * + * For shared/global nodes, build the name from the resource + * type and the device id so each node gets a unique, meaningful + * name (e.g. "processor.cache.1", "processor.tlb.2"). + * + * For per-PE nodes, keep the original "processor." form. + */ + if (node->info->processor->flags & + (ACPI_AEST_PROC_FLAG_SHARED | ACPI_AEST_PROC_FLAG_GLOBAL)) { + static const char *const res_name[] = { + [ACPI_AEST_CACHE_RESOURCE] = "cache", + [ACPI_AEST_TLB_RESOURCE] = "tlb", + [ACPI_AEST_GENERIC_RESOURCE] = "generic", + }; + u8 rtype = node->info->processor->resource_type; + const char *rstr = (rtype < ARRAY_SIZE(res_name) && + res_name[rtype]) ? res_name[rtype] : "unknown"; + + name = devm_kasprintf(node->adev->dev, GFP_KERNEL, + "%s.%s.%d", + aest_node_name[node->type], + rstr, + node->adev->id); + } else { + name = devm_kasprintf(node->adev->dev, GFP_KERNEL, + "%s.%d", + aest_node_name[node->type], + node->info->processor->processor_id); + } break; case ACPI_AEST_MEMORY_ERROR_NODE: case ACPI_AEST_SMMU_ERROR_NODE: diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 9d67d79eb4a2c..9704af97fee89 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -8,6 +8,7 @@ #include #include #include +#include #define MAX_GSI_PER_NODE 2 #define DEFAULT_CE_THRESHOLD 1 @@ -94,6 +95,8 @@ struct aest_event { /* Vendor node : hardware ID. */ char *hid; u32 index; + /* Processor node: ACPI_AEST_PROC_FLAG_* bitmask (SHARED/GLOBAL) */ + u8 proc_flags; u64 ce_threshold; int addressing_mode; struct ras_ext_regs regs; @@ -387,7 +390,17 @@ static inline void aest_sync(struct aest_node *node) static inline bool aest_dev_is_oncore(struct aest_device *adev) { - return adev->type == ACPI_AEST_PROCESSOR_ERROR_NODE; + /* + * A processor node is "on-core" (uses PPI + cpuhp) only when its + * interrupt is a per-CPU PPI. A shared processor node (e.g. cluster + * L3 cache, DSU) uses an SPI and must follow the non-oncore path + * (aest_online_dev) so that aest_config_irq and aest_online_dev are + * called instead of cpuhp_setup_state. + */ + if (adev->type != ACPI_AEST_PROCESSOR_ERROR_NODE) + return false; + return irq_is_percpu(adev->irq[ACPI_AEST_NODE_FAULT_HANDLING]) || + irq_is_percpu(adev->irq[ACPI_AEST_NODE_ERROR_RECOVERY]); } static inline int default_errgsr_mapping(int errgsr_bit) From 995d2dd4febcb95165c8f89fc7fcb8eb785293b2 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 5 May 2026 17:53:46 +0530 Subject: [PATCH 1093/1330] FROMLIST: ras: aest: Fix CE/UE error counts not incrementing in debugfs The error counts visible under: /sys/kernel/debug/aest//processor//err_count always reported zero, even though corrected errors (CEs) were being serviced by the interrupt handler. aest_oncore_dev_init_debugfs() sets up per CPU debugfs entries but wired them up incorrectly in two places: - this_cpu_ptr(adev->adev_oncore) was used inside for_each_possible_cpu(). This always selects the slot for the CPU executing the init code, so all debugfs files ended up referencing the same per CPU aest_device instance instead of the CPU indicated by the loop variable. - The code referenced adev->nodes[i], i.e. the template nodes allocated before __setup_ppi, rather than the per-CPU copies at percpu_dev->nodes[i]. The IRQ handler updates CE counters in the per-CPU records created by __setup_ppi, the template records are never touched at runtime, so err_count always read as zero. Fix this by: - Using per_cpu_ptr(adev->adev_oncore, cpu) when iterating over CPUs. Wiring debugfs files to percpu_dev->nodes[i] so counters reflect the data updated by the IRQ handler. - Using adev->nodes[i].name for debugfs directory names. The per-CPU node receives name via a shallow memcpy and is not the authoritative source. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-2-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda (cherry picked from commit 8e82ad6656396ea34341195d9cc0760864eb9884) --- drivers/ras/aest/aest-sysfs.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c index 66e9c1103f996..f710503e4d74a 100644 --- a/drivers/ras/aest/aest-sysfs.c +++ b/drivers/ras/aest/aest-sysfs.c @@ -189,16 +189,23 @@ aest_oncore_dev_init_debugfs(struct aest_device *adev) char name[16]; for_each_possible_cpu(cpu) { - percpu_dev = this_cpu_ptr(adev->adev_oncore); + percpu_dev = per_cpu_ptr(adev->adev_oncore, cpu); - snprintf(name, sizeof(name), "processor%u%u", cpu); + snprintf(name, sizeof(name), "processor%u", cpu); percpu_dev->debugfs = debugfs_create_dir(name, adev->debugfs); for (i = 0; i < adev->node_cnt; i++) { - node = &adev->nodes[i]; - - node->debugfs = debugfs_create_dir(node->name, - percpu_dev->debugfs); + node = &percpu_dev->nodes[i]; + + /* + * Use adev->nodes[i].name (the original) rather than + * node->name from the per-CPU copy. The per-CPU copy + * receives node->name via shallow memcpy in __setup_ppi; + * the original is the authoritative, guaranteed-valid + * string. + */ + node->debugfs = debugfs_create_dir(adev->nodes[i].name, + percpu_dev->debugfs); aest_node_init_debugfs(node); } } From a8519714a28a06cca8bb9f58cf12aea3e3ba751c Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 5 May 2026 17:53:47 +0530 Subject: [PATCH 1094/1330] FROMLIST: ras: aest: Skip unimplemented records in debugfs The record_implemented bitmap uses the same semantics as the rest of the driver: a SET bit means the record is NOT implemented (skip it), a CLEAR bit means the record IS implemented (process it). aest_node_init_debugfs() and aest_node_err_count_show() were iterating all record_count records unconditionally, creating debugfs entries and accumulating error counts for unimplemented records too. Fix both functions to skip records where the corresponding bit is set in node->record_implemented, consistent with how aest_node_foreach_record() handles the same bitmap. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-3-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda (cherry picked from commit 66ff7ded0f7e818f5b39d4f2b680ec41d2f3c658) --- drivers/ras/aest/aest-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c index f710503e4d74a..b36190bb3b3e4 100644 --- a/drivers/ras/aest/aest-sysfs.c +++ b/drivers/ras/aest/aest-sysfs.c @@ -52,7 +52,8 @@ static int aest_node_err_count_show(struct seq_file *m, void *data) int i; for (i = 0; i < node->record_count; i++) - aest_error_count(&node->records[i], &count); + if (!test_bit(i, node->record_implemented)) + aest_error_count(&node->records[i], &count); seq_printf(m, "CE: %llu\n" "DE: %llu\n" @@ -174,8 +175,11 @@ aest_node_init_debugfs(struct aest_node *node) record = &node->records[i]; if (!record->name) continue; + /* Skip records not implemented on this node. */ + if (test_bit(i, node->record_implemented)) + continue; record->debugfs = debugfs_create_dir(record->name, - node->debugfs); + node->debugfs); aest_record_init_debugfs(record); } } From 9328af446c7cac6e748882d8d184d00315b05d44 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 5 May 2026 17:53:48 +0530 Subject: [PATCH 1095/1330] FROMLIST: ras: aest: Add panic_on_ue module parameter The driver unconditionally calls panic() whenever an unrecoverable, uncontainable UE (UET_UC or UET_UEU) is detected. There is no way for the user to suppress this behaviour, which makes it difficult to test UE injection or to run in environments where a kernel panic on every UE is undesirable. Add a module parameter `aest_panic_on_ue` When set to 0 the driver logs the UE and continues instead of panicking. Usage: # Boot time (kernel cmdline) aest.aest_panic_on_ue=0 # Runtime echo 0 > /sys/module/aest/parameters/aest_panic_on_ue Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-4-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda (cherry picked from commit 8c588f197bbc45769b100c1ce9bc739b379774c8) --- drivers/ras/aest/aest-core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index b4f4c975da1da..9ce782a66edfc 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -22,6 +22,11 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); #undef pr_fmt #define pr_fmt(fmt) "AEST: " fmt +static bool aest_panic_on_ue; +module_param(aest_panic_on_ue, bool, 0644); +MODULE_PARM_DESC(aest_panic_on_ue, + "Panic on unrecoverable error: 0=off 1=on (default: 1)"); + #ifdef CONFIG_DEBUG_FS struct dentry *aest_debugfs; #endif @@ -342,9 +347,11 @@ void aest_proc_record(struct aest_record *record, void *data, bool fake) aest_record_info( record, "Simulated error! Skip panic due to fault injection\n"); - else + else if (aest_panic_on_ue) aest_panic(record, ®s, "AEST: unrecoverable error encountered"); + else + aest_record_err(record, "UE detected, panic suppressed\n"); } aest_log(record, ®s); From 078812cecb9d923bf2ec722dec77e93cce0e9cac Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 5 May 2026 17:53:49 +0530 Subject: [PATCH 1096/1330] FROMLIST: dt-bindings: arm: ras: Introduce bindings for ARM AEST The Arm Error Source Table (AEST) specification describes how firmware exposes RAS error source topology to the operating system. On ACPI systems this information is provided via the AEST ACPI table. Introduce Device Tree bindings that provide an equivalent description of AEST error sources for DT-based platforms. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-5-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda (cherry picked from commit 2f3c8da0cfff461ff2f9cb38fad5db33286b2590) --- .../devicetree/bindings/arm/arm,aest.yaml | 406 ++++++++++++++++++ include/dt-bindings/arm/aest.h | 43 ++ 2 files changed, 449 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,aest.yaml create mode 100644 include/dt-bindings/arm/aest.h diff --git a/Documentation/devicetree/bindings/arm/arm,aest.yaml b/Documentation/devicetree/bindings/arm/arm,aest.yaml new file mode 100644 index 0000000000000..7809a0d382703 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,aest.yaml @@ -0,0 +1,406 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,aest.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Error Source Table (AEST) + +maintainers: + - Umang Chheda + +description: + The Arm Error Source Table (AEST) describes RAS error sources and their + register interfaces. Each error source exposes one or more error records + through either system registers or a memory-mapped register window, and + may signal errors via interrupts. The top-level node acts as a container + for one or more child nodes, each describing a single AEST error source. + Refer to the Arm AEST specification (DEN0085 / DDI 0587B) for details. + Flag bit constants for use in DT source files are defined in + . + +properties: + compatible: + const: arm,aest + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +required: + - compatible + +additionalProperties: false + +patternProperties: + "^aest-[a-z0-9-]+(@[0-9a-f]+)?$": + type: object + description: + An AEST error source node describing one error source defined by + the Arm AEST specification. + + properties: + compatible: + description: + Identifies the type of AEST error source. Each value corresponds to + a distinct error source class defined by the Arm AEST specification. + arm,aest-proxy represents a proxy error source that forwards errors + from another error source. + enum: + - arm,aest-processor + - arm,aest-memory + - arm,aest-smmu + - arm,aest-gic + - arm,aest-pcie + - arm,aest-vendor + - arm,aest-proxy + + reg: + description: + Register ranges for the error source. Absence of reg implies + system-register access (interface type 0). A single range implies + memory-mapped access (interface type 1). Two ranges imply + single-record memory-mapped access (interface type 2). + minItems: 1 + maxItems: 4 + + reg-names: + description: + Names for the register ranges. The base error-record window is + unnamed (or first entry). Optional named ranges provide access to + the fault-injection, error-group, and interrupt-config register + windows defined by the AEST specification. + minItems: 1 + maxItems: 4 + items: + enum: + - fault-inject + - err-group + - irq-config + + interrupts: + description: Interrupts associated with the error source. + minItems: 1 + maxItems: 2 + + interrupt-names: + description: Names of the interrupts associated with the error source. + minItems: 1 + maxItems: 2 + items: + enum: + - fhi + - eri + + arm,fhi-flags: + description: + Bitmask of flags for the fault-handling interrupt (FHI), as defined + in the AEST node interrupt structure flags field. Constants are + defined in - AEST_IRQ_MODE_LEVEL (0), + AEST_IRQ_MODE_EDGE (1). + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,eri-flags: + description: + Bitmask of flags for the error-recovery interrupt (ERI), as defined + in the AEST node interrupt structure flags field. Constants are + defined in . + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,interface-flags: + description: | + Bitmask of interface flags for the error source, as defined in the + AEST node interface flags field. Constants are defined in + : + AEST_XFACE_SHARED (bit 0) - shared error source, + AEST_XFACE_CLEAR_MISC (bit 1) - clear MISC registers on error, + AEST_XFACE_ERROR_DEVICE (bit 2) - error node device present, + AEST_XFACE_AFFINITY (bit 3) - affinity information valid, + AEST_XFACE_ERROR_GROUP (bit 4) - error group register window present, + AEST_XFACE_FAULT_INJECT (bit 5) - fault injection register window present, + AEST_XFACE_INT_CONFIG (bit 6) - interrupt config register window present. + For system-register interface nodes (no reg property), only + AEST_XFACE_CLEAR_MISC is meaningful; the MMIO window flags + (AEST_XFACE_ERROR_GROUP, AEST_XFACE_FAULT_INJECT, + AEST_XFACE_INT_CONFIG) have no effect without a base address. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,group-format: + description: | + Page-granularity of the error record group register window, which + determines the MMIO mapping size, the number of ERRGSR registers, + and the width of the record-implemented and status-reporting bitmaps. + Constants are defined in : + AEST_GROUP_FORMAT_4K (0) - 4K window, 1 ERRGSR, up to 64 records, + AEST_GROUP_FORMAT_16K (1) - 16K window, 4 ERRGSRs, up to 256 records, + AEST_GROUP_FORMAT_64K (2) - 64K window, 14 ERRGSRs, up to 896 records. + Required for memory-mapped nodes (reg present) where it controls + the ioremap size and ERRGSR layout. For system-register nodes + (no reg property) this property is optional and defaults to + AEST_GROUP_FORMAT_4K. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + arm,num-records: + description: Number of error records implemented by this error source. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,record-impl: + description: + Bitmap of implemented error records within this error source. Bit N + set to 0 means error record N is implemented and must be polled. + $ref: /schemas/types.yaml#/definitions/uint64-array + + arm,status-reporting: + description: + Bitmap indicating which error records support status reporting via + the ERRGSR register. Bit N set to 1 means record N does not report + through ERRGSR and must be polled explicitly. + $ref: /schemas/types.yaml#/definitions/uint64-array + + arm,addressing-mode: + description: + Bitmap indicating the address type reported in ERR_ADDR for each + error record. Bit N set to 0 means record N reports System Physical + Addresses (SPA); bit N set to 1 means record N reports node-specific + Logical Addresses (LA) that require OS translation to SPA. + $ref: /schemas/types.yaml#/definitions/uint64-array + + arm,processor-flags: + description: + Bitmask indicating the scope of a processor error source, as defined + in the AEST processor node flags field. Constants are defined in + - AEST_PROC_GLOBAL (bit 0), + AEST_PROC_SHARED (bit 1). + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,resource-type: + description: | + Type of processor resource associated with this error source. + Constants are defined in : + AEST_RESOURCE_CACHE (0), + AEST_RESOURCE_TLB (1), + AEST_RESOURCE_GENERIC (2). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + arm,cache-ref: + description: + Phandle to the cache node associated with this processor error source. + $ref: /schemas/types.yaml#/definitions/phandle + + arm,tlb-level: + description: TLB level identifier for this processor TLB error source. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,resource-ref: + description: + Generic resource reference identifier for this processor error source. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,proximity-domain: + description: + SRAT proximity domain of the memory node associated with this error + source. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,smmu-ref: + description: + Phandle to the SMMU node in the IORT associated with this error + source. + $ref: /schemas/types.yaml#/definitions/phandle + + arm,smmu-subcomponent: + description: + SMMU subcomponent reference identifier for this error source, as + defined in the AEST SMMU node structure. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,gic-type: + description: | + GIC component type for this error source, as defined in the AEST GIC + node structure. Constants are defined in : + AEST_GIC_CPU (0), + AEST_GIC_DISTRIBUTOR (1), + AEST_GIC_REDISTRIBUTOR (2), + AEST_GIC_ITS (3). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + arm,gic-instance: + description: + GIC instance identifier for this error source, used to distinguish + multiple instances of the same GIC component type. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,pcie-segment: + description: + PCI segment number of the PCIe root port associated with this error + source, corresponding to the IORT node reference. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,vendor-hid: + description: + 8-character ACPI Hardware ID string identifying the vendor error + source, as defined in the AEST vendor node structure. + $ref: /schemas/types.yaml#/definitions/string + + arm,vendor-uid: + description: + ACPI unique instance identifier for this vendor error source, used + to distinguish multiple instances with the same hardware ID. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - compatible + - arm,num-records + + allOf: + - if: + required: + - reg + then: + required: + - arm,group-format + - if: + properties: + compatible: + contains: + const: arm,aest-processor + then: + properties: + arm,processor-flags: {} + arm,resource-type: {} + arm,cache-ref: {} + arm,tlb-level: {} + arm,resource-ref: {} + else: + properties: + arm,processor-flags: false + arm,resource-type: false + arm,cache-ref: false + arm,tlb-level: false + arm,resource-ref: false + + - if: + properties: + compatible: + contains: + const: arm,aest-memory + then: + required: + - arm,proximity-domain + properties: + arm,proximity-domain: {} + else: + properties: + arm,proximity-domain: false + + - if: + properties: + compatible: + contains: + const: arm,aest-smmu + then: + required: + - arm,smmu-ref + properties: + arm,smmu-ref: {} + arm,smmu-subcomponent: {} + else: + properties: + arm,smmu-ref: false + arm,smmu-subcomponent: false + + - if: + properties: + compatible: + contains: + const: arm,aest-gic + then: + properties: + arm,gic-type: {} + arm,gic-instance: {} + else: + properties: + arm,gic-type: false + arm,gic-instance: false + + - if: + properties: + compatible: + contains: + const: arm,aest-pcie + then: + required: + - arm,pcie-segment + properties: + arm,pcie-segment: {} + else: + properties: + arm,pcie-segment: false + + - if: + properties: + compatible: + contains: + const: arm,aest-vendor + then: + required: + - arm,vendor-hid + properties: + arm,vendor-hid: {} + arm,vendor-uid: {} + else: + properties: + arm,vendor-hid: false + arm,vendor-uid: false + + unevaluatedProperties: false + +examples: + - | + #include + #include + + aest { + compatible = "arm,aest"; + #address-cells = <2>; + #size-cells = <2>; + + /* System-register based processor error source (no reg property) */ + aest-processor-0 { + compatible = "arm,aest-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x3>; + arm,status-reporting = /bits/ 64 <0x0>; + arm,addressing-mode = /bits/ 64 <0x0>; + arm,processor-flags = ; + arm,resource-type = ; + interrupts = ; + interrupt-names = "fhi"; + }; + + /* Memory-mapped memory controller error source */ + aest-memory-0@50010000 { + compatible = "arm,aest-memory"; + reg = <0x0 0x50010000 0x0 0x1000>, + <0x0 0x50011000 0x0 0x1000>, + <0x0 0x50012000 0x0 0x1000>; + reg-names = "err-group", "fault-inject", "irq-config"; + arm,group-format = ; + arm,num-records = <4>; + arm,record-impl = /bits/ 64 <0xf>; + arm,status-reporting = /bits/ 64 <0x0>; + arm,addressing-mode = /bits/ 64 <0x0>; + arm,interface-flags = ; + arm,proximity-domain = <0>; + interrupts = , + ; + interrupt-names = "fhi", "eri"; + }; + }; diff --git a/include/dt-bindings/arm/aest.h b/include/dt-bindings/arm/aest.h new file mode 100644 index 0000000000000..43679314e98e8 --- /dev/null +++ b/include/dt-bindings/arm/aest.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for the Arm Error Source Table (AEST) + * DT binding (Documentation/devicetree/bindings/arm/arm,aest.yaml). + */ + +#ifndef _DT_BINDINGS_ARM_AEST_H +#define _DT_BINDINGS_ARM_AEST_H + +/* arm,interface-flags - AEST node interface flags field */ +#define AEST_XFACE_SHARED 1 +#define AEST_XFACE_CLEAR_MISC 2 +#define AEST_XFACE_ERROR_DEVICE 4 +#define AEST_XFACE_AFFINITY 8 +#define AEST_XFACE_ERROR_GROUP 16 +#define AEST_XFACE_FAULT_INJECT 32 +#define AEST_XFACE_INT_CONFIG 64 + +/* arm,fhi-flags / arm,eri-flags - AEST node interrupt flags field */ +#define AEST_IRQ_MODE_LEVEL 0 +#define AEST_IRQ_MODE_EDGE 1 + +/* arm,processor-flags - AEST processor node flags field */ +#define AEST_PROC_GLOBAL 1 +#define AEST_PROC_SHARED 2 + +/* arm,group-format - error record group register window page size */ +#define AEST_GROUP_FORMAT_4K 0 +#define AEST_GROUP_FORMAT_16K 1 +#define AEST_GROUP_FORMAT_64K 2 + +/* arm,resource-type - processor resource type */ +#define AEST_RESOURCE_CACHE 0 +#define AEST_RESOURCE_TLB 1 +#define AEST_RESOURCE_GENERIC 2 + +/* arm,gic-type - GIC component type */ +#define AEST_GIC_CPU 0 +#define AEST_GIC_DISTRIBUTOR 1 +#define AEST_GIC_REDISTRIBUTOR 2 +#define AEST_GIC_ITS 3 + +#endif /* _DT_BINDINGS_ARM_AEST_H */ From dedc5175f66d80792fa88bb46d5b87aa5f4f1658 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 5 May 2026 17:53:50 +0530 Subject: [PATCH 1097/1330] FROMLIST: ras: aest: Add DT frontend for ARM AEST RAS error sources Add a Device Tree frontend for the Arm AEST RAS framework, allowing the existing AEST core driver to be used on DT-only systems. The DT frontend parses the "arm,aest" Device Tree hierarchy and populates the same internal structures as the ACPI-based implementation. It is initialized at the same layer as ACPI and is mutually exclusive with it, ensuring identical behaviour regardless of the firmware interface in use. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-6-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda (cherry picked from commit 6aff3e676829cbb71b8e6a0c9df504a45ff63955) --- drivers/ras/aest/Kconfig | 15 +- drivers/ras/aest/Makefile | 2 + drivers/ras/aest/aest-of.c | 673 +++++++++++++++++++++++++++++++++++++ 3 files changed, 688 insertions(+), 2 deletions(-) create mode 100644 drivers/ras/aest/aest-of.c diff --git a/drivers/ras/aest/Kconfig b/drivers/ras/aest/Kconfig index 0b09a5d5acce3..ca034255faddf 100644 --- a/drivers/ras/aest/Kconfig +++ b/drivers/ras/aest/Kconfig @@ -7,11 +7,22 @@ config AEST tristate "ARM AEST Driver" - depends on ACPI_AEST && RAS - + depends on ACPI_AEST || OF_AEST + depends on RAS help The Arm Error Source Table (AEST) provides details on ACPI extensions that enable kernel-first handling of errors in a system that supports the Armv8 RAS extensions. If set, the kernel will report and log hardware errors. + +config OF_AEST + bool "ARM Error Source Table DT Support" + depends on ARM64_RAS_EXTN && OF + help + Enable support for discovering ARM RAS error sources using the + Device Tree based Arm Error Source Table (AEST) specification. + This allows the kernel to enumerate and manage hardware error + reporting blocks described in firmware for ARMv8 and later + systems. Select this option if your platform describes AEST + nodes in Device Tree and relies on RAS error handling. diff --git a/drivers/ras/aest/Makefile b/drivers/ras/aest/Makefile index e5a45fde6d362..2997952901c05 100644 --- a/drivers/ras/aest/Makefile +++ b/drivers/ras/aest/Makefile @@ -6,3 +6,5 @@ aest-y := aest-core.o aest-y += aest-sysfs.o aest-y += aest-inject.o aest-y += aest-cmn.o + +obj-$(CONFIG_OF_AEST) += aest-of.o diff --git a/drivers/ras/aest/aest-of.c b/drivers/ras/aest/aest-of.c new file mode 100644 index 0000000000000..939db2c417427 --- /dev/null +++ b/drivers/ras/aest/aest-of.c @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "DT AEST: " fmt + +struct dt_aest_priv { + struct xarray aest_array; + u32 node_id; +}; + +static const struct of_device_id dt_aest_child_match[] = { + { .compatible = "arm,aest-processor", .data = (void *)ACPI_AEST_PROCESSOR_ERROR_NODE }, + { .compatible = "arm,aest-memory", .data = (void *)ACPI_AEST_MEMORY_ERROR_NODE }, + { .compatible = "arm,aest-smmu", .data = (void *)ACPI_AEST_SMMU_ERROR_NODE }, + { .compatible = "arm,aest-vendor", .data = (void *)ACPI_AEST_VENDOR_ERROR_NODE }, + { .compatible = "arm,aest-gic", .data = (void *)ACPI_AEST_GIC_ERROR_NODE }, + { .compatible = "arm,aest-pcie", .data = (void *)ACPI_AEST_PCIE_ERROR_NODE }, + { .compatible = "arm,aest-proxy", .data = (void *)ACPI_AEST_PROXY_ERROR_NODE }, + { } +}; + +static int dt_aest_node_type(struct device_node *np) +{ + const struct of_device_id *match; + + match = of_match_node(dt_aest_child_match, np); + if (!match) { + pr_warn("unknown compatible for %pOF\n", np); + return -EINVAL; + } + return (int)(uintptr_t)match->data; +} + +static struct aest_hnode *dt_aest_alloc_hnode(int node_type, u32 id) +{ + struct aest_hnode *ahnode; + + ahnode = kzalloc_obj(*ahnode, GFP_KERNEL); + if (!ahnode) + return NULL; + + INIT_LIST_HEAD(&ahnode->list); + ahnode->count = 0; + ahnode->id = id; + ahnode->type = node_type; + return ahnode; +} + +static int dt_aest_build_interface(struct device_node *np, + struct acpi_aest_node *anode) +{ + struct acpi_aest_node_interface_header *hdr; + struct acpi_aest_node_interface_common *common; + struct resource res; + struct resource named_res; + u32 gfmt = 0, flags = 0, nrec = 1; + u32 itype; + int ret; + size_t body_sz; + + /* + * Deduce interface type from the presence and count of reg entries: + * no reg -> system-register access (type 0) + * 1 range -> memory-mapped access (type 1) + * 2+ ranges -> single-record MMIO (type 2) + */ + if (!of_property_present(np, "reg")) + itype = ACPI_AEST_NODE_SYSTEM_REGISTER; + else if (of_property_count_elems_of_size(np, "reg", sizeof(u32)) <= + (of_n_addr_cells(np) + of_n_size_cells(np))) + itype = ACPI_AEST_NODE_MEMORY_MAPPED; + else + itype = ACPI_AEST_NODE_SINGLE_RECORD_MEMORY_MAPPED; + + of_property_read_u32(np, "arm,group-format", &gfmt); + of_property_read_u32(np, "arm,interface-flags", &flags); + of_property_read_u32(np, "arm,num-records", &nrec); + + switch (gfmt) { + case ACPI_AEST_NODE_GROUP_FORMAT_16K: + body_sz = sizeof(struct acpi_aest_node_interface_16k); + break; + case ACPI_AEST_NODE_GROUP_FORMAT_64K: + body_sz = sizeof(struct acpi_aest_node_interface_64k); + break; + default: + body_sz = sizeof(struct acpi_aest_node_interface_4k); + break; + } + + hdr = kzalloc(sizeof(*hdr) + body_sz, GFP_KERNEL); + if (!hdr) + return -ENOMEM; + + /* Fill header */ + hdr->type = (u8)itype; + hdr->group_format = (u8)gfmt; + hdr->flags = flags; + hdr->error_record_count = nrec; + hdr->error_record_index = 0; + + if (itype != ACPI_AEST_NODE_SYSTEM_REGISTER) { + ret = of_address_to_resource(np, 0, &res); + if (ret) { + pr_err("node %pOF: missing 'reg' for MMIO interface\n", np); + kfree(hdr); + return ret; + } + hdr->address = res.start; + } + + switch (gfmt) { + case ACPI_AEST_NODE_GROUP_FORMAT_4K: { + struct acpi_aest_node_interface_4k *b = + (struct acpi_aest_node_interface_4k *)(hdr + 1); + of_property_read_u64(np, "arm,record-impl", + &b->error_record_implemented); + of_property_read_u64(np, "arm,status-reporting", + &b->error_status_reporting); + of_property_read_u64(np, "arm,addressing-mode", + &b->addressing_mode); + common = &b->common; + anode->record_implemented = + (unsigned long *)&b->error_record_implemented; + anode->status_reporting = + (unsigned long *)&b->error_status_reporting; + anode->addressing_mode = + (unsigned long *)&b->addressing_mode; + break; + } + case ACPI_AEST_NODE_GROUP_FORMAT_16K: { + struct acpi_aest_node_interface_16k *b = + (struct acpi_aest_node_interface_16k *)(hdr + 1); + of_property_read_u64_array(np, "arm,record-impl", + b->error_record_implemented, 4); + of_property_read_u64_array(np, "arm,status-reporting", + b->error_status_reporting, 4); + of_property_read_u64_array(np, "arm,addressing-mode", + b->addressing_mode, 4); + common = &b->common; + anode->record_implemented = + (unsigned long *)b->error_record_implemented; + anode->status_reporting = + (unsigned long *)b->error_status_reporting; + anode->addressing_mode = + (unsigned long *)b->addressing_mode; + break; + } + case ACPI_AEST_NODE_GROUP_FORMAT_64K: { + struct acpi_aest_node_interface_64k *b = + (struct acpi_aest_node_interface_64k *)(hdr + 1); + of_property_read_u64_array(np, "arm,record-impl", + b->error_record_implemented, 14); + of_property_read_u64_array(np, "arm,status-reporting", + b->error_status_reporting, 14); + of_property_read_u64_array(np, "arm,addressing-mode", + b->addressing_mode, 14); + common = &b->common; + anode->record_implemented = + (unsigned long *)b->error_record_implemented; + anode->status_reporting = + (unsigned long *)b->error_status_reporting; + anode->addressing_mode = + (unsigned long *)b->addressing_mode; + break; + } + default: + pr_err("node %pOF: unsupported group-format %u\n", np, gfmt); + kfree(hdr); + return -EINVAL; + } + + if (!of_address_to_resource(np, of_property_match_string( + np, "reg-names", "fault-inject"), &named_res)) + common->fault_inject_register_base = named_res.start; + + if (!of_address_to_resource(np, of_property_match_string( + np, "reg-names", "err-group"), &named_res)) + common->error_group_register_base = named_res.start; + + if (!of_address_to_resource(np, of_property_match_string( + np, "reg-names", "irq-config"), &named_res)) + common->interrupt_config_register_base = named_res.start; + + anode->interface_hdr = hdr; + anode->common = common; + + return 0; +} + +static int dt_aest_build_interrupt(struct device_node *np, + struct acpi_aest_node *anode) +{ + struct acpi_aest_node_interrupt_v2 *irq_arr; + int fhi_irq, eri_irq, count = 0; + u32 fhi_flags = 0, eri_flags = 0; + + of_property_read_u32(np, "arm,fhi-flags", &fhi_flags); + of_property_read_u32(np, "arm,eri-flags", &eri_flags); + + fhi_irq = of_irq_get_byname(np, "fhi"); + if (fhi_irq == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (fhi_irq < 0 && fhi_irq != -EINVAL) { + const char *name = NULL; + + of_property_read_string(np, "interrupt-names", &name); + + pr_warn("node %pOF: failed to map FHI IRQ: %d (interrupt-names[0]=\"%s\", want \"%s\")\n", + np, fhi_irq, name ?: "", "fhi"); + } + eri_irq = of_irq_get_byname(np, "eri"); + if (eri_irq == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (eri_irq < 0 && eri_irq != -EINVAL) { + const char *name = NULL; + + of_property_read_string_index(np, "interrupt-names", 1, &name); + + pr_warn("node %pOF: failed to map ERI IRQ: %d (interrupt-names[1]=\"%s\", want \"%s\")\n", + np, eri_irq, name ?: "", "eri"); + } + + if (fhi_irq > 0) + count++; + if (eri_irq > 0) + count++; + + if (!count) { + anode->interrupt = NULL; + anode->interrupt_count = 0; + return 0; + } + + irq_arr = kcalloc(count, sizeof(*irq_arr), GFP_KERNEL); + if (!irq_arr) + return -ENOMEM; + + count = 0; + if (fhi_irq > 0) { + irq_arr[count].gsiv = fhi_irq; + irq_arr[count].flags = AEST_INTERRUPT_MODE | fhi_flags; + irq_arr[count].type = ACPI_AEST_NODE_FAULT_HANDLING; + count++; + } + if (eri_irq > 0) { + irq_arr[count].gsiv = eri_irq; + irq_arr[count].flags = eri_flags; + irq_arr[count].type = ACPI_AEST_NODE_ERROR_RECOVERY; + count++; + } + + anode->interrupt = irq_arr; + anode->interrupt_count = count; + return 0; +} + +static int dt_aest_build_node_specific(struct device_node *np, + struct acpi_aest_node *anode, + int node_type) +{ + switch (node_type) { + + case ACPI_AEST_PROCESSOR_ERROR_NODE: { + struct acpi_aest_processor *proc; + u32 rtype = 0, pflags = 0; + + proc = kzalloc_obj(*proc, GFP_KERNEL); + if (!proc) + return -ENOMEM; + + of_property_read_u32(np, "arm,resource-type", &rtype); + of_property_read_u32(np, "arm,processor-flags", &pflags); + + proc->resource_type = (u8)rtype; + proc->flags = (u8)pflags; + + /* Processor cache/TLB/generic sub-structure */ + switch (rtype) { + case ACPI_AEST_CACHE_RESOURCE: { + struct acpi_aest_processor_cache *c; + struct device_node *cache_np; + + c = kzalloc_obj(*c, GFP_KERNEL); + if (!c) { + kfree(proc); + return -ENOMEM; + } + + cache_np = of_parse_phandle(np, "arm,cache-ref", 0); + if (cache_np) { + c->cache_reference = cache_np->phandle; + of_node_put(cache_np); + } + anode->cache = c; + break; + } + case ACPI_AEST_TLB_RESOURCE: { + struct acpi_aest_processor_tlb *t; + + t = kzalloc_obj(*t, GFP_KERNEL); + if (!t) { + kfree(proc); + return -ENOMEM; + } + of_property_read_u32(np, "arm,tlb-level", + &t->tlb_level); + anode->tlb = t; + break; + } + default: { + struct acpi_aest_processor_generic *g; + + g = kzalloc_obj(*g, GFP_KERNEL); + if (!g) { + kfree(proc); + return -ENOMEM; + } + of_property_read_u32(np, "arm,resource-ref", + &g->resource); + anode->generic = g; + break; + } + } + anode->processor = proc; + break; + } + + case ACPI_AEST_MEMORY_ERROR_NODE: { + struct acpi_aest_memory *mem; + + mem = kzalloc_obj(*mem, GFP_KERNEL); + + if (!mem) + return -ENOMEM; + of_property_read_u32(np, "arm,proximity-domain", + &mem->srat_proximity_domain); + anode->memory = mem; + break; + } + + case ACPI_AEST_SMMU_ERROR_NODE: { + struct acpi_aest_smmu *smmu; + struct device_node *smmu_np; + + smmu = kzalloc_obj(*smmu, GFP_KERNEL); + + if (!smmu) + return -ENOMEM; + smmu_np = of_parse_phandle(np, "arm,smmu-ref", 0); + if (smmu_np) { + /* Use the DT node offset as the IORT reference */ + smmu->iort_node_reference = smmu_np->phandle; + of_node_put(smmu_np); + } + of_property_read_u32(np, "arm,smmu-subcomponent", + &smmu->subcomponent_reference); + anode->smmu = smmu; + break; + } + + case ACPI_AEST_VENDOR_ERROR_NODE: { + struct acpi_aest_vendor_v2 *vendor; + const char *hid = "ARMHC000"; + + vendor = kzalloc_obj(*vendor, GFP_KERNEL); + + if (!vendor) + return -ENOMEM; + of_property_read_string(np, "arm,vendor-hid", &hid); + strscpy(vendor->acpi_hid, hid, sizeof(vendor->acpi_hid)); + of_property_read_u32(np, "arm,vendor-uid", + &vendor->acpi_uid); + anode->vendor = vendor; + break; + } + + case ACPI_AEST_GIC_ERROR_NODE: { + struct acpi_aest_gic *gic; + + gic = kzalloc_obj(*gic, GFP_KERNEL); + + if (!gic) + return -ENOMEM; + of_property_read_u32(np, "arm,gic-type", + &gic->interface_type); + of_property_read_u32(np, "arm,gic-instance", + &gic->instance_id); + anode->gic = gic; + break; + } + + case ACPI_AEST_PCIE_ERROR_NODE: { + struct acpi_aest_pcie *pcie; + + pcie = kzalloc_obj(*pcie, GFP_KERNEL); + + if (!pcie) + return -ENOMEM; + of_property_read_u32(np, "arm,pcie-segment", + &pcie->iort_node_reference); + anode->pcie = pcie; + break; + } + + case ACPI_AEST_PROXY_ERROR_NODE: + /* No node-specific data for proxy nodes */ + anode->spec_pointer = NULL; + break; + + default: + return -EINVAL; + } + + return 0; +} + +static struct acpi_aest_node * +dt_aest_alloc_anode(struct device_node *np, int node_type) +{ + struct acpi_aest_node *anode; + int ret; + + anode = kzalloc_obj(*anode, GFP_KERNEL); + if (!anode) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&anode->list); + anode->type = node_type; + + ret = dt_aest_build_interface(np, anode); + if (ret) + goto err_free; + + ret = dt_aest_build_node_specific(np, anode, node_type); + if (ret) + goto err_free; + + ret = dt_aest_build_interrupt(np, anode); + if (ret) + goto err_free; + + return anode; + +err_free: + kfree(anode->interface_hdr); + kfree(anode->spec_pointer); + kfree(anode->processor_spec_pointer); + kfree(anode); + return ERR_PTR(ret); +} + +static int dt_aest_init_one_node(struct device_node *np, + struct dt_aest_priv *priv) +{ + int node_type; + struct aest_hnode *ahnode; + struct acpi_aest_node *anode; + + node_type = dt_aest_node_type(np); + if (node_type < 0) { + pr_warn("unknown node type for %pOF, skipping\n", np); + return 0; + } + + ahnode = dt_aest_alloc_hnode(node_type, priv->node_id); + if (!ahnode) + return -ENOMEM; + + anode = dt_aest_alloc_anode(np, node_type); + if (IS_ERR(anode)) { + kfree(ahnode); + return PTR_ERR(anode); + } + + list_add_tail(&anode->list, &ahnode->list); + ahnode->count = 1; + + if (xa_err(xa_store(&priv->aest_array, priv->node_id, + ahnode, GFP_KERNEL))) { + kfree(anode); + kfree(ahnode); + return -ENOMEM; + } + priv->node_id++; + return 0; +} + +static int dt_aest_init_nodes(struct device_node *aest_root, + struct dt_aest_priv *priv) +{ + struct device_node *np; + int ret; + + for_each_available_child_of_node(aest_root, np) { + ret = dt_aest_init_one_node(np, priv); + if (ret) { + pr_err("failed to init node %pOF: %d\n", np, ret); + of_node_put(np); + return ret; + } + } + return 0; +} + +static struct platform_device *dt_aest_alloc_pdev(struct aest_hnode *ahnode, + int index) +{ + struct platform_device *pdev; + struct resource *res; + struct acpi_aest_node *anode; + int ret, size, j; + int irq[AEST_MAX_INTERRUPT_PER_NODE] = { 0 }; + + pdev = platform_device_alloc("AEST", index); + if (!pdev) + return ERR_PTR(-ENOMEM); + + res = kcalloc(ahnode->count + AEST_MAX_INTERRUPT_PER_NODE, + sizeof(*res), GFP_KERNEL); + if (!res) { + platform_device_put(pdev); + return ERR_PTR(-ENOMEM); + } + + j = 0; + list_for_each_entry(anode, &ahnode->list, list) { + if (anode->interface_hdr->type != + ACPI_AEST_NODE_SYSTEM_REGISTER) { + res[j].name = AEST_NODE_NAME; + res[j].start = anode->interface_hdr->address; + + switch (anode->interface_hdr->group_format) { + case ACPI_AEST_NODE_GROUP_FORMAT_4K: + size = 4 * KB; break; + case ACPI_AEST_NODE_GROUP_FORMAT_16K: + size = 16 * KB; break; + case ACPI_AEST_NODE_GROUP_FORMAT_64K: + size = 64 * KB; break; + default: + size = 4 * KB; + } + res[j].end = res[j].start + size - 1; + res[j].flags = IORESOURCE_MEM; + j++; + } + + if (anode->interrupt && anode->interrupt_count > 0) { + int k; + + for (k = 0; k < anode->interrupt_count && + k < AEST_MAX_INTERRUPT_PER_NODE; k++) { + + struct acpi_aest_node_interrupt_v2 *intr = + &anode->interrupt[k]; + int itype = intr->type; + int virq = intr->gsiv; + struct irq_data *irqd; + + if (!virq) + continue; + if (itype >= AEST_MAX_INTERRUPT_PER_NODE) + continue; + if (irq[itype] == virq) + continue; + irq[itype] = virq; + /* + * aest_config_irq() writes intr->gsiv directly + * to the hardware IRQ-config register, so it + * must hold the GIC hardware SPI number, not the + * Linux virtual IRQ. Convert here now that we + * have the virq in hand; the resource still gets + * the virq so devm_request_irq() works correctly. + */ + irqd = irq_get_irq_data(virq); + if (irqd) + intr->gsiv = irqd->hwirq; + + res[j].name = (itype == ACPI_AEST_NODE_FAULT_HANDLING) + ? AEST_FHI_NAME : AEST_ERI_NAME; + res[j].start = virq; + res[j].end = virq; + res[j].flags = IORESOURCE_IRQ; + j++; + } + } + } + + ret = platform_device_add_resources(pdev, res, j); + kfree(res); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(ret); + } + + ret = platform_device_add_data(pdev, &ahnode, sizeof(ahnode)); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(ret); + } + + ret = platform_device_add(pdev); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(ret); + } + + return pdev; +} + +static int dt_aest_alloc_pdevs(struct dt_aest_priv *priv) +{ + struct aest_hnode *ahnode; + unsigned long i; + int ret = 0, index = 0; + + xa_for_each(&priv->aest_array, i, ahnode) { + struct platform_device *pdev = + dt_aest_alloc_pdev(ahnode, index++); + if (IS_ERR(pdev)) { + ret = PTR_ERR(pdev); + pr_err("failed to alloc pdev for node %u: %d\n", + ahnode->id, ret); + break; + } + } + return ret; +} + +static int __init dt_aest_init(void) +{ + struct device_node *aest_root; + struct dt_aest_priv priv = {}; + int ret; + + if (!acpi_disabled) + return 0; + + aest_root = of_find_compatible_node(NULL, NULL, "arm,aest"); + if (!aest_root) + return 0; + + xa_init(&priv.aest_array); + + ret = dt_aest_init_nodes(aest_root, &priv); + of_node_put(aest_root); + if (ret) { + pr_err("failed to init AEST nodes: %d\n", ret); + return ret; + } + + ret = dt_aest_alloc_pdevs(&priv); + if (ret) { + pr_err("failed to alloc AEST pdevs: %d\n", ret); + return ret; + } + + pr_info("registered %u AEST error source(s) from DT\n", priv.node_id); + + return 0; +} +subsys_initcall_sync(dt_aest_init); From f730efe64884939614a2082ea2137dcb839545d3 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 5 May 2026 17:53:52 +0530 Subject: [PATCH 1098/1330] FROMLIST: arm64: dts: qcom: monaco: add AEST error nodes Add AEST RAS error source nodes for the Monaco SoC. The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Link: https://lore.kernel.org/all/20260505-aest-devicetree-support-v1-8-d5d6ffacf0a5@oss.qualcomm.com/ Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda (cherry picked from commit 965645d7f2020b4a265f79d081682ce456e077fc) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 3984252777c45..eb3818d733110 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -29,6 +30,46 @@ #address-cells = <2>; #size-cells = <2>; + aest { + compatible = "arm,aest"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aest-processor-0 { + compatible = "arm,aest-processor"; + arm,num-records = <1>; + arm,record-impl = /bits/ 64 <0x0>; + arm,status-reporting = /bits/ 64 <0x0>; + arm,addressing-mode = /bits/ 64 <0x0>; + arm,processor-flags = ; + interrupts = ; + interrupt-names = "fhi"; + }; + + aest-l3-cluster0 { + compatible = "arm,aest-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x1>; + arm,status-reporting = /bits/ 64 <0x0>; + arm,addressing-mode = /bits/ 64 <0x0>; + arm,processor-flags = ; + interrupts = ; + interrupt-names = "fhi"; + }; + + aest-l3-cluster1 { + compatible = "arm,aest-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x1>; + arm,status-reporting = /bits/ 64 <0x0>; + arm,addressing-mode = /bits/ 64 <0x0>; + arm,processor-flags = ; + interrupts = ; + interrupt-names = "fhi"; + }; + }; + clocks { xo_board_clk: xo-board-clk { compatible = "fixed-clock"; From 54106c85f5faabb16e1f4b9c8c13f3c73b33be52 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Thu, 16 Apr 2026 17:04:48 +0530 Subject: [PATCH 1099/1330] FROMLIST: arm64: dts: qcom: purwa-iot-evk: Update TSENS thermal zone MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Purwa IOT boards support a different thermal junction temperature specification compared to the base Purwa platform due to package level differences. Update the passive trip thresholds to 105°C to align with the higher temperature specification. Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20260416-purwa_high_tj-v1-1-b538f98d42da@oss.qualcomm.com (cherry picked from commit fd53d0e0a90e65cbc71d202b8cf6efaf893789ed) --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index dca57f2db1fe1..2f55f27196f31 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -1345,6 +1345,38 @@ }; }; +&thermal_gpuss_0 { + trips { + trip-point0 { + temperature = <105000>; + }; + }; +}; + +&thermal_gpuss_1 { + trips { + trip-point0 { + temperature = <105000>; + }; + }; +}; + +&thermal_gpuss_2 { + trips { + trip-point0 { + temperature = <105000>; + }; + }; +}; + +&thermal_gpuss_3 { + trips { + trip-point0 { + temperature = <105000>; + }; + }; +}; + &tlmm { edp_reg_en: edp-reg-en-state { pins = "gpio70"; From 7d032a988d13e4cc91a123380289d38f57d9488d Mon Sep 17 00:00:00 2001 From: Ignatius Michael Jihan Date: Fri, 22 May 2026 17:01:49 +0530 Subject: [PATCH 1100/1330] QCLINUX: arm64: dts: qcom: add Purwa CAMX EL2 overlay Add a device tree overlay to enable EL2 boot support for the Purwa platform with CAMX configuration. CRs-Fixed: 4546991 Signed-off-by: Ignatius Michael Jihan (cherry picked from commit 8d6e4e962e7e504e94b8b1a42240ad191d9867bd) --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ arch/arm64/boot/dts/qcom/purwa-camx-el2.dtso | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/purwa-camx-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e8318f2e7a170..39f52181b99b8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -541,6 +541,10 @@ purwa-evk-camx-dtbs := purwa-iot-evk.dtb purwa-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += purwa-evk-camx.dtb +purwa-camx-el2-dtbs := purwa-iot-evk-el2.dtb purwa-evk-camx.dtbo purwa-camx-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += purwa-camx-el2.dtb + qcs5430-fps-camx-dtbs := qcs6490-rb3gen2.dtb qcs5430-fps-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs5430-fps-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/purwa-camx-el2.dtso b/arch/arm64/boot/dts/qcom/purwa-camx-el2.dtso new file mode 100644 index 0000000000000..5584660dbcfd6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-camx-el2.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path = "/soc@0/qcom,cam-icp"; + __overlay__ { + camera-firmware { + iommus = <&apps_smmu 0x1901 0x0>; + }; + }; + }; +}; From 535b78d256f54deeaa3744d12489931b7f7cea19 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Mon, 2 Mar 2026 10:34:46 +0200 Subject: [PATCH 1101/1330] UPSTREAM: phy: qcom: m31-eusb2: Make USB repeater optional A repeater is not required for the PHY to function. On systems with multiple PHY instances connected to a multi-port controller, some PHYs may be unconnected. All PHYs must still probe successfully even without attached repeaters, otherwise the controller probe fails. So make it optional. Signed-off-by: Wesley Cheng [abel.vesa@oss.qualcomm.com: commit re-worded to reflect actual reason] Reviewed-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260302-phy-qcom-m31-eusb2-make-repeater-optional-v2-1-dbf714c72056@oss.qualcomm.com/ (cherry picked from commit 984aa89de0ab9645f8e95840cc3b1ce55526c853) --- drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c index 68f1ba8fec4ad..0bec8657149c9 100644 --- a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c @@ -285,7 +285,7 @@ static int m31eusb2_phy_probe(struct platform_device *pdev) phy_set_drvdata(phy->phy, phy); - phy->repeater = devm_of_phy_get_by_index(dev, dev->of_node, 0); + phy->repeater = devm_phy_optional_get(dev, NULL); if (IS_ERR(phy->repeater)) return dev_err_probe(dev, PTR_ERR(phy->repeater), "failed to get repeater\n"); From fb20891673d00adbfc9553dc6ee88703244163d5 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 25 May 2026 23:08:47 +0530 Subject: [PATCH 1102/1330] FROMLIST: clk: qcom: gcc-glymur: Move EVA clocks to critical clock list The gcc_eva_ahb_clk and gcc_eva_xo_clk branch clocks should not be registered as standalone GCC branch clocks. Drop these clocks from the GCC clock list and instead add their CBCR registers to the GCC critical clocks list to ensure they remain enabled during early boot. Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller") Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-1-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit 18eab67ef55f11476bf0fc218fa86b02e0d4d831) --- drivers/clk/qcom/gcc-glymur.c | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gcc-glymur.c b/drivers/clk/qcom/gcc-glymur.c index cd11470a75f3f..ac3282c9150c9 100644 --- a/drivers/clk/qcom/gcc-glymur.c +++ b/drivers/clk/qcom/gcc-glymur.c @@ -3670,21 +3670,6 @@ static struct clk_branch gcc_disp_hf_axi_clk = { }, }; -static struct clk_branch gcc_eva_ahb_clk = { - .halt_reg = 0x9b004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x9b004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x9b004, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_eva_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_eva_axi0_clk = { .halt_reg = 0x9b008, .halt_check = BRANCH_HALT_SKIP, @@ -3715,19 +3700,6 @@ static struct clk_branch gcc_eva_axi0c_clk = { }, }; -static struct clk_branch gcc_eva_xo_clk = { - .halt_reg = 0x9b024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9b024, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_eva_xo_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x64000, .halt_check = BRANCH_HALT, @@ -7994,10 +7966,8 @@ static struct clk_regmap *gcc_glymur_clocks[] = { [GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr, [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, - [GCC_EVA_AHB_CLK] = &gcc_eva_ahb_clk.clkr, [GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr, [GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr, - [GCC_EVA_XO_CLK] = &gcc_eva_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, @@ -8546,6 +8516,8 @@ static u32 gcc_glymur_critical_cbcrs[] = { 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 0x32004, /* GCC_VIDEO_AHB_CLK */ 0x32058, /* GCC_VIDEO_XO_CLK */ + 0x9b004, /* GCC_EVA_AHB_CLK */ + 0x9b024, /* GCC_EVA_XO_CLK */ }; static const struct regmap_config gcc_glymur_regmap_config = { From 30287409c1ce5f3389eb5851374f7c65180aad96 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 25 May 2026 23:08:14 +0530 Subject: [PATCH 1103/1330] FROMLIST: dt-bindings: clock: qcom: Add EVA clock and reset controller for Glymur SoC Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-2-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit dc215296393bb0634224eb345853a926abd0bcf2) --- .../bindings/clock/qcom,glymur-evacc.yaml | 76 +++++++++++++++++++ include/dt-bindings/clock/qcom,glymur-evacc.h | 38 ++++++++++ 2 files changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml create mode 100644 include/dt-bindings/clock/qcom,glymur-evacc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml new file mode 100644 index 0000000000000..8315e3ce82ecf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-evacc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm EVA Clock & Reset Controller on Glymur SoC + +maintainers: + - Taniya Das + +description: | + Qualcomm EVA clock control module which supports the clocks, resets and + power domains for the EVA instances on Glymur SoC. + + See also: + - include/dt-bindings/clock/qcom,glymur-evacc.h + +properties: + compatible: + const: qcom,glymur-evacc + + clocks: + items: + - description: Interface clock from GCC + - description: Board XO source + - description: Board XO_A source + - description: Sleep clock source + + power-domains: + description: + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain + + required-opps: + description: + Required OPP nodes for the MMCX and MXC power domains. + items: + - description: MMCX performance point + - description: MXC performance point + +required: + - compatible + - clocks + - power-domains + - required-opps + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ab00000 { + compatible = "qcom,glymur-evacc"; + reg = <0x0ab00000 0x10000>; + clocks = <&gcc GCC_EVA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,glymur-evacc.h b/include/dt-bindings/clock/qcom,glymur-evacc.h new file mode 100644 index 0000000000000..35a7b45503516 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-evacc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H + +/* EVA_CC clocks */ +#define EVA_CC_AHB_CLK 0 +#define EVA_CC_AHB_CLK_SRC 1 +#define EVA_CC_MVS0_CLK 2 +#define EVA_CC_MVS0_CLK_SRC 3 +#define EVA_CC_MVS0_DIV_CLK_SRC 4 +#define EVA_CC_MVS0_FREERUN_CLK 5 +#define EVA_CC_MVS0_SHIFT_CLK 6 +#define EVA_CC_MVS0C_CLK 7 +#define EVA_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define EVA_CC_MVS0C_FREERUN_CLK 9 +#define EVA_CC_MVS0C_SHIFT_CLK 10 +#define EVA_CC_PLL0 11 +#define EVA_CC_SLEEP_CLK 12 +#define EVA_CC_SLEEP_CLK_SRC 13 +#define EVA_CC_XO_CLK 14 +#define EVA_CC_XO_CLK_SRC 15 + +/* EVA_CC power domains */ +#define EVA_CC_MVS0_GDSC 0 +#define EVA_CC_MVS0C_GDSC 1 + +/* EVA_CC resets */ +#define EVA_CC_INTERFACE_BCR 0 +#define EVA_CC_MVS0_BCR 1 +#define EVA_CC_MVS0C_CLK_ARES 2 +#define EVA_CC_MVS0C_BCR 3 +#define EVA_CC_MVS0C_FREERUN_CLK_ARES 4 + +#endif /* _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H */ From 1c8c60bfe02a0c071c1dfe48467814614c695118 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 26 May 2026 00:12:10 +0530 Subject: [PATCH 1104/1330] FROMLIST: clk: qcom: Add EVA clock controller driver for Glymur SoC Add the Enhanced Video Analytics (EVA) clock controller driver for the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs and resets for the EVA subsystem which handles vision processing workloads. Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-3-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit a9bb2c28f8c98d1012d0f05d0ae61199eb95e84e) --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/evacc-glymur.c | 453 ++++++++++++++++++++++++++++++++ 3 files changed, 465 insertions(+) create mode 100644 drivers/clk/qcom/evacc-glymur.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 775ee9a9c4ae2..b952efd73d779 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -65,6 +65,17 @@ config CLK_GLYMUR_DISPCC Say Y if you want to support display devices and functionality such as splash screen. +config CLK_GLYMUR_EVACC + tristate "Glymur EVA Clock Controller" + depends on ARM64 || COMPILE_TEST + default m if ARCH_QCOM + select CLK_GLYMUR_GCC + help + Support for the Enhanced Video Analytics (EVA) clock controller on + Qualcomm Technologies, Inc. Glymur devices. + Say Y if you want to support EVA devices and functionality such as + vision processing. + config CLK_GLYMUR_GCC tristate "GLYMUR Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 343da4e9113aa..b4cd483a14f25 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o +obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o diff --git a/drivers/clk/qcom/evacc-glymur.c b/drivers/clk/qcom/evacc-glymur.c new file mode 100644 index 0000000000000..eab43ba922f37 --- /dev/null +++ b/drivers/clk/qcom/evacc-glymur.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_AHB_CLK, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_EVA_CC_PLL0_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco taycan_eko_t_vco[] = { + { 249600000, 2500000000, 0 }, +}; + +/* 840.0 MHz Configuration */ +static const struct alpha_pll_config eva_cc_pll0_config = { + .l = 0x2b, + .alpha = 0xc000, + .config_ctl_val = 0x25c400e7, + .config_ctl_hi_val = 0x0a8060e0, + .config_ctl_hi1_val = 0xf51dea20, + .user_ctl_val = 0x00000008, + .user_ctl_hi_val = 0x00000002, +}; + +static struct clk_alpha_pll eva_cc_pll0 = { + .offset = 0x0, + .config = &eva_cc_pll0_config, + .vco_table = taycan_eko_t_vco, + .num_vco = ARRAY_SIZE(taycan_eko_t_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct parent_map eva_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data eva_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map eva_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_EVA_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data eva_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &eva_cc_pll0.clkr.hw }, +}; + +static const struct parent_map eva_cc_parent_map_2[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data eva_cc_parent_data_2[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_eva_cc_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 eva_cc_ahb_clk_src = { + .cmd_rcgr = 0x8018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = eva_cc_parent_map_0, + .freq_tbl = ftbl_eva_cc_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_ahb_clk_src", + .parent_data = eva_cc_parent_data_0, + .num_parents = ARRAY_SIZE(eva_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_eva_cc_mvs0_clk_src[] = { + F(840000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1050000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1350000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1500000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1650000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 eva_cc_mvs0_clk_src = { + .cmd_rcgr = 0x8000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = eva_cc_parent_map_1, + .freq_tbl = ftbl_eva_cc_mvs0_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0_clk_src", + .parent_data = eva_cc_parent_data_1, + .num_parents = ARRAY_SIZE(eva_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_eva_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 eva_cc_sleep_clk_src = { + .cmd_rcgr = 0x80e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = eva_cc_parent_map_2, + .freq_tbl = ftbl_eva_cc_sleep_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_sleep_clk_src", + .parent_data = eva_cc_parent_data_2, + .num_parents = ARRAY_SIZE(eva_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 eva_cc_xo_clk_src = { + .cmd_rcgr = 0x80bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = eva_cc_parent_map_0, + .freq_tbl = ftbl_eva_cc_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_xo_clk_src", + .parent_data = eva_cc_parent_data_0, + .num_parents = ARRAY_SIZE(eva_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_regmap_div eva_cc_mvs0_div_clk_src = { + .reg = 0x809c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &eva_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div eva_cc_mvs0c_div2_div_clk_src = { + .reg = 0x8060, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &eva_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch eva_cc_mvs0_clk = { + .halt_reg = 0x807c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x807c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x807c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0_clk", + .parent_hws = (const struct clk_hw*[]) { + &eva_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0_freerun_clk = { + .halt_reg = 0x808c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x808c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0_freerun_clk", + .parent_hws = (const struct clk_hw*[]) { + &eva_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0_shift_clk = { + .halt_reg = 0x80d8, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x80d8, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80d8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &eva_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0c_clk = { + .halt_reg = 0x804c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x804c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0c_clk", + .parent_hws = (const struct clk_hw*[]) { + &eva_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0c_freerun_clk = { + .halt_reg = 0x805c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x805c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0c_freerun_clk", + .parent_hws = (const struct clk_hw*[]) { + &eva_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0c_shift_clk = { + .halt_reg = 0x80dc, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x80dc, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "eva_cc_mvs0c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &eva_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc eva_cc_mvs0c_gdsc = { + .gdscr = 0x8034, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "eva_cc_mvs0c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc eva_cc_mvs0_gdsc = { + .gdscr = 0x8068, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "eva_cc_mvs0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent = &eva_cc_mvs0c_gdsc.pd, +}; + +static struct clk_regmap *eva_cc_glymur_clocks[] = { + [EVA_CC_AHB_CLK_SRC] = &eva_cc_ahb_clk_src.clkr, + [EVA_CC_MVS0_CLK] = &eva_cc_mvs0_clk.clkr, + [EVA_CC_MVS0_CLK_SRC] = &eva_cc_mvs0_clk_src.clkr, + [EVA_CC_MVS0_DIV_CLK_SRC] = &eva_cc_mvs0_div_clk_src.clkr, + [EVA_CC_MVS0_FREERUN_CLK] = &eva_cc_mvs0_freerun_clk.clkr, + [EVA_CC_MVS0_SHIFT_CLK] = &eva_cc_mvs0_shift_clk.clkr, + [EVA_CC_MVS0C_CLK] = &eva_cc_mvs0c_clk.clkr, + [EVA_CC_MVS0C_DIV2_DIV_CLK_SRC] = &eva_cc_mvs0c_div2_div_clk_src.clkr, + [EVA_CC_MVS0C_FREERUN_CLK] = &eva_cc_mvs0c_freerun_clk.clkr, + [EVA_CC_MVS0C_SHIFT_CLK] = &eva_cc_mvs0c_shift_clk.clkr, + [EVA_CC_PLL0] = &eva_cc_pll0.clkr, + [EVA_CC_SLEEP_CLK_SRC] = &eva_cc_sleep_clk_src.clkr, + [EVA_CC_XO_CLK_SRC] = &eva_cc_xo_clk_src.clkr, +}; + +static struct gdsc *eva_cc_glymur_gdscs[] = { + [EVA_CC_MVS0_GDSC] = &eva_cc_mvs0_gdsc, + [EVA_CC_MVS0C_GDSC] = &eva_cc_mvs0c_gdsc, +}; + +static const struct qcom_reset_map eva_cc_glymur_resets[] = { + [EVA_CC_INTERFACE_BCR] = { 0x80a0 }, + [EVA_CC_MVS0_BCR] = { 0x8064 }, + [EVA_CC_MVS0C_CLK_ARES] = { 0x804c, 2 }, + [EVA_CC_MVS0C_BCR] = { 0x8030 }, + [EVA_CC_MVS0C_FREERUN_CLK_ARES] = { 0x805c, 2 }, +}; + +static struct clk_alpha_pll *eva_cc_glymur_plls[] = { + &eva_cc_pll0, +}; + +static const u32 eva_cc_glymur_critical_cbcrs[] = { + 0x80a4, /* EVA_CC_AHB_CLK */ + 0x80f8, /* EVA_CC_SLEEP_CLK */ + 0x80d4, /* EVA_CC_XO_CLK */ +}; + +static const struct regmap_config eva_cc_glymur_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9f50, + .fast_io = true, +}; + +static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap) +{ + /* Update CTRL_IN register */ + regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0)); +} + +static const struct qcom_cc_driver_data eva_cc_glymur_driver_data = { + .alpha_plls = eva_cc_glymur_plls, + .num_alpha_plls = ARRAY_SIZE(eva_cc_glymur_plls), + .clk_cbcrs = eva_cc_glymur_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(eva_cc_glymur_critical_cbcrs), + .clk_regs_configure = clk_glymur_regs_configure, +}; + +static const struct qcom_cc_desc eva_cc_glymur_desc = { + .config = &eva_cc_glymur_regmap_config, + .clks = eva_cc_glymur_clocks, + .num_clks = ARRAY_SIZE(eva_cc_glymur_clocks), + .resets = eva_cc_glymur_resets, + .num_resets = ARRAY_SIZE(eva_cc_glymur_resets), + .gdscs = eva_cc_glymur_gdscs, + .num_gdscs = ARRAY_SIZE(eva_cc_glymur_gdscs), + .use_rpm = true, + .driver_data = &eva_cc_glymur_driver_data, +}; + +static const struct of_device_id eva_cc_glymur_match_table[] = { + { .compatible = "qcom,glymur-evacc" }, + { } +}; +MODULE_DEVICE_TABLE(of, eva_cc_glymur_match_table); + +static int eva_cc_glymur_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &eva_cc_glymur_desc); +} + +static struct platform_driver eva_cc_glymur_driver = { + .probe = eva_cc_glymur_probe, + .driver = { + .name = "evacc-glymur", + .of_match_table = eva_cc_glymur_match_table, + }, +}; + +module_platform_driver(eva_cc_glymur_driver); + +MODULE_DESCRIPTION("QTI EVACC Glymur Driver"); +MODULE_LICENSE("GPL"); From 6d4b6facf48c180596f048c0dd0f91c6871c3f77 Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Mon, 25 May 2026 19:04:59 +0530 Subject: [PATCH 1105/1330] arm64: dts: qcom: shikra-iqs-evk: Add DSI panel support Add lcd_bias fixed regulator (3.3V, controlled via pm8150 GPIO4) Enable mdss, mdss_dsi0, mdss_dsi0_phy nodes Add DLC DLC0697 panel node on DSI0 with reset/enable GPIOs, vddio/bias supplies, and TE pin Configure mdss_dsi0_out with 4-lane data path Set pm8150_l11 to 1232mV for DSI VDDA PHY PLL lock Add tlmm pinctrl states for panel reset, reset-suspend, and TE pin. Signed-off-by: Vishnu Saini (cherry picked from commit 872330a93c804b1c2afede355d49f64a29e91f2d) --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 66 +++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 687c978be5bfb..7a2a7b5743bbb 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -42,6 +42,18 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + lcd_bias: regulator-lcd-bias { + compatible = "regulator-fixed"; + regulator-name = "lcd_bias"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pm8150_l17>; + gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_bias_en>; + pinctrl-names = "default"; + }; }; &gpu { @@ -52,6 +64,60 @@ firmware-name = "qcom/shikra/a704_zap.mbn"; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8150_l11>; + status = "okay"; + + panel@0 { + compatible = "dlc,dlc0697"; + reg = <0>; + + reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + enable-gpios = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&pm8150_l15>; + bias-supply = <&lcd_bias>; + + pinctrl-0 = <&panel_rst_n &panel_te_pin>; + pinctrl-1 = <&panel_rst_n_suspend>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pm8150_gpios { + lcd_bias_en: lcd-bias-en-state { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-disable; + }; +}; + +&pm8150_l11 { + /* DSI VDDA - must be at NOM voltage for PHY PLL lock */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + regulator-allow-set-load; +}; + &remoteproc_cdsp { firmware-name = "qcom/shikra/cdsp.mbn"; From e8519eeded88fd929ca4114774ccbfa53c2a885d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 21 Apr 2026 16:11:01 +0530 Subject: [PATCH 1106/1330] FROMLIST: PCI/pwrctrl: Do not try to power on/off devices that don't need pwrctrl pci_pwrctrl_is_required() is used to detect whether a device really needs the PCI pwrctrl support or not. It is currently used in pci_pwrctrl_create_device(), but not in pci_pwrctrl_power_{on/off}_device() APIs. This leads to pwrctrl core trying to power on/off the incompatible devices like USB hub downstream ports defined in DT. Hence, add this check to prevent pwrctrl core from poking at wrong devices. For this purpose, move the pci_pwrctrl_is_required() helper definition to the top. Link: https://lore.kernel.org/r/20260421104102.12322-1-manivannan.sadhasivam@oss.qualcomm.com Fixes: b35cf3b6aa1e ("PCI/pwrctrl: Add APIs to power on/off pwrctrl devices") Reported-by: Krishna Chaitanya Chundru Signed-off-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang (cherry picked from commit acd6cd0e23c6805184faa5b9a2134ff82021806a) --- drivers/pci/pwrctrl/core.c | 90 ++++++++++++++++++++------------------ 1 file changed, 48 insertions(+), 42 deletions(-) diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c index 97cff5b8ca885..b5a0a14d316e9 100644 --- a/drivers/pci/pwrctrl/core.c +++ b/drivers/pci/pwrctrl/core.c @@ -139,6 +139,48 @@ int devm_pci_pwrctrl_device_set_ready(struct device *dev, } EXPORT_SYMBOL_GPL(devm_pci_pwrctrl_device_set_ready); +/* + * Check whether the pwrctrl device really needs to be created or not. The + * pwrctrl device will only be created if the node satisfies below requirements: + * + * 1. Presence of compatible property with "pci" prefix to match against the + * pwrctrl driver (AND) + * 2. At least one of the power supplies defined in the devicetree node of the + * device (OR) in the remote endpoint parent node to indicate pwrctrl + * requirement. + */ +static bool pci_pwrctrl_is_required(struct device_node *np) +{ + struct device_node *endpoint; + const char *compat; + int ret; + + ret = of_property_read_string(np, "compatible", &compat); + if (ret < 0) + return false; + + if (!strstarts(compat, "pci")) + return false; + + if (of_pci_supply_present(np)) + return true; + + if (of_graph_is_present(np)) { + for_each_endpoint_of_node(np, endpoint) { + struct device_node *remote __free(device_node) = + of_graph_get_remote_port_parent(endpoint); + if (remote) { + if (of_pci_supply_present(remote)) { + of_node_put(endpoint); + return true; + } + } + } + } + + return false; +} + static int __pci_pwrctrl_power_off_device(struct device *dev) { struct pci_pwrctrl *pwrctrl = dev_get_drvdata(dev); @@ -157,6 +199,9 @@ static void pci_pwrctrl_power_off_device(struct device_node *np) for_each_available_child_of_node_scoped(np, child) pci_pwrctrl_power_off_device(child); + if (!pci_pwrctrl_is_required(np)) + return; + pdev = of_find_device_by_node(np); if (!pdev) return; @@ -213,6 +258,9 @@ static int pci_pwrctrl_power_on_device(struct device_node *np) return ret; } + if (!pci_pwrctrl_is_required(np)) + return 0; + pdev = of_find_device_by_node(np); if (!pdev) return 0; @@ -268,48 +316,6 @@ int pci_pwrctrl_power_on_devices(struct device *parent) } EXPORT_SYMBOL_GPL(pci_pwrctrl_power_on_devices); -/* - * Check whether the pwrctrl device really needs to be created or not. The - * pwrctrl device will only be created if the node satisfies below requirements: - * - * 1. Presence of compatible property with "pci" prefix to match against the - * pwrctrl driver (AND) - * 2. At least one of the power supplies defined in the devicetree node of the - * device (OR) in the remote endpoint parent node to indicate pwrctrl - * requirement. - */ -static bool pci_pwrctrl_is_required(struct device_node *np) -{ - struct device_node *endpoint; - const char *compat; - int ret; - - ret = of_property_read_string(np, "compatible", &compat); - if (ret < 0) - return false; - - if (!strstarts(compat, "pci")) - return false; - - if (of_pci_supply_present(np)) - return true; - - if (of_graph_is_present(np)) { - for_each_endpoint_of_node(np, endpoint) { - struct device_node *remote __free(device_node) = - of_graph_get_remote_port_parent(endpoint); - if (remote) { - if (of_pci_supply_present(remote)) { - of_node_put(endpoint); - return true; - } - } - } - } - - return false; -} - static int pci_pwrctrl_create_device(struct device_node *np, struct device *parent) { From ce2eb8afb3e4f2969eead75150a9354a26b68016 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 15 May 2026 00:00:00 +0800 Subject: [PATCH 1107/1330] WORKAROUND: phy: qcom: qmp-pcie: Add vdda-refgen and vdda-qref supplies for Monaco The PCIe QMP PHYs on Monaco (QCS8300) require stable reference voltage provided by refgen and reference clock provided by qref. The refgen and qref require power supplies. Add a new sa8775p_qmp_phy_vreg_l list with vdda-qref and vdda-refgen supplies, and use it for qcs8300_qmp_gen4x2, sa8775p_qmp_gen4x2 and sa8775p_qmp_gen4x4 PCIe PHY configurations. Workaround will be reverted once the vote qref regulator for PCIe available in upstream. Signed-off-by: Ziyue Zhang (cherry picked from commit 02d02c13992d3406125e694216e411203dd2f5bb) --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 86e71ff796d9e..9c880cd72b584 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3390,6 +3390,10 @@ static const char * const sm8550_qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2", "vdda-qref","vdda-qref2", }; +static const char * const sa8775p_qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", "vdda-qref", "vdda-refgen", +}; + /* list of resets */ static const char * const ipq8074_pciephy_reset_l[] = { "phy", "common", @@ -3740,8 +3744,8 @@ static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sa8775p_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4454,8 +4458,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sa8775p_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4495,8 +4499,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sa8775p_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, From de33930c71f0a2ef4666944cd422aca2e67f1011 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 15 May 2026 00:00:00 +0800 Subject: [PATCH 1108/1330] WORKAROUND: arm64: dts: qcom: qcs8300-ride: Add vdda-qref and vdda-refgen supplies for PCIe PHYs The PCIe QMP PHYs on QCS8300 require stable reference voltage provided by refgen and reference clock provided by qref. Add vdda-qref-supply and vdda-refgen-supply to pcie0_phy and pcie1_phy nodes on the qcs8300-ride board. Workaround will be reverted once the vote qref regulator for PCIe available in upstream. Signed-off-by: Ziyue Zhang (cherry picked from commit 64fbefde7acc60f01e9caa4eb689bae60390f66d) --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 844b513743cb1..8b732689dfd12 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -638,7 +638,9 @@ &pcie0_phy { vdda-phy-supply = <&vreg_l6a>; - vdda-pll-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l5a>; + vdda-qref-supply = <&vreg_l7a>; + vdda-refgen-supply = <&refgen>; status = "okay"; }; @@ -658,6 +660,8 @@ &pcie1_phy { vdda-phy-supply = <&vreg_l6a>; vdda-pll-supply = <&vreg_l5a>; + vdda-qref-supply = <&vreg_l7a>; + vdda-refgen-supply = <&refgen>; status = "okay"; }; From 98ef44b17f2113900291802fd8502d807a7fdb47 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Fri, 22 May 2026 16:20:20 +0530 Subject: [PATCH 1109/1330] FROMLIST: arm64: dts: qcom: qcs615-ride: fix sdhc_2 vqmmc-supply for UHS-I mode SD card is detected as SDHS instead of UHS-I because sdhc_2 was configured with vreg_s4a as vqmmc-supply, which cannot switch between 1.8V and 3.3V. Switch vqmmc-supply to vreg_l2a and update its voltage range to 1800000-2960000 uV to enable proper UHS-I signaling. Link: https://lore.kernel.org/all/20260522105020.3588377-1-mchunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara Signed-off-by: Pradeep P V K (cherry picked from commit 195c20d3e5ac3676a4e11ec40e68dd6afcc17eb1) --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index addb6e6e66ee4..5f847f33539d0 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -258,8 +258,8 @@ vreg_l2a: ldo2 { regulator-name = "vreg_l2a"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <3100000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; vmmc-supply = <&vreg_l10a>; - vqmmc-supply = <&vreg_s4a>; + vqmmc-supply = <&vreg_l2a>; status = "okay"; }; From 43195aaa41262abc1ef33849ec248154db16f6b7 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Wed, 27 May 2026 22:28:26 +0530 Subject: [PATCH 1110/1330] PENDING: arm64: dts: qcom: glymur-crd: Add FocalTech FT3D81 touchscreen support The Glymur CRD board includes a FocalTech FT3D81 touchscreen connected to I2C bus.FT3D81 driver is compatible to ft112. Signed-off-by: Pradyot Kumar Nayak (cherry picked from commit 165f40a00de938b8edd0176323ad9ecd26c16460) --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index e80990181f74a..44c83a6a52c54 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -658,17 +658,15 @@ status = "okay"; touchscreen@38 { - compatible = "hid-over-i2c"; + compatible = "focaltech,ft8112"; reg = <0x38>; - hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; + vcc33-supply = <&vreg_misc_3p3>; + vccio-supply = <&vreg_l15b_e0_1p8>; reset-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <100>; pinctrl-0 = <&ts0_default>; pinctrl-names = "default"; From df99f1dffb900cff54b7cbbdcf058dfb246a4abd Mon Sep 17 00:00:00 2001 From: Shashank Maurya Date: Wed, 27 May 2026 23:04:02 +0530 Subject: [PATCH 1111/1330] arm64: dts: qcom: shikra-iqs-evk: Add pinctrl for DLC0697 DSI panel Add TLMM pinctrl states for the DLC0697 DSI panel. This includes configuring GPIO3 for the panel reset signal (active and suspend states) and GPIO86 for the tearing effect (TE) signal using the mdp_vsync_p function. Signed-off-by: Shashank Maurya (cherry picked from commit 7aa3e6667b315fae478317d505b75023a51360b6) --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 23 +++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 7a2a7b5743bbb..690601da142e0 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -169,6 +169,29 @@ status = "okay"; }; +&tlmm { + panel_rst_n: panel-rst-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_rst_n_suspend: panel-rst-n-suspend-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + panel_te_pin: panel-te-pin-state { + pins = "gpio86"; + function = "mdp_vsync_p"; + drive-strength = <2>; + bias-pull-down; + }; +}; + &uart0 { status = "okay"; }; From 55087ac24a731c74db54a4b4d7e79fc7ba6a806c Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:58 +0530 Subject: [PATCH 1112/1330] Revert "FROMLIST: media: qcom: venus: flip the venus/iris switch" This reverts commit 46f670f2b85181106503ed4d1c597e080c4c3c3e. Signed-off-by: Gourav Kumar (cherry picked from commit 572f9d98870c168b59a75961e5a60efece21e0b8) --- drivers/media/platform/qcom/iris/Makefile | 9 ++-- drivers/media/platform/qcom/iris/iris_probe.c | 2 + drivers/media/platform/qcom/venus/core.c | 49 ------------------- drivers/media/platform/qcom/venus/core.h | 11 ----- 4 files changed, 7 insertions(+), 64 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 8cdea242f7fdb..c889d76b31836 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -12,10 +12,7 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_glymur.o \ - iris_platform_vpu2.o \ - iris_platform_vpu3x.o \ - iris_platform_vpu4x.o \ + iris_platform_gen2.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ @@ -31,4 +28,8 @@ qcom-iris-objs += iris_buffer.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ +ifeq ($(CONFIG_VIDEO_QCOM_VENUS),) +qcom-iris-objs += iris_platform_gen1.o +endif + obj-$(CONFIG_VIDEO_QCOM_IRIS) += qcom-iris.o diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index a8c8e8c07eb09..7b84daf914808 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -384,6 +384,7 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, }, +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_VENUS)) { .compatible = "qcom,sc7280-venus", .data = &sc7280_data, @@ -392,6 +393,7 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,sm8250-venus", .data = &sm8250_data, }, +#endif { .compatible = "qcom,sm8550-iris", .data = &sm8550_data, diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c index d8e3588b4b5f5..78a13ece7b86d 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -968,7 +968,6 @@ static const struct venus_resources sc7180_res = { .enc_nodename = "video-encoder", }; -#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) static const struct freq_tbl sm8250_freq_table[] = { { 0, 444000000 }, { 0, 366000000 }, @@ -1128,50 +1127,6 @@ static const struct venus_resources sc7280_res = { .enc_nodename = "video-encoder", }; -static const struct freq_tbl sc8280xp_freq_table[] = { - { 0, 239999999 }, - { 0, 338000000 }, - { 0, 366000000 }, - { 0, 444000000 }, - { 0, 533000000 }, - { 0, 560000000 }, -}; - -static const struct venus_resources sc8280xp_res = { - .freq_tbl = sc8280xp_freq_table, - .freq_tbl_size = ARRAY_SIZE(sc8280xp_freq_table), - .reg_tbl = sm8350_reg_preset, - .reg_tbl_size = ARRAY_SIZE(sm8350_reg_preset), - .bw_tbl_enc = sm8250_bw_table_enc, - .bw_tbl_enc_size = ARRAY_SIZE(sm8250_bw_table_enc), - .bw_tbl_dec = sm8250_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), - .clks = { "core", "iface" }, - .clks_num = 2, - .resets = { "core" }, - .resets_num = 1, - .vcodec0_clks = { "vcodec0_core" }, - .vcodec_clks_num = 1, - .vcodec_pmdomains = (const char *[]) { "venus", "vcodec0" }, - .vcodec_pmdomains_num = 2, - .opp_pmdomain = (const char *[]) { "mx", NULL }, - .vcodec_num = 1, - .max_load = 7833600, /* 7680x4320@60fps */ - .hfi_version = HFI_VERSION_6XX, - .vpu_version = VPU_VERSION_IRIS2, - .num_vpp_pipes = 4, - .vmem_id = VIDC_RESOURCE_NONE, - .vmem_size = 0, - .vmem_addr = 0, - .dma_mask = GENMASK(31, 29) - 1, - .cp_start = 0, - .cp_size = 0x25800000, - .cp_nonpixel_start = 0x1000000, - .cp_nonpixel_size = 0x24800000, - .fwname = "qcom/vpu-2.0/venus.mbn", -}; -#endif - static const struct bw_tbl qcm2290_bw_table_dec[] = { { 352800, 597000, 0, 746000, 0 }, /* 1080p@30 + 720p@30 */ { 244800, 413000, 0, 516000, 0 }, /* 1080p@30 */ @@ -1227,15 +1182,11 @@ static const struct of_device_id venus_dt_match[] = { { .compatible = "qcom,msm8998-venus", .data = &msm8998_res, }, { .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res, }, { .compatible = "qcom,sc7180-venus", .data = &sc7180_res, }, -#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) { .compatible = "qcom,sc7280-venus", .data = &sc7280_res, }, -#endif { .compatible = "qcom,sdm660-venus", .data = &sdm660_res, }, { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, }, { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2, }, -#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) { .compatible = "qcom,sm8250-venus", .data = &sm8250_res, }, -#endif { } }; MODULE_DEVICE_TABLE(of, venus_dt_match); diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index 3921d65389cbc..6eeb1fa30d7fc 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -55,10 +55,8 @@ enum vpu_version { VPU_VERSION_AR50, VPU_VERSION_AR50_LITE, VPU_VERSION_IRIS1, -#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) VPU_VERSION_IRIS2, VPU_VERSION_IRIS2_1, -#endif }; struct firmware_version { @@ -533,22 +531,13 @@ struct venus_inst { #define IS_V1(core) ((core)->res->hfi_version == HFI_VERSION_1XX) #define IS_V3(core) ((core)->res->hfi_version == HFI_VERSION_3XX) #define IS_V4(core) ((core)->res->hfi_version == HFI_VERSION_4XX) -#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) #define IS_V6(core) ((core)->res->hfi_version == HFI_VERSION_6XX) -#else -#define IS_V6(core) (0) -#endif #define IS_AR50(core) ((core)->res->vpu_version == VPU_VERSION_AR50) #define IS_AR50_LITE(core) ((core)->res->vpu_version == VPU_VERSION_AR50_LITE) #define IS_IRIS1(core) ((core)->res->vpu_version == VPU_VERSION_IRIS1) -#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) #define IS_IRIS2(core) ((core)->res->vpu_version == VPU_VERSION_IRIS2) #define IS_IRIS2_1(core) ((core)->res->vpu_version == VPU_VERSION_IRIS2_1) -#else -#define IS_IRIS2(core) (0) -#define IS_IRIS2_1(core) (0) -#endif static inline bool is_lite(struct venus_core *core) { From 646b40c7c8e8d8c7df757546cb7a027a65774807 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 27 Mar 2026 22:19:56 +0200 Subject: [PATCH 1113/1330] FROMGIT: media: qcom: venus: flip the venus/iris switch With the Iris and Venus driver having more or less feature parity for "HFI 6xx" platforms and with Iris gaining support for SC7280, flip the switch. Use Iris by default for SM8250 and SC7280, the platforms which are supported by both drivers, and use Venus only if Iris is not compiled at all. Use IS_ENABLED to strip out the code and data structures which are used by the disabled platforms. Link: https://lore.kernel.org/all/20260327-venus-iris-flip-switch-v5-4-2f4b6c636927@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov [bod: Moved two conditional compats inside of one ifdef for ci] [bod: Changed IS_V6(core) (0) to ((void)(core), 0) for ci] Signed-off-by: Bryan O'Donoghue (cherry picked from commit 044ed63ad08f75c3e422dbc4da10affcca7dd713) --- drivers/media/platform/qcom/iris/Makefile | 5 +---- drivers/media/platform/qcom/iris/iris_probe.c | 2 -- drivers/media/platform/qcom/venus/core.c | 6 +++++- drivers/media/platform/qcom/venus/core.h | 11 +++++++++++ 4 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index c889d76b31836..a898a4a7eff01 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -12,6 +12,7 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ + iris_platform_gen1.o \ iris_platform_gen2.o \ iris_power.o \ iris_probe.o \ @@ -28,8 +29,4 @@ qcom-iris-objs += iris_buffer.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ -ifeq ($(CONFIG_VIDEO_QCOM_VENUS),) -qcom-iris-objs += iris_platform_gen1.o -endif - obj-$(CONFIG_VIDEO_QCOM_IRIS) += qcom-iris.o diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 7b84daf914808..a8c8e8c07eb09 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -384,7 +384,6 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, }, -#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_VENUS)) { .compatible = "qcom,sc7280-venus", .data = &sc7280_data, @@ -393,7 +392,6 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,sm8250-venus", .data = &sm8250_data, }, -#endif { .compatible = "qcom,sm8550-iris", .data = &sm8550_data, diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c index 78a13ece7b86d..73a08d10c3b27 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -968,6 +968,7 @@ static const struct venus_resources sc7180_res = { .enc_nodename = "video-encoder", }; +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) static const struct freq_tbl sm8250_freq_table[] = { { 0, 444000000 }, { 0, 366000000 }, @@ -1126,6 +1127,7 @@ static const struct venus_resources sc7280_res = { .dec_nodename = "video-decoder", .enc_nodename = "video-encoder", }; +#endif static const struct bw_tbl qcm2290_bw_table_dec[] = { { 352800, 597000, 0, 746000, 0 }, /* 1080p@30 + 720p@30 */ @@ -1182,11 +1184,13 @@ static const struct of_device_id venus_dt_match[] = { { .compatible = "qcom,msm8998-venus", .data = &msm8998_res, }, { .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res, }, { .compatible = "qcom,sc7180-venus", .data = &sc7180_res, }, - { .compatible = "qcom,sc7280-venus", .data = &sc7280_res, }, { .compatible = "qcom,sdm660-venus", .data = &sdm660_res, }, { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, }, { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2, }, +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) + { .compatible = "qcom,sc7280-venus", .data = &sc7280_res, }, { .compatible = "qcom,sm8250-venus", .data = &sm8250_res, }, +#endif { } }; MODULE_DEVICE_TABLE(of, venus_dt_match); diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index 6eeb1fa30d7fc..9a6dd0c1d5652 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -55,8 +55,10 @@ enum vpu_version { VPU_VERSION_AR50, VPU_VERSION_AR50_LITE, VPU_VERSION_IRIS1, +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) VPU_VERSION_IRIS2, VPU_VERSION_IRIS2_1, +#endif }; struct firmware_version { @@ -531,13 +533,22 @@ struct venus_inst { #define IS_V1(core) ((core)->res->hfi_version == HFI_VERSION_1XX) #define IS_V3(core) ((core)->res->hfi_version == HFI_VERSION_3XX) #define IS_V4(core) ((core)->res->hfi_version == HFI_VERSION_4XX) +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) #define IS_V6(core) ((core)->res->hfi_version == HFI_VERSION_6XX) +#else +#define IS_V6(core) (((void)(core), 0)) +#endif #define IS_AR50(core) ((core)->res->vpu_version == VPU_VERSION_AR50) #define IS_AR50_LITE(core) ((core)->res->vpu_version == VPU_VERSION_AR50_LITE) #define IS_IRIS1(core) ((core)->res->vpu_version == VPU_VERSION_IRIS1) +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) #define IS_IRIS2(core) ((core)->res->vpu_version == VPU_VERSION_IRIS2) #define IS_IRIS2_1(core) ((core)->res->vpu_version == VPU_VERSION_IRIS2_1) +#else +#define IS_IRIS2(core) (((void)(core), 0)) +#define IS_IRIS2_1(core) (((void)(core), 0)) +#endif static inline bool is_lite(struct venus_core *core) { From a54edae2d6333eea4dc5aba195c8ae748e999eec Mon Sep 17 00:00:00 2001 From: Wei Zhang Date: Tue, 21 Apr 2026 14:33:48 +0800 Subject: [PATCH 1114/1330] FROMLIST: wifi: ath11k: raise max vdevs to 4 on hardware with P2P and dual-station support When P2P support is enabled, wpa_supplicant creates a p2p-device interface by default, which implicitly consumes one vdev. On systems managed by NetworkManager, this interface cannot be reliably disabled, leaving only two usable interfaces for user configurations. Increase num_vdevs to four for QCA6390 hw2.0, WCN6855 hw2.0/hw2.1, QCA2066 hw2.1, and QCA6698AQ hw2.1 to account for the implicit p2p-device and enable common concurrency scenarios such as AP + AP + STA. This change increases interface concurrency in the two-channel scenario by raising the maximum vdev limit, while keeping other combination rules unchanged. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-05266-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.41 Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Tested-on: QCA2066 hw2.1 PCI WLAN.HSP.1.1-03926.13-QCAHSPSWPL_V2_SILICONZ_CE-2.52297.9 Tested-on: QCA6698AQ hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Link: https://lore.kernel.org/linux-wireless/20260525020711.2590815-1-wei.zhang@oss.qualcomm.com/ Signed-off-by: Wei Zhang (cherry picked from commit f29363bbe07822e03a7b24180b02cea32379f936) --- drivers/net/wireless/ath/ath11k/core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c index 3f6f4db5b7ee1..8dacc878c0068 100644 --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c @@ -267,7 +267,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .coldboot_cal_ftm = false, .cbcal_restart_fw = false, .fw_mem_mode = 0, - .num_vdevs = 2 + 1, + .num_vdevs = 4, .num_peers = 512, .supports_suspend = true, .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), @@ -445,7 +445,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .coldboot_cal_ftm = false, .cbcal_restart_fw = false, .fw_mem_mode = 0, - .num_vdevs = 2 + 1, + .num_vdevs = 4, .num_peers = 512, .supports_suspend = true, .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), @@ -535,7 +535,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .coldboot_cal_ftm = false, .cbcal_restart_fw = false, .fw_mem_mode = 0, - .num_vdevs = 2 + 1, + .num_vdevs = 4, .num_peers = 512, .supports_suspend = true, .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), @@ -797,7 +797,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .coldboot_cal_ftm = false, .cbcal_restart_fw = false, .fw_mem_mode = 0, - .num_vdevs = 2 + 1, + .num_vdevs = 4, .num_peers = 512, .supports_suspend = true, .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), @@ -886,7 +886,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .coldboot_cal_ftm = false, .cbcal_restart_fw = false, .fw_mem_mode = 0, - .num_vdevs = 2 + 1, + .num_vdevs = 4, .num_peers = 512, .supports_suspend = true, .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), From 01044d0e6452a90ab5929f66aec745215fb9cf06 Mon Sep 17 00:00:00 2001 From: Wei Zhang Date: Mon, 11 May 2026 21:49:04 -0700 Subject: [PATCH 1115/1330] FROMLIST: wifi: ath12k: fix inconsistent arvif state in vdev_create error paths ath12k_mac_vdev_create() has three error path issues that leave arvif in an inconsistent state: 1. When ath12k_wmi_vdev_create() fails, the function returns directly without clearing arvif->ar, which was already set before the WMI call. Subsequent code checking arvif->ar to determine vdev readiness will see a non-NULL value despite no vdev existing in firmware. 2. When ath12k_wmi_send_peer_delete_cmd() fails in err_peer_del, the code jumped to err: skipping the DP peer cleanup and vdev rollback, leaving num_created_vdevs, vdev maps and arvif list membership live. 3. When ath12k_wait_for_peer_delete_done() fails, the code jumped to err_vdev_del: skipping the DP peer cleanup. Fix by changing the ath12k_wmi_vdev_create() failure to goto err instead of returning directly, routing both err_peer_del failure paths through err_dp_peer_del: for proper DP peer and vdev rollback, and consolidating the arvif state cleanup at err:. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: 477cabfdb776 ("wifi: ath12k: modify link arvif creation and removal for MLO") Link: https://lore.kernel.org/linux-wireless/20260512044906.1735821-1-wei.zhang@oss.qualcomm.com/ Signed-off-by: Wei Zhang (cherry picked from commit d086d2fa366aaaa98d273d381637252650c7b12a) --- drivers/net/wireless/ath/ath12k/mac.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c index ad547b06c0483..c6386432a9cdf 100644 --- a/drivers/net/wireless/ath/ath12k/mac.c +++ b/drivers/net/wireless/ath/ath12k/mac.c @@ -10283,7 +10283,7 @@ int ath12k_mac_vdev_create(struct ath12k *ar, struct ath12k_link_vif *arvif) if (ret) { ath12k_warn(ab, "failed to create WMI vdev %d: %d\n", arvif->vdev_id, ret); - return ret; + goto err; } ar->num_created_vdevs++; @@ -10430,13 +10430,13 @@ int ath12k_mac_vdev_create(struct ath12k *ar, struct ath12k_link_vif *arvif) if (ret) { ath12k_warn(ar->ab, "failed to delete peer vdev_id %d addr %pM\n", arvif->vdev_id, arvif->bssid); - goto err; + goto err_dp_peer_del; } ret = ath12k_wait_for_peer_delete_done(ar, arvif->vdev_id, arvif->bssid); if (ret) - goto err_vdev_del; + goto err_dp_peer_del; ar->num_peers--; } @@ -10453,8 +10453,6 @@ int ath12k_mac_vdev_create(struct ath12k *ar, struct ath12k_link_vif *arvif) ath12k_wmi_vdev_delete(ar, arvif->vdev_id); ar->num_created_vdevs--; - arvif->is_created = false; - arvif->ar = NULL; ar->allocated_vdev_map &= ~(1LL << arvif->vdev_id); ab->free_vdev_map |= 1LL << arvif->vdev_id; ab->free_vdev_stats_id_map &= ~(1LL << arvif->vdev_stats_id); @@ -10463,6 +10461,7 @@ int ath12k_mac_vdev_create(struct ath12k *ar, struct ath12k_link_vif *arvif) spin_unlock_bh(&ar->data_lock); err: + arvif->is_created = false; arvif->ar = NULL; return ret; } From 6ee5d8f0c05e6bcc163ac28681bc43fccd2787b2 Mon Sep 17 00:00:00 2001 From: Wei Zhang Date: Mon, 11 May 2026 21:49:05 -0700 Subject: [PATCH 1116/1330] FROMLIST: wifi: ath12k: fix NULL deref in change_sta_links for unready link _ieee80211_set_active_links() calls _ieee80211_link_use_channel() for each newly-added link and WARN_ON_ONCE()s if it fails. The call uses assign_on_failure=true, which allows mac80211 to continue despite driver failures, but when a mac80211-level channel validation fails (e.g., combinations check, DFS, or no available radio), drv_assign_vif_chanctx() is never reached. Since ath12k_mac_vdev_create() is only called from that path, arvif->is_created remains false and arvif->ar remains NULL for the failed link. The subsequent drv_change_sta_links() call reaches ath12k_mac_op_change_sta_links(), which allocates an arsta and sets ahsta->links_map |= BIT(link_id) for the broken link before checking whether the link is ready. When the vdev was never created, only station_add() is skipped, but the link remains in links_map. Any subsequent operation iterating links_map and dereferencing arvif->ar without a NULL check will crash. Two observed examples are NULL deref in ath12k_mac_ml_station_remove() on disconnect and in ath12k_mac_op_set_key() when wpa_supplicant installs PTK keys. BUG: Unable to handle kernel NULL pointer dereference at 0x00000000 pc : ath12k_mac_station_post_remove+0x40/0xe8 [ath12k] Call trace: ath12k_mac_station_post_remove+0x40/0xe8 [ath12k] ath12k_mac_op_sta_state+0xb60/0x1720 [ath12k] drv_sta_state+0x100/0xbd8 [mac80211] __sta_info_destroy_part2+0x148/0x178 [mac80211] ieee80211_set_disassoc+0x500/0x678 [mac80211] BUG: Unable to handle kernel NULL pointer dereference at 0x00000000 pc : ath12k_mac_op_set_key+0x1f8/0x2c0 [ath12k] Call trace: ath12k_mac_op_set_key+0x1f8/0x2c0 [ath12k] drv_set_key+0x70/0x100 [mac80211] ieee80211_key_enable_hw_accel+0x78/0x260 [mac80211] ieee80211_add_key+0x16c/0x2ac [mac80211] nl80211_new_key+0x138/0x280 [cfg80211] Fix this by checking arvif->is_created before calling ath12k_mac_alloc_assign_link_sta(). This prevents the broken link from entering links_map, so all subsequent operations iterating the bitmap are protected. The reliability of arvif->is_created across all error paths is ensured by the preceding patch. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: a27fa6148dac ("wifi: ath12k: support change_sta_links() mac80211 op") Link: https://lore.kernel.org/linux-wireless/20260512044906.1735821-1-wei.zhang@oss.qualcomm.com/ Signed-off-by: Wei Zhang (cherry picked from commit f542adb59d7428ee3f278ca80aca382904a30fbb) --- drivers/net/wireless/ath/ath12k/mac.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c index c6386432a9cdf..ba0681a94c14e 100644 --- a/drivers/net/wireless/ath/ath12k/mac.c +++ b/drivers/net/wireless/ath/ath12k/mac.c @@ -8044,16 +8044,16 @@ int ath12k_mac_op_change_sta_links(struct ieee80211_hw *hw, continue; arvif = wiphy_dereference(hw->wiphy, ahvif->link[link_id]); - arsta = ath12k_mac_alloc_assign_link_sta(ah, ahsta, ahvif, link_id); + if (!arvif || !arvif->is_created) + continue; - if (!arvif || !arsta) { + arsta = ath12k_mac_alloc_assign_link_sta(ah, ahsta, ahvif, link_id); + if (!arsta) { ath12k_hw_warn(ah, "Failed to alloc/assign link sta"); continue; } ar = arvif->ar; - if (!ar) - continue; ret = ath12k_mac_station_add(ar, arvif, arsta); if (ret) { From 6781ae875e3602076f9ea857681667b17a0f98ed Mon Sep 17 00:00:00 2001 From: Yepuri Siddu Date: Wed, 27 May 2026 18:04:50 +0530 Subject: [PATCH 1117/1330] arm64: dts: qcom: shikra: Add wcn3988-pmu node to EVK boards Add wcn3988-pmu node with supply regulators and bt-enable-gpios to shikra EVK board DTS files. Update the BT node supply references to use PMU-managed LDOs (vreg_pmu_io/xo/rf/ch0) instead of direct PMIC regulators, and move BT node to the board-specific shikra-evk.dtsi. Signed-off-by: Yepuri Siddu (cherry picked from commit 1e015b8fba8f3260b6f8328ec74ae06cf5b47530) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 36 ++++++++++++++++-- arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 37 +++++++++++++++++-- arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 41 ++++++++++++++++++--- arch/arm64/boot/dts/qcom/shikra.dtsi | 8 ---- 5 files changed, 109 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 3bd62ba3221d9..170515bb59fab 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -37,6 +37,34 @@ pinctrl-names = "default"; }; + wcn3988-pmu { + compatible = "qcom,wcn3988-pmu"; + + vddio-supply = <&pm4125_l7>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + + bt-enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + }; + }; }; &gpu { @@ -191,10 +219,10 @@ status = "okay"; bluetooth { - vddio-supply = <&pm4125_l7>; - vddxo-supply = <&pm4125_l13>; - vddrf-supply = <&pm4125_l10>; - vddch0-supply = <&pm4125_l22>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 8d87a78bd8782..d59005e56c81b 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -36,6 +36,35 @@ pinctrl-0 = <&lcd_bias_en>; pinctrl-names = "default"; }; + + wcn3988-pmu { + compatible = "qcom,wcn3988-pmu"; + + vddio-supply = <&pm4125_l7>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + + bt-enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + }; + }; }; &gpu { @@ -189,10 +218,10 @@ status = "okay"; bluetooth { - vddio-supply = <&pm4125_l7>; - vddxo-supply = <&pm4125_l13>; - vddrf-supply = <&pm4125_l10>; - vddch0-supply = <&pm4125_l22>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi index e69499f77c682..167e15257fcee 100644 --- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -21,3 +21,12 @@ firmware-name = "qcom/shikra/qupv3fw.elf"; status = "okay"; }; + +&uart8 { + + bluetooth { + compatible = "qcom,wcn3988-bt"; + + max-speed = <3200000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 690601da142e0..f2f1d4ace0332 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -35,9 +35,9 @@ }; }; - vreg_bt_3p3_dummy: regulator-bt-3p3-dummy { + vreg_wcn_3p3: regulator-wcn-3p3 { compatible = "regulator-fixed"; - regulator-name = "bt_3p3_dummy"; + regulator-name = "wcn_3p3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -54,6 +54,35 @@ pinctrl-0 = <&lcd_bias_en>; pinctrl-names = "default"; }; + + wcn3988-pmu { + compatible = "qcom,wcn3988-pmu"; + + vddio-supply = <&pm8150_s4>; + vddxo-supply = <&pm8150_l12>; + vddrf-supply = <&pm8150_l8>; + vddch0-supply = <&vreg_wcn_3p3>; + + bt-enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + }; + }; }; &gpu { @@ -200,10 +229,10 @@ status = "okay"; bluetooth { - vddio-supply = <&pm8150_s4>; - vddxo-supply = <&pm8150_l12>; - vddrf-supply = <&pm8150_l8>; - vddch0-supply = <&vreg_bt_3p3_dummy>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 28176b082e470..a513d6cdb6fd9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -2910,14 +2910,6 @@ pinctrl-names = "default"; status = "disabled"; - - bluetooth { - compatible = "qcom,wcn3988-bt"; - - enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; - max-speed = <3200000>; - }; - }; i2c9: i2c@4aa4000 { From 58c1e9f2bcd27425a8acdf031d2859f1a38268a2 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Fri, 22 May 2026 15:45:07 +0530 Subject: [PATCH 1118/1330] arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm Add gpio-reserved-ranges property to the tlmm node for all three Shikra EVK variants (CQM, CQS, IQS) to mark GPIOs used by the SoC internally and not available for general use. Signed-off-by: Anurag Pateriya (cherry picked from commit f85e592b0c3f5e61ae47eab025b1c93da45ebd05) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 2 ++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 2 ++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 170515bb59fab..9b529e33c3e85 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -181,6 +181,8 @@ }; &tlmm { + gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; + lcd_bias_en: lcd-bias-en-state { pins = "gpio151"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index d59005e56c81b..1c931cf2d052a 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -181,6 +181,8 @@ }; &tlmm { + gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; + lcd_bias_en: lcd-bias-en-state { pins = "gpio151"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index f2f1d4ace0332..738167d9c0011 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -199,6 +199,8 @@ }; &tlmm { + gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; + panel_rst_n: panel-rst-n-state { pins = "gpio3"; function = "gpio"; From 0ac431698c63305b341577e1914533915065c9f6 Mon Sep 17 00:00:00 2001 From: Yepuri Siddu Date: Fri, 29 May 2026 11:43:05 +0530 Subject: [PATCH 1119/1330] arm64: dts: qcom: shikra: Fix wcn3988-pmu node on EVK boards Rename bt-enable-gpios to swctrl-gpios, add sw_ctrl_default pinctrl state for gpio88, and add missing vreg_pmu_ch1 (ldo4) regulator to wcn3988-pmu node across cqm-evk, cqs-evk and iqs-evk boards. Signed-off-by: Yepuri Siddu (cherry picked from commit a1e5396e06e971b04509da73634d77848c41865e) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 15 ++++++++++++++- arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 16 +++++++++++++++- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 15 ++++++++++++++- 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 9b529e33c3e85..9cc32ae4d5a62 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -40,12 +40,15 @@ wcn3988-pmu { compatible = "qcom,wcn3988-pmu"; + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + vddio-supply = <&pm4125_l7>; vddxo-supply = <&pm4125_l13>; vddrf-supply = <&pm4125_l10>; vddch0-supply = <&pm4125_l22>; - bt-enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; regulators { vreg_pmu_io: ldo0 { @@ -63,6 +66,10 @@ vreg_pmu_ch0: ldo3 { regulator-name = "vreg_pmu_ch0"; }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; }; }; }; @@ -211,6 +218,12 @@ bias-pull-down; }; + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio88"; + function = "gpio"; + bias-pull-down; + }; + }; &uart0 { diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 1c931cf2d052a..6be3dfee7d554 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -40,12 +40,15 @@ wcn3988-pmu { compatible = "qcom,wcn3988-pmu"; + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + vddio-supply = <&pm4125_l7>; vddxo-supply = <&pm4125_l13>; vddrf-supply = <&pm4125_l10>; vddch0-supply = <&pm4125_l22>; - bt-enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; regulators { vreg_pmu_io: ldo0 { @@ -63,6 +66,10 @@ vreg_pmu_ch0: ldo3 { regulator-name = "vreg_pmu_ch0"; }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; }; }; }; @@ -210,6 +217,13 @@ drive-strength = <2>; bias-pull-down; }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio88"; + function = "gpio"; + bias-pull-down; + }; + }; &uart0 { diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 738167d9c0011..5b082eabfc6bc 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -58,12 +58,15 @@ wcn3988-pmu { compatible = "qcom,wcn3988-pmu"; + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + vddio-supply = <&pm8150_s4>; vddxo-supply = <&pm8150_l12>; vddrf-supply = <&pm8150_l8>; vddch0-supply = <&vreg_wcn_3p3>; - bt-enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; regulators { vreg_pmu_io: ldo0 { @@ -81,6 +84,10 @@ vreg_pmu_ch0: ldo3 { regulator-name = "vreg_pmu_ch0"; }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; }; }; }; @@ -221,6 +228,12 @@ drive-strength = <2>; bias-pull-down; }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio88"; + function = "gpio"; + bias-pull-down; + }; }; &uart0 { From 18722001567c5ca040f9a58348a6b7ff276bd704 Mon Sep 17 00:00:00 2001 From: Sunyun Yang Date: Fri, 8 May 2026 21:40:09 +0800 Subject: [PATCH 1120/1330] drm/bridge: Add Lontium LT9611C(EX/UXD) MIPI DSI to HDMI driver LT9611C(EX/UXD) is an I2C-controlled chip that Receiver signal/dual port mipi dsi and output hdmi, differences in hardware features: - LT9611C: supports 1-port mipi dsi to hdmi 1.4 - LT9611EX: supports 2-port mipi dsi to hdmi 1.4 - LT9611UXD: supports 2-port mipi dsi to hdmi 1.4/2.0 Link : https://lore.kernel.org/lkml/20260508134009.4582-3-syyang@lontium.com/ Signed-off-by: Sunyun Yang Reviewed-by: Dmitry Baryshkov Signed-off-by: Mohit Dsor (cherry picked from commit c78dc5acc49eadb967b44accbfa8b37aead3ee61) --- drivers/gpu/drm/bridge/Kconfig | 18 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/lontium-lt9611c.c | 1241 ++++++++++++++++++++++ 3 files changed, 1260 insertions(+) create mode 100644 drivers/gpu/drm/bridge/lontium-lt9611c.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 297bdf68dfff7..66ca9d44161f9 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -177,6 +177,24 @@ config DRM_LONTIUM_LT9611 HDMI signals Please say Y if you have such hardware. +config DRM_LONTIUM_LT9611C + tristate "Lontium LT9611C DSI/HDMI bridge" + select SND_SOC_HDMI_CODEC if SND_SOC + depends on OF + select CRC8 + select FW_LOADER + select DRM_PANEL_BRIDGE + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_DISPLAY_HELPER + select DRM_DISPLAY_HDMI_STATE_HELPER + select REGMAP_I2C + help + Driver for Lontium DSI to HDMI bridge + chip driver that converts dual DSI and I2S to + HDMI signals + Please say Y if you have such hardware. + config DRM_LONTIUM_LT9611UXC tristate "Lontium LT9611UXC DSI/HDMI bridge" select SND_SOC_HDMI_CODEC if SND_SOC diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index dc2ff31797b36..34113d6c4eb1e 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o +obj-$(CONFIG_DRM_LONTIUM_LT9611C) += lontium-lt9611c.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o obj-$(CONFIG_DRM_LONTIUM_LT8713SX) += lontium-lt8713sx.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o diff --git a/drivers/gpu/drm/bridge/lontium-lt9611c.c b/drivers/gpu/drm/bridge/lontium-lt9611c.c new file mode 100644 index 0000000000000..cb584855fd8f0 --- /dev/null +++ b/drivers/gpu/drm/bridge/lontium-lt9611c.c @@ -0,0 +1,1241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Lontium Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FW_SIZE (64 * 1024) +#define LT_PAGE_SIZE 256 +#define FW_FILE "Lontium/lt9611c_fw.bin" +#define LT9611C_CRC_POLYNOMIAL 0x31 +#define LT9611C_PAGE_CONTROL 0xff + +enum lt9611_chip_type { + CHIP_LT9611C = 0, + CHIP_LT9611EX, + CHIP_LT9611UXD, +}; + +struct lt9611c { + struct device *dev; + struct i2c_client *client; + struct drm_bridge bridge; + struct regmap *regmap; + /* Protects all accesses to registers by stopping the on-chip MCU */ + struct mutex ocm_lock; + struct work_struct work; + struct device_node *dsi0_node; + struct device_node *dsi1_node; + struct mipi_dsi_device *dsi0; + struct mipi_dsi_device *dsi1; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data supplies[2]; + int fw_version; + /* Chip variant: C/EX/UXD */ + enum lt9611_chip_type chip_type; + /* HDMI cable connection status */ + bool hdmi_connected; +}; + +DECLARE_CRC8_TABLE(lt9611c_crc8_table); + +static const struct regmap_range_cfg lt9611c_ranges[] = { + { + .name = "register_range", + .range_min = 0, + .range_max = 0xfe9c, + .selector_reg = LT9611C_PAGE_CONTROL, + .selector_mask = 0xff, + .selector_shift = 0, + .window_start = 0, + .window_len = 0x100, + }, +}; + +static const struct regmap_config lt9611c_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xfe9c, + .ranges = lt9611c_ranges, + .num_ranges = ARRAY_SIZE(lt9611c_ranges), +}; + +static int lt9611c_read_write_flow(struct lt9611c *lt9611c, u8 *params, + unsigned int param_count, u8 *return_buffer, + unsigned int return_count) +{ + int ret; + unsigned int i; + unsigned int temp; + unsigned int max_params = 0xe0dd - 0xe0b0 + 1; + + regmap_write(lt9611c->regmap, 0xe0de, 0x01); + + ret = regmap_read_poll_timeout(lt9611c->regmap, 0xe0ae, temp, + temp == 0x01, 1000, 100 * 1000); + if (ret) + return -ETIMEDOUT; + + for (i = 0; i < param_count && i < max_params; i++) + regmap_write(lt9611c->regmap, 0xe0b0 + i, params[i]); + + regmap_write(lt9611c->regmap, 0xe0de, 0x02); + + ret = regmap_read_poll_timeout(lt9611c->regmap, 0xe0ae, temp, + temp == 0x02, 1000, 100 * 1000); + if (ret) + return -ETIMEDOUT; + + return regmap_bulk_read(lt9611c->regmap, 0xe085, return_buffer, + return_count); +} + +static void lt9611c_config_parameters(struct lt9611c *lt9611c) +{ + const struct reg_sequence seq_write_paras[] = { + REG_SEQ0(0xe0ee, 0x01), + REG_SEQ0(0xe103, 0x3f), /*fifo rst*/ + REG_SEQ0(0xe103, 0xff), + REG_SEQ0(0xe05e, 0xc1), + REG_SEQ0(0xe058, 0x00), + REG_SEQ0(0xe059, 0x50), + REG_SEQ0(0xe05a, 0x10), + REG_SEQ0(0xe05a, 0x00), + REG_SEQ0(0xe058, 0x21), + }; + + regmap_multi_reg_write(lt9611c->regmap, seq_write_paras, ARRAY_SIZE(seq_write_paras)); +} + +static void lt9611c_wren(struct lt9611c *lt9611c) +{ + regmap_write(lt9611c->regmap, 0xe05a, 0x04); + regmap_write(lt9611c->regmap, 0xe05a, 0x00); +} + +static void lt9611c_wrdi(struct lt9611c *lt9611c) +{ + regmap_write(lt9611c->regmap, 0xe05a, 0x08); + regmap_write(lt9611c->regmap, 0xe05a, 0x00); +} + +static void lt9611c_erase_op(struct lt9611c *lt9611c, u32 addr) +{ + const struct reg_sequence seq_write[] = { + REG_SEQ0(0xe0ee, 0x01), + REG_SEQ0(0xe05a, 0x04), + REG_SEQ0(0xe05a, 0x00), + REG_SEQ0(0xe05b, (addr >> 16) & 0xff), + REG_SEQ0(0xe05c, (addr >> 8) & 0xff), + REG_SEQ0(0xe05d, addr & 0xff), + REG_SEQ0(0xe05a, 0x01), + REG_SEQ0(0xe05a, 0x00), + }; + + regmap_multi_reg_write(lt9611c->regmap, seq_write, ARRAY_SIZE(seq_write)); +} + +static void read_flash_reg_status(struct lt9611c *lt9611c, unsigned int *status) +{ + const struct reg_sequence seq_write[] = { + REG_SEQ0(0xe103, 0x3f), + REG_SEQ0(0xe103, 0xff), + REG_SEQ0(0xe05e, 0x40), + REG_SEQ0(0xe056, 0x05), + REG_SEQ0(0xe055, 0x25), + REG_SEQ0(0xe055, 0x01), + REG_SEQ0(0xe058, 0x21), + }; + + regmap_multi_reg_write(lt9611c->regmap, seq_write, ARRAY_SIZE(seq_write)); + + regmap_read(lt9611c->regmap, 0xe05f, status); +} + +static void lt9611c_crc_to_sram(struct lt9611c *lt9611c) +{ + const struct reg_sequence seq_write[] = { + REG_SEQ0(0xe051, 0x00), + REG_SEQ0(0xe055, 0xc0), + REG_SEQ0(0xe055, 0x80), + REG_SEQ0(0xe05e, 0xc0), + REG_SEQ0(0xe058, 0x21), + }; + + regmap_multi_reg_write(lt9611c->regmap, seq_write, ARRAY_SIZE(seq_write)); +} + +static void lt9611c_data_to_sram(struct lt9611c *lt9611c) +{ + const struct reg_sequence seq_write[] = { + REG_SEQ0(0xe051, 0xff), + REG_SEQ0(0xe055, 0x80), + REG_SEQ0(0xe05e, 0xc0), + REG_SEQ0(0xe058, 0x21), + }; + + regmap_multi_reg_write(lt9611c->regmap, seq_write, ARRAY_SIZE(seq_write)); +} + +static void lt9611c_sram_to_flash(struct lt9611c *lt9611c, size_t addr) +{ + const struct reg_sequence seq_write[] = { + REG_SEQ0(0xe05b, (addr >> 16) & 0xff), + REG_SEQ0(0xe05c, (addr >> 8) & 0xff), + REG_SEQ0(0xe05d, addr & 0xff), + REG_SEQ0(0xe05a, 0x30), + REG_SEQ0(0xe05a, 0x00), + }; + + regmap_multi_reg_write(lt9611c->regmap, seq_write, ARRAY_SIZE(seq_write)); +} + +static void lt9611c_block_erase(struct lt9611c *lt9611c) +{ + struct device *dev = lt9611c->dev; + int i; + unsigned int block_num; + unsigned int flash_status = 0; + u32 flash_addr = 0; + + for (block_num = 0; block_num < 2; block_num++) { + flash_addr = (block_num * 0x008000); + lt9611c_erase_op(lt9611c, flash_addr); + msleep(100); + i = 0; + while (1) { + read_flash_reg_status(lt9611c, &flash_status); + if ((flash_status & 0x01) == 0) + break; + + if (i > 50) + break; + + i++; + msleep(50); + } + } + + dev_dbg(dev, "erase flash done.\n"); +} + +static int lt9611c_write_data(struct lt9611c *lt9611c, const struct firmware *fw, size_t addr) +{ + struct device *dev = lt9611c->dev; + int ret; + unsigned int page = 0, num = 0, i = 0; + size_t size, index; + const u8 *data; + u8 value; + + data = fw->data; + size = fw->size; + page = (size + LT_PAGE_SIZE - 1) / LT_PAGE_SIZE; + if (page * LT_PAGE_SIZE > FW_SIZE) { + dev_err(dev, "firmware size out of range\n"); + return -EINVAL; + } + + dev_dbg(dev, "%u pages, total size %zu byte\n", page, size); + + for (num = 0; num < page; num++) { + lt9611c_data_to_sram(lt9611c); + + for (i = 0; i < LT_PAGE_SIZE; i++) { + index = num * LT_PAGE_SIZE + i; + value = (index < size) ? data[index] : 0xff; + + ret = regmap_write(lt9611c->regmap, 0xe059, value); + if (ret < 0) { + dev_err(dev, "write error at page %u, index %u\n", num, i); + return ret; + } + } + + lt9611c_wren(lt9611c); + lt9611c_sram_to_flash(lt9611c, addr); + + addr += LT_PAGE_SIZE; + } + + lt9611c_wrdi(lt9611c); + + return 0; +} + +static int lt9611c_write_crc(struct lt9611c *lt9611c, u8 fw_crc, size_t addr) +{ + struct device *dev = lt9611c->dev; + int ret; + + lt9611c_crc_to_sram(lt9611c); + ret = regmap_write(lt9611c->regmap, 0xe059, fw_crc); + if (ret < 0) { + dev_err(dev, "failed to write crc\n"); + return ret; + } + + lt9611c_wren(lt9611c); + lt9611c_sram_to_flash(lt9611c, addr); + lt9611c_wrdi(lt9611c); + + dev_dbg(dev, "crc 0x%02x written to flash at addr 0x%zx\n", fw_crc, addr); + + return 0; +} + +static void lt9611c_reset(struct lt9611c *lt9611c) +{ + gpiod_set_value_cansleep(lt9611c->reset_gpio, 1); + msleep(20); + + gpiod_set_value_cansleep(lt9611c->reset_gpio, 0); + msleep(20); + + gpiod_set_value_cansleep(lt9611c->reset_gpio, 1); + msleep(400); + + dev_dbg(lt9611c->dev, "lt9611c reset"); +} + +static int lt9611c_upgrade_result(struct lt9611c *lt9611c, u8 fw_crc) +{ + struct device *dev = lt9611c->dev; + unsigned int crc_result; + + regmap_write(lt9611c->regmap, 0xe0ee, 0x01); + regmap_read(lt9611c->regmap, 0xe021, &crc_result); + + if (crc_result != fw_crc) { + dev_err(dev, "lt9611c fw upgrade failed, expected crc=0x%02x, read crc=0x%02x\n", + fw_crc, crc_result); + return -1; + } + + dev_dbg(dev, "lt9611c firmware upgrade success, crc=0x%02x\n", crc_result); + return 0; +} + +static int lt9611c_firmware_upgrade(struct lt9611c *lt9611c) +{ + struct device *dev = lt9611c->dev; + const struct firmware *fw; + u8 *buffer; + size_t total_size = FW_SIZE - 1; + u8 fw_crc; + int ret; + + /* 1. load firmware */ + ret = request_firmware(&fw, FW_FILE, dev); + if (ret) + return dev_err_probe(dev, ret, "failed to load '%s'\n", FW_FILE); + + /* 2. check size */ + if (fw->size > total_size) { + dev_err(dev, "firmware too large (%zu > %zu)\n", fw->size, total_size); + ret = -EINVAL; + goto out_release_fw; + } + dev_dbg(dev, "firmware size: %zu bytes\n", fw->size); + + /* 3. calculate crc8 */ + buffer = kzalloc(total_size, GFP_KERNEL); + if (!buffer) { + ret = -ENOMEM; + goto out_release_fw; + } + + memset(buffer, 0xff, total_size); + memcpy(buffer, fw->data, fw->size); + + fw_crc = crc8(lt9611c_crc8_table, buffer, total_size, 0); + kfree(buffer); + + dev_dbg(dev, "firmware crc: 0x%02x\n", fw_crc); + dev_dbg(dev, "starting firmware upgrade, size: %zu bytes\n", fw->size); + + /* 4. firmware upgrade */ + lt9611c_config_parameters(lt9611c); + lt9611c_block_erase(lt9611c); + + ret = lt9611c_write_data(lt9611c, fw, 0); + if (ret < 0) { + dev_err(dev, "failed to write firmware data\n"); + goto out_release_fw; + } + + ret = lt9611c_write_crc(lt9611c, fw_crc, FW_SIZE - 1); + if (ret < 0) { + dev_err(dev, "failed to write firmware crc\n"); + goto out_release_fw; + } + + /* 5. check upgrade of result */ + lt9611c_reset(lt9611c); + ret = lt9611c_upgrade_result(lt9611c, fw_crc); + +out_release_fw: + release_firmware(fw); + return ret; +} + +static struct lt9611c *bridge_to_lt9611c(struct drm_bridge *bridge) +{ + return container_of(bridge, struct lt9611c, bridge); +} + +/*read only*/ +static const struct lt9611c *bridge_to_lt9611c_const(const struct drm_bridge *bridge) +{ + return container_of(bridge, const struct lt9611c, bridge); +} + +static void lt9611c_lock(struct lt9611c *lt9611c) +{ + mutex_lock(<9611c->ocm_lock); + regmap_write(lt9611c->regmap, 0xe0ee, 0x01); +} + +static void lt9611c_unlock(struct lt9611c *lt9611c) +{ + regmap_write(lt9611c->regmap, 0xe0ee, 0x00); + mutex_unlock(<9611c->ocm_lock); +} + +static irqreturn_t lt9611c_irq_thread_handler(int irq, void *dev_id) +{ + struct lt9611c *lt9611c = dev_id; + struct device *dev = lt9611c->dev; + int ret; + unsigned int irq_status; + u8 cmd[5] = {0x52, 0x48, 0x31, 0x3a, 0x00}; + u8 data[5]; + + guard(mutex)(<9611c->ocm_lock); + + ret = regmap_read(lt9611c->regmap, 0xe084, &irq_status); + if (ret) { + dev_err(dev, "failed to read irq status: %d\n", ret); + return IRQ_HANDLED; + } + + if (!(irq_status & BIT(0))) + return IRQ_HANDLED; + + ret = lt9611c_read_write_flow(lt9611c, cmd, ARRAY_SIZE(cmd), data, ARRAY_SIZE(data)); + if (ret) { + dev_err(dev, "failed to read HPD status\n"); + } else { + lt9611c->hdmi_connected = (data[4] == 0x02); + dev_dbg(dev, "HDMI %s\n", lt9611c->hdmi_connected ? "connected" : "disconnected"); + } + + /*Clear interrupt: hardware requires two writes with delay*/ + regmap_write(lt9611c->regmap, 0xe0df, irq_status & BIT(0)); + usleep_range(10000, 12000); + regmap_write(lt9611c->regmap, 0xe0df, irq_status & (~BIT(0))); + + schedule_work(<9611c->work); + + return IRQ_HANDLED; +} + +static void lt9611c_hpd_work(struct work_struct *work) +{ + struct lt9611c *lt9611c = container_of(work, struct lt9611c, work); + bool connected; + + mutex_lock(<9611c->ocm_lock); + connected = lt9611c->hdmi_connected; + mutex_unlock(<9611c->ocm_lock); + + drm_bridge_hpd_notify(<9611c->bridge, + connected ? connector_status_connected : + connector_status_disconnected); +} + +static int lt9611c_regulator_init(struct lt9611c *lt9611c) +{ + struct device *dev = lt9611c->dev; + int ret; + + lt9611c->supplies[0].supply = "vcc"; + lt9611c->supplies[1].supply = "vdd"; + + ret = devm_regulator_bulk_get(dev, 2, lt9611c->supplies); + + return ret; +} + +static struct mipi_dsi_device *lt9611c_attach_dsi(struct lt9611c *lt9611c, + struct device_node *dsi_node) +{ + const struct mipi_dsi_device_info info = { "lt9611c", 0, NULL }; + struct mipi_dsi_device *dsi; + struct mipi_dsi_host *host; + struct device *dev = lt9611c->dev; + int ret; + + host = of_find_mipi_dsi_host_by_node(dsi_node); + if (!host) + return ERR_PTR(dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n")); + + dsi = devm_mipi_dsi_device_register_full(dev, host, &info); + if (IS_ERR(dsi)) + return ERR_PTR(dev_err_probe(dev, PTR_ERR(dsi), "failed to create dsi device\n")); + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_VIDEO_HSE; + + ret = devm_mipi_dsi_attach(dev, dsi); + if (ret < 0) + return ERR_PTR(dev_err_probe(dev, ret, "failed to attach dsi to host\n")); + + return dsi; +} + +static int lt9611c_bridge_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + + return drm_bridge_attach(encoder, lt9611c->bridge.next_bridge, bridge, flags); +} + +static enum drm_mode_status +lt9611c_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, + const struct drm_display_mode *mode, + unsigned long long tmds_rate) +{ + const struct lt9611c *lt9611c = bridge_to_lt9611c_const(bridge); + + if (lt9611c->chip_type == CHIP_LT9611UXD) { + if (tmds_rate > 600000000) + return MODE_CLOCK_HIGH; + + } else { + if (tmds_rate > 340000000) + return MODE_CLOCK_HIGH; + } + + if (tmds_rate < 25000000) + return MODE_CLOCK_LOW; + + return MODE_OK; +} + +static void lt9611c_video_setup(struct lt9611c *lt9611c, + const struct drm_display_mode *mode) +{ + struct device *dev = lt9611c->dev; + int ret; + u32 h_total, hactive, hsync_len, hfront_porch, hback_porch; + u32 v_total, vactive, vsync_len, vfront_porch, vback_porch; + u8 timing_set_cmd[26] = {0x57, 0x4d, 0x33, 0x3a}; + u8 return_param[3]; + u8 framerate; + u8 vic = 0x00; + + guard(mutex)(<9611c->ocm_lock); + h_total = mode->htotal; + hactive = mode->hdisplay; + hsync_len = mode->hsync_end - mode->hsync_start; + hfront_porch = mode->hsync_start - mode->hdisplay; + hback_porch = mode->htotal - mode->hsync_end; + + v_total = mode->vtotal; + vactive = mode->vdisplay; + vsync_len = mode->vsync_end - mode->vsync_start; + vfront_porch = mode->vsync_start - mode->vdisplay; + vback_porch = mode->vtotal - mode->vsync_end; + framerate = drm_mode_vrefresh(mode); + vic = drm_match_cea_mode(mode); + + dev_dbg(dev, "hactive=%d, vactive=%d\n", hactive, vactive); + dev_dbg(dev, "framerate=%d\n", framerate); + dev_dbg(dev, "vic = 0x%02x\n", vic); + + timing_set_cmd[4] = (h_total >> 8) & 0xff; + timing_set_cmd[5] = h_total & 0xff; + timing_set_cmd[6] = (hactive >> 8) & 0xff; + timing_set_cmd[7] = hactive & 0xff; + timing_set_cmd[8] = (hfront_porch >> 8) & 0xff; + timing_set_cmd[9] = hfront_porch & 0xff; + timing_set_cmd[10] = (hsync_len >> 8) & 0xff; + timing_set_cmd[11] = hsync_len & 0xff; + timing_set_cmd[12] = (hback_porch >> 8) & 0xff; + timing_set_cmd[13] = hback_porch & 0xff; + timing_set_cmd[14] = (v_total >> 8) & 0xff; + timing_set_cmd[15] = v_total & 0xff; + timing_set_cmd[16] = (vactive >> 8) & 0xff; + timing_set_cmd[17] = vactive & 0xFF; + timing_set_cmd[18] = (vfront_porch >> 8) & 0xff; + timing_set_cmd[19] = vfront_porch & 0xff; + timing_set_cmd[20] = (vsync_len >> 8) & 0xff; + timing_set_cmd[21] = vsync_len & 0xff; + timing_set_cmd[22] = (vback_porch >> 8) & 0xff; + timing_set_cmd[23] = vback_porch & 0xff; + timing_set_cmd[24] = framerate; + timing_set_cmd[25] = vic; + + ret = lt9611c_read_write_flow(lt9611c, + timing_set_cmd, ARRAY_SIZE(timing_set_cmd), + return_param, ARRAY_SIZE(return_param)); + if (ret) + dev_err(dev, "video set failed\n"); +} + +static void lt9611c_bridge_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); + if (ret) + dev_err(lt9611c->dev, "regulator bulk enable failed.\n"); + lt9611c_reset(lt9611c); +} + +static void lt9611c_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + struct drm_connector *connector; + struct drm_connector_state *conn_state; + struct drm_crtc_state *crtc_state; + struct drm_display_mode *mode; + + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); + if (WARN_ON(!connector)) + return; + + conn_state = drm_atomic_get_new_connector_state(state, connector); + if (WARN_ON(!conn_state)) + return; + + crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); + if (WARN_ON(!crtc_state)) + return; + + mode = &crtc_state->adjusted_mode; + + lt9611c_video_setup(lt9611c, mode); +} + +static void lt9611c_bridge_atomic_post_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + int ret; + + ret = regulator_bulk_disable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); + if (ret) + dev_err(lt9611c->dev, "regulator bulk disable failed.\n"); + gpiod_set_value_cansleep(lt9611c->reset_gpio, 0); +} + +static enum drm_connector_status +lt9611c_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + struct device *dev = lt9611c->dev; + int ret; + bool connected = false; + u8 cmd[5] = {0x52, 0x48, 0x31, 0x3a, 0x00}; + u8 data[5]; + + guard(mutex)(<9611c->ocm_lock); + + ret = lt9611c_read_write_flow(lt9611c, cmd, ARRAY_SIZE(cmd), data, ARRAY_SIZE(data)); + if (ret) + dev_err(dev, "failed to read HPD status (err=%d)\n", ret); + else + connected = (data[4] == 0x02); + + lt9611c->hdmi_connected = connected; + + return connected ? connector_status_connected : + connector_status_disconnected; +} + +static int lt9611c_get_edid_block(void *data, u8 *buf, + unsigned int block, size_t len) +{ + struct lt9611c *lt9611c = data; + struct device *dev = lt9611c->dev; + u8 cmd[5] = {0x52, 0x48, 0x33, 0x3a, 0x00}; + u8 packet[37]; + int ret, i, offset = 0; + + if (len != 128) + return -EINVAL; + guard(mutex)(<9611c->ocm_lock); + + for (i = 0; i < 4; i++) { + cmd[4] = block * 4 + i; + ret = lt9611c_read_write_flow(lt9611c, cmd, ARRAY_SIZE(cmd), + packet, ARRAY_SIZE(packet)); + if (ret) { + dev_err(dev, "Failed to read EDID block %u packet %d\n", + block, i); + return ret; + } + memcpy(buf + offset, &packet[5], 32); + offset += 32; + } + + return 0; +} + +static const struct drm_edid *lt9611c_bridge_edid_read(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + + return drm_edid_read_custom(connector, lt9611c_get_edid_block, lt9611c); +} + +static int lt9611c_hdmi_write_avi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + u8 *cmd; + u8 data[5]; + int ret; + + guard(mutex)(<9611c->ocm_lock); + + cmd = kmalloc(5 + len, GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + cmd[0] = 0x57; + cmd[1] = 0x48; + cmd[2] = 0x35; + cmd[3] = 0x3a; + cmd[4] = 0x01;/*write avi*/ + memcpy(cmd + 5, buffer, len); + + ret = lt9611c_read_write_flow(lt9611c, cmd, 5 + len, + data, ARRAY_SIZE(data)); + kfree(cmd); + + if (ret < 0) { + dev_err(lt9611c->dev, "write avi infoframe failed!\n"); + return ret; + } + + return 0; +} + +static int lt9611c_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + u8 cmd[5] = {0x57, 0x48, 0x42, 0x3a, 0x01}; + u8 data[5]; + int ret; + + guard(mutex)(<9611c->ocm_lock); + + ret = lt9611c_read_write_flow(lt9611c, cmd, ARRAY_SIZE(cmd), + data, ARRAY_SIZE(data)); + + if (ret < 0) { + dev_err(lt9611c->dev, "clear avi infoframe failed!\n"); + return ret; + } + + return 0; +} + +static int lt9611c_hdmi_write_audio_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + u8 *cmd; + u8 data[5]; + int ret; + + guard(mutex)(<9611c->ocm_lock); + + cmd = kmalloc(5 + len, GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + cmd[0] = 0x57; + cmd[1] = 0x48; + cmd[2] = 0x35; + cmd[3] = 0x3a; + cmd[4] = 0x02;/*write audio*/ + memcpy(cmd + 5, buffer, len); + + ret = lt9611c_read_write_flow(lt9611c, cmd, 5 + len, + data, ARRAY_SIZE(data)); + + kfree(cmd); + + if (ret < 0) { + dev_err(lt9611c->dev, "write audio infoframe failed!\n"); + return ret; + } + + return 0; +} + +static int lt9611c_hdmi_clear_audio_infoframe(struct drm_bridge *bridge) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + u8 cmd[5] = {0x57, 0x48, 0x42, 0x3a, 0x02}; + u8 data[5]; + int ret; + + guard(mutex)(<9611c->ocm_lock); + + ret = lt9611c_read_write_flow(lt9611c, cmd, ARRAY_SIZE(cmd), + data, ARRAY_SIZE(data)); + + if (ret < 0) { + dev_err(lt9611c->dev, "clear audio infoframe failed!\n"); + return ret; + } + + return 0; +} + +static int lt9611c_hdmi_audio_prepare(struct drm_bridge *bridge, + struct drm_connector *connector, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + u8 audio_cmd[6] = {0x57, 0x48, 0x36, 0x3a}; + u8 data[5]; + int ret; + + if (hparms->sample_width == 32) + return -EINVAL; + + switch (fmt->fmt) { + case HDMI_I2S: + audio_cmd[4] = 0x01; + break; + case HDMI_SPDIF: + audio_cmd[4] = 0x02; + break; + default: + return -EINVAL; + } + + audio_cmd[5] = hparms->channels; + guard(mutex)(<9611c->ocm_lock); + + ret = lt9611c_read_write_flow(lt9611c, audio_cmd, sizeof(audio_cmd), + data, sizeof(data)); + if (ret < 0) { + dev_err(lt9611c->dev, "set audio info failed!\n"); + return ret; + } + + return drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, + &hparms->cea); +} + +static void lt9611c_hdmi_audio_shutdown(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector); +} + +static int lt9611c_hdmi_audio_startup(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + return 0; +} + +static const struct drm_bridge_funcs lt9611c_bridge_funcs = { + .attach = lt9611c_bridge_attach, + .detect = lt9611c_bridge_detect, + .edid_read = lt9611c_bridge_edid_read, + .atomic_pre_enable = lt9611c_bridge_atomic_pre_enable, + .atomic_enable = lt9611c_bridge_atomic_enable, + .atomic_post_disable = lt9611c_bridge_atomic_post_disable, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + + .hdmi_tmds_char_rate_valid = lt9611c_hdmi_tmds_char_rate_valid, + .hdmi_write_avi_infoframe = lt9611c_hdmi_write_avi_infoframe, + .hdmi_clear_avi_infoframe = lt9611c_hdmi_clear_avi_infoframe, + .hdmi_write_audio_infoframe = lt9611c_hdmi_write_audio_infoframe, + .hdmi_clear_audio_infoframe = lt9611c_hdmi_clear_audio_infoframe, + + .hdmi_audio_startup = lt9611c_hdmi_audio_startup, + .hdmi_audio_prepare = lt9611c_hdmi_audio_prepare, + .hdmi_audio_shutdown = lt9611c_hdmi_audio_shutdown, +}; + +static int lt9611c_parse_dt(struct device *dev, + struct lt9611c *lt9611c) +{ + lt9611c->dsi0_node = of_graph_get_remote_node(dev->of_node, 0, -1); + if (!lt9611c->dsi0_node) + return dev_err_probe(dev, -ENODEV, "failed to get remote node for primary dsi\n"); + + lt9611c->dsi1_node = of_graph_get_remote_node(dev->of_node, 1, -1); + + return drm_of_find_panel_or_bridge(dev->of_node, 2, -1, NULL, <9611c->bridge.next_bridge); +} + +static int lt9611c_gpio_init(struct lt9611c *lt9611c) +{ + struct device *dev = lt9611c->dev; + + lt9611c->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(lt9611c->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(lt9611c->reset_gpio), + "failed to acquire reset gpio\n"); + + return 0; +} + +static int lt9611c_read_version(struct lt9611c *lt9611c) +{ + u8 buf[2]; + int ret; + + ret = regmap_write(lt9611c->regmap, 0xe0ee, 0x01); + if (ret) + return ret; + + ret = regmap_bulk_read(lt9611c->regmap, 0xe080, buf, ARRAY_SIZE(buf)); + if (ret) + return ret; + + return (buf[0] << 8) | buf[1]; +} + +static int lt9611c_read_chipid(struct lt9611c *lt9611c) +{ + struct device *dev = lt9611c->dev; + u8 chipid[2]; + int ret; + + ret = regmap_write(lt9611c->regmap, 0xe0ee, 0x01); + if (ret) + return ret; + + ret = regmap_bulk_read(lt9611c->regmap, 0xe100, chipid, 2); + if (ret) + return ret; + + if (chipid[0] != 0x23 || chipid[1] != 0x06) { + dev_err(dev, "ChipID: 0x%02x 0x%02x\n", chipid[0], chipid[1]); + return -ENODEV; + } + + return 0; +} + +static ssize_t lt9611c_firmware_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct lt9611c *lt9611c = dev_get_drvdata(dev); + int ret; + + lt9611c_lock(lt9611c); + + ret = lt9611c_firmware_upgrade(lt9611c); + if (ret < 0) + dev_err(dev, "upgrade failure\n"); + + lt9611c_unlock(lt9611c); + + return ret < 0 ? ret : len; +} + +static ssize_t lt9611c_firmware_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct lt9611c *lt9611c = dev_get_drvdata(dev); + + return sysfs_emit(buf, "0x%04x\n", lt9611c->fw_version); +} + +static DEVICE_ATTR_RW(lt9611c_firmware); + +static struct attribute *lt9611c_attrs[] = { + &dev_attr_lt9611c_firmware.attr, + NULL, +}; + +static const struct attribute_group lt9611c_attr_group = { + .attrs = lt9611c_attrs, +}; + +static const struct attribute_group *lt9611c_attr_groups[] = { + <9611c_attr_group, + NULL, +}; + +static int lt9611c_probe(struct i2c_client *client) +{ + const struct i2c_device_id *id = i2c_client_get_device_id(client); + struct lt9611c *lt9611c; + struct device *dev = &client->dev; + bool fw_updated = false; + int ret; + + crc8_populate_msb(lt9611c_crc8_table, LT9611C_CRC_POLYNOMIAL); + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + return dev_err_probe(dev, -ENODEV, "device doesn't support I2C\n"); + + lt9611c = devm_drm_bridge_alloc(dev, struct lt9611c, bridge, <9611c_bridge_funcs); + if (IS_ERR(lt9611c)) + return dev_err_probe(dev, PTR_ERR(lt9611c), "drm bridge alloc failed.\n"); + + lt9611c->dev = dev; + lt9611c->client = client; + lt9611c->chip_type = id->driver_data; + ret = devm_mutex_init(dev, <9611c->ocm_lock); + if (ret) + return dev_err_probe(dev, ret, "failed to init mutex\n"); + + lt9611c->regmap = devm_regmap_init_i2c(client, <9611c_regmap_config); + if (IS_ERR(lt9611c->regmap)) + return dev_err_probe(dev, PTR_ERR(lt9611c->regmap), "regmap i2c init failed\n"); + + ret = lt9611c_parse_dt(dev, lt9611c); + if (ret) + return dev_err_probe(dev, ret, "failed to parse device tree\n"); + + ret = lt9611c_gpio_init(lt9611c); + if (ret < 0) + goto err_of_put; + + ret = lt9611c_regulator_init(lt9611c); + if (ret < 0) + goto err_of_put; + + ret = regulator_bulk_enable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); + if (ret) + goto err_of_put; + + lt9611c_reset(lt9611c); + + lt9611c_lock(lt9611c); + + ret = lt9611c_read_chipid(lt9611c); + if (ret < 0) { + dev_err(dev, "failed to read chip id.\n"); + lt9611c_unlock(lt9611c); + goto err_disable_regulators; + } + +retry: + lt9611c->fw_version = lt9611c_read_version(lt9611c); + if (lt9611c->fw_version < 0) { + dev_err(dev, "failed to read fw version\n"); + ret = -EOPNOTSUPP; + lt9611c_unlock(lt9611c); + goto err_disable_regulators; + + } else if (lt9611c->fw_version == 0) { + if (!fw_updated) { + fw_updated = true; + ret = lt9611c_firmware_upgrade(lt9611c); + if (ret < 0) { + lt9611c_unlock(lt9611c); + goto err_disable_regulators; + } + + goto retry; + + } else { + dev_err(dev, "fw version 0x%04x, update failed\n", lt9611c->fw_version); + ret = -EOPNOTSUPP; + lt9611c_unlock(lt9611c); + goto err_disable_regulators; + } + } + + lt9611c_unlock(lt9611c); + dev_dbg(dev, "current version:0x%04x", lt9611c->fw_version); + + INIT_WORK(<9611c->work, lt9611c_hpd_work); + + ret = devm_request_threaded_irq(&client->dev, client->irq, NULL, + lt9611c_irq_thread_handler, + IRQF_TRIGGER_FALLING | + IRQF_ONESHOT | + IRQF_NO_AUTOEN, + "lt9611c", lt9611c); + if (ret) { + dev_err(dev, "failed to request irq\n"); + goto err_disable_regulators; + } + + lt9611c->bridge.of_node = client->dev.of_node; + lt9611c->bridge.ops = DRM_BRIDGE_OP_DETECT | + DRM_BRIDGE_OP_EDID | + DRM_BRIDGE_OP_HPD | + DRM_BRIDGE_OP_HDMI | + DRM_BRIDGE_OP_HDMI_AUDIO; + lt9611c->bridge.type = DRM_MODE_CONNECTOR_HDMIA; + + lt9611c->bridge.hdmi_audio_dev = dev; + lt9611c->bridge.hdmi_audio_max_i2s_playback_channels = 8; + lt9611c->bridge.hdmi_audio_dai_port = 2; + + devm_drm_bridge_add(dev, <9611c->bridge); + + /* Attach primary DSI */ + lt9611c->dsi0 = lt9611c_attach_dsi(lt9611c, lt9611c->dsi0_node); + if (IS_ERR(lt9611c->dsi0)) { + ret = PTR_ERR(lt9611c->dsi0); + goto err_remove_bridge; + } + + /* Attach secondary DSI, if specified */ + if (lt9611c->dsi1_node) { + lt9611c->dsi1 = lt9611c_attach_dsi(lt9611c, lt9611c->dsi1_node); + if (IS_ERR(lt9611c->dsi1)) { + ret = PTR_ERR(lt9611c->dsi1); + goto err_remove_bridge; + } + } + + lt9611c->hdmi_connected = false; + i2c_set_clientdata(client, lt9611c); + enable_irq(client->irq); + lt9611c_reset(lt9611c); + + return 0; + +err_remove_bridge: + free_irq(client->irq, lt9611c); + cancel_work_sync(<9611c->work); + drm_bridge_remove(<9611c->bridge); + +err_disable_regulators: + regulator_bulk_disable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); + +err_of_put: + of_node_put(lt9611c->dsi1_node); + of_node_put(lt9611c->dsi0_node); + + return ret; +} + +static void lt9611c_remove(struct i2c_client *client) +{ + struct lt9611c *lt9611c = i2c_get_clientdata(client); + + free_irq(client->irq, lt9611c); + cancel_work_sync(<9611c->work); + regulator_bulk_disable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); + of_node_put(lt9611c->dsi1_node); + of_node_put(lt9611c->dsi0_node); +} + +static int lt9611c_bridge_suspend(struct device *dev) +{ + struct lt9611c *lt9611c = dev_get_drvdata(dev); + int ret; + + dev_dbg(lt9611c->dev, "suspend\n"); + disable_irq(lt9611c->client->irq); + ret = regulator_bulk_disable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); + if (ret) { + dev_err(lt9611c->dev, "regulator bulk disable failed.\n"); + return ret; + } + gpiod_set_value_cansleep(lt9611c->reset_gpio, 0); + + return ret; +} + +static int lt9611c_bridge_resume(struct device *dev) +{ + struct lt9611c *lt9611c = dev_get_drvdata(dev); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); + if (ret) { + dev_err(lt9611c->dev, "regulator bulk enable failed.\n"); + return ret; + } + enable_irq(lt9611c->client->irq); + lt9611c_reset(lt9611c); + dev_dbg(lt9611c->dev, "resume\n"); + + return ret; +} + +static const struct dev_pm_ops lt9611c_bridge_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(lt9611c_bridge_suspend, + lt9611c_bridge_resume) +}; + +static struct i2c_device_id lt9611c_id[] = { + /* chip_type */ + { "lontium,lt9611c", 0 }, + { "lontium,lt9611ex", 1 }, + { "lontium,lt9611uxd", 2 }, + { /* sentinel */ } +}; + +static const struct of_device_id lt9611c_match_table[] = { + { .compatible = "lontium,lt9611c" }, + { .compatible = "lontium,lt9611ex" }, + { .compatible = "lontium,lt9611uxd" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, lt9611c_match_table); + +static struct i2c_driver lt9611c_driver = { + .driver = { + .name = "lt9611c", + .of_match_table = lt9611c_match_table, + .pm = <9611c_bridge_pm_ops, + .dev_groups = lt9611c_attr_groups, + }, + .probe = lt9611c_probe, + .remove = lt9611c_remove, + .id_table = lt9611c_id, +}; +module_i2c_driver(lt9611c_driver); + +MODULE_AUTHOR("SunYun Yang "); +MODULE_DESCRIPTION("Lontium LT9611C(EX/UXD) MIPI DSI to HDMI driver"); +MODULE_LICENSE("GPL"); +MODULE_FIRMWARE(FW_FILE); + From eb299c6cd9b990ac74a4d022b1a4098e8f806bdd Mon Sep 17 00:00:00 2001 From: Mohit Dsor Date: Thu, 28 May 2026 21:40:01 +0530 Subject: [PATCH 1121/1330] drm/bridge: Enable LT9611UXD in LT9611C driver Changes to enable lt9611uxd in lt9611c driver. Added support for port selection, enabled hdmi enable gpio and other changes. Signed-off-by: Mohit Dsor (cherry picked from commit 1876296dd06771b2a157f65982aaf08c584d6771) --- drivers/gpu/drm/bridge/lontium-lt9611c.c | 280 ++++++++++++++++++----- 1 file changed, 228 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611c.c b/drivers/gpu/drm/bridge/lontium-lt9611c.c index cb584855fd8f0..4b83322493903 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611c.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611c.c @@ -41,6 +41,13 @@ enum lt9611_chip_type { CHIP_LT9611UXD, }; +enum lt9611c_ports { + PORT_SWAP_A = 0, + PORT_SWAP_B, + PORT_SWAP_AB, + PORT_MAX, +}; + struct lt9611c { struct device *dev; struct i2c_client *client; @@ -54,12 +61,15 @@ struct lt9611c { struct mipi_dsi_device *dsi0; struct mipi_dsi_device *dsi1; struct gpio_desc *reset_gpio; + struct gpio_desc *hdmi_gpio; struct regulator_bulk_data supplies[2]; int fw_version; /* Chip variant: C/EX/UXD */ enum lt9611_chip_type chip_type; /* HDMI cable connection status */ bool hdmi_connected; + /* Selected DSI port configuration */ + int selected_port; }; DECLARE_CRC8_TABLE(lt9611c_crc8_table); @@ -97,7 +107,7 @@ static int lt9611c_read_write_flow(struct lt9611c *lt9611c, u8 *params, regmap_write(lt9611c->regmap, 0xe0de, 0x01); ret = regmap_read_poll_timeout(lt9611c->regmap, 0xe0ae, temp, - temp == 0x01, 1000, 100 * 1000); + temp == 0x01, 1000, 400 * 1000); if (ret) return -ETIMEDOUT; @@ -107,7 +117,7 @@ static int lt9611c_read_write_flow(struct lt9611c *lt9611c, u8 *params, regmap_write(lt9611c->regmap, 0xe0de, 0x02); ret = regmap_read_poll_timeout(lt9611c->regmap, 0xe0ae, temp, - temp == 0x02, 1000, 100 * 1000); + temp == 0x02, 1000, 400 * 1000); if (ret) return -ETIMEDOUT; @@ -115,6 +125,48 @@ static int lt9611c_read_write_flow(struct lt9611c *lt9611c, u8 *params, return_count); } +static int lt9611c_select_port(struct lt9611c *lt9611c, int port_select) +{ + int ret; + u8 set_port_swap_cmd_A[6] = {0x57, 0x4d, 0x31, 0x3a, 0x01, 0xc0}; + u8 set_port_swap_cmd_B[6] = {0x57, 0x4d, 0x31, 0x3a, 0x01, 0x40}; + u8 set_port_swap_cmd_AB[6] = {0x57, 0x4d, 0x31, 0x3a, 0x02, 0xd0}; + u8 set_port_swap_ret[5]; + + if (!lt9611c) + return -EINVAL; + + /* MCU must be running (0xe0ee=0x00) for lt9611c_read_write_flow */ + guard(mutex)(<9611c->ocm_lock); + regmap_write(lt9611c->regmap, 0xe0ee, 0x00); + + switch (port_select) { + case PORT_SWAP_A: + ret = lt9611c_read_write_flow(lt9611c, set_port_swap_cmd_A, + 6, set_port_swap_ret, 5); + if (ret < 0 || set_port_swap_ret[4] == 0) + return ret < 0 ? ret : -EIO; + break; + + case PORT_SWAP_B: + ret = lt9611c_read_write_flow(lt9611c, set_port_swap_cmd_B, + 6, set_port_swap_ret, 5); + if (ret < 0 || set_port_swap_ret[4] == 0) + return ret < 0 ? ret : -EIO; + break; + + case PORT_SWAP_AB: + ret = lt9611c_read_write_flow(lt9611c, set_port_swap_cmd_AB, + 6, set_port_swap_ret, 5); + if (ret < 0 || set_port_swap_ret[4] == 0) + return ret < 0 ? ret : -EIO; + break; + default: + return -EINVAL; + } + return 0; +} + static void lt9611c_config_parameters(struct lt9611c *lt9611c) { const struct reg_sequence seq_write_paras[] = { @@ -436,16 +488,22 @@ static irqreturn_t lt9611c_irq_thread_handler(int irq, void *dev_id) u8 cmd[5] = {0x52, 0x48, 0x31, 0x3a, 0x00}; u8 data[5]; - guard(mutex)(<9611c->ocm_lock); + mutex_lock(<9611c->ocm_lock); + + /* Ensure MCU is running for HPD status query */ + regmap_write(lt9611c->regmap, 0xe0ee, 0x00); ret = regmap_read(lt9611c->regmap, 0xe084, &irq_status); if (ret) { dev_err(dev, "failed to read irq status: %d\n", ret); + mutex_unlock(<9611c->ocm_lock); return IRQ_HANDLED; } - if (!(irq_status & BIT(0))) + if (!(irq_status & BIT(0))) { + mutex_unlock(<9611c->ocm_lock); return IRQ_HANDLED; + } ret = lt9611c_read_write_flow(lt9611c, cmd, ARRAY_SIZE(cmd), data, ARRAY_SIZE(data)); if (ret) { @@ -455,10 +513,11 @@ static irqreturn_t lt9611c_irq_thread_handler(int irq, void *dev_id) dev_dbg(dev, "HDMI %s\n", lt9611c->hdmi_connected ? "connected" : "disconnected"); } - /*Clear interrupt: hardware requires two writes with delay*/ - regmap_write(lt9611c->regmap, 0xe0df, irq_status & BIT(0)); + regmap_write(lt9611c->regmap, 0xe0df, BIT(0)); usleep_range(10000, 12000); - regmap_write(lt9611c->regmap, 0xe0df, irq_status & (~BIT(0))); + regmap_write(lt9611c->regmap, 0xe0df, 0x00); + + mutex_unlock(<9611c->ocm_lock); schedule_work(<9611c->work); @@ -619,10 +678,20 @@ static void lt9611c_bridge_atomic_pre_enable(struct drm_bridge *bridge, struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); int ret; - ret = regulator_bulk_enable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); - if (ret) - dev_err(lt9611c->dev, "regulator bulk enable failed.\n"); - lt9611c_reset(lt9611c); + if (lt9611c->hdmi_gpio) { + gpiod_set_value_cansleep(lt9611c->hdmi_gpio, 1); + msleep(20); + } +// lt9611c_reset(lt9611c); + + /* Reapply port selection after reset */ + if (lt9611c->selected_port >= 0) { + msleep(200); + ret = lt9611c_select_port(lt9611c, lt9611c->selected_port); + if (ret < 0) + dev_err(lt9611c->dev, "failed to reapply port selection: %d\n", ret); + msleep(200); + } } static void lt9611c_bridge_atomic_enable(struct drm_bridge *bridge, @@ -655,12 +724,12 @@ static void lt9611c_bridge_atomic_post_disable(struct drm_bridge *bridge, struct drm_atomic_state *state) { struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); - int ret; - ret = regulator_bulk_disable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); - if (ret) - dev_err(lt9611c->dev, "regulator bulk disable failed.\n"); - gpiod_set_value_cansleep(lt9611c->reset_gpio, 0); + /* Keep chip active for HPD detection */ + mutex_lock(<9611c->ocm_lock); + regmap_write(lt9611c->regmap, 0xe0ee, 0x00); + regmap_write(lt9611c->regmap, 0xe0d0, 0x01); + mutex_unlock(<9611c->ocm_lock); } static enum drm_connector_status @@ -673,7 +742,10 @@ lt9611c_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector u8 cmd[5] = {0x52, 0x48, 0x31, 0x3a, 0x00}; u8 data[5]; - guard(mutex)(<9611c->ocm_lock); + mutex_lock(<9611c->ocm_lock); + + /* Ensure MCU is running for HPD status query */ + regmap_write(lt9611c->regmap, 0xe0ee, 0x00); ret = lt9611c_read_write_flow(lt9611c, cmd, ARRAY_SIZE(cmd), data, ARRAY_SIZE(data)); if (ret) @@ -683,6 +755,8 @@ lt9611c_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector lt9611c->hdmi_connected = connected; + mutex_unlock(<9611c->ocm_lock); + return connected ? connector_status_connected : connector_status_disconnected; } @@ -777,6 +851,59 @@ static int lt9611c_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) return 0; } +static int lt9611c_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + u8 *cmd; + u8 data[5]; + int ret; + + guard(mutex)(<9611c->ocm_lock); + + cmd = kmalloc(5 + len, GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + cmd[0] = 0x57; + cmd[1] = 0x48; + cmd[2] = 0x35; + cmd[3] = 0x3a; + cmd[4] = 0x03;/*write hdmi infoframe*/ + memcpy(cmd + 5, buffer, len); + + ret = lt9611c_read_write_flow(lt9611c, cmd, 5 + len, + data, ARRAY_SIZE(data)); + kfree(cmd); + + if (ret < 0) { + dev_err(lt9611c->dev, "write hdmi infoframe failed!\n"); + return ret; + } + + return 0; +} + +static int lt9611c_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) +{ + struct lt9611c *lt9611c = bridge_to_lt9611c(bridge); + u8 cmd[5] = {0x57, 0x48, 0x42, 0x3a, 0x03}; + u8 data[5]; + int ret; + + guard(mutex)(<9611c->ocm_lock); + + ret = lt9611c_read_write_flow(lt9611c, cmd, ARRAY_SIZE(cmd), + data, ARRAY_SIZE(data)); + + if (ret < 0) { + dev_err(lt9611c->dev, "clear hdmi infoframe failed!\n"); + return ret; + } + + return 0; +} + static int lt9611c_hdmi_write_audio_infoframe(struct drm_bridge *bridge, const u8 *buffer, size_t len) { @@ -895,6 +1022,8 @@ static const struct drm_bridge_funcs lt9611c_bridge_funcs = { .hdmi_tmds_char_rate_valid = lt9611c_hdmi_tmds_char_rate_valid, .hdmi_write_avi_infoframe = lt9611c_hdmi_write_avi_infoframe, .hdmi_clear_avi_infoframe = lt9611c_hdmi_clear_avi_infoframe, + .hdmi_write_hdmi_infoframe = lt9611c_hdmi_write_hdmi_infoframe, + .hdmi_clear_hdmi_infoframe = lt9611c_hdmi_clear_hdmi_infoframe, .hdmi_write_audio_infoframe = lt9611c_hdmi_write_audio_infoframe, .hdmi_clear_audio_infoframe = lt9611c_hdmi_clear_audio_infoframe, @@ -924,6 +1053,11 @@ static int lt9611c_gpio_init(struct lt9611c *lt9611c) return dev_err_probe(dev, PTR_ERR(lt9611c->reset_gpio), "failed to acquire reset gpio\n"); + lt9611c->hdmi_gpio = devm_gpiod_get_optional(dev, "hdmi", GPIOD_OUT_LOW); + if (IS_ERR(lt9611c->hdmi_gpio)) + return dev_err_probe(dev, PTR_ERR(lt9611c->hdmi_gpio), + "failed to acquire hdmi gpio\n"); + return 0; } @@ -1007,7 +1141,6 @@ static const struct attribute_group *lt9611c_attr_groups[] = { static int lt9611c_probe(struct i2c_client *client) { - const struct i2c_device_id *id = i2c_client_get_device_id(client); struct lt9611c *lt9611c; struct device *dev = &client->dev; bool fw_updated = false; @@ -1024,7 +1157,7 @@ static int lt9611c_probe(struct i2c_client *client) lt9611c->dev = dev; lt9611c->client = client; - lt9611c->chip_type = id->driver_data; + lt9611c->chip_type = (enum lt9611_chip_type)(uintptr_t)of_device_get_match_data(dev); ret = devm_mutex_init(dev, <9611c->ocm_lock); if (ret) return dev_err_probe(dev, ret, "failed to init mutex\n"); @@ -1041,15 +1174,13 @@ static int lt9611c_probe(struct i2c_client *client) if (ret < 0) goto err_of_put; - ret = lt9611c_regulator_init(lt9611c); - if (ret < 0) - goto err_of_put; - - ret = regulator_bulk_enable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); - if (ret) - goto err_of_put; + if (lt9611c->hdmi_gpio) { + gpiod_set_value_cansleep(lt9611c->hdmi_gpio, 1); + msleep(20); + } lt9611c_reset(lt9611c); + msleep(300); lt9611c_lock(lt9611c); @@ -1076,7 +1207,6 @@ static int lt9611c_probe(struct i2c_client *client) lt9611c_unlock(lt9611c); goto err_disable_regulators; } - goto retry; } else { @@ -1088,13 +1218,25 @@ static int lt9611c_probe(struct i2c_client *client) } lt9611c_unlock(lt9611c); + + /* Select port B so the chip is configured for the correct DSI input */ + msleep(200); + ret = lt9611c_select_port(lt9611c, PORT_SWAP_B); + if (ret < 0) { + dev_warn(dev, "port B selection failed (%d), HPD may not work\n", ret); + lt9611c->selected_port = -1; + } else { + lt9611c->selected_port = PORT_SWAP_B; + } + msleep(200); + dev_dbg(dev, "current version:0x%04x", lt9611c->fw_version); INIT_WORK(<9611c->work, lt9611c_hpd_work); ret = devm_request_threaded_irq(&client->dev, client->irq, NULL, lt9611c_irq_thread_handler, - IRQF_TRIGGER_FALLING | + IRQF_TRIGGER_RISING | IRQF_ONESHOT | IRQF_NO_AUTOEN, "lt9611c", lt9611c); @@ -1111,6 +1253,20 @@ static int lt9611c_probe(struct i2c_client *client) DRM_BRIDGE_OP_HDMI_AUDIO; lt9611c->bridge.type = DRM_MODE_CONNECTOR_HDMIA; + lt9611c->bridge.vendor = "Lontium"; + switch (lt9611c->chip_type) { + case CHIP_LT9611C: + lt9611c->bridge.product = "LT9611C"; + break; + case CHIP_LT9611EX: + lt9611c->bridge.product = "LT9611EX"; + break; + case CHIP_LT9611UXD: + default: + lt9611c->bridge.product = "LT9611UXD"; + break; + } + lt9611c->bridge.hdmi_audio_dev = dev; lt9611c->bridge.hdmi_audio_max_i2s_playback_channels = 8; lt9611c->bridge.hdmi_audio_dai_port = 2; @@ -1135,19 +1291,33 @@ static int lt9611c_probe(struct i2c_client *client) lt9611c->hdmi_connected = false; i2c_set_clientdata(client, lt9611c); + + /* Enable HPD interrupt in the chip */ + { + unsigned int irq_status; + + mutex_lock(<9611c->ocm_lock); + regmap_write(lt9611c->regmap, 0xe0ee, 0x01); + regmap_read(lt9611c->regmap, 0xe084, &irq_status); + if (irq_status) { + regmap_write(lt9611c->regmap, 0xe0df, irq_status); + msleep(20); + regmap_write(lt9611c->regmap, 0xe0df, 0x00); + } + regmap_write(lt9611c->regmap, 0xe0d0, 0x01); + regmap_write(lt9611c->regmap, 0xe0ee, 0x00); + mutex_unlock(<9611c->ocm_lock); + } + enable_irq(client->irq); - lt9611c_reset(lt9611c); + msleep(100); return 0; err_remove_bridge: - free_irq(client->irq, lt9611c); cancel_work_sync(<9611c->work); - drm_bridge_remove(<9611c->bridge); err_disable_regulators: - regulator_bulk_disable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); - err_of_put: of_node_put(lt9611c->dsi1_node); of_node_put(lt9611c->dsi0_node); @@ -1159,9 +1329,11 @@ static void lt9611c_remove(struct i2c_client *client) { struct lt9611c *lt9611c = i2c_get_clientdata(client); - free_irq(client->irq, lt9611c); + /* + * IRQ was requested with devm_request_threaded_irq and is freed + * automatically by devres — do NOT call free_irq() here. + */ cancel_work_sync(<9611c->work); - regulator_bulk_disable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); of_node_put(lt9611c->dsi1_node); of_node_put(lt9611c->dsi0_node); } @@ -1169,18 +1341,14 @@ static void lt9611c_remove(struct i2c_client *client) static int lt9611c_bridge_suspend(struct device *dev) { struct lt9611c *lt9611c = dev_get_drvdata(dev); - int ret; dev_dbg(lt9611c->dev, "suspend\n"); disable_irq(lt9611c->client->irq); - ret = regulator_bulk_disable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); - if (ret) { - dev_err(lt9611c->dev, "regulator bulk disable failed.\n"); - return ret; - } gpiod_set_value_cansleep(lt9611c->reset_gpio, 0); + if (lt9611c->hdmi_gpio) + gpiod_set_value_cansleep(lt9611c->hdmi_gpio, 0); - return ret; + return 0; } static int lt9611c_bridge_resume(struct device *dev) @@ -1188,16 +1356,25 @@ static int lt9611c_bridge_resume(struct device *dev) struct lt9611c *lt9611c = dev_get_drvdata(dev); int ret; - ret = regulator_bulk_enable(ARRAY_SIZE(lt9611c->supplies), lt9611c->supplies); - if (ret) { - dev_err(lt9611c->dev, "regulator bulk enable failed.\n"); - return ret; + if (lt9611c->hdmi_gpio) { + gpiod_set_value_cansleep(lt9611c->hdmi_gpio, 1); + msleep(20); } - enable_irq(lt9611c->client->irq); lt9611c_reset(lt9611c); + + /* Reapply port selection after reset, same as atomic_pre_enable */ + if (lt9611c->selected_port >= 0) { + msleep(200); + ret = lt9611c_select_port(lt9611c, lt9611c->selected_port); + if (ret < 0) + dev_warn(lt9611c->dev, "resume: failed to reapply port selection, ret=%d\n", ret); + msleep(200); + } + + enable_irq(lt9611c->client->irq); dev_dbg(lt9611c->dev, "resume\n"); - return ret; + return 0; } static const struct dev_pm_ops lt9611c_bridge_pm_ops = { @@ -1214,9 +1391,9 @@ static struct i2c_device_id lt9611c_id[] = { }; static const struct of_device_id lt9611c_match_table[] = { - { .compatible = "lontium,lt9611c" }, - { .compatible = "lontium,lt9611ex" }, - { .compatible = "lontium,lt9611uxd" }, + { .compatible = "lontium,lt9611c", .data = (void *)CHIP_LT9611C }, + { .compatible = "lontium,lt9611ex", .data = (void *)CHIP_LT9611EX }, + { .compatible = "lontium,lt9611uxd", .data = (void *)CHIP_LT9611UXD }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, lt9611c_match_table); @@ -1238,4 +1415,3 @@ MODULE_AUTHOR("SunYun Yang "); MODULE_DESCRIPTION("Lontium LT9611C(EX/UXD) MIPI DSI to HDMI driver"); MODULE_LICENSE("GPL"); MODULE_FIRMWARE(FW_FILE); - From a340ff7256ea9e8aabdb572baeb4bde1958eb845 Mon Sep 17 00:00:00 2001 From: Mohit Dsor Date: Thu, 28 May 2026 22:04:24 +0530 Subject: [PATCH 1122/1330] arm64: defconfig: Enable LT9611C bridge driver This driver provides access to LT9611C bridge driver to access Lontium LT9611UXD DSI to HDMI chip. Signed-off-by: Mohit Dsor (cherry picked from commit ce4b9e888e6098412e046f770901c10eae838303) --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8db2f38dc16e3..8e12adfefb9f6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1013,6 +1013,7 @@ CONFIG_DRM_LONTIUM_LT8713SX=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9211=m CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611C=m CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=m CONFIG_DRM_NWL_MIPI_DSI=m From 439e286ac4659c287f3a192eed967b689d54df4a Mon Sep 17 00:00:00 2001 From: Aastha Pandey Date: Fri, 29 May 2026 14:25:45 +0530 Subject: [PATCH 1123/1330] arm64: dts: qcom: shikra: Add GPU cooling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when reaching 115°C. Signed-off-by: Aastha Pandey (cherry picked from commit ce608bd50df182f40501ca742697cbb5caed22d6) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a513d6cdb6fd9..5f6f60bfd2a49 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -4555,6 +4555,7 @@ }; gpuss-thermal { + polling-delay-passive = <10>; thermal-sensors = <&tsens0 6>; trips { @@ -4564,12 +4565,25 @@ type = "hot"; }; - gpuss-critical { + gpuss_alert0: gpuss-alert0 { temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpuss-critical { + temperature = <120000>; hysteresis = <0>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-thermal { From 022e28e2f6e3de84e303b75464b8d187d225ed5b Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Fri, 29 May 2026 15:12:22 +0530 Subject: [PATCH 1124/1330] QCLINUX: arm64: configs: enable USB configfs UVC and UAC2 functions Enable USB configfs support for UVC (USB Video Class) and UAC2 (USB Audio Class 2) function drivers in the Qualcomm ARM64 defconfig. This allows the platform to expose video and audio gadget functions via configfs, enabling use cases such as USB camera and audio device emulation over gadget mode. These options are required for test and development scenarios involving multimedia streaming over USB. Signed-off-by: Pratham Pratap (cherry picked from commit c8f71c6be43ccb516c7f1840b0b874c9b0e4fe3d) --- arch/arm64/configs/qcom.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 60b55f3d2e0a8..62142b5caeec2 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -66,6 +66,8 @@ CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y CONFIG_UHID=m +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_UAC2=y CONFIG_VCPU_STALL_DETECTOR=y CONFIG_VHOST_NET=y CONFIG_VHOST_VSOCK=y From d8066037c7039d5e73f76ded91b8597572667cf8 Mon Sep 17 00:00:00 2001 From: Mohit Dsor Date: Thu, 28 May 2026 22:09:13 +0530 Subject: [PATCH 1125/1330] Revert "arm64: dts: qcom: shikra-iqs-evk: Add pinctrl for DLC0697 DSI panel" This reverts commit 7aa3e6667b315fae478317d505b75023a51360b6. Shikra-IQS-EVK needs DSI-HDMI in place of DSI Panel. Signed-off-by: Mohit Dsor (cherry picked from commit 4639d6f4464970b5147fdedb8a117e25246201c5) --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 5b082eabfc6bc..f5435d1727d21 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -208,27 +208,6 @@ &tlmm { gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; - panel_rst_n: panel-rst-n-state { - pins = "gpio3"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - panel_rst_n_suspend: panel-rst-n-suspend-state { - pins = "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - panel_te_pin: panel-te-pin-state { - pins = "gpio86"; - function = "mdp_vsync_p"; - drive-strength = <2>; - bias-pull-down; - }; - sw_ctrl_default: sw-ctrl-default-state { pins = "gpio88"; function = "gpio"; From 50d4aff9d32c92778ecf6606be94479f1baaf378 Mon Sep 17 00:00:00 2001 From: Mohit Dsor Date: Thu, 28 May 2026 22:20:21 +0530 Subject: [PATCH 1126/1330] Revert "arm64: dts: qcom: shikra-iqs-evk: Add DSI panel support" This reverts commit 872330a93c804b1c2afede355d49f64a29e91f2d. Shikra-IQS-EVK needs DSI-HDMI in place of DSI Panel. Signed-off-by: Mohit Dsor (cherry picked from commit e5fd4c5dab8aba0b182e60f15edcaf0b9bcd278d) --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 66 --------------------- 1 file changed, 66 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index f5435d1727d21..a790954a99853 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -43,18 +43,6 @@ regulator-always-on; }; - lcd_bias: regulator-lcd-bias { - compatible = "regulator-fixed"; - regulator-name = "lcd_bias"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&pm8150_l17>; - gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-0 = <&lcd_bias_en>; - pinctrl-names = "default"; - }; - wcn3988-pmu { compatible = "qcom,wcn3988-pmu"; @@ -100,60 +88,6 @@ firmware-name = "qcom/shikra/a704_zap.mbn"; }; -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - vdda-supply = <&pm8150_l11>; - status = "okay"; - - panel@0 { - compatible = "dlc,dlc0697"; - reg = <0>; - - reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; - enable-gpios = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; - - vddio-supply = <&pm8150_l15>; - bias-supply = <&lcd_bias>; - - pinctrl-0 = <&panel_rst_n &panel_te_pin>; - pinctrl-1 = <&panel_rst_n_suspend>; - pinctrl-names = "default", "sleep"; - - port { - panel_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - }; -}; - -&mdss_dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&mdss_dsi0_phy { - status = "okay"; -}; - -&pm8150_gpios { - lcd_bias_en: lcd-bias-en-state { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - bias-disable; - }; -}; - -&pm8150_l11 { - /* DSI VDDA - must be at NOM voltage for PHY PLL lock */ - regulator-min-microvolt = <1232000>; - regulator-max-microvolt = <1232000>; - regulator-allow-set-load; -}; - &remoteproc_cdsp { firmware-name = "qcom/shikra/cdsp.mbn"; From 22f4c82d6c755926e0700694af95c4efbcb39fb0 Mon Sep 17 00:00:00 2001 From: Mohit Dsor Date: Thu, 28 May 2026 22:29:08 +0530 Subject: [PATCH 1127/1330] arm64: dts: qcom: shikra: Add lt9611uxd node to IQS EVK board Added lt9611uxd node to iqs evk board and done changes like regulators and gpios needed for it. Signed-off-by: Mohit Dsor (cherry picked from commit 9896f69f0a1205466ce2703a95a21f53b55968b8) --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 105 ++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index a790954a99853..f61e96d36c269 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -8,6 +8,7 @@ #include "shikra-iqs-som.dtsi" #include "shikra-evk.dtsi" #include +#include / { model = "Qualcomm Technologies, Inc. Shikra IQS EVK"; @@ -25,7 +26,30 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + regulators { + lcd_bias: regulator-lcd-bias { + compatible = "regulator-fixed"; + regulator-name = "lcd_bias"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pm8150_l17>; + gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_bias_en>; + pinctrl-names = "default"; + }; + vreg_wlan_3p3_dummy: regulator-wlan-3p3-dummy { compatible = "regulator-fixed"; regulator-name = "wlan_3p3_dummy"; @@ -88,6 +112,71 @@ firmware-name = "qcom/shikra/a704_zap.mbn"; }; +&i2c4 { + status = "okay"; + + lt9611uxd: lt,lt9611uxd@41 { + compatible = "lontium,lt9611uxd"; + reg = <0x41>; + interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; + hdmi-gpios = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + }; + + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8150_l11>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pm8150_gpios { + lcd_bias_en: lcd-bias-en-state { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &remoteproc_cdsp { firmware-name = "qcom/shikra/cdsp.mbn"; @@ -142,6 +231,22 @@ &tlmm { gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-disable; /* push-pull output: chip drives both HIGH and LOW */ + input-enable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <8>; + output-high; + input-disable; + }; + sw_ctrl_default: sw-ctrl-default-state { pins = "gpio88"; function = "gpio"; From 2cde66cf0e8769eae45b7447885def6062bd12c7 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 29 May 2026 19:42:31 +0530 Subject: [PATCH 1128/1330] soc: qcom: llcc: Add configuration data for Shikra SoC Add Last Level Cache table and configs for the Shikra SoC. Signed-off-by: Komal Bajaj (cherry picked from commit c4f07b31a7fecd9971bdfe09842de83e45b1f609) --- drivers/soc/qcom/llcc-qcom.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index b80d3f9cff641..f933a5eee8cc2 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1966,6 +1966,20 @@ static const struct llcc_slice_config sdm845_data[] = {{ }, }; +static const struct llcc_slice_config shikra_data[] = { + { + .usecase_id = LLCC_ECC, + .slice_id = 26, + .max_cap = 256, + .priority = 3, + .fixed_size = true, + .bonus_ways = 0x3, + .cache_mode = 0, + .activate_on_init = true, + .vict_prio = true, + }, +}; + static const struct llcc_slice_config sm6350_data[] = { { .usecase_id = LLCC_CPUSS, @@ -4207,6 +4221,15 @@ static const struct qcom_llcc_config sdm845_cfg[] = { }, }; +static const struct qcom_llcc_config shikra_cfg[] = { + { + .sct_data = shikra_data, + .size = ARRAY_SIZE(shikra_data), + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, +}; + static const struct qcom_llcc_config sm6350_cfg[] = { { .sct_data = sm6350_data, @@ -4369,6 +4392,11 @@ static const struct qcom_sct_config sdm845_cfgs = { .num_config = ARRAY_SIZE(sdm845_cfg), }; +static const struct qcom_sct_config shikra_cfgs = { + .llcc_config = shikra_cfg, + .num_config = ARRAY_SIZE(shikra_cfg), +}; + static const struct qcom_sct_config sm6350_cfgs = { .llcc_config = sm6350_cfg, .num_config = ARRAY_SIZE(sm6350_cfg), @@ -5161,6 +5189,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs }, { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs }, + { .compatible = "qcom,shikra-llcc", .data = &shikra_cfgs }, { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs }, { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs }, From 24139ecad482e39dad5267c1c838447cf9e5da5f Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Fri, 29 May 2026 13:40:45 +0530 Subject: [PATCH 1129/1330] FROMLIST: mmc: sdhci-msm: Set ice clk rate Set ice clk rate from sdhci msm platform driver, needed for target which are having legacy ice support, and need sdhci msm platform driver to set rate. Link: https://lore.kernel.org/all/20260529081045.2877910-2-ram.gupta@oss.qualcomm.com/ Signed-off-by: Ram Prakash Gupta Signed-off-by: Pradeep P V K (cherry picked from commit 02b47c255b4029dd2da14e3351f46ccf40ce4194) --- drivers/mmc/host/sdhci-msm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 111a437244d6b..ca4ee864f5ca5 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -275,6 +275,7 @@ struct sdhci_msm_host { /* core, iface, cal and sleep clocks */ struct clk_bulk_data bulk_clks[4]; #ifdef CONFIG_MMC_CRYPTO + struct clk *ice_clk; /* ICE clock */ struct qcom_ice *ice; #endif unsigned long clk_rate; @@ -2659,6 +2660,17 @@ static int sdhci_msm_probe(struct platform_device *pdev) return ret; } +#ifdef CONFIG_MMC_CRYPTO + /* Setup ICE clock */ + msm_host->ice_clk = devm_clk_get(&pdev->dev, "ice"); + if (!IS_ERR(msm_host->ice_clk)) { + /* Vote for max. clk rate for max. performance */ + ret = clk_set_rate(msm_host->ice_clk, INT_MAX); + if (ret) + dev_err(&pdev->dev, "ice clk set rate failed (%d)\n", ret); + } +#endif + /* Setup main peripheral bus clock */ clk = devm_clk_get(&pdev->dev, "iface"); if (IS_ERR(clk)) { From 118b98b0d4d97a1e162bd213899fb7beac913ae8 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Mon, 1 Jun 2026 09:21:59 +0800 Subject: [PATCH 1130/1330] arm64: dts: qcom: shikra: migrate WiFi power control to pwrseq Switch WiFi supply nodes to PMU regulators and move power control from driver to pwrseq, aligning with the Bluetooth power model. Also remove unused dummy WLAN 3.3V regulator. Signed-off-by: Miaoqing Pan (cherry picked from commit 94eb471718d95c27e31f0c7edf5a206aa704fa12) --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 6 +++--- arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 6 +++--- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 14 +++----------- 3 files changed, 9 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 9cc32ae4d5a62..e0fab065aea12 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -268,9 +268,9 @@ &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; - vdd-1.8-xo-supply = <&pm4125_l13>; - vdd-1.3-rfa-supply = <&pm4125_l10>; - vdd-3.3-ch0-supply = <&pm4125_l22>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; qcom,calibration-variant = "Shikra_EVK"; firmware-name = "cq2390"; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 6be3dfee7d554..c9dea2c921856 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -272,9 +272,9 @@ &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; - vdd-1.8-xo-supply = <&pm4125_l13>; - vdd-1.3-rfa-supply = <&pm4125_l10>; - vdd-3.3-ch0-supply = <&pm4125_l22>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; qcom,calibration-variant = "Shikra_EVK"; firmware-name = "cq2390"; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index f61e96d36c269..96fd3f168fa16 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -49,14 +49,6 @@ pinctrl-0 = <&lcd_bias_en>; pinctrl-names = "default"; }; - - vreg_wlan_3p3_dummy: regulator-wlan-3p3-dummy { - compatible = "regulator-fixed"; - regulator-name = "wlan_3p3_dummy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; }; vreg_wcn_3p3: regulator-wcn-3p3 { @@ -292,9 +284,9 @@ &wifi { vdd-0.8-cx-mx-supply = <&pm8150_s4>; - vdd-1.8-xo-supply = <&pm8150_l12>; - vdd-1.3-rfa-supply = <&pm8150_l8>; - vdd-3.3-ch0-supply = <&vreg_wlan_3p3_dummy>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; qcom,calibration-variant = "Shikra_EVK"; firmware-name = "cq2390"; From 5edd65f4bfbce05834a12e2a4e069cc18bc8e084 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Mon, 25 May 2026 16:12:08 +0530 Subject: [PATCH 1131/1330] FROMLIST: serial: qcom_geni: Fix RX DMA stall when SE_DMA_RX_LEN_IN is zero In qcom_geni_serial_handle_rx_dma(), geni_se_rx_dma_unprep() clears port->rx_dma_addr before SE_DMA_RX_LEN_IN is read. If the register is zero, for example when the RX stale counter fires on an idle line, the handler returns without calling geni_se_rx_dma_prep(). The next RX DMA interrupt then hits the !port->rx_dma_addr guard and returns immediately, so the RX DMA buffer is never rearmed and later input is lost. Keep the handler on the rearm path when rx_in is zero. Warn about the unexpected zero-length DMA completion, skip received-data handling, and always call geni_se_rx_dma_prep(). Link: https://lore.kernel.org/all/20260528-serial-rx-0-byte-fix-v1-1-dc4e876c7368@oss.qualcomm.com/ Fixes: 2aaa43c70778 ("tty: serial: qcom-geni-serial: add support for serial engine DMA") Signed-off-by: Viken Dadhaniya (cherry picked from commit 07adbc9a90e022f1ca39001e1e8202b270f0ff34) --- drivers/tty/serial/qcom_geni_serial.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 774c0b7f8508c..9d372db5216fc 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -904,12 +904,9 @@ static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) port->rx_dma_addr = 0; rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); - if (!rx_in) { - dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); - return; - } - - if (!drop) + if (!rx_in) + dev_warn_ratelimited(uport->dev, "serial engine reports 0 RX bytes in!\n"); + else if (!drop) handle_rx_uart(uport, rx_in); ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, From 84fae4656bd326fa2f43222ad78d0798156a8c67 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Fri, 29 May 2026 19:53:11 +0530 Subject: [PATCH 1132/1330] FROMLIST: arm64: dts: qcom: sm8750: add reboot-mode support Add PSCI SYSTEM_RESET2 reboot-modes for sm8750-mtp and sm8750-qrd for use by the psci-reboot-mode driver. The following modes are defined: - bootloader: reboot into fastboot mode for fastboot flashing. - edl: reboot into emergency download mode for image loading via the Firehose protocol. Link: https://lore.kernel.org/r/20260529-psci_sys_reset-dt-changes-for-pakala-v2-1-1964ebf1924c@oss.qualcomm.com Signed-off-by: Anurag Pateriya (cherry picked from commit d7f29faab25794e50a846cbae1bc4bd450c80c14) --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 7 +++++++ arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 7 +++++++ arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 69ebd0138db70..f2afdc2366fde 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -1374,3 +1374,10 @@ status = "okay"; }; + +&psci { + reboot-mode { + mode-bootloader = <0x80010001 0x2>; + mode-edl = <0x80000000 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index 801c46d556022..795d0d34e47ef 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -1154,3 +1154,10 @@ status = "okay"; }; + +&psci { + reboot-mode { + mode-bootloader = <0x80010001 0x2>; + mode-edl = <0x80000000 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index bb7a8bfb05561..32b8ebec41db3 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -263,7 +263,7 @@ interrupts = ; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; From a8accd7ab77a526adcdcaf024e1eb80f748ed9d2 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Fri, 22 May 2026 18:13:59 +0530 Subject: [PATCH 1133/1330] PENDING: arm64: dts: qcom: shikra: add reboot-mode support Add reboot-mode child nodes to shikra-evk.dtsi to configure fastboot (mode-bootloader) and EDL (mode-edl) reboot modes, since all EVK board DTS files include this shared DTSI. Signed-off-by: Anurag Pateriya (cherry picked from commit 90df8a960d0300b35f8a7b9bbdc38c4280e32a9a) --- arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 7 +++++++ arch/arm64/boot/dts/qcom/shikra.dtsi | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi index 167e15257fcee..99f88fb48e808 100644 --- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -17,6 +17,13 @@ status = "okay"; }; +&psci { + reboot-mode { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; +}; + &qupv3_0 { firmware-name = "qcom/shikra/qupv3fw.elf"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 5f6f60bfd2a49..4337a8ee49b4e 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -281,6 +281,11 @@ interrupts = ; }; + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + rpm: remoteproc { compatible = "qcom,shikra-rpm-proc", "qcom,rpm-proc"; From 073bfc7b5c28bde37582fcff7daf9c605ae19210 Mon Sep 17 00:00:00 2001 From: Sushrut Shree Trivedi Date: Thu, 30 Apr 2026 10:12:18 +0530 Subject: [PATCH 1134/1330] FROMLIST: pci: quirks: Advertise D3cold capability for UPD720201 PCIe-to-USB bridge UPD720201 does not advertise D3cold support until firmware is loaded post pci enumeration. This results in upd blocking D3cold entry during system suspend and causing overall failure to enter XO shutdown. Hence, add a quirk to advertise D3cold PME capability since the HW actually supports and advertises it post firmware loading. Link: https://lore.kernel.org/all/20260430-d3cold_support-v1-1-6734f280c481@oss.qualcomm.com/ Signed-off-by: Sushrut Shree Trivedi (cherry picked from commit 2557ced2fdda1e9364140ee861bf5807a331def3) --- drivers/pci/quirks.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index bcdf8b51d183b..737bc37f54943 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6401,3 +6401,13 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); #endif + +/* + * Renesas PCIe-to-USB bridge UPD720201 does not advertise D3cold + * capability by default until firmware is loaded post-enumeration. + */ +static void quirk_enable_d3cold(struct pci_dev *dev) +{ + dev->pme_support = dev->pme_support | (1 << PCI_D3cold); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RENESAS, 0x0014, quirk_enable_d3cold); From c1aeef971687725300ce320b732e55956a2067ba Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Mon, 11 May 2026 15:14:22 +0530 Subject: [PATCH 1135/1330] FROMLIST: usb: dwc3: qcom: Modify interrupt handling for eUSB2 Phy targets eUSB2 targets handle wakeup interrupts differently depending on device speed when operating in host mode. According to the eUSB2 specification, remote wakeup signaling in host mode is detected via different data-line assertions based on the connected device speed. When a low-speed device is connected, the host repeater drives eD+ to logic '1' upon detecting a K-state on the USB lines during remote wakeup (eUSB2 specification, Section 5.5.14). When a full-speed or high-speed device is connected, the host repeater drives eD- to logic '1' upon detecting a K-state on the USB line during remote wakeup (eUSB2 specification, Sections 5.5.15 and 5.5.18). Since the eUSB2 PHY's "DP" and "DM" interrupt lines monitor the eD+ and eD- line states, configure the wakeup interrupts accordingly Link: https://lore.kernel.org/all/20260511094422.3561509-1-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati Signed-off-by: Pratham Pratap (cherry picked from commit e929e6d4fe8556b3d25732242a7e516947983723) --- drivers/usb/dwc3/dwc3-qcom.c | 94 +++++++++++++++++++++++++++++++----- 1 file changed, 83 insertions(+), 11 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index b51fd97521df3..3479792c2acd7 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -62,6 +62,10 @@ static const u32 pwr_evnt_irq_stat_reg[DWC3_QCOM_MAX_PORTS] = { 0x238, }; +struct dwc3_qcom_platform_data { + bool uses_eusb2_phy; +}; + struct dwc3_qcom_port { int qusb2_phy_irq; int dp_hs_phy_irq; @@ -87,6 +91,7 @@ struct dwc3_qcom { struct icc_path *icc_path_apps; enum usb_role current_role; + bool uses_eusb2_phy; }; #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc) @@ -274,15 +279,23 @@ static void dwc3_qcom_disable_wakeup_irq(int irq) disable_irq_nosync(irq); } -static void dwc3_qcom_disable_port_interrupts(struct dwc3_qcom_port *port) +static void dwc3_qcom_disable_port_interrupts(struct dwc3_qcom *qcom, int port_index) { + struct dwc3_qcom_port *port = &qcom->ports[port_index]; + dwc3_qcom_disable_wakeup_irq(port->qusb2_phy_irq); if (port->usb2_speed == USB_SPEED_LOW) { - dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); + if (qcom->uses_eusb2_phy) + dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); + else + dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); } else if ((port->usb2_speed == USB_SPEED_HIGH) || (port->usb2_speed == USB_SPEED_FULL)) { - dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); + if (qcom->uses_eusb2_phy) + dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); + else + dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); } else { dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); @@ -291,8 +304,10 @@ static void dwc3_qcom_disable_port_interrupts(struct dwc3_qcom_port *port) dwc3_qcom_disable_wakeup_irq(port->ss_phy_irq); } -static void dwc3_qcom_enable_port_interrupts(struct dwc3_qcom_port *port) +static void dwc3_qcom_enable_port_interrupts(struct dwc3_qcom *qcom, int port_index) { + struct dwc3_qcom_port *port = &qcom->ports[port_index]; + dwc3_qcom_enable_wakeup_irq(port->qusb2_phy_irq, 0); /* @@ -305,12 +320,20 @@ static void dwc3_qcom_enable_port_interrupts(struct dwc3_qcom_port *port) */ if (port->usb2_speed == USB_SPEED_LOW) { - dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, - IRQ_TYPE_EDGE_FALLING); + if (qcom->uses_eusb2_phy) + dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, + IRQ_TYPE_EDGE_RISING); + else + dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, + IRQ_TYPE_EDGE_FALLING); } else if ((port->usb2_speed == USB_SPEED_HIGH) || (port->usb2_speed == USB_SPEED_FULL)) { - dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, - IRQ_TYPE_EDGE_FALLING); + if (qcom->uses_eusb2_phy) + dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, + IRQ_TYPE_EDGE_RISING); + else + dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, + IRQ_TYPE_EDGE_FALLING); } else { dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, IRQ_TYPE_EDGE_RISING); @@ -326,7 +349,7 @@ static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) int i; for (i = 0; i < qcom->num_ports; i++) - dwc3_qcom_disable_port_interrupts(&qcom->ports[i]); + dwc3_qcom_disable_port_interrupts(qcom, i); } static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) @@ -334,7 +357,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) int i; for (i = 0; i < qcom->num_ports; i++) - dwc3_qcom_enable_port_interrupts(&qcom->ports[i]); + dwc3_qcom_enable_port_interrupts(qcom, i); } static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) @@ -619,6 +642,7 @@ struct dwc3_glue_ops dwc3_qcom_glue_ops = { static int dwc3_qcom_probe(struct platform_device *pdev) { + const struct dwc3_qcom_platform_data *pdata; struct dwc3_probe_data probe_data = {}; struct device *dev = &pdev->dev; struct dwc3_qcom *qcom; @@ -634,6 +658,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev) qcom->dev = &pdev->dev; + pdata = device_get_match_data(dev); + if (pdata) + qcom->uses_eusb2_phy = pdata->uses_eusb2_phy; + qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); if (IS_ERR(qcom->resets)) { return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), @@ -848,8 +876,52 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = { .prepare = pm_sleep_ptr(dwc3_qcom_prepare), }; +static const struct dwc3_qcom_platform_data dwc3_qcom_glymur_pdata = { + .uses_eusb2_phy = true, +}; + static const struct of_device_id dwc3_qcom_of_match[] = { - { .compatible = "qcom,snps-dwc3" }, + { .compatible = "qcom,snps-dwc3", }, + { + .compatible = "qcom,eliza-dwc3", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,glymur-dwc3", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,glymur-dwc3-mp", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,kaanapali-dwc3", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,milos-dwc3", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,sm8550-dwc3", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,sm8650-dwc3", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,sm8750-dwc3", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,x1e80100-dwc3", + .data = &dwc3_qcom_glymur_pdata, + }, + { + .compatible = "qcom,x1e80100-dwc3-mp", + .data = &dwc3_qcom_glymur_pdata, + }, { } }; MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); From aeaea737d1947b936244ccfb053c0290c806ff3c Mon Sep 17 00:00:00 2001 From: Vadlamani Manjusha Date: Thu, 21 May 2026 14:32:48 +0530 Subject: [PATCH 1136/1330] QCLINUX: arm64: dts: qcom: Enable combo mode for CSI1 port In order to enable combo mode on CSI1 mode, resources needs to be in shared mode. This change adds required resources under res-mgr node. Signed-off-by: Vadlamani Manjusha (cherry picked from commit b7de1d752e129c1883a76fa496545847834881b4) --- .../dts/qcom/lemans-evk-camera-sensor.dtsi | 77 +++++-------------- 1 file changed, 19 insertions(+), 58 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi index e1ee2ba8c78e6..959e2690848ff 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi @@ -125,7 +125,7 @@ }; /*cam0a-ov9282*/ - rb8_slot0: qcom,cam-sensor1 { + qcom,cam-sensor1 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <0>; sensor-position-roll = <0>; @@ -439,7 +439,7 @@ }; /*cam1-ov9282*/ - rb8_slot1: qcom,cam-sensor21 { + qcom,cam-sensor21 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <1>; sensor-position-roll = <0>; @@ -454,10 +454,8 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_active_rst1>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_suspend_rst1>; + pinctrl-0 = <&cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_suspend_rst1>; pinctrl-names = "cam_default", "cam_suspend"; gpios = <&tlmm 73 0>, <&tlmm 133 0>, @@ -478,14 +476,14 @@ status = "ok"; }; - /*cam1-imx577*/ - qcom,cam-sensor26 { + /*cam1-cmk_imx577*/ + qcom,cam-sensor28 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <1>; sensor-position-roll = <0>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; - eeprom-src = <&eeprom_cam26>; + eeprom-src = <&eeprom_cam28>; cam_vio-supply = <&vreg_s4a>; regulator-names = "cam_vio"; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; @@ -515,18 +513,17 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; - cell-index = <26>; + cell-index = <28>; status = "ok"; }; - /*cam1-cmk_imx577*/ - qcom,cam-sensor28 { + /*cam1-ov9282*/ + qcom,cam-sensor31 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <1>; sensor-position-roll = <0>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; - eeprom-src = <&eeprom_cam28>; cam_vio-supply = <&vreg_s4a>; regulator-names = "cam_vio"; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; @@ -536,13 +533,8 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_active_rst1>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_suspend_rst1>; - pinctrl-names = "cam_default", "cam_suspend"; gpios = <&tlmm 73 0>, - <&tlmm 133 0>, + <&expander2 2 0>, <&pmm8654au_0_gpios 8 0>; gpio-reset = <1>; gpio-custom1 = <2>; @@ -556,43 +548,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; - cell-index = <28>; - status = "ok"; - }; - - eeprom_cam26: qcom,eeprom26 { - compatible = "qcom,eeprom"; - cam_vio-supply = <&vreg_s4a>; - regulator-names = "cam_vio"; - power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000>; - rgltr-max-voltage = <1800000>; - rgltr-load-current = <120000>; - gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_active_rst1>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_suspend_rst1>; - pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 73 0>, - <&tlmm 133 0>, - <&pmm8654au_0_gpios 8 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAMIF_MCLK1", - "CAM_RESET1", - "CAM_CUSTOM1"; - sensor-mode = <0>; - cci-master = <0>; - clocks = <&camcc CAM_CC_MCLK1_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "nominal"; - clock-rates = <24000000>; - cell-index = <26>; + cell-index = <31>; status = "ok"; }; @@ -755,7 +711,7 @@ }; /*cam2-ov9282*/ - rb8_slot2: qcom,cam-sensor22 { + qcom,cam-sensor22 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; sensor-position-roll = <0>; @@ -994,7 +950,7 @@ }; /*cam3-ov9282*/ - rb8_slot3: qcom,cam-sensor23 { + qcom,cam-sensor23 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <3>; sensor-position-roll = <0>; @@ -1115,6 +1071,11 @@ qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; gpios-shared = <518 519 520 521>; + gpios-shared-pinctrl = <633>; + shared-pctrl-gpio-names = "mclk1"; + pinctrl-0 = <&cam_sensor_mclk1_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend>; + pinctrl-names = "mclk1_active", "mclk1_suspend"; status = "ok"; }; }; From 419132d8a54693b62e4a36ee00af27afcab0b548 Mon Sep 17 00:00:00 2001 From: Vadlamani Manjusha Date: Mon, 25 May 2026 20:03:32 +0530 Subject: [PATCH 1137/1330] QCLINUX: arm64: dts: qcom: Fix GPIO free and acquire logic Prevent GPIOs managed by pinctrl from being requested and freed via the GPIO framework. Restrict GPIO request/free operations to non-pinctrl GPIOs by adding appropriate conditions. Signed-off-by: Vadlamani Manjusha (cherry picked from commit fc647a8ed68a7d50d7cddc7111014addd57c064f) --- .../dts/qcom/lemans-evk-camera-sensor.dtsi | 266 +++++++----------- 1 file changed, 105 insertions(+), 161 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi index 959e2690848ff..f7005902a98a2 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera-sensor.dtsi @@ -125,7 +125,7 @@ }; /*cam0a-ov9282*/ - qcom,cam-sensor1 { + rb8_slot0: qcom,cam-sensor1 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <0>; sensor-position-roll = <0>; @@ -140,20 +140,16 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_active_rst0>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_suspend_rst0>; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 72 0>, - <&tlmm 132 0>, + gpios =<&tlmm 132 0>, <&pmm8654au_0_gpios 7 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK0", - "CAMIF_RESET0", + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET0", "CAM_CUSTOM1"; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK0_CLK>; @@ -181,21 +177,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_active_rst0>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_suspend_rst0>; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 72 0>, - <&tlmm 132 0>, + gpios =<&tlmm 132 0>, <&pmm8654au_0_gpios 7 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK0", - "CAMIF_RESET0", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET0", + "CAM_CUSTOM1"; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK0_CLK>; clock-names = "cam_clk"; @@ -222,21 +214,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_active_rst0>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_suspend_rst0>; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 72 0>, - <&tlmm 132 0>, + gpios =<&tlmm 132 0>, <&pmm8654au_0_gpios 7 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK0", - "CAMIF_RESET0", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET0", + "CAM_CUSTOM1"; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK0_CLK>; clock-names = "cam_clk"; @@ -257,21 +245,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_active_rst0>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_suspend_rst0>; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 72 0>, - <&tlmm 132 0>, + gpios =<&tlmm 132 0>, <&pmm8654au_0_gpios 7 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK0", - "CAMIF_RESET0", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET0", + "CAM_CUSTOM1"; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK0_CLK>; clock-names = "cam_clk"; @@ -292,20 +276,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_active_rst0>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_suspend_rst0>; - gpios = <&tlmm 72 0>, - <&tlmm 132 0>, + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; + pinctrl-names = "cam_default", "cam_suspend"; + gpios =<&tlmm 132 0>, <&pmm8654au_0_gpios 7 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK0", - "CAMIF_RESET0", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET0", + "CAM_CUSTOM1"; sensor-mode = <0>; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK0_CLK>; @@ -439,7 +420,7 @@ }; /*cam1-ov9282*/ - qcom,cam-sensor21 { + rb8_slot1: qcom,cam-sensor21 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <1>; sensor-position-roll = <0>; @@ -454,9 +435,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_active_rst1>; - pinctrl-1 = <&cam_sensor_suspend_rst1>; - pinctrl-names = "cam_default", "cam_suspend"; gpios = <&tlmm 73 0>, <&tlmm 133 0>, <&pmm8654au_0_gpios 8 0>; @@ -493,11 +471,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_active_rst1>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_suspend_rst1>; - pinctrl-names = "cam_default", "cam_suspend"; gpios = <&tlmm 73 0>, <&tlmm 133 0>, <&pmm8654au_0_gpios 8 0>; @@ -535,7 +508,7 @@ gpio-no-mux = <0>; gpios = <&tlmm 73 0>, <&expander2 2 0>, - <&pmm8654au_0_gpios 8 0>; + <&pmm8654au_0_gpios 8 0>; gpio-reset = <1>; gpio-custom1 = <2>; gpio-req-tbl-num = <0 1 2>; @@ -563,11 +536,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_active_rst1>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_suspend_rst1>; - pinctrl-names = "cam_default", "cam_suspend"; gpios = <&tlmm 73 0>, <&tlmm 133 0>, <&pmm8654au_0_gpios 8 0>; @@ -711,7 +679,7 @@ }; /*cam2-ov9282*/ - qcom,cam-sensor22 { + rb8_slot2: qcom,cam-sensor22 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; sensor-position-roll = <0>; @@ -726,21 +694,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_active_rst2>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_suspend_rst2>; + pinctrl-0 = <&cam_sensor_mclk2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 74 0>, - <&tlmm 134 0>, + gpios = <&tlmm 134 0>, <&pmm8654au_0_gpios 9 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK2", - "CAMIF_RESET2", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET2", + "CAM_CUSTOM1"; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK2_CLK>; clock-names = "cam_clk"; @@ -767,21 +731,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_active_rst2>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_suspend_rst2>; + pinctrl-0 = <&cam_sensor_mclk2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 74 0>, - <&tlmm 134 0>, + gpios = <&tlmm 134 0>, <&pmm8654au_0_gpios 9 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK2", - "CAMIF_RESET2", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET2", + "CAM_CUSTOM1"; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK2_CLK>; clock-names = "cam_clk"; @@ -802,21 +762,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_active_rst2>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_suspend_rst2>; + pinctrl-0 = <&cam_sensor_mclk2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 74 0>, - <&tlmm 134 0>, + gpios = <&tlmm 134 0>, <&pmm8654au_0_gpios 9 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET2", + "CAM_CUSTOM1"; sensor-mode = <0>; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK2_CLK>; @@ -950,7 +906,7 @@ }; /*cam3-ov9282*/ - qcom,cam-sensor23 { + rb8_slot3: qcom,cam-sensor23 { compatible = "qcom,cam-sensor"; csiphy-sd-index = <3>; sensor-position-roll = <0>; @@ -965,21 +921,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk3_active - &cam_sensor_active_rst3>; - pinctrl-1 = <&cam_sensor_mclk3_suspend - &cam_sensor_suspend_rst3>; + pinctrl-0 = <&cam_sensor_mclk3_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpios = <&tlmm 75 0>, - <&tlmm 135 0>, + gpios = <&tlmm 135 0>, <&pmm8654au_0_gpios 10 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK3", - "CAMIF_RESET3", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET3", + "CAM_CUSTOM1"; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK3_CLK>; clock-names = "cam_clk"; @@ -1006,21 +958,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk3_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk3_active - &cam_sensor_active_rst3>; - pinctrl-1 = <&cam_sensor_mclk3_suspend - &cam_sensor_suspend_rst3>; - gpios = <&tlmm 75 0>, - <&tlmm 135 0>, + gpios = <&tlmm 135 0>, <&pmm8654au_0_gpios 10 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAM_MCLK3", - "CAMIF_RESET3", - "CAM_CUSTOM1"; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET3", + "CAM_CUSTOM1"; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK3_CLK>; clock-names = "cam_clk"; @@ -1041,21 +989,17 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-0 = <&cam_sensor_mclk3_active - &cam_sensor_active_rst3>; - pinctrl-1 = <&cam_sensor_mclk3_suspend - &cam_sensor_suspend_rst3>; - gpios = <&tlmm 75 0>, - <&tlmm 135 0>, - <&pmm8654au_0_gpios 10 0>; + pinctrl-0 = <&cam_sensor_mclk3_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend>; pinctrl-names = "cam_default", "cam_suspend"; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAMIF_MCLK3", - "CAM_RESET3", - "CAM_CUSTOM1"; + gpios = <&tlmm 135 0>, + <&pmm8654au_0_gpios 10 0>; + gpio-reset = <0>; + gpio-custom1 = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "CAMIF_RESET3", + "CAM_CUSTOM1"; sensor-mode = <0>; cci-master = <0>; clocks = <&camcc CAM_CC_MCLK3_CLK>; From 0576237ea50fec71397e6f8f4e041b4d403083a2 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 26 Mar 2026 20:20:28 -0700 Subject: [PATCH 1138/1330] FROMLIST: arm64: dts: qcom: kaanapali: Add SoCCP for Kaanapali SoC Add remoteproc PAS loader for SoCCP with its SMP2P. On Kaanapali, it is brought up by bootloader, so set the status "okay". Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260326-knp-soccp-dt-v1-1-a60c2ae36e9b@oss.qualcomm.com (cherry picked from commit 3f9dfdaf6bb96bafb076847406e041ca1efd00cf) --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 72 +++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index f4c7ca80641f7..c3e2f4d2a12d8 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -513,6 +513,32 @@ }; }; + smp2p-soccp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <617>, <616>; + qcom,local-pid = <0>; + qcom,remote-pid = <19>; + + soccp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + soccp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -1522,6 +1548,52 @@ }; }; + remoteproc_soccp: remoteproc-soccp@d00000 { + compatible = "qcom,kaanapali-soccp-pas"; + reg = <0x0 0x00d00000 0x0 0x200000>; + + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "pong"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + memory-region = <&soccp_mem>, + <&soccp_dtb_mem>; + + qcom,smem-states = <&soccp_smp2p_out 0>, + <&soccp_smp2p_out 8>; + qcom,smem-state-names = "stop", + "ping"; + + status = "okay"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <19>; + label = "soccp"; + }; + }; + ipcc: mailbox@1106000 { compatible = "qcom,kaanapali-ipcc", "qcom,ipcc"; reg = <0x0 0x01106000 0x0 0x1000>; From b89b1ac3a1f916bb6f810858993e3111dc59c7ff Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 26 Mar 2026 20:20:29 -0700 Subject: [PATCH 1139/1330] FROMLIST: arm64: dts: qcom: kaanapali-qrd: Add SoCCP node Add SoCCP node on Kaanapali QRD board. Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260326-knp-soccp-dt-v1-2-a60c2ae36e9b@oss.qualcomm.com (cherry picked from commit e51c63c4d717fb80bce93d4aada0629754cbb6bf) --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 95dce0812725c..387dd71f313ab 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -794,6 +794,11 @@ status = "okay"; }; +&remoteproc_soccp { + firmware-name = "qcom/kaanapali/soccp.mbn", + "qcom/kaanapali/soccp_dtb.mbn"; +}; + &tlmm { gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ From 54e3f5abd843a34e1a3fa82b3d5103db5e494078 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 26 Mar 2026 20:20:30 -0700 Subject: [PATCH 1140/1330] FROMLIST: arm64: dts: qcom: kaanapali-mtp: Add SoCCP node Add SoCCP node on Kaanapali MTP board. Signed-off-by: Jingyi Wang Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20260326-knp-soccp-dt-v1-3-a60c2ae36e9b@oss.qualcomm.com (cherry picked from commit dc0c616d6302d39cd49eb3c3df0ba7e517ecfca3) --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 7bce5653ea748..f410e7f64d7eb 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -1084,6 +1084,11 @@ status = "okay"; }; +&remoteproc_soccp { + firmware-name = "qcom/kaanapali/soccp.mbn", + "qcom/kaanapali/soccp_dtb.mbn"; +}; + &sdhc_2 { cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; From 24d71baca05f91ae0a30b72d30f7bd89edbc58f1 Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Mon, 1 Jun 2026 16:59:22 +0800 Subject: [PATCH 1141/1330] FROMLIST: arm64: dts: qcom: kaanapali: add reboot-mode support Add PSCI SYSTEM_RESET2 reboot-modes for kaanapali-mtp and kaanapali-qrd for use by the psci-reboot-mode driver. The following modes are defined: - bootloader: reboot into fastboot mode for fastboot flashing. - edl: reboot into emergency download mode for image loading via the Firehose protocol. Link: https://lore.kernel.org/all/20260529-psci_sys_reset-dt-changes-for-pakala-v1-2-7c32161cf50b@oss.qualcomm.com/ Signed-off-by: Xin Liu Signed-off-by: Anurag Pateriya (cherry picked from commit 0fa62a7f1fc9497b61161a6aef4d1897995e5f84) --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 7 +++++++ arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 7 +++++++ arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 +- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index f410e7f64d7eb..587ae33493fbf 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -1361,3 +1361,10 @@ status = "okay"; }; + +&psci { + reboot-mode { + mode-bootloader = <0x80010001 0x2>; + mode-edl = <0x80000000 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 387dd71f313ab..378bf3bf6d927 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -856,3 +856,10 @@ status = "okay"; }; + +&psci { + reboot-mode { + mode-bootloader = <0x80010001 0x2>; + mode-edl = <0x80000000 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index c3e2f4d2a12d8..4066dd92ee1f0 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -274,7 +274,7 @@ interrupts = ; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; From 8804e935ec140558c0bc1e142079790f89ccf08b Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 2 Jun 2026 11:10:13 +0800 Subject: [PATCH 1142/1330] PENDING: arm64: dts: qcom: kaanapali: add Coresight ETR and routing in staging dtso Add CTCU, QDSS replicator, dual ETR (tmc_etr/tmc_etr1), ETR replicator, SWAO replicator, and tmc_etf out-port to complete the DDR memory trace routing path in the kaanapali staging overlay. Signed-off-by: Jie Gan (cherry picked from commit 02b6b2a2375321bbf98042a06371fa5369d55e4c) --- .../boot/dts/qcom/kaanapali-staging.dtso | 191 ++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-staging.dtso b/arch/arm64/boot/dts/qcom/kaanapali-staging.dtso index d7a5b0b084872..39347415c815e 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-staging.dtso +++ b/arch/arm64/boot/dts/qcom/kaanapali-staging.dtso @@ -9,6 +9,150 @@ /plugin/; &soc { + ctcu: ctcu@10001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x0 0x10001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&tmc_etr_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&tmc_etr1_out>; + }; + }; + }; + }; + + replicator_qdss: replicator@10046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_qdss_in: endpoint { + remote-endpoint = <&replicator_swao_out0>; + }; + }; + }; + + out-ports { + port { + replicator_qdss_out: endpoint { + remote-endpoint = <&replicator_etr_in>; + }; + }; + }; + }; + + tmc_etr: tmc@10048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x04e0 0x0>; + arm,scatter-gather; + + in-ports { + port { + tmc_etr_in: endpoint { + remote-endpoint = <&replicator_etr_out0>; + }; + }; + }; + + out-ports { + port { + tmc_etr_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator_etr: replicator@1004e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x1004e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_etr_in: endpoint { + remote-endpoint = <&replicator_qdss_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + replicator_etr_out0: endpoint { + remote-endpoint = <&tmc_etr_in>; + }; + }; + + port@1 { + reg = <1>; + + replicator_etr_out1: endpoint { + remote-endpoint = <&tmc_etr1_in>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x1004f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x0500 0x0>; + arm,scatter-gather; + + in-ports { + port { + tmc_etr1_in: endpoint { + remote-endpoint = <&replicator_etr_out1>; + }; + }; + }; + + out-ports { + port { + tmc_etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + tgu@11301000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x11301000 0x0 0x1000>; @@ -17,6 +161,53 @@ clock-names = "apb_pclk"; }; + tmc@11305000 { + out-ports { + port { + tmc_etf_out: endpoint { + remote-endpoint = <&replicator_swao_in>; + }; + }; + }; + }; + + replicator_swao: replicator@11306000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x11306000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_swao_in: endpoint { + remote-endpoint = <&tmc_etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + replicator_swao_out0: endpoint { + remote-endpoint = <&replicator_qdss_in>; + }; + }; + + port@1 { + reg = <1>; + + replicator_swao_out1: endpoint { + remote-endpoint = <&eud_in>; + }; + }; + }; + }; + tgu@1130e000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x1130e000 0x0 0x1000>; From 9791d255922e5392cac7522badab88717fce0f8c Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 2 Jun 2026 20:51:49 +0530 Subject: [PATCH 1143/1330] FROMLIST: dt-bindings: clock: qcom: Add bindings for PDM GP_MN clock divider Add device tree bindings for the Qualcomm Peripheral Web's PDM GP_MN clock divider. The hardware generates a fractional output frequency from a fixed input clock (typically TCXO4) using the relation Fout = Fin * (M / N), with duty cycle controlled by a separate D register. The clock output is routed over a gpio controlled pin. Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-1-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit b40e7dbd6b5ce988ec22e3428060a77adeb7c5cb) --- .../bindings/clock/qcom,clk-gp-mnd.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml b/Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml new file mode 100644 index 0000000000000..c1688bb3d68d8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,clk-gp-mnd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Peripheral Web's PDM GP_MN Clock Divider + +maintainers: + - Taniya Das + +description: | + The Peripheral Web's PDM GP_MN clock divider receives an input clock + (TCXO4) with frequency Fin and generates an output clock with + frequency Fout = Fin * (M / N) and a duty cycle controlled by D + and routed over a gpio pin. + + The divider is configured using three registers: + + - GP_MN_CLK_MDIV: holds the M value. + - GP_MN_CLK_NDIV: holds the ones complement of (N - M). + - GP_MN_CLK_DUTY: holds the D value. + + For every N input clock cycles the GP_MN produces M output clock + cycles. D is the number of native clock cycles in which the GP_MN + output is low, counted over 2^13 native clock cycles. + + Hardware constraints: + + M <= 511 + N <= 8191 + N > 2 * M + M < D < (N - M) + M and N must be coprime (no common divisor) + +properties: + compatible: + const: qcom,clk-gp-mnd + + reg: + maxItems: 1 + + clocks: + items: + - description: PDM XO4 source clock + - description: PDM AHB bus clock for register access + + clock-names: + items: + - const: pdm_clk + - const: ahb_clk + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + pinctrl-0: + description: Pin configuration for the GP_MN output in the active state. + + pinctrl-names: + items: + - const: active + + assigned-clocks: + maxItems: 1 + description: Parent clock phandle used to set the input frequency. + + assigned-clock-rates: + maxItems: 1 + description: | + Rate for the parent clock in Hz. + Supported rates: 19200000, 9600000, 6400000, 4800000. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - clock-output-names + - pinctrl-0 + - pinctrl-names + - assigned-clocks + - assigned-clock-rates + +additionalProperties: false + +examples: + - | + #include + gp_mn: clock-controller@88d3000 { + compatible = "qcom,clk-gp-mnd"; + reg = <0x88d3000 0xc>; + clocks = <&gcc GCC_PDM_XO4_CLK>, + <&gcc GCC_PDM_AHB_CLK>; + clock-names = "pdm_clk", "ahb_clk"; + clock-output-names = "gp_mn_clk"; + pinctrl-0 = <&gp_mn_pin_active>; + pinctrl-names = "active"; + assigned-clocks = <&gcc GCC_PDM_XO4_CLK>; + assigned-clock-rates = <4800000>; + #clock-cells = <0>; + }; From a7b8aa36b020ce405a27df5c8d1f340fbb4b61a5 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 2 Jun 2026 20:51:50 +0530 Subject: [PATCH 1144/1330] FROMLIST: clk: qcom: Add a driver for PDM GP_MN fractional clock divider The PDM (Pulse Density Modulation) hardware block on Qualcomm SoCs contains a GP_MN clock divider that produces a fractional output frequency from a fixed input clock (typically TCXO4): Fout = Fin * (M / N) The hardware encodes the period in the NDIV register as the 1's complement of (N - M), and controls the duty cycle via a separate DUTY register that counts the number of low-phase native clock cycles over the period N. Add a standalone platform driver for this block that uses rational_best_approximation() to find the closest M/N pair within the 9-bit M and 13-bit N hardware limits, programs the MDIV, NDIV, and DUTY registers via regmap, and implements the full clk_ops surface including determine_rate, set_rate, recalc_rate, get_duty_cycle, and set_duty_cycle. The PDM AHB bus clock is gated around every register access. Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-2-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das (cherry picked from commit a832eb6ab586eacf06f26da7a8298e320174b276) --- drivers/clk/qcom/Kconfig | 15 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-gp-mnd.c | 333 ++++++++++++++++++++++++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/clk/qcom/clk-gp-mnd.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b952efd73d779..cf8bb0e39c27d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1798,4 +1798,19 @@ config SM_VIDEOCC_8450 SM8450 or SM8475 devices. Say Y if you want to support video devices and functionality such as video encode/decode. + +config QCOM_CLK_GP_MND + tristate "Qualcomm PDM GP_MN clock divider" + depends on ARM64 || COMPILE_TEST + help + Support for the Qualcomm PDM GP_MN clock divider found in PDM + (Pulse Density Modulation) hardware blocks. + Given an input clock of frequency Fin (TCXO4), the output + frequency is Fout = Fin * (M / N). For every N input cycles + the divider produces M output cycles. D controls the duty + cycle: it is the number of native clock cycles in which the + GP_MN output is low, counted over 8192 native clock cycles. + + Say Y or M if you want to support GP_MN-based frequency and + duty-cycle configuration on Qualcomm SoCs. endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b4cd483a14f25..6add2d4ac7ba3 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -208,6 +208,7 @@ obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8750) += videocc-sm8750.o obj-$(CONFIG_SM_VIDEOCC_MILOS) += videocc-milos.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o +obj-$(CONFIG_QCOM_CLK_GP_MND) += clk-gp-mnd.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o obj-$(CONFIG_KRAITCC) += krait-cc.o diff --git a/drivers/clk/qcom/clk-gp-mnd.c b/drivers/clk/qcom/clk-gp-mnd.c new file mode 100644 index 0000000000000..826b6b62ddc7b --- /dev/null +++ b/drivers/clk/qcom/clk-gp-mnd.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * PDM GP_MND clock divider register offsets. + * + * The hardware computes: + * Fout = Fin * (M / N) + * + * with duty cycle controlled by D, where M < D < (N - M). + * + * Register encoding: + * MDIV = M + * NDIV = ~(N - M) [1's complement of (N - M), masked to N_REG_WIDTH bits] + * DUTY = D + */ +#define GP_MND_MDIV_REG 0x0 +#define GP_MND_NDIV_REG 0x4 +#define GP_MND_DUTY_REG 0x8 + +#define GP_MND_M_WIDTH 9 +#define GP_MND_N_WIDTH 13 + +#define GP_MND_MAX_M GENMASK(GP_MND_M_WIDTH - 1, 0) +#define GP_MND_MAX_N GENMASK(GP_MND_N_WIDTH - 1, 0) + +/** + * struct clk_gp_mnd - GP_MND fractional clock divider + * @pdm_ahb_clk: AHB bus clock required for register access + * @regmap: register map for the PDM block + * @hw: handle between common and hardware-specific interfaces + * @m_val: M value (numerator) + * @n_val: N value (period) + */ +struct clk_gp_mnd { + struct clk *pdm_ahb_clk; + struct regmap *regmap; + struct clk_hw hw; + unsigned int m_val; + unsigned int n_val; +}; + +#define to_clk_gp_mnd(_hw) container_of(_hw, struct clk_gp_mnd, hw) + +static int gp_mnd_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long m = 0, n = 0; + + rational_best_approximation(req->rate, req->best_parent_rate, + (unsigned long)GP_MND_MAX_M, + (unsigned long)GP_MND_MAX_N, + &m, &n); + + if (!m || !n) + return -EINVAL; + + /* N = 2M + 1 leaves no valid D satisfying M < D < (N - M) */ + if (n == 2 * m + 1) + return -EINVAL; + + req->rate = DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate * m, n); + + return 0; +} + +static int gp_mnd_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_gp_mnd *gp = to_clk_gp_mnd(hw); + unsigned long m = 0, n = 0; + unsigned int d_val, n_val; + int ret; + + rational_best_approximation(rate, parent_rate, + (unsigned long)GP_MND_MAX_M, + (unsigned long)GP_MND_MAX_N, + &m, &n); + + if (!m || !n) + return -EINVAL; + + /* + * When N = 2M + 1 the valid D range [M+1, M] is empty; no duty + * cycle can satisfy M < D < (N - M). Reject before touching hw. + */ + if (n == 2 * m + 1) + return -EINVAL; + + ret = clk_prepare_enable(gp->pdm_ahb_clk); + if (ret) + return ret; + + ret = regmap_write(gp->regmap, GP_MND_MDIV_REG, m); + if (ret) + goto err_unprepare; + + /* N divider holds the 1's complement of (N - M), N_WIDTH bits wide */ + n_val = ~(n - m) & GP_MND_MAX_N; + ret = regmap_write(gp->regmap, GP_MND_NDIV_REG, n_val); + if (ret) + goto err_unprepare; + + /* Program the closest-to-50% duty cycle. */ + d_val = n / 2; + ret = regmap_write(gp->regmap, GP_MND_DUTY_REG, d_val); + if (ret) + goto err_unprepare; + + gp->m_val = m; + gp->n_val = n; + +err_unprepare: + clk_disable_unprepare(gp->pdm_ahb_clk); + + return ret; +} + +static unsigned long gp_mnd_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_gp_mnd *gp = to_clk_gp_mnd(hw); + unsigned int m_val, n_val; + int ret; + + ret = clk_prepare_enable(gp->pdm_ahb_clk); + if (ret) + return 0; + + ret = regmap_read(gp->regmap, GP_MND_MDIV_REG, &m_val); + if (ret) + goto out_unprepare; + + m_val &= GP_MND_MAX_M; + + ret = regmap_read(gp->regmap, GP_MND_NDIV_REG, &n_val); + if (ret) + goto out_unprepare; + + /* Reverse the 1's complement encoding: N = ~NDIV_REG + M */ + n_val = (~n_val & GP_MND_MAX_N) + m_val; + +out_unprepare: + clk_disable_unprepare(gp->pdm_ahb_clk); + + if (ret) + return 0; + + if (!n_val) + return 0; + + gp->m_val = m_val; + gp->n_val = n_val; + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * m_val, n_val); +} + +static int gp_mnd_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) +{ + struct clk_gp_mnd *gp = to_clk_gp_mnd(hw); + unsigned int d_val; + int ret; + + if (!gp->n_val) { + duty->num = 1; + duty->den = 2; + return 0; + } + + ret = clk_prepare_enable(gp->pdm_ahb_clk); + if (ret) + return ret; + + ret = regmap_read(gp->regmap, GP_MND_DUTY_REG, &d_val); + + clk_disable_unprepare(gp->pdm_ahb_clk); + + if (ret) + return ret; + + duty->num = d_val; + duty->den = gp->n_val; + + return 0; +} + +static int gp_mnd_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) +{ + struct clk_gp_mnd *gp = to_clk_gp_mnd(hw); + unsigned int d_val; + int ret; + + if (!gp->n_val || !gp->m_val) + return -EINVAL; + + /* D = (1 - duty) * N, giving the low-phase count */ + d_val = DIV_ROUND_UP((u64)(duty->den - duty->num) * gp->n_val, duty->den); + + /* Hardware constraint: M < D < (N - M) */ + if (d_val <= gp->m_val || d_val >= (gp->n_val - gp->m_val)) + return -EINVAL; + + ret = clk_prepare_enable(gp->pdm_ahb_clk); + if (ret) + return ret; + + ret = regmap_write(gp->regmap, GP_MND_DUTY_REG, d_val); + + clk_disable_unprepare(gp->pdm_ahb_clk); + + return ret; +} + +static const struct clk_ops clk_gp_mnd_ops = { + .determine_rate = gp_mnd_clk_determine_rate, + .set_rate = gp_mnd_clk_set_rate, + .recalc_rate = gp_mnd_clk_recalc_rate, + .get_duty_cycle = gp_mnd_clk_get_duty_cycle, + .set_duty_cycle = gp_mnd_clk_set_duty_cycle, +}; + +static const struct regmap_config gp_mnd_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static int clk_gp_mnd_probe(struct platform_device *pdev) +{ + struct clk_parent_data parent_data = { .index = 0 }; + struct clk_init_data init = { + .ops = &clk_gp_mnd_ops, + .parent_data = &parent_data, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }; + struct device *dev = &pdev->dev; + struct clk_gp_mnd *gp; + struct clk *clk; + struct pinctrl *pin; + struct pinctrl_state *pin_default_state; + void __iomem *base; + int ret; + + gp = devm_kzalloc(dev, sizeof(*gp), GFP_KERNEL); + if (!gp) + return -ENOMEM; + + gp->pdm_ahb_clk = devm_clk_get(dev, "ahb_clk"); + if (IS_ERR(gp->pdm_ahb_clk)) + return dev_err_probe(dev, PTR_ERR(gp->pdm_ahb_clk), + "failed to get ahb_clk\n"); + + clk = devm_clk_get(dev, "pdm_clk"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + /* Set default rate if not already configured */ + if (!clk_get_rate(clk)) { + ret = clk_set_rate(clk, 19200000); + if (ret) + dev_warn(dev, "failed to set default pdm_clk rate\n"); + } + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to map PDM registers\n"); + + gp->regmap = devm_regmap_init_mmio(dev, base, &gp_mnd_regmap_config); + if (IS_ERR(gp->regmap)) + return dev_err_probe(dev, PTR_ERR(gp->regmap), + "failed to init regmap\n"); + + ret = of_property_read_string_index(dev->of_node, + "clock-output-names", 0, + &init.name); + if (ret) + return dev_err_probe(dev, ret, "missing clock-output-names\n"); + + gp->hw.init = &init; + + pin = devm_pinctrl_get(dev); + if (IS_ERR(pin)) + return dev_err_probe(dev, PTR_ERR(pin), "missing pinctrl device\n"); + + pin_default_state = pinctrl_lookup_state(pin, "active"); + if (IS_ERR(pin_default_state)) + return dev_err_probe(dev, PTR_ERR(pin_default_state), + "missing pinctrl default state\n"); + + ret = pinctrl_select_state(pin, pin_default_state); + if (ret) + return dev_err_probe(dev, ret, + "failed to select pinctrl default state\n"); + + ret = devm_clk_hw_register(dev, &gp->hw); + if (ret) + return dev_err_probe(dev, ret, + "failed to register gp_mnd clock\n"); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &gp->hw); +} + +static const struct of_device_id clk_gp_mnd_match_table[] = { + { .compatible = "qcom,clk-gp-mnd" }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_gp_mnd_match_table); + +static struct platform_driver clk_gp_mnd_driver = { + .probe = clk_gp_mnd_probe, + .driver = { + .name = "qcom-clk-gp-mnd", + .of_match_table = clk_gp_mnd_match_table, + }, +}; +module_platform_driver(clk_gp_mnd_driver); + +MODULE_DESCRIPTION("Qualcomm PDM GP_MND clock divider driver"); +MODULE_LICENSE("GPL"); From ce3f44e85a9bc40d0cd2501593c742451f745e6d Mon Sep 17 00:00:00 2001 From: Dipa Ramesh Mantre Date: Tue, 19 May 2026 18:33:38 +0530 Subject: [PATCH 1145/1330] PENDING: arm64: dts: qcom: hamoa: Enable CDSP cooling in staging dtso MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike the CPU, the CDSP does not throttle its speed automatically when it reaches high temperatures in hamoa. Set up CDSP cooling by throttling the cdsp when it reaches 105°C. Signed-off-by: Dipa Ramesh Mantre (cherry picked from commit 3a0e3a57a352718db3e2a3874d2560fcc43b4de6) --- arch/arm64/boot/dts/qcom/hamoa-staging.dtso | 82 +++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-staging.dtso b/arch/arm64/boot/dts/qcom/hamoa-staging.dtso index feb3c7c5ccd82..6a1e106ae8a9a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-staging.dtso +++ b/arch/arm64/boot/dts/qcom/hamoa-staging.dtso @@ -8,6 +8,8 @@ /dts-v1/; /plugin/; +#include + &soc { tgu@10b0e000 { compatible = "qcom,tgu", "arm,primecell"; @@ -33,3 +35,83 @@ clock-names = "apb_pclk"; }; }; + +&remoteproc_cdsp { + cooling { + compatible = "qcom,qmi-cooling-cdsp"; + + cdsp_tmd0: cdsp-tmd0 { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; +}; + +&thermal_nsp0 { + trips { + nsp0_alert0: trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&nsp0_alert0>; + cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_nsp1 { + trips { + nsp1_alert0: trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&nsp1_alert0>; + cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_nsp2 { + trips { + nsp2_alert0: trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&nsp2_alert0>; + cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_nsp3 { + trips { + nsp3_alert0: trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&nsp3_alert0>; + cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + From 96f0de9dc1f61f9d07e5cf399c6a0b7e0d7b5749 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 1 Jun 2026 12:39:56 +0530 Subject: [PATCH 1146/1330] QCLINUX: arm64: dts: qcom: Change Purwa camera firmware path Update the path for the camera icp firmware. Signed-off-by: Chandan Kumar Jha (cherry picked from commit d8f6f41d809852c58cf61768b73f378b19cc83a9) --- arch/arm64/boot/dts/qcom/purwa-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/purwa-camera.dtsi b/arch/arm64/boot/dts/qcom/purwa-camera.dtsi index 5896e5759e22f..fe1057fe97f92 100644 --- a/arch/arm64/boot/dts/qcom/purwa-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-camera.dtsi @@ -34,7 +34,7 @@ src-clock-name = "icp_clk_src"; operating-points-v2 = <&icp_opp_table>; clock-control-debugfs = "true"; - fw_name = "qcom/x1p4x100/CAMERA_ICP"; + fw_name = "qcom/x1p42100/CAMERA_ICP"; ubwc-ipe-fetch-cfg = <0x707b 0x7083>; ubwc-ipe-write-cfg = <0x161ef 0x1620f>; ubwc-bps-fetch-cfg = <0x707b 0x7083>; From 2c2343632650f2f79a20a95dbe1b522adb8771f7 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Mon, 1 Jun 2026 05:20:10 +0530 Subject: [PATCH 1147/1330] FROMLIST: scsi: ufs: core: Add UFSHCD_QUIRK_SKIP_DEVICE_RESET quirk Add a new host quirk UFSHCD_QUIRK_SKIP_DEVICE_RESET to allow host controller drivers to skip asserting device reset during UFS power down. When RST_N is asserted, the UFS device firmware wakes up and executes its internal reset routine. This routine initializes multiple hardware blocks and causing the device to draw a large curreny during this time. If the power rail transitions to LPM (Low Power Mode) while the device is still drawing this elevated current, it may trigger an OCP (Over Current Protection) fault in the regulator. For some UFS devices (e.g., Micron), the elevated current draw persists until the reset line is deasserted, making a fixed delay insufficient to prevent OCP. This quirk allows such devices to skip device reset during UFS power down. The device reset will instead be asserted as part of the platform shutdown sequence. Link: https://lore.kernel.org/linux-scsi/20260531235011.1052706-2-nitin.rawat@oss.qualcomm.com/ Signed-off-by: Nitin Rawat Signed-off-by: Pradeep P V K (cherry picked from commit 1f2a619664b709bf62d59c4660c673014babce5a) --- include/ufs/ufshcd.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 8563b66489764..85c6d9fe23433 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -690,6 +690,26 @@ enum ufshcd_quirks { * because it causes link startup to become unreliable. */ UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE = 1 << 26, + + /* + * On some platforms, the VCC regulator has a slow ramp-up time. Add a + * delay after enabling VCC to ensure it's stable. + */ + UFSHCD_QUIRK_VCC_ON_DELAY = 1 << 27, + + /* + * Some UFS devices keep drawing larger current after reset is + * asserted until it is deasserted. Asserting device reset + * during UFS power down causes the device firmware to wake up and + * execute its reset routine, drawing current beyond the permissible + * limit for low-power mode (LPM). This may trigger an OCP fault on + * the regulator supplying power to UFS. + * + * Enable this quirk to skip asserting device reset during UFS power + * down. This is handled only in shutdown; the device reset will be + * asserted as part of the platform shutdown sequence. + */ + UFSHCD_QUIRK_SKIP_DEVICE_RESET = 1 << 28, }; enum ufshcd_caps { From 59b2df05fb4eddc5aef7bb6c7470c12cc6892152 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Mon, 1 Jun 2026 05:20:11 +0530 Subject: [PATCH 1148/1330] FROMLIST: scsi: ufs: ufs-qcom: Enable SKIP DEVICE RESET Quirk A previous fix [1] addressed an OCP (Over Current Protection) issue during UFS power down (PC=3) by adding a 10ms delay after asserting HWRST. The delay allows the UFS device to complete its reset routine before the power rail transitions to LPM (Low Power Mode). However, this fix is insufficient for certain Micron UFS parts. Unlike other vendors whose reset routine completes within ~10ms, Micron parts continue to draw current beyond the LPM threshold for a longer duration after reset is asserted, specifically until the reset is deasserted (RST_N goes high). No fixed delay can reliably cover this window since there is currently no mechanism for the host to query whether the device reset routine has completed. Enable the UFSHCD_QUIRK_SKIP_DEVICE_RESET quirk to skip device assert reset during UFS power down for Micron parts. For all other vendors, the existing behavior (assert reset + 10ms delay) is preserved. This quirk is applicable only during shutdown. The device reset will be asserted as part of the platform shutdown sequences. [1] commit 5127be409c6c ("scsi: ufs: ufs-qcom: Fix UFS OCP issue during UFS power down (PC=3)") Link: https://lore.kernel.org/linux-scsi/20260531235011.1052706-3-nitin.rawat@oss.qualcomm.com/ Signed-off-by: Nitin Rawat Signed-off-by: Pradeep P V K (cherry picked from commit 6a34168ee0709f9806be1a07788b8c52fce6d229) --- drivers/ufs/host/ufs-qcom.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 4c61c31820f01..f1a19d6a3913a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -775,9 +775,17 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, if (!ufs_qcom_is_link_active(hba)) ufs_qcom_disable_lane_clks(host); - - /* reset the connected UFS device during power down */ - if (ufs_qcom_is_link_off(hba) && host->device_reset) { + /* + * For some UFS vendors, skip asserting device reset here. + * These vendor parts keep drawing larger current after reset + * is asserted until it is deasserted, and the 10ms delay is + * not sufficient to prevent OCP (Over Current Protection) + * on the regulator. This is for the powerdown case, so + * the device reset can be asserted later as part of the + * platform shutdown sequence. + */ + if (ufs_qcom_is_link_off(hba) && host->device_reset && + !(hba->quirks & UFSHCD_QUIRK_SKIP_DEVICE_RESET)) { ufs_qcom_device_reset_ctrl(hba, true); /* * After sending the SSU command, asserting the rst_n @@ -1114,6 +1122,19 @@ static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = { static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba) { ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups); + + /* + * Some UFS parts keep drawing larger current after reset is asserted + * until it is deasserted. The 10ms delay added after asserting HWRST + * (as done for other vendors) is not sufficient for these parts. + * + * Skip asserting device reset during UFS power down for these parts + * to prevent OCP (Over Current Protection) fault on the regulator. + * This is handled only in shutdown; the device reset will be asserted + * as part of the platform shutdown sequence. + */ + if (hba->dev_info.wmanufacturerid == UFS_VENDOR_MICRON) + hba->quirks |= UFSHCD_QUIRK_SKIP_DEVICE_RESET; } static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) From 2463b81782e20a456d758699bb42ce0923958d64 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 1 Jun 2026 18:37:31 +0530 Subject: [PATCH 1149/1330] arm64: dts: qcom: shikra: Split PMU nodes for heterogeneous CPUs Arm heterogeneous configurations should have separate PMU nodes for each CPU arch as the arch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific arch implementations. All the kryo CPUs are missing PMU compatibles, so they can't be fixed. Signed-off-by: Komal Bajaj (cherry picked from commit b13b14e497f09970cdb10e5ffde09278458786d6) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 4337a8ee49b4e..3257ea4f8f3a0 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -276,9 +276,14 @@ }; }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a78c { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; }; psci: psci { @@ -2154,6 +2159,16 @@ #address-cells = <2>; #size-cells = <2>; ranges; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu3>; + }; + }; }; apcs_glb: mailbox@f400000 { From 375e829c1b4cae18f7d0776cb13cd16cea3f84f3 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 1 Jun 2026 18:43:47 +0530 Subject: [PATCH 1150/1330] arm64: dts: qcom: shikra: switch to interrupt-cells 4 to add PPI partitions The ARM PMUs share the same per-cpu (PPI) interrupt, so we need to switch to interrupt-cells = <4> in the GIC node to allow adding an interrupt partition map phandle as the 4th cell value for GIC_PPI interrupts. Signed-off-by: Komal Bajaj (cherry picked from commit bf449f3bcc8154d4a9e42c29031362f953f56c76) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 368 +++++++++++++-------------- 1 file changed, 184 insertions(+), 184 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 3257ea4f8f3a0..c7aa493304f52 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -296,7 +296,7 @@ glink-edge { compatible = "qcom,glink-rpm"; - interrupts = ; + interrupts = ; qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&apcs_glb 0>; @@ -358,7 +358,7 @@ mpm: interrupt-controller { compatible = "qcom,mpm"; qcom,rpm-msg-ram = <&apss_mpm>; - interrupts = ; + interrupts = ; mboxes = <&apcs_glb 1>; interrupt-controller; #interrupt-cells = <2>; @@ -477,7 +477,7 @@ compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; - interrupts = ; + interrupts = ; mboxes = <&apcs_glb 6>; @@ -500,7 +500,7 @@ compatible = "qcom,smp2p"; qcom,smem = <617>, <616>; - interrupts = ; + interrupts = ; mboxes = <&apcs_glb 10>; @@ -523,7 +523,7 @@ compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; - interrupts = ; + interrupts = ; mboxes = <&apcs_glb 14>; @@ -557,7 +557,7 @@ modem_smsm: modem@1 { reg = <1>; - interrupts = ; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; @@ -587,7 +587,7 @@ compatible = "qcom,shikra-tlmm"; reg = <0x0 0x00500000 0x0 0x800000>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -1021,7 +1021,7 @@ compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x00c91000 0x0 0x1000>; - interrupts = ; + interrupts = ; interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; @@ -1071,7 +1071,7 @@ <0x0 0x0f00000 0x0 0x80000>, <0x0 0x1000000 0x0 0x80000>; reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; - interrupts = ; + interrupts = ; }; gcc: clock-controller@1400000 { @@ -1198,7 +1198,7 @@ cryptobam: dma-controller@1b04000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01b04000 0x0 0x24000>; - interrupts = ; + interrupts = ; #dma-cells = <1>; iommus = <&apps_smmu 0x84 0x0011>, <&apps_smmu 0x86 0x0011>, @@ -1273,8 +1273,8 @@ compatible = "qcom,shikra-tsens", "qcom,tsens-v2"; reg = <0x0 0x04411000 0x0 0x1000>, <0x0 0x04410000 0x0 0x1000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; #qcom,sensors = <14>; @@ -1314,8 +1314,8 @@ iommus = <&apps_smmu 0xc0 0x0>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -1374,8 +1374,8 @@ compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x4784000 0x0 0x1000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <4>; @@ -1435,10 +1435,10 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <133333333>; - interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "dwc_usb3", "pwr_event", "qusb2_phy", @@ -1496,7 +1496,7 @@ "cx_mem", "cx_dbgc"; - interrupts = ; + interrupts = ; clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, <&gpucc GPU_CC_AHB_CLK>, @@ -1603,15 +1603,15 @@ #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + ; clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, @@ -1628,7 +1628,7 @@ iris: video-codec@5a00000 { compatible = "qcom,shikra-iris", "qcom,qcm2290-venus"; reg = <0 0x5a00000 0 0x200000>; - interrupts = ; + interrupts = ; power-domains = <&gcc GCC_VENUS_GDSC>, <&gcc GCC_VCODEC0_GDSC>, @@ -1739,14 +1739,14 @@ "vfe1", "vfe1_cphy_rx"; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "csid0", "csid1", "csiphy0", @@ -1790,7 +1790,7 @@ compatible = "qcom,shikra-cci", "qcom,msm8996-cci"; reg = <0x0 0x05c1b000 0x0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; @@ -1825,7 +1825,7 @@ compatible = "qcom,shikra-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; reg-names = "mdss"; - interrupts = ; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -2053,71 +2053,71 @@ #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; wifi: wifi@c800000 { @@ -2125,18 +2125,18 @@ reg = <0x0 0x0c800000 0x0 0x800000>; reg-names = "membase"; memory-region = <&wlan_mem>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; iommus = <&apps_smmu 0x1a0 0x1>; qcom,msa-fixed-perm; @@ -2148,9 +2148,9 @@ reg = <0x0 0xf200000 0x0 0x10000>, /* GICD */ <0x0 0xf240000 0x0 0x80000>; /* GICR * 4 regions */ - interrupts = ; + interrupts = ; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; #redistributor-regions = <1>; @@ -2180,8 +2180,8 @@ watchdog@f410000 { compatible = "qcom,apss-wdt-shikra", "qcom,kpss-wdt"; reg = <0x0 0x0f410000 0x0 0x1000>; - interrupts = , - ; + interrupts = , + ; clocks = <&sleep_clk>; }; @@ -2197,49 +2197,49 @@ reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; frame-number = <0>; - interrupts = , - ; + interrupts = , + ; }; frame@f423000 { reg = <0x0f423000 0x1000>; frame-number = <1>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@f425000 { reg = <0x0f425000 0x1000>; frame-number = <2>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@f427000 { reg = <0x0f427000 0x1000>; frame-number = <3>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@f429000 { reg = <0x0f429000 0x1000>; frame-number = <4>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@f42b000 { reg = <0x0f42b000 0x1000>; frame-number = <5>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@f42d000 { reg = <0x0f42d000 0x1000>; frame-number = <6>; - interrupts = ; + interrupts = ; status = "disabled"; }; }; @@ -2248,22 +2248,22 @@ compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x04a00000 0x0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; dma-channels = <16>; dma-channel-mask = <0xff>; @@ -2304,7 +2304,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4a80000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; @@ -2336,7 +2336,7 @@ compatible = "qcom,geni-spi"; reg = <0x0 0x4a80000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; @@ -2365,7 +2365,7 @@ compatible = "qcom,geni-debug-uart"; reg = <0x0 0x04a80000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; @@ -2387,7 +2387,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4a84000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; @@ -2419,7 +2419,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04a84000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; @@ -2441,7 +2441,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4a88000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; @@ -2473,7 +2473,7 @@ compatible = "qcom,geni-spi"; reg = <0x0 0x4a88000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; @@ -2502,7 +2502,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04a88000 0x0 0x4000>; - interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>, <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; @@ -2525,7 +2525,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4a8c000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; @@ -2557,7 +2557,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04a8c000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; @@ -2579,7 +2579,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4a90000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; @@ -2611,7 +2611,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04a90000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; @@ -2633,7 +2633,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4a94000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; @@ -2665,7 +2665,7 @@ compatible = "qcom,geni-spi"; reg = <0x0 0x4a94000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; @@ -2694,7 +2694,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04a94000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; @@ -2716,7 +2716,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4a98000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; @@ -2748,7 +2748,7 @@ compatible = "qcom,geni-spi"; reg = <0x0 0x4a98000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; @@ -2777,7 +2777,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04a98000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; @@ -2799,7 +2799,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4a9c000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; @@ -2831,7 +2831,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04a9c000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; @@ -2853,7 +2853,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4aa0000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; clock-names = "se"; @@ -2885,7 +2885,7 @@ compatible = "qcom,geni-spi"; reg = <0x0 0x4aa0000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; clock-names = "se"; @@ -2914,7 +2914,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04aa0000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; clock-names = "se"; @@ -2936,7 +2936,7 @@ compatible = "qcom,geni-i2c"; reg = <0x0 0x4aa4000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; clock-names = "se"; @@ -2968,7 +2968,7 @@ compatible = "qcom,geni-uart"; reg = <0x0 0x04aa4000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; clock-names = "se"; @@ -2990,7 +2990,7 @@ bam_dmux_dma: dma-controller@6044000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x06044000 0x0 0x19000>; - interrupts = ; + interrupts = ; #dma-cells = <1>; qcom,ee = <0>; @@ -3003,7 +3003,7 @@ compatible = "qcom,shikra-mpss-pas"; reg = <0x0 0x06080000 0x0 0x100>; - interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -3034,7 +3034,7 @@ status = "disabled"; glink-edge { - interrupts = ; + interrupts = ; mboxes = <&apcs_glb 12>; qcom,remote-pid = <1>; label = "mpss"; @@ -4300,7 +4300,7 @@ compatible = "qcom,shikra-cdsp-pas"; reg = <0x0 0x0b300000 0x0 0x100000>; - interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>, <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -4331,7 +4331,7 @@ status = "disabled"; glink-edge { - interrupts = ; + interrupts = ; mboxes = <&apcs_glb 4>; qcom,remote-pid = <5>; label = "cdsp"; @@ -4392,7 +4392,7 @@ compatible = "qcom,shikra-lpaicp-pas"; reg = <0x0 0x0b800000 0x0 0x200000>; - interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>, <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, @@ -4415,7 +4415,7 @@ status = "disabled"; glink-edge { - interrupts = ; + interrupts = ; mboxes = <&apcs_glb 9>; qcom,remote-pid = <26>; label = "lpaicp"; @@ -4440,8 +4440,8 @@ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; @@ -4736,9 +4736,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; From b51b74f3254b588bd2d552469461de88b2602cb3 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 2 Jun 2026 14:30:35 +0530 Subject: [PATCH 1151/1330] arm64: dts: qcom: shikra: add cache sizes and fix cpu3 power coefficient Add cache-size properties to the L2 cache for cpu3 (256 KiB) and the shared L3 cache (512 KiB) to allow the kernel to correctly report cache topology. Also correct the dynamic-power-coefficient for cpu3 from 486 to 489 to reflect the accurate power model for that CPU cluster. Signed-off-by: Komal Bajaj (cherry picked from commit d0e416db53dd5e81e391b5b5a624283740b86639) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index c7aa493304f52..814d33a350005 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -120,7 +120,7 @@ enable-method = "psci"; next-level-cache = <&l2_3>; capacity-dmips-mhz = <1946>; - dynamic-power-coefficient = <486>; + dynamic-power-coefficient = <489>; clocks = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; @@ -135,6 +135,7 @@ cache-level = <2>; cache-unified; next-level-cache = <&l3>; + cache-size = <0x40000>; }; }; @@ -164,6 +165,7 @@ compatible = "cache"; cache-level = <3>; cache-unified; + cache-size = <0x80000>; }; }; From 629158ede31f1b834876265f213f2cc22b998cd5 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 2 Jun 2026 14:34:56 +0530 Subject: [PATCH 1152/1330] arm64: dts: qcom: shikra: add SCM clock and reset-cells to firmware node The SCM node requires the CE1 clock to be enabled for cryptographic operations. Add the core clock reference and clock-names property to allow the SCM driver to manage it correctly. Also add #reset-cells = <1> to expose the SCM reset controller interface. Signed-off-by: Komal Bajaj (cherry picked from commit 7a3de337a6748569c2c1b9a7d5057d157b91ae12) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 814d33a350005..908f7b946bfdc 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -186,7 +186,10 @@ firmware { scm { compatible = "qcom,scm-shikra", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; qcom,dload-mode = <&tcsr_regs 0x13000>; + #reset-cells = <1>; interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; }; From ffd6294c857091f5b354900d0fdb0d4acb0b5812 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 2 Jun 2026 14:36:13 +0530 Subject: [PATCH 1153/1330] arm64: dts: qcom: shikra: fix memory node base address The reserved-memory list allocates memory regions well below memory node address, such as hyp@80000000 and smem@86000000. Correct the memory node base address from 0xa0000000 to 0x80000000, which is the actual start of DRAM on shikra. Signed-off-by: Komal Bajaj (cherry picked from commit 801dfaf7d8957784dd47a327a93f551b5fc56c9b) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 908f7b946bfdc..03db5f589f756 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -195,10 +195,10 @@ }; }; - memory@a0000000 { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ - reg = <0x0 0xa0000000 0x0 0x0>; + reg = <0x0 0x80000000 0x0 0x0>; }; modem-etm0 { From 174a0be74f8d13022588e68962de13356579bf9d Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 2 Jun 2026 14:40:10 +0530 Subject: [PATCH 1154/1330] arm64: dts: qcom: shikra: drop unused labels from OPP table entries Remove the per-node labels (e.g. cpu0_opp_768mhz, cpu3_opp_1017mhz) from all OPP entries in cpu0_opp_table and cpu3_opp_table. These labels are not referenced anywhere. Signed-off-by: Komal Bajaj (cherry picked from commit e5898e92cc25c9b890422b9cfe5e2ff039730017) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 03db5f589f756..aadb063279070 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -220,32 +220,32 @@ compatible = "operating-points-v2"; opp-shared; - cpu0_opp_768mhz: opp-768000000 { + opp-768000000 { opp-hz = /bits/ 64 <768000000>; opp-peak-kBps = <1200000 17817600>; }; - cpu0_opp_1017mhz: opp-1017600000 { + opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; opp-peak-kBps = <2188000 25804800>; }; - cpu0_opp_1094mhz: opp-1094400000 { + opp-1094400000 { opp-hz = /bits/ 64 <1094400000>; opp-peak-kBps = <3072000 30105600>; }; - cpu0_opp_1497mhz: opp-1497600000 { + opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-peak-kBps = <4068000 38707200>; }; - cpu0_opp_1612mhz: opp-1612800000 { + opp-1612800000 { opp-hz = /bits/ 64 <1612800000>; opp-peak-kBps = <6220000 43008000>; }; - cpu0_opp_1804mhz: opp-1804800000 { + opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-peak-kBps = <7216000 43622400>; }; @@ -255,27 +255,27 @@ compatible = "operating-points-v2"; opp-shared; - cpu3_opp_1017mhz: opp-1017600000 { + opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; opp-peak-kBps = <2188000 25804800>; }; - cpu3_opp_1190mhz: opp-1190400000 { + opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; opp-peak-kBps = <3072000 30105600>; }; - cpu3_opp_1497mhz: opp-1497600000 { + opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-peak-kBps = <4068000 38707200>; }; - cpu3_opp_1708mhz: opp-1708800000 { + opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-peak-kBps = <6220000 43008000>; }; - cpu3_opp_1900mhz: opp-1900800000 { + opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-peak-kBps = <7216000 43622400>; }; From 87d3c954527e12364c76bb244345c3c02e27913f Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 2 Jun 2026 14:44:28 +0530 Subject: [PATCH 1155/1330] arm64: dts: qcom: shikra: fix LLCC interrupt number Correct the LLCC system cache controller interrupt from SPI 571 to SPI 539, which is the correct GIC SPI line for the LLCC on shikra. Signed-off-by: Komal Bajaj (cherry picked from commit c9c7c8bc008ded7456e555c1e94a0a5c0f26a1a2) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index aadb063279070..cdcca6dc1dcca 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1075,8 +1075,10 @@ reg = <0x0 0x00e00000 0x0 0x80000>, <0x0 0x0f00000 0x0 0x80000>, <0x0 0x1000000 0x0 0x80000>; - reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; - interrupts = ; + reg-names = "llcc0_base", + "llcc1_base", + "llcc_broadcast_base"; + interrupts = ; }; gcc: clock-controller@1400000 { From 232b678d724afe9f4ed74c3aa6f6090b870998c4 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 2 Jun 2026 14:53:18 +0530 Subject: [PATCH 1156/1330] arm64: dts: qcom: shikra: fix qfprom base address and child offsets Correct the qfprom efuse node base address from 0x01b40000 to 0x01b44000 and expand the region size from 0x700 to 0x3000. Update the child fuse offsets accordingly: - hstx-trim: node address and reg corrected to 0x25b - gpu-speed-bin: node address and reg corrected from 0x6006 to 0x2006 Signed-off-by: Komal Bajaj (cherry picked from commit 905504a7e7b44364a7ef824a623d9c598c5f871d) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index cdcca6dc1dcca..4bb91ebb7c1fe 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1237,19 +1237,19 @@ interconnect-names = "memory"; }; - qfprom: efuse@1b40000 { + qfprom: efuse@1b44000 { compatible = "qcom,shikra-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; #address-cells = <1>; #size-cells = <1>; - qusb2_hstx_trim_1: hstx-trim@258 { + qusb2_hstx_trim_1: hstx-trim@25b { reg = <0x25b 0x1>; bits = <1 4>; }; - gpu_speed_bin: gpu-speed-bin@6006 { - reg = <0x6006 0x2>; + gpu_speed_bin: gpu-speed-bin@2006 { + reg = <0x2006 0x2>; bits = <5 8>; }; }; From 2f183f75545b4a3df72f14e470405ae9235f7261 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 2 Jun 2026 14:55:53 +0530 Subject: [PATCH 1157/1330] arm64: dts: qcom: shikra: fix sdhc_1 interconnect tags and power domain Switch the sdhc_1 interconnect path tags from QCOM_ICC_TAG_ALWAYS and QCOM_ICC_TAG_ACTIVE_ONLY to the RPM-specific RPM_ALWAYS_TAG and RPM_ACTIVE_TAG macros, which are the correct tags for RPM-managed interconnects on this platform. Also correct the power domain reference from RPMHPD_CX to RPMPD_VDDCX to match the RPM power domain provider used on shikra. Signed-off-by: Komal Bajaj (cherry picked from commit a86ab965ea5ca09cc68d166bd0b941d03814ecb5) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 4bb91ebb7c1fe..3e98447b01fa3 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1333,14 +1333,14 @@ "core", "xo"; - interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, - <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; - power-domains = <&rpmpd RPMHPD_CX>; + power-domains = <&rpmpd RPMPD_VDDCX>; operating-points-v2 = <&sdhc1_opp_table>; qcom,dll-config = <0x000f642c>; From 4479ea645d6acb5a31ef20f41da97c2fd37e6481 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 2 Jun 2026 14:59:17 +0530 Subject: [PATCH 1158/1330] arm64: dts: qcom: shikra: remove spurious crypto interconnect path from remoteprocs Remove the incorrect second interconnect path using MASTER_CRYPTO_CORE0 from both remoteproc_mpss and remoteproc_cdsp nodes. Each remoteproc should only have the single MASTER_AMPSS_M0 to SLAVE_EBI_CH0 path for CPU-to-DDR bandwidth voting. Signed-off-by: Komal Bajaj (cherry picked from commit 33c690578e3be39e262edde2cf5de11248040cfa) --- arch/arm64/boot/dts/qcom/shikra.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 3e98447b01fa3..67a0e9dfafbac 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -3027,8 +3027,6 @@ clock-names = "xo"; interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; power-domains = <&rpmpd RPMHPD_CX>; @@ -4324,8 +4322,6 @@ clock-names = "xo"; interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; power-domains = <&rpmpd RPMHPD_CX>; From 50b2d1140dd1d2b8274b9ea57520ffa01e2a4c1d Mon Sep 17 00:00:00 2001 From: Sankalp Negi Date: Wed, 3 Jun 2026 02:35:53 -0700 Subject: [PATCH 1159/1330] QCLINUX: dt-bindings: mailbox: qcom-ipcc: Add SAIL client IDs Add IPCC_CLIENT_SAIL0/1/2/3 client ID definitions (27-30) to the qcom-ipcc dt-bindings header for use by the SAIL Mailbox device tree overlay. Signed-off-by: Sankalp Negi (cherry picked from commit 8545f27cda64933da54d72d144bafaf59e2ab685) --- include/dt-bindings/mailbox/qcom-ipcc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h index fd85a79381b31..4ef14cba6bdd6 100644 --- a/include/dt-bindings/mailbox/qcom-ipcc.h +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -33,6 +33,10 @@ #define IPCC_CLIENT_NSP1 18 #define IPCC_CLIENT_TME 23 #define IPCC_CLIENT_WPSS 24 +#define IPCC_CLIENT_SAIL0 27 +#define IPCC_CLIENT_SAIL1 28 +#define IPCC_CLIENT_SAIL2 29 +#define IPCC_CLIENT_SAIL3 30 #define IPCC_CLIENT_GPDSP0 31 #define IPCC_CLIENT_GPDSP1 32 From 5b79a57746ff39833691295e7986ee6773dc1846 Mon Sep 17 00:00:00 2001 From: Sankalp Negi Date: Wed, 3 Jun 2026 02:35:53 -0700 Subject: [PATCH 1160/1330] QCLINUX: arm64: dts: qcom: lemans: Add SAIL Mailbox device tree overlay Add lemans-sail-mb.dtso overlay for Lemans platform providing: - ipcc_computeL1: IPCC Compute-L1 controller - sail_mailbox: SAIL Mailbox device node. Signed-off-by: Sankalp Negi (cherry picked from commit ae662f25eae1ebbe1ea0aea74bdd803b1ae67c6f) --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/lemans-sail-mb.dtso | 65 ++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-sail-mb.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 39f52181b99b8..c97af2b60f6bf 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -522,6 +522,7 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo +dtb-$(CONFIG_ARCH_QCOM) += lemans-sail-mb.dtbo monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo diff --git a/arch/arm64/boot/dts/qcom/lemans-sail-mb.dtso b/arch/arm64/boot/dts/qcom/lemans-sail-mb.dtso new file mode 100644 index 0000000000000..806d7712542bf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-sail-mb.dtso @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&soc { + ipcc_computeL1: qcom,ipcc@488000 { + compatible = "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + num_mbox_chans = <5>; + }; + + sail_mailbox: sail-mailbox@1ffe02c { + compatible = "qcom,sail-mailbox"; + reg = <0x0 0x01FFE02C 0x0 0x10>, + <0x0 0x01FFD018 0x0 0x10>, + <0x0 0x17C0000C 0x0 0x04>; + mboxes = <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x2>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL1 0x3>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x4>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x5>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x6>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x7>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL2 0x8>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL1 0x9>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL2 0xa>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL1 0xb>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0xc>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0xd>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL1 0xe>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL2 0xf>, + <&ipcc_computeL1 IPCC_CLIENT_SAIL3 0x10>; + memory-region = <&sail_mailbox_mem>, + <&sail_ota_mem>; + interrupt-parent = <&ipcc_computeL1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + sail-handshake-delay = <50000>; + status = "okay"; + }; +}; From b9caa536d960d24f99ffed50b374ee3baff4882c Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 3 Jun 2026 17:52:25 +0530 Subject: [PATCH 1161/1330] dt-bindings: firmware: qcom,scm: complete shikra clock constraints Extend the incomplete shikra binding by adding qcom,scm-shikra to the allOf blocks that enforce clock requirements and constrain clock count. Signed-off-by: Komal Bajaj (cherry picked from commit ace7bbf80379046bc822dd68414d74cc8a2eb0ff) --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 4c45c207fc58e..096da72c57c9b 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -144,6 +144,7 @@ allOf: - qcom,scm-msm8974 - qcom,scm-msm8976 - qcom,scm-qcm2290 + - qcom,scm-shikra - qcom,scm-sm6375 then: required: @@ -163,6 +164,7 @@ allOf: - qcom,scm-msm8660 - qcom,scm-msm8960 - qcom,scm-qcm2290 + - qcom,scm-shikra - qcom,scm-sm6375 then: properties: From f90149a848e9be70e04ac75014f2f8d63a18cfd3 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 3 Jun 2026 19:08:10 +0530 Subject: [PATCH 1162/1330] pinctrl: qcom: shikra: align with upstream post-submission review Update the driver per upstream review feedback: remove unused egpio and intr_target_reg fields, drop the UFS_RESET macro, fix GPIO/SDC pin numbering and register offsets, correct rgmii_groups[] and fix whitespace and line wrapping. Signed-off-by: Komal Bajaj (cherry picked from commit f8edc7185f94c85f434fe136c8b8b60c13ad63a7) --- drivers/pinctrl/qcom/pinctrl-shikra.c | 590 ++++++++++---------------- 1 file changed, 228 insertions(+), 362 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c index b9253b0f0755e..ed0bff4a1202b 100644 --- a/drivers/pinctrl/qcom/pinctrl-shikra.c +++ b/drivers/pinctrl/qcom/pinctrl-shikra.c @@ -27,19 +27,16 @@ msm_mux_##f8, \ msm_mux_##f9, \ msm_mux_##f10, \ - msm_mux_##f11 /* egpio mode */ \ + msm_mux_##f11 \ }, \ .nfuncs = 12, \ .ctl_reg = REG_SIZE * id, \ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ - .egpio_enable = 12, \ - .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -64,7 +61,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -80,31 +76,6 @@ .intr_detection_width = -1, \ } -#define UFS_RESET(pg_name, ctl, io) \ - { \ - .grp = PINCTRL_PINGROUP(#pg_name, \ - pg_name##_pins, \ - ARRAY_SIZE(pg_name##_pins)), \ - .ctl_reg = ctl, \ - .io_reg = io, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = 3, \ - .drv_bit = 0, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = 0, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - static const struct pinctrl_pin_desc shikra_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), @@ -268,10 +239,17 @@ static const struct pinctrl_pin_desc shikra_pins[] = { PINCTRL_PIN(159, "GPIO_159"), PINCTRL_PIN(160, "GPIO_160"), PINCTRL_PIN(161, "GPIO_161"), - PINCTRL_PIN(162, "SDC1_DATA"), - PINCTRL_PIN(163, "SDC1_RCLK"), - PINCTRL_PIN(164, "SDC1_CMD"), - PINCTRL_PIN(165, "SDC1_CLK"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "SDC1_RCLK"), + PINCTRL_PIN(167, "SDC1_CLK"), + PINCTRL_PIN(168, "SDC1_CMD"), + PINCTRL_PIN(169, "SDC1_DATA"), + PINCTRL_PIN(170, "SDC2_CLK"), + PINCTRL_PIN(171, "SDC2_CMD"), + PINCTRL_PIN(172, "SDC2_DATA"), }; #define DECLARE_MSM_GPIO_PINS(pin) \ @@ -443,13 +421,13 @@ DECLARE_MSM_GPIO_PINS(163); DECLARE_MSM_GPIO_PINS(164); DECLARE_MSM_GPIO_PINS(165); -static const unsigned int sdc1_data_pins[] = { 162 }; -static const unsigned int sdc1_rclk_pins[] = { 163 }; -static const unsigned int sdc1_cmd_pins[] = { 164 }; -static const unsigned int sdc1_clk_pins[] = { 165 }; -static const unsigned int sdc2_clk_pins[] = { 166 }; -static const unsigned int sdc2_cmd_pins[] = { 167 }; -static const unsigned int sdc2_data_pins[] = { 168 }; +static const unsigned int sdc1_rclk_pins[] = { 166 }; +static const unsigned int sdc1_clk_pins[] = { 167 }; +static const unsigned int sdc1_cmd_pins[] = { 168 }; +static const unsigned int sdc1_data_pins[] = { 169 }; +static const unsigned int sdc2_clk_pins[] = { 170 }; +static const unsigned int sdc2_cmd_pins[] = { 171 }; +static const unsigned int sdc2_data_pins[] = { 172 }; enum shikra_functions { msm_mux_gpio, @@ -734,12 +712,11 @@ static const char *const cri_trng1_groups[] = { }; static const char *const dac_calib_groups[] = { - "gpio3", "gpio4", "gpio17", "gpio18", "gpio19", - "gpio64", "gpio66", "gpio66", "gpio68", "gpio69", - "gpio70", "gpio89", "gpio5", "gpio90", "gpio88", - "gpio117", "gpio97", "gpio118", "gpio116", "gpio6", - "gpio7", "gpio8", "gpio9", "gpio14", "gpio15", - "gpio16", + "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio63", "gpio64", "gpio66", "gpio68", "gpio69", + "gpio70", "gpio88", "gpio89", "gpio90", "gpio97", "gpio116", + "gpio117", "gpio118", }; static const char *const dbg_out_clk_groups[] = { @@ -1114,108 +1091,12 @@ static const char *const rgmii0_mdio_groups[] = { "gpio133", }; -static const char *const rgmii0_rx_ctl_groups[] = { - "gpio122", -}; - -static const char *const rgmii0_rxc_groups[] = { - "gpio121", -}; - -static const char *const rgmii0_rxd0_groups[] = { - "gpio123", -}; - -static const char *const rgmii0_rxd1_groups[] = { - "gpio124", -}; - -static const char *const rgmii0_rxd2_groups[] = { - "gpio125", -}; - -static const char *const rgmii0_rxd3_groups[] = { - "gpio126", -}; - -static const char *const rgmii0_tx_ctl_groups[] = { - "gpio128", -}; - -static const char *const rgmii0_txc_groups[] = { - "gpio127", -}; - -static const char *const rgmii0_txd0_groups[] = { - "gpio129", -}; - -static const char *const rgmii0_txd1_groups[] = { - "gpio130", -}; - -static const char *const rgmii0_txd2_groups[] = { - "gpio131", -}; - -static const char *const rgmii0_txd3_groups[] = { - "gpio132", -}; - -static const char *const rgmii1_mdc_groups[] = { - "gpio150", -}; - -static const char *const rgmii1_mdio_groups[] = { - "gpio149", -}; - -static const char *const rgmii1_rx_ctl_groups[] = { - "gpio138", -}; - -static const char *const rgmii1_rxc_groups[] = { - "gpio137", -}; - -static const char *const rgmii1_rxd0_groups[] = { - "gpio139", -}; - -static const char *const rgmii1_rxd1_groups[] = { - "gpio140", -}; - -static const char *const rgmii1_rxd2_groups[] = { - "gpio141", -}; - -static const char *const rgmii1_rxd3_groups[] = { - "gpio142", -}; - -static const char *const rgmii1_tx_ctl_groups[] = { - "gpio144", -}; - -static const char *const rgmii1_txc_groups[] = { - "gpio143", -}; - -static const char *const rgmii1_txd0_groups[] = { - "gpio145", -}; - -static const char *const rgmii1_txd1_groups[] = { - "gpio146", -}; - -static const char *const rgmii1_txd2_groups[] = { - "gpio147", -}; - -static const char *const rgmii1_txd3_groups[] = { - "gpio148", +static const char *const rgmii_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", + "gpio133", "gpio134", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", }; static const char *const sd_write_protect_groups[] = { @@ -1230,8 +1111,8 @@ static const char *const sdc2_tb_trig_groups[] = { "gpio32", }; -static const char *const ssbi_wtr0_groups[] = { - "gpio70", +static const char *const ssbi_wtr_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", }; static const char *const ssbi_wtr1_groups[] = { @@ -1524,219 +1405,205 @@ static const struct pinfunction shikra_functions[] = { MSM_PIN_FUNCTION(wlan1_adc1), }; -/* Every pin is maintained as a single group, and missing or non-existing pin - * would be maintained as dummy group to synchronize pin group index with - * pin descriptor registered with pinctrl core. - * Clients would not be able to request these dummy pin groups. - */ static const struct msm_pingroup shikra_groups[] = { - [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _, 0, -1), - [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist_fail, _, phase_flag, atest_tsens, _, _, _, - _, _, 0, -1), - [2] = PINGROUP(2, qup0_se0, ddr_bist_start, _, phase_flag, atest_tsens2, _, _, _, _, _, _, - 0, -1), - [3] = PINGROUP(3, qup0_se0, ddr_bist_stop, _, phase_flag, dac_calib, _, _, _, _, _, _, - 0, -1), - [4] = PINGROUP(4, qup0_se1, qup0_se1, ddr_bist_complete, _, phase_flag, dac_calib, _, _, - _, _, _, 0, -1), - [5] = PINGROUP(5, qup0_se1, qup0_se1, _, phase_flag, dac_calib, _, _, _, _, _, _, 0, -1), - [6] = PINGROUP(6, qup0_se2, cri_trng0, _, phase_flag, dac_calib, _, _, _, _, _, _, 0, -1), - [7] = PINGROUP(7, qup0_se2, cri_trng1, _, phase_flag, dac_calib, _, _, _, _, _, _, 0, -1), - [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _, 0, -1), - [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _, 0, -1), - [10] = PINGROUP(10, qup0_se3, qup0_se3, _, _, _, _, _, _, _, _, _, 0, -1), - [11] = PINGROUP(11, qup0_se3, qup0_se3, _, phase_flag, _, _, _, _, _, _, _, 0, -1), - [12] = PINGROUP(12, qup0_se4, qup0_se4, char_exec_release, _, _, _, _, _, _, _, _, 0, -1), - [13] = PINGROUP(13, qup0_se4, qup0_se4, char_exec_pending, _, _, _, _, _, _, _, _, 0, -1), - [14] = PINGROUP(14, qup0_se5, pll_clk, tgu_ch0_trigout, dac_calib, wlan1_adc0, _, _, _, _, - _, _, 0, -1), - [15] = PINGROUP(15, qup0_se5, tgu_ch1_trigout, _, dac_calib, wlan1_adc1, _, _, _, _, _, _, - 0, -1), - [16] = PINGROUP(16, qup0_se5, tgu_ch2_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _, - 0, -1), - [17] = PINGROUP(17, qup0_se5, tgu_ch3_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _, - 0, -1), - [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _, 0, -1), - [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _, 0, -1), - [20] = PINGROUP(20, qup0_se7, qup0_se7, cri_trng, _, _, _, _, _, _, _, _, 0, -1), - [21] = PINGROUP(21, qup0_se7, qup0_se7, tsense_pwm, _, _, _, _, _, _, _, _, 0, -1), - [22] = PINGROUP(22, qup0_se8, pll_clk, agera_pll, pbs_out, _, _, _, _, _, _, _, 0, -1), - [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _, 0, -1), - [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _, 0, -1), - [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _, 0, -1), - [26] = PINGROUP(26, qup0_se9, qup0_se9, _, _, _, _, _, _, _, _, _, 0, -1), - [27] = PINGROUP(27, qup0_se9, qup0_se9, prng_rosc, _, _, _, _, _, _, _, _, 0, -1), - [28] = PINGROUP(28, qup0_se1, qup0_se6, emac1_mcg1, prng_rosc, _, phase_flag, qdss_cti, - _, _, _, _, 0, -1), - [29] = PINGROUP(29, qup0_se1, qup0_se6, emac1_mcg0, _, phase_flag, qdss_cti, _, _, _, _, - _, 0, -1), - [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _, 0, -1), - [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp, emac1_ptp, _, phase_flag, qdss_cti, _, - _, _, _, 0, -1), - [32] = PINGROUP(32, pwm_0, sdc2_tb_trig, _, _, _, _, _, _, _, _, _, 0, -1), - [33] = PINGROUP(33, emac1_ptp, emac1_ptp, sdc1_tb_trig, _, _, _, _, _, _, _, _, 0, -1), - [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _, 0, -1), - [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _, 0, -1), - [36] = PINGROUP(36, cci_i2c_sda0, _, _, _, _, _, _, _, _, _, _, 0, -1), - [37] = PINGROUP(37, cci_i2c_scl0, _, _, _, _, _, _, _, _, _, _, 0, -1), - [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _, 0, -1), - [39] = PINGROUP(39, cci_async_in0, _, _, _, _, _, _, _, _, _, _, 0, -1), - [40] = PINGROUP(40, cci_timer, emac1_mcg2, pwm_1, _, _, _, _, _, _, _, _, 0, -1), - [41] = PINGROUP(41, cci_i2c_sda1, _, _, _, _, _, _, _, _, _, _, 0, -1), - [42] = PINGROUP(42, cci_i2c_scl1, _, _, _, _, _, _, _, _, _, _, 0, -1), - [43] = PINGROUP(43, cci_timer, emac0_mcg3, pll_bist, _, _, _, _, _, _, _, _, 0, -1), - [44] = PINGROUP(44, emac0_mcg2, pll_bist, _, _, _, _, _, _, _, _, _, 0, -1), - [45] = PINGROUP(45, tsc_async, emac0_mcg1, pwm_7, gcc_gp1, _, _, _, _, _, _, _, 0, -1), - [46] = PINGROUP(46, tsc_async, emac0_mcg0, _, _, _, _, _, _, _, _, _, 0, -1), - [47] = PINGROUP(47, cci_timer, emac1_mcg3, _, _, _, _, _, _, _, _, _, 0, -1), - [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _, 0, -1), - [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _, 0, -1), - [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _, 0, -1), - [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _, 0, -1), - [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [53] = PINGROUP(53, _, nav_gpio, gcc_gp3, pwm_7, _, pbs_in, atest_usb, _, _, _, _, 0, -1), - [54] = PINGROUP(54, _, pwm_1, _, pbs_in, phase_flag, atest_char, _, _, _, _, _, 0, -1), - [55] = PINGROUP(55, _, pwm_0, _, pbs_in, phase_flag, atest_char, _, _, _, _, _, 0, -1), - [56] = PINGROUP(56, _, pwm_6, _, pbs_in, phase_flag, atest_char, _, _, _, _, _, 0, -1), - [57] = PINGROUP(57, _, pwm_2, _, pbs_in, phase_flag, atest_char, _, _, _, _, _, 0, -1), - [58] = PINGROUP(58, _, nav_gpio, pwm_8, _, pbs_in, atest_bbrx, atest_usb, - vsense_trigger_mirnat, emac1_dll, _, _, 0, -1), - [59] = PINGROUP(59, _, vfr_1, _, pbs_in, atest_bbrx, atest_usb, emac1_dll, _, _, _, _, - 0, -1), - [60] = PINGROUP(60, _, emac1_ptp, emac1_ptp, emac0_ptp, emac0_ptp, _, pbs_in, - atest_gpsadc, atest_usb, emac0_dll, _, 0, -1), - [61] = PINGROUP(61, _, pwm_9, gcc_gp2, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb, - emac0_dll, _, _, _, 0, -1), - [62] = PINGROUP(62, _, pwm_2, _, pbs_in, phase_flag, atest_char, _, _, _, _, - _, 0, -1), - [63] = PINGROUP(63, _, nav_gpio, emac0_ptp, emac0_ptp, _, pbs_in, phase_flag, dac_calib, - _, _, _, 0, -1), - [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _, 0, -1), - [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _, 0, -1), - [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [68] = PINGROUP(68, _, ssbi_wtr2, emac1_ptp, emac1_ptp, pwm_9, dac_calib, _, _, _, _, _, - 0, -1), - [69] = PINGROUP(69, _, ssbi_wtr3, emac0_ptp, emac0_ptp, _, phase_flag, dac_calib, _, _, _, - _, 0, -1), - [70] = PINGROUP(70, _, ssbi_wtr0, _, phase_flag, dac_calib, _, _, _, _, _, _, 0, -1), - [71] = PINGROUP(71, _, ssbi_wtr1, nav_gpio, _, phase_flag, _, _, _, _, _, _, 0, -1), - [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _, 0, -1), - [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [74] = PINGROUP(74, pll_reset_n, _, pbs_in, phase_flag, _, _, _, _, _, _, _, 0, -1), - [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _, 0, -1), - [76] = PINGROUP(76, pll_bypassnl, _, _, _, _, _, _, _, _, _, _, 0, -1), - [77] = PINGROUP(77, uim2_data, pwm_3, _, _, _, _, _, _, _, _, _, 0, -1), - [78] = PINGROUP(78, uim2_clk, _, _, _, _, _, _, _, _, _, _, 0, -1), - [79] = PINGROUP(79, uim2_reset, pwm_4, _, _, _, _, _, _, _, _, _, 0, -1), - [80] = PINGROUP(80, uim2_present, pwm_5, _, _, _, _, _, _, _, _, _, 0, -1), - [81] = PINGROUP(81, uim1_data, _, _, _, _, _, _, _, _, _, _, 0, -1), - [82] = PINGROUP(82, uim1_clk, _, _, _, _, _, _, _, _, _, _, 0, -1), - [83] = PINGROUP(83, uim1_reset, _, _, _, _, _, _, _, _, _, _, 0, -1), - [84] = PINGROUP(84, uim1_present, _, _, _, _, _, _, _, _, _, _, 0, -1), - [85] = PINGROUP(85, emac0_ptp, emac0_ptp, _, _, _, _, _, _, _, _, _, 0, -1), - [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync, mdp_vsync, _, _, _, _, _, _, _, _, 0, -1), - [87] = PINGROUP(87, _, pwm_6, _, _, _, _, _, _, _, _, _, 0, -1), - [88] = PINGROUP(88, gcc_gp2, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), - [89] = PINGROUP(89, gcc_gp3, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), - [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), - [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _, 0, -1), - [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _, 0, -1), - [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _, 0, -1), - [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _, 0, -1), - [96] = PINGROUP(96, dmic0_clk, cam_mclk, i2s1_clk, jitter_bist, atest_gpsadc, atest_usb, _, - _, _, _, _, 0, -1), - [97] = PINGROUP(97, dmic0_data, i2s1_ws, dac_calib, _, _, _, _, _, _, _, _, 0, -1), - [98] = PINGROUP(98, dmic1_clk, cam_mclk, i2s1_data0, _, _, atest_usb, ddr_pxi0, _, _, _, - _, 0, -1), - [99] = PINGROUP(99, dmic1_data, i2s1_data1, jitter_bist, _, atest_usb, ddr_pxi0, _, _, _, - _, _, 0, -1), - [100] = PINGROUP(100, i2s2_clk, nav_gpio, _, _, atest_usb, ddr_pxi1, _, _, _, _, _, 0, -1), - [101] = PINGROUP(101, i2s2_ws, nav_gpio, _, _, atest_usb, ddr_pxi1, _, _, _, _, _, 0, -1), - [102] = PINGROUP(102, i2s2_data0, pwm_8, _, phase_flag, _, _, _, _, _, _, _, 0, -1), - [103] = PINGROUP(103, ext_mclk, i2s2_data1, _, _, _, _, _, _, _, _, _, 0, -1), - [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _, 0, -1), - [105] = PINGROUP(105, swr0_tx_clk, i2s0_clk, _, _, _, _, _, _, _, _, _, 0, -1), - [106] = PINGROUP(106, swr0_tx_data0, i2s0_ws, _, _, _, _, _, _, _, _, _, 0, -1), - [107] = PINGROUP(107, swr0_rx_clk, i2s0_data0, _, _, _, _, _, _, _, _, _, 0, -1), - [108] = PINGROUP(108, swr0_rx_data0, i2s0_data1, _, _, _, _, _, _, _, _, _, 0, -1), - [109] = PINGROUP(109, swr0_rx_data1, i2s0_data2, sd_write_protect, _, _, _, _, _, _, _, _, - 0, -1), - [110] = PINGROUP(110, ext_mclk, i2s0_data3, _, gcc_gp1, _, _, _, _, _, _, _, 0, -1), - [111] = PINGROUP(111, i2s3_clk, _, _, _, _, _, _, _, _, _, _, 0, -1), - [112] = PINGROUP(112, i2s3_ws, _, _, _, _, _, _, _, _, _, _, 0, -1), - [113] = PINGROUP(113, i2s3_data0, _, _, _, _, _, _, _, _, _, _, 0, -1), - [114] = PINGROUP(114, ext_mclk, i2s3_data1, _, _, _, _, _, _, _, _, _, 0, -1), - [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _, 0, -1), - [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), - [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _, 0, -1), - [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _, 0, -1), - [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [120] = PINGROUP(120, emac0_phy, _, _, _, _, _, _, _, _, _, _, 0, -1), - [121] = PINGROUP(121, rgmii0_rxc, _, _, _, _, _, _, _, _, _, _, 0, -1), - [122] = PINGROUP(122, rgmii0_rx_ctl, _, _, _, _, _, _, _, _, _, _, 0, -1), - [123] = PINGROUP(123, rgmii0_rxd0, _, _, _, _, _, _, _, _, _, _, 0, -1), - [124] = PINGROUP(124, rgmii0_rxd1, _, _, _, _, _, _, _, _, _, _, 0, -1), - [125] = PINGROUP(125, rgmii0_rxd2, _, _, _, _, _, _, _, _, _, _, 0, -1), - [126] = PINGROUP(126, rgmii0_rxd3, _, _, _, _, _, _, _, _, _, _, 0, -1), - [127] = PINGROUP(127, rgmii0_txc, _, _, _, _, _, _, _, _, _, _, 0, -1), - [128] = PINGROUP(128, rgmii0_tx_ctl, _, _, _, _, _, _, _, _, _, _, 0, -1), - [129] = PINGROUP(129, rgmii0_txd0, _, _, _, _, _, _, _, _, _, _, 0, -1), - [130] = PINGROUP(130, rgmii0_txd1, _, _, _, _, _, _, _, _, _, _, 0, -1), - [131] = PINGROUP(131, rgmii0_txd2, _, _, _, _, _, _, _, _, _, _, 0, -1), - [132] = PINGROUP(132, rgmii0_txd3, _, _, _, _, _, _, _, _, _, _, 0, -1), - [133] = PINGROUP(133, rgmii0_mdio, _, _, _, _, _, _, _, _, _, _, 0, -1), - [134] = PINGROUP(134, rgmii0_mdc, _, _, _, _, _, _, _, _, _, _, 0, -1), - [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [136] = PINGROUP(136, emac1_phy, _, _, _, _, _, _, _, _, _, _, 0, -1), - [137] = PINGROUP(137, rgmii1_rxc, _, _, _, _, _, _, _, _, _, _, 0, -1), - [138] = PINGROUP(138, rgmii1_rx_ctl, _, _, _, _, _, _, _, _, _, _, 0, -1), - [139] = PINGROUP(139, rgmii1_rxd0, _, _, _, _, _, _, _, _, _, _, 0, -1), - [140] = PINGROUP(140, rgmii1_rxd1, _, _, _, _, _, _, _, _, _, _, 0, -1), - [141] = PINGROUP(141, rgmii1_rxd2, _, _, _, _, _, _, _, _, _, _, 0, -1), - [142] = PINGROUP(142, rgmii1_rxd3, _, _, _, _, _, _, _, _, _, _, 0, -1), - [143] = PINGROUP(143, rgmii1_txc, _, _, _, _, _, _, _, _, _, _, 0, -1), - [144] = PINGROUP(144, rgmii1_tx_ctl, _, _, _, _, _, _, _, _, _, _, 0, -1), - [145] = PINGROUP(145, rgmii1_txd0, _, _, _, _, _, _, _, _, _, _, 0, -1), - [146] = PINGROUP(146, rgmii1_txd1, _, _, _, _, _, _, _, _, _, _, 0, -1), - [147] = PINGROUP(147, rgmii1_txd2, _, _, _, _, _, _, _, _, _, _, 0, -1), - [148] = PINGROUP(148, rgmii1_txd3, _, _, _, _, _, _, _, _, _, _, 0, -1), - [149] = PINGROUP(149, rgmii1_mdio, _, _, _, _, _, _, _, _, _, _, 0, -1), - [150] = PINGROUP(150, rgmii1_mdc, _, _, _, _, _, _, _, _, _, _, 0, -1), - [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _, 0, -1), - [162] = SDC_QDSD_PINGROUP(sdc1_data, 0x1AC000, 9, 0), - [163] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1AC004, 0, 0), - [164] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1AC000, 11, 3), - [165] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1AC000, 13, 6), - [166] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1AA000, 14, 6), - [167] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1AA000, 11, 3), - [168] = SDC_QDSD_PINGROUP(sdc2_data, 0x1AA000, 9, 0), + [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _), + [2] = PINGROUP(2, qup0_se0, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _, _), + [3] = PINGROUP(3, qup0_se0, ddr_bist, _, phase_flag, dac_calib, _, _, _, _, _, _), + [4] = PINGROUP(4, qup0_se1_23, qup0_se1_01, ddr_bist, _, phase_flag, dac_calib, _, _, _, + _, _), + [5] = PINGROUP(5, qup0_se1_23, qup0_se1_01, _, phase_flag, dac_calib, _, _, _, _, _, _), + [6] = PINGROUP(6, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), + [7] = PINGROUP(7, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), + [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup0_se3_01, qup0_se3_23, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup0_se3_01, qup0_se3_23, _, phase_flag, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _), + [15] = PINGROUP(15, qup0_se5, tgu_ch_trigout, _, dac_calib, wlan, _, _, _, _, _, _), + [16] = PINGROUP(16, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), + [17] = PINGROUP(17, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), + [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup0_se7_01, qup0_se7_23, cri_trng, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup0_se7_01, qup0_se7_23, tsense_pwm, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup0_se9_23, qup0_se9_01, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup0_se9_23, qup0_se9_01, prng_rosc, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup0_se1, qup0_se6, emac_mcg, prng_rosc, _, phase_flag, qdss_cti, + _, _, _, _), + [29] = PINGROUP(29, qup0_se1, qup0_se6, emac_mcg, _, phase_flag, qdss_cti, _, _, _, _, _), + [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _), + [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp_aux, emac1_ptp_pps, _, phase_flag, + qdss_cti, _, _, _, _), + [32] = PINGROUP(32, pwm, sdc_tb_trig, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, emac1_ptp_aux, emac1_ptp_pps, sdc_tb_trig, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, cci_i2c0, _, _, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, cci_i2c0, _, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, cci_async, _, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, cci_timer, emac_mcg, pwm, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, tsc_async, emac_mcg, pwm, gcc_gp, _, _, _, _, _, _, _), + [46] = PINGROUP(46, tsc_async, emac_mcg, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, cci_timer, emac_mcg, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, _, nav_gpio, gcc_gp, pwm, _, pbs_in, atest_usb, _, _, _, _), + [54] = PINGROUP(54, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [55] = PINGROUP(55, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [56] = PINGROUP(56, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [57] = PINGROUP(57, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [58] = PINGROUP(58, _, nav_gpio, pwm, _, pbs_in, atest_bbrx, atest_usb, + vsense_trigger_mirnat, emac_dll, _, _), + [59] = PINGROUP(59, _, vfr, _, pbs_in, atest_bbrx, atest_usb, emac_dll, _, _, _, _), + [60] = PINGROUP(60, _, emac1_ptp_aux, emac1_ptp_pps, emac0_ptp_aux, emac0_ptp_pps, _, + pbs_in, atest_gpsadc, atest_usb, emac_dll, _), + [61] = PINGROUP(61, _, pwm, gcc_gp, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb, + emac_dll, _, _, _), + [62] = PINGROUP(62, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [63] = PINGROUP(63, _, nav_gpio, emac0_ptp_aux, emac0_ptp_pps, _, pbs_in, phase_flag, + dac_calib, _, _, _), + [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, _, ssbi_wtr, emac1_ptp_aux, emac1_ptp_pps, pwm, dac_calib, _, _, _, + _, _), + [69] = PINGROUP(69, _, ssbi_wtr, emac0_ptp_aux, emac0_ptp_pps, _, phase_flag, dac_calib, + _, _, _, _), + [70] = PINGROUP(70, _, ssbi_wtr, _, phase_flag, dac_calib, _, _, _, _, _, _), + [71] = PINGROUP(71, _, ssbi_wtr, nav_gpio, _, phase_flag, _, _, _, _, _, _), + [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _), + [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, uim2, pwm, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, uim2, _, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, uim2, pwm, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, uim2, pwm, _, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, uim1, _, _, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, uim1, _, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, uim1, _, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, uim1, _, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, emac0_ptp_aux, emac0_ptp_pps, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync_out0, mdp_vsync_out1, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, pwm, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [96] = PINGROUP(96, dmic, cam_mclk, i2s1, jitter_bist, atest_gpsadc, atest_usb, _, _, _, + _, _), + [97] = PINGROUP(97, dmic, i2s1, dac_calib, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, dmic, cam_mclk, i2s1, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _), + [99] = PINGROUP(99, dmic, i2s1, jitter_bist, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [100] = PINGROUP(100, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [101] = PINGROUP(101, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [102] = PINGROUP(102, i2s2, pwm, _, phase_flag, _, _, _, _, _, _, _), + [103] = PINGROUP(103, ext_mclk, i2s2, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, swr0_rx, i2s0, sd_write_protect, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, ext_mclk, i2s0, _, gcc_gp, _, _, _, _, _, _, _), + [111] = PINGROUP(111, i2s3, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, i2s3, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, i2s3, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, ext_mclk, i2s3, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, emac_phy, _, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, rgmii, _, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, rgmii, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, rgmii, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, rgmii, _, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, rgmii, _, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, rgmii, _, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, rgmii, _, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, rgmii, _, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, rgmii, _, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, rgmii, _, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, rgmii, _, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, rgmii, _, _, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, rgmii, _, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, rgmii, _, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, emac_phy, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, rgmii, _, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, rgmii, _, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, rgmii, _, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, rgmii, _, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, rgmii, _, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, rgmii, _, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, rgmii, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, rgmii, _, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, rgmii, _, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, rgmii, _, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, rgmii, _, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, rgmii, _, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, rgmii, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, rgmii, _, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, _), + [166] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xac004, 0, 0), + [167] = SDC_QDSD_PINGROUP(sdc1_clk, 0xac000, 13, 6), + [168] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xac000, 11, 3), + [169] = SDC_QDSD_PINGROUP(sdc1_data, 0xac000, 9, 0), + [170] = SDC_QDSD_PINGROUP(sdc2_clk, 0xaa000, 14, 6), + [171] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xaa000, 11, 3), + [172] = SDC_QDSD_PINGROUP(sdc2_data, 0xaa000, 9, 0), }; static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = { - {1, 9}, {2, 31}, {5, 49}, {6, 53}, {9, 72}, {10, 10}, - {12, 22}, {14, 26}, {17, 29}, {18, 24}, {20, 32}, {22, 33}, - {25, 34}, {27, 35}, {28, 36}, {29, 37}, {30, 38}, {31, 39}, - {32, 40}, {33, 41}, {38, 42}, {40, 43}, {43, 44}, {44, 45}, - {45, 46}, {46, 47}, {47, 48}, {48, 60}, {50, 50}, {51, 51}, - {52, 61}, {53, 62}, {57, 52}, {58, 63}, {60, 54}, {63, 64}, - {73, 55}, {74, 56}, {75, 57}, {77, 3}, {80, 4}, {84, 5}, - {85, 67}, {86, 69}, {88, 70}, {89, 71}, {90, 73}, {91, 74}, - {92, 75}, {93, 76}, {94, 77}, {95, 78}, {97, 79}, {99, 80}, - {100, 11}, {101, 13}, {102, 14}, {103, 15}, {106, 16}, {108, 17}, - {112, 18}, {116, 19}, {117, 20}, {119, 21}, {120, 23}, {136, 25}, - {159, 27}, {161, 28}, + {1, 9 }, {2, 31 }, {5, 49 }, {6, 53 }, {9, 72 }, {10, 10 }, + {12, 22 }, {14, 26 }, {17, 29 }, {18, 24 }, {20, 32 }, {22, 33 }, + {25, 34 }, {27, 35 }, {28, 36 }, {29, 37 }, {30, 38 }, {31, 39 }, + {32, 40 }, {33, 41 }, {38, 42 }, {40, 43 }, {43, 44 }, {44, 45 }, + {45, 46 }, {46, 47 }, {47, 48 }, {48, 60 }, {50, 50 }, {51, 51 }, + {52, 61 }, {53, 62 }, {57, 52 }, {58, 63 }, {60, 54 }, {63, 64 }, + {73, 55 }, {74, 56 }, {75, 57 }, {77, 3 }, {80, 4 }, {84, 5 }, + {85, 67 }, {86, 69 }, {88, 70 }, {89, 71 }, {90, 73 }, {91, 74 }, + {92, 75 }, {93, 76 }, {94, 77 }, {95, 78 }, {97, 79 }, {99, 80 }, + {100, 11 }, {101, 13 }, {102, 14 }, {103, 15 }, {106, 16 }, {108, 17 }, + {112, 18 }, {116, 19 }, {117, 20 }, {119, 21 }, {120, 23 }, {136, 25 }, + {159, 27 }, {161, 28 }, }; static const struct msm_pinctrl_soc_data shikra_tlmm = { @@ -1749,7 +1616,6 @@ static const struct msm_pinctrl_soc_data shikra_tlmm = { .ngpios = 166, .wakeirq_map = shikra_mpm_map, .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map), - .egpio_func = 11, }; static int shikra_tlmm_probe(struct platform_device *pdev) @@ -1761,6 +1627,7 @@ static const struct of_device_id shikra_tlmm_of_match[] = { { .compatible = "qcom,shikra-tlmm", .data = &shikra_tlmm }, {}, }; +MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match); static struct platform_driver shikra_tlmm_driver = { .driver = { @@ -1784,4 +1651,3 @@ module_exit(shikra_tlmm_exit); MODULE_DESCRIPTION("QTI Shikra TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match); From b672b217298de9268c1c18cf98f24638b3464eec Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Thu, 28 May 2026 17:21:27 +0530 Subject: [PATCH 1163/1330] QCLINUX: arm64: dts: qcom: Add Glymur crd camx overlay dts Add CAMX overlay dts file for Glymur crd boards. This change also enables the compilation of the CAMX overlay for Glymur crd boards. Signed-off-by: Chandan Kumar Jha (cherry picked from commit a82b9ac9459aeb8c8443bef40c75801a8df2d2d8) --- arch/arm64/boot/dts/qcom/Makefile | 5 + arch/arm64/boot/dts/qcom/glymur-camera.dtsi | 2454 +++++++++++++++++ arch/arm64/boot/dts/qcom/glymur-crd-camx.dtso | 27 + 3 files changed, 2486 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/glymur-camera.dtsi create mode 100644 arch/arm64/boot/dts/qcom/glymur-crd-camx.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index c97af2b60f6bf..0daa3f06f1ce1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -500,6 +500,11 @@ x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += x1-el2.dtbo +glymur-crd-camx-dtbs := glymur-crd.dtb glymur-crd-camx.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd-camx.dtbo + hamoa-evk-camx-dtbs := hamoa-iot-evk.dtb hamoa-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-evk-camx.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-camera.dtsi b/arch/arm64/boot/dts/qcom/glymur-camera.dtsi new file mode 100644 index 0000000000000..9e50200f82830 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-camera.dtsi @@ -0,0 +1,2454 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +&soc { + cam_icp: qcom,icp@ac00000 { + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0 0xac01000 0x0 0x1000>, + <0x0 0x0ac04000 0x0 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x1000 0x4000>; + interrupts = ; + interrupt-names = "icp"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + memory-region = <&camera_mem>; + clocks = <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names = "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clock-rates = <0 300000000 0 0>, + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "nominal"; + nrt-device; + src-clock-name = "icp_clk_src"; + operating-points-v2 = <&icp_opp_table>; + clock-control-debugfs = "true"; + fw_name = "qcom/glymur/CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x00000A0A>; + cam_hw_pid = <3>; + cell-index = <0>; + status = "okay"; + + icp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_cpas: qcom,cam-cpas@ac13000 { + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg = <0x0 0xac13000 0x0 0x1000>, + <0x0 0xac19000 0x0 0xC000>, + <0x0 0xbbf0000 0x0 0x1F00>; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg-cam-base = <0x13000 0x19000 0x0bbf0000>; + interrupts = ; + interrupt-names = "cpas_camnoc"; + camnoc-axi-min-ib-bw = <3000000000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names = "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk", + "camnoc_axi_nrt_clk", + "camcc_debug_clk"; + clock-rates = < 0 0 0 0 0 0 0 0 0 0 0 0>, + < 0 0 0 64000000 0 0 80000000 0 240000000 0 0 0>, + < 0 0 0 80000000 0 0 100000000 0 300000000 0 0 0>, + < 0 0 0 80000000 0 0 400000000 0 400000000 0 0 0>; + clock-cntl-level = "suspend", "lowsvsd1", "lowsvs", "nominal"; + clock-names-option = "cam_icp_clk"; + clocks-option = <&camcc CAM_CC_ICP_CLK>; + clock-rates-option = <400000000>; + src-clock-name = "camnoc_axi_clk_src"; + operating-points-v2 = <&cpas_opp_table>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + cam-icc-path-names = "cam_ahb"; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnects =<&hsc_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_sf_0", + "cam_sf_icp"; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = <0 0>, <0 76800>, <0 76800>, <0 150000>, + <0 150000>, <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = "csiphy0", "csiphy1", "csiphy4", + "cci0", "cci1", "csid0", "csid1", "csid2", + "csid3", "ife0", "ife1", "ife2", "ife3", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", + "rt-cdm3", "cam-cdm-intf0", "bps0", "icp0", + "jpeg-dma0", "jpeg-enc0", "tpg13", "tpg14", + "tpg15"; + cell-index = <0>; + status = "okay"; + + camera-bus-nodes { + level0-nodes { + level-index = <0>; + + bps0_all_rd: bps0-all-rd { + cell-index = <0>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <1>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_wr>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <2>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt1_rd>; + }; + + ife0_linear_stats_wr: ife0-linear-stats-wr { + cell-index = <3>; + node-name = "ife0-linear-stats-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr3>; + }; + + ife0_pdaf_wr: ife0-pdaf-wr { + cell-index = <4>; + node-name = "ife0-pdaf-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_rt0_wr2>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <5>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <6>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_linear_stats_wr: ife1-linear-stats-wr { + cell-index = <7>; + node-name = "ife1-linear-stats-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr3>; + }; + + ife1_pdaf_wr: ife1-pdaf-wr { + cell-index = <8>; + node-name = "ife1-pdaf-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <9>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <10>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr0>; + }; + + ife2_rdi_stats_pixel_raw_wr: ife2-rdi-stats-pixel-raw-wr { + cell-index = <11>; + node-name = "ife2-rdi-stats-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr4>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <12>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level1_rt0_wr4>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <13>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + constituent-paths = ; + parent-node = <&level2_nrt0_wr>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <14>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <15>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <16>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <17>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_wr0>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <18>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <19>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_wr0>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <20>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <21>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + /* IFE Lite 0 */ + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <22>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + + /* IFE Lite 1 */ + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <23>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = ; + parent-node = <&level1_nrt0_rd1>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <24>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <25>; + node-name = "level1-nrt0-rd1"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <26>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <27>; + node-name = "level1-sfe-rd"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = ; + }; + + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <28>; + node-name = "level1-ife-ubwc-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <29>; + node-name = "level1-ife-rdi-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <30>; + node-name = "level1-ife-pdaf"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr3: level1-rt0-wr3 { + cell-index = <31>; + node-name = "level1-ife01-linear-stats"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + + level1_rt0_wr4: level1-rt0-wr4 { + cell-index = <32>; + node-name = "level1-ifelite"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = ; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <33>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <34>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <35>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = ; + bus-width-factor = <4>; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <36>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_wr: level2-rt0-wr { + cell-index = <37>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + }; + + level3-nodes { + level-index = <3>; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <38>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <39>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_icp"; + }; + }; + + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <40>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0"; + }; + }; + }; + }; + + cpas_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_cci0: qcom,cci0@ac15000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac15000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupts = ; + interrupt-names = "cci0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + operating-points-v2 = <&cci0_opp_table>; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + cell-index = <0>; + status = "okay"; + + cci0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci0: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_100Khz_cci0: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + }; + + cam_cci1: qcom,cci1@ac16000 { + compatible = "qcom,cci", "simple-bus"; + reg = <0x0 0xac16000 0x0 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupts = ; + interrupt-names = "cci1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + operating-points-v2 = <&cci1_opp_table>; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci3_active>; + pinctrl-3 = <&cci3_suspend>; + cell-index = <1>; + status = "okay"; + + cci1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + i2c_freq_custom_cci1: qcom,i2c-custom-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c-fast-mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c-fast-plus-mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + + i2c_freq_100Khz_cci1: qcom,i2c-standard-mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "okay"; + }; + }; + + qcom,rt-cdm0@ac25000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac25000 0x0 0x400>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupts = ; + interrupt-names = "rt-cdm0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-rates = <400000000 0>; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table0>; + nrt-device; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <0>; + status = "okay"; + + cdm_cpas_opp_table0: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm1@ac26000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xac26000 0x0 0x400>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x26000>; + interrupts = ; + interrupt-names = "rt-cdm1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + clock-rates = <400000000 0>; + src-clock-name = "cam_cc_fast_ahb_clk_src"; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table1>; + nrt-device; + cdm-client-names = "ife1", "dualife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <1>; + status = "okay"; + + cdm_cpas_opp_table1: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_jpeg_enc: qcom,jpegenc@ac2a000 { + compatible = "qcom,cam_jpeg_enc_680"; + reg = <0x0 0xac2a000 0x0 0x1000>, + <0x0 0x0ac19000 0x0 0xc000>; + reg-names = "jpegenc_hw", "cam_camnoc"; + reg-cam-base = <0x2a000 0x19000>; + interrupts = ; + interrupt-names = "jpeg"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "jpegenc_clk_src", + "jpegenc_clk"; + clock-rates = <160000000 0>, + <200000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + operating-points-v2 = <&jpeg_enc_opp_table>; + nrt-device; + cam_hw_pid = <12 14>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + cell-index = <0>; + status = "okay"; + + jpeg_enc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-48000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_jpeg_dma: qcom,jpegdma@ac2b000 { + compatible = "qcom,cam_jpeg_dma_680"; + reg = <0x0 0xac2b000 0x0 0x1000>, + <0x0 0x0ac19000 0x0 0xc000>; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg-cam-base = <0x2b000 0x19000>; + interrupts = ; + interrupt-names = "jpegdma"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-names = "jpegdma_clk_src", + "jpegdma_clk"; + clock-rates = <160000000 0>, + <200000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + operating-points-v2 = <&jpeg_dma_opp_table>; + nrt-device; + cam_hw_pid = <13 15>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + cell-index = <0>; + status = "okay"; + + jpeg_dma_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-48000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_bps: qcom,bps@ac2c000 { + compatible = "qcom,cam-bps680"; + reg = <0x0 0xac2c000 0x0 0xb000>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + power-domains = <&camcc CAM_CC_BPS_GDSC>; + clocks = <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_CPAS_BPS_CLK>; + clock-names = "bps_ahb_clk", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk", + "cam_cc_cpas_bps_clk"; + clock-rates = <0 0 160000000 0 0>, + <0 0 200000000 0 0>, + <0 0 400000000 0 0>, + <0 0 600000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "nominal"; + nrt-device; + src-clock-name = "bps_clk_src"; + operating-points-v2 = <&bps_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <6 7>; + cell-index = <0>; + status = "okay"; + + bps_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + compatible = "qcom,cam-ipe680"; + reg = <0x0 0xac42000 0x0 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + power-domains = <&camcc CAM_CC_IPE_0_GDSC>; + clocks = <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CPAS_IPE_NPS_CLK>; + clock-names = "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_cpas_ipe_nps_clk"; + clock-rates = <0 0 0 304000000 0 0 0>, + <0 0 0 364000000 0 0 0>, + <0 0 0 500000000 0 0 0>, + <0 0 0 600000000 0 0 0>, + <0 0 0 700000000 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + operating-points-v2 = <&ipe0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <22 23 30>; + cell-index = <0>; + status = "okay"; + + ipe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-304000000 { + opp-hz = /bits/ 64 <304000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-364000000 { + opp-hz = /bits/ 64 <364000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe0: qcom,ife0@ac62000 { + compatible = "qcom,vfe680"; + reg = <0x0 0xac62000 0x0 0xf000>, + <0x0 0xac19000 0x0 0xc000>; + reg-names = "ife", "cam_camnoc"; + reg-cam-base = <0x62000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "ife0"; + power-domains = <&camcc CAM_CC_IFE_0_GDSC>; + clocks = <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>; + clock-names = "ife_0_fast_ahb", + "ife_0_clk_src", + "ife_0_clk", + "cam_cc_cpas_ife_0_clk"; + clock-rates = <0 345600000 0 0>, + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_0_clk_src"; + operating-points-v2 = <&vfe0_opp_table>; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 4 20 8>; + cell-index = <0>; + status = "okay"; + + vfe0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-727000000 { + opp-hz = /bits/ 64 <727000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe1: qcom,ife1@ac71000 { + compatible = "qcom,vfe680"; + reg = <0x0 0xac71000 0x0 0xf000>, + <0x0 0xac19000 0x0 0xc000>; + reg-names = "ife", "cam_camnoc"; + reg-cam-base = <0x71000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "ife1"; + power-domains = <&camcc CAM_CC_IFE_1_GDSC>; + clocks = <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>; + clock-names = "ife_1_fast_ahb", + "ife_1_clk_src", + "ife_1_clk", + "cam_cc_cpas_ife_1_clk"; + clock-rates = <0 345600000 0 0>, + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_1_clk_src"; + operating-points-v2 = <&vfe1_opp_table>; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <17 5 21 9>; + cell-index = <1>; + status = "okay"; + + vfe1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-727000000 { + opp-hz = /bits/ 64 <727000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid0: qcom,csid0@acb7000 { + compatible = "qcom,csid695"; + reg = <0x0 0xacb7000 0x0 0xd00>, + <0x0 0xacb6000 0x0 0x1000>; + reg-names = "csid", "csid_top"; + reg-cam-base = <0xb7000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "csid0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0 0>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clock-rates = <300000000 0 0>, + <400000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "csid_clk_src"; + operating-points-v2 = <&csid0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <0>; + status = "okay"; + + csid0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid1: qcom,csid1@acb9000 { + compatible = "qcom,csid695"; + reg = <0x0 0xacb9000 0x0 0xd00>, + <0x0 0xacb6000 0x0 0x1000>; + reg-names = "csid", "csid_top"; + reg-cam-base = <0xb9000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupts = ; + interrupt-names = "csid1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <1 0 0>; + clocks = <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clock-rates = <300000000 0 0>, + <400000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "csid_clk_src"; + operating-points-v2 = <&csid1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <1>; + status = "okay"; + + csid1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite0: qcom,csid-lite0@acc6000 { + compatible = "qcom,csid-lite680"; + reg = <0x0 0xacc6000 0x0 0xa00>; + reg-names = "csid-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xc6000>; + interrupts = ; + interrupt-names = "csid-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 1 0 0 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite0_opp_table>; + clock-control-debugfs = "true"; + cell-index = <2>; + status = "okay"; + + csid_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite0: qcom,ife-lite0@acc6000 { + compatible = "qcom,vfe-lite695"; + reg = <0x0 0xacc6000 0x0 0x4000>; + reg-names = "ife-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xc6000>; + interrupts = ; + interrupt-names = "ife-lite0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 0 0 1 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite0_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <0>; + cell-index = <2>; + status = "okay"; + + vfe_lite0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csid_lite1: qcom,csid-lite1@acca000 { + compatible = "qcom,csid-lite680"; + reg = <0x0 0xacca000 0x0 0xa00>; + reg-names = "csid-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xca000>; + interrupts = ; + interrupt-names = "csid-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 1 0 0 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb_clk", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_csid_clk_src"; + operating-points-v2 = <&csid_lite1_opp_table>; + clock-control-debugfs = "true"; + cell-index = <3>; + status = "okay"; + + csid_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_vfe_lite1: qcom,ife-lite1@acca000 { + compatible = "qcom,vfe-lite695"; + reg = <0x0 0xacca000 0x0 0x4000>; + reg-names = "ife-lite"; + rt-wrapper-base = <0xc6000>; + reg-cam-base = <0xca000>; + interrupts = ; + interrupt-names = "ife-lite1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + shared-clks = <0 0 0 1 0 0>; + clocks = <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-names = "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clock-rates = <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "ife_lite_clk_src"; + operating-points-v2 = <&vfe_lite1_opp_table>; + clock-control-debugfs = "true"; + cam_hw_pid = <1>; + cell-index = <3>; + status = "okay"; + + vfe_lite1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266666667 { + opp-hz = /bits/ 64 <266666667>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xace4000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupts = ; + interrupt-names = "CSIPHY0"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l4f_e1_1p08>; + csi-vdd-0p9-supply = <&vreg_l1f_e1_0p82>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 832000>; + rgltr-max-voltage = <1200000 832000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = <300000000 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy0_opp_table>; + cell-index = <0>; + status = "okay"; + + csiphy0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xace6000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupts = ; + interrupt-names = "CSIPHY1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l4f_e1_1p08>; + csi-vdd-0p9-supply = <&vreg_l1f_e1_0p82>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 832000>; + rgltr-max-voltage = <1200000 832000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = <300000000 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy1_opp_table>; + cell-index = <1>; + status = "okay"; + + csiphy1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0 0xacec000 0x0 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupts = ; + interrupt-names = "CSIPHY4"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + regulator-names = "csi-vdd-1p2", "csi-vdd-0p9"; + csi-vdd-1p2-supply = <&vreg_l4f_e1_1p08>; + csi-vdd-0p9-supply = <&vreg_l1f_e1_0p82>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <1200000 832000>; + rgltr-max-voltage = <1200000 832000>; + rgltr-load-current = <58900 147000>; + shared-clks = <1 0 0 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = <300000000 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + operating-points-v2 = <&csiphy4_opp_table>; + cell-index = <4>; + status = "okay"; + + csiphy4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf6000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg0", "cam_cpas_top"; + reg-cam-base = <0xf6000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg0"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg0_opp_table>; + cell-index = <13>; + phy-id = <0>; + status = "okay"; + + csiphy_tpg0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf7000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg1", "cam_cpas_top"; + reg-cam-base = <0xf7000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg1"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg1_opp_table>; + cell-index = <14>; + phy-id = <1>; + status = "okay"; + + csiphy_tpg1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + cam_csiphy_tpg15: qcom,tpg15@acf8000 { + compatible = "qcom,cam-tpg103"; + reg = <0x0 0xacf8000 0x0 0x400>, + <0x0 0xac13000 0x0 0x1000>; + reg-names = "tpg2", "cam_cpas_top"; + reg-cam-base = <0xf8000 0x13000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + interrupts = ; + interrupt-names = "tpg2"; + shared-clks = <1 0>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-names = "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clock-rates = <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + operating-points-v2 = <&csiphy_tpg2_opp_table>; + cell-index = <15>; + phy-id = <2>; + status = "okay"; + + csiphy_tpg2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm2@acf9000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xacf9000 0x0 0x400>; + reg-names = "rt-cdm2"; + reg-cam-base = <0xf9000>; + interrupts = ; + interrupt-names = "rt-cdm2"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_lite_ahb"; + clock-rates = <80000000 0>; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table2>; + nrt-device; + cdm-client-names = "ife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <2>; + status = "okay"; + + cdm_cpas_opp_table2: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,rt-cdm3@acfa000 { + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0x0 0xacfa000 0x0 0x400>; + reg-names = "rt-cdm3"; + reg-cam-base = <0xfa000>; + interrupts = ; + interrupt-names = "rt-cdm3"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_ife_lite_ahb"; + clock-rates = <80000000 0>; + src-clock-name = "cam_cc_slow_ahb_clk_src"; + clock-cntl-level = "nominal"; + operating-points-v2 = <&cdm_cpas_opp_table3>; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + cell-index = <3>; + status = "okay"; + + cdm_cpas_opp_table3: opp-table { + compatible = "operating-points-v2"; + + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + cell-index = <0>; + status = "okay"; + }; + + cam_icp_firmware: qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "okay"; + icp_pc_en; + icp_use_pil; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "okay"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "okay"; + }; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "okay"; + }; + + cam_smmu: qcom,cam-smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "okay"; + force_cache_allocs; + need_shared_buffer_padding; + + msm-cam-smmu-cpas-cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x0000>; + cam-smmu-label = "rt-cdm"; + dma-coherent; + multiple-client-devices; + + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1800 0x0060>, + <&apps_smmu 0x1820 0x0060>, + <&apps_smmu 0x1840 0x0060>, + <&apps_smmu 0x1860 0x0060>, + <&apps_smmu 0x1900 0x0000>, + <&apps_smmu 0x1980 0x0020>, + <&apps_smmu 0x19A0 0x0020>; + cam-smmu-label = "icp"; + dma-coherent; + + icp_iova_mem_map: iova-mem-map { + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x14b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "okay"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + iova-region-start = <0x14400000>; + iova-region-len = <0x700000>; + iova-region-id = <0x6>; + status = "okay"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.7 GB */ + iova-region-name = "io"; + iova-region-start = <0x14c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + status = "okay"; + }; + + iova-mem-region-shared { + /* Shared region is ~250MB long */ + iova-region-name = "shared"; + iova-region-start = <0x4800000>; + iova-region-len = <0xFC00000>; + iova-region-id = <0x1>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0820 0x0000>; + dma-coherent; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18E0 0x0000>; + cam-smmu-label = "jpeg"; + dma-coherent; + + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "okay"; + }; + }; + }; + + msm-cam-smmu-secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "okay"; + }; + + qcom,camera-main { + compatible = "qcom,camera_x1e80100"; + status = "okay"; + }; +}; + +&tlmm { + cam_sensor_active_rst0: cam-sensor-active-rst0 { + /* RESET REAR */ + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + pins = "gpio109"; + function = "gpio"; + }; + }; + + cam_sensor_suspend_rst0: cam-sensor-suspend-rst0 { + /* RESET REAR */ + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + + mux { + pins = "gpio109"; + function = "gpio"; + }; + }; + + cam_sensor_active_rst4: cam-sensor-active-rst4 { + /* RESET REAR */ + config { + pins = "gpio239"; + bias-disable; /* No PULL */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio239"; + function = "gpio"; + }; + }; + + cam_sensor_suspend_rst4: cam-sensor-suspend-rst4 { + /* RESET REAR */ + config { + pins = "gpio239"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <12>; /* 12 MA */ + output-low; + }; + + mux { + pins = "gpio239"; + function = "gpio"; + }; + }; + + cam_sensor_mclk0_active: cam-sensor-mclk0-active { + /* mclk0 */ + config { + pins = "gpio96"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk0_suspend: cam-sensor-mclk0-suspend { + /* mclk0 */ + config { + pins = "gpio96"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk1_active: cam-sensor-mclk1-active { + /* mclk1 */ + config { + pins = "gpio97"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio97"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk1_suspend: cam-sensor-mclk1-suspend { + /* mclk1 */ + config { + pins = "gpio97"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio97"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk2_active: cam-sensor-mclk2-active { + /* mclk2 */ + config { + pins = "gpio98"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio98"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk2_suspend: cam-sensor-mclk2-suspend { + /* mclk2 */ + config { + pins = "gpio98"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio98"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk3_active: cam-sensor-mclk3-active { + /* mclk3 */ + config { + pins = "gpio99"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio99"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk3_suspend: cam-sensor-mclk3-suspend { + /* mclk3 */ + config { + pins = "gpio99"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + + mux { + pins = "gpio99"; + function = "cam_mclk"; + }; + }; + + cam_sensor_mclk4_active: cam-sensor-mclk4-active { + /* mclk4 */ + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio100"; + function = "cam_asc_mclk4"; + }; + }; + + cam_sensor_mclk4_suspend: cam-sensor-mclk4-suspend { + /* mclk4 */ + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <12>; /* 12 MA */ + }; + + mux { + pins = "gpio100"; + function = "cam_asc_mclk4"; + }; + }; + + cci_i2c_sda0_active: cci_i2c_sda0_active { + mux { + /* CLK, DATA */ + pins = "gpio101"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio101"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda0_suspend: cci_i2c_sda0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio101"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio101"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci_i2c_scl0_active { + mux { + /* CLK, DATA */ + pins = "gpio102"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio102"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl0_suspend: cci_i2c_scl0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio102"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci_i2c_sda1_active { + mux { + /* CLK, DATA */ + pins = "gpio103"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio103"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda1_suspend: cci_i2c_sda1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio103"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio103"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci_i2c_scl1_active { + mux { + /* CLK, DATA */ + pins = "gpio104"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio104"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl1_suspend: cci_i2c_scl1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio104"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci_i2c_sda2_active { + mux { + /* CLK, DATA */ + pins = "gpio105"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio105"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda2_suspend: cci_i2c_sda2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio105"; + function = "cci_i2c_sda"; + }; + + config { + pins = "gpio105"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci_i2c_scl2_active { + mux { + /* CLK, DATA */ + pins = "gpio106"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio106"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl2_suspend: cci_i2c_scl2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio106"; + function = "cci_i2c_scl"; + }; + + config { + pins = "gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3-active { + config { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + function = "asc_cci"; + }; + }; + + cci3_suspend: cci3-suspend { + config { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + mux { + /* DATA, CLK */ + pins = "gpio235","gpio236"; + function = "asc_cci"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd-camx.dtso b/arch/arm64/boot/dts/qcom/glymur-crd-camx.dtso new file mode 100644 index 0000000000000..b75789c8aae6b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd-camx.dtso @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "glymur-camera.dtsi" + +&cam_icp_firmware { + camera-firmware { + iommus = <&apps_smmu 0x1901 0x0000>; + }; +}; From f4cfa9e15c585ba25dca90ac4ef8e309f86ada24 Mon Sep 17 00:00:00 2001 From: Karthik S Date: Wed, 20 May 2026 13:45:57 +0530 Subject: [PATCH 1164/1330] FROMLIST: arm64: dts: qcom: lemans: Enable audio over DISPLAY-PORT Add dailinks for DISPLAY-PORT to enable audio functionality on edp0. Link: https://lore.kernel.org/all/20260413043713.1659-1-kumar.singh@oss.qualcomm.com/ Signed-off-by: Karthik S (cherry picked from commit 0199b6378e8ad89ca9ec5b5beafd8e0d7f0aa11c) --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 7f379d9b82d78..b19cc80680038 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -189,6 +189,22 @@ sound-dai = <&q6apm>; }; }; + + dp0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss0_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; usb2_vbus: regulator-usb2-vbus { From 5df1ab7b34d41cfd7211376b07005e8b9c335484 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Fri, 27 Feb 2026 00:29:32 +0530 Subject: [PATCH 1165/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Move SD card support to overlay The lemans EVK board supports either eMMC or SD-card, but only one can be active at a time. Move the SDHC node for SD card into a dedicated device tree overlay. This decoupling allows the storage medium to be selected dynamically by applying the appropriate overlay for either SD card or eMMC support. Link: https://lore.kernel.org/all/20260227102405.2339544-2-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara (cherry picked from commit a9adf3c2277fc0debbc559c146cef697b6a1f33f) --- arch/arm64/boot/dts/qcom/Makefile | 3 +++ .../boot/dts/qcom/lemans-evk-sd-card.dtso | 25 +++++++++++++++++++ arch/arm64/boot/dts/qcom/lemans-evk.dts | 16 ------------ 3 files changed, 28 insertions(+), 16 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-sd-card.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0daa3f06f1ce1..5552aa9dbf301 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -44,6 +44,9 @@ dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb +lemans-evk-sd-card-dtbs := lemans-evk.dtb lemans-evk-sd-card.dtbo +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-sd-card.dtb + lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo lemans-evk-camera-dtbs := lemans-evk.dtb lemans-evk-camera.dtbo diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-sd-card.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-sd-card.dtso new file mode 100644 index 0000000000000..007ab63473495 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-sd-card.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&sdhc { + vmmc-supply = <&vmmc_sdc>; + vqmmc-supply = <&vreg_sdc>; + + pinctrl-0 = <&sdc_default>, <&sd_cd>; + pinctrl-1 = <&sdc_sleep>, <&sd_cd>; + pinctrl-names = "default", "sleep"; + + bus-width = <4>; + cd-gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index b19cc80680038..59daedd02e848 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -939,22 +939,6 @@ status = "okay"; }; -&sdhc { - vmmc-supply = <&vmmc_sdc>; - vqmmc-supply = <&vreg_sdc>; - - pinctrl-0 = <&sdc_default>, <&sd_cd>; - pinctrl-1 = <&sdc_sleep>, <&sd_cd>; - pinctrl-names = "default", "sleep"; - - bus-width = <4>; - cd-gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; - no-mmc; - no-sdio; - - status = "okay"; -}; - &serdes0 { phy-supply = <&vreg_l5a>; vdda-0p9-supply = <&vreg_l4a>; From ba2d3d157961f97bce1f6f87f5acfff41095e2d2 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Fri, 27 Feb 2026 00:33:16 +0530 Subject: [PATCH 1166/1330] FROMLIST: arm64: dts: qcom: lemans-evk: Add SDHCI support for eMMC via overlay Enable the SDHCI controller for eMMC functionality on the lemans EVK using a device tree overlay. Configure the corresponding addresse space and resources for eMMC. Link: https://lore.kernel.org/all/20260227102405.2339544-3-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara (cherry picked from commit 8b52a77ad91f9289239ff6f190d17ccf46d5a4f4) --- arch/arm64/boot/dts/qcom/Makefile | 3 + arch/arm64/boot/dts/qcom/lemans-evk-emmc.dtso | 64 +++++++++++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 10 ++- 3 files changed, 74 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-emmc.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5552aa9dbf301..82248b1d91461 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -44,6 +44,9 @@ dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb +lemans-evk-emmc-dtbs := lemans-evk.dtb lemans-evk-emmc.dtbo +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-emmc.dtb + lemans-evk-sd-card-dtbs := lemans-evk.dtb lemans-evk-sd-card.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-sd-card.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-emmc.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-emmc.dtso new file mode 100644 index 0000000000000..52739d39a1ff8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-emmc.dtso @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + vmmc_sdc1: regulator-l8c { + compatible = "regulator-fixed"; + regulator-name = "vreg-sdc1"; + + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + }; + + vqmmc_sdc1: regulator-s4a { + compatible = "regulator-fixed"; + regulator-name = "vqmmc-sdc1"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&sdhc { + vmmc-supply = <&vmmc_sdc1>; + vqmmc-supply = <&vqmmc_sdc1>; + + pinctrl-0 = <&sdc_default>, <&sdc_rclk>; + pinctrl-1 = <&sdc_sleep>, <&sdc_rclk_sleep>; + + pinctrl-names = "default", "sleep"; + + supports-cqe; + non-removable; + + qcom,dll-config = <0x000F64EC>; + max-frequency = <50000000>; + + bus-width = <8>; + no-sd; + no-sdio; + + status = "okay"; +}; + +&tlmm { + sdc_rclk: sdc1-rclk-state { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + sdc_rclk_sleep: sdc1-rclk-sleep-state { + pins = "sdc1_rclk"; + drive-strength = <2>; + bias-bus-hold; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 23a97ed059946..211c4df9c75f0 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3963,7 +3963,9 @@ sdhc: mmc@87c4000 { compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x0 0x087c4000 0x0 0x1000>; + reg = <0x0 0x87C4000 0x0 0x1000>, + <0x0 0x87C5000 0x0 0x1000>; + reg-names = "hc", "cqhci"; interrupts = , ; @@ -3971,9 +3973,11 @@ "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", - "core"; + "core", + "xo"; interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, From 52546e6b10829a00268e69fd8a7fc3125c8bdbd4 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 5 May 2026 17:53:51 +0530 Subject: [PATCH 1167/1330] FROMLIST: arm64: dts: qcom: lemans: add AEST error nodes Add AEST RAS error source nodes for the Lemans SoC. The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-7-d5d6ffacf0a5@oss.qualcomm.com/ Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda (cherry picked from commit 46bbcdd823a1063b91fb3c7637f0ef77fbe320ea) --- arch/arm64/boot/dts/qcom/lemans.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 211c4df9c75f0..182b458ac4516 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -30,6 +31,46 @@ #address-cells = <2>; #size-cells = <2>; + aest { + compatible = "arm,aest"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aest-processor-0 { + compatible = "arm,aest-processor"; + arm,num-records = <1>; + arm,record-impl = /bits/ 64 <0x0>; + arm,status-reporting = /bits/ 64 <0x0>; + arm,addressing-mode = /bits/ 64 <0x0>; + arm,processor-flags = ; + interrupts = ; + interrupt-names = "fhi"; + }; + + aest-l3-cluster0 { + compatible = "arm,aest-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x1>; + arm,status-reporting = /bits/ 64 <0x0>; + arm,addressing-mode = /bits/ 64 <0x0>; + arm,processor-flags = ; + interrupts = ; + interrupt-names = "fhi"; + }; + + aest-l3-cluster1 { + compatible = "arm,aest-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x1>; + arm,status-reporting = /bits/ 64 <0x0>; + arm,addressing-mode = /bits/ 64 <0x0>; + arm,processor-flags = ; + interrupts = ; + interrupt-names = "fhi"; + }; + }; + clocks { xo_board_clk: xo-board-clk { compatible = "fixed-clock"; From 6527ac0bbe5a13e0813e28363f0920e70b9c973b Mon Sep 17 00:00:00 2001 From: Jianping Li Date: Tue, 19 May 2026 17:40:19 +0800 Subject: [PATCH 1168/1330] FROMLIST: fastrpc: Reduce log level for DSP info and reserved memory messages On some platforms (e.g. QCS615 Talos), fastrpc may temporarily fail to retrieve DSP attributes during boot, resulting in repeated "Error: dsp information is incorrect" messages printed on the console. These messages are observed continuously during boot when metadata flashing is enabled as part of RC releases, causing unnecessary log noise. Similarly, the absence of reserved DMA memory is a valid configuration and does not represent an error condition. Since these scenarios are expected and do not indicate a failure, downgrade the log level from dev_err/dev_info to dev_dbg to avoid flooding the console. No functional change intended. Link: https://lore.kernel.org/all/20260514062825.50172-1-jianping.li@oss.qualcomm.com/ Signed-off-by: Jianping Li (cherry picked from commit 2339d281d5ddc1cb6d4ed38e9a61514ffb68346a) --- drivers/misc/fastrpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 15d7622a29f02..1d39ce5f30343 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -2036,7 +2036,7 @@ static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap, kfree(dsp_attributes); return -EOPNOTSUPP; } else if (err) { - dev_err(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err); + dev_dbg(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err); kfree(dsp_attributes); return err; } @@ -2641,7 +2641,7 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) } if (of_reserved_mem_device_init_by_idx(rdev, rdev->of_node, 0)) - dev_info(rdev, "no reserved DMA memory for FASTRPC\n"); + dev_dbg(rdev, "no reserved DMA memory for FASTRPC\n"); vmcount = of_property_read_variable_u32_array(rdev->of_node, "qcom,vmids", &vmids[0], 0, FASTRPC_MAX_VMIDS); From 693823a5031369756d220fbc28c56b94ca1c695b Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:15 +0530 Subject: [PATCH 1169/1330] FROMLIST: dt-bindings: iommu: arm,smmu: Document interconnects property Some SoC implementations require a bandwidth vote on an interconnect path before the SMMU register space is accessible. Add the optional 'interconnects' property to the binding to allow platform DT nodes to describe this path. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-1-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro (cherry picked from commit 6df15543b873ccaedfcb4734c86eb43cba7d9e31) --- .../devicetree/bindings/iommu/arm,smmu.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 97f1c6498b18a..c23bc601dfc02 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -243,6 +243,13 @@ properties: minItems: 1 maxItems: 3 + interconnects: + maxItems: 1 + description: + Interconnect path to the SMMU register space. Required on SoCs + where the SMMU registers are only accessible after a bandwidth + vote has been placed on the interconnect fabric. + nvidia,memory-controller: description: | A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. @@ -604,6 +611,26 @@ allOf: clock-names: false clocks: false + - if: + properties: + compatible: + items: + - enum: + - qcom,qcs615-smmu-500 + - qcom,qcs8300-smmu-500 + - qcom,sa8775p-smmu-500 + - qcom,sc7280-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: + properties: + interconnects: + maxItems: 1 + else: + properties: + interconnects: false + - if: properties: compatible: From 2a20574dfac36c3426b2a86a8e46ed14b2f37d6b Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:02:24 +0530 Subject: [PATCH 1170/1330] FROMLIST: iommu/arm-smmu: Add interconnect bandwidth voting support On some SoCs the SMMU registers require an active interconnect bandwidth vote to be accessible. While other clients typically satisfy this requirement implicitly, certain corner cases (e.g. during sleep/wakeup transitions) can leave the SMMU without a vote, causing intermittent register access failures. Add support for an optional interconnect path to the arm-smmu driver and vote for bandwidth while the SMMU is active. The path is acquired from DT if present and ignored otherwise. The bandwidth vote is enabled before accessing SMMU registers during probe and runtime resume, and released during runtime suspend and on error paths. Generally, from an architectural perspective, GEM_NOC and DDR are expected to have an active vote whenever the adreno_smmu block is powered on. In most common use cases, this requirement is implicitly satisfied because other GPU-related clients (for example, the GMU device) already hold a GEM_NOC vote when adreno_smmu is enabled. However, there are certain corner cases, such as during sleep/wakeup transitions, where the GEM_NOC vote can be removed before adreno_smmu is powered down. If adreno_smmu is then accessed while the interconnect vote is missing, it can lead to the observed failures. Because of the precise ordering involved, this scenario is difficult to reproduce consistently. (also GDSC is involved in adreno usecases can have an independent vote) Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-2-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro (cherry picked from commit 2831e573df248b887fed74f001867f3eaa65223c) --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 57 ++++++++++++++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 + 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 83a6fac172ae9..744ff8b4d5733 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -53,6 +53,11 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +/* Interconnect bandwidth vote values for the SMMU register access path */ +#define ARM_SMMU_ICC_AVG_BW 0 +#define ARM_SMMU_ICC_PEAK_BW_HIGH 1000 +#define ARM_SMMU_ICC_PEAK_BW_LOW 0 + static int force_stage; module_param(force_stage, int, S_IRUGO); MODULE_PARM_DESC(force_stage, @@ -86,6 +91,36 @@ static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) } } +static int arm_smmu_icc_get(struct arm_smmu_device *smmu) +{ + smmu->icc_path = devm_of_icc_get(smmu->dev, NULL); + if (IS_ERR(smmu->icc_path)) { + int err = PTR_ERR(smmu->icc_path); + + if (err == -ENODEV) { + smmu->icc_path = NULL; + return 0; + } + return dev_err_probe(smmu->dev, err, + "failed to get interconnect path\n"); + } + return 0; +} + +static void arm_smmu_icc_enable(struct arm_smmu_device *smmu) +{ + if (smmu->icc_path) + WARN_ON(icc_set_bw(smmu->icc_path, ARM_SMMU_ICC_AVG_BW, + ARM_SMMU_ICC_PEAK_BW_HIGH)); +} + +static void arm_smmu_icc_disable(struct arm_smmu_device *smmu) +{ + if (smmu->icc_path) + WARN_ON(icc_set_bw(smmu->icc_path, ARM_SMMU_ICC_AVG_BW, + ARM_SMMU_ICC_PEAK_BW_LOW)); +} + static void arm_smmu_rpm_use_autosuspend(struct arm_smmu_device *smmu) { /* @@ -2212,6 +2247,17 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (err) return err; + /* + * Acquire and vote the interconnect path before accessing any SMMU + * registers (including ARM_SMMU_GR0_ID0 in arm_smmu_device_cfg_probe). + */ + err = arm_smmu_icc_get(smmu); + if (err) { + clk_bulk_disable_unprepare(smmu->num_clks, smmu->clks); + return err; + } + arm_smmu_icc_enable(smmu); + err = arm_smmu_device_cfg_probe(smmu); if (err) return err; @@ -2291,8 +2337,10 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev) if (pm_runtime_enabled(smmu->dev)) pm_runtime_force_suspend(smmu->dev); - else + else { clk_bulk_disable(smmu->num_clks, smmu->clks); + arm_smmu_icc_disable(smmu); + } clk_bulk_unprepare(smmu->num_clks, smmu->clks); } @@ -2312,9 +2360,13 @@ static int __maybe_unused arm_smmu_runtime_resume(struct device *dev) struct arm_smmu_device *smmu = dev_get_drvdata(dev); int ret; + arm_smmu_icc_enable(smmu); + ret = clk_bulk_enable(smmu->num_clks, smmu->clks); - if (ret) + if (ret) { + arm_smmu_icc_disable(smmu); return ret; + } arm_smmu_device_reset(smmu); @@ -2326,6 +2378,7 @@ static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) struct arm_smmu_device *smmu = dev_get_drvdata(dev); clk_bulk_disable(smmu->num_clks, smmu->clks); + arm_smmu_icc_disable(smmu); return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 26d2e33cd328b..c00606a416b2f 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -335,6 +336,7 @@ struct arm_smmu_device { int num_clks; unsigned int *irqs; struct clk_bulk_data *clks; + struct icc_path *icc_path; spinlock_t global_sync_lock; From 837382dd215c5125dc77e3a653c55938a8c4146c Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:17 +0530 Subject: [PATCH 1171/1330] FROMLIST: arm64: dts: qcom: kodiak: Add GEM_NOC interconnect for adreno SMMU On Kodiak platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-3-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro (cherry picked from commit abb8a3a200a280c06eead183a3a34d544b209d34) --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index b64665a86a627..f372a78ba33e4 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -3338,6 +3338,8 @@ power-domains = <&gpucc GPU_CC_CX_GDSC>; dma-coherent; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; gfx_0_tbu: tbu@3dd9000 { From d94752cbaaa327631714a24b8fc6cb33ae24ee45 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:18 +0530 Subject: [PATCH 1172/1330] FROMLIST: arm64: dts: qcom: lemans: Add GEM_NOC interconnect for adreno SMMU On Lemans platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-4-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro (cherry picked from commit 467002d35fe56d1d6063c1bb065f16ebf9d9a9d4) --- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 182b458ac4516..6369128bdd521 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4501,6 +4501,8 @@ , , ; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; serdes0: phy@8901000 { From f182bd53ebc1a53a38be1a7189d4fa260dab5fa4 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:20 +0530 Subject: [PATCH 1173/1330] FROMLIST: arm64: dts: qcom: talos: Add GEM_NOC interconnect for adreno SMMU On Talos platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-6-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro (cherry picked from commit 277da5daa2951397d4addf7a04b640696367d68c) --- arch/arm64/boot/dts/qcom/talos.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 0592ea8dff9b6..5d4d66d764505 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -2096,6 +2096,8 @@ "iface"; power-domains = <&gpucc CX_GDSC>; dma-coherent; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; stm@6002000 { From 8c31045d9e1e03295b9bf54370f3995260ffd345 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 26 May 2026 20:05:19 +0530 Subject: [PATCH 1174/1330] FROMLIST: arm64: dts: qcom: monaco: Add GEM_NOC interconnect for adreno SMMU On Monaco platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-5-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro (cherry picked from commit 98236fed0fc02e5496c567ee154ba699336ea681) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index eb3818d733110..daf2444370fbf 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5167,6 +5167,8 @@ "gpu_cc_hub_aon_clk"; power-domains = <&gpucc GPU_CC_CX_GDSC>; dma-coherent; + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; pmu@9091000 { From 6a199d6dfc8cf417bac0a97e9e198982b510cdfe Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Thu, 16 Jul 2026 21:55:53 +0200 Subject: [PATCH 1175/1330] Ubuntu: [Config] synchronize config after rebase Signed-off-by: Kuba Pawlak --- debian.qcom/config/annotations | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index a639b51de92b5..2faca6451afe3 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -124,8 +124,10 @@ CONFIG_TOUCHSCREEN_APPLE_Z2 note<'TODO: update note'> # ---- Annotations without notes ---- CONFIG_AC97_BUS policy<{'arm64': 'y'}> +CONFIG_ACPI_AEST policy<{'arm64': 'n'}> CONFIG_ADI_AXI_ADC policy<{'arm64': '-'}> CONFIG_ADI_AXI_DAC policy<{'arm64': '-'}> +CONFIG_AEST policy<{'arm64': 'y'}> CONFIG_AHCI_IMX policy<{'arm64': '-'}> CONFIG_AHCI_MTK policy<{'arm64': '-'}> CONFIG_AHCI_MVEBU policy<{'arm64': '-'}> @@ -329,6 +331,7 @@ CONFIG_CLK_ELIZA_DISPCC policy<{'arm64-qcom': 'y', 'arm6 CONFIG_CLK_ELIZA_GCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_ELIZA_TCSRCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_GLYMUR_CAMCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> +CONFIG_CLK_GLYMUR_EVACC policy<{'arm64': 'm'}> CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_GPUCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_VIDEOCC policy<{'arm64': 'y'}> @@ -397,6 +400,7 @@ CONFIG_CLK_RK3588 policy<{'arm64': '-'}> CONFIG_CLK_RV1126B policy<{'arm64': '-'}> CONFIG_CLK_RZG2L policy<{'arm64': '-'}> CONFIG_CLK_RZV2H policy<{'arm64': '-'}> +CONFIG_CLK_SHIKRA_AUDIOCORECC policy<{'arm64': 'y'}> CONFIG_CLK_SHIKRA_DISPCC policy<{'arm64': 'm'}> CONFIG_CLK_SHIKRA_GCC policy<{'arm64': 'y'}> CONFIG_CLK_SHIKRA_GPUCC policy<{'arm64': 'm'}> @@ -754,6 +758,7 @@ CONFIG_DRM_INNO_HDMI policy<{'arm64': '-'}> CONFIG_DRM_KMB_DISPLAY policy<{'arm64': '-'}> CONFIG_DRM_LOGICVC policy<{'arm64': 'n'}> CONFIG_DRM_LONTIUM_LT8713SX policy<{'arm64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611C policy<{'arm64': 'm'}> CONFIG_DRM_MEDIATEK policy<{'arm64': '-'}> CONFIG_DRM_MEDIATEK_DP policy<{'arm64': '-'}> CONFIG_DRM_MEDIATEK_HDMI policy<{'arm64': '-'}> @@ -1379,6 +1384,7 @@ CONFIG_NVMEM_ZYNQMP policy<{'arm64': '-'}> CONFIG_NVME_APPLE policy<{'arm64': '-'}> CONFIG_NXP_SAR_ADC policy<{'arm64': '-'}> CONFIG_NXP_STM_TIMER policy<{'arm64': '-'}> +CONFIG_OF_AEST policy<{'arm64': 'y'}> CONFIG_OLPC_EC policy<{'arm64': '-'}> CONFIG_OLPC_XO175 policy<{'arm64': '-'}> CONFIG_OLPC_XO175_EC policy<{'arm64': '-'}> @@ -1793,6 +1799,7 @@ CONFIG_QCOM_APR policy<{'arm64': 'y'}> CONFIG_QCOM_BAM_DMA policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_APCC_MSM8996 policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_APCS_MSM8916 policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_GP_MND policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_SMD_RPM policy<{'arm64': 'y'}> CONFIG_QCOM_CPR policy<{'arm64': 'y'}> CONFIG_QCOM_CPUCP_MBOX policy<{'arm64': 'y'}> @@ -1841,6 +1848,7 @@ CONFIG_QCOM_SMP2P policy<{'arm64': 'y'}> CONFIG_QCOM_SMP2P_SLEEPSTATE policy<{'arm64': '-'}> CONFIG_QCOM_SMSM policy<{'arm64': 'y'}> CONFIG_QCOM_SOC_DEBUG policy<{'arm64': '-'}> +CONFIG_QCOM_SPEL policy<{'arm64': 'y'}> CONFIG_QCOM_SPMI_ADC5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_ADC_TM5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_MBG_TM policy<{'arm64': '-'}> @@ -1989,6 +1997,7 @@ CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> CONFIG_RTSN policy<{'arm64': '-'}> +CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11)"'}> CONFIG_RZG2L_ADC policy<{'arm64': '-'}> CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> From a2c5b6f3ad962670ee600a80f351541f1f9fa451 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Thu, 16 Jul 2026 22:22:19 +0200 Subject: [PATCH 1176/1330] UBUNTU: SAUCE: arm64: dts: qcom: glymur: Drop duplicate gpu/gmu nodes The July qcom-next-7.1-rc6 rebase brought in the upstream FROMLIST GPU commits for Glymur ("Add GPU smmu node", "Add GPU support for Glymur", "Add GPU cooling"), which add a gpu@3d00000 node plus gxclkctl and gmu@3d6c000. However our tree already carried an older GPU subsystem block (gpu@3d00000 + gmu@3d6a000) that had been added during the June 7.1-rc2 rebase as a graduated-upstream build fix. The cherry-picks did not remove that older block, leaving two gpu@3d00000 nodes and producing: glymur.dtsi: ERROR (duplicate_node_names): /soc@0/gpu@3d00000: Duplicate node name Remove the stale older block (the second gpu@3d00000 and the gmu@3d6a000 node). The remaining gpu/gxclkctl/gmu@3d6c000 nodes now match the qcom-next tip exactly. Signed-off-by: kuba.pawlak@canonical.com Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/glymur.dtsi | 180 --------------------------- 1 file changed, 180 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 0f8bb20fbcbf7..28822619906a9 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4314,186 +4314,6 @@ }; }; - gpu: gpu@3d00000 { - compatible = "qcom,adreno-44070001", "qcom,adreno"; - reg = <0x0 0x03d00000 0x0 0x40000>, - <0x0 0x03d9e000 0x0 0x2000>, - <0x0 0x03d61000 0x0 0x800>; - reg-names = "kgsl_3d0_reg_memory", - "cx_mem", - "cx_dbgc"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x0>, - <&adreno_smmu 1 0x0>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - #cooling-cells = <2>; - - interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "gfx-mem"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2-adreno", - "operating-points-v2"; - - opp-310000000 { - opp-hz = /bits/ 64 <310000000>; - opp-level = ; - opp-peak-kBps = <2136719>; - opp-supported-hw = <0xf>; - }; - - opp-410000000 { - opp-hz = /bits/ 64 <410000000>; - opp-level = ; - opp-peak-kBps = <6074219>; - opp-supported-hw = <0xf>; - }; - - opp-572000000 { - opp-hz = /bits/ 64 <572000000>; - opp-level = ; - opp-peak-kBps = <12449219>; - qcom,opp-acd-level = <0xe02d5ffd>; - opp-supported-hw = <0xf>; - }; - - opp-760000000 { - opp-hz = /bits/ 64 <760000000>; - opp-level = ; - opp-peak-kBps = <12449219>; - qcom,opp-acd-level = <0xc0285ffd>; - opp-supported-hw = <0xf>; - }; - - opp-820000000 { - opp-hz = /bits/ 64 <820000000>; - opp-level = ; - opp-peak-kBps = <16500000>; - qcom,opp-acd-level = <0xa82e5ffd>; - opp-supported-hw = <0xf>; - }; - - opp-915000000 { - opp-hz = /bits/ 64 <915000000>; - opp-level = ; - opp-peak-kBps = <16500000>; - qcom,opp-acd-level = <0x882d5ffd>; - opp-supported-hw = <0xf>; - }; - - opp-1070000000 { - opp-hz = /bits/ 64 <1070000000>; - opp-level = ; - opp-peak-kBps = <16500000>; - qcom,opp-acd-level = <0x882b5ffd>; - opp-supported-hw = <0xf>; - }; - - opp-1185000000 { - opp-hz = /bits/ 64 <1185000000>; - opp-level = ; - opp-peak-kBps = <16500000>; - qcom,opp-acd-level = <0x882a5ffd>; - opp-supported-hw = <0xf>; - }; - - opp-1350000000 { - opp-hz = /bits/ 64 <1350000000>; - opp-level = ; - opp-peak-kBps = <18597657>; - qcom,opp-acd-level = <0x882a5ffd>; - opp-supported-hw = <0xf>; - }; - - opp-1550000000 { - opp-hz = /bits/ 64 <1550000000>; - opp-level = ; - opp-peak-kBps = <18597657>; - qcom,opp-acd-level = <0xa8295ffd>; - opp-supported-hw = <0x7>; - }; - - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-level = ; - opp-peak-kBps = <18597657>; - qcom,opp-acd-level = <0x88295ffd>; - opp-supported-hw = <0x7>; - }; - - opp-1850000000 { - opp-hz = /bits/ 64 <1850000000>; - opp-level = ; - opp-peak-kBps = <18597657>; - qcom,opp-acd-level = <0x88285ffd>; - opp-supported-hw = <0x3>; - }; - }; - }; - - gmu: gmu@3d6a000 { - compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"; - - reg = <0x0 0x03d37000 0x0 0x68000>; - reg-names = "gmu"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_GPU_GEMNOC_GFX_CLK>, - <&gpucc GPU_CC_HUB_CX_INT_CLK>; - clock-names = "ahb", - "gmu", - "cxo", - "memnoc", - "hub"; - - power-domains = <&gpucc GPU_CC_CX_GDSC>, <&gpucc GPU_CC_CX_GDSC>; - //<&gxclkctl GX_CLKCTL_GX_GDSC>; TODO: - power-domain-names = "cx", - "gx"; - - iommus = <&adreno_smmu 5 0x0>; - - qcom,qmp = <&aoss_qmp>; - - operating-points-v2 = <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-575000000 { - opp-hz = /bits/ 64 <575000000>; - opp-level = ; - }; - - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-level = ; - }; - - opp-725000000 { - opp-hz = /bits/ 64 <725000000>; - opp-level = ; - }; - - opp-750000000 { - opp-hz = /bits/ 64 <750000000>; - opp-level = ; - }; - }; - }; - gpucc: clock-controller@3d90000 { compatible = "qcom,glymur-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; From 0cd8a53515d4fd1af0d28be9ecce55f236eef068 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Thu, 16 Jul 2026 22:55:21 +0200 Subject: [PATCH 1177/1330] UBUNTU: SAUCE: arm64: dts: qcom: purwa-iot-evk: adapt TSENS override to inline thermal model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The July qcom-next-7.1-rc6 rebase pulled in "FROMLIST: arm64: dts: qcom: purwa-iot-evk: Update TSENS thermal zone" (54106c85f5fa), which raises the GPUSS passive trip points to 105C for the IoT package. It does so by overriding &thermal_gpuss_0..3 — labels that only exist in the upstream label-based thermal model (defined in hamoa.dtsi in qcom-next). Our tree still carries the older inline thermal-zones model for purwa (purwa.dtsi redefines thermal-zones with node names gpuss-0-thermal .. gpuss-3-thermal), where those zone labels do not exist. This caused: purwa-iot-evk.dts: Label or path thermal_gpuss_0 not found FATAL ERROR: Syntax error parsing input tree Adapt the override to our model: our inline zones already label the passive trip points (gpuss0_alert0 .. gpuss3_alert0), so target those directly to apply the same 105C passive threshold. Functionally equivalent to the upstream change. Signed-off-by: kuba.pawlak@canonical.com Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 32 ++++++---------------- 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index 2f55f27196f31..85b9175c54541 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -1345,36 +1345,20 @@ }; }; -&thermal_gpuss_0 { - trips { - trip-point0 { - temperature = <105000>; - }; - }; +&gpuss0_alert0 { + temperature = <105000>; }; -&thermal_gpuss_1 { - trips { - trip-point0 { - temperature = <105000>; - }; - }; +&gpuss1_alert0 { + temperature = <105000>; }; -&thermal_gpuss_2 { - trips { - trip-point0 { - temperature = <105000>; - }; - }; +&gpuss2_alert0 { + temperature = <105000>; }; -&thermal_gpuss_3 { - trips { - trip-point0 { - temperature = <105000>; - }; - }; +&gpuss3_alert0 { + temperature = <105000>; }; &tlmm { From f78280b32deda607ba25bcaf8fd259f9cb0387be Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Thu, 16 Jul 2026 23:29:58 +0200 Subject: [PATCH 1178/1330] UBUNTU: SAUCE: pinctrl: qcom: shikra: fix PINGROUP macro/table mismatch The July qcom-next-7.1-rc6 rebase applied "pinctrl: qcom: shikra: align with upstream post-submission review" via an auto (take-theirs) conflict resolution, which left drivers/pinctrl/qcom/pinctrl-shikra.c as a garbled hybrid: the old 14-argument PINGROUP macro definition (id, f1..f11, wake_off, bit) combined with the new 12-argument pin table entries (id, f1..f11). This broke the build: pinctrl-shikra.c: error: macro 'PINGROUP' requires 14 arguments, but only 12 given The Shikra pinctrl driver carries no Ubuntu-specific content, so replace the file wholesale with the qcom-next tip version, which is internally consistent (12-argument PINGROUP macro and matching table). Signed-off-by: kuba.pawlak@canonical.com Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/pinctrl/qcom/pinctrl-shikra.c | 806 +++++++------------------- 1 file changed, 203 insertions(+), 603 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c index ed0bff4a1202b..0fc98369948cb 100644 --- a/drivers/pinctrl/qcom/pinctrl-shikra.c +++ b/drivers/pinctrl/qcom/pinctrl-shikra.c @@ -10,7 +10,7 @@ #include "pinctrl-msm.h" #define REG_SIZE 0x1000 -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, wake_off, bit) \ +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ { \ .grp = PINCTRL_PINGROUP("gpio" #id, \ gpio##id##_pins, \ @@ -436,73 +436,38 @@ enum shikra_functions { msm_mux_atest_char, msm_mux_atest_gpsadc, msm_mux_atest_tsens, - msm_mux_atest_tsens2, msm_mux_atest_usb, msm_mux_cam_mclk, - msm_mux_cci_async_in0, - msm_mux_cci_i2c_scl0, - msm_mux_cci_i2c_scl1, - msm_mux_cci_i2c_sda0, - msm_mux_cci_i2c_sda1, + msm_mux_cci_async, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, msm_mux_cci_timer, - msm_mux_char_exec_pending, - msm_mux_char_exec_release, + msm_mux_char_exec, msm_mux_cri_trng, - msm_mux_cri_trng0, - msm_mux_cri_trng1, msm_mux_dac_calib, msm_mux_dbg_out_clk, - msm_mux_ddr_bist_complete, - msm_mux_ddr_bist_fail, - msm_mux_ddr_bist_start, - msm_mux_ddr_bist_stop, - msm_mux_ddr_pxi0, - msm_mux_ddr_pxi1, - msm_mux_dmic0_clk, - msm_mux_dmic0_data, - msm_mux_dmic1_clk, - msm_mux_dmic1_data, - msm_mux_emac0_dll, - msm_mux_emac0_mcg0, - msm_mux_emac0_mcg1, - msm_mux_emac0_mcg2, - msm_mux_emac0_mcg3, - msm_mux_emac0_phy, - msm_mux_emac0_ptp, - msm_mux_emac1_dll, - msm_mux_emac1_mcg0, - msm_mux_emac1_mcg1, - msm_mux_emac1_mcg2, - msm_mux_emac1_mcg3, - msm_mux_emac1_phy, - msm_mux_emac1_ptp, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_dmic, + msm_mux_emac_dll, + msm_mux_emac_mcg, + msm_mux_emac_phy, + msm_mux_emac0_ptp_aux, + msm_mux_emac0_ptp_pps, + msm_mux_emac1_ptp_aux, + msm_mux_emac1_ptp_pps, msm_mux_ext_mclk, - msm_mux_gcc_gp1, - msm_mux_gcc_gp2, - msm_mux_gcc_gp3, + msm_mux_gcc_gp, msm_mux_gsm0_tx, - msm_mux_i2s0_clk, - msm_mux_i2s0_data0, - msm_mux_i2s0_data1, - msm_mux_i2s0_data2, - msm_mux_i2s0_data3, - msm_mux_i2s0_ws, - msm_mux_i2s1_clk, - msm_mux_i2s1_data0, - msm_mux_i2s1_data1, - msm_mux_i2s1_ws, - msm_mux_i2s2_clk, - msm_mux_i2s2_data0, - msm_mux_i2s2_data1, - msm_mux_i2s2_ws, - msm_mux_i2s3_clk, - msm_mux_i2s3_data0, - msm_mux_i2s3_data1, - msm_mux_i2s3_ws, + msm_mux_i2s0, + msm_mux_i2s1, + msm_mux_i2s2, + msm_mux_i2s3, msm_mux_jitter_bist, msm_mux_m_voc, - msm_mux_mdp_vsync, msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_out0, + msm_mux_mdp_vsync_out1, msm_mux_mdp_vsync_p, msm_mux_mdp_vsync_s, msm_mux_mpm_pwr, @@ -513,93 +478,45 @@ enum shikra_functions { msm_mux_pbs_out, msm_mux_pcie0_clk_req_n, msm_mux_phase_flag, - msm_mux_pll_bist, - msm_mux_pll_bypassnl, - msm_mux_pll_clk, - msm_mux_pll_reset_n, + msm_mux_pll, msm_mux_prng_rosc, - msm_mux_pwm_0, - msm_mux_pwm_1, - msm_mux_pwm_2, - msm_mux_pwm_3, - msm_mux_pwm_4, - msm_mux_pwm_5, - msm_mux_pwm_6, - msm_mux_pwm_7, - msm_mux_pwm_8, - msm_mux_pwm_9, + msm_mux_pwm, msm_mux_qdss_cti, msm_mux_qup0_se0, msm_mux_qup0_se1, + msm_mux_qup0_se1_01, + msm_mux_qup0_se1_23, msm_mux_qup0_se2, - msm_mux_qup0_se3, - msm_mux_qup0_se4, + msm_mux_qup0_se3_01, + msm_mux_qup0_se3_23, + msm_mux_qup0_se4_01, + msm_mux_qup0_se4_23, msm_mux_qup0_se5, msm_mux_qup0_se6, - msm_mux_qup0_se7, + msm_mux_qup0_se7_01, + msm_mux_qup0_se7_23, msm_mux_qup0_se8, msm_mux_qup0_se9, - msm_mux_rgmii0_mdc, - msm_mux_rgmii0_mdio, - msm_mux_rgmii0_rx_ctl, - msm_mux_rgmii0_rxc, - msm_mux_rgmii0_rxd0, - msm_mux_rgmii0_rxd1, - msm_mux_rgmii0_rxd2, - msm_mux_rgmii0_rxd3, - msm_mux_rgmii0_tx_ctl, - msm_mux_rgmii0_txc, - msm_mux_rgmii0_txd0, - msm_mux_rgmii0_txd1, - msm_mux_rgmii0_txd2, - msm_mux_rgmii0_txd3, - msm_mux_rgmii1_mdc, - msm_mux_rgmii1_mdio, - msm_mux_rgmii1_rx_ctl, - msm_mux_rgmii1_rxc, - msm_mux_rgmii1_rxd0, - msm_mux_rgmii1_rxd1, - msm_mux_rgmii1_rxd2, - msm_mux_rgmii1_rxd3, - msm_mux_rgmii1_tx_ctl, - msm_mux_rgmii1_txc, - msm_mux_rgmii1_txd0, - msm_mux_rgmii1_txd1, - msm_mux_rgmii1_txd2, - msm_mux_rgmii1_txd3, + msm_mux_qup0_se9_01, + msm_mux_qup0_se9_23, + msm_mux_rgmii, msm_mux_sd_write_protect, - msm_mux_sdc1_tb_trig, - msm_mux_sdc2_tb_trig, - msm_mux_ssbi_wtr0, - msm_mux_ssbi_wtr1, - msm_mux_ssbi_wtr2, - msm_mux_ssbi_wtr3, - msm_mux_swr0_rx_clk, - msm_mux_swr0_rx_data0, - msm_mux_swr0_rx_data1, - msm_mux_swr0_tx_clk, - msm_mux_swr0_tx_data0, - msm_mux_tgu_ch0_trigout, - msm_mux_tgu_ch1_trigout, - msm_mux_tgu_ch2_trigout, - msm_mux_tgu_ch3_trigout, + msm_mux_sdc_cdc, + msm_mux_sdc_tb_trig, + msm_mux_ssbi_wtr, + msm_mux_swr0_rx, + msm_mux_swr0_tx, + msm_mux_tgu_ch_trigout, msm_mux_tsc_async, msm_mux_tsense_pwm, - msm_mux_uim1_clk, - msm_mux_uim1_data, - msm_mux_uim1_present, - msm_mux_uim1_reset, - msm_mux_uim2_clk, - msm_mux_uim2_data, - msm_mux_uim2_present, - msm_mux_uim2_reset, + msm_mux_uim1, + msm_mux_uim2, msm_mux_unused_adsp, msm_mux_unused_gsm1, msm_mux_usb0_phy_ps, - msm_mux_vfr_1, + msm_mux_vfr, msm_mux_vsense_trigger_mirnat, - msm_mux_wlan1_adc0, - msm_mux_wlan1_adc1, + msm_mux_wlan, msm_mux__, }; @@ -651,64 +568,40 @@ static const char *const atest_gpsadc_groups[] = { }; static const char *const atest_tsens_groups[] = { - "gpio1", -}; - -static const char *const atest_tsens2_groups[] = { - "gpio2", + "gpio1", "gpio2", }; static const char *const atest_usb_groups[] = { - "gpio96", "gpio98", "gpio99", "gpio100", "gpio101", - "gpio60", "gpio61", "gpio53", "gpio58", "gpio59", + "gpio53", "gpio58", "gpio59", "gpio60", "gpio61", "gpio96", + "gpio98", "gpio99", "gpio100", "gpio101", }; static const char *const cam_mclk_groups[] = { "gpio34", "gpio35", "gpio96", "gpio98", }; -static const char *const cci_async_in0_groups[] = { +static const char *const cci_async_groups[] = { "gpio39", }; -static const char *const cci_i2c_scl0_groups[] = { - "gpio37", -}; - -static const char *const cci_i2c_scl1_groups[] = { - "gpio42", +static const char *const cci_i2c0_groups[] = { + "gpio36", "gpio37", }; -static const char *const cci_i2c_sda0_groups[] = { - "gpio36", -}; - -static const char *const cci_i2c_sda1_groups[] = { - "gpio41", +static const char *const cci_i2c1_groups[] = { + "gpio41", "gpio42", }; static const char *const cci_timer_groups[] = { - "gpio38", "gpio47", "gpio40", "gpio43", + "gpio38", "gpio40", "gpio43", "gpio47", }; -static const char *const char_exec_pending_groups[] = { - "gpio13", -}; - -static const char *const char_exec_release_groups[] = { - "gpio12", +static const char *const char_exec_groups[] = { + "gpio12", "gpio13", }; static const char *const cri_trng_groups[] = { - "gpio20", -}; - -static const char *const cri_trng0_groups[] = { - "gpio6", -}; - -static const char *const cri_trng1_groups[] = { - "gpio7", + "gpio6", "gpio7", "gpio20", }; static const char *const dac_calib_groups[] = { @@ -723,99 +616,44 @@ static const char *const dbg_out_clk_groups[] = { "gpio61", }; -static const char *const ddr_bist_complete_groups[] = { - "gpio4", -}; - -static const char *const ddr_bist_fail_groups[] = { - "gpio1", -}; - -static const char *const ddr_bist_start_groups[] = { - "gpio2", -}; - -static const char *const ddr_bist_stop_groups[] = { - "gpio3", -}; - -static const char *const ddr_pxi0_groups[] = { - "gpio98", "gpio99", -}; - -static const char *const ddr_pxi1_groups[] = { - "gpio100", "gpio101", +static const char *const ddr_bist_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4", }; -static const char *const dmic0_clk_groups[] = { - "gpio96", +static const char *const ddr_pxi_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", }; -static const char *const dmic0_data_groups[] = { - "gpio97", +static const char *const dmic_groups[] = { + "gpio96", "gpio97", "gpio98", "gpio99", }; -static const char *const dmic1_clk_groups[] = { - "gpio98", +static const char *const emac_dll_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", }; -static const char *const dmic1_data_groups[] = { - "gpio99", +static const char *const emac_mcg_groups[] = { + "gpio28", "gpio29", "gpio40", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", }; -static const char *const emac0_dll_groups[] = { - "gpio60", "gpio61", +static const char *const emac_phy_groups[] = { + "gpio120", "gpio136", }; -static const char *const emac0_mcg0_groups[] = { - "gpio46", -}; - -static const char *const emac0_mcg1_groups[] = { - "gpio45", -}; - -static const char *const emac0_mcg2_groups[] = { - "gpio44", -}; - -static const char *const emac0_mcg3_groups[] = { - "gpio43", -}; - -static const char *const emac0_phy_groups[] = { - "gpio120", -}; - -static const char *const emac0_ptp_groups[] = { +static const char *const emac0_ptp_aux_groups[] = { "gpio60", "gpio63", "gpio69", "gpio85", }; -static const char *const emac1_dll_groups[] = { - "gpio58", "gpio59", -}; - -static const char *const emac1_mcg0_groups[] = { - "gpio29", -}; - -static const char *const emac1_mcg1_groups[] = { - "gpio28", -}; - -static const char *const emac1_mcg2_groups[] = { - "gpio40", -}; - -static const char *const emac1_mcg3_groups[] = { - "gpio47", +static const char *const emac0_ptp_pps_groups[] = { + "gpio60", "gpio63", "gpio69", "gpio85", }; -static const char *const emac1_phy_groups[] = { - "gpio136", +static const char *const emac1_ptp_aux_groups[] = { + "gpio31", "gpio33", "gpio60", "gpio68", }; -static const char *const emac1_ptp_groups[] = { +static const char *const emac1_ptp_pps_groups[] = { "gpio31", "gpio33", "gpio60", "gpio68", }; @@ -823,92 +661,28 @@ static const char *const ext_mclk_groups[] = { "gpio103", "gpio104", "gpio110", "gpio114", }; -static const char *const gcc_gp1_groups[] = { - "gpio45", "gpio110", -}; - -static const char *const gcc_gp2_groups[] = { - "gpio61", "gpio88", -}; - -static const char *const gcc_gp3_groups[] = { - "gpio53", "gpio89", +static const char *const gcc_gp_groups[] = { + "gpio45", "gpio53", "gpio61", "gpio88", "gpio89", "gpio110", }; static const char *const gsm0_tx_groups[] = { "gpio75", }; -static const char *const i2s0_clk_groups[] = { - "gpio105", -}; - -static const char *const i2s0_data0_groups[] = { - "gpio107", -}; - -static const char *const i2s0_data1_groups[] = { - "gpio108", -}; - -static const char *const i2s0_data2_groups[] = { - "gpio109", -}; - -static const char *const i2s0_data3_groups[] = { - "gpio110", -}; - -static const char *const i2s0_ws_groups[] = { - "gpio106", -}; - -static const char *const i2s1_clk_groups[] = { - "gpio96", -}; - -static const char *const i2s1_data0_groups[] = { - "gpio98", -}; - -static const char *const i2s1_data1_groups[] = { - "gpio99", -}; - -static const char *const i2s1_ws_groups[] = { - "gpio97", -}; - -static const char *const i2s2_clk_groups[] = { - "gpio100", -}; - -static const char *const i2s2_data0_groups[] = { - "gpio102", -}; - -static const char *const i2s2_data1_groups[] = { - "gpio103", -}; - -static const char *const i2s2_ws_groups[] = { - "gpio101", +static const char *const i2s0_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", }; -static const char *const i2s3_clk_groups[] = { - "gpio111", +static const char *const i2s1_groups[] = { + "gpio96", "gpio97", "gpio98", "gpio99", }; -static const char *const i2s3_data0_groups[] = { - "gpio113", +static const char *const i2s2_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", }; -static const char *const i2s3_data1_groups[] = { - "gpio114", -}; - -static const char *const i2s3_ws_groups[] = { - "gpio112", +static const char *const i2s3_groups[] = { + "gpio111", "gpio112", "gpio113", "gpio114", }; static const char *const jitter_bist_groups[] = { @@ -919,12 +693,16 @@ static const char *const m_voc_groups[] = { "gpio0", }; -static const char *const mdp_vsync_groups[] = { +static const char *const mdp_vsync_e_groups[] = { + "gpio94", +}; + +static const char *const mdp_vsync_out0_groups[] = { "gpio86", }; -static const char *const mdp_vsync_e_groups[] = { - "gpio94", +static const char *const mdp_vsync_out1_groups[] = { + "gpio86", }; static const char *const mdp_vsync_p_groups[] = { @@ -944,7 +722,7 @@ static const char *const mss_lte_groups[] = { }; static const char *const nav_gpio_groups[] = { - "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92", + "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92", "gpio95", "gpio100", "gpio101", "gpio104", }; @@ -953,14 +731,13 @@ static const char *const pa_indicator_or_groups[] = { }; static const char *const pbs_in_groups[] = { - "gpio49", "gpio50", "gpio59", "gpio60", "gpio61", - "gpio62", "gpio63", "gpio51", "gpio48", "gpio74", - "gpio74", "gpio54", "gpio55", "gpio56", "gpio57", - "gpio58", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio53", "gpio54", + "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", + "gpio61", "gpio62", "gpio63", "gpio74", }; static const char *const pbs_out_groups[] = { - "gpio24", "gpio22", "gpio23", + "gpio22", "gpio23", "gpio24", }; static const char *const pcie0_clk_req_n_groups[] = { @@ -968,97 +745,66 @@ static const char *const pcie0_clk_req_n_groups[] = { }; static const char *const phase_flag_groups[] = { - "gpio1", "gpio2", "gpio56", "gpio11", "gpio62", - "gpio63", "gpio63", "gpio69", "gpio70", "gpio71", - "gpio72", "gpio74", "gpio3", "gpio57", "gpio31", - "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", - "gpio9", "gpio29", "gpio29", "gpio54", "gpio16", - "gpio17", "gpio102", "gpio55", "gpio0", "gpio48", - "gpio49", "gpio50", + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio11", "gpio16", + "gpio17", "gpio28", "gpio29", "gpio30", "gpio31", "gpio48", + "gpio49", "gpio50", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio62", "gpio63", "gpio64", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio74", "gpio102", }; -static const char *const pll_bist_groups[] = { - "gpio43", "gpio44", -}; - -static const char *const pll_bypassnl_groups[] = { - "gpio76", -}; - -static const char *const pll_clk_groups[] = { - "gpio14", "gpio22", -}; - -static const char *const pll_reset_n_groups[] = { - "gpio74", +static const char *const pll_groups[] = { + "gpio14", "gpio22", "gpio43", "gpio44", "gpio74", "gpio76", }; static const char *const prng_rosc_groups[] = { "gpio27", "gpio28", }; -static const char *const pwm_0_groups[] = { - "gpio32", "gpio55", -}; - -static const char *const pwm_1_groups[] = { - "gpio40", "gpio54", -}; - -static const char *const pwm_2_groups[] = { - "gpio62", "gpio57", -}; - -static const char *const pwm_3_groups[] = { - "gpio77", -}; - -static const char *const pwm_4_groups[] = { - "gpio79", +static const char *const pwm_groups[] = { + "gpio32", "gpio40", "gpio45", "gpio53", "gpio54", "gpio55", + "gpio56", "gpio57", "gpio58", "gpio61", "gpio62", "gpio68", + "gpio77", "gpio79", "gpio80", "gpio87", "gpio102" }; -static const char *const pwm_5_groups[] = { - "gpio80", -}; - -static const char *const pwm_6_groups[] = { - "gpio87", "gpio56", +static const char *const qdss_cti_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95", }; -static const char *const pwm_7_groups[] = { - "gpio45", "gpio53", +static const char *const qup0_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", }; -static const char *const pwm_8_groups[] = { - "gpio102", "gpio58", +static const char *const qup0_se1_groups[] = { + "gpio28", "gpio29", }; -static const char *const pwm_9_groups[] = { - "gpio61", "gpio68", +static const char *const qup0_se1_01_groups[] = { + "gpio4", "gpio5", }; -static const char *const qdss_cti_groups[] = { - "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95", +static const char *const qup0_se1_23_groups[] = { + "gpio4", "gpio5", }; -static const char *const qup0_se0_groups[] = { - "gpio2", "gpio3", "gpio0", "gpio1", +static const char *const qup0_se2_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31", }; -static const char *const qup0_se1_groups[] = { - "gpio5", "gpio4", "gpio4", "gpio28", "gpio5", "gpio29", +static const char *const qup0_se3_01_groups[] = { + "gpio10", "gpio11", }; -static const char *const qup0_se2_groups[] = { - "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31", +static const char *const qup0_se3_23_groups[] = { + "gpio10", "gpio11", }; -static const char *const qup0_se3_groups[] = { - "gpio10", "gpio11", "gpio11", "gpio10", +static const char *const qup0_se4_01_groups[] = { + "gpio12", "gpio13", }; -static const char *const qup0_se4_groups[] = { - "gpio12", "gpio13", "gpio13", "gpio12", +static const char *const qup0_se4_23_groups[] = { + "gpio12", "gpio13", }; static const char *const qup0_se5_groups[] = { @@ -1066,12 +812,15 @@ static const char *const qup0_se5_groups[] = { }; static const char *const qup0_se6_groups[] = { - "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", - "gpio31", + "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", "gpio31", }; -static const char *const qup0_se7_groups[] = { - "gpio20", "gpio21", "gpio21", "gpio20", +static const char *const qup0_se7_01_groups[] = { + "gpio20", "gpio21", +}; + +static const char *const qup0_se7_23_groups[] = { + "gpio20", "gpio21", }; static const char *const qup0_se8_groups[] = { @@ -1079,16 +828,15 @@ static const char *const qup0_se8_groups[] = { }; static const char *const qup0_se9_groups[] = { - "gpio27", "gpio48", "gpio26", "gpio49", "gpio26", - "gpio50", "gpio27", "gpio51", + "gpio48", "gpio49", "gpio50", "gpio51", }; -static const char *const rgmii0_mdc_groups[] = { - "gpio134", +static const char *const qup0_se9_01_groups[] = { + "gpio26", "gpio27", }; -static const char *const rgmii0_mdio_groups[] = { - "gpio133", +static const char *const qup0_se9_23_groups[] = { + "gpio26", "gpio27", }; static const char *const rgmii_groups[] = { @@ -1103,64 +851,28 @@ static const char *const sd_write_protect_groups[] = { "gpio109", }; -static const char *const sdc1_tb_trig_groups[] = { - "gpio33", +static const char *const sdc_cdc_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", }; -static const char *const sdc2_tb_trig_groups[] = { - "gpio32", +static const char *const sdc_tb_trig_groups[] = { + "gpio32", "gpio33", }; static const char *const ssbi_wtr_groups[] = { "gpio68", "gpio69", "gpio70", "gpio71", }; -static const char *const ssbi_wtr1_groups[] = { - "gpio71", -}; - -static const char *const ssbi_wtr2_groups[] = { - "gpio68", -}; - -static const char *const ssbi_wtr3_groups[] = { - "gpio69", -}; - -static const char *const swr0_rx_clk_groups[] = { - "gpio107", -}; - -static const char *const swr0_rx_data0_groups[] = { - "gpio108", -}; - -static const char *const swr0_rx_data1_groups[] = { - "gpio109", -}; - -static const char *const swr0_tx_clk_groups[] = { - "gpio105", -}; - -static const char *const swr0_tx_data0_groups[] = { - "gpio106", -}; - -static const char *const tgu_ch0_trigout_groups[] = { - "gpio14", +static const char *const swr0_rx_groups[] = { + "gpio107", "gpio108", "gpio109", }; -static const char *const tgu_ch1_trigout_groups[] = { - "gpio15", +static const char *const swr0_tx_groups[] = { + "gpio105", "gpio106", }; -static const char *const tgu_ch2_trigout_groups[] = { - "gpio16", -}; - -static const char *const tgu_ch3_trigout_groups[] = { - "gpio17", +static const char *const tgu_ch_trigout_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", }; static const char *const tsc_async_groups[] = { @@ -1171,36 +883,12 @@ static const char *const tsense_pwm_groups[] = { "gpio21", }; -static const char *const uim1_clk_groups[] = { - "gpio82", -}; - -static const char *const uim1_data_groups[] = { - "gpio81", -}; - -static const char *const uim1_present_groups[] = { - "gpio84", -}; - -static const char *const uim1_reset_groups[] = { - "gpio83", +static const char *const uim1_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", }; -static const char *const uim2_clk_groups[] = { - "gpio78", -}; - -static const char *const uim2_data_groups[] = { - "gpio77", -}; - -static const char *const uim2_present_groups[] = { - "gpio80", -}; - -static const char *const uim2_reset_groups[] = { - "gpio79", +static const char *const uim2_groups[] = { + "gpio77", "gpio78", "gpio79", "gpio80", }; static const char *const unused_adsp_groups[] = { @@ -1215,7 +903,7 @@ static const char *const usb0_phy_ps_groups[] = { "gpio90", }; -static const char *const vfr_1_groups[] = { +static const char *const vfr_groups[] = { "gpio59", }; @@ -1223,15 +911,10 @@ static const char *const vsense_trigger_mirnat_groups[] = { "gpio58", }; -static const char *const wlan1_adc0_groups[] = { - "gpio14", -}; - -static const char *const wlan1_adc1_groups[] = { - "gpio15", +static const char *const wlan_groups[] = { + "gpio14", "gpio15", }; - static const struct pinfunction shikra_functions[] = { MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(agera_pll), @@ -1239,73 +922,38 @@ static const struct pinfunction shikra_functions[] = { MSM_PIN_FUNCTION(atest_char), MSM_PIN_FUNCTION(atest_gpsadc), MSM_PIN_FUNCTION(atest_tsens), - MSM_PIN_FUNCTION(atest_tsens2), MSM_PIN_FUNCTION(atest_usb), MSM_PIN_FUNCTION(cam_mclk), - MSM_PIN_FUNCTION(cci_async_in0), - MSM_PIN_FUNCTION(cci_i2c_scl0), - MSM_PIN_FUNCTION(cci_i2c_scl1), - MSM_PIN_FUNCTION(cci_i2c_sda0), - MSM_PIN_FUNCTION(cci_i2c_sda1), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), MSM_PIN_FUNCTION(cci_timer), - MSM_PIN_FUNCTION(char_exec_pending), - MSM_PIN_FUNCTION(char_exec_release), + MSM_PIN_FUNCTION(char_exec), MSM_PIN_FUNCTION(cri_trng), - MSM_PIN_FUNCTION(cri_trng0), - MSM_PIN_FUNCTION(cri_trng1), MSM_PIN_FUNCTION(dac_calib), MSM_PIN_FUNCTION(dbg_out_clk), - MSM_PIN_FUNCTION(ddr_bist_complete), - MSM_PIN_FUNCTION(ddr_bist_fail), - MSM_PIN_FUNCTION(ddr_bist_start), - MSM_PIN_FUNCTION(ddr_bist_stop), - MSM_PIN_FUNCTION(ddr_pxi0), - MSM_PIN_FUNCTION(ddr_pxi1), - MSM_PIN_FUNCTION(dmic0_clk), - MSM_PIN_FUNCTION(dmic0_data), - MSM_PIN_FUNCTION(dmic1_clk), - MSM_PIN_FUNCTION(dmic1_data), - MSM_PIN_FUNCTION(emac0_dll), - MSM_PIN_FUNCTION(emac0_mcg0), - MSM_PIN_FUNCTION(emac0_mcg1), - MSM_PIN_FUNCTION(emac0_mcg2), - MSM_PIN_FUNCTION(emac0_mcg3), - MSM_PIN_FUNCTION(emac0_phy), - MSM_PIN_FUNCTION(emac0_ptp), - MSM_PIN_FUNCTION(emac1_dll), - MSM_PIN_FUNCTION(emac1_mcg0), - MSM_PIN_FUNCTION(emac1_mcg1), - MSM_PIN_FUNCTION(emac1_mcg2), - MSM_PIN_FUNCTION(emac1_mcg3), - MSM_PIN_FUNCTION(emac1_phy), - MSM_PIN_FUNCTION(emac1_ptp), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dmic), + MSM_PIN_FUNCTION(emac_dll), + MSM_PIN_FUNCTION(emac_mcg), + MSM_PIN_FUNCTION(emac_phy), + MSM_PIN_FUNCTION(emac0_ptp_aux), + MSM_PIN_FUNCTION(emac0_ptp_pps), + MSM_PIN_FUNCTION(emac1_ptp_aux), + MSM_PIN_FUNCTION(emac1_ptp_pps), MSM_PIN_FUNCTION(ext_mclk), - MSM_PIN_FUNCTION(gcc_gp1), - MSM_PIN_FUNCTION(gcc_gp2), - MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_gp), MSM_PIN_FUNCTION(gsm0_tx), - MSM_PIN_FUNCTION(i2s0_clk), - MSM_PIN_FUNCTION(i2s0_data0), - MSM_PIN_FUNCTION(i2s0_data1), - MSM_PIN_FUNCTION(i2s0_data2), - MSM_PIN_FUNCTION(i2s0_data3), - MSM_PIN_FUNCTION(i2s0_ws), - MSM_PIN_FUNCTION(i2s1_clk), - MSM_PIN_FUNCTION(i2s1_data0), - MSM_PIN_FUNCTION(i2s1_data1), - MSM_PIN_FUNCTION(i2s1_ws), - MSM_PIN_FUNCTION(i2s2_clk), - MSM_PIN_FUNCTION(i2s2_data0), - MSM_PIN_FUNCTION(i2s2_data1), - MSM_PIN_FUNCTION(i2s2_ws), - MSM_PIN_FUNCTION(i2s3_clk), - MSM_PIN_FUNCTION(i2s3_data0), - MSM_PIN_FUNCTION(i2s3_data1), - MSM_PIN_FUNCTION(i2s3_ws), + MSM_PIN_FUNCTION(i2s0), + MSM_PIN_FUNCTION(i2s1), + MSM_PIN_FUNCTION(i2s2), + MSM_PIN_FUNCTION(i2s3), MSM_PIN_FUNCTION(jitter_bist), MSM_PIN_FUNCTION(m_voc), - MSM_PIN_FUNCTION(mdp_vsync), MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_out0), + MSM_PIN_FUNCTION(mdp_vsync_out1), MSM_PIN_FUNCTION(mdp_vsync_p), MSM_PIN_FUNCTION(mdp_vsync_s), MSM_PIN_FUNCTION(mpm_pwr), @@ -1316,93 +964,45 @@ static const struct pinfunction shikra_functions[] = { MSM_PIN_FUNCTION(pbs_out), MSM_PIN_FUNCTION(pcie0_clk_req_n), MSM_PIN_FUNCTION(phase_flag), - MSM_PIN_FUNCTION(pll_bist), - MSM_PIN_FUNCTION(pll_bypassnl), - MSM_PIN_FUNCTION(pll_clk), - MSM_PIN_FUNCTION(pll_reset_n), + MSM_PIN_FUNCTION(pll), MSM_PIN_FUNCTION(prng_rosc), - MSM_PIN_FUNCTION(pwm_0), - MSM_PIN_FUNCTION(pwm_1), - MSM_PIN_FUNCTION(pwm_2), - MSM_PIN_FUNCTION(pwm_3), - MSM_PIN_FUNCTION(pwm_4), - MSM_PIN_FUNCTION(pwm_5), - MSM_PIN_FUNCTION(pwm_6), - MSM_PIN_FUNCTION(pwm_7), - MSM_PIN_FUNCTION(pwm_8), - MSM_PIN_FUNCTION(pwm_9), + MSM_PIN_FUNCTION(pwm), MSM_PIN_FUNCTION(qdss_cti), MSM_PIN_FUNCTION(qup0_se0), MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se1_01), + MSM_PIN_FUNCTION(qup0_se1_23), MSM_PIN_FUNCTION(qup0_se2), - MSM_PIN_FUNCTION(qup0_se3), - MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se3_01), + MSM_PIN_FUNCTION(qup0_se3_23), + MSM_PIN_FUNCTION(qup0_se4_01), + MSM_PIN_FUNCTION(qup0_se4_23), MSM_PIN_FUNCTION(qup0_se5), MSM_PIN_FUNCTION(qup0_se6), - MSM_PIN_FUNCTION(qup0_se7), + MSM_PIN_FUNCTION(qup0_se7_01), + MSM_PIN_FUNCTION(qup0_se7_23), MSM_PIN_FUNCTION(qup0_se8), MSM_PIN_FUNCTION(qup0_se9), - MSM_PIN_FUNCTION(rgmii0_mdc), - MSM_PIN_FUNCTION(rgmii0_mdio), - MSM_PIN_FUNCTION(rgmii0_rx_ctl), - MSM_PIN_FUNCTION(rgmii0_rxc), - MSM_PIN_FUNCTION(rgmii0_rxd0), - MSM_PIN_FUNCTION(rgmii0_rxd1), - MSM_PIN_FUNCTION(rgmii0_rxd2), - MSM_PIN_FUNCTION(rgmii0_rxd3), - MSM_PIN_FUNCTION(rgmii0_tx_ctl), - MSM_PIN_FUNCTION(rgmii0_txc), - MSM_PIN_FUNCTION(rgmii0_txd0), - MSM_PIN_FUNCTION(rgmii0_txd1), - MSM_PIN_FUNCTION(rgmii0_txd2), - MSM_PIN_FUNCTION(rgmii0_txd3), - MSM_PIN_FUNCTION(rgmii1_mdc), - MSM_PIN_FUNCTION(rgmii1_mdio), - MSM_PIN_FUNCTION(rgmii1_rx_ctl), - MSM_PIN_FUNCTION(rgmii1_rxc), - MSM_PIN_FUNCTION(rgmii1_rxd0), - MSM_PIN_FUNCTION(rgmii1_rxd1), - MSM_PIN_FUNCTION(rgmii1_rxd2), - MSM_PIN_FUNCTION(rgmii1_rxd3), - MSM_PIN_FUNCTION(rgmii1_tx_ctl), - MSM_PIN_FUNCTION(rgmii1_txc), - MSM_PIN_FUNCTION(rgmii1_txd0), - MSM_PIN_FUNCTION(rgmii1_txd1), - MSM_PIN_FUNCTION(rgmii1_txd2), - MSM_PIN_FUNCTION(rgmii1_txd3), + MSM_PIN_FUNCTION(qup0_se9_01), + MSM_PIN_FUNCTION(qup0_se9_23), + MSM_PIN_FUNCTION(rgmii), MSM_PIN_FUNCTION(sd_write_protect), - MSM_PIN_FUNCTION(sdc1_tb_trig), - MSM_PIN_FUNCTION(sdc2_tb_trig), - MSM_PIN_FUNCTION(ssbi_wtr0), - MSM_PIN_FUNCTION(ssbi_wtr1), - MSM_PIN_FUNCTION(ssbi_wtr2), - MSM_PIN_FUNCTION(ssbi_wtr3), - MSM_PIN_FUNCTION(swr0_rx_clk), - MSM_PIN_FUNCTION(swr0_rx_data0), - MSM_PIN_FUNCTION(swr0_rx_data1), - MSM_PIN_FUNCTION(swr0_tx_clk), - MSM_PIN_FUNCTION(swr0_tx_data0), - MSM_PIN_FUNCTION(tgu_ch0_trigout), - MSM_PIN_FUNCTION(tgu_ch1_trigout), - MSM_PIN_FUNCTION(tgu_ch2_trigout), - MSM_PIN_FUNCTION(tgu_ch3_trigout), + MSM_PIN_FUNCTION(sdc_cdc), + MSM_PIN_FUNCTION(sdc_tb_trig), + MSM_PIN_FUNCTION(ssbi_wtr), + MSM_PIN_FUNCTION(swr0_rx), + MSM_PIN_FUNCTION(swr0_tx), + MSM_PIN_FUNCTION(tgu_ch_trigout), MSM_PIN_FUNCTION(tsc_async), MSM_PIN_FUNCTION(tsense_pwm), - MSM_PIN_FUNCTION(uim1_clk), - MSM_PIN_FUNCTION(uim1_data), - MSM_PIN_FUNCTION(uim1_present), - MSM_PIN_FUNCTION(uim1_reset), - MSM_PIN_FUNCTION(uim2_clk), - MSM_PIN_FUNCTION(uim2_data), - MSM_PIN_FUNCTION(uim2_present), - MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), MSM_PIN_FUNCTION(unused_adsp), MSM_PIN_FUNCTION(unused_gsm1), MSM_PIN_FUNCTION(usb0_phy_ps), - MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vfr), MSM_PIN_FUNCTION(vsense_trigger_mirnat), - MSM_PIN_FUNCTION(wlan1_adc0), - MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan), }; static const struct msm_pingroup shikra_groups[] = { From b8178c85d4fbaaaf4801f0e930f873304abb96b0 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Thu, 16 Jul 2026 23:29:58 +0200 Subject: [PATCH 1179/1330] UBUNTU: SAUCE: PCI: dwc: update D3cold eligibility helper call after rename "FROMLIST: PCI: host-common: Add helper to determine host bridge D3cold eligibility" renames pci_host_common_can_enter_d3cold() to pci_host_common_d3cold_possible() and gives it a second out-parameter (bool *pme_capable). That commit was cherry-picked during the July qcom-next-7.1-rc6 rebase and updated the helper definition/declaration, but the caller in dw_pcie_suspend_noirq() (which entered our tree earlier as a graduated-upstream change) was left calling the old name/signature: pcie-designware-host.c: error: implicit declaration of function 'pci_host_common_can_enter_d3cold' Update the caller to the new name and pass a pme_capable out-parameter, matching the qcom-next tip. Our tree does not carry the pwrctrl skip_pwrctrl_off field, so pme_capable is only used to satisfy the new interface. Signed-off-by: kuba.pawlak@canonical.com Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9861768631efa..59a88cd4a568d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1207,13 +1207,14 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) int dw_pcie_suspend_noirq(struct dw_pcie *pci) { + bool pme_capable = false; int ret = 0; u32 val; if (!dw_pcie_link_up(pci)) goto stop_link; - if (!pci_host_common_can_enter_d3cold(pci->pp.bridge)) + if (!pci_host_common_d3cold_possible(pci->pp.bridge, &pme_capable)) return 0; if (pci->pp.ops->pme_turn_off) { From 785eb7894e8eff75a63ad035fa56d20b0f4b922e Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Fri, 17 Jul 2026 07:25:50 +0200 Subject: [PATCH 1180/1330] UBUNTU: SAUCE: soc: qcom: ubwc: add UBWC config accessor helpers The July qcom-next-7.1-rc6 rebase brought in the iris "retrieve UBWC platform configuration" series, whose gen2 packetization code calls the qcom_ubwc_* accessor helpers: iris_hfi_gen2_packet.c: error: implicit declaration of function 'qcom_ubwc_macrotile_mode' (and _min_acc_length_64b, _swizzle, _bank_spread) Our include/linux/soc/qcom/ubwc.h carried the struct fields but not these inline accessors (graduated-upstream gap). The rest of the header is identical to the qcom-next tip, so add the four missing inline helpers to match. No functional change beyond exposing the accessors. Signed-off-by: kuba.pawlak@canonical.com Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- include/linux/soc/qcom/ubwc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index f052e241736c4..f5d0e23412611 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -74,4 +74,29 @@ static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg) return ret; } +/* + * This is the best guess, based on the MDSS driver, which worked so far. + */ +static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data *cfg) +{ + return cfg->ubwc_enc_version == UBWC_1_0 && + (cfg->ubwc_dec_version == UBWC_2_0 || + cfg->ubwc_dec_version == UBWC_3_0); +} + +static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg) +{ + return cfg->macrotile_mode; +} + +static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg) +{ + return cfg->ubwc_bank_spread; +} + +static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) +{ + return cfg->ubwc_swizzle; +} + #endif /* __QCOM_UBWC_H__ */ From abb2731f8240678ae2c256e35b5aefe80df031a9 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Fri, 17 Jul 2026 09:57:54 +0200 Subject: [PATCH 1181/1330] UBUNTU: SAUCE: media: iris: add iris driver at qcom-next-7.1-rc6 tip state Bring drivers/media/platform/qcom/iris/ to the qcom-next-7.1-rc6 tip (c99e264f) in a single step. Qualcomm's qcom-next branch develops the iris driver through a long sequence of apply / revert / re-apply churn (Secure PAS, context banks, platform-data splits, UBWC config retrieval, glymur/kaanapali/X1P42100 platform data). Cherry-picking that history commit-by-commit produced 47 iris-only commits (21 FROM*/PENDING adds interleaved with 26 reverts) whose only lasting effect is the final directory state, and which -- when replayed with take-theirs conflict resolution -- left the tree inconsistent and unbuildable. The iris directory carries no Ubuntu-specific content, so those 47 churn commits have been dropped and the directory is checked out wholesale from the qcom-next tip, which is the intended, self-consistent end state. This matches Qualcomm exactly and builds cleanly (the qcom_scm PAS-context API and the UBWC accessor helpers added in a separate commit are present). Equivalent to the previous incremental fixes (iris firmware Secure-PAS adaptation + wholesale sync); flattened here into one commit for a clean, reviewable patchset. Signed-off-by: kuba.pawlak@canonical.com Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/media/platform/qcom/iris/Kconfig | 1 + drivers/media/platform/qcom/iris/Makefile | 6 +- drivers/media/platform/qcom/iris/iris_core.c | 2 + drivers/media/platform/qcom/iris/iris_core.h | 4 + .../media/platform/qcom/iris/iris_firmware.c | 107 ++++++++++++++--- .../qcom/iris/iris_hfi_gen2_command.c | 15 +-- .../platform/qcom/iris/iris_hfi_gen2_packet.c | 18 +-- .../platform/qcom/iris/iris_platform_common.h | 20 +--- .../qcom/iris/iris_platform_qcs8300.h | 1 - .../platform/qcom/iris/iris_platform_sm8550.h | 1 - .../platform/qcom/iris/iris_platform_vpu2.c | 15 ++- .../platform/qcom/iris/iris_platform_vpu3x.c | 110 ++++++++---------- .../platform/qcom/iris/iris_platform_vpu4x.c | 14 +-- drivers/media/platform/qcom/iris/iris_probe.c | 10 +- drivers/media/platform/qcom/iris/iris_vdec.c | 3 +- drivers/media/platform/qcom/iris/iris_vidc.c | 3 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 1 + .../platform/qcom/iris/iris_vpu_buffer.c | 22 +++- .../platform/qcom/iris/iris_vpu_common.c | 9 -- 19 files changed, 206 insertions(+), 156 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platform/qcom/iris/Kconfig index 5498f48362d15..af78a1775937b 100644 --- a/drivers/media/platform/qcom/iris/Kconfig +++ b/drivers/media/platform/qcom/iris/Kconfig @@ -5,6 +5,7 @@ config VIDEO_QCOM_IRIS select V4L2_MEM2MEM_DEV select QCOM_MDT_LOADER select QCOM_SCM + select QCOM_UBWC_CONFIG select VIDEOBUF2_DMA_CONTIG help This is a V4L2 driver for Qualcomm iris video accelerator diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index a898a4a7eff01..8cdea242f7fdb 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -12,8 +12,10 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_gen1.o \ - iris_platform_gen2.o \ + iris_platform_glymur.o \ + iris_platform_vpu2.o \ + iris_platform_vpu3x.o \ + iris_platform_vpu4x.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c index 48a5bd39d836f..932c32f95a283 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -83,6 +83,8 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_unload_fw; + core->iris_firmware_data->init_hfi_ops(core); + ret = iris_hfi_core_init(core); if (ret) goto error_unload_fw; diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index c15b375e37909..1bc001df0cec4 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -30,6 +30,8 @@ enum domain_type { DECODER = BIT(1), }; +struct qcom_ubwc_cfg_data; + enum iris_vcodec_core_id { IRIS_VCODEC0 = 1, IRIS_VCODEC1, @@ -62,6 +64,7 @@ enum iris_vcodec_core_id { * @iris_platform_data: a structure for platform data * @iris_firmware_data: a pointer to the firmware (or HFI) specific data * @iris_firmware_desc: a pointer to the firmware-specific descriptive data + * @ubwc_cfg: UBWC configuration for the platform * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory @@ -114,6 +117,7 @@ struct iris_core { const struct iris_platform_data *iris_platform_data; const struct iris_firmware_data *iris_firmware_data; const struct iris_firmware_desc *iris_firmware_desc; + const struct qcom_ubwc_cfg_data *ubwc_cfg; enum iris_core_state state; dma_addr_t iface_q_table_daddr; dma_addr_t sfr_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index 07b1d71505baf..86ab578a4ec87 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -17,24 +17,99 @@ #include "iris_core.h" #include "iris_firmware.h" -#define IRIS_PAS_ID 9 +#define IRIS_PAS_ID 9 #define MAX_FIRMWARE_NAME_SIZE 128 -static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) +/* Detect Gen2 firmware by scanning the blob for: + * QC_IMAGE_VERSION_STRING= + * and then checking: + * - version starts with "vfw", OR + * - version matches "video-firmware.N.M" with N >= 2 + */ + +static bool iris_detect_gen2_from_fwdata(const u8 *data, size_t size) +{ + const char *marker = "QC_IMAGE_VERSION_STRING="; + const size_t mlen = strlen(marker); + int major = 0, minor = 0; + char version_buf[64]; + size_t max; + + max = (size > mlen) ? size - mlen : 0; + for (size_t i = 0; i < max; i++) { + if (!memcmp(data + i, marker, mlen)) { + const char *found = (const char *)(data + i + mlen); + + strscpy(version_buf, found, sizeof(version_buf)); + if (!strncmp(version_buf, "vfw", 3)) + return true; + if (sscanf(version_buf, "video-firmware.%d.%d", &major, &minor) == 2 && + major >= 2) + return true; + break; + } + } + + return false; +} + +static const struct firmware *iris_detect_firmware(struct iris_core *core, + const char **fw_name) +{ + const struct firmware *firmware; + bool has_both_gens; + int ret; + + *fw_name = NULL; + if (core->iris_platform_data->firmware_desc_gen2) + core->iris_firmware_desc = core->iris_platform_data->firmware_desc_gen2; + else if (core->iris_platform_data->firmware_desc_gen1) + core->iris_firmware_desc = core->iris_platform_data->firmware_desc_gen1; + else + return ERR_PTR(-EINVAL); + + has_both_gens = core->iris_platform_data->firmware_desc_gen2 && + core->iris_platform_data->firmware_desc_gen1; + + ret = of_property_read_string_index(dev_of_node(core->dev), "firmware-name", 0, fw_name); + if (ret) { + *fw_name = core->iris_firmware_desc->fwname; + ret = request_firmware(&firmware, *fw_name, core->dev); + if (ret && has_both_gens) { + core->iris_firmware_desc = core->iris_platform_data->firmware_desc_gen1; + *fw_name = core->iris_firmware_desc->fwname; + ret = request_firmware(&firmware, *fw_name, core->dev); + } + + return ret ? ERR_PTR(ret) : firmware; + } + + ret = request_firmware(&firmware, *fw_name, core->dev); + if (ret) + return ERR_PTR(ret); + + if (has_both_gens && + !iris_detect_gen2_from_fwdata((const u8 *)firmware->data, firmware->size)) { + dev_info(core->dev, "Gen1 FW detected in %s\n", *fw_name); + core->iris_firmware_desc = core->iris_platform_data->firmware_desc_gen1; + } + + return firmware; +} + +static int iris_load_fw_to_memory(struct iris_core *core) { struct qcom_scm_pas_context *ctx; const struct firmware *firmware = NULL; struct device *dev = core->dev; struct resource res; phys_addr_t mem_phys; + const char *fw_name; size_t res_size; ssize_t fw_size; int ret; - if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4) - return -EINVAL; - ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); if (ret) return ret; @@ -50,9 +125,11 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) ctx->use_tzmem = core->fw.dev; - ret = request_firmware(&firmware, fw_name, dev); - if (ret) - return ret; + firmware = iris_detect_firmware(core, &fw_name); + if (IS_ERR(firmware)) + return PTR_ERR(firmware); + + core->iris_firmware_data = core->iris_firmware_desc->firmware_data; fw_size = qcom_mdt_get_size(firmware); if (fw_size < 0 || res_size < (size_t)fw_size) { @@ -91,18 +168,12 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) int iris_fw_load(struct iris_core *core) { const struct tz_cp_config *cp_config; - const char *fwpath = NULL; int i, ret; - ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0, - &fwpath); - if (ret) - fwpath = core->iris_firmware_desc->fwname; - - ret = iris_load_fw_to_memory(core, fwpath); + ret = iris_load_fw_to_memory(core); if (ret) { - dev_err(core->dev, "firmware download failed\n"); - return -ENOMEM; + dev_err(core->dev, "firmware download failed %d\n", ret); + return ret; } for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { @@ -118,7 +189,7 @@ int iris_fw_load(struct iris_core *core) } } - return ret; + return 0; } int iris_fw_unload(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index a3533a1450bb6..1d8b47e7164ee 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -10,7 +10,6 @@ #define UNSPECIFIED_COLOR_FORMAT 5 #define NUM_SYS_INIT_PACKETS 8 -#define NUM_COMV_AV1 18 #define SYS_INIT_PKT_SIZE (sizeof(struct iris_hfi_header) + \ NUM_SYS_INIT_PACKETS * (sizeof(struct iris_hfi_packet) + sizeof(u32))) @@ -1207,18 +1206,10 @@ static u32 iris_hfi_gen2_buf_type_from_driver(u32 domain, enum iris_buffer_type static int iris_hfi_gen2_set_num_comv(struct iris_inst *inst) { - struct platform_inst_caps *caps; - struct iris_core *core = inst->core; - u32 num_comv; - - caps = core->iris_platform_data->inst_caps; + u32 num_comv = inst->buffers[BUF_OUTPUT].min_count; - /* - * AV1 needs more comv buffers than other codecs. - * Update accordingly. - */ - num_comv = (inst->codec == V4L2_PIX_FMT_AV1) ? - NUM_COMV_AV1 : caps->num_comv; + if (inst->fw_min_count) + num_comv = inst->fw_min_count; return iris_hfi_gen2_session_set_property(inst, HFI_PROP_COMV_BUFFER_COUNT, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c index d77fa29f44fc6..0d05dd2afc07d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c @@ -3,6 +3,9 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + #include "iris_hfi_common.h" #include "iris_hfi_gen2.h" #include "iris_hfi_gen2_packet.h" @@ -120,6 +123,7 @@ static void iris_hfi_gen2_create_packet(struct iris_hfi_header *hdr, u32 pkt_typ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_header *hdr) { + const struct qcom_ubwc_cfg_data *ubwc = core->ubwc_cfg; u32 payload = 0; iris_hfi_gen2_create_header(hdr, 0, core->header_id++); @@ -136,7 +140,7 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade &payload, sizeof(u32)); - payload = core->iris_platform_data->ubwc_config->max_channels; + payload = qcom_ubwc_macrotile_mode(ubwc) ? 8 : 4; iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_MAX_CHANNELS, HFI_HOST_FLAGS_NONE, @@ -146,7 +150,7 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade &payload, sizeof(u32)); - payload = core->iris_platform_data->ubwc_config->mal_length; + payload = qcom_ubwc_min_acc_length_64b(ubwc) ? 64 : 32; iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_MAL_LENGTH, HFI_HOST_FLAGS_NONE, @@ -156,7 +160,7 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade &payload, sizeof(u32)); - payload = core->iris_platform_data->ubwc_config->highest_bank_bit; + payload = ubwc->highest_bank_bit; iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_HBB, HFI_HOST_FLAGS_NONE, @@ -166,7 +170,7 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade &payload, sizeof(u32)); - payload = core->iris_platform_data->ubwc_config->bank_swzl_level; + payload = !!(qcom_ubwc_swizzle(ubwc) & UBWC_SWIZZLE_ENABLE_LVL1); iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_BANK_SWZL_LEVEL1, HFI_HOST_FLAGS_NONE, @@ -176,7 +180,7 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade &payload, sizeof(u32)); - payload = core->iris_platform_data->ubwc_config->bank_swz2_level; + payload = !!(qcom_ubwc_swizzle(ubwc) & UBWC_SWIZZLE_ENABLE_LVL2); iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_BANK_SWZL_LEVEL2, HFI_HOST_FLAGS_NONE, @@ -186,7 +190,7 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade &payload, sizeof(u32)); - payload = core->iris_platform_data->ubwc_config->bank_swz3_level; + payload = !!(qcom_ubwc_swizzle(ubwc) & UBWC_SWIZZLE_ENABLE_LVL3); iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_BANK_SWZL_LEVEL3, HFI_HOST_FLAGS_NONE, @@ -196,7 +200,7 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade &payload, sizeof(u32)); - payload = core->iris_platform_data->ubwc_config->bank_spreading; + payload = qcom_ubwc_bank_spread(ubwc); iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_BANK_SPREADING, HFI_HOST_FLAGS_NONE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 45c0ec69466ca..51af2e13fe526 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -87,16 +87,6 @@ struct tz_cp_config { u32 cp_nonpixel_size; }; -struct ubwc_config_data { - u32 max_channels; - u32 mal_length; - u32 highest_bank_bit; - u32 bank_swzl_level; - u32 bank_swz2_level; - u32 bank_swz3_level; - u32 bank_spreading; -}; - struct platform_inst_caps { u32 min_frame_width; u32 max_frame_width; @@ -107,7 +97,6 @@ struct platform_inst_caps { u32 mb_cycles_vpp; u32 mb_cycles_fw; u32 mb_cycles_fw_vpp; - u32 num_comv; u32 max_frame_rate; u32 max_operating_rate; }; @@ -284,14 +273,10 @@ struct platform_pd_data { }; struct iris_platform_data { - /* - * XXX: replace with gen1 / gen2 pointers once we have platforms - * supporting both firmware kinds. - */ - const struct iris_firmware_desc *firmware_desc; + const struct iris_firmware_desc *firmware_desc_gen1, *firmware_desc_gen2; const struct vpu_ops *vpu_ops; - void (*set_preset_registers)(struct iris_core *core); + int (*init_cb_devs)(struct iris_core *core); void (*deinit_cb_devs)(struct iris_core *core); const struct icc_info *icc_tbl; @@ -314,7 +299,6 @@ struct iris_platform_data { struct platform_inst_caps *inst_caps; const struct tz_cp_config *tz_cp_config_data; u32 tz_cp_config_data_size; - struct ubwc_config_data *ubwc_config; u32 num_vpp_pipe; bool no_aon; u32 max_session_count; diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h index 61025f1e965b8..3cfecae80d1e9 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -15,7 +15,6 @@ static struct platform_inst_caps platform_inst_cap_qcs8300 = { .mb_cycles_vpp = 200, .mb_cycles_fw = 326389, .mb_cycles_fw_vpp = 44156, - .num_comv = 0, .max_frame_rate = MAXIMUM_FPS, .max_operating_rate = MAXIMUM_FPS, }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h index 3b3f17b18707e..03a63904579e1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -23,7 +23,6 @@ static struct platform_inst_caps platform_inst_cap_sm8550 = { .mb_cycles_vpp = 200, .mb_cycles_fw = 489583, .mb_cycles_fw_vpp = 66234, - .num_comv = 0, .max_frame_rate = MAXIMUM_FPS, .max_operating_rate = MAXIMUM_FPS, }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 3c820c8ac9557..1105ff897fa10 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -16,13 +16,19 @@ #include "iris_platform_sc7280.h" #include "iris_platform_sm8250.h" -const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = { +static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = { .firmware_data = &iris_hfi_gen1_data, .get_vpu_buffer_size = iris_vpu_buf_size, .fwname = "qcom/vpu/vpu20_p1.mbn", }; -const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = { +static const struct iris_firmware_desc iris_vpu20_p1_gen2_s6_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .fwname = "qcom/vpu/vpu20_p1_gen2_s6.mbn", +}; + +static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = { .firmware_data = &iris_hfi_gen1_data, .get_vpu_buffer_size = iris_vpu_buf_size, .fwname = "qcom/vpu/vpu20_p4.mbn", @@ -84,7 +90,8 @@ static const struct tz_cp_config tz_cp_config_vpu2[] = { }; const struct iris_platform_data sc7280_data = { - .firmware_desc = &iris_vpu20_p1_gen1_desc, + .firmware_desc_gen1 = &iris_vpu20_p1_gen1_desc, + .firmware_desc_gen2 = &iris_vpu20_p1_gen2_s6_desc, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), @@ -112,7 +119,7 @@ const struct iris_platform_data sc7280_data = { }; const struct iris_platform_data sm8250_data = { - .firmware_desc = &iris_vpu20_p4_gen1_desc, + .firmware_desc_gen1 = &iris_vpu20_p4_gen1_desc, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index a6ad4cc6c0635..42fad209b6bd3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -19,31 +19,25 @@ #include "iris_platform_sm8750.h" #include "iris_platform_x1p42100.h" -const struct iris_firmware_desc iris_vpu36_p4_s7_gen2_desc = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .fwname = "qcom/vpu/vpu36_p4_s7.mbn", -}; - -const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { +static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, .fwname = "qcom/vpu/vpu30_p4_s6.mbn", }; -const struct iris_firmware_desc iris_vpu30_p4_gen2_desc = { +static const struct iris_firmware_desc iris_vpu30_p4_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, .fwname = "qcom/vpu/vpu30_p4.mbn", }; -const struct iris_firmware_desc iris_vpu33_p4_gen2_desc = { +static const struct iris_firmware_desc iris_vpu33_p4_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu33_buf_size, .fwname = "qcom/vpu/vpu33_p4.mbn", }; -const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = { +static const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu33_buf_size, .fwname = "qcom/vpu/vpu35_p4.mbn", @@ -99,16 +93,6 @@ static const char * const iris_opp_clk_table_vpu3x[] = { NULL, }; -static struct ubwc_config_data iris_ubwc_config_vpu3x = { - .max_channels = 8, - .mal_length = 32, - .highest_bank_bit = 16, - .bank_swzl_level = 0, - .bank_swz2_level = 1, - .bank_swz3_level = 1, - .bank_spreading = 1, -}; - static const struct tz_cp_config tz_cp_config_vpu3[] = { { .cp_start = 0, @@ -118,6 +102,38 @@ static const struct tz_cp_config tz_cp_config_vpu3[] = { }, }; +/* + * Shares most of SM8550 data except: + * - inst_caps to platform_inst_cap_qcs8300 + */ +const struct iris_platform_data qcs8300_data = { + .firmware_desc_gen2 = &iris_vpu30_p4_s6_gen2_desc, + .vpu_ops = &iris_vpu3_ops, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_qcs8300, + .tz_cp_config_data = tz_cp_config_vpu3, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), + .num_vpp_pipe = 2, + .max_session_count = 16, + .max_core_mbpf = ((4096 * 2176) / 256) * 4, + .max_core_mbps = (((3840 * 2176) / 256) * 120), +}; + static int sm8550_init_cb_devs(struct iris_core *core) { const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ @@ -147,6 +163,12 @@ static int sm8550_init_cb_devs(struct iris_core *core) return PTR_ERR(dev); } +const struct iris_firmware_desc iris_vpu36_p4_s7_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu36_p4_s7.mbn", +}; + static void sm8550_deinit_cb_devs(struct iris_core *core) { if (core->dev_np) @@ -160,7 +182,7 @@ static void sm8550_deinit_cb_devs(struct iris_core *core) } const struct iris_platform_data glymur_data = { - .firmware_desc = &iris_vpu36_p4_s7_gen2_desc, + .firmware_desc_gen2 = &iris_vpu36_p4_s7_gen2_desc, .vpu_ops = &iris_vpu36_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -181,7 +203,6 @@ const struct iris_platform_data glymur_data = { .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = iris_glymur_tz_cp_config, .tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config), - .ubwc_config = &iris_ubwc_config_vpu3x, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -189,41 +210,8 @@ const struct iris_platform_data glymur_data = { .dual_core = true, }; -/* - * Shares most of SM8550 data except: - * - inst_caps to platform_inst_cap_qcs8300 - */ -const struct iris_platform_data qcs8300_data = { - .firmware_desc = &iris_vpu30_p4_s6_gen2_desc, - .vpu_ops = &iris_vpu3_ops, - .icc_tbl = iris_icc_info_vpu3x, - .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), - .clk_rst_tbl = sm8550_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec = iris_bw_table_dec_vpu3x, - .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = &iris_pmdomain_table_vpu3x, - .opp_pd_tbl = iris_opp_pd_table_vpu3x, - .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = iris_opp_clk_table_vpu3x, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu3x_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), - .inst_caps = &platform_inst_cap_qcs8300, - .tz_cp_config_data = tz_cp_config_vpu3, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), - .ubwc_config = &iris_ubwc_config_vpu3x, - .num_vpp_pipe = 2, - .max_session_count = 16, - .max_core_mbpf = ((4096 * 2176) / 256) * 4, - .max_core_mbps = (((3840 * 2176) / 256) * 120), -}; - const struct iris_platform_data sm8550_data = { - .firmware_desc = &iris_vpu30_p4_gen2_desc, + .firmware_desc_gen2 = &iris_vpu30_p4_gen2_desc, .vpu_ops = &iris_vpu3_ops, .init_cb_devs = sm8550_init_cb_devs, .deinit_cb_devs = sm8550_deinit_cb_devs, @@ -246,7 +234,6 @@ const struct iris_platform_data sm8550_data = { .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), - .ubwc_config = &iris_ubwc_config_vpu3x, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -260,7 +247,7 @@ const struct iris_platform_data sm8550_data = { * - controller_rst_tbl to sm8650_controller_reset_table */ const struct iris_platform_data sm8650_data = { - .firmware_desc = &iris_vpu33_p4_gen2_desc, + .firmware_desc_gen2 = &iris_vpu33_p4_gen2_desc, .vpu_ops = &iris_vpu33_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -283,7 +270,6 @@ const struct iris_platform_data sm8650_data = { .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), - .ubwc_config = &iris_ubwc_config_vpu3x, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -291,7 +277,7 @@ const struct iris_platform_data sm8650_data = { }; const struct iris_platform_data sm8750_data = { - .firmware_desc = &iris_vpu35_p4_gen2_desc, + .firmware_desc_gen2 = &iris_vpu35_p4_gen2_desc, .vpu_ops = &iris_vpu35_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -312,7 +298,6 @@ const struct iris_platform_data sm8750_data = { .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), - .ubwc_config = &iris_ubwc_config_vpu3x, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -320,7 +305,7 @@ const struct iris_platform_data sm8750_data = { }; const struct iris_platform_data x1p42100_data = { - .firmware_desc = &iris_vpu30_p4_gen2_desc, + .firmware_desc_gen2 = &iris_vpu30_p4_gen2_desc, .vpu_ops = &iris_vpu3_purwa_ops, .init_cb_devs = sm8550_init_cb_devs, .deinit_cb_devs = sm8550_deinit_cb_devs, @@ -343,7 +328,6 @@ const struct iris_platform_data x1p42100_data = { .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), - .ubwc_config = &iris_ubwc_config_vpu3x, .num_vpp_pipe = 1, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c index 29fd795c98418..103aab2bb1044 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c @@ -62,23 +62,12 @@ static struct platform_inst_caps iris_inst_cap_vpu4x = { .mb_cycles_vpp = 200, .mb_cycles_fw = 489583, .mb_cycles_fw_vpp = 66234, - .num_comv = 0, .max_frame_rate = MAXIMUM_FPS, .max_operating_rate = MAXIMUM_FPS, }; -static struct ubwc_config_data iris_ubwc_config_vpu4x = { - .max_channels = 8, - .mal_length = 32, - .highest_bank_bit = 16, - .bank_swzl_level = 0, - .bank_swz2_level = 1, - .bank_swz3_level = 1, - .bank_spreading = 1, -}; - const struct iris_platform_data kaanapali_data = { - .firmware_desc = &iris_vpu40_p2_s7_gen2_desc, + .firmware_desc_gen2 = &iris_vpu40_p2_s7_gen2_desc, .vpu_ops = &iris_vpu4x_ops, .icc_tbl = iris_icc_info_vpu4x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu4x), @@ -99,7 +88,6 @@ const struct iris_platform_data kaanapali_data = { .inst_caps = &iris_inst_cap_vpu4x, .tz_cp_config_data = tz_cp_config_kaanapali, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), - .ubwc_config = &iris_ubwc_config_vpu4x, .num_vpp_pipe = 2, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index a8c8e8c07eb09..359485bb9f936 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "iris_core.h" #include "iris_ctrls.h" @@ -258,8 +259,10 @@ static int iris_probe(struct platform_device *pdev) return core->irq; core->iris_platform_data = of_device_get_match_data(core->dev); - core->iris_firmware_desc = core->iris_platform_data->firmware_desc; - core->iris_firmware_data = core->iris_firmware_desc->firmware_data; + + core->ubwc_cfg = qcom_ubwc_config_get_data(); + if (IS_ERR(core->ubwc_cfg)) + return PTR_ERR(core->ubwc_cfg); ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr, iris_hfi_isr_handler, IRQF_TRIGGER_HIGH, "iris", core); @@ -269,7 +272,6 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); iris_init_ops(core); - core->iris_firmware_data->init_hfi_ops(core); ret = iris_init_resources(core); if (ret) @@ -279,8 +281,6 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; - iris_session_init_caps(core); - ret = v4l2_device_register(dev, &core->v4l2_dev); if (ret) goto err_deinit_cb; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index 7a3fd6a2fd505..a0bcbeb426a0c 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -24,7 +24,7 @@ int iris_vdec_inst_init(struct iris_inst *inst) inst->fmt_src = kzalloc_obj(*inst->fmt_src); inst->fmt_dst = kzalloc_obj(*inst->fmt_dst); - inst->fw_min_count = MIN_BUFFERS; + inst->fw_min_count = 0; f = inst->fmt_src; f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; @@ -253,6 +253,7 @@ int iris_vdec_s_fmt(struct iris_inst *inst, struct v4l2_format *f) /* Update capture format based on new ip w/h */ output_fmt->fmt.pix_mp.width = ALIGN(f->fmt.pix_mp.width, 128); output_fmt->fmt.pix_mp.height = ALIGN(f->fmt.pix_mp.height, 32); + inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT); inst->buffers[BUF_OUTPUT].size = iris_get_buffer_size(inst, BUF_OUTPUT); inst->crop.left = 0; diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 735ec17290425..ae27d12a06b14 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -9,6 +9,7 @@ #include #include +#include "iris_ctrls.h" #include "iris_vidc.h" #include "iris_instance.h" #include "iris_vdec.h" @@ -200,6 +201,8 @@ int iris_open(struct file *filp) goto fail_m2m_release; } + iris_session_init_caps(core); + if (inst->domain == DECODER) ret = iris_vdec_inst_init(inst); else if (inst->domain == ENCODER) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index ba93c25e9363c..60359d45ed981 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -420,6 +420,7 @@ const struct vpu_ops iris_vpu3_ops = { .power_off_controller = iris_vpu_power_off_controller, .power_on_controller = iris_vpu_power_on_controller, .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode = iris_vpu_set_hwmode, }; const struct vpu_ops iris_vpu3_purwa_ops = { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c index 9270422c16019..7ac6d9e49584d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -731,6 +731,24 @@ static u32 iris_vpu_dec_comv_size(struct iris_inst *inst) u32 height = f->fmt.pix_mp.height; u32 width = f->fmt.pix_mp.width; + if (inst->codec == V4L2_PIX_FMT_H264) + return hfi_buffer_comv_h264d(width, height, num_comv); + else if (inst->codec == V4L2_PIX_FMT_HEVC) + return hfi_buffer_comv_h265d(width, height, num_comv); + + return 0; +} + +static u32 iris_vpu3x_4x_dec_comv_size(struct iris_inst *inst) +{ + u32 num_comv = inst->buffers[BUF_OUTPUT].min_count; + struct v4l2_format *f = inst->fmt_src; + u32 height = f->fmt.pix_mp.height; + u32 width = f->fmt.pix_mp.width; + + if (inst->fw_min_count) + num_comv = inst->fw_min_count; + if (inst->codec == V4L2_PIX_FMT_H264) return hfi_buffer_comv_h264d(width, height, num_comv); else if (inst->codec == V4L2_PIX_FMT_HEVC) @@ -2025,7 +2043,7 @@ u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type) static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = { {BUF_BIN, iris_vpu_dec_bin_size }, - {BUF_COMV, iris_vpu_dec_comv_size }, + {BUF_COMV, iris_vpu3x_4x_dec_comv_size }, {BUF_NON_COMV, iris_vpu_dec_non_comv_size }, {BUF_LINE, iris_vpu_dec_line_size }, {BUF_PERSIST, iris_vpu_dec_persist_size }, @@ -2098,7 +2116,7 @@ u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_typ static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = { {BUF_BIN, iris_vpu_dec_bin_size }, - {BUF_COMV, iris_vpu_dec_comv_size }, + {BUF_COMV, iris_vpu3x_4x_dec_comv_size }, {BUF_NON_COMV, iris_vpu_dec_non_comv_size }, {BUF_LINE, iris_vpu4x_dec_line_size }, {BUF_PERSIST, iris_vpu4x_dec_persist_size }, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 215ed79ab2339..c96c02862aeec 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -291,14 +291,8 @@ int iris_vpu_power_on_hw(struct iris_core *core) if (ret && ret != -ENOENT) goto err_disable_hw_clock; - ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); - if (ret) - goto err_disable_hw_ahb_clock; - return 0; -err_disable_hw_ahb_clock: - iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: @@ -314,9 +308,6 @@ int iris_vpu_set_hwmode(struct iris_core *core) int iris_vpu_switch_to_hwmode(struct iris_core *core) { - if (!core->iris_platform_data->vpu_ops->set_hwmode) - return 0; - return core->iris_platform_data->vpu_ops->set_hwmode(core); } From ff9d8816ea8d7719bea56be34794b3479c279e62 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 20 Jul 2026 14:05:14 +0200 Subject: [PATCH 1182/1330] UBUNTU: Start new release Ignore: yes Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 439bc5f14e546..4f1c8426440b8 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,3 +1,11 @@ +linux-qcom (7.0.0-1009.12) UNRELEASED; urgency=medium + + CHANGELOG: Do not edit directly. Autogenerated at release. + CHANGELOG: Use the printchanges target to see the current changes. + CHANGELOG: Use the insertchanges target to create the final log. + + -- Kuba Pawlak Mon, 20 Jul 2026 14:05:14 +0200 + linux-qcom (7.0.0-1008.11) resolute; urgency=medium * Miscellaneous Ubuntu changes From 195d8e8400977eba6d57dfa2f3c4c0e032d13d67 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Mon, 20 Jul 2026 14:05:26 +0200 Subject: [PATCH 1183/1330] UBUNTU: Ubuntu-qcom-7.0.0-1009.12 Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 256 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 251 insertions(+), 5 deletions(-) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 4f1c8426440b8..8444f86a864ab 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,10 +1,256 @@ -linux-qcom (7.0.0-1009.12) UNRELEASED; urgency=medium +linux-qcom (7.0.0-1009.12) resolute; urgency=medium - CHANGELOG: Do not edit directly. Autogenerated at release. - CHANGELOG: Use the printchanges target to see the current changes. - CHANGELOG: Use the insertchanges target to create the final log. + * Miscellaneous Ubuntu changes + - SAUCE: arm64: dts: qcom: glymur: Drop duplicate gpu/gmu nodes + - SAUCE: arm64: dts: qcom: purwa-iot-evk: adapt TSENS override to inline + thermal model + - SAUCE: pinctrl: qcom: shikra: fix PINGROUP macro/table mismatch + - SAUCE: PCI: dwc: update D3cold eligibility helper call after rename + - SAUCE: soc: qcom: ubwc: add UBWC config accessor helpers + - SAUCE: media: iris: add iris driver at qcom-next-7.1-rc6 tip state + + * Miscellaneous upstream changes + - FROMLIST: drm/msm/dp: return 0 from audio_prepare when cable is + disconnected + - FROMLIST: PCI: host-common: Add helper to determine host bridge D3cold + eligibility + - FROMLIST: PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling + rails/clocks + - QCLINUX: qcom-dcc: add shikra register list and move config to header + - FROMLIST: drm/msm/a8xx: Fix RSCC offset + - FROMLIST: dt-bindings: display/msm: gpu: Document Adreno X2-185 + - FROMLIST: dt-bindings: arm-smmu: Update the description for Glymur GPU + SMMU + - FROMLIST: arm64: dts: qcom: glymur: Add GPU smmu node + - FROMLIST: arm64: dts: qcom: Add GPU support for Glymur + - FROMLIST: arm64: dts: qcom: glymur: Add GPU cooling + - PENDING: arm64: dts: qcom: hamoa: add TGU in staging dtso + - PENDING: arm64: dts: qcom: sm8750: add TGU in staging dtso + - PENDING: arm64: dts: qcom: kaanapali: add TGU in staging dtso + - FROMLIST: arm64: dts: qcom: monaco: add GDSP fastrpc-compute-cb nodes + - FROMLIST: arm64: dts: qcom: shikra: Add qcrypto node support + - FROMLIST: arm64: dts: qcom: shikra: Add TRNG support + - FROMLIST: arm64: dts: qcom: shikra: Enable ice support + - arm64: dts: qcom: shikra: Add pm4125 s1 regulator + - arm64: dts: qcom: Add dedicated BT 3.3V dummy regulator. + - arm64: dts: qcom: shikra-cqs-evk: Enable display + - arm64: dts: qcom: Add AudioCoreCC node support on Shikra + - arm64: dts: qcom: Fix pm4125 vbus regulator compatible and constraints + - FROMLIST: genirq: export irq_can_set_affinity() for module drivers + - FROMLIST: wifi: ath12k: enable threaded NAPI when DP IRQ affinity is + unavailable + - FROMLIST: arm64: dts: qcom: sm8750: allow mode-switch events to reach + the QMP Combo PHY + - PENDING: arm64: dts: qcom: glymur: add Coresight devices for APSS debug + block + - WORKAROUND:arm64: dts: glymur-crd: Reset gpio added to touchscreen node + - FROMLIST: arm64: dts: qcom: sm8750: wire UFS to ice instance + - FROMLIST: soc: qcom: spmi-pmic: add SUBTYPEs for Glymur/Kaanapali/SM8750 + PMICs + - FROMLIST: dt-bindings: power: limits: Describe Qualcomm SPEL hardware + - FROMLIST: powercap: qcom: Add SPEL powercap driver + - FROMLIST: arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au + - FROMLIST: arm64: dts: qcom: kaanapali: add the GPU SMMU node + - FROMLIST: arm64: dts: qcom: Add GPU support for Kaanapali + - FROMLIST: arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU + - FROMLIST: arm64: dts: qcom: kaanapali: Add qfprom node + - FROMLIST: arm64: dts: qcom: kaanapali: Add GPU cooling + - FROMLIST: arm64: dts: qcom: Enable secondary mi2s + - FROMLIST: arm64: dts: qcom: qcs6490: Enable DP audio + - FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Add WCD headset playback + and record for qcs6490-rb3gen2 industrial mezzanine + - FROMLIST: drm/msm/a8xx: Make a8xx_recover IFPC safe + - FROMLIST: drm/msm/a6xx: Limit GXPD votes to recovery in A8x + - FROMLIST: arm64: dts: qcom: glymur: Enable SPEL powercap driver + - QCLINUX: defconfig: Enable Qualcomm SPEL driver + - QCLINUX: memory-dump: add memory dump table for Shikra + - arm64: dts: qcom: shikra: Enable MPSS remoteproc + - arm64: dts: qcom: shikra: Add DDR BWMON support + - arm64: dts: qcom: hamoa: add CAMX EL2 overlay + - arm64: dts: qcom: shikra: Add EPSS L3 interconnect provider node + - FROMLIST: arm64: dts: qcom: glymur: Configure DP endpoints for 2-lane + operation + - FROMLIST: arm64: dts: qcom: monaco: Move eMMC CQE support from SoC to + board DT + - FROMLIST: arm64: dts: qcom: monaco-evk: Enable SDHCI for SD Card via + overlay + - FROMLIST: arm64: dts: qcom: monaco-evk: Add SDHCI support for eMMC via + overlay + - FROMLIST: arm64: dts: qcom: kodiak: increase fastrpc compute-cb session + slots + - arm64: dts: qcom: shikra: Add BAM-DMUX support + - arm64: dts: qcom: shikra: Add CAMSS node + - arm64: dts: qcom: shikra: Add CCI definitions + - arm64: dts: qcom: shikra: Add pin configuration for mclks + - arm64: dts: qcom: shikra-cqm-evk-imx577-camera: Add DT overlay + - arm64: dts: qcom: shikra-iqs-evk-imx577-camera: Add DT overlay + - arm64: dts: qcom: shikra: Add CPU OPP tables to scale DDR/L3 + - arm64: dts: qcom: Update cpufreq node for Shikra SoC + - QCLINUX: arm64: configs: Add Linux software RAID support + - QCLINUX: arm64: configs: Enable SmartPQI support + - ARM: dts: msm: Add support for shikra GPU + - dt-bindings: regulator: qcom,usb-vbus-regulator: add qcom,pm4125-vbus- + reg + - regulator: qcom_usb_vbus: add support for qcom,pm4125-vbus-reg + - FROMLIST: dt-bindings: crypto: qcom,prng: Document Shikra TRNG + - FROMLIST: dt-bindings: crypto: qcom-qce: Document the Shikra crypto + engine + - dt-bindings: bam-dma: Increase maxItems to seven for iommus + - dt-bindings: crypto: qcom,inline-crypto-engine: Document Shikra ICE + - clk: qcom: common: Register reset controller only when resets are + present + - clk: qcom: common: Skip NULL clock hw entries during registration + - dt-bindings: clock: qcom: Add GCC LPASS clocks support for Shikra + - clk: qcom: gcc-shikra: Mark GCC LPASS clocks as critical + - dt-bindings: clock: qcom: Add Qualcomm Shikra Audio Core Clock + Controller + - clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra + SoC + - soc: qcom: rpmpd: Reuse sm6125 power domains for shikra + - soc: qcom: pd-mapper: Add shikra PD support for CQM/CQS/IQS + - soc: qcom: pd-mapper: Fix shikra compatible strings to use -som suffix + - dt-bindings: regulator: qcom,usb-vbus-regulator: fix allOf schema + - dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible + - dt-bindings: interconnect: qcom,shikra-epss-l3: Add EPSS L3 DT binding + - interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC + - dt-bindings: media: qcom: Add Shikra CAMSS compatible + - dt-bindings: i2c: qcom-cci: Document Shikra compatible + - media: qcom: camss: add support for QCM2390 camss + - soc: qcom: smsm: Increase default num_hosts to 5 for Shikra + - dmaengine: qcom: bam_dma: Defer IRQ trigger type to device tree + - arm64: defconfig: Enable Qualcomm BAM-DMUX WWAN driver + - drm/msm/adreno: Add support for A704 GPU + - dt-bindings: display/msm/gpu: Add support for A704 shikra GPU + - dt-bindings: cpufreq: qcom-hw: Update Shikra CPUFREQ bindings + - cpufreq: qcom-cpufreq-hw: Update qcom,shikra-epss compatible + - soc: qcom: smsm: Add trace events + - net: wwan: qcom_bam_dmux: Add trace events + - FROMLIST: ACPI/AEST: Parse the AEST table + - FROMLIST: ras: AEST: Add probe/remove for AEST driver + - FROMLIST: ras: AEST: support different group format + - FROMLIST: ras: AEST: Unify the read/write interface for system and MMIO + register + - FROMLIST: ras: AEST: Probe RAS system architecture version + - FROMLIST: ras: AEST: Support RAS Common Fault Injection Model Extension + - FROMLIST: ras: AEST: Support CE threshold of error record + - FROMLIST: ras: AEST: Enable and register IRQs + - FROMLIST: ras: AEST: Add cpuhp callback + - FROMLIST: ras: AEST: Introduce AEST driver sysfs interface + - FROMLIST: ras: AEST: Add error count tracking and debugfs interface + - FROMLIST: ras: AEST: Allow configuring CE threshold via debugfs + - FROMLIST: ras: AEST: Introduce AEST inject interface to test AEST driver + - FROMLIST: ras: AEST: Add framework to process AEST vendor node + - FROMLIST: ras: AEST: support vendor node CMN700 + - FROMLIST: trace, ras: add ARM RAS extension trace event + - FROMLIST: ras: aest: Fix shared processor node handling and error log + messages + - FROMLIST: ras: aest: Fix CE/UE error counts not incrementing in debugfs + - FROMLIST: ras: aest: Skip unimplemented records in debugfs + - FROMLIST: ras: aest: Add panic_on_ue module parameter + - FROMLIST: dt-bindings: arm: ras: Introduce bindings for ARM AEST + - FROMLIST: ras: aest: Add DT frontend for ARM AEST RAS error sources + - FROMLIST: arm64: dts: qcom: monaco: add AEST error nodes + - FROMLIST: arm64: dts: qcom: purwa-iot-evk: Update TSENS thermal zone + - QCLINUX: arm64: dts: qcom: add Purwa CAMX EL2 overlay + - UPSTREAM: phy: qcom: m31-eusb2: Make USB repeater optional + - FROMLIST: clk: qcom: gcc-glymur: Move EVA clocks to critical clock list + - FROMLIST: dt-bindings: clock: qcom: Add EVA clock and reset controller + for Glymur SoC + - FROMLIST: clk: qcom: Add EVA clock controller driver for Glymur SoC + - arm64: dts: qcom: shikra-iqs-evk: Add DSI panel support + - FROMLIST: PCI/pwrctrl: Do not try to power on/off devices that don't + need pwrctrl + - WORKAROUND: phy: qcom: qmp-pcie: Add vdda-refgen and vdda-qref supplies + for Monaco + - WORKAROUND: arm64: dts: qcom: qcs8300-ride: Add vdda-qref and vdda- + refgen supplies for PCIe PHYs + - FROMLIST: arm64: dts: qcom: qcs615-ride: fix sdhc_2 vqmmc-supply for + UHS-I mode + - PENDING: arm64: dts: qcom: glymur-crd: Add FocalTech FT3D81 touchscreen + support + - arm64: dts: qcom: shikra-iqs-evk: Add pinctrl for DLC0697 DSI panel + - Revert "FROMLIST: media: qcom: venus: flip the venus/iris switch" + - FROMGIT: media: qcom: venus: flip the venus/iris switch + - FROMLIST: wifi: ath11k: raise max vdevs to 4 on hardware with P2P and + dual-station support + - FROMLIST: wifi: ath12k: fix inconsistent arvif state in vdev_create + error paths + - FROMLIST: wifi: ath12k: fix NULL deref in change_sta_links for unready + link + - arm64: dts: qcom: shikra: Add wcn3988-pmu node to EVK boards + - arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm + - arm64: dts: qcom: shikra: Fix wcn3988-pmu node on EVK boards + - drm/bridge: Add Lontium LT9611C(EX/UXD) MIPI DSI to HDMI driver + - drm/bridge: Enable LT9611UXD in LT9611C driver + - arm64: defconfig: Enable LT9611C bridge driver + - arm64: dts: qcom: shikra: Add GPU cooling + - QCLINUX: arm64: configs: enable USB configfs UVC and UAC2 functions + - Revert "arm64: dts: qcom: shikra-iqs-evk: Add pinctrl for DLC0697 DSI + panel" + - Revert "arm64: dts: qcom: shikra-iqs-evk: Add DSI panel support" + - arm64: dts: qcom: shikra: Add lt9611uxd node to IQS EVK board + - soc: qcom: llcc: Add configuration data for Shikra SoC + - FROMLIST: mmc: sdhci-msm: Set ice clk rate + - arm64: dts: qcom: shikra: migrate WiFi power control to pwrseq + - FROMLIST: serial: qcom_geni: Fix RX DMA stall when SE_DMA_RX_LEN_IN is + zero + - FROMLIST: arm64: dts: qcom: sm8750: add reboot-mode support + - PENDING: arm64: dts: qcom: shikra: add reboot-mode support + - FROMLIST: pci: quirks: Advertise D3cold capability for UPD720201 + - FROMLIST: usb: dwc3: qcom: Modify interrupt handling for eUSB2 Phy + targets + - QCLINUX: arm64: dts: qcom: Enable combo mode for CSI1 port + - QCLINUX: arm64: dts: qcom: Fix GPIO free and acquire logic + - FROMLIST: arm64: dts: qcom: kaanapali: Add SoCCP for Kaanapali SoC + - FROMLIST: arm64: dts: qcom: kaanapali-qrd: Add SoCCP node + - FROMLIST: arm64: dts: qcom: kaanapali-mtp: Add SoCCP node + - FROMLIST: arm64: dts: qcom: kaanapali: add reboot-mode support + - PENDING: arm64: dts: qcom: kaanapali: add Coresight ETR and routing in + staging dtso + - FROMLIST: dt-bindings: clock: qcom: Add bindings for PDM GP_MN clock + divider + - FROMLIST: clk: qcom: Add a driver for PDM GP_MN fractional clock divider + - PENDING: arm64: dts: qcom: hamoa: Enable CDSP cooling in staging dtso + - QCLINUX: arm64: dts: qcom: Change Purwa camera firmware path + - FROMLIST: scsi: ufs: core: Add UFSHCD_QUIRK_SKIP_DEVICE_RESET quirk + - FROMLIST: scsi: ufs: ufs-qcom: Enable SKIP DEVICE RESET Quirk + - arm64: dts: qcom: shikra: Split PMU nodes for heterogeneous CPUs + - arm64: dts: qcom: shikra: switch to interrupt-cells 4 to add PPI + partitions + - arm64: dts: qcom: shikra: add cache sizes and fix cpu3 power coefficient + - arm64: dts: qcom: shikra: add SCM clock and reset-cells to firmware node + - arm64: dts: qcom: shikra: fix memory node base address + - arm64: dts: qcom: shikra: drop unused labels from OPP table entries + - arm64: dts: qcom: shikra: fix LLCC interrupt number + - arm64: dts: qcom: shikra: fix qfprom base address and child offsets + - arm64: dts: qcom: shikra: fix sdhc_1 interconnect tags and power domain + - arm64: dts: qcom: shikra: remove spurious crypto interconnect path from + remoteprocs + - QCLINUX: dt-bindings: mailbox: qcom-ipcc: Add SAIL client IDs + - QCLINUX: arm64: dts: qcom: lemans: Add SAIL Mailbox device tree overlay + - dt-bindings: firmware: qcom,scm: complete shikra clock constraints + - pinctrl: qcom: shikra: align with upstream post-submission review + - QCLINUX: arm64: dts: qcom: Add Glymur crd camx overlay dts + - FROMLIST: arm64: dts: qcom: lemans: Enable audio over DISPLAY-PORT + - FROMLIST: arm64: dts: qcom: lemans-evk: Move SD card support to overlay + - FROMLIST: arm64: dts: qcom: lemans-evk: Add SDHCI support for eMMC via + overlay + - FROMLIST: arm64: dts: qcom: lemans: add AEST error nodes + - FROMLIST: fastrpc: Reduce log level for DSP info and reserved memory + messages + - FROMLIST: dt-bindings: iommu: arm,smmu: Document interconnects property + - FROMLIST: iommu/arm-smmu: Add interconnect bandwidth voting support + - FROMLIST: arm64: dts: qcom: kodiak: Add GEM_NOC interconnect for adreno + SMMU + - FROMLIST: arm64: dts: qcom: lemans: Add GEM_NOC interconnect for adreno + SMMU + - FROMLIST: arm64: dts: qcom: talos: Add GEM_NOC interconnect for adreno + SMMU + - FROMLIST: arm64: dts: qcom: monaco: Add GEM_NOC interconnect for adreno + SMMU + - Ubuntu: [Config] synchronize config after rebase - -- Kuba Pawlak Mon, 20 Jul 2026 14:05:14 +0200 + -- Kuba Pawlak Mon, 20 Jul 2026 14:05:26 +0200 linux-qcom (7.0.0-1008.11) resolute; urgency=medium From fd34bc4b263c2f18a11b8c4df5a968faa79e85b4 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Fri, 26 Jun 2026 16:32:09 +0800 Subject: [PATCH 1184/1330] Revert "FROMLIST: arm64: dts: qcom: purwa-iot-evk: Update TSENS thermal zone" This reverts commit a898eb1c745ea2b25b896985e9c211a66b4823d7. Signed-off-by: Yushan Li (cherry picked from commit a0c5d0a6b029efb4cb9f7379ae439fd51a152856) --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index 85b9175c54541..dca57f2db1fe1 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -1345,22 +1345,6 @@ }; }; -&gpuss0_alert0 { - temperature = <105000>; -}; - -&gpuss1_alert0 { - temperature = <105000>; -}; - -&gpuss2_alert0 { - temperature = <105000>; -}; - -&gpuss3_alert0 { - temperature = <105000>; -}; - &tlmm { edp_reg_en: edp-reg-en-state { pins = "gpio70"; From 77f1e3bb4b06ff5f589bed14d3b1e3bfebe78116 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:26 +0530 Subject: [PATCH 1185/1330] Revert "FROMLIST: media: iris: Add platform data for glymur" This reverts commit 03baa6bce8b33ed503b69e8d32cb39861d2643d8. Signed-off-by: Gourav Kumar (cherry picked from commit 7d8af5b9604ea9f4bac9d05c5ade5d4a28abebc6) (cherry picked from commit 6d149bf00a85e5f9b5978891261a2862341acc5c) --- drivers/media/platform/qcom/iris/Makefile | 1 - .../platform/qcom/iris/iris_platform_common.h | 5 -- .../platform/qcom/iris/iris_platform_glymur.c | 71 ------------------- .../platform/qcom/iris/iris_platform_glymur.h | 15 ---- .../platform/qcom/iris/iris_platform_vpu3x.c | 41 ++++++----- drivers/media/platform/qcom/iris/iris_probe.c | 4 -- 6 files changed, 22 insertions(+), 115 deletions(-) delete mode 100644 drivers/media/platform/qcom/iris/iris_platform_glymur.c delete mode 100644 drivers/media/platform/qcom/iris/iris_platform_glymur.h diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 8cdea242f7fdb..f8a017d878d62 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -12,7 +12,6 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_glymur.o \ iris_platform_vpu2.o \ iris_platform_vpu3x.o \ iris_platform_vpu4x.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 51af2e13fe526..d09edb02aeb6d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -29,10 +29,6 @@ struct iris_inst; #define DEFAULT_QP 20 #define BITRATE_DEFAULT 20000000 -#define VIDEO_REGION_SECURE_FW_REGION_ID 0 -#define VIDEO_REGION_VM0_SECURE_NP_ID 1 -#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 - enum stage_type { STAGE_1 = 1, STAGE_2 = 2, @@ -47,7 +43,6 @@ enum pipe_type { extern const struct iris_firmware_data iris_hfi_gen1_data; extern const struct iris_firmware_data iris_hfi_gen2_data; -extern const struct iris_platform_data glymur_data; extern const struct iris_platform_data kaanapali_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/drivers/media/platform/qcom/iris/iris_platform_glymur.c deleted file mode 100644 index 194431665e077..0000000000000 --- a/drivers/media/platform/qcom/iris/iris_platform_glymur.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include "iris_core.h" -#include "iris_platform_common.h" -#include "iris_platform_glymur.h" - -const struct platform_clk_data iris_glymur_clk_table[] = { - {IRIS_AXI_VCODEC_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_VCODEC_CLK, "vcodec0_core" }, - {IRIS_AXI_CTRL_CLK, "iface1" }, - {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, - {IRIS_AXI_VCODEC1_CLK, "iface2" }, - {IRIS_VCODEC1_CLK, "vcodec1_core" }, - {IRIS_VCODEC1_FREERUN_CLK, "vcodec1_core_freerun" }, -}; - -const char * const iris_glymur_clk_reset_table[] = { - "bus0", - "bus1", - "core", - "vcodec0_core", - "bus2", - "vcodec1_core", -}; - -const char * const iris_glymur_opp_clk_table[] = { - "vcodec0_core", - "vcodec1_core", - "core", - NULL, -}; - -const struct platform_pd_data iris_glymur_pmdomain_table = { - .pd_types = (enum platform_pm_domain_type []) { - IRIS_CTRL_POWER_DOMAIN, - IRIS_VCODEC_POWER_DOMAIN, - IRIS_VCODEC1_POWER_DOMAIN, - }, - .pd_names = (const char *[]) { - "venus", - "vcodec0", - "vcodec1", - }, - .pd_count = 3, -}; - -const struct tz_cp_config iris_glymur_tz_cp_config[] = { - { - .cp_start = VIDEO_REGION_SECURE_FW_REGION_ID, - .cp_size = 0, - .cp_nonpixel_start = 0, - .cp_nonpixel_size = 0x1000000, - }, - { - .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID, - .cp_size = 0, - .cp_nonpixel_start = 0x1000000, - .cp_nonpixel_size = 0x24800000, - }, - { - .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID, - .cp_size = 0, - .cp_nonpixel_start = 0x25800000, - .cp_nonpixel_size = 0xda600000, - }, -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/drivers/media/platform/qcom/iris/iris_platform_glymur.h deleted file mode 100644 index 875a3c65c58f1..0000000000000 --- a/drivers/media/platform/qcom/iris/iris_platform_glymur.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __IRIS_PLATFORM_GLYMUR_H__ -#define __IRIS_PLATFORM_GLYMUR_H__ - -extern const struct platform_clk_data iris_glymur_clk_table[9]; -extern const char * const iris_glymur_clk_reset_table[6]; -extern const char * const iris_glymur_opp_clk_table[4]; -extern const struct platform_pd_data iris_glymur_pmdomain_table; -extern const struct tz_cp_config iris_glymur_tz_cp_config[3]; - -#endif /* __IRIS_PLATFORM_GLYMUR_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index 42fad209b6bd3..1c511f72cf43c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -12,14 +12,13 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" -#include "iris_platform_glymur.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8550.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" #include "iris_platform_x1p42100.h" -static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { +const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, .fwname = "qcom/vpu/vpu30_p4_s6.mbn", @@ -181,33 +180,37 @@ static void sm8550_deinit_cb_devs(struct iris_core *core) core->dev_p = NULL; } -const struct iris_platform_data glymur_data = { - .firmware_desc_gen2 = &iris_vpu36_p4_s7_gen2_desc, - .vpu_ops = &iris_vpu36_ops, +/* + * Shares most of SM8550 data except: + * - inst_caps to platform_inst_cap_qcs8300 + */ +const struct iris_platform_data qcs8300_data = { + .firmware_desc = &iris_vpu30_p4_s6_gen2_desc, + .vpu_ops = &iris_vpu3_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), - .clk_rst_tbl = iris_glymur_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(iris_glymur_clk_reset_table), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = &iris_glymur_pmdomain_table, + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl = iris_glymur_clk_table, - .clk_tbl_size = ARRAY_SIZE(iris_glymur_clk_table), - .opp_clk_tbl = iris_glymur_opp_clk_table, + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ - .dma_mask = 0xffe00000 - 1, + .dma_mask = 0xe0000000 - 1, .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = iris_glymur_tz_cp_config, - .tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config), - .num_vpp_pipe = 4, + .inst_caps = &platform_inst_cap_qcs8300, + .tz_cp_config_data = tz_cp_config_vpu3, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), + .ubwc_config = &iris_ubwc_config_vpu3x, + .num_vpp_pipe = 2, .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((8192 * 4320) / 256) * 60, - .dual_core = true, + .max_core_mbpf = ((4096 * 2176) / 256) * 4, + .max_core_mbps = (((3840 * 2176) / 256) * 120), }; const struct iris_platform_data sm8550_data = { diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 359485bb9f936..b0d5993603482 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -372,10 +372,6 @@ static const struct dev_pm_ops iris_pm_ops = { }; static const struct of_device_id iris_dt_match[] = { - { - .compatible = "qcom,glymur-iris", - .data = &glymur_data, - }, { .compatible = "qcom,kaanapali-iris", .data = &kaanapali_data, From a7ac17c102cb345373b59088af5cf84e6438c3d3 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:31 +0530 Subject: [PATCH 1186/1330] Revert "FROMLIST: media: iris: Add support to select core for dual core platforms" This reverts commit 97f393da4fa1f35b428d27cacef556b31f48d7b8. Signed-off-by: Gourav Kumar (cherry picked from commit c2da1286089965d75e05889313875b91c9b15857) (cherry picked from commit a4e18d64906958f0189cdb962e287eff0018ae18) --- .../media/platform/qcom/iris/iris_common.c | 10 -- .../media/platform/qcom/iris/iris_common.h | 1 - drivers/media/platform/qcom/iris/iris_core.h | 7 -- .../platform/qcom/iris/iris_hfi_common.h | 1 - .../qcom/iris/iris_hfi_gen2_command.c | 19 ---- .../qcom/iris/iris_hfi_gen2_defines.h | 1 - .../media/platform/qcom/iris/iris_instance.h | 2 - .../platform/qcom/iris/iris_platform_common.h | 1 - drivers/media/platform/qcom/iris/iris_power.c | 11 +-- drivers/media/platform/qcom/iris/iris_utils.c | 91 ++++--------------- drivers/media/platform/qcom/iris/iris_vb2.c | 4 - drivers/media/platform/qcom/iris/iris_vidc.c | 6 +- 12 files changed, 23 insertions(+), 131 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media/platform/qcom/iris/iris_common.c index dade0273717a2..25836561bcf3e 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -46,16 +46,6 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) inst->metadata_idx++; } -int iris_set_core_id(struct iris_inst *inst) -{ - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; - - if (!inst->core->iris_platform_data->dual_core) - return 0; - - return hfi_ops->session_set_core_id(inst, inst->core_id); -} - int iris_process_streamon_input(struct iris_inst *inst) { const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; diff --git a/drivers/media/platform/qcom/iris/iris_common.h b/drivers/media/platform/qcom/iris/iris_common.h index 34e32c60f7687..b2a27b781c9ac 100644 --- a/drivers/media/platform/qcom/iris/iris_common.h +++ b/drivers/media/platform/qcom/iris/iris_common.h @@ -11,7 +11,6 @@ struct iris_buffer; int iris_vb2_buffer_to_driver(struct vb2_buffer *vb2, struct iris_buffer *buf); void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf); -int iris_set_core_id(struct iris_inst *inst); int iris_process_streamon_input(struct iris_inst *inst); int iris_process_streamon_output(struct iris_inst *inst); int iris_session_streamoff(struct iris_inst *inst, u32 plane); diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 1bc001df0cec4..abad04b7d475c 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -30,13 +30,6 @@ enum domain_type { DECODER = BIT(1), }; -struct qcom_ubwc_cfg_data; - -enum iris_vcodec_core_id { - IRIS_VCODEC0 = 1, - IRIS_VCODEC1, -}; - /** * struct iris_core - holds core parameters valid for all instances * diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 47786529998d5..a27447eb25199 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -131,7 +131,6 @@ struct iris_hfi_session_ops { int (*session_drain)(struct iris_inst *inst, u32 plane); int (*session_resume_drain)(struct iris_inst *inst, u32 plane); int (*session_close)(struct iris_inst *inst); - int (*session_set_core_id)(struct iris_inst *inst, u32 core_id); }; struct hfi_subscription_params { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 1d8b47e7164ee..7ac69af63eadb 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1291,24 +1291,6 @@ static int iris_hfi_gen2_session_release_buffer(struct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } -static int iris_hfi_gen2_set_core_id(struct iris_inst *inst, u32 core_id) -{ - struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst); - u32 payload = core_id; - - iris_hfi_gen2_packet_session_command(inst, - HFI_PROP_CORE_ID, - HFI_HOST_FLAGS_NONE, - HFI_PORT_NONE, - inst->session_id, - HFI_PAYLOAD_U32, - &payload, - sizeof(u32)); - - return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet, - inst_hfi_gen2->packet->size); -} - static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_open = iris_hfi_gen2_session_open, .session_set_config_params = iris_hfi_gen2_session_set_config_params, @@ -1322,7 +1304,6 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_drain = iris_hfi_gen2_session_drain, .session_resume_drain = iris_hfi_gen2_session_resume_drain, .session_close = iris_hfi_gen2_session_close, - .session_set_core_id = iris_hfi_gen2_set_core_id, }; static struct iris_inst *iris_hfi_gen2_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 600e9dc076690..cecf771c55dd3 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -56,7 +56,6 @@ #define HFI_PROP_BUFFER_HOST_MAX_COUNT 0x03000123 #define HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT 0x03000124 #define HFI_PROP_PIC_ORDER_CNT_TYPE 0x03000128 -#define HFI_PROP_CORE_ID 0x030001a9 enum hfi_rate_control { HFI_RC_VBR_CFR = 0x00000000, diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h index 99491513ee0de..9fa635e27a28d 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -39,7 +39,6 @@ struct iris_fmt { * * @list: used for attach an instance to the core * @core: pointer to core structure - * @core_id: specifies the hardware core on which the session runs * @session_id: id of current video session * @hfi_session_ops: iris HFI session ops * @ctx_q_lock: lock to serialize queues related ioctls @@ -85,7 +84,6 @@ struct iris_fmt { struct iris_inst { struct list_head list; struct iris_core *core; - u32 core_id; u32 session_id; const struct iris_hfi_session_ops *hfi_session_ops; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index d09edb02aeb6d..9be8c213729e2 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -301,7 +301,6 @@ struct iris_platform_data { u32 max_core_mbpf; /* max number of macroblocks per second supported */ u32 max_core_mbps; - bool dual_core; }; #endif diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/platform/qcom/iris/iris_power.c index 0e116c63f529d..91aa21d4070eb 100644 --- a/drivers/media/platform/qcom/iris/iris_power.c +++ b/drivers/media/platform/qcom/iris/iris_power.c @@ -77,9 +77,9 @@ static int iris_vote_interconnects(struct iris_inst *inst) static int iris_set_clocks(struct iris_inst *inst) { - u64 vcodec0_freq = 0, vcodec1_freq = 0; struct iris_core *core = inst->core; struct iris_inst *instance; + u64 freq = 0; int ret; mutex_lock(&core->lock); @@ -87,14 +87,11 @@ static int iris_set_clocks(struct iris_inst *inst) if (!instance->max_input_data_size) continue; - if (instance->core_id == IRIS_VCODEC0) - vcodec0_freq += instance->power.min_freq; - else if (instance->core_id == IRIS_VCODEC1) - vcodec1_freq += instance->power.min_freq; + freq += instance->power.min_freq; } - core->power.clk_freq = vcodec0_freq > vcodec1_freq ? vcodec0_freq : vcodec1_freq; - ret = iris_opp_set_rate(core->dev, core->power.clk_freq); + core->power.clk_freq = freq; + ret = iris_opp_set_rate(core->dev, freq); mutex_unlock(&core->lock); return ret; diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/platform/qcom/iris/iris_utils.c index 430b533078c3b..29b07d88507eb 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -87,95 +87,40 @@ struct iris_inst *iris_get_instance(struct iris_core *core, u32 session_id) return NULL; } -static u32 iris_get_mbps(struct iris_inst *inst) -{ - u32 fps = max(inst->frame_rate, inst->operating_rate); - - return iris_get_mbpf(inst) * fps; -} - -static void iris_get_core_load(struct iris_core *core, u32 *core_load, u32 *core_session, bool mbpf) -{ - bool dual_core = core->iris_platform_data->dual_core; - struct iris_inst *inst; - u32 load; - - core_load[0] = 0; - core_load[1] = 0; - core_session[0] = 0; - core_session[1] = 0; - - list_for_each_entry(inst, &core->instances, list) { - if (mbpf) - load = iris_get_mbpf(inst); - else - load = iris_get_mbps(inst); - - if (inst->core_id == IRIS_VCODEC0) { - core_load[0] += load; - core_session[0]++; - } else if (dual_core && inst->core_id == IRIS_VCODEC1) { - core_load[1] += load; - core_session[1]++; - } - } -} - -static int iris_select_core_id(struct iris_inst *inst, u32 *core_load, u32 *core_session, - u32 max_load, u32 new_load) -{ - u32 max_session = inst->core->iris_platform_data->max_session_count; - bool dual_core = inst->core->iris_platform_data->dual_core; - u32 core_index; - - core_index = (core_load[0] > core_load[1] && dual_core) ? 1 : 0; - - if (core_session[core_index] >= max_session) - core_index = core_index == 0 && dual_core ? 1 : 0; - - if (core_session[core_index] >= max_session) - return -ENOMEM; - - if (core_load[core_index] + new_load <= max_load) - inst->core_id = core_index == 0 ? IRIS_VCODEC0 : IRIS_VCODEC1; - else - return -ENOMEM; - - return 0; -} - int iris_check_core_mbpf(struct iris_inst *inst) { - u32 max_core_mbpf = inst->core->iris_platform_data->max_core_mbpf; - u32 core_mbpf[2], core_session[2], new_mbpf; struct iris_core *core = inst->core; - int ret; + struct iris_inst *instance; + u32 total_mbpf = 0; mutex_lock(&core->lock); - inst->core_id = 0; - iris_get_core_load(inst->core, core_mbpf, core_session, true); - new_mbpf = iris_get_mbpf(inst); - ret = iris_select_core_id(inst, core_mbpf, core_session, max_core_mbpf, new_mbpf); + list_for_each_entry(instance, &core->instances, list) + total_mbpf += iris_get_mbpf(instance); mutex_unlock(&core->lock); - return ret; + if (total_mbpf > core->iris_platform_data->max_core_mbpf) + return -ENOMEM; + + return 0; } int iris_check_core_mbps(struct iris_inst *inst) { - u32 max_core_mbps = inst->core->iris_platform_data->max_core_mbps; - u32 core_mbps[2] = {0, 0}, core_session[2], new_mbps; struct iris_core *core = inst->core; - int ret; + struct iris_inst *instance; + u32 total_mbps = 0, fps = 0; mutex_lock(&core->lock); - inst->core_id = 0; - iris_get_core_load(inst->core, core_mbps, core_session, false); - new_mbps = iris_get_mbps(inst); - ret = iris_select_core_id(inst, core_mbps, core_session, max_core_mbps, new_mbps); + list_for_each_entry(instance, &core->instances, list) { + fps = max(instance->frame_rate, instance->operating_rate); + total_mbps += iris_get_mbpf(instance) * fps; + } mutex_unlock(&core->lock); - return ret; + if (total_mbps > core->iris_platform_data->max_core_mbps) + return -ENOMEM; + + return 0; } bool is_rotation_90_or_270(struct iris_inst *inst) diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/platform/qcom/iris/iris_vb2.c index dbb89396e6514..a2ea2d67f60d0 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -176,10 +176,6 @@ int iris_vb2_start_streaming(struct vb2_queue *q, unsigned int count) if (ret) goto error; - ret = iris_set_core_id(inst); - if (ret) - goto error; - if (V4L2_TYPE_IS_OUTPUT(q->type)) { if (inst->domain == DECODER) ret = iris_vdec_streamon_input(inst); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index ae27d12a06b14..f805430ab4778 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -42,20 +42,16 @@ static void iris_v4l2_fh_deinit(struct iris_inst *inst, struct file *filp) static void iris_add_session(struct iris_inst *inst) { - u32 max_session_count = inst->core->iris_platform_data->max_session_count; struct iris_core *core = inst->core; struct iris_inst *iter; u32 count = 0; - if (inst->core->iris_platform_data->dual_core) - max_session_count *= 2; - mutex_lock(&core->lock); list_for_each_entry(iter, &core->instances, list) count++; - if (count < max_session_count) + if (count < core->iris_platform_data->max_session_count) list_add_tail(&inst->list, &core->instances); mutex_unlock(&core->lock); From d3da17c1cb88c269523f06ad1c20f2df4b8aca78 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:32 +0530 Subject: [PATCH 1187/1330] Revert "FROMLIST: media: iris: Add power sequence for Glymur" This reverts commit 428f03614bc404f2a3bdccf049a53e205ad6ee23. Signed-off-by: Gourav Kumar (cherry picked from commit 087010ae497e6e397d4ea57fb0f35afa2e276a8e) (cherry picked from commit fad359e7164a2bb243e0f6367651378620efa03e) --- .../platform/qcom/iris/iris_platform_common.h | 4 - drivers/media/platform/qcom/iris/iris_vpu3x.c | 137 ------------------ .../platform/qcom/iris/iris_vpu_common.h | 1 - .../qcom/iris/iris_vpu_register_defines.h | 7 - 4 files changed, 149 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 9be8c213729e2..bc88465f45b71 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -65,9 +65,6 @@ enum platform_clk_type { IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, IRIS_APV_HW_CLK, - IRIS_AXI_VCODEC1_CLK, - IRIS_VCODEC1_CLK, - IRIS_VCODEC1_FREERUN_CLK, }; struct platform_clk_data { @@ -206,7 +203,6 @@ enum platform_pm_domain_type { IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, - IRIS_VCODEC1_POWER_DOMAIN, }; struct iris_firmware_data { diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 60359d45ed981..91a9059941c1f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -27,16 +27,6 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) return pwr_status ? false : true; } -static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) -{ - u32 value, pwr_status; - - value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); - pwr_status = value & BIT(4); - - return !pwr_status; -} - static void iris_vpu3_power_off_hardware(struct iris_core *core) { u32 reg_val = 0, value, i; @@ -296,124 +286,6 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } -static int iris_vpu36_power_on_hw1(struct iris_core *core) -{ - int ret; - - ret = iris_enable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); - if (ret) - return ret; - - ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC1_CLK); - if (ret) - goto err_disable_hw1_power; - - ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_FREERUN_CLK); - if (ret) - goto err_disable_axi1_clk; - - ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_CLK); - if (ret) - goto err_disable_hw1_free_clk; - - return 0; - -err_disable_hw1_free_clk: - iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); -err_disable_axi1_clk: - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); -err_disable_hw1_power: - iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); - - return ret; -} - -static int iris_vpu36_power_on_hw(struct iris_core *core) -{ - int ret; - - ret = iris_vpu35_power_on_hw(core); - if (ret) - return ret; - - ret = iris_vpu36_power_on_hw1(core); - if (ret) - goto err_power_off_hw; - - return 0; - -err_power_off_hw: - iris_vpu35_power_off_hw(core); - - return ret; -} - -static void iris_vpu36_power_off_hw1(struct iris_core *core) -{ - u32 value, i; - int ret; - - if (iris_vpu36_hw1_power_collapsed(core)) - goto disable_power; - - value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); - if (value) - writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); - - for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { - ret = readl_poll_timeout(core->reg_base + VCODEC1_SS_IDLE_STATUSN + 4 * i, - value, value & DMA_NOC_IDLE, 2000, 20000); - if (ret) - goto disable_power; - } - - writel(REQ_VCODEC1_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); - ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, - value, value & NOC_LPI_VCODEC1_STATUS_DONE, 2000, 20000); - if (ret) - goto disable_power; - - writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); - - writel(VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + - CPU_CS_AHB_BRIDGE_SYNC_RESET); - writel(VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); - writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); - -disable_power: - iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, false); - iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK); - iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); - iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); -} - -static void iris_vpu36_power_off_hw(struct iris_core *core) -{ - iris_vpu35_power_off_hw(core); - iris_vpu36_power_off_hw1(core); -} - -static int iris_vpu36_set_hwmode(struct iris_core *core) -{ - int ret; - - ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); - if (ret) - return ret; - - ret = iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, true); - if (ret) - goto error_disable_hwmode; - - return 0; - -error_disable_hwmode: - iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false); - - return ret; -} - const struct vpu_ops iris_vpu3_ops = { .power_off_hw = iris_vpu3_power_off_hardware, .power_on_hw = iris_vpu_power_on_hw, @@ -450,12 +322,3 @@ const struct vpu_ops iris_vpu35_ops = { .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode = iris_vpu_set_hwmode, }; - -const struct vpu_ops iris_vpu36_ops = { - .power_off_hw = iris_vpu36_power_off_hw, - .power_on_hw = iris_vpu36_power_on_hw, - .power_off_controller = iris_vpu35_vpu4x_power_off_controller, - .power_on_controller = iris_vpu35_vpu4x_power_on_controller, - .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, - .set_hwmode = iris_vpu36_set_hwmode, -}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index c0b32ae9e1c6c..9d531fd8c3cc6 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,7 +13,6 @@ extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu3_purwa_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; -extern const struct vpu_ops iris_vpu36_ops; extern const struct vpu_ops iris_vpu4x_ops; struct vpu_ops { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index 37f234484f1b8..72168b9ffa738 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -7,7 +7,6 @@ #define __IRIS_VPU_REGISTER_DEFINES_H__ #define VCODEC_BASE_OFFS 0x00000000 -#define VCODEC1_BASE_OFFS 0x00040000 #define AON_MVP_NOC_RESET 0x0001F000 #define CPU_BASE_OFFS 0x000A0000 #define WRAPPER_BASE_OFFS 0x000B0000 @@ -15,8 +14,6 @@ #define AON_BASE_OFFS 0x000E0000 #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) -#define VCODEC1_SS_IDLE_STATUSN (VCODEC1_BASE_OFFS + 0x70) -#define DMA_NOC_IDLE BIT(22) #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) @@ -38,8 +35,6 @@ #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) #define CORE_BRIDGE_SW_RESET BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) -#define VCODEC1_BRIDGE_SW_RESET BIT(2) -#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(3) #define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) #define MSK_SIGNAL_FROM_TENSILICA BIT(0) @@ -57,13 +52,11 @@ #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) #define REQ_POWER_DOWN_PREP BIT(0) -#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1) #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) #define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ #define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ #define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ -#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8) #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) From e2e1775163e9611bf471c361d2b2129551ea3600 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:33 +0530 Subject: [PATCH 1188/1330] Revert "FROMLIST: media: iris: Use power domain type to look up pd_devs index" This reverts commit 36925cccb34ff533b792a73e151ba52cd2d5b167. Signed-off-by: Gourav Kumar (cherry picked from commit 88027f1da11f8b9c80b422ececcc477550072091) (cherry picked from commit 50bfdffa9c294e6a8e40cc5b98ad62d579299bf4) --- .../platform/qcom/iris/iris_platform_common.h | 9 +--- .../qcom/iris/iris_platform_kaanapali.h | 22 +++----- .../platform/qcom/iris/iris_platform_vpu2.c | 18 ++----- .../platform/qcom/iris/iris_platform_vpu3x.c | 27 ++++------ .../platform/qcom/iris/iris_platform_vpu4x.c | 3 +- drivers/media/platform/qcom/iris/iris_probe.c | 4 +- .../media/platform/qcom/iris/iris_resources.c | 44 +--------------- .../media/platform/qcom/iris/iris_resources.h | 6 +-- drivers/media/platform/qcom/iris/iris_vpu3x.c | 12 +++-- drivers/media/platform/qcom/iris/iris_vpu4x.c | 52 ++++++++++++------- .../platform/qcom/iris/iris_vpu_common.c | 23 ++++---- 11 files changed, 84 insertions(+), 136 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index bc88465f45b71..7c1b9fe0ddd99 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -257,12 +257,6 @@ struct iris_firmware_desc { const char *fwname; }; -struct platform_pd_data { - enum platform_pm_domain_type *pd_types; - const char **pd_names; - u32 pd_count; -}; - struct iris_platform_data { const struct iris_firmware_desc *firmware_desc_gen1, *firmware_desc_gen2; @@ -274,7 +268,8 @@ struct iris_platform_data { unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; unsigned int bw_tbl_dec_size; - const struct platform_pd_data *pmdomain_tbl; + const char * const *pmdomain_tbl; + unsigned int pmdomain_tbl_size; const char * const *opp_pd_tbl; unsigned int opp_pd_tbl_size; const struct platform_clk_data *clk_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h index cade13ce1985b..78c22be80f5c3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h @@ -16,22 +16,12 @@ static const char *const kaanapali_clk_reset_table[] = { "vcodec0_core_freerun_reset", }; -static const struct platform_pd_data kaanapali_pmdomain_table = { - .pd_types = (enum platform_pm_domain_type []) { - IRIS_CTRL_POWER_DOMAIN, - IRIS_VCODEC_POWER_DOMAIN, - IRIS_VPP0_HW_POWER_DOMAIN, - IRIS_VPP1_HW_POWER_DOMAIN, - IRIS_APV_HW_POWER_DOMAIN, - }, - .pd_names = (const char *[]) { - "venus", - "vcodec0", - "vpp0", - "vpp1", - "apv", - }, - .pd_count = 5, +static const char *const kaanapali_pmdomain_table[] = { + "venus", + "vcodec0", + "vpp0", + "vpp1", + "apv", }; static const struct platform_clk_data kaanapali_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 1105ff897fa10..4a020300bb794 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -68,17 +68,7 @@ static const struct icc_info iris_icc_info_vpu2[] = { static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" }; -static const struct platform_pd_data iris_pmdomain_table_vpu2 = { - .pd_types = (enum platform_pm_domain_type []) { - IRIS_CTRL_POWER_DOMAIN, - IRIS_VCODEC_POWER_DOMAIN, - }, - .pd_names = (const char *[]) { - "venus", - "vcodec0", - }, - .pd_count = 2, -}; +static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" }; static const struct tz_cp_config tz_cp_config_vpu2[] = { { @@ -97,7 +87,8 @@ const struct iris_platform_data sc7280_data = { .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), .bw_tbl_dec = sc7280_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl = &iris_pmdomain_table_vpu2, + .pmdomain_tbl = iris_pmdomain_table_vpu2, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), .opp_pd_tbl = sc7280_opp_pd_table, .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), .clk_tbl = sc7280_clk_table, @@ -127,7 +118,8 @@ const struct iris_platform_data sm8250_data = { .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2), .bw_tbl_dec = sm8250_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl = &iris_pmdomain_table_vpu2, + .pmdomain_tbl = iris_pmdomain_table_vpu2, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), .opp_pd_tbl = sm8250_opp_pd_table, .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), .clk_tbl = sm8250_clk_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index 1c511f72cf43c..59ac878a8ea9b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -73,17 +73,7 @@ static const struct bw_info iris_bw_table_dec_vpu3x[] = { { ((1920 * 1080) / 256) * 30, 294000 }, }; -static const struct platform_pd_data iris_pmdomain_table_vpu3x = { - .pd_types = (enum platform_pm_domain_type []) { - IRIS_CTRL_POWER_DOMAIN, - IRIS_VCODEC_POWER_DOMAIN, - }, - .pd_names = (const char *[]) { - "venus", - "vcodec0", - }, - .pd_count = 2, -}; +static const char * const iris_pmdomain_table_vpu3x[] = { "venus", "vcodec0" }; static const char * const iris_opp_pd_table_vpu3x[] = { "mxc", "mmcx" }; @@ -193,7 +183,8 @@ const struct iris_platform_data qcs8300_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = &iris_pmdomain_table_vpu3x, + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -224,7 +215,8 @@ const struct iris_platform_data sm8550_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = &iris_pmdomain_table_vpu3x, + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -260,7 +252,8 @@ const struct iris_platform_data sm8650_data = { .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = &iris_pmdomain_table_vpu3x, + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -288,7 +281,8 @@ const struct iris_platform_data sm8750_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = &iris_pmdomain_table_vpu3x, + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8750_clk_table, @@ -318,7 +312,8 @@ const struct iris_platform_data x1p42100_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = &iris_pmdomain_table_vpu3x, + .pmdomain_tbl = iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = x1p42100_clk_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c index 103aab2bb1044..a4b840c21634f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c @@ -75,7 +75,8 @@ const struct iris_platform_data kaanapali_data = { .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu4x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu4x), - .pmdomain_tbl = &kaanapali_pmdomain_table, + .pmdomain_tbl = kaanapali_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), .opp_pd_tbl = iris_opp_pd_table_vpu4x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu4x), .clk_tbl = kaanapali_clk_table, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index b0d5993603482..8c4b4750acd2b 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -44,8 +44,8 @@ static int iris_init_power_domains(struct iris_core *core) int ret; struct dev_pm_domain_attach_data iris_pd_data = { - .pd_names = core->iris_platform_data->pmdomain_tbl->pd_names, - .num_pd_names = core->iris_platform_data->pmdomain_tbl->pd_count, + .pd_names = core->iris_platform_data->pmdomain_tbl, + .num_pd_names = core->iris_platform_data->pmdomain_tbl_size, .pd_flags = PD_FLAG_NO_DEV_LINK, }; diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c index da783874cc1a4..b10884eb3ac64 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -72,43 +72,10 @@ int iris_opp_set_rate(struct device *dev, unsigned long freq) return dev_pm_opp_set_opp(dev, opp); } -static int iris_get_pd_index_by_type(struct iris_core *core, enum platform_pm_domain_type pd_type) +int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev) { - const struct platform_pd_data *pd_tbl; - u32 pd_count, i; - - pd_tbl = core->iris_platform_data->pmdomain_tbl; - pd_count = core->iris_platform_data->pmdomain_tbl->pd_count; - - for (i = 0; i < pd_count; i++) { - if (pd_tbl->pd_types[i] == pd_type) - return i; - } - - return -EINVAL; -} - -int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type, bool hwmode) -{ - int pd_index = iris_get_pd_index_by_type(core, pd_type); - - if (pd_index < 0) - return pd_index; - - return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[pd_index], hwmode); -} - -int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type) -{ - int pd_index = iris_get_pd_index_by_type(core, pd_type); - struct device *pd_dev; int ret; - if (pd_index < 0) - return pd_index; - - pd_dev = core->pmdomain_tbl->pd_devs[pd_index]; - ret = iris_opp_set_rate(core->dev, ULONG_MAX); if (ret) return ret; @@ -120,17 +87,10 @@ int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_ty return ret; } -int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type) +int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev) { - int pd_index = iris_get_pd_index_by_type(core, pd_type); - struct device *pd_dev; int ret; - if (pd_index < 0) - return pd_index; - - pd_dev = core->pmdomain_tbl->pd_devs[pd_index]; - ret = iris_opp_set_rate(core->dev, 0); if (ret) return ret; diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h index 8b46f036e9121..e6a6dc24a7f12 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -9,15 +9,13 @@ struct iris_core; int iris_opp_set_rate(struct device *dev, unsigned long freq); -int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type); -int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type); +int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev); +int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev); int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id); struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_type buffer_type); -int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type, - bool hwmode); #endif diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 91a9059941c1f..54aa079b2bd92 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -75,7 +75,8 @@ static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; @@ -92,7 +93,7 @@ static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } @@ -240,7 +241,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); disable_power: - iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); return 0; @@ -250,7 +251,8 @@ static int iris_vpu35_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; @@ -273,7 +275,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core) err_disable_axi_clk: iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c index bf7ad4e7cb8a4..92c0b06bbbff4 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -27,24 +27,28 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 { int ret; - ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, hw_mode); + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], + hw_mode); if (ret) return ret; if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret = iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, hw_mode); + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode); if (ret) goto restore_hw_domain_mode; } if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret = iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, hw_mode); + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode); if (ret) goto restore_vpp0_domain_mode; } if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { - ret = iris_genpd_set_hwmode(core, IRIS_APV_HW_POWER_DOMAIN, hw_mode); + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_APV_HW_POWER_DOMAIN], hw_mode); if (ret) goto restore_vpp1_domain_mode; } @@ -53,12 +57,14 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 restore_vpp1_domain_mode: if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, !hw_mode); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_DOMAIN], + !hw_mode); restore_vpp0_domain_mode: if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, !hw_mode); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN], + !hw_mode); restore_hw_domain_mode: - iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, !hw_mode); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode); return ret; } @@ -67,7 +73,8 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); if (ret) return ret; @@ -78,7 +85,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core) return 0; disable_apv_hw_power_domain: - iris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); return ret; } @@ -133,7 +140,7 @@ static void iris_vpu4x_power_off_apv(struct iris_core *core) disable_clocks_and_power: iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK); - iris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); } static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core) @@ -220,18 +227,21 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR); int ret; - ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret = iris_enable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); if (ret) goto disable_hw_power_domain; } if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret = iris_enable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); if (ret) goto disable_vpp0_power_domain; } @@ -252,12 +262,14 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) iris_vpu4x_disable_hardware_clocks(core, efuse_value); disable_vpp1_power_domain: if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); disable_vpp0_power_domain: if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); disable_hw_power_domain: - iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } @@ -328,12 +340,14 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core) iris_vpu4x_disable_hardware_clocks(core, efuse_value); if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); - iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); } static int iris_vpu4x_set_hwmode(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index c96c02862aeec..6b2e319a974a7 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -214,15 +214,15 @@ int iris_vpu_power_off_controller(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); - iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); return 0; } void iris_vpu_power_off_hw(struct iris_core *core) { - iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false); - iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); } @@ -243,7 +243,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; int ret; - ret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); if (ret) return ret; @@ -270,7 +270,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) err_disable_axi_clock: iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); return ret; } @@ -279,7 +279,8 @@ int iris_vpu_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; @@ -296,14 +297,14 @@ int iris_vpu_power_on_hw(struct iris_core *core) err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } int iris_vpu_set_hwmode(struct iris_core *core) { - return iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); + return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true); } int iris_vpu_switch_to_hwmode(struct iris_core *core) @@ -368,7 +369,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); - iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); reset_control_bulk_reset(clk_rst_tbl_size, core->resets); @@ -379,7 +380,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); if (ret) return ret; @@ -402,7 +403,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) err_disable_axi1_clk: iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); err_disable_power: - iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); return ret; } From a95bc6b77d88791d066ff253722f7e5909104171 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:34 +0530 Subject: [PATCH 1189/1330] Revert "FROMLIST: media: iris: Rename clock and power domain macros to use vcodec prefix" This reverts commit 43f8008081f008f27c417ffb4db6bfba11e37e17. Signed-off-by: Gourav Kumar (cherry picked from commit edfbdaedc237f2a1add4465acde2efb872a97440) (cherry picked from commit 23751a05dc9cdde8cb8398073062a51cfbca89b3) --- .../platform/qcom/iris/iris_platform_common.h | 12 +++---- .../qcom/iris/iris_platform_kaanapali.h | 20 +++++------ .../platform/qcom/iris/iris_platform_sc7280.h | 10 +++--- .../platform/qcom/iris/iris_platform_sm8250.h | 6 ++-- .../platform/qcom/iris/iris_platform_sm8550.h | 6 ++-- .../platform/qcom/iris/iris_platform_sm8750.h | 12 +++---- .../qcom/iris/iris_platform_x1p42100.h | 8 ++--- drivers/media/platform/qcom/iris/iris_vpu3x.c | 30 ++++++++--------- drivers/media/platform/qcom/iris/iris_vpu4x.c | 30 ++++++++--------- .../platform/qcom/iris/iris_vpu_common.c | 33 +++++++++---------- 10 files changed, 81 insertions(+), 86 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 7c1b9fe0ddd99..da4e799881c01 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -53,14 +53,14 @@ extern const struct iris_platform_data sm8750_data; extern const struct iris_platform_data x1p42100_data; enum platform_clk_type { - IRIS_AXI_VCODEC_CLK, + IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ IRIS_CTRL_CLK, IRIS_AHB_CLK, - IRIS_VCODEC_CLK, - IRIS_VCODEC_AHB_CLK, - IRIS_AXI_CTRL_CLK, + IRIS_HW_CLK, + IRIS_HW_AHB_CLK, + IRIS_AXI1_CLK, IRIS_CTRL_FREERUN_CLK, - IRIS_VCODEC_FREERUN_CLK, + IRIS_HW_FREERUN_CLK, IRIS_BSE_HW_CLK, IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, @@ -199,7 +199,7 @@ struct icc_vote_data { enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, - IRIS_VCODEC_POWER_DOMAIN, + IRIS_HW_POWER_DOMAIN, IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h index 78c22be80f5c3..247fb9d7cb632 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h @@ -25,16 +25,16 @@ static const char *const kaanapali_pmdomain_table[] = { }; static const struct platform_clk_data kaanapali_clk_table[] = { - {IRIS_AXI_VCODEC_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_VCODEC_CLK, "vcodec0_core" }, - {IRIS_AXI_CTRL_CLK, "iface1" }, - {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, - {IRIS_BSE_HW_CLK, "vcodec_bse" }, - {IRIS_VPP0_HW_CLK, "vcodec_vpp0" }, - {IRIS_VPP1_HW_CLK, "vcodec_vpp1" }, - {IRIS_APV_HW_CLK, "vcodec_apv" }, + { IRIS_AXI_CLK, "iface" }, + { IRIS_CTRL_CLK, "core" }, + { IRIS_HW_CLK, "vcodec0_core" }, + { IRIS_AXI1_CLK, "iface1" }, + { IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, + { IRIS_BSE_HW_CLK, "vcodec_bse" }, + { IRIS_VPP0_HW_CLK, "vcodec_vpp0" }, + { IRIS_VPP1_HW_CLK, "vcodec_vpp1" }, + { IRIS_APV_HW_CLK, "vcodec_apv" }, }; static const char *const kaanapali_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h index 6b783e524b819..0ec8f334df670 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -16,11 +16,11 @@ static const struct bw_info sc7280_bw_table_dec[] = { static const char * const sc7280_opp_pd_table[] = { "cx" }; static const struct platform_clk_data sc7280_clk_table[] = { - {IRIS_CTRL_CLK, "core" }, - {IRIS_AXI_VCODEC_CLK, "iface" }, - {IRIS_AHB_CLK, "bus" }, - {IRIS_VCODEC_CLK, "vcodec_core" }, - {IRIS_VCODEC_AHB_CLK, "vcodec_bus" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_HW_CLK, "vcodec_core" }, + {IRIS_HW_AHB_CLK, "vcodec_bus" }, }; static const char * const sc7280_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h index 964e1cd920860..50306043eb8ec 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -16,9 +16,9 @@ static const struct bw_info sm8250_bw_table_dec[] = { static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" }; static const struct platform_clk_data sm8250_clk_table[] = { - {IRIS_AXI_VCODEC_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, }; static const char * const sm8250_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h index 03a63904579e1..3c9dae995bb24 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -9,9 +9,9 @@ static const char * const sm8550_clk_reset_table[] = { "bus" }; static const struct platform_clk_data sm8550_clk_table[] = { - {IRIS_AXI_VCODEC_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, }; static struct platform_inst_caps platform_inst_cap_sm8550 = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h index f843f13251c5c..719056656a5ba 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h @@ -11,12 +11,12 @@ static const char * const sm8750_clk_reset_table[] = { }; static const struct platform_clk_data sm8750_clk_table[] = { - {IRIS_AXI_VCODEC_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_VCODEC_CLK, "vcodec0_core" }, - {IRIS_AXI_CTRL_CLK, "iface1" }, - {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI1_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, }; #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h index 2c0b0644cd5aa..d89acfbc1233d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h +++ b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h @@ -7,10 +7,10 @@ #define __IRIS_PLATFORM_X1P42100_H__ static const struct platform_clk_data x1p42100_clk_table[] = { - {IRIS_AXI_VCODEC_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_VCODEC_CLK, "vcodec0_core" }, - {IRIS_BSE_HW_CLK, "vcodec0_bse" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_BSE_HW_CLK, "vcodec0_bse" }, }; static const char *const x1p42100_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 54aa079b2bd92..5799e7e2aae2b 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -75,12 +75,11 @@ static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); if (ret) goto err_disable_power; @@ -91,9 +90,9 @@ static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) return 0; err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); return ret; } @@ -242,7 +241,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core) disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); return 0; } @@ -251,31 +250,30 @@ static int iris_vpu35_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); + ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); if (ret) goto err_disable_axi_clk; - ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); if (ret) goto err_disable_hw_free_clk; return 0; err_disable_hw_free_clk: - iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); err_disable_axi_clk: - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); return ret; } @@ -284,8 +282,8 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) { iris_vpu33_power_off_hardware(core); - iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); } const struct vpu_ops iris_vpu3_ops = { diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c index 92c0b06bbbff4..02e100a4045fc 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -27,8 +27,7 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 { int ret; - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], - hw_mode); + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode); if (ret) return ret; @@ -64,7 +63,7 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN], !hw_mode); restore_hw_domain_mode: - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode); return ret; } @@ -163,15 +162,15 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v { int ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); + ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); if (ret) goto disable_axi_clock; - ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); if (ret) goto disable_hw_free_run_clock; @@ -199,11 +198,11 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v disable_bse_hw_clock: iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); disable_hw_free_run_clock: - iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); return ret; } @@ -217,9 +216,9 @@ static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32 efuse iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); - iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); } static int iris_vpu4x_power_on_hardware(struct iris_core *core) @@ -227,8 +226,7 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR); int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); if (ret) return ret; @@ -269,7 +267,7 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs [IRIS_VPP0_HW_POWER_DOMAIN]); disable_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); return ret; } @@ -347,7 +345,7 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs [IRIS_VPP0_HW_POWER_DOMAIN]); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); } static int iris_vpu4x_set_hwmode(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 6b2e319a974a7..663f2af2c8385 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -213,7 +213,7 @@ int iris_vpu_power_off_controller(struct iris_core *core) disable_power: iris_disable_unprepare_clock(core, IRIS_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); return 0; @@ -221,10 +221,10 @@ int iris_vpu_power_off_controller(struct iris_core *core) void iris_vpu_power_off_hw(struct iris_core *core) { - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); - iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); } void iris_vpu_power_off(struct iris_core *core) @@ -251,7 +251,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); if (ret) goto err_disable_power; @@ -268,7 +268,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) err_disable_ctrl_clock: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); err_disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); @@ -279,32 +279,31 @@ int iris_vpu_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_VCODEC_AHB_CLK); + ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); if (ret && ret != -ENOENT) goto err_disable_hw_clock; return 0; err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); return ret; } int iris_vpu_set_hwmode(struct iris_core *core) { - return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true); + return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); } int iris_vpu_switch_to_hwmode(struct iris_core *core) @@ -367,7 +366,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) disable_power: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); @@ -384,7 +383,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CTRL_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK); if (ret) goto err_disable_power; @@ -401,7 +400,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) err_disable_ctrl_free_clk: iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); err_disable_axi1_clk: - iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); From d109d0d1b8366e0d4518d897f401beb57c303f0d Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:36 +0530 Subject: [PATCH 1190/1330] Revert "FROMLIST: media: iris: Fix VM count passed to firmware" This reverts commit a39682c0928d9d3f5a5f0f70d56f2118518f47ff. Signed-off-by: Gourav Kumar (cherry picked from commit e005c55eee6574b1536207e02bb6e2e053467d8d) (cherry picked from commit 87904e5d9faca89ffed849c8554a28a68b0084e1) --- drivers/media/platform/qcom/iris/iris_vpu_common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 663f2af2c8385..ca96e91222c67 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -78,6 +78,7 @@ int iris_vpu_boot_firmware(struct iris_core *core) iris_vpu_setup_ucregion_memory_map(core); writel(ctrl_init, core->reg_base + CTRL_INIT); + writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); while (!ctrl_status && count < max_tries) { ctrl_status = readl(core->reg_base + CTRL_STATUS); From 53fc8fde8f078f4373394df8d6aad1877fe0c726 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:37 +0530 Subject: [PATCH 1191/1330] Revert "FROMLIST: media: iris: Add platform data for X1P42100" This reverts commit 2119eda20561b0383f0bc3493d7908841132c916. Signed-off-by: Gourav Kumar (cherry picked from commit a3a27e08973a6c4f9a5206f418c5aa4aeb342cd4) (cherry picked from commit 3901510a411c8ca50f8ccf3466789f0b285d38f2) --- .../platform/qcom/iris/iris_platform_common.h | 1 - .../platform/qcom/iris/iris_platform_vpu3x.c | 32 ------------------- .../qcom/iris/iris_platform_x1p42100.h | 22 ------------- drivers/media/platform/qcom/iris/iris_probe.c | 4 --- 4 files changed, 59 deletions(-) delete mode 100644 drivers/media/platform/qcom/iris/iris_platform_x1p42100.h diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index da4e799881c01..22284d0e8b903 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -50,7 +50,6 @@ extern const struct iris_platform_data sm8250_data; extern const struct iris_platform_data sm8550_data; extern const struct iris_platform_data sm8650_data; extern const struct iris_platform_data sm8750_data; -extern const struct iris_platform_data x1p42100_data; enum platform_clk_type { IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index 59ac878a8ea9b..c6f5f7e27409d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -16,7 +16,6 @@ #include "iris_platform_sm8550.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" -#include "iris_platform_x1p42100.h" const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, @@ -300,34 +299,3 @@ const struct iris_platform_data sm8750_data = { .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, }; - -const struct iris_platform_data x1p42100_data = { - .firmware_desc_gen2 = &iris_vpu30_p4_gen2_desc, - .vpu_ops = &iris_vpu3_purwa_ops, - .init_cb_devs = sm8550_init_cb_devs, - .deinit_cb_devs = sm8550_deinit_cb_devs, - .icc_tbl = iris_icc_info_vpu3x, - .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), - .clk_rst_tbl = sm8550_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec = iris_bw_table_dec_vpu3x, - .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), - .opp_pd_tbl = iris_opp_pd_table_vpu3x, - .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl = x1p42100_clk_table, - .clk_tbl_size = ARRAY_SIZE(x1p42100_clk_table), - .opp_clk_tbl = x1p42100_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu3x_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_vpu3, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), - .num_vpp_pipe = 1, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h deleted file mode 100644 index d89acfbc1233d..0000000000000 --- a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#ifndef __IRIS_PLATFORM_X1P42100_H__ -#define __IRIS_PLATFORM_X1P42100_H__ - -static const struct platform_clk_data x1p42100_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, - {IRIS_BSE_HW_CLK, "vcodec0_bse" }, -}; - -static const char *const x1p42100_opp_clk_table[] = { - "vcodec0_core", - "vcodec0_bse", - NULL, -}; - -#endif diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 8c4b4750acd2b..d710fe4843960 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -400,10 +400,6 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,sm8750-iris", .data = &sm8750_data, }, - { - .compatible = "qcom,x1p42100-iris", - .data = &x1p42100_data, - }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match); From 0c88bcb503d67b875344195791b935f735f04133 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:38 +0530 Subject: [PATCH 1192/1330] Revert "FROMLIST: media: iris: Add hardware power on/off ops for X1P42100" This reverts commit eb72f02882913936d3b055b7fb56bc85dcc0eb52. Signed-off-by: Gourav Kumar (cherry picked from commit 58cfd196bf19e528b041d7c67bbade6120e0d189) (cherry picked from commit bfeb948159f13e3d08987c37d63c638e93f04f1f) --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 41 ------------------- .../platform/qcom/iris/iris_vpu_common.h | 1 - 2 files changed, 42 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 5799e7e2aae2b..3dad47be78b58 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -71,38 +71,6 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) iris_vpu_power_off_hw(core); } -static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) -{ - int ret; - - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); - if (ret) - return ret; - - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); - if (ret) - goto err_disable_power; - - ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); - if (ret) - goto err_disable_hw_clock; - - return 0; - -err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); -err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); - - return ret; -} - -static void iris_vpu3_purwa_power_off_hardware(struct iris_core *core) -{ - iris_vpu3_power_off_hardware(core); - iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); -} - static void iris_vpu33_power_off_hardware(struct iris_core *core) { bool handshake_done = false, handshake_busy = false; @@ -295,15 +263,6 @@ const struct vpu_ops iris_vpu3_ops = { .set_hwmode = iris_vpu_set_hwmode, }; -const struct vpu_ops iris_vpu3_purwa_ops = { - .power_off_hw = iris_vpu3_purwa_power_off_hardware, - .power_on_hw = iris_vpu3_purwa_power_on_hw, - .power_off_controller = iris_vpu_power_off_controller, - .power_on_controller = iris_vpu_power_on_controller, - .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, - .set_hwmode = iris_vpu_set_hwmode, -}; - const struct vpu_ops iris_vpu33_ops = { .power_off_hw = iris_vpu33_power_off_hardware, .power_on_hw = iris_vpu_power_on_hw, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index 9d531fd8c3cc6..09799a375c142 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,7 +10,6 @@ struct iris_core; extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; -extern const struct vpu_ops iris_vpu3_purwa_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; extern const struct vpu_ops iris_vpu4x_ops; From 3592ad8045116fe5973829cdcc5e0f3599631b0f Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:39 +0530 Subject: [PATCH 1193/1330] Revert "FROMLIST: media: qcom: iris: extract firmware description data" This reverts commit 4224b95f63cd71c565a4bdb0b97ced98f943d83b. Signed-off-by: Gourav Kumar (cherry picked from commit 0ba9eb0dbf87a26ec5de3d1860a5d65853d69447) (cherry picked from commit 88b95d2b8a6ff59891e1ccfd866ef9e3cc42c708) --- .../media/platform/qcom/iris/iris_buffer.c | 2 +- drivers/media/platform/qcom/iris/iris_core.h | 4 -- .../media/platform/qcom/iris/iris_firmware.c | 7 +++- .../qcom/iris/iris_hfi_gen1_command.c | 2 +- .../platform/qcom/iris/iris_platform_common.h | 13 +++--- .../platform/qcom/iris/iris_platform_vpu2.c | 27 +++--------- .../platform/qcom/iris/iris_platform_vpu3x.c | 41 ++++++------------- .../platform/qcom/iris/iris_platform_vpu4x.c | 10 ++--- drivers/media/platform/qcom/iris/iris_probe.c | 5 +-- 9 files changed, 38 insertions(+), 73 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 32b941c10cd96..762cdbf728b07 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -295,7 +295,7 @@ static void iris_fill_internal_buf_info(struct iris_inst *inst, { struct iris_buffers *buffers = &inst->buffers[buffer_type]; - buffers->size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, buffer_type); + buffers->size = inst->core->iris_platform_data->get_vpu_buffer_size(inst, buffer_type); buffers->min_count = iris_vpu_buf_count(inst, buffer_type); } diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index abad04b7d475c..7d128e7724ed1 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -56,8 +56,6 @@ enum domain_type { * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data * @iris_firmware_data: a pointer to the firmware (or HFI) specific data - * @iris_firmware_desc: a pointer to the firmware-specific descriptive data - * @ubwc_cfg: UBWC configuration for the platform * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory @@ -109,8 +107,6 @@ struct iris_core { struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; const struct iris_firmware_data *iris_firmware_data; - const struct iris_firmware_desc *iris_firmware_desc; - const struct qcom_ubwc_cfg_data *ubwc_cfg; enum iris_core_state state; dma_addr_t iface_q_table_daddr; dma_addr_t sfr_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index 86ab578a4ec87..ec8e5d0d55985 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -170,7 +170,12 @@ int iris_fw_load(struct iris_core *core) const struct tz_cp_config *cp_config; int i, ret; - ret = iris_load_fw_to_memory(core); + ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0, + &fwpath); + if (ret) + fwpath = core->iris_platform_data->fwname; + + ret = iris_load_fw_to_memory(core, fwpath); if (ret) { dev_err(core->dev, "firmware download failed %d\n", ret); return ret; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 83373862655f7..3fb90a466a64e 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -918,7 +918,7 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst *inst, u32 plane) if (iris_split_mode_enabled(inst)) { bufsz.type = HFI_BUFFER_OUTPUT; - bufsz.size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, BUF_DPB); + bufsz.size = inst->core->iris_platform_data->get_vpu_buffer_size(inst, BUF_DPB); ret = hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz)); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 22284d0e8b903..53ae4d6b47e62 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -250,14 +250,14 @@ struct iris_firmware_data { unsigned int enc_op_int_buf_tbl_size; }; -struct iris_firmware_desc { +struct iris_platform_data { + /* + * XXX: remove firmware_data pointer and consider moving + * get_vpu_buffer_size pointer once we have platforms supporting both + * firmware kinds. + */ const struct iris_firmware_data *firmware_data; u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); - const char *fwname; -}; - -struct iris_platform_data { - const struct iris_firmware_desc *firmware_desc_gen1, *firmware_desc_gen2; const struct vpu_ops *vpu_ops; @@ -279,6 +279,7 @@ struct iris_platform_data { const char * const *controller_rst_tbl; unsigned int controller_rst_tbl_size; u64 dma_mask; + const char *fwname; struct iris_fmt *inst_iris_fmts; u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 4a020300bb794..692fbc2aab564 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -16,24 +16,6 @@ #include "iris_platform_sc7280.h" #include "iris_platform_sm8250.h" -static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .fwname = "qcom/vpu/vpu20_p1.mbn", -}; - -static const struct iris_firmware_desc iris_vpu20_p1_gen2_s6_desc = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, - .fwname = "qcom/vpu/vpu20_p1_gen2_s6.mbn", -}; - -static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .fwname = "qcom/vpu/vpu20_p4.mbn", -}; - static struct iris_fmt iris_fmts_vpu2_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -80,8 +62,8 @@ static const struct tz_cp_config tz_cp_config_vpu2[] = { }; const struct iris_platform_data sc7280_data = { - .firmware_desc_gen1 = &iris_vpu20_p1_gen1_desc, - .firmware_desc_gen2 = &iris_vpu20_p1_gen2_s6_desc, + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), @@ -96,6 +78,7 @@ const struct iris_platform_data sc7280_data = { .opp_clk_tbl = sc7280_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu20_p1.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, @@ -110,7 +93,8 @@ const struct iris_platform_data sc7280_data = { }; const struct iris_platform_data sm8250_data = { - .firmware_desc_gen1 = &iris_vpu20_p4_gen1_desc, + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), @@ -127,6 +111,7 @@ const struct iris_platform_data sm8250_data = { .opp_clk_tbl = sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu20_p4.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index c6f5f7e27409d..cbd13a2e09b1b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -17,30 +17,6 @@ #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" -const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .fwname = "qcom/vpu/vpu30_p4_s6.mbn", -}; - -static const struct iris_firmware_desc iris_vpu30_p4_gen2_desc = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .fwname = "qcom/vpu/vpu30_p4.mbn", -}; - -static const struct iris_firmware_desc iris_vpu33_p4_gen2_desc = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, - .fwname = "qcom/vpu/vpu33_p4.mbn", -}; - -static const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, - .fwname = "qcom/vpu/vpu35_p4.mbn", -}; - static struct iris_fmt iris_fmts_vpu3x_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -174,7 +150,8 @@ static void sm8550_deinit_cb_devs(struct iris_core *core) * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .firmware_desc = &iris_vpu30_p4_s6_gen2_desc, + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -191,6 +168,7 @@ const struct iris_platform_data qcs8300_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu30_p4_s6.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_qcs8300, @@ -204,7 +182,8 @@ const struct iris_platform_data qcs8300_data = { }; const struct iris_platform_data sm8550_data = { - .firmware_desc_gen2 = &iris_vpu30_p4_gen2_desc, + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .init_cb_devs = sm8550_init_cb_devs, .deinit_cb_devs = sm8550_deinit_cb_devs, @@ -223,6 +202,7 @@ const struct iris_platform_data sm8550_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu30_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -239,9 +219,11 @@ const struct iris_platform_data sm8550_data = { * - vpu_ops to iris_vpu33_ops * - clk_rst_tbl to sm8650_clk_reset_table * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { - .firmware_desc_gen2 = &iris_vpu33_p4_gen2_desc, + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -260,6 +242,7 @@ const struct iris_platform_data sm8650_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu33_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -272,7 +255,8 @@ const struct iris_platform_data sm8650_data = { }; const struct iris_platform_data sm8750_data = { - .firmware_desc_gen2 = &iris_vpu35_p4_gen2_desc, + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -289,6 +273,7 @@ const struct iris_platform_data sm8750_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu35_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c index a4b840c21634f..02f8399e64759 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c @@ -14,12 +14,6 @@ #include "iris_platform_kaanapali.h" -const struct iris_firmware_desc iris_vpu40_p2_s7_gen2_desc = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu4x_buf_size, - .fwname = "qcom/vpu/vpu40_p2_s7.mbn", -}; - static struct iris_fmt iris_fmts_vpu4x_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -67,7 +61,8 @@ static struct platform_inst_caps iris_inst_cap_vpu4x = { }; const struct iris_platform_data kaanapali_data = { - .firmware_desc_gen2 = &iris_vpu40_p2_s7_gen2_desc, + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu4x_buf_size, .vpu_ops = &iris_vpu4x_ops, .icc_tbl = iris_icc_info_vpu4x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu4x), @@ -84,6 +79,7 @@ const struct iris_platform_data kaanapali_data = { .opp_clk_tbl = kaanapali_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu40_p2_s7.mbn", .inst_iris_fmts = iris_fmts_vpu4x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu4x_dec), .inst_caps = &iris_inst_cap_vpu4x, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index d710fe4843960..5f4046e72955c 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -259,10 +259,7 @@ static int iris_probe(struct platform_device *pdev) return core->irq; core->iris_platform_data = of_device_get_match_data(core->dev); - - core->ubwc_cfg = qcom_ubwc_config_get_data(); - if (IS_ERR(core->ubwc_cfg)) - return PTR_ERR(core->ubwc_cfg); + core->iris_firmware_data = core->iris_platform_data->firmware_data; ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr, iris_hfi_isr_handler, IRQF_TRIGGER_HIGH, "iris", core); From 4b35db12b7c7d82869b637679fb7e7951e81b15b Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:40 +0530 Subject: [PATCH 1194/1330] Revert "FROMLIST: media: qcom: iris: use new firmware name for SM8250" This reverts commit 10f101b3273a0101bb28d6c35d3dfb0503d1c287. Signed-off-by: Gourav Kumar (cherry picked from commit d04a6c04534012d160bded975b58ba70cd1b64ee) (cherry picked from commit 9c2dd557b20e21a11f505565103c31dcc68824cd) --- drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 692fbc2aab564..ab2a19aa9c36c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -111,7 +111,7 @@ const struct iris_platform_data sm8250_data = { .opp_clk_tbl = sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu20_p4.mbn", + .fwname = "qcom/vpu-1.0/venus.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, From ae6e61f9f5aaa31c541c3da1d5aeddf89b29f55f Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:42 +0530 Subject: [PATCH 1195/1330] Revert "FROMLIST: media: qcom: iris: split platform data from firmware data" This reverts commit 2cb6e86f15f02e0786578fbed65732ecb4ac4655. Signed-off-by: Gourav Kumar (cherry picked from commit 1b49a28327d3b4ef87e9dc0ba159c8e4267b689e) (cherry picked from commit bbeff782f1646a70af877c3e6a8d7deffb556fe3) --- drivers/media/platform/qcom/iris/Makefile | 7 +- .../platform/qcom/iris/iris_platform_common.h | 3 - .../{iris_hfi_gen1.c => iris_platform_gen1.c} | 134 ++++++++ .../{iris_hfi_gen2.c => iris_platform_gen2.c} | 304 ++++++++++++++++++ .../platform/qcom/iris/iris_platform_sm8250.h | 29 -- .../platform/qcom/iris/iris_platform_vpu2.c | 124 ------- 6 files changed, 440 insertions(+), 161 deletions(-) rename drivers/media/platform/qcom/iris/{iris_hfi_gen1.c => iris_platform_gen1.c} (67%) rename drivers/media/platform/qcom/iris/{iris_hfi_gen2.c => iris_platform_gen2.c} (71%) delete mode 100644 drivers/media/platform/qcom/iris/iris_platform_sm8250.h delete mode 100644 drivers/media/platform/qcom/iris/iris_platform_vpu2.c diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index f8a017d878d62..2fde45f817276 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -4,17 +4,14 @@ qcom-iris-objs += iris_buffer.o \ iris_ctrls.o \ iris_firmware.o \ iris_hfi_common.o \ - iris_hfi_gen1.o \ iris_hfi_gen1_command.o \ iris_hfi_gen1_response.o \ - iris_hfi_gen2.o \ iris_hfi_gen2_command.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_vpu2.o \ - iris_platform_vpu3x.o \ - iris_platform_vpu4x.o \ + iris_platform_gen1.o \ + iris_platform_gen2.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 53ae4d6b47e62..1dc3817b22b73 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -40,9 +40,6 @@ enum pipe_type { PIPE_4 = 4, }; -extern const struct iris_firmware_data iris_hfi_gen1_data; -extern const struct iris_firmware_data iris_hfi_gen2_data; - extern const struct iris_platform_data kaanapali_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c similarity index 67% rename from drivers/media/platform/qcom/iris/iris_hfi_gen1.c rename to drivers/media/platform/qcom/iris/iris_platform_gen1.c index 60f51a1ba9412..9e632a973f476 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -3,16 +3,38 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include "iris_core.h" #include "iris_ctrls.h" #include "iris_platform_common.h" +#include "iris_resources.h" #include "iris_hfi_gen1.h" #include "iris_hfi_gen1_defines.h" #include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" +#include "iris_instance.h" + +#include "iris_platform_sc7280.h" #define BITRATE_MIN 32000 #define BITRATE_MAX 160000000 +#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 +static struct iris_fmt platform_fmts_sm8250_dec[] = { + [IRIS_FMT_H264] = { + .pixfmt = V4L2_PIX_FMT_H264, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] = { + .pixfmt = V4L2_PIX_FMT_HEVC, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] = { + .pixfmt = V4L2_PIX_FMT_VP9, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = { { .cap_id = PIPE, @@ -226,6 +248,56 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = { }, }; +static struct platform_inst_caps platform_inst_cap_sm8250 = { + .min_frame_width = 128, + .max_frame_width = 8192, + .min_frame_height = 128, + .max_frame_height = 8192, + .max_mbpf = 138240, + .mb_cycles_vsp = 25, + .mb_cycles_vpp = 200, + .max_frame_rate = MAXIMUM_FPS, + .max_operating_rate = MAXIMUM_FPS, +}; + +static const struct icc_info sm8250_icc_table[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const sm8250_clk_reset_table[] = { "bus", "core" }; + +static const struct bw_info sm8250_bw_table_dec[] = { + { ((4096 * 2160) / 256) * 60, 2403000 }, + { ((4096 * 2160) / 256) * 30, 1224000 }, + { ((1920 * 1080) / 256) * 60, 812000 }, + { ((1920 * 1080) / 256) * 30, 416000 }, +}; + +static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" }; + +static const char * const sm8250_opp_pd_table[] = { "mx" }; + +static const struct platform_clk_data sm8250_clk_table[] = { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static const char * const sm8250_opp_clk_table[] = { + "vcodec0_core", + NULL, +}; + +static const struct tz_cp_config tz_cp_config_sm8250[] = { + { + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x01000000, + .cp_nonpixel_size = 0x24800000, + }, +}; + static const u32 sm8250_vdec_input_config_param_default[] = { HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, @@ -284,3 +356,65 @@ const struct iris_firmware_data iris_hfi_gen1_data = { .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; + +const struct iris_platform_data sm8250_data = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu2_ops, + .icc_tbl = sm8250_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), + .clk_rst_tbl = sm8250_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table), + .bw_tbl_dec = sm8250_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), + .pmdomain_tbl = sm8250_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table), + .opp_pd_tbl = sm8250_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), + .clk_tbl = sm8250_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table), + .opp_clk_tbl = sm8250_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu-1.0/venus.mbn", + .inst_iris_fmts = platform_fmts_sm8250_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), + .inst_caps = &platform_inst_cap_sm8250, + .tz_cp_config_data = tz_cp_config_sm8250, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; + +const struct iris_platform_data sc7280_data = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu2_ops, + .icc_tbl = sm8250_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), + .bw_tbl_dec = sc7280_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), + .pmdomain_tbl = sm8250_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table), + .opp_pd_tbl = sc7280_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), + .clk_tbl = sc7280_clk_table, + .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table), + .opp_clk_tbl = sc7280_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu20_p1.mbn", + .inst_iris_fmts = platform_fmts_sm8250_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), + .inst_caps = &platform_inst_cap_sm8250, + .tz_cp_config_data = tz_cp_config_sm8250, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), + .num_vpp_pipe = 1, + .no_aon = true, + .max_session_count = 16, + .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, + /* max spec for SC7280 is 4096x2176@60fps */ + .max_core_mbps = 4096 * 2176 / 256 * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c similarity index 71% rename from drivers/media/platform/qcom/iris/iris_hfi_gen2.c rename to drivers/media/platform/qcom/iris/iris_platform_gen2.c index ce8490d64854c..b83a2af4cb7d4 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -4,15 +4,41 @@ * Copyright (c) 2025 Linaro Ltd */ +#include "iris_core.h" #include "iris_ctrls.h" #include "iris_hfi_gen2.h" #include "iris_hfi_gen2_defines.h" #include "iris_platform_common.h" #include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#include "iris_platform_kaanapali.h" +#include "iris_platform_qcs8300.h" +#include "iris_platform_sm8650.h" +#include "iris_platform_sm8750.h" #define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 +static struct iris_fmt platform_fmts_sm8550_dec[] = { + [IRIS_FMT_H264] = { + .pixfmt = V4L2_PIX_FMT_H264, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] = { + .pixfmt = V4L2_PIX_FMT_HEVC, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] = { + .pixfmt = V4L2_PIX_FMT_VP9, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_AV1] = { + .pixfmt = V4L2_PIX_FMT_AV1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = { { .cap_id = PROFILE_H264, @@ -717,6 +743,109 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = { }, }; +static struct platform_inst_caps platform_inst_cap_sm8550 = { + .min_frame_width = 96, + .max_frame_width = 8192, + .min_frame_height = 96, + .max_frame_height = 8192, + .max_mbpf = (8192 * 4352) / 256, + .mb_cycles_vpp = 200, + .mb_cycles_fw = 489583, + .mb_cycles_fw_vpp = 66234, + .num_comv = 0, + .max_frame_rate = MAXIMUM_FPS, + .max_operating_rate = MAXIMUM_FPS, +}; + +static int sm8550_init_cb_devs(struct iris_core *core) +{ + const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ + const u32 f_id_p = 1; /* IRIS_PIXEL */ + struct device *dev; + + dev = iris_create_cb_dev(core, "iris_non_pixel", &f_id_np); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + core->dev_np = dev; + core->dev_bs = core->dev_np; + + dev = iris_create_cb_dev(core, "iris_pixel", &f_id_p); + if (IS_ERR(dev)) + goto err_unreg_dev_np; + + core->dev_p = dev; + + return 0; + +err_unreg_dev_np: + platform_device_unregister(to_platform_device(core->dev_np)); + core->dev_np = NULL; + core->dev_bs = NULL; + + return PTR_ERR(dev); +} + +static void sm8550_deinit_cb_devs(struct iris_core *core) +{ + if (core->dev_np) + platform_device_unregister(to_platform_device(core->dev_np)); + if (core->dev_p) + platform_device_unregister(to_platform_device(core->dev_p)); + + core->dev_np = NULL; + core->dev_bs = NULL; + core->dev_p = NULL; +} + +static const struct icc_info sm8550_icc_table[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const sm8550_clk_reset_table[] = { "bus" }; + +static const struct bw_info sm8550_bw_table_dec[] = { + { ((4096 * 2160) / 256) * 60, 1608000 }, + { ((4096 * 2160) / 256) * 30, 826000 }, + { ((1920 * 1080) / 256) * 60, 567000 }, + { ((1920 * 1080) / 256) * 30, 294000 }, +}; + +static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" }; + +static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" }; + +static const struct platform_clk_data sm8550_clk_table[] = { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static const char * const sm8550_opp_clk_table[] = { + "vcodec0_core", + NULL, +}; + +static struct ubwc_config_data ubwc_config_sm8550 = { + .max_channels = 8, + .mal_length = 32, + .highest_bank_bit = 16, + .bank_swzl_level = 0, + .bank_swz2_level = 1, + .bank_swz3_level = 1, + .bank_spreading = 1, +}; + +static const struct tz_cp_config tz_cp_config_sm8550[] = { + { + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x01000000, + .cp_nonpixel_size = 0x24800000, + }, +}; + static const u32 sm8550_vdec_input_config_params_default[] = { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, @@ -894,3 +1023,178 @@ const struct iris_firmware_data iris_hfi_gen2_data = { .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; + +const struct iris_platform_data kaanapali_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu4x_buf_size, + .vpu_ops = &iris_vpu4x_ops, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = kaanapali_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = kaanapali_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = kaanapali_clk_table, + .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), + .opp_clk_tbl = kaanapali_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu40_p2_s7.mbn", + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_kaanapali, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 2, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4352) / 256) * 60, +}; + +const struct iris_platform_data sm8550_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu3_ops, + .init_cb_devs = sm8550_init_cb_devs, + .deinit_cb_devs = sm8550_deinit_cb_devs, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = sm8550_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_sm8550, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +const struct iris_platform_data sm8650_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .vpu_ops = &iris_vpu33_ops, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = sm8650_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl = sm8650_controller_reset_table, + .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = sm8550_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu33_p4.mbn", + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_sm8550, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; + +const struct iris_platform_data sm8750_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .vpu_ops = &iris_vpu35_ops, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = sm8750_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = sm8550_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = sm8750_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table), + .opp_clk_tbl = sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu35_p4.mbn", + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_sm8550, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; + +/* + * Shares most of SM8550 data except: + * - inst_caps to platform_inst_cap_qcs8300 + */ +const struct iris_platform_data qcs8300_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu3_ops, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = sm8550_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu30_p4_s6.mbn", + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_qcs8300, + .tz_cp_config_data = tz_cp_config_sm8550, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 2, + .max_session_count = 16, + .max_core_mbpf = ((4096 * 2176) / 256) * 4, + .max_core_mbps = (((3840 * 2176) / 256) * 120), +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h deleted file mode 100644 index 50306043eb8ec..0000000000000 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#ifndef __IRIS_PLATFORM_SM8250_H__ -#define __IRIS_PLATFORM_SM8250_H__ - -static const struct bw_info sm8250_bw_table_dec[] = { - { ((4096 * 2160) / 256) * 60, 2403000 }, - { ((4096 * 2160) / 256) * 30, 1224000 }, - { ((1920 * 1080) / 256) * 60, 812000 }, - { ((1920 * 1080) / 256) * 30, 416000 }, -}; - -static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" }; - -static const struct platform_clk_data sm8250_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8250_opp_clk_table[] = { - "vcodec0_core", - NULL, -}; - -#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c deleted file mode 100644 index ab2a19aa9c36c..0000000000000 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include "iris_core.h" -#include "iris_ctrls.h" -#include "iris_platform_common.h" -#include "iris_resources.h" -#include "iris_hfi_gen1.h" -#include "iris_hfi_gen1_defines.h" -#include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" -#include "iris_instance.h" - -#include "iris_platform_sc7280.h" -#include "iris_platform_sm8250.h" - -static struct iris_fmt iris_fmts_vpu2_dec[] = { - [IRIS_FMT_H264] = { - .pixfmt = V4L2_PIX_FMT_H264, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] = { - .pixfmt = V4L2_PIX_FMT_HEVC, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] = { - .pixfmt = V4L2_PIX_FMT_VP9, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - -static struct platform_inst_caps platform_inst_cap_vpu2 = { - .min_frame_width = 128, - .max_frame_width = 8192, - .min_frame_height = 128, - .max_frame_height = 8192, - .max_mbpf = 138240, - .mb_cycles_vsp = 25, - .mb_cycles_vpp = 200, - .max_frame_rate = MAXIMUM_FPS, - .max_operating_rate = MAXIMUM_FPS, -}; - -static const struct icc_info iris_icc_info_vpu2[] = { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" }; - -static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" }; - -static const struct tz_cp_config tz_cp_config_vpu2[] = { - { - .cp_start = 0, - .cp_size = 0x25800000, - .cp_nonpixel_start = 0x01000000, - .cp_nonpixel_size = 0x24800000, - }, -}; - -const struct iris_platform_data sc7280_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu2_ops, - .icc_tbl = iris_icc_info_vpu2, - .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), - .bw_tbl_dec = sc7280_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl = iris_pmdomain_table_vpu2, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), - .opp_pd_tbl = sc7280_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), - .clk_tbl = sc7280_clk_table, - .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table), - .opp_clk_tbl = sc7280_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu20_p1.mbn", - .inst_iris_fmts = iris_fmts_vpu2_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), - .inst_caps = &platform_inst_cap_vpu2, - .tz_cp_config_data = tz_cp_config_vpu2, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), - .num_vpp_pipe = 1, - .no_aon = true, - .max_session_count = 16, - .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, - /* max spec for SC7280 is 4096x2176@60fps */ - .max_core_mbps = 4096 * 2176 / 256 * 60, -}; - -const struct iris_platform_data sm8250_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu2_ops, - .icc_tbl = iris_icc_info_vpu2, - .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), - .clk_rst_tbl = iris_clk_reset_table_vpu2, - .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2), - .bw_tbl_dec = sm8250_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl = iris_pmdomain_table_vpu2, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), - .opp_pd_tbl = sm8250_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), - .clk_tbl = sm8250_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table), - .opp_clk_tbl = sm8250_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu-1.0/venus.mbn", - .inst_iris_fmts = iris_fmts_vpu2_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), - .inst_caps = &platform_inst_cap_vpu2, - .tz_cp_config_data = tz_cp_config_vpu2, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; From dfacc0ba652fc2de8c686a1e1a47f10e1d5e26c2 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:43 +0530 Subject: [PATCH 1196/1330] Revert "FROMLIST: media: qcom: iris: split firmware_data from raw platform data" This reverts commit 123d5ea2dabe88a081922d3b44d6cf857674bcd9. Signed-off-by: Gourav Kumar (cherry picked from commit a2ab16b6faa9d51bd1a9cede07f8ae0fd511ac03) (cherry picked from commit 34b161ada75b45d5c9f6af8e0b6932d5c7b8f2d5) --- .../media/platform/qcom/iris/iris_buffer.c | 82 ++--- drivers/media/platform/qcom/iris/iris_core.h | 2 - drivers/media/platform/qcom/iris/iris_ctrls.c | 8 +- .../qcom/iris/iris_hfi_gen1_command.c | 8 +- .../qcom/iris/iris_hfi_gen2_command.c | 66 ++-- .../platform/qcom/iris/iris_platform_common.h | 86 ++--- .../platform/qcom/iris/iris_platform_gen1.c | 67 ++-- .../platform/qcom/iris/iris_platform_gen2.c | 320 +++++++++++++++--- drivers/media/platform/qcom/iris/iris_probe.c | 2 +- drivers/media/platform/qcom/iris/iris_vidc.c | 10 +- .../platform/qcom/iris/iris_vpu_common.c | 2 +- 11 files changed, 435 insertions(+), 218 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 762cdbf728b07..68336824aee1d 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -301,31 +301,31 @@ static void iris_fill_internal_buf_info(struct iris_inst *inst, void iris_get_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; + const struct iris_platform_data *platform_data = inst->core->iris_platform_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->dec_ip_int_buf_tbl; - internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; + internal_buf_type = platform_data->dec_ip_int_buf_tbl; + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type = firmware_data->dec_op_int_buf_tbl; - internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; + internal_buf_type = platform_data->dec_op_int_buf_tbl; + internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->enc_ip_int_buf_tbl; - internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; + internal_buf_type = platform_data->enc_ip_int_buf_tbl; + internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type = firmware_data->enc_op_int_buf_tbl; - internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; + internal_buf_type = platform_data->enc_op_int_buf_tbl; + internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } @@ -366,7 +366,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; + const struct iris_platform_data *platform_data = inst->core->iris_platform_data; u32 internal_buffer_count, i, j; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -374,19 +374,19 @@ int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->dec_ip_int_buf_tbl; - internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; + internal_buf_type = platform_data->dec_ip_int_buf_tbl; + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = firmware_data->dec_op_int_buf_tbl; - internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; + internal_buf_type = platform_data->dec_op_int_buf_tbl; + internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->enc_ip_int_buf_tbl; - internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; + internal_buf_type = platform_data->enc_ip_int_buf_tbl; + internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = firmware_data->enc_op_int_buf_tbl; - internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; + internal_buf_type = platform_data->enc_op_int_buf_tbl; + internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; } } @@ -442,7 +442,7 @@ int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris_buffe int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; + const struct iris_platform_data *platform_data = inst->core->iris_platform_data; struct iris_buffer *buffer, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -451,19 +451,19 @@ int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->dec_ip_int_buf_tbl; - internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; + internal_buf_type = platform_data->dec_ip_int_buf_tbl; + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = firmware_data->dec_op_int_buf_tbl; - internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; + internal_buf_type = platform_data->dec_op_int_buf_tbl; + internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->enc_ip_int_buf_tbl; - internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; + internal_buf_type = platform_data->enc_ip_int_buf_tbl; + internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = firmware_data->enc_op_int_buf_tbl; - internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; + internal_buf_type = platform_data->enc_op_int_buf_tbl; + internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; } } @@ -501,7 +501,7 @@ int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buf static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool force) { - const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; + const struct iris_platform_data *platform_data = inst->core->iris_platform_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -510,19 +510,19 @@ static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->dec_ip_int_buf_tbl; - len = firmware_data->dec_ip_int_buf_tbl_size; + internal_buf_type = platform_data->dec_ip_int_buf_tbl; + len = platform_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = firmware_data->dec_op_int_buf_tbl; - len = firmware_data->dec_op_int_buf_tbl_size; + internal_buf_type = platform_data->dec_op_int_buf_tbl; + len = platform_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->enc_ip_int_buf_tbl; - len = firmware_data->enc_ip_int_buf_tbl_size; + internal_buf_type = platform_data->enc_ip_int_buf_tbl; + len = platform_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = firmware_data->enc_op_int_buf_tbl; - len = firmware_data->enc_op_int_buf_tbl_size; + internal_buf_type = platform_data->enc_op_int_buf_tbl; + len = platform_data->enc_op_int_buf_tbl_size; } } @@ -595,17 +595,17 @@ static int iris_release_internal_buffers(struct iris_inst *inst, static int iris_release_input_internal_buffers(struct iris_inst *inst) { - const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; + const struct iris_platform_data *platform_data = inst->core->iris_platform_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; int ret; if (inst->domain == DECODER) { - internal_buf_type = firmware_data->dec_ip_int_buf_tbl; - internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; + internal_buf_type = platform_data->dec_ip_int_buf_tbl; + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = firmware_data->enc_ip_int_buf_tbl; - internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; + internal_buf_type = platform_data->enc_ip_int_buf_tbl; + internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; } for (i = 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 7d128e7724ed1..5f8668e1a16d7 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -55,7 +55,6 @@ enum domain_type { * @resets: table of iris reset clocks * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data - * @iris_firmware_data: a pointer to the firmware (or HFI) specific data * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory @@ -106,7 +105,6 @@ struct iris_core { struct reset_control_bulk_data *resets; struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; - const struct iris_firmware_data *iris_firmware_data; enum iris_core_state state; dma_addr_t iface_q_table_daddr; dma_addr_t sfr_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c index ef7adac3764d7..5a24aa869b2dc 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -332,8 +332,8 @@ void iris_session_init_caps(struct iris_core *core) const struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; - caps = core->iris_firmware_data->inst_fw_caps_dec; - num_cap = core->iris_firmware_data->inst_fw_caps_dec_size; + caps = core->iris_platform_data->inst_fw_caps_dec; + num_cap = core->iris_platform_data->inst_fw_caps_dec_size; for (i = 0; i < num_cap; i++) { cap_id = caps[i].cap_id; @@ -360,8 +360,8 @@ void iris_session_init_caps(struct iris_core *core) } } - caps = core->iris_firmware_data->inst_fw_caps_enc; - num_cap = core->iris_firmware_data->inst_fw_caps_enc_size; + caps = core->iris_platform_data->inst_fw_caps_enc; + num_cap = core->iris_platform_data->inst_fw_caps_enc_size; for (i = 0; i < num_cap; i++) { cap_id = caps[i].cap_id; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 3fb90a466a64e..0017ade4adbd9 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1033,8 +1033,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p }; if (inst->domain == DECODER) { - config_params = core->iris_firmware_data->dec_input_config_params_default; - config_params_size = core->iris_firmware_data->dec_input_config_params_default_size; + config_params = core->iris_platform_data->dec_input_config_params_default; + config_params_size = core->iris_platform_data->dec_input_config_params_default_size; if (V4L2_TYPE_IS_OUTPUT(plane)) { handler = vdec_prop_type_handle_inp_arr; handler_size = ARRAY_SIZE(vdec_prop_type_handle_inp_arr); @@ -1043,8 +1043,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p handler_size = ARRAY_SIZE(vdec_prop_type_handle_out_arr); } } else { - config_params = core->iris_firmware_data->enc_input_config_params; - config_params_size = core->iris_firmware_data->enc_input_config_params_size; + config_params = core->iris_platform_data->enc_input_config_params; + config_params_size = core->iris_platform_data->enc_input_config_params_size; handler = venc_prop_type_handle_inp_arr; handler_size = ARRAY_SIZE(venc_prop_type_handle_inp_arr); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 7ac69af63eadb..90dd7f22f3040 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -600,7 +600,7 @@ static int iris_hfi_gen2_set_super_block(struct iris_inst *inst, u32 plane) static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 plane) { - const struct iris_firmware_data *fdata = inst->core->iris_firmware_data; + const struct iris_platform_data *pdata = inst->core->iris_platform_data; u32 config_params_size = 0, i, j; const u32 *config_params = NULL; int ret; @@ -629,31 +629,31 @@ static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 p if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { if (inst->codec == V4L2_PIX_FMT_H264) { - config_params = fdata->dec_input_config_params_default; - config_params_size = fdata->dec_input_config_params_default_size; + config_params = pdata->dec_input_config_params_default; + config_params_size = pdata->dec_input_config_params_default_size; } else if (inst->codec == V4L2_PIX_FMT_HEVC) { - config_params = fdata->dec_input_config_params_hevc; - config_params_size = fdata->dec_input_config_params_hevc_size; + config_params = pdata->dec_input_config_params_hevc; + config_params_size = pdata->dec_input_config_params_hevc_size; } else if (inst->codec == V4L2_PIX_FMT_VP9) { - config_params = fdata->dec_input_config_params_vp9; - config_params_size = fdata->dec_input_config_params_vp9_size; + config_params = pdata->dec_input_config_params_vp9; + config_params_size = pdata->dec_input_config_params_vp9_size; } else if (inst->codec == V4L2_PIX_FMT_AV1) { - config_params = fdata->dec_input_config_params_av1; - config_params_size = fdata->dec_input_config_params_av1_size; + config_params = pdata->dec_input_config_params_av1; + config_params_size = pdata->dec_input_config_params_av1_size; } else { return -EINVAL; } } else { - config_params = fdata->dec_output_config_params; - config_params_size = fdata->dec_output_config_params_size; + config_params = pdata->dec_output_config_params; + config_params_size = pdata->dec_output_config_params_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - config_params = fdata->enc_input_config_params; - config_params_size = fdata->enc_input_config_params_size; + config_params = pdata->enc_input_config_params; + config_params_size = pdata->enc_input_config_params_size; } else { - config_params = fdata->enc_output_config_params; - config_params_size = fdata->enc_output_config_params_size; + config_params = pdata->enc_output_config_params; + config_params_size = pdata->enc_output_config_params_size; } } @@ -848,24 +848,24 @@ static int iris_hfi_gen2_subscribe_change_param(struct iris_inst *inst, u32 plan switch (inst->codec) { case V4L2_PIX_FMT_H264: - change_param = core->iris_firmware_data->dec_input_config_params_default; + change_param = core->iris_platform_data->dec_input_config_params_default; change_param_size = - core->iris_firmware_data->dec_input_config_params_default_size; + core->iris_platform_data->dec_input_config_params_default_size; break; case V4L2_PIX_FMT_HEVC: - change_param = core->iris_firmware_data->dec_input_config_params_hevc; + change_param = core->iris_platform_data->dec_input_config_params_hevc; change_param_size = - core->iris_firmware_data->dec_input_config_params_hevc_size; + core->iris_platform_data->dec_input_config_params_hevc_size; break; case V4L2_PIX_FMT_VP9: - change_param = core->iris_firmware_data->dec_input_config_params_vp9; + change_param = core->iris_platform_data->dec_input_config_params_vp9; change_param_size = - core->iris_firmware_data->dec_input_config_params_vp9_size; + core->iris_platform_data->dec_input_config_params_vp9_size; break; case V4L2_PIX_FMT_AV1: - change_param = core->iris_firmware_data->dec_input_config_params_av1; + change_param = core->iris_platform_data->dec_input_config_params_av1; change_param_size = - core->iris_firmware_data->dec_input_config_params_av1_size; + core->iris_platform_data->dec_input_config_params_av1_size; break; } @@ -995,29 +995,29 @@ static int iris_hfi_gen2_subscribe_property(struct iris_inst *inst, u32 plane) return 0; if (V4L2_TYPE_IS_OUTPUT(plane)) { - subscribe_prop_size = core->iris_firmware_data->dec_input_prop_size; - subcribe_prop = core->iris_firmware_data->dec_input_prop; + subscribe_prop_size = core->iris_platform_data->dec_input_prop_size; + subcribe_prop = core->iris_platform_data->dec_input_prop; } else { switch (inst->codec) { case V4L2_PIX_FMT_H264: - subcribe_prop = core->iris_firmware_data->dec_output_prop_avc; + subcribe_prop = core->iris_platform_data->dec_output_prop_avc; subscribe_prop_size = - core->iris_firmware_data->dec_output_prop_avc_size; + core->iris_platform_data->dec_output_prop_avc_size; break; case V4L2_PIX_FMT_HEVC: - subcribe_prop = core->iris_firmware_data->dec_output_prop_hevc; + subcribe_prop = core->iris_platform_data->dec_output_prop_hevc; subscribe_prop_size = - core->iris_firmware_data->dec_output_prop_hevc_size; + core->iris_platform_data->dec_output_prop_hevc_size; break; case V4L2_PIX_FMT_VP9: - subcribe_prop = core->iris_firmware_data->dec_output_prop_vp9; + subcribe_prop = core->iris_platform_data->dec_output_prop_vp9; subscribe_prop_size = - core->iris_firmware_data->dec_output_prop_vp9_size; + core->iris_platform_data->dec_output_prop_vp9_size; break; case V4L2_PIX_FMT_AV1: - subcribe_prop = core->iris_firmware_data->dec_output_prop_av1; + subcribe_prop = core->iris_platform_data->dec_output_prop_av1; subscribe_prop_size = - core->iris_firmware_data->dec_output_prop_av1_size; + core->iris_platform_data->dec_output_prop_av1_size; break; } } diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 1dc3817b22b73..e33188146f163 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -201,16 +201,48 @@ enum platform_pm_domain_type { IRIS_APV_HW_POWER_DOMAIN, }; -struct iris_firmware_data { +struct iris_platform_data { void (*init_hfi_ops)(struct iris_core *core); + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); + const struct vpu_ops *vpu_ops; - u32 core_arch; - + int (*init_cb_devs)(struct iris_core *core); + void (*deinit_cb_devs)(struct iris_core *core); + const struct icc_info *icc_tbl; + unsigned int icc_tbl_size; + const struct bw_info *bw_tbl_dec; + unsigned int bw_tbl_dec_size; + const char * const *pmdomain_tbl; + unsigned int pmdomain_tbl_size; + const char * const *opp_pd_tbl; + unsigned int opp_pd_tbl_size; + const struct platform_clk_data *clk_tbl; + const char * const *opp_clk_tbl; + unsigned int clk_tbl_size; + const char * const *clk_rst_tbl; + unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; + u64 dma_mask; + const char *fwname; + struct iris_fmt *inst_iris_fmts; + u32 inst_iris_fmts_size; + struct platform_inst_caps *inst_caps; const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; - + const struct tz_cp_config *tz_cp_config_data; + u32 tz_cp_config_data_size; + u32 core_arch; + struct ubwc_config_data *ubwc_config; + u32 num_vpp_pipe; + bool no_aon; + u32 max_session_count; + /* max number of macroblocks per frame supported */ + u32 max_core_mbpf; + /* max number of macroblocks per second supported */ + u32 max_core_mbps; const u32 *dec_input_config_params_default; unsigned int dec_input_config_params_default_size; const u32 *dec_input_config_params_hevc; @@ -225,7 +257,6 @@ struct iris_firmware_data { unsigned int enc_input_config_params_size; const u32 *enc_output_config_params; unsigned int enc_output_config_params_size; - const u32 *dec_input_prop; unsigned int dec_input_prop_size; const u32 *dec_output_prop_avc; @@ -236,7 +267,6 @@ struct iris_firmware_data { unsigned int dec_output_prop_vp9_size; const u32 *dec_output_prop_av1; unsigned int dec_output_prop_av1_size; - const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; @@ -247,48 +277,4 @@ struct iris_firmware_data { unsigned int enc_op_int_buf_tbl_size; }; -struct iris_platform_data { - /* - * XXX: remove firmware_data pointer and consider moving - * get_vpu_buffer_size pointer once we have platforms supporting both - * firmware kinds. - */ - const struct iris_firmware_data *firmware_data; - u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); - - const struct vpu_ops *vpu_ops; - - int (*init_cb_devs)(struct iris_core *core); - void (*deinit_cb_devs)(struct iris_core *core); - const struct icc_info *icc_tbl; - unsigned int icc_tbl_size; - const struct bw_info *bw_tbl_dec; - unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; - const char * const *opp_pd_tbl; - unsigned int opp_pd_tbl_size; - const struct platform_clk_data *clk_tbl; - const char * const *opp_clk_tbl; - unsigned int clk_tbl_size; - const char * const *clk_rst_tbl; - unsigned int clk_rst_tbl_size; - const char * const *controller_rst_tbl; - unsigned int controller_rst_tbl_size; - u64 dma_mask; - const char *fwname; - struct iris_fmt *inst_iris_fmts; - u32 inst_iris_fmts_size; - struct platform_inst_caps *inst_caps; - const struct tz_cp_config *tz_cp_config_data; - u32 tz_cp_config_data_size; - u32 num_vpp_pipe; - bool no_aon; - u32 max_session_count; - /* max number of macroblocks per frame supported */ - u32 max_core_mbpf; - /* max number of macroblocks per second supported */ - u32 max_core_mbps; -}; - #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 9e632a973f476..6592c1ed9ca50 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -332,33 +332,8 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { BUF_SCRATCH_2, }; -const struct iris_firmware_data iris_hfi_gen1_data = { - .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, - - .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), - - .dec_input_config_params_default = - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params = sm8250_venc_input_config_param, - .enc_input_config_params_size = - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), -}; - const struct iris_platform_data sm8250_data = { - .firmware_data = &iris_hfi_gen1_data, + .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -380,16 +355,35 @@ const struct iris_platform_data sm8250_data = { .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, + .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K, .max_core_mbps = ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default = + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params = sm8250_venc_input_config_param, + .enc_input_config_params_size = + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; const struct iris_platform_data sc7280_data = { - .firmware_data = &iris_hfi_gen1_data, + .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -409,6 +403,10 @@ const struct iris_platform_data sc7280_data = { .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, + .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), .num_vpp_pipe = 1, @@ -417,4 +415,19 @@ const struct iris_platform_data sc7280_data = { .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ .max_core_mbps = 4096 * 2176 / 256 * 60, + .dec_input_config_params_default = + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params = sm8250_venc_input_config_param, + .enc_input_config_params_size = + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index b83a2af4cb7d4..deaf6248f7f9e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -958,16 +958,41 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { BUF_SCRATCH_2, }; -const struct iris_firmware_data iris_hfi_gen2_data = { +const struct iris_platform_data kaanapali_data = { .init_hfi_ops = iris_hfi_gen2_sys_ops_init, - - .core_arch = VIDEO_ARCH_LX, - + .get_vpu_buffer_size = iris_vpu4x_buf_size, + .vpu_ops = &iris_vpu4x_ops, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = kaanapali_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = kaanapali_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = kaanapali_clk_table, + .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), + .opp_clk_tbl = kaanapali_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu40_p2_s7.mbn", + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), - + .tz_cp_config_data = tz_cp_config_kaanapali, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), + .core_arch = VIDEO_ARCH_LX, + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 2, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4352) / 256) * 60, .dec_input_config_params_default = sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size = @@ -980,10 +1005,6 @@ const struct iris_firmware_data iris_hfi_gen2_data = { sm8550_vdec_input_config_param_vp9, .dec_input_config_params_vp9_size = ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 = - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), .dec_output_config_params = sm8550_vdec_output_config_params, .dec_output_config_params_size = @@ -1009,55 +1030,18 @@ const struct iris_firmware_data iris_hfi_gen2_data = { .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, .dec_output_prop_vp9_size = ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; -const struct iris_platform_data kaanapali_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu4x_buf_size, - .vpu_ops = &iris_vpu4x_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = kaanapali_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = kaanapali_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = kaanapali_clk_table, - .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), - .opp_clk_tbl = kaanapali_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu40_p2_s7.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_kaanapali, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), - .ubwc_config = &ubwc_config_sm8550, - .num_vpp_pipe = 2, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((8192 * 4352) / 256) * 60, -}; - const struct iris_platform_data sm8550_data = { - .firmware_data = &iris_hfi_gen2_data, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .init_cb_devs = sm8550_init_cb_devs, @@ -1081,13 +1065,72 @@ const struct iris_platform_data sm8550_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch = VIDEO_ARCH_LX, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default = + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc = + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 = + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 = + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), + .dec_output_config_params = + sm8550_vdec_output_config_params, + .dec_output_config_params_size = + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params = + sm8550_venc_input_config_params, + .enc_input_config_params_size = + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params = + sm8550_venc_output_config_params, + .enc_output_config_params_size = + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop = sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), + + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; /* @@ -1098,7 +1141,7 @@ const struct iris_platform_data sm8550_data = { * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { - .firmware_data = &iris_hfi_gen2_data, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, .icc_tbl = sm8550_icc_table, @@ -1122,17 +1165,76 @@ const struct iris_platform_data sm8650_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch = VIDEO_ARCH_LX, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default = + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc = + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 = + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 = + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), + .dec_output_config_params = + sm8550_vdec_output_config_params, + .dec_output_config_params_size = + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params = + sm8550_venc_input_config_params, + .enc_input_config_params_size = + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params = + sm8550_venc_output_config_params, + .enc_output_config_params_size = + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop = sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), + + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; const struct iris_platform_data sm8750_data = { - .firmware_data = &iris_hfi_gen2_data, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, .icc_tbl = sm8550_icc_table, @@ -1154,13 +1256,72 @@ const struct iris_platform_data sm8750_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch = VIDEO_ARCH_LX, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default = + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc = + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 = + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 = + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), + .dec_output_config_params = + sm8550_vdec_output_config_params, + .dec_output_config_params_size = + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params = + sm8550_venc_input_config_params, + .enc_input_config_params_size = + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params = + sm8550_venc_output_config_params, + .enc_output_config_params_size = + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop = sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), + + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; /* @@ -1168,7 +1329,7 @@ const struct iris_platform_data sm8750_data = { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .firmware_data = &iris_hfi_gen2_data, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .icc_tbl = sm8550_icc_table, @@ -1190,11 +1351,70 @@ const struct iris_platform_data qcs8300_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_qcs8300, + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch = VIDEO_ARCH_LX, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 2, .max_session_count = 16, .max_core_mbpf = ((4096 * 2176) / 256) * 4, .max_core_mbps = (((3840 * 2176) / 256) * 120), + .dec_input_config_params_default = + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc = + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 = + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 = + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), + .dec_output_config_params = + sm8550_vdec_output_config_params, + .dec_output_config_params_size = + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params = + sm8550_venc_input_config_params, + .enc_input_config_params_size = + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params = + sm8550_venc_output_config_params, + .enc_output_config_params_size = + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop = sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), + + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 5f4046e72955c..6a714943c8e39 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -259,7 +259,6 @@ static int iris_probe(struct platform_device *pdev) return core->irq; core->iris_platform_data = of_device_get_match_data(core->dev); - core->iris_firmware_data = core->iris_platform_data->firmware_data; ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr, iris_hfi_isr_handler, IRQF_TRIGGER_HIGH, "iris", core); @@ -269,6 +268,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); iris_init_ops(core); + core->iris_platform_data->init_hfi_ops(core); ret = iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index f805430ab4778..a910b4a2d1a75 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -246,7 +246,7 @@ static void iris_session_close(struct iris_inst *inst) static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; + const struct iris_platform_data *platform_data = inst->core->iris_platform_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -254,11 +254,11 @@ static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 p u32 count = 0; if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = firmware_data->dec_ip_int_buf_tbl; - internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; + internal_buf_type = platform_data->dec_ip_int_buf_tbl; + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = firmware_data->dec_op_int_buf_tbl; - internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; + internal_buf_type = platform_data->dec_op_int_buf_tbl; + internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; } for (i = 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index ca96e91222c67..aa0b66954680d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -63,7 +63,7 @@ static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core) writel(QTBL_ENABLE, core->reg_base + QTBL_INFO); if (core->sfr_daddr) { - value = (u32)core->sfr_daddr + core->iris_firmware_data->core_arch; + value = (u32)core->sfr_daddr + core->iris_platform_data->core_arch; writel(value, core->reg_base + SFR_ADDR); } From f470d016dffeca3c64f26ce90288bfc791b910a5 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:44 +0530 Subject: [PATCH 1197/1330] Revert "FROMLIST: media: qcom: iris: drop hw_response_timeout_val from platform data" This reverts commit a40da675a7582a5ba95455aaab56b9557312c071. Signed-off-by: Gourav Kumar (cherry picked from commit 4366088b3f14ce6389e20256da357ac64bc35df9) (cherry picked from commit 69ec1650e9dd49af8d6ebb4a23722ebd35bfae5f) --- drivers/media/platform/qcom/iris/iris_core.c | 3 ++- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_platform_gen1.c | 2 ++ drivers/media/platform/qcom/iris/iris_platform_gen2.c | 6 ++++++ drivers/media/platform/qcom/iris/iris_utils.c | 5 ++++- 5 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c index 932c32f95a283..f61ce89e1be73 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -29,13 +29,14 @@ void iris_core_deinit(struct iris_core *core) static int iris_wait_for_system_response(struct iris_core *core) { + u32 hw_response_timeout_val = core->iris_platform_data->hw_response_timeout; int ret; if (core->state == IRIS_CORE_ERROR) return -EIO; ret = wait_for_completion_timeout(&core->core_init_done, - msecs_to_jiffies(HW_RESPONSE_TIMEOUT_VALUE)); + msecs_to_jiffies(hw_response_timeout_val)); if (!ret) { core->state = IRIS_CORE_ERROR; return -ETIMEDOUT; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index e33188146f163..f989303bc1ade 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -235,6 +235,7 @@ struct iris_platform_data { const struct tz_cp_config *tz_cp_config_data; u32 tz_cp_config_data_size; u32 core_arch; + u32 hw_response_timeout; struct ubwc_config_data *ubwc_config; u32 num_vpp_pipe; bool no_aon; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 6592c1ed9ca50..293834d6359b8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -361,6 +361,7 @@ const struct iris_platform_data sm8250_data = { .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K, @@ -409,6 +410,7 @@ const struct iris_platform_data sc7280_data = { .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 1, .no_aon = true, .max_session_count = 16, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index deaf6248f7f9e..856caf46b9dfc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -959,6 +959,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { }; const struct iris_platform_data kaanapali_data = { + .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu4x_buf_size, .vpu_ops = &iris_vpu4x_ops, @@ -988,6 +989,7 @@ const struct iris_platform_data kaanapali_data = { .tz_cp_config_data = tz_cp_config_kaanapali, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 2, .max_session_count = 16, @@ -1072,6 +1074,7 @@ const struct iris_platform_data sm8550_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, @@ -1172,6 +1175,7 @@ const struct iris_platform_data sm8650_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, @@ -1263,6 +1267,7 @@ const struct iris_platform_data sm8750_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, @@ -1358,6 +1363,7 @@ const struct iris_platform_data qcs8300_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 2, .max_session_count = 16, diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/platform/qcom/iris/iris_utils.c index 29b07d88507eb..cfc5b576ec56b 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -55,13 +55,16 @@ void iris_helper_buffers_done(struct iris_inst *inst, unsigned int type, int iris_wait_for_session_response(struct iris_inst *inst, bool is_flush) { + struct iris_core *core = inst->core; + u32 hw_response_timeout_val; struct completion *done; int ret; + hw_response_timeout_val = core->iris_platform_data->hw_response_timeout; done = is_flush ? &inst->flush_completion : &inst->completion; mutex_unlock(&inst->lock); - ret = wait_for_completion_timeout(done, msecs_to_jiffies(HW_RESPONSE_TIMEOUT_VALUE)); + ret = wait_for_completion_timeout(done, msecs_to_jiffies(hw_response_timeout_val)); mutex_lock(&inst->lock); if (!ret) { iris_inst_change_state(inst, IRIS_INST_ERROR); From 64abc4e400f09724903e65c9def3391be8435a31 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:45 +0530 Subject: [PATCH 1198/1330] Revert "FROMLIST: media: qcom: iris: move get_instance to iris_hfi_sys_ops" This reverts commit f4ae97728b76f007b5deac796c2cf815bb5420c1. Signed-off-by: Gourav Kumar (cherry picked from commit 0a5cf3619a0f1ed239e93c720d1c7b702536016d) (cherry picked from commit 2b9d7c7408d2774c51f80644e747a4960184e50b) --- .../platform/qcom/iris/iris_hfi_common.h | 2 -- .../media/platform/qcom/iris/iris_hfi_gen1.h | 2 ++ .../qcom/iris/iris_hfi_gen1_command.c | 28 ++++++++--------- .../media/platform/qcom/iris/iris_hfi_gen2.h | 1 + .../qcom/iris/iris_hfi_gen2_command.c | 30 +++++++++---------- .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_gen1.c | 2 ++ .../platform/qcom/iris/iris_platform_gen2.c | 4 +++ drivers/media/platform/qcom/iris/iris_vidc.c | 2 +- 9 files changed, 38 insertions(+), 34 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index a27447eb25199..9aa84a1d8f950 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -112,8 +112,6 @@ struct iris_hfi_sys_ops { int (*sys_pc_prep)(struct iris_core *core); void (*sys_hfi_response_handler)(struct iris_core *core); - - struct iris_inst *(*sys_get_instance)(void); }; struct iris_hfi_session_ops { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h index c37adf65055a5..38e9d262d7df4 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h @@ -7,8 +7,10 @@ #define __IRIS_HFI_GEN1_H__ struct iris_core; +struct iris_inst; void iris_hfi_gen1_sys_ops_init(struct iris_core *core); void iris_hfi_gen1_response_handler(struct iris_core *core); +struct iris_inst *iris_hfi_gen1_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 0017ade4adbd9..26b7feb05d15b 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1076,19 +1076,6 @@ static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_close = iris_hfi_gen1_session_close, }; -static struct iris_inst *iris_hfi_gen1_get_instance(void) -{ - struct iris_inst *out; - - out = kzalloc_obj(*out); - if (!out) - return NULL; - - out->hfi_session_ops = &iris_hfi_gen1_session_ops; - - return out; -} - static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { .sys_init = iris_hfi_gen1_sys_init, .sys_image_version = iris_hfi_gen1_sys_image_version, @@ -1096,11 +1083,22 @@ static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, .sys_hfi_response_handler = iris_hfi_gen1_response_handler, - - .sys_get_instance = iris_hfi_gen1_get_instance, }; void iris_hfi_gen1_sys_ops_init(struct iris_core *core) { core->hfi_sys_ops = &iris_hfi_gen1_sys_ops; } + +struct iris_inst *iris_hfi_gen1_get_instance(void) +{ + struct iris_inst *out; + + out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->hfi_session_ops = &iris_hfi_gen1_session_ops; + + return out; +} diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h index 21ab58e0aa840..6cc6d9890c128 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h @@ -36,5 +36,6 @@ struct iris_inst_hfi_gen2 { void iris_hfi_gen2_sys_ops_init(struct iris_core *core); void iris_hfi_gen2_response_handler(struct iris_core *core); +struct iris_inst *iris_hfi_gen2_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 90dd7f22f3040..552d4230e455c 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1306,20 +1306,6 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_close = iris_hfi_gen2_session_close, }; -static struct iris_inst *iris_hfi_gen2_get_instance(void) -{ - struct iris_inst_hfi_gen2 *out; - - /* The allocation is intentionally larger than struct iris_inst. */ - out = kzalloc_obj(*out); - if (!out) - return NULL; - - out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; - - return &out->inst; -} - static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { .sys_init = iris_hfi_gen2_sys_init, .sys_image_version = iris_hfi_gen2_sys_image_version, @@ -1327,11 +1313,23 @@ static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, .sys_hfi_response_handler = iris_hfi_gen2_response_handler, - - .sys_get_instance = iris_hfi_gen2_get_instance, }; void iris_hfi_gen2_sys_ops_init(struct iris_core *core) { core->hfi_sys_ops = &iris_hfi_gen2_sys_ops; } + +struct iris_inst *iris_hfi_gen2_get_instance(void) +{ + struct iris_inst_hfi_gen2 *out; + + /* The allocation is intentionally larger than struct iris_inst. */ + out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; + + return &out->inst; +} diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index f989303bc1ade..bf1e9fe489e0b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -203,6 +203,7 @@ enum platform_pm_domain_type { struct iris_platform_data { void (*init_hfi_ops)(struct iris_core *core); + struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 293834d6359b8..9eeb500c65d90 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -333,6 +333,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { }; const struct iris_platform_data sm8250_data = { + .get_instance = iris_hfi_gen1_get_instance, .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, @@ -384,6 +385,7 @@ const struct iris_platform_data sm8250_data = { }; const struct iris_platform_data sc7280_data = { + .get_instance = iris_hfi_gen1_get_instance, .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 856caf46b9dfc..655098e260740 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -1043,6 +1043,7 @@ const struct iris_platform_data kaanapali_data = { }; const struct iris_platform_data sm8550_data = { + .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, @@ -1144,6 +1145,7 @@ const struct iris_platform_data sm8550_data = { * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { + .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, @@ -1238,6 +1240,7 @@ const struct iris_platform_data sm8650_data = { }; const struct iris_platform_data sm8750_data = { + .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, @@ -1334,6 +1337,7 @@ const struct iris_platform_data sm8750_data = { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { + .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index a910b4a2d1a75..359ff9997bedb 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -157,7 +157,7 @@ int iris_open(struct file *filp) pm_runtime_put_sync(core->dev); - inst = core->hfi_sys_ops->sys_get_instance(); + inst = core->iris_platform_data->get_instance(); if (!inst) return -ENOMEM; From 6ea6d79786b7983758fcec562dc050e6f815fda7 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:47 +0530 Subject: [PATCH 1199/1330] Revert "FROMLIST: media: qcom: iris: merge hfi_response_ops and hfi_command_ops" This reverts commit a6625a0660fae1a835dc699ed507f6bed091a2aa. Signed-off-by: Gourav Kumar (cherry picked from commit 985cc2f2c167fcf115ef768b5a0865db71d3676f) (cherry picked from commit cdbaa604a181ee19909a5f293fd8ed5509d3f320) --- drivers/media/platform/qcom/iris/iris_core.h | 6 ++++-- .../media/platform/qcom/iris/iris_hfi_common.c | 6 +++--- .../media/platform/qcom/iris/iris_hfi_common.h | 8 +++++--- drivers/media/platform/qcom/iris/iris_hfi_gen1.h | 4 ++-- .../platform/qcom/iris/iris_hfi_gen1_command.c | 8 +++----- .../platform/qcom/iris/iris_hfi_gen1_response.c | 11 ++++++++++- drivers/media/platform/qcom/iris/iris_hfi_gen2.h | 4 ++-- .../platform/qcom/iris/iris_hfi_gen2_command.c | 8 +++----- .../platform/qcom/iris/iris_hfi_gen2_response.c | 11 ++++++++++- .../platform/qcom/iris/iris_platform_common.h | 3 ++- .../media/platform/qcom/iris/iris_platform_gen1.c | 6 ++++-- .../media/platform/qcom/iris/iris_platform_gen2.c | 15 ++++++++++----- drivers/media/platform/qcom/iris/iris_probe.c | 3 ++- .../media/platform/qcom/iris/iris_vpu_common.c | 2 +- 14 files changed, 61 insertions(+), 34 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 5f8668e1a16d7..c85fd7f292467 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -68,7 +68,8 @@ enum domain_type { * @header_id: id of packet header * @packet_id: id of packet * @power: a structure for clock and bw information - * @hfi_sys_ops: iris HFI system ops + * @hfi_ops: iris hfi command ops + * @hfi_response_ops: iris hfi response ops * @core_init_done: structure of signal completion for system response * @intr_status: interrupt status * @sys_error_handler: a delayed work for handling system fatal error @@ -118,7 +119,8 @@ struct iris_core { u32 header_id; u32 packet_id; struct iris_core_power power; - const struct iris_hfi_sys_ops *hfi_sys_ops; + const struct iris_hfi_command_ops *hfi_ops; + const struct iris_hfi_response_ops *hfi_response_ops; struct completion core_init_done; u32 intr_status; struct delayed_work sys_error_handler; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/media/platform/qcom/iris/iris_hfi_common.c index 8769ec61f1176..621c66593d88d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c @@ -76,7 +76,7 @@ u32 iris_hfi_get_v4l2_matrix_coefficients(u32 hfi_coefficients) int iris_hfi_core_init(struct iris_core *core) { - const struct iris_hfi_sys_ops *hfi_ops = core->hfi_sys_ops; + const struct iris_hfi_command_ops *hfi_ops = core->hfi_ops; int ret; ret = hfi_ops->sys_init(core); @@ -109,7 +109,7 @@ irqreturn_t iris_hfi_isr_handler(int irq, void *data) iris_vpu_clear_interrupt(core); mutex_unlock(&core->lock); - core->hfi_sys_ops->sys_hfi_response_handler(core); + core->hfi_response_ops->hfi_response_handler(core); if (!iris_vpu_watchdog(core, core->intr_status)) enable_irq(irq); @@ -144,7 +144,7 @@ int iris_hfi_pm_suspend(struct iris_core *core) int iris_hfi_pm_resume(struct iris_core *core) { - const struct iris_hfi_sys_ops *ops = core->hfi_sys_ops; + const struct iris_hfi_command_ops *ops = core->hfi_ops; int ret; ret = iris_vpu_power_on(core); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 9aa84a1d8f950..18684ada78b21 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -105,13 +105,11 @@ struct iris_hfi_prop_type_handle { int (*handle)(struct iris_inst *inst, u32 plane); }; -struct iris_hfi_sys_ops { +struct iris_hfi_command_ops { int (*sys_init)(struct iris_core *core); int (*sys_image_version)(struct iris_core *core); int (*sys_interframe_powercollapse)(struct iris_core *core); int (*sys_pc_prep)(struct iris_core *core); - - void (*sys_hfi_response_handler)(struct iris_core *core); }; struct iris_hfi_session_ops { @@ -131,6 +129,10 @@ struct iris_hfi_session_ops { int (*session_close)(struct iris_inst *inst); }; +struct iris_hfi_response_ops { + void (*hfi_response_handler)(struct iris_core *core); +}; + struct hfi_subscription_params { u32 bitstream_resolution; u32 crop_offsets[2]; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h index 38e9d262d7df4..19b8e9054a757 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h @@ -9,8 +9,8 @@ struct iris_core; struct iris_inst; -void iris_hfi_gen1_sys_ops_init(struct iris_core *core); -void iris_hfi_gen1_response_handler(struct iris_core *core); +void iris_hfi_gen1_command_ops_init(struct iris_core *core); +void iris_hfi_gen1_response_ops_init(struct iris_core *core); struct iris_inst *iris_hfi_gen1_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 26b7feb05d15b..a28b0c7ebbadd 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1076,18 +1076,16 @@ static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_close = iris_hfi_gen1_session_close, }; -static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { +static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { .sys_init = iris_hfi_gen1_sys_init, .sys_image_version = iris_hfi_gen1_sys_image_version, .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, - - .sys_hfi_response_handler = iris_hfi_gen1_response_handler, }; -void iris_hfi_gen1_sys_ops_init(struct iris_core *core) +void iris_hfi_gen1_command_ops_init(struct iris_core *core) { - core->hfi_sys_ops = &iris_hfi_gen1_sys_ops; + core->hfi_ops = &iris_hfi_gen1_command_ops; } struct iris_inst *iris_hfi_gen1_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index bfd7495bf44f0..8e864c239e293 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -688,7 +688,7 @@ static void iris_hfi_gen1_flush_debug_queue(struct iris_core *core, u8 *packet) } } -void iris_hfi_gen1_response_handler(struct iris_core *core) +static void iris_hfi_gen1_response_handler(struct iris_core *core) { memset(core->response_packet, 0, sizeof(struct hfi_pkt_hdr)); while (!iris_hfi_queue_msg_read(core, core->response_packet)) { @@ -698,3 +698,12 @@ void iris_hfi_gen1_response_handler(struct iris_core *core) iris_hfi_gen1_flush_debug_queue(core, core->response_packet); } + +static const struct iris_hfi_response_ops iris_hfi_gen1_response_ops = { + .hfi_response_handler = iris_hfi_gen1_response_handler, +}; + +void iris_hfi_gen1_response_ops_init(struct iris_core *core) +{ + core->hfi_response_ops = &iris_hfi_gen1_response_ops; +} diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h index 6cc6d9890c128..b9d3749a10efe 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h @@ -34,8 +34,8 @@ struct iris_inst_hfi_gen2 { struct hfi_subscription_params dst_subcr_params; }; -void iris_hfi_gen2_sys_ops_init(struct iris_core *core); -void iris_hfi_gen2_response_handler(struct iris_core *core); +void iris_hfi_gen2_command_ops_init(struct iris_core *core); +void iris_hfi_gen2_response_ops_init(struct iris_core *core); struct iris_inst *iris_hfi_gen2_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 552d4230e455c..29814d77c969f 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1306,18 +1306,16 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_close = iris_hfi_gen2_session_close, }; -static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { +static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { .sys_init = iris_hfi_gen2_sys_init, .sys_image_version = iris_hfi_gen2_sys_image_version, .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, - - .sys_hfi_response_handler = iris_hfi_gen2_response_handler, }; -void iris_hfi_gen2_sys_ops_init(struct iris_core *core) +void iris_hfi_gen2_command_ops_init(struct iris_core *core) { - core->hfi_sys_ops = &iris_hfi_gen2_sys_ops; + core->hfi_ops = &iris_hfi_gen2_command_ops; } struct iris_inst *iris_hfi_gen2_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index c350d231265e5..8e19f61bbbf9e 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -977,7 +977,7 @@ static void iris_hfi_gen2_flush_debug_queue(struct iris_core *core, u8 *packet) } } -void iris_hfi_gen2_response_handler(struct iris_core *core) +static void iris_hfi_gen2_response_handler(struct iris_core *core) { if (iris_vpu_watchdog(core, core->intr_status)) { struct iris_hfi_packet pkt = {.type = HFI_SYS_ERROR_WD_TIMEOUT}; @@ -997,3 +997,12 @@ void iris_hfi_gen2_response_handler(struct iris_core *core) iris_hfi_gen2_flush_debug_queue(core, core->response_packet); } + +static const struct iris_hfi_response_ops iris_hfi_gen2_response_ops = { + .hfi_response_handler = iris_hfi_gen2_response_handler, +}; + +void iris_hfi_gen2_response_ops_init(struct iris_core *core) +{ + core->hfi_response_ops = &iris_hfi_gen2_response_ops; +} diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index bf1e9fe489e0b..fd3ad0f16b045 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -202,7 +202,8 @@ enum platform_pm_domain_type { }; struct iris_platform_data { - void (*init_hfi_ops)(struct iris_core *core); + void (*init_hfi_command_ops)(struct iris_core *core); + void (*init_hfi_response_ops)(struct iris_core *core); struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 9eeb500c65d90..546f6c025d547 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -334,7 +334,8 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { const struct iris_platform_data sm8250_data = { .get_instance = iris_hfi_gen1_get_instance, - .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, + .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -386,7 +387,8 @@ const struct iris_platform_data sm8250_data = { const struct iris_platform_data sc7280_data = { .get_instance = iris_hfi_gen1_get_instance, - .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, + .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 655098e260740..8e98857f76f99 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -960,7 +960,8 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { const struct iris_platform_data kaanapali_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu4x_buf_size, .vpu_ops = &iris_vpu4x_ops, .icc_tbl = sm8550_icc_table, @@ -1044,7 +1045,8 @@ const struct iris_platform_data kaanapali_data = { const struct iris_platform_data sm8550_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .init_cb_devs = sm8550_init_cb_devs, @@ -1146,7 +1148,8 @@ const struct iris_platform_data sm8550_data = { */ const struct iris_platform_data sm8650_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, .icc_tbl = sm8550_icc_table, @@ -1241,7 +1244,8 @@ const struct iris_platform_data sm8650_data = { const struct iris_platform_data sm8750_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, .icc_tbl = sm8550_icc_table, @@ -1338,7 +1342,8 @@ const struct iris_platform_data sm8750_data = { */ const struct iris_platform_data qcs8300_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .icc_tbl = sm8550_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 6a714943c8e39..fe4bef12f7fbe 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -268,7 +268,8 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); iris_init_ops(core); - core->iris_platform_data->init_hfi_ops(core); + core->iris_platform_data->init_hfi_command_ops(core); + core->iris_platform_data->init_hfi_response_ops(core); ret = iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index aa0b66954680d..96e5b305c5f4a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -149,7 +149,7 @@ int iris_vpu_prepare_pc(struct iris_core *core) if (!wfi_status || !idle_status) goto skip_power_off; - ret = core->hfi_sys_ops->sys_pc_prep(core); + ret = core->hfi_ops->sys_pc_prep(core); if (ret) goto skip_power_off; From 4122267f02ff42d59e12aaf169a12fbddddb742c Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:48 +0530 Subject: [PATCH 1200/1330] Revert "FROMLIST: media: qcom: iris: split HFI session ops from core ops" This reverts commit c118090e106fa681265eac9889a34fde760d7aa9. Signed-off-by: Gourav Kumar (cherry picked from commit f9f88d8793d6f982e3d9a5ec1302f359aa6dc162) (cherry picked from commit fadfeff8fbd4e228b55e37481bb7d925d0a78dff) --- .../media/platform/qcom/iris/iris_buffer.c | 4 +- .../media/platform/qcom/iris/iris_common.c | 8 ++-- drivers/media/platform/qcom/iris/iris_ctrls.c | 46 +++++++++---------- .../platform/qcom/iris/iris_hfi_common.h | 3 -- .../qcom/iris/iris_hfi_gen1_command.c | 23 +++------- .../qcom/iris/iris_hfi_gen2_command.c | 17 ++----- .../media/platform/qcom/iris/iris_instance.h | 4 -- drivers/media/platform/qcom/iris/iris_vb2.c | 2 +- drivers/media/platform/qcom/iris/iris_vdec.c | 6 +-- drivers/media/platform/qcom/iris/iris_venc.c | 4 +- drivers/media/platform/qcom/iris/iris_vidc.c | 2 +- 11 files changed, 47 insertions(+), 72 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 68336824aee1d..d927b392fb762 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -404,7 +404,7 @@ int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; int ret; ret = hfi_ops->session_queue_buf(inst, buf); @@ -572,7 +572,7 @@ int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 plane) static int iris_release_internal_buffers(struct iris_inst *inst, enum iris_buffer_type buffer_type) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; struct iris_buffers *buffers = &inst->buffers[buffer_type]; struct iris_buffer *buffer, *next; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media/platform/qcom/iris/iris_common.c index 25836561bcf3e..7f1c7fe144f70 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -48,7 +48,7 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_process_streamon_input(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; enum iris_inst_sub_state set_sub_state = 0; int ret; @@ -90,7 +90,7 @@ int iris_process_streamon_input(struct iris_inst *inst) int iris_process_streamon_output(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; enum iris_inst_sub_state clear_sub_state = 0; bool drain_active, drc_active, first_ipsc; int ret = 0; @@ -189,7 +189,7 @@ static void iris_flush_deferred_buffers(struct iris_inst *inst, static void iris_kill_session(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; if (!inst->session_id) return; @@ -200,7 +200,7 @@ static void iris_kill_session(struct iris_inst *inst) int iris_session_streamoff(struct iris_inst *inst, u32 plane) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; enum iris_buffer_type buffer_type; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c index 5a24aa869b2dc..3cec957580f5e 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -399,7 +399,7 @@ static u32 iris_get_port_info(struct iris_inst *inst, int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 hfi_value = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -412,7 +412,7 @@ int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 hfi_value = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -425,7 +425,7 @@ int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; struct v4l2_format *inp_f = inst->fmt_src; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 height = inp_f->fmt.pix_mp.height; @@ -446,7 +446,7 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 work_route = inst->fw_caps[PIPE].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -459,7 +459,7 @@ int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 hfi_id, hfi_value; if (inst->codec == V4L2_PIX_FMT_H264) { @@ -479,7 +479,7 @@ int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 hfi_id, hfi_value; if (inst->codec == V4L2_PIX_FMT_H264) { @@ -499,7 +499,7 @@ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; struct hfi_profile_level pl; @@ -520,7 +520,7 @@ int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_ca int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 header_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -539,7 +539,7 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; u32 header_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -561,7 +561,7 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; u32 bitrate = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -586,7 +586,7 @@ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; u32 peak_bitrate = inst->fw_caps[cap_id].value; u32 bitrate = inst->fw_caps[BITRATE].value; @@ -613,7 +613,7 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; @@ -640,7 +640,7 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; @@ -667,7 +667,7 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 entropy_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -687,7 +687,7 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 entropy_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 profile; @@ -712,7 +712,7 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; u32 min_qp_enable = 0, client_qp_enable = 0; @@ -776,7 +776,7 @@ int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; u32 max_qp_enable = 0, client_qp_enable; u32 i_frame_qp, p_frame_qp, b_frame_qp; @@ -841,7 +841,7 @@ int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; u32 i_frame_qp, p_frame_qp, b_frame_qp; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -902,7 +902,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; struct hfi_quantization_range_v2 range; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -923,7 +923,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -953,7 +953,7 @@ int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val = HFI_DISABLE_FLIP; @@ -972,7 +972,7 @@ int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; struct vb2_queue *q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); u32 ir_period = inst->fw_caps[cap_id].value; u32 ir_type = 0; @@ -998,7 +998,7 @@ int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type ca int iris_set_properties(struct iris_inst *inst, u32 plane) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; struct platform_inst_fw_cap *cap; int ret; u32 i; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 18684ada78b21..3edb5ae582b49 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -110,9 +110,6 @@ struct iris_hfi_command_ops { int (*sys_image_version)(struct iris_core *core); int (*sys_interframe_powercollapse)(struct iris_core *core); int (*sys_pc_prep)(struct iris_core *core); -}; - -struct iris_hfi_session_ops { int (*session_set_config_params)(struct iris_inst *inst, u32 plane); int (*session_set_property)(struct iris_inst *inst, u32 packet_type, u32 flag, u32 plane, u32 payload_type, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index a28b0c7ebbadd..e42d17653c2c3 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1063,7 +1063,11 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p return 0; } -static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { +static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { + .sys_init = iris_hfi_gen1_sys_init, + .sys_image_version = iris_hfi_gen1_sys_image_version, + .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, + .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, .session_open = iris_hfi_gen1_session_open, .session_set_config_params = iris_hfi_gen1_session_set_config_params, .session_set_property = iris_hfi_gen1_session_set_property, @@ -1076,13 +1080,6 @@ static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_close = iris_hfi_gen1_session_close, }; -static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { - .sys_init = iris_hfi_gen1_sys_init, - .sys_image_version = iris_hfi_gen1_sys_image_version, - .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, - .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, -}; - void iris_hfi_gen1_command_ops_init(struct iris_core *core) { core->hfi_ops = &iris_hfi_gen1_command_ops; @@ -1090,13 +1087,5 @@ void iris_hfi_gen1_command_ops_init(struct iris_core *core) struct iris_inst *iris_hfi_gen1_get_instance(void) { - struct iris_inst *out; - - out = kzalloc_obj(*out); - if (!out) - return NULL; - - out->hfi_session_ops = &iris_hfi_gen1_session_ops; - - return out; + return kzalloc_obj(struct iris_inst); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 29814d77c969f..46d8e6fe6baf2 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1291,7 +1291,11 @@ static int iris_hfi_gen2_session_release_buffer(struct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } -static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { +static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { + .sys_init = iris_hfi_gen2_sys_init, + .sys_image_version = iris_hfi_gen2_sys_image_version, + .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, + .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, .session_open = iris_hfi_gen2_session_open, .session_set_config_params = iris_hfi_gen2_session_set_config_params, .session_set_property = iris_hfi_gen2_session_set_property, @@ -1306,13 +1310,6 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_close = iris_hfi_gen2_session_close, }; -static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { - .sys_init = iris_hfi_gen2_sys_init, - .sys_image_version = iris_hfi_gen2_sys_image_version, - .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, - .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, -}; - void iris_hfi_gen2_command_ops_init(struct iris_core *core) { core->hfi_ops = &iris_hfi_gen2_command_ops; @@ -1324,10 +1321,6 @@ struct iris_inst *iris_hfi_gen2_get_instance(void) /* The allocation is intentionally larger than struct iris_inst. */ out = kzalloc_obj(*out); - if (!out) - return NULL; - - out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; return &out->inst; } diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h index 9fa635e27a28d..63dd889c9992a 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -15,8 +15,6 @@ #define DEFAULT_WIDTH 320 #define DEFAULT_HEIGHT 240 -struct iris_hfi_session_ops; - enum iris_fmt_type_out { IRIS_FMT_H264, IRIS_FMT_HEVC, @@ -40,7 +38,6 @@ struct iris_fmt { * @list: used for attach an instance to the core * @core: pointer to core structure * @session_id: id of current video session - * @hfi_session_ops: iris HFI session ops * @ctx_q_lock: lock to serialize queues related ioctls * @lock: lock to seralise forward and reverse threads * @fh: reference of v4l2 file handler @@ -85,7 +82,6 @@ struct iris_inst { struct list_head list; struct iris_core *core; u32 session_id; - const struct iris_hfi_session_ops *hfi_session_ops; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ struct mutex lock; /* lock to serialize forward and reverse threads */ struct v4l2_fh fh; diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/platform/qcom/iris/iris_vb2.c index a2ea2d67f60d0..bf0b8400996ec 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -129,7 +129,7 @@ int iris_vb2_queue_setup(struct vb2_queue *q, if (!inst->once_per_session_set) { inst->once_per_session_set = true; - ret = inst->hfi_session_ops->session_open(inst); + ret = core->hfi_ops->session_open(inst); if (ret) { ret = -EINVAL; dev_err(core->dev, "session open failed\n"); diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index a0bcbeb426a0c..0d93e56de4afd 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -372,7 +372,7 @@ int iris_vdec_streamon_input(struct iris_inst *inst) int iris_vdec_streamon_output(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; int ret; ret = hfi_ops->session_set_config_params(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); @@ -449,7 +449,7 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_vdec_start_cmd(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; enum iris_inst_sub_state clear_sub_state = 0; struct vb2_queue *dst_vq; int ret; @@ -512,7 +512,7 @@ int iris_vdec_start_cmd(struct iris_inst *inst) int iris_vdec_stop_cmd(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; int ret; ret = hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c index c11fee4799cdd..4d886769d958b 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -575,7 +575,7 @@ int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_venc_start_cmd(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; enum iris_inst_sub_state clear_sub_state = 0; struct vb2_queue *dst_vq; int ret; @@ -617,7 +617,7 @@ int iris_venc_start_cmd(struct iris_inst *inst) int iris_venc_stop_cmd(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; int ret; ret = hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 359ff9997bedb..96dc55b1e6860 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -227,7 +227,7 @@ int iris_open(struct file *filp) static void iris_session_close(struct iris_inst *inst) { - const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; bool wait_for_response = true; int ret; From 72b701a268d31ec1bfbfa6dfcd0d8c9222a83794 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:49 +0530 Subject: [PATCH 1201/1330] Revert "FROMLIST: media: qcom: iris: don't use function indirection in gen2-specific code" This reverts commit 3ba6edcae18fae7533b657e975fc26d09f3b4f8d. Signed-off-by: Gourav Kumar (cherry picked from commit 5d1340a71382656ed3499d10d8fdcc9e7383eaaa) (cherry picked from commit 75581f0dd19ec14fca39025a6f8f6d7991668648) --- .../platform/qcom/iris/iris_hfi_gen2_command.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 46d8e6fe6baf2..41ec04d955f16 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1204,19 +1204,19 @@ static u32 iris_hfi_gen2_buf_type_from_driver(u32 domain, enum iris_buffer_type } } -static int iris_hfi_gen2_set_num_comv(struct iris_inst *inst) +static int iris_set_num_comv(struct iris_inst *inst) { u32 num_comv = inst->buffers[BUF_OUTPUT].min_count; if (inst->fw_min_count) num_comv = inst->fw_min_count; - return iris_hfi_gen2_session_set_property(inst, - HFI_PROP_COMV_BUFFER_COUNT, - HFI_HOST_FLAGS_NONE, - HFI_PORT_BITSTREAM, - HFI_PAYLOAD_U32, - &num_comv, sizeof(u32)); + return core->hfi_ops->session_set_property(inst, + HFI_PROP_COMV_BUFFER_COUNT, + HFI_HOST_FLAGS_NONE, + HFI_PORT_BITSTREAM, + HFI_PAYLOAD_U32, + &num_comv, sizeof(u32)); } static void iris_hfi_gen2_get_buffer(u32 domain, struct iris_buffer *buffer, @@ -1248,7 +1248,7 @@ static int iris_hfi_gen2_session_queue_buffer(struct iris_inst *inst, struct iri iris_hfi_gen2_get_buffer(inst->domain, buffer, &hfi_buffer); if (buffer->type == BUF_COMV) { - ret = iris_hfi_gen2_set_num_comv(inst); + ret = iris_set_num_comv(inst); if (ret) return ret; } From 80ed54fb35d26fc18ce13ea0c97822179d09b5b9 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:50 +0530 Subject: [PATCH 1202/1330] Revert "FROMLIST: media: qcom: iris: use common set_preset_registers function" This reverts commit f7c099d95df11961e696cf97f4f2b3eb3f785d24. Signed-off-by: Gourav Kumar (cherry picked from commit ec7aac0eff74e8797d22f68661fc2454f6f82a7d) (cherry picked from commit 265ec195c6d9e0fbf45952d82a1b6bc87cb30cba) --- drivers/media/platform/qcom/iris/iris_platform_gen1.c | 7 +++++++ drivers/media/platform/qcom/iris/iris_platform_gen2.c | 10 ++++++++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 7 +------ drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 -- 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 546f6c025d547..1bbdefc48d718 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -260,6 +260,11 @@ static struct platform_inst_caps platform_inst_cap_sm8250 = { .max_operating_rate = MAXIMUM_FPS, }; +static void iris_set_sm8250_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + 0xB0088); +} + static const struct icc_info sm8250_icc_table[] = { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -338,6 +343,7 @@ const struct iris_platform_data sm8250_data = { .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, + .set_preset_registers = iris_set_sm8250_preset_registers, .icc_tbl = sm8250_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), .clk_rst_tbl = sm8250_clk_reset_table, @@ -391,6 +397,7 @@ const struct iris_platform_data sc7280_data = { .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, + .set_preset_registers = iris_set_sm8250_preset_registers, .icc_tbl = sm8250_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), .bw_tbl_dec = sc7280_bw_table_dec, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 8e98857f76f99..e4cb38cecbb82 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -757,6 +757,11 @@ static struct platform_inst_caps platform_inst_cap_sm8550 = { .max_operating_rate = MAXIMUM_FPS, }; +static void iris_set_sm8550_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + 0xB0088); +} + static int sm8550_init_cb_devs(struct iris_core *core) { const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ @@ -964,6 +969,7 @@ const struct iris_platform_data kaanapali_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu4x_buf_size, .vpu_ops = &iris_vpu4x_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = kaanapali_clk_reset_table, @@ -1049,6 +1055,7 @@ const struct iris_platform_data sm8550_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, .init_cb_devs = sm8550_init_cb_devs, .deinit_cb_devs = sm8550_deinit_cb_devs, .icc_tbl = sm8550_icc_table, @@ -1152,6 +1159,7 @@ const struct iris_platform_data sm8650_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8650_clk_reset_table, @@ -1248,6 +1256,7 @@ const struct iris_platform_data sm8750_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8750_clk_reset_table, @@ -1346,6 +1355,7 @@ const struct iris_platform_data qcs8300_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8550_clk_reset_table, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 96e5b305c5f4a..3e3482d1841d2 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -476,7 +476,7 @@ int iris_vpu_power_on(struct iris_core *core) iris_opp_set_rate(core->dev, freq); - iris_vpu_set_preset_registers(core); + core->iris_platform_data->set_preset_registers(core); iris_vpu_interrupt_init(core); core->intr_status = 0; @@ -493,8 +493,3 @@ int iris_vpu_power_on(struct iris_core *core) return ret; } - -void iris_vpu_set_preset_registers(struct iris_core *core) -{ - writel(0x0, core->reg_base + 0xb0088); -} diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index 09799a375c142..dee3b1349c5e8 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -42,6 +42,4 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core); void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core); u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size); -void iris_vpu_set_preset_registers(struct iris_core *core); - #endif From 040da6242765a1fa5a8965be385a002ed26a9f2c Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:52 +0530 Subject: [PATCH 1203/1330] Revert "FROMLIST: media: qcom: iris: drop pas_id from the iris_platform_data struct" This reverts commit 61333e4328bb6332909aa8afb328965b48885f43. Signed-off-by: Gourav Kumar (cherry picked from commit 41458ecbabf5372b9e4688db94ab8e74ab785944) (cherry picked from commit 59879680d3f517bc0760b5f89bb58ab8534293bb) --- drivers/media/platform/qcom/iris/iris_firmware.c | 7 +++---- drivers/media/platform/qcom/iris/iris_platform_common.h | 2 ++ drivers/media/platform/qcom/iris/iris_platform_gen1.c | 2 ++ drivers/media/platform/qcom/iris/iris_platform_gen2.c | 5 +++++ 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index ec8e5d0d55985..e00cb5a1c8c16 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -17,8 +17,6 @@ #include "iris_core.h" #include "iris_firmware.h" -#define IRIS_PAS_ID 9 - #define MAX_FIRMWARE_NAME_SIZE 128 /* Detect Gen2 firmware by scanning the blob for: @@ -100,6 +98,7 @@ static const struct firmware *iris_detect_firmware(struct iris_core *core, static int iris_load_fw_to_memory(struct iris_core *core) { + u32 pas_id = core->iris_platform_data->pas_id; struct qcom_scm_pas_context *ctx; const struct firmware *firmware = NULL; struct device *dev = core->dev; @@ -119,7 +118,7 @@ static int iris_load_fw_to_memory(struct iris_core *core) dev = core->fw.dev ? : core->dev; - ctx = devm_qcom_scm_pas_context_alloc(dev, IRIS_PAS_ID, mem_phys, res_size); + ctx = devm_qcom_scm_pas_context_alloc(dev, pas_id, mem_phys, res_size); if (!ctx) return -ENOMEM; @@ -189,7 +188,7 @@ int iris_fw_load(struct iris_core *core) cp_config->cp_nonpixel_size); if (ret) { dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); - qcom_scm_pas_shutdown(IRIS_PAS_ID); + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); return ret; } } diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index fd3ad0f16b045..4ca914906ca83 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -12,6 +12,7 @@ struct iris_core; struct iris_inst; +#define IRIS_PAS_ID 9 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ @@ -227,6 +228,7 @@ struct iris_platform_data { unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; + u32 pas_id; struct iris_fmt *inst_iris_fmts; u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 1bbdefc48d718..df8e6bf9430ed 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -360,6 +360,7 @@ const struct iris_platform_data sm8250_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu-1.0/venus.mbn", + .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, @@ -412,6 +413,7 @@ const struct iris_platform_data sc7280_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu20_p1.mbn", + .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index e4cb38cecbb82..f0c4504a9cc61 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -986,6 +986,7 @@ const struct iris_platform_data kaanapali_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu40_p2_s7.mbn", + .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1074,6 +1075,7 @@ const struct iris_platform_data sm8550_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu30_p4.mbn", + .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1178,6 +1180,7 @@ const struct iris_platform_data sm8650_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu33_p4.mbn", + .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1273,6 +1276,7 @@ const struct iris_platform_data sm8750_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu35_p4.mbn", + .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1372,6 +1376,7 @@ const struct iris_platform_data qcs8300_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu30_p4_s6.mbn", + .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_qcs8300, From 1efd9d82f236263b1e50d4ff4640797ca8a93afa Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:53 +0530 Subject: [PATCH 1204/1330] Revert "PENDING: media: iris: add helper to select context bank device" This reverts commit f4c1c6e5a6df14e31fbc82722f83ae47917726b5. Signed-off-by: Gourav Kumar (cherry picked from commit 0c0f1b1738f336a6cb3bf5f1ee261372e9ab1346) (cherry picked from commit 5539ea501edfbc8650e62962cebd996ac28be45a) --- .../media/platform/qcom/iris/iris_buffer.c | 8 ++-- .../media/platform/qcom/iris/iris_hfi_queue.c | 16 ++++--- .../media/platform/qcom/iris/iris_resources.c | 42 ------------------- .../media/platform/qcom/iris/iris_resources.h | 1 - drivers/media/platform/qcom/iris/iris_vidc.c | 4 +- 5 files changed, 13 insertions(+), 58 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index d927b392fb762..1d53c7414b754 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -336,7 +336,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, enum iris_buffer_type buffer_type, u32 index) { struct iris_buffers *buffers = &inst->buffers[buffer_type]; - struct device *dev = iris_get_cb_dev(inst, buffer_type); + struct iris_core *core = inst->core; struct iris_buffer *buffer; if (!buffers->size) @@ -352,7 +352,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, buffer->buffer_size = buffers->size; buffer->dma_attrs = DMA_ATTR_WRITE_COMBINE | DMA_ATTR_NO_KERNEL_MAPPING; - buffer->kvaddr = dma_alloc_attrs(dev, buffer->buffer_size, + buffer->kvaddr = dma_alloc_attrs(core->dev, buffer->buffer_size, &buffer->device_addr, GFP_KERNEL, buffer->dma_attrs); if (!buffer->kvaddr) { kfree(buffer); @@ -489,10 +489,10 @@ int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer) { - struct device *dev = iris_get_cb_dev(inst, buffer->type); + struct iris_core *core = inst->core; list_del(&buffer->list); - dma_free_attrs(dev, buffer->buffer_size, buffer->kvaddr, + dma_free_attrs(core->dev, buffer->buffer_size, buffer->kvaddr, buffer->device_addr, buffer->dma_attrs); kfree(buffer); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_queue.c b/drivers/media/platform/qcom/iris/iris_hfi_queue.c index f465ff00a9ba3..bf6db23b53e21 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_queue.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_queue.c @@ -245,26 +245,25 @@ static void iris_hfi_queue_deinit(struct iris_iface_q_info *iface_q) int iris_hfi_queues_init(struct iris_core *core) { - struct device *dev = core->dev_np ? core->dev_np : core->dev; struct iris_hfi_queue_table_header *q_tbl_hdr; u32 queue_size; /* Iris hardware requires 4K queue alignment */ queue_size = ALIGN((sizeof(*q_tbl_hdr) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ)), SZ_4K); - core->iface_q_table_vaddr = dma_alloc_attrs(dev, queue_size, + core->iface_q_table_vaddr = dma_alloc_attrs(core->dev, queue_size, &core->iface_q_table_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->iface_q_table_vaddr) { - dev_err(dev, "queues alloc and map failed\n"); + dev_err(core->dev, "queues alloc and map failed\n"); return -ENOMEM; } - core->sfr_vaddr = dma_alloc_attrs(dev, SFR_SIZE, + core->sfr_vaddr = dma_alloc_attrs(core->dev, SFR_SIZE, &core->sfr_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->sfr_vaddr) { - dev_err(dev, "sfr alloc and map failed\n"); - dma_free_attrs(dev, sizeof(*q_tbl_hdr), core->iface_q_table_vaddr, + dev_err(core->dev, "sfr alloc and map failed\n"); + dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); return -ENOMEM; } @@ -292,7 +291,6 @@ int iris_hfi_queues_init(struct iris_core *core) void iris_hfi_queues_deinit(struct iris_core *core) { - struct device *dev = core->dev_np ? core->dev_np : core->dev; u32 queue_size; if (!core->iface_q_table_vaddr) @@ -302,7 +300,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) iris_hfi_queue_deinit(&core->message_queue); iris_hfi_queue_deinit(&core->command_queue); - dma_free_attrs(dev, SFR_SIZE, core->sfr_vaddr, + dma_free_attrs(core->dev, SFR_SIZE, core->sfr_vaddr, core->sfr_daddr, DMA_ATTR_WRITE_COMBINE); core->sfr_vaddr = NULL; @@ -311,7 +309,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) queue_size = ALIGN(sizeof(struct iris_hfi_queue_table_header) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K); - dma_free_attrs(dev, queue_size, core->iface_q_table_vaddr, + dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); core->iface_q_table_vaddr = NULL; diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c index b10884eb3ac64..b53a66d8851b6 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -13,7 +13,6 @@ #include #include "iris_core.h" -#include "iris_instance.h" #include "iris_resources.h" #define BW_THRESHOLD 50000 @@ -176,44 +175,3 @@ struct device *iris_create_cb_dev(struct iris_core *core, const char *name, cons return ERR_PTR(ret); } - -struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_type buffer_type) -{ - struct iris_core *core = inst->core; - struct device *dev = NULL; - - switch (buffer_type) { - case BUF_INPUT: - if (inst->domain == DECODER) - dev = core->dev_bs; - else - dev = core->dev_p; - break; - case BUF_OUTPUT: - if (inst->domain == DECODER) - dev = core->dev_p; - else - dev = core->dev_bs; - break; - case BUF_BIN: - dev = core->dev_bs; - break; - case BUF_DPB: - case BUF_PARTIAL: - case BUF_SCRATCH_2: - case BUF_VPSS: - dev = core->dev_p; - break; - case BUF_ARP: - case BUF_COMV: - case BUF_LINE: - case BUF_NON_COMV: - case BUF_PERSIST: - dev = core->dev_np; - break; - default: - dev_err(core->dev, "invalid buffer type: %d\n", buffer_type); - } - - return dev ? dev : core->dev; -} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h index e6a6dc24a7f12..4a494627ff238 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -16,6 +16,5 @@ int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id); -struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_type buffer_type); #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 96dc55b1e6860..f7c3ac9f96ce3 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -108,7 +108,7 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_ src_vq->drv_priv = inst; src_vq->buf_struct_size = sizeof(struct iris_buffer); src_vq->min_reqbufs_allocation = MIN_BUFFERS; - src_vq->dev = iris_get_cb_dev(inst, BUF_INPUT); + src_vq->dev = inst->core->dev; src_vq->lock = &inst->ctx_q_lock; ret = vb2_queue_init(src_vq); if (ret) @@ -122,7 +122,7 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_ dst_vq->drv_priv = inst; dst_vq->buf_struct_size = sizeof(struct iris_buffer); dst_vq->min_reqbufs_allocation = MIN_BUFFERS; - dst_vq->dev = iris_get_cb_dev(inst, BUF_OUTPUT); + dst_vq->dev = inst->core->dev; dst_vq->lock = &inst->ctx_q_lock; return vb2_queue_init(dst_vq); From b10e9876dfd0b95abfa22bafb704dfa70f8b479f Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:55 +0530 Subject: [PATCH 1205/1330] Revert "PENDING: media: iris: add context bank devices using iommu-map" This reverts commit bf97a5be01bc4419f0a95a296f1eddd12bdf4428. Signed-off-by: Gourav Kumar (cherry picked from commit ab7d407f06b414620d17e3ef01bb3fb660ad0506) (cherry picked from commit 54de85886d71d702151cc9e59653a0e10e2c10f9) --- drivers/media/platform/qcom/iris/iris_core.h | 6 ---- .../platform/qcom/iris/iris_platform_common.h | 4 +-- drivers/media/platform/qcom/iris/iris_probe.c | 31 +++-------------- .../media/platform/qcom/iris/iris_resources.c | 34 ------------------- .../media/platform/qcom/iris/iris_resources.h | 1 - 5 files changed, 6 insertions(+), 70 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index c85fd7f292467..ef081ccc3429d 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -34,9 +34,6 @@ enum domain_type { * struct iris_core - holds core parameters valid for all instances * * @dev: reference to device structure - * @dev_np: reference to non-pixel context bank device structure - * @dev_p: reference to pixel context bank device structure - * @dev_bs: reference to bitstream context bank device structure * @reg_base: IO memory base address * @irq: iris irq * @v4l2_dev: a holder for v4l2 device structure @@ -80,9 +77,6 @@ enum domain_type { struct iris_core { struct device *dev; - struct device *dev_np; - struct device *dev_p; - struct device *dev_bs; void __iomem *reg_base; int irq; struct v4l2_device v4l2_dev; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 4ca914906ca83..f48f0113d7cc3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -208,9 +208,7 @@ struct iris_platform_data { struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; - - int (*init_cb_devs)(struct iris_core *core); - void (*deinit_cb_devs)(struct iris_core *core); + void (*set_preset_registers)(struct iris_core *core); const struct icc_info *icc_tbl; unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index fe4bef12f7fbe..4b33a3f6cfb03 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -124,20 +124,6 @@ static int iris_init_resets(struct iris_core *core) core->iris_platform_data->controller_rst_tbl_size); } -static int iris_init_cb_devs(struct iris_core *core) -{ - if (core->iris_platform_data->init_cb_devs) - return core->iris_platform_data->init_cb_devs(core); - - return 0; -} - -static void iris_deinit_cb_devs(struct iris_core *core) -{ - if (core->iris_platform_data->deinit_cb_devs) - core->iris_platform_data->deinit_cb_devs(core); -} - static int iris_init_resources(struct iris_core *core) { int ret; @@ -208,7 +194,6 @@ static void iris_remove(struct platform_device *pdev) return; iris_core_deinit(core); - iris_deinit_cb_devs(core); video_unregister_device(core->vdev_dec); video_unregister_device(core->vdev_enc); @@ -275,13 +260,11 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; - ret = iris_init_cb_devs(core); - if (ret) - return ret; + iris_session_init_caps(core); ret = v4l2_device_register(dev, &core->v4l2_dev); if (ret) - goto err_deinit_cb; + return ret; ret = iris_register_video_device(core, DECODER); if (ret) @@ -295,11 +278,9 @@ static int iris_probe(struct platform_device *pdev) dma_mask = core->iris_platform_data->dma_mask; - if (device_iommu_mapped(core->dev)) { - ret = dma_set_mask_and_coherent(core->dev, dma_mask); - if (ret) - goto err_vdev_unreg_enc; - } + ret = dma_set_mask_and_coherent(dev, dma_mask); + if (ret) + goto err_vdev_unreg_enc; dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32)); @@ -318,8 +299,6 @@ static int iris_probe(struct platform_device *pdev) video_unregister_device(core->vdev_dec); err_v4l2_unreg: v4l2_device_unregister(&core->v4l2_dev); -err_deinit_cb: - iris_deinit_cb_devs(core); return ret; } diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c index b53a66d8851b6..773f6548370a2 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -142,36 +141,3 @@ int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type return 0; } - -struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id) -{ - struct platform_device *pdev; - int ret; - - pdev = platform_device_alloc(name, 0); - if (!pdev) - return ERR_PTR(-ENOMEM); - - pdev->dev.parent = core->dev; - - ret = platform_device_add(pdev); - if (ret) { - platform_device_put(pdev); - return ERR_PTR(ret); - } - - ret = of_dma_configure_id(&pdev->dev, core->dev->of_node, true, f_id); - if (ret) - goto error_unregister; - - ret = dma_set_mask_and_coherent(&pdev->dev, core->iris_platform_data->dma_mask); - if (ret) - goto error_unregister; - - return &pdev->dev; - -error_unregister: - platform_device_unregister(to_platform_device(&pdev->dev)); - - return ERR_PTR(ret); -} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h index 4a494627ff238..6bfbd2dc6db09 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -15,6 +15,5 @@ int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); -struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id); #endif From cd9ee1687b8df0ef7803cd622255263f9ee621dc Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:56 +0530 Subject: [PATCH 1206/1330] Revert "PENDING: media: iris: enable sm8550 context banks via init_cb_devs" This reverts commit 9bfd102524eb4481e62b60c81d1fa36091f09507. Signed-off-by: Gourav Kumar (cherry picked from commit deb4c98fc8f78da8020e392b1d201ac744b9b55a) (cherry picked from commit 168bddc9a9e3bdc3c059b47627f2dd05f7abc4fe) --- .../platform/qcom/iris/iris_platform_gen2.c | 43 ------------------- 1 file changed, 43 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index f0c4504a9cc61..e0c99d28762cd 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -762,47 +762,6 @@ static void iris_set_sm8550_preset_registers(struct iris_core *core) writel(0x0, core->reg_base + 0xB0088); } -static int sm8550_init_cb_devs(struct iris_core *core) -{ - const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ - const u32 f_id_p = 1; /* IRIS_PIXEL */ - struct device *dev; - - dev = iris_create_cb_dev(core, "iris_non_pixel", &f_id_np); - if (IS_ERR(dev)) - return PTR_ERR(dev); - - core->dev_np = dev; - core->dev_bs = core->dev_np; - - dev = iris_create_cb_dev(core, "iris_pixel", &f_id_p); - if (IS_ERR(dev)) - goto err_unreg_dev_np; - - core->dev_p = dev; - - return 0; - -err_unreg_dev_np: - platform_device_unregister(to_platform_device(core->dev_np)); - core->dev_np = NULL; - core->dev_bs = NULL; - - return PTR_ERR(dev); -} - -static void sm8550_deinit_cb_devs(struct iris_core *core) -{ - if (core->dev_np) - platform_device_unregister(to_platform_device(core->dev_np)); - if (core->dev_p) - platform_device_unregister(to_platform_device(core->dev_p)); - - core->dev_np = NULL; - core->dev_bs = NULL; - core->dev_p = NULL; -} - static const struct icc_info sm8550_icc_table[] = { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -1057,8 +1016,6 @@ const struct iris_platform_data sm8550_data = { .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .set_preset_registers = iris_set_sm8550_preset_registers, - .init_cb_devs = sm8550_init_cb_devs, - .deinit_cb_devs = sm8550_deinit_cb_devs, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8550_clk_reset_table, From c8bcfc5a212ed34533ce6bfe4f77ed9e4f22b13b Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:25:57 +0530 Subject: [PATCH 1207/1330] Revert "FROMLIST: media: iris: add FPS calculation and VPP FW overhead in frequency formula" This reverts commit 573b0f8af6ef1ba0c060945950e8a6ebaef8a8f5. Signed-off-by: Gourav Kumar (cherry picked from commit 3f12bb5c64616a500502e3b68b3fd900e0ffdfc6) (cherry picked from commit b746299e5386cedbd758487bdb2c3a91fc532555) --- .../media/platform/qcom/iris/iris_instance.h | 4 ---- drivers/media/platform/qcom/iris/iris_vdec.c | 20 ------------------- drivers/media/platform/qcom/iris/iris_vpu2.c | 2 +- .../platform/qcom/iris/iris_vpu_common.c | 6 +----- 4 files changed, 2 insertions(+), 30 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h index 63dd889c9992a..16965150f427b 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -67,8 +67,6 @@ struct iris_fmt { * @metadata_idx: index for metadata buffer * @codec: codec type * @last_buffer_dequeued: a flag to indicate that last buffer is sent by driver - * @last_buf_ns: start time of received input buffer for current one second FPS window - * @frame_counter: input buffer counter for current one second FPS window * @frame_rate: frame rate of current instance * @operating_rate: operating rate of current instance * @hfi_rc_type: rate control type @@ -111,8 +109,6 @@ struct iris_inst { u32 metadata_idx; u32 codec; bool last_buffer_dequeued; - u64 last_buf_ns; - u32 frame_counter; u32 frame_rate; u32 operating_rate; u32 hfi_rc_type; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index 0d93e56de4afd..f05f74e085f7d 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -54,7 +54,6 @@ int iris_vdec_inst_init(struct iris_inst *inst) f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT); inst->buffers[BUF_OUTPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage; - inst->frame_rate = MAXIMUM_FPS; memcpy(&inst->fw_caps[0], &core->inst_fw_caps_dec[0], INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap)); @@ -365,8 +364,6 @@ int iris_vdec_streamon_input(struct iris_inst *inst) if (ret) return ret; - inst->frame_counter = 0; - return iris_process_streamon_input(inst); } @@ -409,7 +406,6 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) { struct iris_buffer *buf = to_iris_buffer(vbuf); struct vb2_buffer *vb2 = &vbuf->vb2_buf; - u64 cur_buf_ns, delta_ns; struct vb2_queue *q; int ret; @@ -426,22 +422,6 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) return 0; } - if (buf->type == BUF_INPUT) { - cur_buf_ns = ktime_get_ns(); - - if (!inst->frame_counter) - inst->last_buf_ns = cur_buf_ns; - - inst->frame_counter++; - delta_ns = cur_buf_ns - inst->last_buf_ns; - - if (delta_ns >= NSEC_PER_SEC) { - inst->frame_rate = clamp_t(u32, inst->frame_counter, DEFAULT_FPS, - MAXIMUM_FPS); - inst->frame_counter = 0; - } - } - iris_scale_power(inst); return iris_queue_buffer(inst, buf); diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c index b8714dcbad10a..01ef40f389574 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -18,7 +18,7 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) struct v4l2_format *inp_f = inst->fmt_src; u32 mbs_per_second, mbpf, height, width; unsigned long vpp_freq, vsp_freq; - u32 fps = inst->frame_rate; + u32 fps = DEFAULT_FPS; width = max(inp_f->fmt.pix_mp.width, inst->crop.width); height = max(inp_f->fmt.pix_mp.height, inst->crop.height); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 3e3482d1841d2..69e6126dc4d95 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -420,7 +420,7 @@ u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_siz u32 height, width, mbs_per_second, mbpf; u64 fw_cycles, fw_vpp_cycles; u64 vsp_cycles, vpp_cycles; - u32 fps = inst->frame_rate; + u32 fps = DEFAULT_FPS; width = max(inp_f->fmt.pix_mp.width, inst->crop.width); height = max(inp_f->fmt.pix_mp.height, inst->crop.height); @@ -439,10 +439,6 @@ u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_siz if (inst->fw_caps[PIPE].value > 1) vpp_cycles += div_u64(vpp_cycles * 59, 1000); - /* 1.05 is VPP FW overhead */ - if (inst->fw_caps[STAGE].value == STAGE_2) - vpp_cycles += mult_frac(vpp_cycles, 5, 100); - vsp_cycles = fps * data_size * 8; vsp_cycles = div_u64(vsp_cycles, 2); /* VSP FW overhead 1.05 */ From 565b36c0d4da3401d493bf37340037c92c2eb917 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:26:00 +0530 Subject: [PATCH 1208/1330] Revert "PENDING: media: iris: update MDT PAS load call for new API" This reverts commit fe0cd11ec5ac3ac3c2595cc5f71c9a0e0daa010e. Signed-off-by: Gourav Kumar (cherry picked from commit c76add22a18ad8866dfc38d61bb8fbcffc57059d) (cherry picked from commit 498273ef064314baa873a6a812ce4b39d2ac5018) --- drivers/media/platform/qcom/iris/iris_firmware.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index e00cb5a1c8c16..5b14f2da1b3c4 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -107,6 +107,7 @@ static int iris_load_fw_to_memory(struct iris_core *core) const char *fw_name; size_t res_size; ssize_t fw_size; + void *mem_virt; int ret; ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); @@ -136,16 +137,22 @@ static int iris_load_fw_to_memory(struct iris_core *core) goto err_release_fw; } - ret = qcom_mdt_pas_load(ctx, firmware, fw_name, NULL); + mem_virt = memremap(mem_phys, res_size, MEMREMAP_WC); + if (!mem_virt) { + ret = -ENOMEM; + goto err_release_fw; + } + + ret = qcom_mdt_pas_load(ctx, firmware, fw_name, mem_virt, NULL); qcom_scm_pas_metadata_release(ctx); if (ret) - goto err_release_fw; + goto err_mem_unmap; if (core->fw.iommu_domain) { ret = iommu_map(core->fw.iommu_domain, 0, mem_phys, res_size, IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); if (ret) - goto err_release_fw; + goto err_mem_unmap; } ret = qcom_scm_pas_prepare_and_auth_reset(ctx); @@ -158,6 +165,8 @@ static int iris_load_fw_to_memory(struct iris_core *core) err_iommu_unmap: iommu_unmap(core->fw.iommu_domain, 0, res_size); +err_mem_unmap: + memunmap(mem_virt); err_release_fw: release_firmware(firmware); From f9eacba8e104060811a3055e1134c271a4b5e8e6 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:26:02 +0530 Subject: [PATCH 1209/1330] Revert "FROMLIST: media: iris: Enable Secure PAS support with IOMMU managed by Linux" This reverts commit fb6622cf93fd939918247f3c785df56f9e14ff4d. Signed-off-by: Gourav Kumar (cherry picked from commit 627c6e193bef230548bd212e0f27f869c002ab36) (cherry picked from commit 6e0b2867ade1fe33ff57933943f729cb594fea2d) --- drivers/media/platform/qcom/iris/iris_core.c | 9 +- drivers/media/platform/qcom/iris/iris_core.h | 5 - .../media/platform/qcom/iris/iris_firmware.c | 135 ++---------------- .../media/platform/qcom/iris/iris_firmware.h | 2 - 4 files changed, 13 insertions(+), 138 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c index f61ce89e1be73..7b863e067551d 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -18,7 +18,6 @@ void iris_core_deinit(struct iris_core *core) if (core->state != IRIS_CORE_DEINIT) { iris_fw_unload(core); iris_vpu_power_off(core); - iris_fw_deinit(core); iris_hfi_queues_deinit(core); core->state = IRIS_CORE_DEINIT; } @@ -68,13 +67,9 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_queue_deinit; - ret = iris_fw_init(core); - if (ret) - goto error_power_off; - ret = iris_fw_load(core); if (ret) - goto error_firmware_deinit; + goto error_power_off; ret = iris_vpu_boot_firmware(core); if (ret) @@ -96,8 +91,6 @@ int iris_core_init(struct iris_core *core) error_unload_fw: iris_fw_unload(core); -error_firmware_deinit: - iris_fw_deinit(core); error_power_off: iris_vpu_power_off(core); error_queue_deinit: diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index ef081ccc3429d..fb194c967ad4f 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -82,11 +82,6 @@ struct iris_core { struct v4l2_device v4l2_dev; struct video_device *vdev_dec; struct video_device *vdev_enc; - struct video_firmware { - struct device *dev; - struct qcom_scm_pas_context *ctx; - struct iommu_domain *iommu_domain; - } fw; const struct v4l2_file_operations *iris_v4l2_file_ops; const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops_dec; const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops_enc; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index 5b14f2da1b3c4..3aa1991042b61 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -3,15 +3,10 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ -#include #include #include -#include -#include #include -#include #include -#include #include #include "iris_core.h" @@ -99,7 +94,6 @@ static const struct firmware *iris_detect_firmware(struct iris_core *core, static int iris_load_fw_to_memory(struct iris_core *core) { u32 pas_id = core->iris_platform_data->pas_id; - struct qcom_scm_pas_context *ctx; const struct firmware *firmware = NULL; struct device *dev = core->dev; struct resource res; @@ -117,19 +111,9 @@ static int iris_load_fw_to_memory(struct iris_core *core) mem_phys = res.start; res_size = resource_size(&res); - dev = core->fw.dev ? : core->dev; - - ctx = devm_qcom_scm_pas_context_alloc(dev, pas_id, mem_phys, res_size); - if (!ctx) - return -ENOMEM; - - ctx->use_tzmem = core->fw.dev; - - firmware = iris_detect_firmware(core, &fw_name); - if (IS_ERR(firmware)) - return PTR_ERR(firmware); - - core->iris_firmware_data = core->iris_firmware_desc->firmware_data; + ret = request_firmware(&firmware, fw_name, dev); + if (ret) + return ret; fw_size = qcom_mdt_get_size(firmware); if (fw_size < 0 || res_size < (size_t)fw_size) { @@ -143,29 +127,9 @@ static int iris_load_fw_to_memory(struct iris_core *core) goto err_release_fw; } - ret = qcom_mdt_pas_load(ctx, firmware, fw_name, mem_virt, NULL); - qcom_scm_pas_metadata_release(ctx); - if (ret) - goto err_mem_unmap; - - if (core->fw.iommu_domain) { - ret = iommu_map(core->fw.iommu_domain, 0, mem_phys, res_size, - IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); - if (ret) - goto err_mem_unmap; - } - - ret = qcom_scm_pas_prepare_and_auth_reset(ctx); - if (ret) - goto err_iommu_unmap; - - core->fw.ctx = ctx; - - return ret; + ret = qcom_mdt_load(dev, firmware, fw_name, + pas_id, mem_virt, mem_phys, res_size, NULL); -err_iommu_unmap: - iommu_unmap(core->fw.iommu_domain, 0, res_size); -err_mem_unmap: memunmap(mem_virt); err_release_fw: release_firmware(firmware); @@ -189,6 +153,12 @@ int iris_fw_load(struct iris_core *core) return ret; } + ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id); + if (ret) { + dev_err(core->dev, "auth and reset failed: %d\n", ret); + return ret; + } + for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { cp_config = &core->iris_platform_data->tz_cp_config_data[i]; ret = qcom_scm_mem_protect_video_var(cp_config->cp_start, @@ -207,91 +177,10 @@ int iris_fw_load(struct iris_core *core) int iris_fw_unload(struct iris_core *core) { - struct qcom_scm_pas_context *ctx = core->fw.ctx; - int ret; - - if (!ctx) - return -EINVAL; - - ret = qcom_scm_pas_shutdown(ctx->pas_id); - if (core->fw.iommu_domain) - iommu_unmap(core->fw.iommu_domain, 0, ctx->mem_size); - - core->fw.ctx = NULL; - return ret; + return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); } int iris_set_hw_state(struct iris_core *core, bool resume) { return qcom_scm_set_remote_state(resume, 0); } - -int iris_fw_init(struct iris_core *core) -{ - struct platform_device_info info; - struct iommu_domain *iommu_dom; - struct platform_device *pdev; - struct device_node *np; - int ret; - - np = of_get_child_by_name(core->dev->of_node, "video-firmware"); - if (!np) - return 0; - - memset(&info, 0, sizeof(info)); - info.fwnode = &np->fwnode; - info.parent = core->dev; - info.name = np->name; - info.dma_mask = DMA_BIT_MASK(32); - - pdev = platform_device_register_full(&info); - if (IS_ERR(pdev)) { - of_node_put(np); - return PTR_ERR(pdev); - } - - pdev->dev.of_node = np; - - ret = of_dma_configure(&pdev->dev, np, true); - if (ret) - goto err_unregister; - - core->fw.dev = &pdev->dev; - - iommu_dom = iommu_get_domain_for_dev(core->fw.dev); - if (!iommu_dom) { - ret = -EINVAL; - goto err_unset_fw_dev; - } - - ret = iommu_attach_device(iommu_dom, core->fw.dev); - if (ret) - goto err_unset_fw_dev; - - core->fw.iommu_domain = iommu_dom; - - of_node_put(np); - - return 0; - -err_unset_fw_dev: - core->fw.dev = NULL; -err_unregister: - platform_device_unregister(pdev); - of_node_put(np); - return ret; -} - -void iris_fw_deinit(struct iris_core *core) -{ - if (!core->fw.dev) - return; - - if (core->fw.iommu_domain) { - iommu_detach_device(core->fw.iommu_domain, core->fw.dev); - core->fw.iommu_domain = NULL; - } - - platform_device_unregister(to_platform_device(core->fw.dev)); - core->fw.dev = NULL; -} diff --git a/drivers/media/platform/qcom/iris/iris_firmware.h b/drivers/media/platform/qcom/iris/iris_firmware.h index adde461099667..e833ecd348871 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.h +++ b/drivers/media/platform/qcom/iris/iris_firmware.h @@ -11,7 +11,5 @@ struct iris_core; int iris_fw_load(struct iris_core *core); int iris_fw_unload(struct iris_core *core); int iris_set_hw_state(struct iris_core *core, bool resume); -int iris_fw_init(struct iris_core *core); -void iris_fw_deinit(struct iris_core *core); #endif From c6db09ea435f7a8ca6dd7d6b4ccc30f1f7ccfed3 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Sat, 23 May 2026 09:26:03 +0530 Subject: [PATCH 1210/1330] Revert "FROMLIST: media: iris: Add platform data for kaanapali" This reverts commit 1a7aeec169892b24bcce1d93e4f1c72e4516c9ed. Signed-off-by: Gourav Kumar (cherry picked from commit b525af135fe540899c6373929b4c163ac9cf9ff4) (cherry picked from commit 3891a7eddb8f93f6f3b3c805eef7e1d04d9be936) --- .../platform/qcom/iris/iris_platform_common.h | 1 - .../platform/qcom/iris/iris_platform_gen2.c | 88 ------------------- .../qcom/iris/iris_platform_kaanapali.h | 63 ------------- drivers/media/platform/qcom/iris/iris_probe.c | 4 - 4 files changed, 156 deletions(-) delete mode 100644 drivers/media/platform/qcom/iris/iris_platform_kaanapali.h diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index f48f0113d7cc3..10c601517d34a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -41,7 +41,6 @@ enum pipe_type { PIPE_4 = 4, }; -extern const struct iris_platform_data kaanapali_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index e0c99d28762cd..5da90d47f9c6e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -12,7 +12,6 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" -#include "iris_platform_kaanapali.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" @@ -922,93 +921,6 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { BUF_SCRATCH_2, }; -const struct iris_platform_data kaanapali_data = { - .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, - .get_vpu_buffer_size = iris_vpu4x_buf_size, - .vpu_ops = &iris_vpu4x_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = kaanapali_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = kaanapali_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = kaanapali_clk_table, - .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table), - .opp_clk_tbl = kaanapali_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu40_p2_s7.mbn", - .pas_id = IRIS_PAS_ID, - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data = tz_cp_config_kaanapali, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali), - .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, - .ubwc_config = &ubwc_config_sm8550, - .num_vpp_pipe = 2, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((8192 * 4352) / 256) * 60, - .dec_input_config_params_default = - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc = - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 = - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_output_config_params = - sm8550_vdec_output_config_params, - .dec_output_config_params_size = - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params = - sm8550_venc_input_config_params, - .enc_input_config_params_size = - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params = - sm8550_venc_output_config_params, - .enc_output_config_params_size = - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop = sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), - .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - - .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), -}; - const struct iris_platform_data sm8550_data = { .get_instance = iris_hfi_gen2_get_instance, .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h deleted file mode 100644 index 247fb9d7cb632..0000000000000 --- a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __IRIS_PLATFORM_KAANAPALI_H__ -#define __IRIS_PLATFORM_KAANAPALI_H__ - -#define VIDEO_REGION_VM0_SECURE_NP_ID 1 -#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 - -static const char *const kaanapali_clk_reset_table[] = { - "bus0", - "bus1", - "core_freerun_reset", - "vcodec0_core_freerun_reset", -}; - -static const char *const kaanapali_pmdomain_table[] = { - "venus", - "vcodec0", - "vpp0", - "vpp1", - "apv", -}; - -static const struct platform_clk_data kaanapali_clk_table[] = { - { IRIS_AXI_CLK, "iface" }, - { IRIS_CTRL_CLK, "core" }, - { IRIS_HW_CLK, "vcodec0_core" }, - { IRIS_AXI1_CLK, "iface1" }, - { IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, - { IRIS_BSE_HW_CLK, "vcodec_bse" }, - { IRIS_VPP0_HW_CLK, "vcodec_vpp0" }, - { IRIS_VPP1_HW_CLK, "vcodec_vpp1" }, - { IRIS_APV_HW_CLK, "vcodec_apv" }, -}; - -static const char *const kaanapali_opp_clk_table[] = { - "vcodec0_core", - "vcodec_apv", - "vcodec_bse", - "core", - NULL, -}; - -static struct tz_cp_config tz_cp_config_kaanapali[] = { - { - .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID, - .cp_size = 0, - .cp_nonpixel_start = 0x01000000, - .cp_nonpixel_size = 0x24800000, - }, - { - .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID, - .cp_size = 0, - .cp_nonpixel_start = 0x25800000, - .cp_nonpixel_size = 0xda400000, - }, -}; - -#endif /* __IRIS_PLATFORM_KAANAPALI_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 4b33a3f6cfb03..9b35b85aa9665 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -349,10 +349,6 @@ static const struct dev_pm_ops iris_pm_ops = { }; static const struct of_device_id iris_dt_match[] = { - { - .compatible = "qcom,kaanapali-iris", - .data = &kaanapali_data, - }, { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, From c066a46fb116345d39aff9fedac29a4481009c6f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:05 +0200 Subject: [PATCH 1211/1330] FROMGIT: media: iris: retrieve UBWC platform configuration Specifying UBWC data in each driver doesn't scale and is prone to errors. Request UBWC data from the central database in preparation to using it through the rest of the driver. Link: https://lore.kernel.org/linux-media/20260507-iris-ubwc-v5-1-e9a3aee53c49@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit d22d52faca4d25705413d1761ca9b0fa8c9a6507) (cherry picked from commit bde45368a1321dc2825912928525657eb75479d0) --- drivers/media/platform/qcom/iris/iris_core.h | 4 ++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index fb194c967ad4f..d10a03aa5685a 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -30,6 +30,8 @@ enum domain_type { DECODER = BIT(1), }; +struct qcom_ubwc_cfg_data; + /** * struct iris_core - holds core parameters valid for all instances * @@ -52,6 +54,7 @@ enum domain_type { * @resets: table of iris reset clocks * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data + * @ubwc_cfg: UBWC configuration for the platform * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory @@ -95,6 +98,7 @@ struct iris_core { struct reset_control_bulk_data *resets; struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; + const struct qcom_ubwc_cfg_data *ubwc_cfg; enum iris_core_state state; dma_addr_t iface_q_table_daddr; dma_addr_t sfr_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 9b35b85aa9665..17bb11513648a 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -245,6 +245,10 @@ static int iris_probe(struct platform_device *pdev) core->iris_platform_data = of_device_get_match_data(core->dev); + core->ubwc_cfg = qcom_ubwc_config_get_data(); + if (IS_ERR(core->ubwc_cfg)) + return PTR_ERR(core->ubwc_cfg); + ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr, iris_hfi_isr_handler, IRQF_TRIGGER_HIGH, "iris", core); if (ret) From 0bddebabee9ac44d63359d8fe83274fb9fef30de Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:06 +0200 Subject: [PATCH 1212/1330] FROMGIT: media: iris: don't specify min_acc_length in the source code The min_acc length can be calculated from the platform UBWC configuration. Use the freshly introduced helper and calculate min_acc length based on the platform UBWC configuration instead of specifying it directly in the source. Link: https://lore.kernel.org/linux-media/20260507-iris-ubwc-v5-2-e9a3aee53c49@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 82ededb5f93a617ad0773560f39526dc8f2c46dd) (cherry picked from commit 85806d84a9774e473708446013efe91c5632a59d) --- drivers/media/platform/qcom/iris/iris_platform_common.h | 9 +++++++++ drivers/media/platform/qcom/iris/iris_platform_gen2.c | 1 - 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 10c601517d34a..27231423046ed 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -75,6 +75,15 @@ struct tz_cp_config { u32 cp_nonpixel_size; }; +struct ubwc_config_data { + u32 max_channels; + u32 highest_bank_bit; + u32 bank_swzl_level; + u32 bank_swz2_level; + u32 bank_swz3_level; + u32 bank_spreading; +}; + struct platform_inst_caps { u32 min_frame_width; u32 max_frame_width; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 5da90d47f9c6e..01c6ffa7e084d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -792,7 +792,6 @@ static const char * const sm8550_opp_clk_table[] = { static struct ubwc_config_data ubwc_config_sm8550 = { .max_channels = 8, - .mal_length = 32, .highest_bank_bit = 16, .bank_swzl_level = 0, .bank_swz2_level = 1, From b0b9ab510070e82327afd47d6f54cc4c1a336825 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:07 +0200 Subject: [PATCH 1213/1330] FROMGIT: media: iris: don't specify highest_bank_bit in the source code The highest_bank_bit param is specified both in the Iris driver and in the platform UBWC config. Use the platform UBWC configuration instead of specifying it directly in the source. Link: https://lore.kernel.org/linux-media/20260507-iris-ubwc-v5-3-e9a3aee53c49@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 42c7164efbfcf00a630fe4e61de73f5952ab0dc8) (cherry picked from commit 57c10f2f26173bc7bdcb971a1d78d937eb979d32) --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 - drivers/media/platform/qcom/iris/iris_platform_gen2.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 27231423046ed..0b5302fd10f98 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -77,7 +77,6 @@ struct tz_cp_config { struct ubwc_config_data { u32 max_channels; - u32 highest_bank_bit; u32 bank_swzl_level; u32 bank_swz2_level; u32 bank_swz3_level; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 01c6ffa7e084d..bdeb92e0b7bc2 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -792,7 +792,6 @@ static const char * const sm8550_opp_clk_table[] = { static struct ubwc_config_data ubwc_config_sm8550 = { .max_channels = 8, - .highest_bank_bit = 16, .bank_swzl_level = 0, .bank_swz2_level = 1, .bank_swz3_level = 1, From 04b60b1a59aee3ffba204350b2e3917caf9b9f48 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:08 +0200 Subject: [PATCH 1214/1330] FROMGIT: media: iris: don't specify ubwc_swizzle in the source code The UBWC swizzle is specified both in the Iris driver and in the platform UBWC config. Use the platform UBWC configuration instead of specifying it directly in the source. Link: https://lore.kernel.org/linux-media/20260507-iris-ubwc-v5-4-e9a3aee53c49@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit c14b4f92b31a769404e4245941b313d0a6de4f1f) (cherry picked from commit 672b69c2f368576d002c84a46b602b545b21a33b) --- drivers/media/platform/qcom/iris/iris_platform_common.h | 3 --- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 0b5302fd10f98..b88231178fd75 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -77,9 +77,6 @@ struct tz_cp_config { struct ubwc_config_data { u32 max_channels; - u32 bank_swzl_level; - u32 bank_swz2_level; - u32 bank_swz3_level; u32 bank_spreading; }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index bdeb92e0b7bc2..8072f430bd268 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -792,9 +792,6 @@ static const char * const sm8550_opp_clk_table[] = { static struct ubwc_config_data ubwc_config_sm8550 = { .max_channels = 8, - .bank_swzl_level = 0, - .bank_swz2_level = 1, - .bank_swz3_level = 1, .bank_spreading = 1, }; From 032697ce89fa0266b7da82b0434d5226323bd95a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:09 +0200 Subject: [PATCH 1215/1330] FROMGIT: media: iris: don't specify bank_spreading in the source code The UBWC bank spreading is specified both in the Iris driver and in the platform UBWC config. Use the platform UBWC configuration instead of specifying it directly in the source. Link: https://lore.kernel.org/linux-media/20260507-iris-ubwc-v5-5-e9a3aee53c49@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 7b540a07f1d0cbfc62c359cceb597f1fe122514c) (cherry picked from commit 518c8646fa75c4a7dfbb4f2919e98071a85145d7) --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 - drivers/media/platform/qcom/iris/iris_platform_gen2.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index b88231178fd75..8bae07367089a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -77,7 +77,6 @@ struct tz_cp_config { struct ubwc_config_data { u32 max_channels; - u32 bank_spreading; }; struct platform_inst_caps { diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 8072f430bd268..4e617176dee42 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -792,7 +792,6 @@ static const char * const sm8550_opp_clk_table[] = { static struct ubwc_config_data ubwc_config_sm8550 = { .max_channels = 8, - .bank_spreading = 1, }; static const struct tz_cp_config tz_cp_config_sm8550[] = { From 03eea444a423f14d0bf44b31e04511c5e53bfcd2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:10 +0200 Subject: [PATCH 1216/1330] FROMGIT: media: iris: don't specify max_channels in the source code The UBWC max_channels spreading is specified in the Iris driver, but it also can be calculated from the platform UBWC config. Use the platform UBWC configuration instead of specifying it directly in the source. Link: https://lore.kernel.org/linux-media/20260507-iris-ubwc-v5-6-e9a3aee53c49@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 29b8299ab08312ac080082610c4d7a6c2808ef18) (cherry picked from commit aa9198a1869559157fb2a454e1744aa7b774c92d) --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 - drivers/media/platform/qcom/iris/iris_platform_gen2.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 8bae07367089a..aa6192ebc8d0a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -76,7 +76,6 @@ struct tz_cp_config { }; struct ubwc_config_data { - u32 max_channels; }; struct platform_inst_caps { diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 4e617176dee42..05b1dd11abceb 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -791,7 +791,6 @@ static const char * const sm8550_opp_clk_table[] = { }; static struct ubwc_config_data ubwc_config_sm8550 = { - .max_channels = 8, }; static const struct tz_cp_config tz_cp_config_sm8550[] = { From 08830e54895dabf0560f6621c1b3b7acefed83ed Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:11 +0200 Subject: [PATCH 1217/1330] FROMGIT: media: iris: drop remnants of UBWC configuration Now as all UBWC configuration bits were migrated to be used or derived from the global UBWC platform-specific data, drop the unused struct and field definitions. Link: https://lore.kernel.org/linux-media/20260507-iris-ubwc-v5-7-e9a3aee53c49@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit e2f0779da85f445426adacd2e57d08be38ff4e4a) (cherry picked from commit edb265ce01c6e11415240296ba03573f905431bf) --- drivers/media/platform/qcom/iris/iris_platform_common.h | 4 ---- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 7 ------- 2 files changed, 11 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index aa6192ebc8d0a..8acb42fce444a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -75,9 +75,6 @@ struct tz_cp_config { u32 cp_nonpixel_size; }; -struct ubwc_config_data { -}; - struct platform_inst_caps { u32 min_frame_width; u32 max_frame_width; @@ -240,7 +237,6 @@ struct iris_platform_data { u32 tz_cp_config_data_size; u32 core_arch; u32 hw_response_timeout; - struct ubwc_config_data *ubwc_config; u32 num_vpp_pipe; bool no_aon; u32 max_session_count; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 05b1dd11abceb..a526b50a1cd3f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -790,9 +790,6 @@ static const char * const sm8550_opp_clk_table[] = { NULL, }; -static struct ubwc_config_data ubwc_config_sm8550 = { -}; - static const struct tz_cp_config tz_cp_config_sm8550[] = { { .cp_start = 0, @@ -949,7 +946,6 @@ const struct iris_platform_data sm8550_data = { .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, - .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -1054,7 +1050,6 @@ const struct iris_platform_data sm8650_data = { .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, - .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -1150,7 +1145,6 @@ const struct iris_platform_data sm8750_data = { .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, - .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -1250,7 +1244,6 @@ const struct iris_platform_data qcs8300_data = { .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, - .ubwc_config = &ubwc_config_sm8550, .num_vpp_pipe = 2, .max_session_count = 16, .max_core_mbpf = ((4096 * 2176) / 256) * 4, From 77b87f34ed99bf746848f8d76402d3c8b31f1e8e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:02 +0200 Subject: [PATCH 1218/1330] FROMGIT: media: qcom: iris: drop pas_id from the iris_platform_data struct The PAS ID, the authentication service ID, used by the Iris is a constant and it is not expected to change anytime. Drop it from the platform data and use the constant instead. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-1-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Konrad Dybcio Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 97698845dd532ab6c14dd435144959545d4cfef7) (cherry picked from commit c9770fdca8ff8b5bf4bf0d713b8b6b838b34f354) --- drivers/media/platform/qcom/iris/iris_firmware.c | 11 ++++++----- .../media/platform/qcom/iris/iris_platform_common.h | 2 -- drivers/media/platform/qcom/iris/iris_platform_gen1.c | 2 -- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 4 ---- 4 files changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index 3aa1991042b61..cef89fd3a00b6 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -12,6 +12,8 @@ #include "iris_core.h" #include "iris_firmware.h" +#define IRIS_PAS_ID 9 + #define MAX_FIRMWARE_NAME_SIZE 128 /* Detect Gen2 firmware by scanning the blob for: @@ -93,7 +95,6 @@ static const struct firmware *iris_detect_firmware(struct iris_core *core, static int iris_load_fw_to_memory(struct iris_core *core) { - u32 pas_id = core->iris_platform_data->pas_id; const struct firmware *firmware = NULL; struct device *dev = core->dev; struct resource res; @@ -128,7 +129,7 @@ static int iris_load_fw_to_memory(struct iris_core *core) } ret = qcom_mdt_load(dev, firmware, fw_name, - pas_id, mem_virt, mem_phys, res_size, NULL); + IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL); memunmap(mem_virt); err_release_fw: @@ -153,7 +154,7 @@ int iris_fw_load(struct iris_core *core) return ret; } - ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id); + ret = qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); if (ret) { dev_err(core->dev, "auth and reset failed: %d\n", ret); return ret; @@ -167,7 +168,7 @@ int iris_fw_load(struct iris_core *core) cp_config->cp_nonpixel_size); if (ret) { dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + qcom_scm_pas_shutdown(IRIS_PAS_ID); return ret; } } @@ -177,7 +178,7 @@ int iris_fw_load(struct iris_core *core) int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + return qcom_scm_pas_shutdown(IRIS_PAS_ID); } int iris_set_hw_state(struct iris_core *core, bool resume) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 8acb42fce444a..a4a533b389086 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -12,7 +12,6 @@ struct iris_core; struct iris_inst; -#define IRIS_PAS_ID 9 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ @@ -225,7 +224,6 @@ struct iris_platform_data { unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; - u32 pas_id; struct iris_fmt *inst_iris_fmts; u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index df8e6bf9430ed..1bbdefc48d718 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -360,7 +360,6 @@ const struct iris_platform_data sm8250_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu-1.0/venus.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, @@ -413,7 +412,6 @@ const struct iris_platform_data sc7280_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu20_p1.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index a526b50a1cd3f..1f23ddb972f0f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -934,7 +934,6 @@ const struct iris_platform_data sm8550_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu30_p4.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1038,7 +1037,6 @@ const struct iris_platform_data sm8650_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu33_p4.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1133,7 +1131,6 @@ const struct iris_platform_data sm8750_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu35_p4.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -1232,7 +1229,6 @@ const struct iris_platform_data qcs8300_data = { /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, .fwname = "qcom/vpu/vpu30_p4_s6.mbn", - .pas_id = IRIS_PAS_ID, .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_qcs8300, From c832f284a2cd3e934d3c013caa3ff9aa61db563c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:03 +0200 Subject: [PATCH 1219/1330] FROMGIT: media: qcom: iris: use common set_preset_registers function The set_preset_registers is (currently) common to all supported devices. Extract it to a iris_vpu_common.c and call it directly from iris_vpu_power_on(). Later, if any of the devices requires special handling, it can be sorted out separately. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-2-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 4869025571b9200f0583bacb161ad6696970b073) (cherry picked from commit 216417283a4c00156ad389a500d2328e44789d47) --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 - drivers/media/platform/qcom/iris/iris_platform_gen1.c | 7 ------- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 9 --------- drivers/media/platform/qcom/iris/iris_vpu_common.c | 7 ++++++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 5 files changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index a4a533b389086..91a09047acbe9 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -206,7 +206,6 @@ struct iris_platform_data { struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; - void (*set_preset_registers)(struct iris_core *core); const struct icc_info *icc_tbl; unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 1bbdefc48d718..546f6c025d547 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -260,11 +260,6 @@ static struct platform_inst_caps platform_inst_cap_sm8250 = { .max_operating_rate = MAXIMUM_FPS, }; -static void iris_set_sm8250_preset_registers(struct iris_core *core) -{ - writel(0x0, core->reg_base + 0xB0088); -} - static const struct icc_info sm8250_icc_table[] = { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -343,7 +338,6 @@ const struct iris_platform_data sm8250_data = { .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, - .set_preset_registers = iris_set_sm8250_preset_registers, .icc_tbl = sm8250_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), .clk_rst_tbl = sm8250_clk_reset_table, @@ -397,7 +391,6 @@ const struct iris_platform_data sc7280_data = { .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, - .set_preset_registers = iris_set_sm8250_preset_registers, .icc_tbl = sm8250_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), .bw_tbl_dec = sc7280_bw_table_dec, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 1f23ddb972f0f..c84d4399f84d9 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -756,11 +756,6 @@ static struct platform_inst_caps platform_inst_cap_sm8550 = { .max_operating_rate = MAXIMUM_FPS, }; -static void iris_set_sm8550_preset_registers(struct iris_core *core) -{ - writel(0x0, core->reg_base + 0xB0088); -} - static const struct icc_info sm8550_icc_table[] = { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -917,7 +912,6 @@ const struct iris_platform_data sm8550_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8550_clk_reset_table, @@ -1018,7 +1012,6 @@ const struct iris_platform_data sm8650_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8650_clk_reset_table, @@ -1114,7 +1107,6 @@ const struct iris_platform_data sm8750_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8750_clk_reset_table, @@ -1212,7 +1204,6 @@ const struct iris_platform_data qcs8300_data = { .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, - .set_preset_registers = iris_set_sm8550_preset_registers, .icc_tbl = sm8550_icc_table, .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl = sm8550_clk_reset_table, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 69e6126dc4d95..60a3d429fa439 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -472,7 +472,7 @@ int iris_vpu_power_on(struct iris_core *core) iris_opp_set_rate(core->dev, freq); - core->iris_platform_data->set_preset_registers(core); + iris_vpu_set_preset_registers(core); iris_vpu_interrupt_init(core); core->intr_status = 0; @@ -489,3 +489,8 @@ int iris_vpu_power_on(struct iris_core *core) return ret; } + +void iris_vpu_set_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + 0xb0088); +} diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index dee3b1349c5e8..09799a375c142 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -42,4 +42,6 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core); void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core); u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size); +void iris_vpu_set_preset_registers(struct iris_core *core); + #endif From 7837ae42e6229359fdba7bd1743671b42495f904 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:04 +0200 Subject: [PATCH 1220/1330] FROMGIT: media: qcom: iris: don't use function indirection in gen2-specific code To note that iris_set_num_comv() is gen2-internal, rename it to iris_hfi_gen2_set_num_comv() and then stop using hfi_ops indirection to set session property (like other functions in this file do). Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-3-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Konrad Dybcio Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit c0a100ae13e15d615fbedb0308e71ea267b5517e) (cherry picked from commit 0d2e8868e3c0b6cf435947a6f7c98e3a0b667cb0) --- .../platform/qcom/iris/iris_hfi_gen2_command.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 41ec04d955f16..46d8e6fe6baf2 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1204,19 +1204,19 @@ static u32 iris_hfi_gen2_buf_type_from_driver(u32 domain, enum iris_buffer_type } } -static int iris_set_num_comv(struct iris_inst *inst) +static int iris_hfi_gen2_set_num_comv(struct iris_inst *inst) { u32 num_comv = inst->buffers[BUF_OUTPUT].min_count; if (inst->fw_min_count) num_comv = inst->fw_min_count; - return core->hfi_ops->session_set_property(inst, - HFI_PROP_COMV_BUFFER_COUNT, - HFI_HOST_FLAGS_NONE, - HFI_PORT_BITSTREAM, - HFI_PAYLOAD_U32, - &num_comv, sizeof(u32)); + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_COMV_BUFFER_COUNT, + HFI_HOST_FLAGS_NONE, + HFI_PORT_BITSTREAM, + HFI_PAYLOAD_U32, + &num_comv, sizeof(u32)); } static void iris_hfi_gen2_get_buffer(u32 domain, struct iris_buffer *buffer, @@ -1248,7 +1248,7 @@ static int iris_hfi_gen2_session_queue_buffer(struct iris_inst *inst, struct iri iris_hfi_gen2_get_buffer(inst->domain, buffer, &hfi_buffer); if (buffer->type == BUF_COMV) { - ret = iris_set_num_comv(inst); + ret = iris_hfi_gen2_set_num_comv(inst); if (ret) return ret; } From 038357c3b663174ae3d9172f44d83bc882cfbd07 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:05 +0200 Subject: [PATCH 1221/1330] FROMGIT: media: qcom: iris: split HFI session ops from core ops Calling HFI instance-specific ops should not require double indirection through the core ops. Split instance-specific ops to a separate struct, keep a pointer to it in struct iris_inst and set it directly in the get_instance function. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-4-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 82e4f934dadf3b413fc0fdf2d245f04f77093f96) (cherry picked from commit 86d42314849d4856a14bb39cb049ec14628d4510) --- .../media/platform/qcom/iris/iris_buffer.c | 4 +- .../media/platform/qcom/iris/iris_common.c | 8 ++-- drivers/media/platform/qcom/iris/iris_ctrls.c | 46 +++++++++---------- .../platform/qcom/iris/iris_hfi_common.h | 3 ++ .../qcom/iris/iris_hfi_gen1_command.c | 23 +++++++--- .../qcom/iris/iris_hfi_gen2_command.c | 17 +++++-- .../media/platform/qcom/iris/iris_instance.h | 4 ++ drivers/media/platform/qcom/iris/iris_vb2.c | 2 +- drivers/media/platform/qcom/iris/iris_vdec.c | 6 +-- drivers/media/platform/qcom/iris/iris_venc.c | 4 +- drivers/media/platform/qcom/iris/iris_vidc.c | 2 +- 11 files changed, 72 insertions(+), 47 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 1d53c7414b754..f41596b314c39 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -404,7 +404,7 @@ int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; int ret; ret = hfi_ops->session_queue_buf(inst, buf); @@ -572,7 +572,7 @@ int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 plane) static int iris_release_internal_buffers(struct iris_inst *inst, enum iris_buffer_type buffer_type) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct iris_buffers *buffers = &inst->buffers[buffer_type]; struct iris_buffer *buffer, *next; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media/platform/qcom/iris/iris_common.c index 7f1c7fe144f70..25836561bcf3e 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -48,7 +48,7 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_process_streamon_input(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_inst_sub_state set_sub_state = 0; int ret; @@ -90,7 +90,7 @@ int iris_process_streamon_input(struct iris_inst *inst) int iris_process_streamon_output(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state = 0; bool drain_active, drc_active, first_ipsc; int ret = 0; @@ -189,7 +189,7 @@ static void iris_flush_deferred_buffers(struct iris_inst *inst, static void iris_kill_session(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; if (!inst->session_id) return; @@ -200,7 +200,7 @@ static void iris_kill_session(struct iris_inst *inst) int iris_session_streamoff(struct iris_inst *inst, u32 plane) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_buffer_type buffer_type; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c index 3cec957580f5e..5a24aa869b2dc 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -399,7 +399,7 @@ static u32 iris_get_port_info(struct iris_inst *inst, int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_value = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -412,7 +412,7 @@ int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_value = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -425,7 +425,7 @@ int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct v4l2_format *inp_f = inst->fmt_src; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 height = inp_f->fmt.pix_mp.height; @@ -446,7 +446,7 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 work_route = inst->fw_caps[PIPE].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -459,7 +459,7 @@ int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id, hfi_value; if (inst->codec == V4L2_PIX_FMT_H264) { @@ -479,7 +479,7 @@ int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id, hfi_value; if (inst->codec == V4L2_PIX_FMT_H264) { @@ -499,7 +499,7 @@ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; struct hfi_profile_level pl; @@ -520,7 +520,7 @@ int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_ca int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 header_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -539,7 +539,7 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; u32 header_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -561,7 +561,7 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; u32 bitrate = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -586,7 +586,7 @@ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; u32 peak_bitrate = inst->fw_caps[cap_id].value; u32 bitrate = inst->fw_caps[BITRATE].value; @@ -613,7 +613,7 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; @@ -640,7 +640,7 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; @@ -667,7 +667,7 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 entropy_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -687,7 +687,7 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 entropy_mode = inst->fw_caps[cap_id].value; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 profile; @@ -712,7 +712,7 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; u32 min_qp_enable = 0, client_qp_enable = 0; @@ -776,7 +776,7 @@ int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; u32 max_qp_enable = 0, client_qp_enable; u32 i_frame_qp, p_frame_qp, b_frame_qp; @@ -841,7 +841,7 @@ int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; u32 i_frame_qp, p_frame_qp, b_frame_qp; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -902,7 +902,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct hfi_quantization_range_v2 range; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; @@ -923,7 +923,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -953,7 +953,7 @@ int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; u32 hfi_id = inst->fw_caps[cap_id].hfi_id; u32 hfi_val = HFI_DISABLE_FLIP; @@ -972,7 +972,7 @@ int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct vb2_queue *q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); u32 ir_period = inst->fw_caps[cap_id].value; u32 ir_type = 0; @@ -998,7 +998,7 @@ int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type ca int iris_set_properties(struct iris_inst *inst, u32 plane) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; struct platform_inst_fw_cap *cap; int ret; u32 i; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 3edb5ae582b49..18684ada78b21 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -110,6 +110,9 @@ struct iris_hfi_command_ops { int (*sys_image_version)(struct iris_core *core); int (*sys_interframe_powercollapse)(struct iris_core *core); int (*sys_pc_prep)(struct iris_core *core); +}; + +struct iris_hfi_session_ops { int (*session_set_config_params)(struct iris_inst *inst, u32 plane); int (*session_set_property)(struct iris_inst *inst, u32 packet_type, u32 flag, u32 plane, u32 payload_type, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index e42d17653c2c3..a28b0c7ebbadd 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1063,11 +1063,7 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p return 0; } -static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { - .sys_init = iris_hfi_gen1_sys_init, - .sys_image_version = iris_hfi_gen1_sys_image_version, - .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, - .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, +static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_open = iris_hfi_gen1_session_open, .session_set_config_params = iris_hfi_gen1_session_set_config_params, .session_set_property = iris_hfi_gen1_session_set_property, @@ -1080,6 +1076,13 @@ static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { .session_close = iris_hfi_gen1_session_close, }; +static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { + .sys_init = iris_hfi_gen1_sys_init, + .sys_image_version = iris_hfi_gen1_sys_image_version, + .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, + .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, +}; + void iris_hfi_gen1_command_ops_init(struct iris_core *core) { core->hfi_ops = &iris_hfi_gen1_command_ops; @@ -1087,5 +1090,13 @@ void iris_hfi_gen1_command_ops_init(struct iris_core *core) struct iris_inst *iris_hfi_gen1_get_instance(void) { - return kzalloc_obj(struct iris_inst); + struct iris_inst *out; + + out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->hfi_session_ops = &iris_hfi_gen1_session_ops; + + return out; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 46d8e6fe6baf2..29814d77c969f 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1291,11 +1291,7 @@ static int iris_hfi_gen2_session_release_buffer(struct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } -static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { - .sys_init = iris_hfi_gen2_sys_init, - .sys_image_version = iris_hfi_gen2_sys_image_version, - .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, - .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, +static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_open = iris_hfi_gen2_session_open, .session_set_config_params = iris_hfi_gen2_session_set_config_params, .session_set_property = iris_hfi_gen2_session_set_property, @@ -1310,6 +1306,13 @@ static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { .session_close = iris_hfi_gen2_session_close, }; +static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { + .sys_init = iris_hfi_gen2_sys_init, + .sys_image_version = iris_hfi_gen2_sys_image_version, + .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, + .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, +}; + void iris_hfi_gen2_command_ops_init(struct iris_core *core) { core->hfi_ops = &iris_hfi_gen2_command_ops; @@ -1321,6 +1324,10 @@ struct iris_inst *iris_hfi_gen2_get_instance(void) /* The allocation is intentionally larger than struct iris_inst. */ out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; return &out->inst; } diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h index 16965150f427b..352af99699dd5 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -15,6 +15,8 @@ #define DEFAULT_WIDTH 320 #define DEFAULT_HEIGHT 240 +struct iris_hfi_session_ops; + enum iris_fmt_type_out { IRIS_FMT_H264, IRIS_FMT_HEVC, @@ -38,6 +40,7 @@ struct iris_fmt { * @list: used for attach an instance to the core * @core: pointer to core structure * @session_id: id of current video session + * @hfi_session_ops: iris HFI session ops * @ctx_q_lock: lock to serialize queues related ioctls * @lock: lock to seralise forward and reverse threads * @fh: reference of v4l2 file handler @@ -80,6 +83,7 @@ struct iris_inst { struct list_head list; struct iris_core *core; u32 session_id; + const struct iris_hfi_session_ops *hfi_session_ops; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ struct mutex lock; /* lock to serialize forward and reverse threads */ struct v4l2_fh fh; diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/platform/qcom/iris/iris_vb2.c index bf0b8400996ec..a2ea2d67f60d0 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -129,7 +129,7 @@ int iris_vb2_queue_setup(struct vb2_queue *q, if (!inst->once_per_session_set) { inst->once_per_session_set = true; - ret = core->hfi_ops->session_open(inst); + ret = inst->hfi_session_ops->session_open(inst); if (ret) { ret = -EINVAL; dev_err(core->dev, "session open failed\n"); diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index f05f74e085f7d..752198c54514b 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -369,7 +369,7 @@ int iris_vdec_streamon_input(struct iris_inst *inst) int iris_vdec_streamon_output(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; int ret; ret = hfi_ops->session_set_config_params(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); @@ -429,7 +429,7 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_vdec_start_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state = 0; struct vb2_queue *dst_vq; int ret; @@ -492,7 +492,7 @@ int iris_vdec_start_cmd(struct iris_inst *inst) int iris_vdec_stop_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; int ret; ret = hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c index 4d886769d958b..c11fee4799cdd 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -575,7 +575,7 @@ int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) int iris_venc_start_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state = 0; struct vb2_queue *dst_vq; int ret; @@ -617,7 +617,7 @@ int iris_venc_start_cmd(struct iris_inst *inst) int iris_venc_stop_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; int ret; ret = hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index f7c3ac9f96ce3..b9f0cc7454813 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -227,7 +227,7 @@ int iris_open(struct file *filp) static void iris_session_close(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; bool wait_for_response = true; int ret; From 7dc821c3cc825aea04c61ce7dfa6ee15689c8257 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:06 +0200 Subject: [PATCH 1222/1330] FROMGIT: media: qcom: iris: merge hfi_response_ops and hfi_command_ops There is little point in having two different structures for HFI-related core ops. Merge both of them into the new iris_hfi_ops structure. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-5-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit cd4e5d9712ac067c62eab264dee2876fd6db807d) (cherry picked from commit b055bd856c8c25b7739b02fa261236872255254d) --- drivers/media/platform/qcom/iris/iris_core.h | 6 ++---- drivers/media/platform/qcom/iris/iris_hfi_common.c | 6 +++--- drivers/media/platform/qcom/iris/iris_hfi_common.h | 8 +++----- drivers/media/platform/qcom/iris/iris_hfi_gen1.h | 4 ++-- .../media/platform/qcom/iris/iris_hfi_gen1_command.c | 8 +++++--- .../platform/qcom/iris/iris_hfi_gen1_response.c | 11 +---------- drivers/media/platform/qcom/iris/iris_hfi_gen2.h | 4 ++-- .../media/platform/qcom/iris/iris_hfi_gen2_command.c | 8 +++++--- .../platform/qcom/iris/iris_hfi_gen2_response.c | 11 +---------- .../media/platform/qcom/iris/iris_platform_common.h | 3 +-- .../media/platform/qcom/iris/iris_platform_gen1.c | 6 ++---- .../media/platform/qcom/iris/iris_platform_gen2.c | 12 ++++-------- drivers/media/platform/qcom/iris/iris_probe.c | 3 +-- drivers/media/platform/qcom/iris/iris_vpu_common.c | 2 +- 14 files changed, 33 insertions(+), 59 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index d10a03aa5685a..1592681640ab4 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -68,8 +68,7 @@ struct qcom_ubwc_cfg_data; * @header_id: id of packet header * @packet_id: id of packet * @power: a structure for clock and bw information - * @hfi_ops: iris hfi command ops - * @hfi_response_ops: iris hfi response ops + * @hfi_sys_ops: iris HFI system ops * @core_init_done: structure of signal completion for system response * @intr_status: interrupt status * @sys_error_handler: a delayed work for handling system fatal error @@ -112,8 +111,7 @@ struct iris_core { u32 header_id; u32 packet_id; struct iris_core_power power; - const struct iris_hfi_command_ops *hfi_ops; - const struct iris_hfi_response_ops *hfi_response_ops; + const struct iris_hfi_sys_ops *hfi_sys_ops; struct completion core_init_done; u32 intr_status; struct delayed_work sys_error_handler; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/media/platform/qcom/iris/iris_hfi_common.c index 621c66593d88d..8769ec61f1176 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c @@ -76,7 +76,7 @@ u32 iris_hfi_get_v4l2_matrix_coefficients(u32 hfi_coefficients) int iris_hfi_core_init(struct iris_core *core) { - const struct iris_hfi_command_ops *hfi_ops = core->hfi_ops; + const struct iris_hfi_sys_ops *hfi_ops = core->hfi_sys_ops; int ret; ret = hfi_ops->sys_init(core); @@ -109,7 +109,7 @@ irqreturn_t iris_hfi_isr_handler(int irq, void *data) iris_vpu_clear_interrupt(core); mutex_unlock(&core->lock); - core->hfi_response_ops->hfi_response_handler(core); + core->hfi_sys_ops->sys_hfi_response_handler(core); if (!iris_vpu_watchdog(core, core->intr_status)) enable_irq(irq); @@ -144,7 +144,7 @@ int iris_hfi_pm_suspend(struct iris_core *core) int iris_hfi_pm_resume(struct iris_core *core) { - const struct iris_hfi_command_ops *ops = core->hfi_ops; + const struct iris_hfi_sys_ops *ops = core->hfi_sys_ops; int ret; ret = iris_vpu_power_on(core); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 18684ada78b21..9aa84a1d8f950 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -105,11 +105,13 @@ struct iris_hfi_prop_type_handle { int (*handle)(struct iris_inst *inst, u32 plane); }; -struct iris_hfi_command_ops { +struct iris_hfi_sys_ops { int (*sys_init)(struct iris_core *core); int (*sys_image_version)(struct iris_core *core); int (*sys_interframe_powercollapse)(struct iris_core *core); int (*sys_pc_prep)(struct iris_core *core); + + void (*sys_hfi_response_handler)(struct iris_core *core); }; struct iris_hfi_session_ops { @@ -129,10 +131,6 @@ struct iris_hfi_session_ops { int (*session_close)(struct iris_inst *inst); }; -struct iris_hfi_response_ops { - void (*hfi_response_handler)(struct iris_core *core); -}; - struct hfi_subscription_params { u32 bitstream_resolution; u32 crop_offsets[2]; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h index 19b8e9054a757..38e9d262d7df4 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h @@ -9,8 +9,8 @@ struct iris_core; struct iris_inst; -void iris_hfi_gen1_command_ops_init(struct iris_core *core); -void iris_hfi_gen1_response_ops_init(struct iris_core *core); +void iris_hfi_gen1_sys_ops_init(struct iris_core *core); +void iris_hfi_gen1_response_handler(struct iris_core *core); struct iris_inst *iris_hfi_gen1_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index a28b0c7ebbadd..26b7feb05d15b 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1076,16 +1076,18 @@ static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_close = iris_hfi_gen1_session_close, }; -static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops = { +static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { .sys_init = iris_hfi_gen1_sys_init, .sys_image_version = iris_hfi_gen1_sys_image_version, .sys_interframe_powercollapse = iris_hfi_gen1_sys_interframe_powercollapse, .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, + + .sys_hfi_response_handler = iris_hfi_gen1_response_handler, }; -void iris_hfi_gen1_command_ops_init(struct iris_core *core) +void iris_hfi_gen1_sys_ops_init(struct iris_core *core) { - core->hfi_ops = &iris_hfi_gen1_command_ops; + core->hfi_sys_ops = &iris_hfi_gen1_sys_ops; } struct iris_inst *iris_hfi_gen1_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 8e864c239e293..bfd7495bf44f0 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -688,7 +688,7 @@ static void iris_hfi_gen1_flush_debug_queue(struct iris_core *core, u8 *packet) } } -static void iris_hfi_gen1_response_handler(struct iris_core *core) +void iris_hfi_gen1_response_handler(struct iris_core *core) { memset(core->response_packet, 0, sizeof(struct hfi_pkt_hdr)); while (!iris_hfi_queue_msg_read(core, core->response_packet)) { @@ -698,12 +698,3 @@ static void iris_hfi_gen1_response_handler(struct iris_core *core) iris_hfi_gen1_flush_debug_queue(core, core->response_packet); } - -static const struct iris_hfi_response_ops iris_hfi_gen1_response_ops = { - .hfi_response_handler = iris_hfi_gen1_response_handler, -}; - -void iris_hfi_gen1_response_ops_init(struct iris_core *core) -{ - core->hfi_response_ops = &iris_hfi_gen1_response_ops; -} diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h index b9d3749a10efe..6cc6d9890c128 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h @@ -34,8 +34,8 @@ struct iris_inst_hfi_gen2 { struct hfi_subscription_params dst_subcr_params; }; -void iris_hfi_gen2_command_ops_init(struct iris_core *core); -void iris_hfi_gen2_response_ops_init(struct iris_core *core); +void iris_hfi_gen2_sys_ops_init(struct iris_core *core); +void iris_hfi_gen2_response_handler(struct iris_core *core); struct iris_inst *iris_hfi_gen2_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 29814d77c969f..552d4230e455c 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1306,16 +1306,18 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_close = iris_hfi_gen2_session_close, }; -static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = { +static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { .sys_init = iris_hfi_gen2_sys_init, .sys_image_version = iris_hfi_gen2_sys_image_version, .sys_interframe_powercollapse = iris_hfi_gen2_sys_interframe_powercollapse, .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, + + .sys_hfi_response_handler = iris_hfi_gen2_response_handler, }; -void iris_hfi_gen2_command_ops_init(struct iris_core *core) +void iris_hfi_gen2_sys_ops_init(struct iris_core *core) { - core->hfi_ops = &iris_hfi_gen2_command_ops; + core->hfi_sys_ops = &iris_hfi_gen2_sys_ops; } struct iris_inst *iris_hfi_gen2_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 8e19f61bbbf9e..c350d231265e5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -977,7 +977,7 @@ static void iris_hfi_gen2_flush_debug_queue(struct iris_core *core, u8 *packet) } } -static void iris_hfi_gen2_response_handler(struct iris_core *core) +void iris_hfi_gen2_response_handler(struct iris_core *core) { if (iris_vpu_watchdog(core, core->intr_status)) { struct iris_hfi_packet pkt = {.type = HFI_SYS_ERROR_WD_TIMEOUT}; @@ -997,12 +997,3 @@ static void iris_hfi_gen2_response_handler(struct iris_core *core) iris_hfi_gen2_flush_debug_queue(core, core->response_packet); } - -static const struct iris_hfi_response_ops iris_hfi_gen2_response_ops = { - .hfi_response_handler = iris_hfi_gen2_response_handler, -}; - -void iris_hfi_gen2_response_ops_init(struct iris_core *core) -{ - core->hfi_response_ops = &iris_hfi_gen2_response_ops; -} diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 91a09047acbe9..076080ed4b0f6 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -201,8 +201,7 @@ enum platform_pm_domain_type { }; struct iris_platform_data { - void (*init_hfi_command_ops)(struct iris_core *core); - void (*init_hfi_response_ops)(struct iris_core *core); + void (*init_hfi_ops)(struct iris_core *core); struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 546f6c025d547..9eeb500c65d90 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -334,8 +334,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { const struct iris_platform_data sm8250_data = { .get_instance = iris_hfi_gen1_get_instance, - .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, + .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -387,8 +386,7 @@ const struct iris_platform_data sm8250_data = { const struct iris_platform_data sc7280_data = { .get_instance = iris_hfi_gen1_get_instance, - .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, + .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index c84d4399f84d9..19e99e1c2aff0 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -908,8 +908,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { const struct iris_platform_data sm8550_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .icc_tbl = sm8550_icc_table, @@ -1008,8 +1007,7 @@ const struct iris_platform_data sm8550_data = { */ const struct iris_platform_data sm8650_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, .icc_tbl = sm8550_icc_table, @@ -1103,8 +1101,7 @@ const struct iris_platform_data sm8650_data = { const struct iris_platform_data sm8750_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, .icc_tbl = sm8550_icc_table, @@ -1200,8 +1197,7 @@ const struct iris_platform_data sm8750_data = { */ const struct iris_platform_data qcs8300_data = { .get_instance = iris_hfi_gen2_get_instance, - .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .icc_tbl = sm8550_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 17bb11513648a..c2d174a6e1608 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -257,8 +257,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); iris_init_ops(core); - core->iris_platform_data->init_hfi_command_ops(core); - core->iris_platform_data->init_hfi_response_ops(core); + core->iris_platform_data->init_hfi_ops(core); ret = iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 60a3d429fa439..e77e94ac982b8 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -149,7 +149,7 @@ int iris_vpu_prepare_pc(struct iris_core *core) if (!wfi_status || !idle_status) goto skip_power_off; - ret = core->hfi_ops->sys_pc_prep(core); + ret = core->hfi_sys_ops->sys_pc_prep(core); if (ret) goto skip_power_off; From aa18bc4f0ecdf37a8e693a3be6f7a06e0e6ad714 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:07 +0200 Subject: [PATCH 1223/1330] FROMGIT: media: qcom: iris: move get_instance to iris_hfi_sys_ops The get_instance() is a callback tightly connected to the HFI implementation. Move it into the new iris_hfi_sys_ops structure, merging all core callbacks into a single vtable. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-6-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit c095fcdeb695cf639e4d9d8b625b815e8a43b267) (cherry picked from commit a38c882876156567c00246d3734d580ccbb2fafa) --- .../platform/qcom/iris/iris_hfi_common.h | 2 ++ .../media/platform/qcom/iris/iris_hfi_gen1.h | 2 -- .../qcom/iris/iris_hfi_gen1_command.c | 28 +++++++++-------- .../media/platform/qcom/iris/iris_hfi_gen2.h | 1 - .../qcom/iris/iris_hfi_gen2_command.c | 30 ++++++++++--------- .../platform/qcom/iris/iris_platform_common.h | 1 - .../platform/qcom/iris/iris_platform_gen1.c | 2 -- .../platform/qcom/iris/iris_platform_gen2.c | 4 --- drivers/media/platform/qcom/iris/iris_vidc.c | 2 +- 9 files changed, 34 insertions(+), 38 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index 9aa84a1d8f950..a27447eb25199 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -112,6 +112,8 @@ struct iris_hfi_sys_ops { int (*sys_pc_prep)(struct iris_core *core); void (*sys_hfi_response_handler)(struct iris_core *core); + + struct iris_inst *(*sys_get_instance)(void); }; struct iris_hfi_session_ops { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h index 38e9d262d7df4..c37adf65055a5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h @@ -7,10 +7,8 @@ #define __IRIS_HFI_GEN1_H__ struct iris_core; -struct iris_inst; void iris_hfi_gen1_sys_ops_init(struct iris_core *core); void iris_hfi_gen1_response_handler(struct iris_core *core); -struct iris_inst *iris_hfi_gen1_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 26b7feb05d15b..0017ade4adbd9 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1076,6 +1076,19 @@ static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = { .session_close = iris_hfi_gen1_session_close, }; +static struct iris_inst *iris_hfi_gen1_get_instance(void) +{ + struct iris_inst *out; + + out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->hfi_session_ops = &iris_hfi_gen1_session_ops; + + return out; +} + static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { .sys_init = iris_hfi_gen1_sys_init, .sys_image_version = iris_hfi_gen1_sys_image_version, @@ -1083,22 +1096,11 @@ static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops = { .sys_pc_prep = iris_hfi_gen1_sys_pc_prep, .sys_hfi_response_handler = iris_hfi_gen1_response_handler, + + .sys_get_instance = iris_hfi_gen1_get_instance, }; void iris_hfi_gen1_sys_ops_init(struct iris_core *core) { core->hfi_sys_ops = &iris_hfi_gen1_sys_ops; } - -struct iris_inst *iris_hfi_gen1_get_instance(void) -{ - struct iris_inst *out; - - out = kzalloc_obj(*out); - if (!out) - return NULL; - - out->hfi_session_ops = &iris_hfi_gen1_session_ops; - - return out; -} diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h index 6cc6d9890c128..21ab58e0aa840 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h @@ -36,6 +36,5 @@ struct iris_inst_hfi_gen2 { void iris_hfi_gen2_sys_ops_init(struct iris_core *core); void iris_hfi_gen2_response_handler(struct iris_core *core); -struct iris_inst *iris_hfi_gen2_get_instance(void); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 552d4230e455c..90dd7f22f3040 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1306,6 +1306,20 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_close = iris_hfi_gen2_session_close, }; +static struct iris_inst *iris_hfi_gen2_get_instance(void) +{ + struct iris_inst_hfi_gen2 *out; + + /* The allocation is intentionally larger than struct iris_inst. */ + out = kzalloc_obj(*out); + if (!out) + return NULL; + + out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; + + return &out->inst; +} + static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { .sys_init = iris_hfi_gen2_sys_init, .sys_image_version = iris_hfi_gen2_sys_image_version, @@ -1313,23 +1327,11 @@ static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops = { .sys_pc_prep = iris_hfi_gen2_sys_pc_prep, .sys_hfi_response_handler = iris_hfi_gen2_response_handler, + + .sys_get_instance = iris_hfi_gen2_get_instance, }; void iris_hfi_gen2_sys_ops_init(struct iris_core *core) { core->hfi_sys_ops = &iris_hfi_gen2_sys_ops; } - -struct iris_inst *iris_hfi_gen2_get_instance(void) -{ - struct iris_inst_hfi_gen2 *out; - - /* The allocation is intentionally larger than struct iris_inst. */ - out = kzalloc_obj(*out); - if (!out) - return NULL; - - out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops; - - return &out->inst; -} diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 076080ed4b0f6..c21387c985645 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -202,7 +202,6 @@ enum platform_pm_domain_type { struct iris_platform_data { void (*init_hfi_ops)(struct iris_core *core); - struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); const struct vpu_ops *vpu_ops; const struct icc_info *icc_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 9eeb500c65d90..293834d6359b8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -333,7 +333,6 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { }; const struct iris_platform_data sm8250_data = { - .get_instance = iris_hfi_gen1_get_instance, .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, @@ -385,7 +384,6 @@ const struct iris_platform_data sm8250_data = { }; const struct iris_platform_data sc7280_data = { - .get_instance = iris_hfi_gen1_get_instance, .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 19e99e1c2aff0..10a972f96cbe7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -907,7 +907,6 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { }; const struct iris_platform_data sm8550_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, @@ -1006,7 +1005,6 @@ const struct iris_platform_data sm8550_data = { * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, @@ -1100,7 +1098,6 @@ const struct iris_platform_data sm8650_data = { }; const struct iris_platform_data sm8750_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, @@ -1196,7 +1193,6 @@ const struct iris_platform_data sm8750_data = { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .get_instance = iris_hfi_gen2_get_instance, .init_hfi_ops = iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index b9f0cc7454813..814e8ff76f67e 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -157,7 +157,7 @@ int iris_open(struct file *filp) pm_runtime_put_sync(core->dev); - inst = core->iris_platform_data->get_instance(); + inst = core->hfi_sys_ops->sys_get_instance(); if (!inst) return -ENOMEM; From 39625849f40bdf8717008b323f9d187226765d38 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:08 +0200 Subject: [PATCH 1224/1330] FROMGIT: media: qcom: iris: drop hw_response_timeout_val from platform data The HW response time is a constant between platforms. Remove it from the iris_platform_data structure and use it directly. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-7-eea672b03a95@oss.qualcomm.com/ Suggested-by: Vikash Garodia Reviewed-by: Vikash Garodia Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit ee904ba27b3888a93366a898e88518e82ae3451f) (cherry picked from commit 58a686d2f7170b1633789e87ff457885e1269194) --- drivers/media/platform/qcom/iris/iris_core.c | 3 +-- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 - drivers/media/platform/qcom/iris/iris_platform_gen1.c | 2 -- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 4 ---- drivers/media/platform/qcom/iris/iris_utils.c | 5 +---- 5 files changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c index 7b863e067551d..52bf56e517f91 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -28,14 +28,13 @@ void iris_core_deinit(struct iris_core *core) static int iris_wait_for_system_response(struct iris_core *core) { - u32 hw_response_timeout_val = core->iris_platform_data->hw_response_timeout; int ret; if (core->state == IRIS_CORE_ERROR) return -EIO; ret = wait_for_completion_timeout(&core->core_init_done, - msecs_to_jiffies(hw_response_timeout_val)); + msecs_to_jiffies(HW_RESPONSE_TIMEOUT_VALUE)); if (!ret) { core->state = IRIS_CORE_ERROR; return -ETIMEDOUT; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index c21387c985645..c539e5b7bcab3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -231,7 +231,6 @@ struct iris_platform_data { const struct tz_cp_config *tz_cp_config_data; u32 tz_cp_config_data_size; u32 core_arch; - u32 hw_response_timeout; u32 num_vpp_pipe; bool no_aon; u32 max_session_count; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 293834d6359b8..6592c1ed9ca50 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -361,7 +361,6 @@ const struct iris_platform_data sm8250_data = { .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K, @@ -410,7 +409,6 @@ const struct iris_platform_data sc7280_data = { .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 1, .no_aon = true, .max_session_count = 16, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 10a972f96cbe7..abe523db45c2c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -936,7 +936,6 @@ const struct iris_platform_data sm8550_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -1036,7 +1035,6 @@ const struct iris_platform_data sm8650_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -1127,7 +1125,6 @@ const struct iris_platform_data sm8750_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, @@ -1222,7 +1219,6 @@ const struct iris_platform_data qcs8300_data = { .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), .core_arch = VIDEO_ARCH_LX, - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe = 2, .max_session_count = 16, .max_core_mbpf = ((4096 * 2176) / 256) * 4, diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/platform/qcom/iris/iris_utils.c index cfc5b576ec56b..29b07d88507eb 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -55,16 +55,13 @@ void iris_helper_buffers_done(struct iris_inst *inst, unsigned int type, int iris_wait_for_session_response(struct iris_inst *inst, bool is_flush) { - struct iris_core *core = inst->core; - u32 hw_response_timeout_val; struct completion *done; int ret; - hw_response_timeout_val = core->iris_platform_data->hw_response_timeout; done = is_flush ? &inst->flush_completion : &inst->completion; mutex_unlock(&inst->lock); - ret = wait_for_completion_timeout(done, msecs_to_jiffies(hw_response_timeout_val)); + ret = wait_for_completion_timeout(done, msecs_to_jiffies(HW_RESPONSE_TIMEOUT_VALUE)); mutex_lock(&inst->lock); if (!ret) { iris_inst_change_state(inst, IRIS_INST_ERROR); From 81a0351f27f3f96d740f75a62d14e4472840838a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:09 +0200 Subject: [PATCH 1225/1330] FROMGIT: media: qcom: iris: split firmware_data from raw platform data Having firmware-related fields in platform data results in the tying platform data to the HFI firmware data rather than the actual hardware. For example, SM8450 uses Gen2 firmware, so currently its platform data should be placed next to the other gen2 platforms, although it has the VPU2.0 core, similar to the one found on SM8250 and SC7280 and so the hardware-specific platform data is also close to those devices. Split firmware data to a separate struct, separating hardware-related data from the firmware interfaces. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-8-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 5b44ad08fc61d89d50a8b15c0f65f77970d7bd81) (cherry picked from commit d85773c3caebef943096e4fc4008ac76d2687284) --- .../media/platform/qcom/iris/iris_buffer.c | 82 +++--- drivers/media/platform/qcom/iris/iris_core.h | 2 + drivers/media/platform/qcom/iris/iris_ctrls.c | 8 +- .../qcom/iris/iris_hfi_gen1_command.c | 8 +- .../qcom/iris/iris_hfi_gen2_command.c | 66 ++--- .../platform/qcom/iris/iris_platform_common.h | 81 +++--- .../platform/qcom/iris/iris_platform_gen1.c | 67 ++--- .../platform/qcom/iris/iris_platform_gen2.c | 248 +++--------------- drivers/media/platform/qcom/iris/iris_probe.c | 3 +- drivers/media/platform/qcom/iris/iris_vidc.c | 10 +- .../platform/qcom/iris/iris_vpu_common.c | 2 +- 11 files changed, 206 insertions(+), 371 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index f41596b314c39..95b9a370c972c 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -301,31 +301,31 @@ static void iris_fill_internal_buf_info(struct iris_inst *inst, void iris_get_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type = platform_data->enc_op_int_buf_tbl; - internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_op_int_buf_tbl; + internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; for (i = 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } @@ -366,7 +366,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; u32 internal_buffer_count, i, j; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -374,19 +374,19 @@ int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->enc_op_int_buf_tbl; - internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_op_int_buf_tbl; + internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; } } @@ -442,7 +442,7 @@ int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris_buffe int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; struct iris_buffer *buffer, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -451,19 +451,19 @@ int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->enc_op_int_buf_tbl; - internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_op_int_buf_tbl; + internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size; } } @@ -501,7 +501,7 @@ int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buf static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool force) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -510,19 +510,19 @@ static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - len = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + len = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - len = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + len = firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - len = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + len = firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->enc_op_int_buf_tbl; - len = platform_data->enc_op_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_op_int_buf_tbl; + len = firmware_data->enc_op_int_buf_tbl_size; } } @@ -595,17 +595,17 @@ static int iris_release_internal_buffers(struct iris_inst *inst, static int iris_release_input_internal_buffers(struct iris_inst *inst) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; int ret; if (inst->domain == DECODER) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->enc_ip_int_buf_tbl; - internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size; } for (i = 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 1592681640ab4..e0ca245c8c63a 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -54,6 +54,7 @@ struct qcom_ubwc_cfg_data; * @resets: table of iris reset clocks * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data + * @iris_firmware_data: a pointer to the firmware (or HFI) specific data * @ubwc_cfg: UBWC configuration for the platform * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory @@ -97,6 +98,7 @@ struct iris_core { struct reset_control_bulk_data *resets; struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; + const struct iris_firmware_data *iris_firmware_data; const struct qcom_ubwc_cfg_data *ubwc_cfg; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c index 5a24aa869b2dc..ef7adac3764d7 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -332,8 +332,8 @@ void iris_session_init_caps(struct iris_core *core) const struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; - caps = core->iris_platform_data->inst_fw_caps_dec; - num_cap = core->iris_platform_data->inst_fw_caps_dec_size; + caps = core->iris_firmware_data->inst_fw_caps_dec; + num_cap = core->iris_firmware_data->inst_fw_caps_dec_size; for (i = 0; i < num_cap; i++) { cap_id = caps[i].cap_id; @@ -360,8 +360,8 @@ void iris_session_init_caps(struct iris_core *core) } } - caps = core->iris_platform_data->inst_fw_caps_enc; - num_cap = core->iris_platform_data->inst_fw_caps_enc_size; + caps = core->iris_firmware_data->inst_fw_caps_enc; + num_cap = core->iris_firmware_data->inst_fw_caps_enc_size; for (i = 0; i < num_cap; i++) { cap_id = caps[i].cap_id; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 0017ade4adbd9..3fb90a466a64e 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1033,8 +1033,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p }; if (inst->domain == DECODER) { - config_params = core->iris_platform_data->dec_input_config_params_default; - config_params_size = core->iris_platform_data->dec_input_config_params_default_size; + config_params = core->iris_firmware_data->dec_input_config_params_default; + config_params_size = core->iris_firmware_data->dec_input_config_params_default_size; if (V4L2_TYPE_IS_OUTPUT(plane)) { handler = vdec_prop_type_handle_inp_arr; handler_size = ARRAY_SIZE(vdec_prop_type_handle_inp_arr); @@ -1043,8 +1043,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p handler_size = ARRAY_SIZE(vdec_prop_type_handle_out_arr); } } else { - config_params = core->iris_platform_data->enc_input_config_params; - config_params_size = core->iris_platform_data->enc_input_config_params_size; + config_params = core->iris_firmware_data->enc_input_config_params; + config_params_size = core->iris_firmware_data->enc_input_config_params_size; handler = venc_prop_type_handle_inp_arr; handler_size = ARRAY_SIZE(venc_prop_type_handle_inp_arr); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 90dd7f22f3040..7ac69af63eadb 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -600,7 +600,7 @@ static int iris_hfi_gen2_set_super_block(struct iris_inst *inst, u32 plane) static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *pdata = inst->core->iris_platform_data; + const struct iris_firmware_data *fdata = inst->core->iris_firmware_data; u32 config_params_size = 0, i, j; const u32 *config_params = NULL; int ret; @@ -629,31 +629,31 @@ static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 p if (inst->domain == DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { if (inst->codec == V4L2_PIX_FMT_H264) { - config_params = pdata->dec_input_config_params_default; - config_params_size = pdata->dec_input_config_params_default_size; + config_params = fdata->dec_input_config_params_default; + config_params_size = fdata->dec_input_config_params_default_size; } else if (inst->codec == V4L2_PIX_FMT_HEVC) { - config_params = pdata->dec_input_config_params_hevc; - config_params_size = pdata->dec_input_config_params_hevc_size; + config_params = fdata->dec_input_config_params_hevc; + config_params_size = fdata->dec_input_config_params_hevc_size; } else if (inst->codec == V4L2_PIX_FMT_VP9) { - config_params = pdata->dec_input_config_params_vp9; - config_params_size = pdata->dec_input_config_params_vp9_size; + config_params = fdata->dec_input_config_params_vp9; + config_params_size = fdata->dec_input_config_params_vp9_size; } else if (inst->codec == V4L2_PIX_FMT_AV1) { - config_params = pdata->dec_input_config_params_av1; - config_params_size = pdata->dec_input_config_params_av1_size; + config_params = fdata->dec_input_config_params_av1; + config_params_size = fdata->dec_input_config_params_av1_size; } else { return -EINVAL; } } else { - config_params = pdata->dec_output_config_params; - config_params_size = pdata->dec_output_config_params_size; + config_params = fdata->dec_output_config_params; + config_params_size = fdata->dec_output_config_params_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - config_params = pdata->enc_input_config_params; - config_params_size = pdata->enc_input_config_params_size; + config_params = fdata->enc_input_config_params; + config_params_size = fdata->enc_input_config_params_size; } else { - config_params = pdata->enc_output_config_params; - config_params_size = pdata->enc_output_config_params_size; + config_params = fdata->enc_output_config_params; + config_params_size = fdata->enc_output_config_params_size; } } @@ -848,24 +848,24 @@ static int iris_hfi_gen2_subscribe_change_param(struct iris_inst *inst, u32 plan switch (inst->codec) { case V4L2_PIX_FMT_H264: - change_param = core->iris_platform_data->dec_input_config_params_default; + change_param = core->iris_firmware_data->dec_input_config_params_default; change_param_size = - core->iris_platform_data->dec_input_config_params_default_size; + core->iris_firmware_data->dec_input_config_params_default_size; break; case V4L2_PIX_FMT_HEVC: - change_param = core->iris_platform_data->dec_input_config_params_hevc; + change_param = core->iris_firmware_data->dec_input_config_params_hevc; change_param_size = - core->iris_platform_data->dec_input_config_params_hevc_size; + core->iris_firmware_data->dec_input_config_params_hevc_size; break; case V4L2_PIX_FMT_VP9: - change_param = core->iris_platform_data->dec_input_config_params_vp9; + change_param = core->iris_firmware_data->dec_input_config_params_vp9; change_param_size = - core->iris_platform_data->dec_input_config_params_vp9_size; + core->iris_firmware_data->dec_input_config_params_vp9_size; break; case V4L2_PIX_FMT_AV1: - change_param = core->iris_platform_data->dec_input_config_params_av1; + change_param = core->iris_firmware_data->dec_input_config_params_av1; change_param_size = - core->iris_platform_data->dec_input_config_params_av1_size; + core->iris_firmware_data->dec_input_config_params_av1_size; break; } @@ -995,29 +995,29 @@ static int iris_hfi_gen2_subscribe_property(struct iris_inst *inst, u32 plane) return 0; if (V4L2_TYPE_IS_OUTPUT(plane)) { - subscribe_prop_size = core->iris_platform_data->dec_input_prop_size; - subcribe_prop = core->iris_platform_data->dec_input_prop; + subscribe_prop_size = core->iris_firmware_data->dec_input_prop_size; + subcribe_prop = core->iris_firmware_data->dec_input_prop; } else { switch (inst->codec) { case V4L2_PIX_FMT_H264: - subcribe_prop = core->iris_platform_data->dec_output_prop_avc; + subcribe_prop = core->iris_firmware_data->dec_output_prop_avc; subscribe_prop_size = - core->iris_platform_data->dec_output_prop_avc_size; + core->iris_firmware_data->dec_output_prop_avc_size; break; case V4L2_PIX_FMT_HEVC: - subcribe_prop = core->iris_platform_data->dec_output_prop_hevc; + subcribe_prop = core->iris_firmware_data->dec_output_prop_hevc; subscribe_prop_size = - core->iris_platform_data->dec_output_prop_hevc_size; + core->iris_firmware_data->dec_output_prop_hevc_size; break; case V4L2_PIX_FMT_VP9: - subcribe_prop = core->iris_platform_data->dec_output_prop_vp9; + subcribe_prop = core->iris_firmware_data->dec_output_prop_vp9; subscribe_prop_size = - core->iris_platform_data->dec_output_prop_vp9_size; + core->iris_firmware_data->dec_output_prop_vp9_size; break; case V4L2_PIX_FMT_AV1: - subcribe_prop = core->iris_platform_data->dec_output_prop_av1; + subcribe_prop = core->iris_firmware_data->dec_output_prop_av1; subscribe_prop_size = - core->iris_platform_data->dec_output_prop_av1_size; + core->iris_firmware_data->dec_output_prop_av1_size; break; } } diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index c539e5b7bcab3..13f10383fe483 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -200,44 +200,16 @@ enum platform_pm_domain_type { IRIS_APV_HW_POWER_DOMAIN, }; -struct iris_platform_data { +struct iris_firmware_data { void (*init_hfi_ops)(struct iris_core *core); - u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); - const struct vpu_ops *vpu_ops; - const struct icc_info *icc_tbl; - unsigned int icc_tbl_size; - const struct bw_info *bw_tbl_dec; - unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; - const char * const *opp_pd_tbl; - unsigned int opp_pd_tbl_size; - const struct platform_clk_data *clk_tbl; - const char * const *opp_clk_tbl; - unsigned int clk_tbl_size; - const char * const *clk_rst_tbl; - unsigned int clk_rst_tbl_size; - const char * const *controller_rst_tbl; - unsigned int controller_rst_tbl_size; - u64 dma_mask; - const char *fwname; - struct iris_fmt *inst_iris_fmts; - u32 inst_iris_fmts_size; - struct platform_inst_caps *inst_caps; + + u32 core_arch; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; - const struct tz_cp_config *tz_cp_config_data; - u32 tz_cp_config_data_size; - u32 core_arch; - u32 num_vpp_pipe; - bool no_aon; - u32 max_session_count; - /* max number of macroblocks per frame supported */ - u32 max_core_mbpf; - /* max number of macroblocks per second supported */ - u32 max_core_mbps; + const u32 *dec_input_config_params_default; unsigned int dec_input_config_params_default_size; const u32 *dec_input_config_params_hevc; @@ -252,6 +224,7 @@ struct iris_platform_data { unsigned int enc_input_config_params_size; const u32 *enc_output_config_params; unsigned int enc_output_config_params_size; + const u32 *dec_input_prop; unsigned int dec_input_prop_size; const u32 *dec_output_prop_avc; @@ -262,6 +235,7 @@ struct iris_platform_data { unsigned int dec_output_prop_vp9_size; const u32 *dec_output_prop_av1; unsigned int dec_output_prop_av1_size; + const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; @@ -272,4 +246,45 @@ struct iris_platform_data { unsigned int enc_op_int_buf_tbl_size; }; +struct iris_platform_data { + /* + * XXX: remove firmware_data pointer and consider moving + * get_vpu_buffer_size pointer once we have platforms supporting both + * firmware kinds. + */ + const struct iris_firmware_data *firmware_data; + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); + + const struct vpu_ops *vpu_ops; + const struct icc_info *icc_tbl; + unsigned int icc_tbl_size; + const struct bw_info *bw_tbl_dec; + unsigned int bw_tbl_dec_size; + const char * const *pmdomain_tbl; + unsigned int pmdomain_tbl_size; + const char * const *opp_pd_tbl; + unsigned int opp_pd_tbl_size; + const struct platform_clk_data *clk_tbl; + const char * const *opp_clk_tbl; + unsigned int clk_tbl_size; + const char * const *clk_rst_tbl; + unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; + u64 dma_mask; + const char *fwname; + struct iris_fmt *inst_iris_fmts; + u32 inst_iris_fmts_size; + struct platform_inst_caps *inst_caps; + const struct tz_cp_config *tz_cp_config_data; + u32 tz_cp_config_data_size; + u32 num_vpp_pipe; + bool no_aon; + u32 max_session_count; + /* max number of macroblocks per frame supported */ + u32 max_core_mbpf; + /* max number of macroblocks per second supported */ + u32 max_core_mbps; +}; + #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index 6592c1ed9ca50..9e632a973f476 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -332,8 +332,33 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { BUF_SCRATCH_2, }; -const struct iris_platform_data sm8250_data = { +const struct iris_firmware_data iris_hfi_gen1_data = { .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, + + .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), + + .dec_input_config_params_default = + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params = sm8250_venc_input_config_param, + .enc_input_config_params_size = + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; + +const struct iris_platform_data sm8250_data = { + .firmware_data = &iris_hfi_gen1_data, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -355,35 +380,16 @@ const struct iris_platform_data sm8250_data = { .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, - .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K, .max_core_mbps = ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default = - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params = sm8250_venc_input_config_param, - .enc_input_config_params_size = - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; const struct iris_platform_data sc7280_data = { - .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, + .firmware_data = &iris_hfi_gen1_data, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu2_ops, .icc_tbl = sm8250_icc_table, @@ -403,10 +409,6 @@ const struct iris_platform_data sc7280_data = { .inst_iris_fmts = platform_fmts_sm8250_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps = &platform_inst_cap_sm8250, - .inst_fw_caps_dec = inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data = tz_cp_config_sm8250, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), .num_vpp_pipe = 1, @@ -415,19 +417,4 @@ const struct iris_platform_data sc7280_data = { .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ .max_core_mbps = 4096 * 2176 / 256 * 60, - .dec_input_config_params_default = - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params = sm8250_venc_input_config_param, - .enc_input_config_params_size = - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index abe523db45c2c..05fbab276100a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -906,40 +906,16 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { BUF_SCRATCH_2, }; -const struct iris_platform_data sm8550_data = { +const struct iris_firmware_data iris_hfi_gen2_data = { .init_hfi_ops = iris_hfi_gen2_sys_ops_init, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu3_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8550_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, + + .core_arch = VIDEO_ARCH_LX, + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch = VIDEO_ARCH_LX, - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default = sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size = @@ -996,6 +972,37 @@ const struct iris_platform_data sm8550_data = { .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; +const struct iris_platform_data sm8550_data = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu3_ops, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = sm8550_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl = sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_sm8550, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; + /* * Shares most of SM8550 data except: * - vpu_ops to iris_vpu33_ops @@ -1004,7 +1011,7 @@ const struct iris_platform_data sm8550_data = { * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu33_ops, .icc_tbl = sm8550_icc_table, @@ -1028,75 +1035,16 @@ const struct iris_platform_data sm8650_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, - .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch = VIDEO_ARCH_LX, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default = - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc = - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 = - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 = - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params = - sm8550_vdec_output_config_params, - .dec_output_config_params_size = - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params = - sm8550_venc_input_config_params, - .enc_input_config_params_size = - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params = - sm8550_venc_output_config_params, - .enc_output_config_params_size = - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop = sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), - .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; const struct iris_platform_data sm8750_data = { - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu33_buf_size, .vpu_ops = &iris_vpu35_ops, .icc_tbl = sm8550_icc_table, @@ -1118,71 +1066,12 @@ const struct iris_platform_data sm8750_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_sm8550, - .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch = VIDEO_ARCH_LX, .num_vpp_pipe = 4, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default = - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc = - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 = - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 = - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params = - sm8550_vdec_output_config_params, - .dec_output_config_params_size = - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params = - sm8550_venc_input_config_params, - .enc_input_config_params_size = - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params = - sm8550_venc_output_config_params, - .enc_output_config_params_size = - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop = sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), - .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; /* @@ -1190,7 +1079,7 @@ const struct iris_platform_data sm8750_data = { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .init_hfi_ops = iris_hfi_gen2_sys_ops_init, + .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, .icc_tbl = sm8550_icc_table, @@ -1212,69 +1101,10 @@ const struct iris_platform_data qcs8300_data = { .inst_iris_fmts = platform_fmts_sm8550_dec, .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps = &platform_inst_cap_qcs8300, - .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data = tz_cp_config_sm8550, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch = VIDEO_ARCH_LX, .num_vpp_pipe = 2, .max_session_count = 16, .max_core_mbpf = ((4096 * 2176) / 256) * 4, .max_core_mbps = (((3840 * 2176) / 256) * 120), - .dec_input_config_params_default = - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size = - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc = - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 = - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 = - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size = - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params = - sm8550_vdec_output_config_params, - .dec_output_config_params_size = - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params = - sm8550_venc_input_config_params, - .enc_input_config_params_size = - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params = - sm8550_venc_output_config_params, - .enc_output_config_params_size = - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop = sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), - .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size = - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index c2d174a6e1608..009aaa6d82e77 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -244,6 +244,7 @@ static int iris_probe(struct platform_device *pdev) return core->irq; core->iris_platform_data = of_device_get_match_data(core->dev); + core->iris_firmware_data = core->iris_platform_data->firmware_data; core->ubwc_cfg = qcom_ubwc_config_get_data(); if (IS_ERR(core->ubwc_cfg)) @@ -257,7 +258,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); iris_init_ops(core); - core->iris_platform_data->init_hfi_ops(core); + core->iris_firmware_data->init_hfi_ops(core); ret = iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 814e8ff76f67e..372408b894c19 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -246,7 +246,7 @@ static void iris_session_close(struct iris_inst *inst) static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data = inst->core->iris_platform_data; + const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -254,11 +254,11 @@ static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 p u32 count = 0; if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type = platform_data->dec_ip_int_buf_tbl; - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type = platform_data->dec_op_int_buf_tbl; - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; + internal_buf_type = firmware_data->dec_op_int_buf_tbl; + internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size; } for (i = 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index e77e94ac982b8..7bba3b6209c20 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -63,7 +63,7 @@ static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core) writel(QTBL_ENABLE, core->reg_base + QTBL_INFO); if (core->sfr_daddr) { - value = (u32)core->sfr_daddr + core->iris_platform_data->core_arch; + value = (u32)core->sfr_daddr + core->iris_firmware_data->core_arch; writel(value, core->reg_base + SFR_ADDR); } From 79d0792b0d1f33e88b544228631d773869a5beeb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:10 +0200 Subject: [PATCH 1226/1330] FROMGIT: media: qcom: iris: split platform data from firmware data Finalize the logical separation of the software and hardware interface descriptions by moving hardware properties to the files specific to the particular VPU version. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-9-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 5f21ce799f4c3e98109b85dc024bb69f938d077a) (cherry picked from commit 7b32dbd8323317f67a2466a4b63c57e8258c3705) --- drivers/media/platform/qcom/iris/Makefile | 6 +- .../{iris_platform_gen1.c => iris_hfi_gen1.c} | 134 ----------- .../{iris_platform_gen2.c => iris_hfi_gen2.c} | 214 ------------------ .../platform/qcom/iris/iris_platform_common.h | 3 + .../platform/qcom/iris/iris_platform_sm8250.h | 29 +++ .../platform/qcom/iris/iris_platform_sm8550.h | 1 + .../platform/qcom/iris/iris_platform_vpu2.c | 124 ++++++++++ .../platform/qcom/iris/iris_platform_vpu3x.c | 82 ------- 8 files changed, 161 insertions(+), 432 deletions(-) rename drivers/media/platform/qcom/iris/{iris_platform_gen1.c => iris_hfi_gen1.c} (67%) rename drivers/media/platform/qcom/iris/{iris_platform_gen2.c => iris_hfi_gen2.c} (77%) create mode 100644 drivers/media/platform/qcom/iris/iris_platform_sm8250.h create mode 100644 drivers/media/platform/qcom/iris/iris_platform_vpu2.c diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 2fde45f817276..48e415cbc4390 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -4,14 +4,16 @@ qcom-iris-objs += iris_buffer.o \ iris_ctrls.o \ iris_firmware.o \ iris_hfi_common.o \ + iris_hfi_gen1.o \ iris_hfi_gen1_command.o \ iris_hfi_gen1_response.o \ + iris_hfi_gen2.o \ iris_hfi_gen2_command.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_gen1.o \ - iris_platform_gen2.o \ + iris_platform_vpu2.o \ + iris_platform_vpu3x.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c similarity index 67% rename from drivers/media/platform/qcom/iris/iris_platform_gen1.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen1.c index 9e632a973f476..60f51a1ba9412 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -3,38 +3,16 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_platform_common.h" -#include "iris_resources.h" #include "iris_hfi_gen1.h" #include "iris_hfi_gen1_defines.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" -#include "iris_instance.h" - -#include "iris_platform_sc7280.h" #define BITRATE_MIN 32000 #define BITRATE_MAX 160000000 -#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 -static struct iris_fmt platform_fmts_sm8250_dec[] = { - [IRIS_FMT_H264] = { - .pixfmt = V4L2_PIX_FMT_H264, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] = { - .pixfmt = V4L2_PIX_FMT_HEVC, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] = { - .pixfmt = V4L2_PIX_FMT_VP9, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = { { .cap_id = PIPE, @@ -248,56 +226,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = { }, }; -static struct platform_inst_caps platform_inst_cap_sm8250 = { - .min_frame_width = 128, - .max_frame_width = 8192, - .min_frame_height = 128, - .max_frame_height = 8192, - .max_mbpf = 138240, - .mb_cycles_vsp = 25, - .mb_cycles_vpp = 200, - .max_frame_rate = MAXIMUM_FPS, - .max_operating_rate = MAXIMUM_FPS, -}; - -static const struct icc_info sm8250_icc_table[] = { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8250_clk_reset_table[] = { "bus", "core" }; - -static const struct bw_info sm8250_bw_table_dec[] = { - { ((4096 * 2160) / 256) * 60, 2403000 }, - { ((4096 * 2160) / 256) * 30, 1224000 }, - { ((1920 * 1080) / 256) * 60, 812000 }, - { ((1920 * 1080) / 256) * 30, 416000 }, -}; - -static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" }; - -static const char * const sm8250_opp_pd_table[] = { "mx" }; - -static const struct platform_clk_data sm8250_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8250_opp_clk_table[] = { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8250[] = { - { - .cp_start = 0, - .cp_size = 0x25800000, - .cp_nonpixel_start = 0x01000000, - .cp_nonpixel_size = 0x24800000, - }, -}; - static const u32 sm8250_vdec_input_config_param_default[] = { HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, @@ -356,65 +284,3 @@ const struct iris_firmware_data iris_hfi_gen1_data = { .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; - -const struct iris_platform_data sm8250_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu2_ops, - .icc_tbl = sm8250_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), - .clk_rst_tbl = sm8250_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table), - .bw_tbl_dec = sm8250_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl = sm8250_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl = sm8250_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), - .clk_tbl = sm8250_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table), - .opp_clk_tbl = sm8250_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu-1.0/venus.mbn", - .inst_iris_fmts = platform_fmts_sm8250_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps = &platform_inst_cap_sm8250, - .tz_cp_config_data = tz_cp_config_sm8250, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sc7280_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu2_ops, - .icc_tbl = sm8250_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), - .bw_tbl_dec = sc7280_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl = sm8250_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl = sc7280_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), - .clk_tbl = sc7280_clk_table, - .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table), - .opp_clk_tbl = sc7280_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu20_p1.mbn", - .inst_iris_fmts = platform_fmts_sm8250_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps = &platform_inst_cap_sm8250, - .tz_cp_config_data = tz_cp_config_sm8250, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250), - .num_vpp_pipe = 1, - .no_aon = true, - .max_session_count = 16, - .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, - /* max spec for SC7280 is 4096x2176@60fps */ - .max_core_mbps = 4096 * 2176 / 256 * 60, -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c similarity index 77% rename from drivers/media/platform/qcom/iris/iris_platform_gen2.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen2.c index 05fbab276100a..ce8490d64854c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c @@ -4,40 +4,15 @@ * Copyright (c) 2025 Linaro Ltd */ -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_hfi_gen2.h" #include "iris_hfi_gen2_defines.h" #include "iris_platform_common.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" - -#include "iris_platform_qcs8300.h" -#include "iris_platform_sm8650.h" -#include "iris_platform_sm8750.h" #define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 -static struct iris_fmt platform_fmts_sm8550_dec[] = { - [IRIS_FMT_H264] = { - .pixfmt = V4L2_PIX_FMT_H264, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] = { - .pixfmt = V4L2_PIX_FMT_HEVC, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] = { - .pixfmt = V4L2_PIX_FMT_VP9, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_AV1] = { - .pixfmt = V4L2_PIX_FMT_AV1, - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = { { .cap_id = PROFILE_H264, @@ -742,58 +717,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = { }, }; -static struct platform_inst_caps platform_inst_cap_sm8550 = { - .min_frame_width = 96, - .max_frame_width = 8192, - .min_frame_height = 96, - .max_frame_height = 8192, - .max_mbpf = (8192 * 4352) / 256, - .mb_cycles_vpp = 200, - .mb_cycles_fw = 489583, - .mb_cycles_fw_vpp = 66234, - .num_comv = 0, - .max_frame_rate = MAXIMUM_FPS, - .max_operating_rate = MAXIMUM_FPS, -}; - -static const struct icc_info sm8550_icc_table[] = { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8550_clk_reset_table[] = { "bus" }; - -static const struct bw_info sm8550_bw_table_dec[] = { - { ((4096 * 2160) / 256) * 60, 1608000 }, - { ((4096 * 2160) / 256) * 30, 826000 }, - { ((1920 * 1080) / 256) * 60, 567000 }, - { ((1920 * 1080) / 256) * 30, 294000 }, -}; - -static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" }; - -static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" }; - -static const struct platform_clk_data sm8550_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8550_opp_clk_table[] = { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8550[] = { - { - .cp_start = 0, - .cp_size = 0x25800000, - .cp_nonpixel_start = 0x01000000, - .cp_nonpixel_size = 0x24800000, - }, -}; - static const u32 sm8550_vdec_input_config_params_default[] = { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, @@ -971,140 +894,3 @@ const struct iris_firmware_data iris_hfi_gen2_data = { .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; - -const struct iris_platform_data sm8550_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu3_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8550_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - vpu_ops to iris_vpu33_ops - * - clk_rst_tbl to sm8650_clk_reset_table - * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" - */ -const struct iris_platform_data sm8650_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, - .vpu_ops = &iris_vpu33_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8650_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table), - .controller_rst_tbl = sm8650_controller_reset_table, - .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu33_p4.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sm8750_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, - .vpu_ops = &iris_vpu35_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8750_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8750_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu35_p4.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_sm8550, - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .num_vpp_pipe = 4, - .max_session_count = 16, - .max_core_mbpf = NUM_MBS_8K * 2, - .max_core_mbps = ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - inst_caps to platform_inst_cap_qcs8300 - */ -const struct iris_platform_data qcs8300_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .vpu_ops = &iris_vpu3_ops, - .icc_tbl = sm8550_icc_table, - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl = sm8550_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec = sm8550_bw_table_dec, - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl = sm8550_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl = sm8550_opp_pd_table, - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4_s6.mbn", - .inst_iris_fmts = platform_fmts_sm8550_dec, - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps = &platform_inst_cap_qcs8300, - .tz_cp_config_data = tz_cp_config_sm8550, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), - .num_vpp_pipe = 2, - .max_session_count = 16, - .max_core_mbpf = ((4096 * 2176) / 256) * 4, - .max_core_mbps = (((3840 * 2176) / 256) * 120), -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 13f10383fe483..a696bd3b0f24e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -40,6 +40,9 @@ enum pipe_type { PIPE_4 = 4, }; +extern const struct iris_firmware_data iris_hfi_gen1_data; +extern const struct iris_firmware_data iris_hfi_gen2_data; + extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h new file mode 100644 index 0000000000000..50306043eb8ec --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __IRIS_PLATFORM_SM8250_H__ +#define __IRIS_PLATFORM_SM8250_H__ + +static const struct bw_info sm8250_bw_table_dec[] = { + { ((4096 * 2160) / 256) * 60, 2403000 }, + { ((4096 * 2160) / 256) * 30, 1224000 }, + { ((1920 * 1080) / 256) * 60, 812000 }, + { ((1920 * 1080) / 256) * 30, 416000 }, +}; + +static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" }; + +static const struct platform_clk_data sm8250_clk_table[] = { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static const char * const sm8250_opp_clk_table[] = { + "vcodec0_core", + NULL, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h index 3c9dae995bb24..a9d9709c2e352 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -23,6 +23,7 @@ static struct platform_inst_caps platform_inst_cap_sm8550 = { .mb_cycles_vpp = 200, .mb_cycles_fw = 489583, .mb_cycles_fw_vpp = 66234, + .num_comv = 0, .max_frame_rate = MAXIMUM_FPS, .max_operating_rate = MAXIMUM_FPS, }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c new file mode 100644 index 0000000000000..ab2a19aa9c36c --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_platform_common.h" +#include "iris_resources.h" +#include "iris_hfi_gen1.h" +#include "iris_hfi_gen1_defines.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" +#include "iris_instance.h" + +#include "iris_platform_sc7280.h" +#include "iris_platform_sm8250.h" + +static struct iris_fmt iris_fmts_vpu2_dec[] = { + [IRIS_FMT_H264] = { + .pixfmt = V4L2_PIX_FMT_H264, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] = { + .pixfmt = V4L2_PIX_FMT_HEVC, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] = { + .pixfmt = V4L2_PIX_FMT_VP9, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static struct platform_inst_caps platform_inst_cap_vpu2 = { + .min_frame_width = 128, + .max_frame_width = 8192, + .min_frame_height = 128, + .max_frame_height = 8192, + .max_mbpf = 138240, + .mb_cycles_vsp = 25, + .mb_cycles_vpp = 200, + .max_frame_rate = MAXIMUM_FPS, + .max_operating_rate = MAXIMUM_FPS, +}; + +static const struct icc_info iris_icc_info_vpu2[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" }; + +static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" }; + +static const struct tz_cp_config tz_cp_config_vpu2[] = { + { + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x01000000, + .cp_nonpixel_size = 0x24800000, + }, +}; + +const struct iris_platform_data sc7280_data = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu2_ops, + .icc_tbl = iris_icc_info_vpu2, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), + .bw_tbl_dec = sc7280_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), + .pmdomain_tbl = iris_pmdomain_table_vpu2, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), + .opp_pd_tbl = sc7280_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), + .clk_tbl = sc7280_clk_table, + .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table), + .opp_clk_tbl = sc7280_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu20_p1.mbn", + .inst_iris_fmts = iris_fmts_vpu2_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), + .inst_caps = &platform_inst_cap_vpu2, + .tz_cp_config_data = tz_cp_config_vpu2, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), + .num_vpp_pipe = 1, + .no_aon = true, + .max_session_count = 16, + .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, + /* max spec for SC7280 is 4096x2176@60fps */ + .max_core_mbps = 4096 * 2176 / 256 * 60, +}; + +const struct iris_platform_data sm8250_data = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu2_ops, + .icc_tbl = iris_icc_info_vpu2, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), + .clk_rst_tbl = iris_clk_reset_table_vpu2, + .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2), + .bw_tbl_dec = sm8250_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), + .pmdomain_tbl = iris_pmdomain_table_vpu2, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), + .opp_pd_tbl = sm8250_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), + .clk_tbl = sm8250_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table), + .opp_clk_tbl = sm8250_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu-1.0/venus.mbn", + .inst_iris_fmts = iris_fmts_vpu2_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), + .inst_caps = &platform_inst_cap_vpu2, + .tz_cp_config_data = tz_cp_config_vpu2, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index cbd13a2e09b1b..c2496aa0f8513 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -66,85 +66,6 @@ static const struct tz_cp_config tz_cp_config_vpu3[] = { }, }; -/* - * Shares most of SM8550 data except: - * - inst_caps to platform_inst_cap_qcs8300 - */ -const struct iris_platform_data qcs8300_data = { - .firmware_desc_gen2 = &iris_vpu30_p4_s6_gen2_desc, - .vpu_ops = &iris_vpu3_ops, - .icc_tbl = iris_icc_info_vpu3x, - .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), - .clk_rst_tbl = sm8550_clk_reset_table, - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec = iris_bw_table_dec_vpu3x, - .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = &iris_pmdomain_table_vpu3x, - .opp_pd_tbl = iris_opp_pd_table_vpu3x, - .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl = sm8550_clk_table, - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl = iris_opp_clk_table_vpu3x, - /* Upper bound of DMA address range */ - .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu3x_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), - .inst_caps = &platform_inst_cap_qcs8300, - .tz_cp_config_data = tz_cp_config_vpu3, - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), - .num_vpp_pipe = 2, - .max_session_count = 16, - .max_core_mbpf = ((4096 * 2176) / 256) * 4, - .max_core_mbps = (((3840 * 2176) / 256) * 120), -}; - -static int sm8550_init_cb_devs(struct iris_core *core) -{ - const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ - const u32 f_id_p = 1; /* IRIS_PIXEL */ - struct device *dev; - - dev = iris_create_cb_dev(core, "iris_non_pixel", &f_id_np); - if (IS_ERR(dev)) - return PTR_ERR(dev); - - core->dev_np = dev; - core->dev_bs = core->dev_np; - - dev = iris_create_cb_dev(core, "iris_pixel", &f_id_p); - if (IS_ERR(dev)) - goto err_unreg_dev_np; - - core->dev_p = dev; - - return 0; - -err_unreg_dev_np: - platform_device_unregister(to_platform_device(core->dev_np)); - core->dev_np = NULL; - core->dev_bs = NULL; - - return PTR_ERR(dev); -} - -const struct iris_firmware_desc iris_vpu36_p4_s7_gen2_desc = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, - .fwname = "qcom/vpu/vpu36_p4_s7.mbn", -}; - -static void sm8550_deinit_cb_devs(struct iris_core *core) -{ - if (core->dev_np) - platform_device_unregister(to_platform_device(core->dev_np)); - if (core->dev_p) - platform_device_unregister(to_platform_device(core->dev_p)); - - core->dev_np = NULL; - core->dev_bs = NULL; - core->dev_p = NULL; -} - /* * Shares most of SM8550 data except: * - inst_caps to platform_inst_cap_qcs8300 @@ -174,7 +95,6 @@ const struct iris_platform_data qcs8300_data = { .inst_caps = &platform_inst_cap_qcs8300, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), - .ubwc_config = &iris_ubwc_config_vpu3x, .num_vpp_pipe = 2, .max_session_count = 16, .max_core_mbpf = ((4096 * 2176) / 256) * 4, @@ -185,8 +105,6 @@ const struct iris_platform_data sm8550_data = { .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, .vpu_ops = &iris_vpu3_ops, - .init_cb_devs = sm8550_init_cb_devs, - .deinit_cb_devs = sm8550_deinit_cb_devs, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), .clk_rst_tbl = sm8550_clk_reset_table, From 20cf3fc979d31884d7b96c97bd5aad2115d4cb56 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:11 +0200 Subject: [PATCH 1227/1330] FROMGIT: media: qcom: iris: use new firmware name for SM8250 The linux-firmware is providing the vpuNN_pM.mbn firmware for SM8250 since August of 2024. Stop using the legacy firmware name (vpu-1.0/venus.mbn) and switch to the standard firmware name schema (vpu/vpu20_p4.mbn). Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-10-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Vikash Garodia Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov Signed-off-by: Bryan O'Donoghue (cherry picked from commit 8425f4c9924073717b48adc7f93cc5b57c224088) (cherry picked from commit bc755d8a96e5434aeb70416cad199b79502936f9) --- drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index ab2a19aa9c36c..692fbc2aab564 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -111,7 +111,7 @@ const struct iris_platform_data sm8250_data = { .opp_clk_tbl = sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu-1.0/venus.mbn", + .fwname = "qcom/vpu/vpu20_p4.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, From c193db1ddc961400fcf25f5c93effc61f3627b1d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Mar 2026 02:33:12 +0200 Subject: [PATCH 1228/1330] FROMGIT: media: qcom: iris: extract firmware description data In preparation to adding support for several firmware revisions to be used for a platform, extract the firmware description data. It incorporates firmware name, HFI ops and buffer requirements of the particular firmware build. Link: https://lore.kernel.org/linux-media/20260329-iris-platform-data-v11-11-eea672b03a95@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov [bod: Made struct iris_firmware_desc into static consts to pass media CI] Signed-off-by: Bryan O'Donoghue (cherry picked from commit d93f64b9caa6af56620d8b030a6d33b4b814ccac) (cherry picked from commit 966227317f6582412d44d9940e632d1da81d6ce7) --- .../media/platform/qcom/iris/iris_buffer.c | 2 +- drivers/media/platform/qcom/iris/iris_core.h | 2 + .../media/platform/qcom/iris/iris_firmware.c | 2 +- .../qcom/iris/iris_hfi_gen1_command.c | 2 +- .../platform/qcom/iris/iris_platform_common.h | 15 ++++--- .../platform/qcom/iris/iris_platform_vpu2.c | 20 ++++++--- .../platform/qcom/iris/iris_platform_vpu3x.c | 41 +++++++++++++------ drivers/media/platform/qcom/iris/iris_probe.c | 3 +- 8 files changed, 58 insertions(+), 29 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 95b9a370c972c..60e3d14450c8b 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -295,7 +295,7 @@ static void iris_fill_internal_buf_info(struct iris_inst *inst, { struct iris_buffers *buffers = &inst->buffers[buffer_type]; - buffers->size = inst->core->iris_platform_data->get_vpu_buffer_size(inst, buffer_type); + buffers->size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, buffer_type); buffers->min_count = iris_vpu_buf_count(inst, buffer_type); } diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index e0ca245c8c63a..24da60448cf24 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -55,6 +55,7 @@ struct qcom_ubwc_cfg_data; * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data * @iris_firmware_data: a pointer to the firmware (or HFI) specific data + * @iris_firmware_desc: a pointer to the firmware-specific descriptive data * @ubwc_cfg: UBWC configuration for the platform * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory @@ -99,6 +100,7 @@ struct iris_core { struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; const struct iris_firmware_data *iris_firmware_data; + const struct iris_firmware_desc *iris_firmware_desc; const struct qcom_ubwc_cfg_data *ubwc_cfg; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index cef89fd3a00b6..be032eb5f79c7 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -146,7 +146,7 @@ int iris_fw_load(struct iris_core *core) ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0, &fwpath); if (ret) - fwpath = core->iris_platform_data->fwname; + fwpath = core->iris_firmware_desc->fwname; ret = iris_load_fw_to_memory(core, fwpath); if (ret) { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 3fb90a466a64e..83373862655f7 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -918,7 +918,7 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst *inst, u32 plane) if (iris_split_mode_enabled(inst)) { bufsz.type = HFI_BUFFER_OUTPUT; - bufsz.size = inst->core->iris_platform_data->get_vpu_buffer_size(inst, BUF_DPB); + bufsz.size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, BUF_DPB); ret = hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz)); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index a696bd3b0f24e..9ae7f9f7103ef 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -249,14 +249,18 @@ struct iris_firmware_data { unsigned int enc_op_int_buf_tbl_size; }; +struct iris_firmware_desc { + const struct iris_firmware_data *firmware_data; + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); + const char *fwname; +}; + struct iris_platform_data { /* - * XXX: remove firmware_data pointer and consider moving - * get_vpu_buffer_size pointer once we have platforms supporting both - * firmware kinds. + * XXX: replace with gen1 / gen2 pointers once we have platforms + * supporting both firmware kinds. */ - const struct iris_firmware_data *firmware_data; - u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type); + const struct iris_firmware_desc *firmware_desc; const struct vpu_ops *vpu_ops; const struct icc_info *icc_tbl; @@ -275,7 +279,6 @@ struct iris_platform_data { const char * const *controller_rst_tbl; unsigned int controller_rst_tbl_size; u64 dma_mask; - const char *fwname; struct iris_fmt *inst_iris_fmts; u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 692fbc2aab564..41986af8313b1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -16,6 +16,18 @@ #include "iris_platform_sc7280.h" #include "iris_platform_sm8250.h" +static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu20_p1.mbn", +}; + +static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = { + .firmware_data = &iris_hfi_gen1_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu20_p4.mbn", +}; + static struct iris_fmt iris_fmts_vpu2_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -62,8 +74,7 @@ static const struct tz_cp_config tz_cp_config_vpu2[] = { }; const struct iris_platform_data sc7280_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, + .firmware_desc = &iris_vpu20_p1_gen1_desc, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), @@ -78,7 +89,6 @@ const struct iris_platform_data sc7280_data = { .opp_clk_tbl = sc7280_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu20_p1.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, @@ -93,8 +103,7 @@ const struct iris_platform_data sc7280_data = { }; const struct iris_platform_data sm8250_data = { - .firmware_data = &iris_hfi_gen1_data, - .get_vpu_buffer_size = iris_vpu_buf_size, + .firmware_desc = &iris_vpu20_p4_gen1_desc, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), @@ -111,7 +120,6 @@ const struct iris_platform_data sm8250_data = { .opp_clk_tbl = sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu20_p4.mbn", .inst_iris_fmts = iris_fmts_vpu2_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index c2496aa0f8513..c249ff8275414 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -17,6 +17,30 @@ #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" +static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu30_p4_s6.mbn", +}; + +static const struct iris_firmware_desc iris_vpu30_p4_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu30_p4.mbn", +}; + +static const struct iris_firmware_desc iris_vpu33_p4_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .fwname = "qcom/vpu/vpu33_p4.mbn", +}; + +static const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .fwname = "qcom/vpu/vpu35_p4.mbn", +}; + static struct iris_fmt iris_fmts_vpu3x_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -71,8 +95,7 @@ static const struct tz_cp_config tz_cp_config_vpu3[] = { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, + .firmware_desc = &iris_vpu30_p4_s6_gen2_desc, .vpu_ops = &iris_vpu3_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -89,7 +112,6 @@ const struct iris_platform_data qcs8300_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4_s6.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_qcs8300, @@ -102,8 +124,7 @@ const struct iris_platform_data qcs8300_data = { }; const struct iris_platform_data sm8550_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu_buf_size, + .firmware_desc = &iris_vpu30_p4_gen2_desc, .vpu_ops = &iris_vpu3_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -120,7 +141,6 @@ const struct iris_platform_data sm8550_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu30_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -137,11 +157,9 @@ const struct iris_platform_data sm8550_data = { * - vpu_ops to iris_vpu33_ops * - clk_rst_tbl to sm8650_clk_reset_table * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, + .firmware_desc = &iris_vpu33_p4_gen2_desc, .vpu_ops = &iris_vpu33_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -160,7 +178,6 @@ const struct iris_platform_data sm8650_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu33_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, @@ -173,8 +190,7 @@ const struct iris_platform_data sm8650_data = { }; const struct iris_platform_data sm8750_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu33_buf_size, + .firmware_desc = &iris_vpu35_p4_gen2_desc, .vpu_ops = &iris_vpu35_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -191,7 +207,6 @@ const struct iris_platform_data sm8750_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu35_p4.mbn", .inst_iris_fmts = iris_fmts_vpu3x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 009aaa6d82e77..ed9f037708691 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -244,7 +244,8 @@ static int iris_probe(struct platform_device *pdev) return core->irq; core->iris_platform_data = of_device_get_match_data(core->dev); - core->iris_firmware_data = core->iris_platform_data->firmware_data; + core->iris_firmware_desc = core->iris_platform_data->firmware_desc; + core->iris_firmware_data = core->iris_firmware_desc->firmware_data; core->ubwc_cfg = qcom_ubwc_config_get_data(); if (IS_ERR(core->ubwc_cfg)) From 4ecf88b457b11cc51ee4f97fd5c7ea4a0a8e86a4 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Tue, 12 May 2026 18:21:09 +0300 Subject: [PATCH 1229/1330] FROMLIST: media: iris: Initialize HFI ops after firmware load in core init The HFI sys ops were previously initialized in probe() but, we don't have firmware loaded at probe time. Since HFI is tightly coupled to firmware, initialize the HFI sys ops after firmware has been successfully loaded and booted. Link: https://lore.kernel.org/all/20260512-kodiak-gen2-support-v4-v5-1-a98968423d24@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov (cherry picked from commit e884383c836b0c7a9b1fcf5ee20bfa773a123270) (cherry picked from commit 81152e72d2d885dd25eae698f8de2f2083960251) --- drivers/media/platform/qcom/iris/iris_probe.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index ed9f037708691..e847e74854ad4 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -259,7 +259,6 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); iris_init_ops(core); - core->iris_firmware_data->init_hfi_ops(core); ret = iris_init_resources(core); if (ret) From 027f21993d45f45548e3daa01271cf0bf91f9f2b Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Tue, 12 May 2026 18:21:10 +0300 Subject: [PATCH 1230/1330] FROMLIST: media: iris: Add Gen2 firmware autodetect and fallback Some Iris platforms support both Gen1 and Gen2 HFI firmware images. Update the firmware loading logic to handle this generically by preferring Gen2 when available, while safely falling back to Gen1 when required. The firmware loading logic is updated with the following priority: 1. Device Tree (`firmware-name`): If specified, load unconditionally. 2. Gen2 default : If no DT override exists, select the Gen2 firmware descriptor when present and attempt to load the corresponding firmware image. 3. Gen1 Fallback: If loading the Gen2 firmware fails and a Gen1 descriptor is available, retry with the Gen1 firmware image. When a platform provides both Gen1 and Gen2 firmware descriptors and the firmware is loaded via a DT override, the driver detects the firmware generation at runtime before authentication by inspecting the firmware data. The firmware is classified as Gen2 if the QC_IMAGE_VERSION_STRING starts with "vfw" or matches the "video-firmware.N.M" format with N >= 2. If a Gen1 firmware image is detected in this case, the driver switches to the Gen1 firmware descriptor and associated platform data so that the correct HFI implementation is used. This change makes firmware generation detection platform-agnostic, preserves DT overrides, prefers newer Gen2 firmware when available, and maintains compatibility with platforms that only support Gen1. Link: https://lore.kernel.org/all/20260512-kodiak-gen2-support-v4-v5-2-a98968423d24@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal Co-developed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov (cherry picked from commit 3a4ae830e1d3c92a3ca1bd0c4699f6ed25b773e7) (cherry picked from commit ffc4196a6afc1e40206defe19c8df54e61496431) --- .../media/platform/qcom/iris/iris_firmware.c | 29 +++-- .../platform/qcom/iris/iris_platform_common.h | 6 +- .../platform/qcom/iris/iris_platform_vpu2.c | 11 +- .../platform/qcom/iris/iris_platform_vpu3x.c | 114 +++++++++++++++++- .../platform/qcom/iris/iris_platform_vpu4x.c | 3 +- drivers/media/platform/qcom/iris/iris_probe.c | 6 +- 6 files changed, 138 insertions(+), 31 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index be032eb5f79c7..20c07e2ba299f 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -112,9 +112,19 @@ static int iris_load_fw_to_memory(struct iris_core *core) mem_phys = res.start; res_size = resource_size(&res); - ret = request_firmware(&firmware, fw_name, dev); - if (ret) - return ret; + dev = core->fw.dev ? : core->dev; + + ctx = devm_qcom_scm_pas_context_alloc(dev, IRIS_PAS_ID, mem_phys, res_size); + if (!ctx) + return -ENOMEM; + + ctx->use_tzmem = core->fw.dev; + + firmware = iris_detect_firmware(core, &fw_name); + if (IS_ERR(firmware)) + return PTR_ERR(firmware); + + core->iris_firmware_data = core->iris_firmware_desc->firmware_data; fw_size = qcom_mdt_get_size(firmware); if (fw_size < 0 || res_size < (size_t)fw_size) { @@ -143,23 +153,12 @@ int iris_fw_load(struct iris_core *core) const struct tz_cp_config *cp_config; int i, ret; - ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0, - &fwpath); - if (ret) - fwpath = core->iris_firmware_desc->fwname; - - ret = iris_load_fw_to_memory(core, fwpath); + ret = iris_load_fw_to_memory(core); if (ret) { dev_err(core->dev, "firmware download failed %d\n", ret); return ret; } - ret = qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); - if (ret) { - dev_err(core->dev, "auth and reset failed: %d\n", ret); - return ret; - } - for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { cp_config = &core->iris_platform_data->tz_cp_config_data[i]; ret = qcom_scm_mem_protect_video_var(cp_config->cp_start, diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 9ae7f9f7103ef..33c46347c272b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -256,11 +256,7 @@ struct iris_firmware_desc { }; struct iris_platform_data { - /* - * XXX: replace with gen1 / gen2 pointers once we have platforms - * supporting both firmware kinds. - */ - const struct iris_firmware_desc *firmware_desc; + const struct iris_firmware_desc *firmware_desc_gen1, *firmware_desc_gen2; const struct vpu_ops *vpu_ops; const struct icc_info *icc_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 41986af8313b1..4a020300bb794 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -22,6 +22,12 @@ static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = { .fwname = "qcom/vpu/vpu20_p1.mbn", }; +static const struct iris_firmware_desc iris_vpu20_p1_gen2_s6_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu33_buf_size, + .fwname = "qcom/vpu/vpu20_p1_gen2_s6.mbn", +}; + static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = { .firmware_data = &iris_hfi_gen1_data, .get_vpu_buffer_size = iris_vpu_buf_size, @@ -74,7 +80,8 @@ static const struct tz_cp_config tz_cp_config_vpu2[] = { }; const struct iris_platform_data sc7280_data = { - .firmware_desc = &iris_vpu20_p1_gen1_desc, + .firmware_desc_gen1 = &iris_vpu20_p1_gen1_desc, + .firmware_desc_gen2 = &iris_vpu20_p1_gen2_s6_desc, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), @@ -103,7 +110,7 @@ const struct iris_platform_data sc7280_data = { }; const struct iris_platform_data sm8250_data = { - .firmware_desc = &iris_vpu20_p4_gen1_desc, + .firmware_desc_gen1 = &iris_vpu20_p4_gen1_desc, .vpu_ops = &iris_vpu2_ops, .icc_tbl = iris_icc_info_vpu2, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index c249ff8275414..f7b636101682d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -95,7 +95,7 @@ static const struct tz_cp_config tz_cp_config_vpu3[] = { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data = { - .firmware_desc = &iris_vpu30_p4_s6_gen2_desc, + .firmware_desc_gen2 = &iris_vpu30_p4_s6_gen2_desc, .vpu_ops = &iris_vpu3_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -123,8 +123,84 @@ const struct iris_platform_data qcs8300_data = { .max_core_mbps = (((3840 * 2176) / 256) * 120), }; +static int sm8550_init_cb_devs(struct iris_core *core) +{ + const u32 f_id_np = 0; /* IRIS_NON_PIXEL_VCODEC */ + const u32 f_id_p = 1; /* IRIS_PIXEL */ + struct device *dev; + + dev = iris_create_cb_dev(core, "iris_non_pixel", &f_id_np); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + core->dev_np = dev; + core->dev_bs = core->dev_np; + + dev = iris_create_cb_dev(core, "iris_pixel", &f_id_p); + if (IS_ERR(dev)) + goto err_unreg_dev_np; + + core->dev_p = dev; + + return 0; + +err_unreg_dev_np: + platform_device_unregister(to_platform_device(core->dev_np)); + core->dev_np = NULL; + core->dev_bs = NULL; + + return PTR_ERR(dev); +} + +const struct iris_firmware_desc iris_vpu36_p4_s7_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu36_p4_s7.mbn", +}; + +static void sm8550_deinit_cb_devs(struct iris_core *core) +{ + if (core->dev_np) + platform_device_unregister(to_platform_device(core->dev_np)); + if (core->dev_p) + platform_device_unregister(to_platform_device(core->dev_p)); + + core->dev_np = NULL; + core->dev_bs = NULL; + core->dev_p = NULL; +} + +const struct iris_platform_data glymur_data = { + .firmware_desc_gen2 = &iris_vpu36_p4_s7_gen2_desc, + .vpu_ops = &iris_vpu36_ops, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = iris_glymur_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(iris_glymur_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = &iris_glymur_pmdomain_table, + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = iris_glymur_clk_table, + .clk_tbl_size = ARRAY_SIZE(iris_glymur_clk_table), + .opp_clk_tbl = iris_glymur_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xffe00000 - 1, + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = iris_glymur_tz_cp_config, + .tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config), + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4320) / 256) * 60, + .dual_core = true, +}; + const struct iris_platform_data sm8550_data = { - .firmware_desc = &iris_vpu30_p4_gen2_desc, + .firmware_desc_gen2 = &iris_vpu30_p4_gen2_desc, .vpu_ops = &iris_vpu3_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -159,7 +235,7 @@ const struct iris_platform_data sm8550_data = { * - controller_rst_tbl to sm8650_controller_reset_table */ const struct iris_platform_data sm8650_data = { - .firmware_desc = &iris_vpu33_p4_gen2_desc, + .firmware_desc_gen2 = &iris_vpu33_p4_gen2_desc, .vpu_ops = &iris_vpu33_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -190,7 +266,7 @@ const struct iris_platform_data sm8650_data = { }; const struct iris_platform_data sm8750_data = { - .firmware_desc = &iris_vpu35_p4_gen2_desc, + .firmware_desc_gen2 = &iris_vpu35_p4_gen2_desc, .vpu_ops = &iris_vpu35_ops, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), @@ -217,3 +293,33 @@ const struct iris_platform_data sm8750_data = { .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, }; + +const struct iris_platform_data x1p42100_data = { + .firmware_desc_gen2 = &iris_vpu30_p4_gen2_desc, + .vpu_ops = &iris_vpu3_purwa_ops, + .init_cb_devs = sm8550_init_cb_devs, + .deinit_cb_devs = sm8550_deinit_cb_devs, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = sm8550_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl = x1p42100_clk_table, + .clk_tbl_size = ARRAY_SIZE(x1p42100_clk_table), + .opp_clk_tbl = x1p42100_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = tz_cp_config_vpu3, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), + .num_vpp_pipe = 1, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((7680 * 4320) / 256) * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c index 02f8399e64759..1817315103ac3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c @@ -61,8 +61,7 @@ static struct platform_inst_caps iris_inst_cap_vpu4x = { }; const struct iris_platform_data kaanapali_data = { - .firmware_data = &iris_hfi_gen2_data, - .get_vpu_buffer_size = iris_vpu4x_buf_size, + .firmware_desc_gen2 = &iris_vpu40_p2_s7_gen2_desc, .vpu_ops = &iris_vpu4x_ops, .icc_tbl = iris_icc_info_vpu4x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu4x), diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index e847e74854ad4..1a820c1a95ed9 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -244,8 +244,6 @@ static int iris_probe(struct platform_device *pdev) return core->irq; core->iris_platform_data = of_device_get_match_data(core->dev); - core->iris_firmware_desc = core->iris_platform_data->firmware_desc; - core->iris_firmware_data = core->iris_firmware_desc->firmware_data; core->ubwc_cfg = qcom_ubwc_config_get_data(); if (IS_ERR(core->ubwc_cfg)) @@ -264,7 +262,9 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; - iris_session_init_caps(core); + ret = iris_init_cb_devs(core); + if (ret) + return ret; ret = v4l2_device_register(dev, &core->v4l2_dev); if (ret) From 3bef6f3ed3020f3aa071171d9796301eff393d54 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Thu, 14 May 2026 00:28:22 +0530 Subject: [PATCH 1231/1330] FROMLIST: media: iris: optimize COMV buffer allocation for VPU3x and VPU4x The existing iris_vpu_dec_comv_size() used VIDEO_MAX_FRAME (32) as num_comv count unconditionally when calculating the co-located motion vector (COMV) buffer size. This resulted in an oversized COMV buffer allocation throughout decode session, wasting memory regardless of actual number of buffers required. For VPU3x and VPU4x platforms, introduce iris_vpu3x_4x_dec_comv_size() to replace iris_vpu_dec_comv_size(). These derive num_comv dynamically, it uses inst->fw_min_count once the firmware has reported its buffer requirements, and fallback to output count during initialization before firmware has communicated its requirements. This aligns the COMV buffer size to the actual count needed rather than always allocating with fixed VIDEO_MAX_FRAME value. Additionally, during iris_vdec_inst_init(), fw_min_count was initialized to MIN_BUFFERS instead of 0. This masked the fallback logic and caused the COMV size calculation to use MIN_BUFFERS even before firmware had reported its actual requirements. Fix this by initializing fw_min_count to 0. During testing of 1080p AVC, it reduces the COMV buffer size from 32.89MB to 6.16MB per decode session, significantly reducing memory consumption. Link: https://lore.kernel.org/all/20260514-optimize_comv_buffer-v4-1-7da70b586aec@oss.qualcomm.com/ Reviewed-by: Vikash Garodia Signed-off-by: Vishnu Reddy (cherry picked from commit 859dbe78464cc6445f9c80bc667238f891943037) (cherry picked from commit eaef8c350ee33d378504ca608ec45384551d7b90) --- drivers/media/platform/qcom/iris/iris_platform_sm8550.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h index a9d9709c2e352..3c9dae995bb24 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -23,7 +23,6 @@ static struct platform_inst_caps platform_inst_cap_sm8550 = { .mb_cycles_vpp = 200, .mb_cycles_fw = 489583, .mb_cycles_fw_vpp = 66234, - .num_comv = 0, .max_frame_rate = MAXIMUM_FPS, .max_operating_rate = MAXIMUM_FPS, }; From b8d6310ae3d7c5081d4408bb19a1e8c20fc8b40d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:03 +0200 Subject: [PATCH 1232/1330] FROMGIT: soc: qcom: ubwc: add helper to get min_acc length MDSS and GPU drivers use different approaches to get min_acc length. Add helper function that can be used by all the drivers. The helper reflects our current best guess, it blindly copies the approach adopted by the MDSS drivers and it matches current values selected by the GPU driver. Link: https://lore.kernel.org/all/20260125-iris-ubwc-v4-1-1ff30644ac81@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue Acked-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov (cherry picked from commit 9bd42e2ad021ca48bf6083d738f497162ddf1e88) (cherry picked from commit 89123cfe1e7685dbf15724da5c94b3f8c46ced0b) --- include/linux/soc/qcom/ubwc.h | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index f5d0e23412611..5bdeca18d54df 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -84,19 +84,4 @@ static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data cfg->ubwc_dec_version == UBWC_3_0); } -static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg) -{ - return cfg->macrotile_mode; -} - -static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg) -{ - return cfg->ubwc_bank_spread; -} - -static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) -{ - return cfg->ubwc_swizzle; -} - #endif /* __QCOM_UBWC_H__ */ From f75565851b9aa47403397c996c7fdab0186b8a7c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 25 Jan 2026 13:30:04 +0200 Subject: [PATCH 1233/1330] FROMGIT: soc: qcom: ubwc: add helpers to get programmable values Currently the database stores macrotile_mode in the data. However it can be derived from the rest of the data: it should be used for UBWC encoding >= 3.0 except for several corner cases (SM8150 and SC8180X). The ubwc_bank_spread field seems to be based on the impreside data we had for the MDSS and DPU programming. In some cases UBWC engine inside the display controller doesn't need to program it, although bank spread is to be enabled. Bank swizzle is also currently stored as is, but it is almost standard (banks 1-3 for UBWC 1.0 and 2-3 for other versions), the only exception being Lemans (it uses only bank 3). Add helpers returning values from the config for now. They will be rewritten later, in a separate series, but having the helper now simplifies refacroring the code later. Link: https://lore.kernel.org/all/20260125-iris-ubwc-v4-2-1ff30644ac81@oss.qualcomm.com/ Tested-by: Wangao Wang Signed-off-by: Dmitry Baryshkov (cherry picked from commit bfc78e394647ac85d876a0ade6e6f10136e1827e) (cherry picked from commit 78e8f5c20980520c9ee5b4dd6c9cd07b3fef54a5) --- include/linux/soc/qcom/ubwc.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index 5bdeca18d54df..f5d0e23412611 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -84,4 +84,19 @@ static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data cfg->ubwc_dec_version == UBWC_3_0); } +static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg) +{ + return cfg->macrotile_mode; +} + +static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg) +{ + return cfg->ubwc_bank_spread; +} + +static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) +{ + return cfg->ubwc_swizzle; +} + #endif /* __QCOM_UBWC_H__ */ From aa9f8611abb7c9b2f41569ff8b1364dc8ee81cac Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 20 Mar 2026 04:33:15 +0200 Subject: [PATCH 1234/1330] arm64: dts: qcom: purwa: deduplicate thermal sensors with Hamoa Hamoa and Purwa have pretty close thermal zones definitions. The major difference is that several zones are absent (because of the lack of the CPU cluster) and several zones use tsens2 instead of tsens3. Instead of completely duplicating thermal zones for Purwa, reuse themal zones from Hamoa, patching them where required. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260320-purwa-drop-thermals-v1-1-2c9fe046cd02@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 2c098c2bae7177779c1801319d019a23e312d482) (cherry picked from commit ca8b12d317a95f47ee9a038b6f083603721addf4) --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 50 +-- arch/arm64/boot/dts/qcom/purwa.dtsi | 590 +++------------------------- 2 files changed, 72 insertions(+), 568 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 92acfe414fcac..91dfb9fcab105 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -10995,7 +10995,7 @@ }; }; - cpu2-0-top-thermal { + thermal_cpu2_0_top: cpu2-0-top-thermal { thermal-sensors = <&tsens2 1>; trips { @@ -11007,7 +11007,7 @@ }; }; - cpu2-0-btm-thermal { + thermal_cpu2_0_btm: cpu2-0-btm-thermal { thermal-sensors = <&tsens2 2>; trips { @@ -11019,7 +11019,7 @@ }; }; - cpu2-1-top-thermal { + thermal_cpu2_1_top: cpu2-1-top-thermal { thermal-sensors = <&tsens2 3>; trips { @@ -11031,7 +11031,7 @@ }; }; - cpu2-1-btm-thermal { + thermal_cpu2_1_btm: cpu2-1-btm-thermal { thermal-sensors = <&tsens2 4>; trips { @@ -11043,7 +11043,7 @@ }; }; - cpu2-2-top-thermal { + thermal_cpu2_2_top: cpu2-2-top-thermal { thermal-sensors = <&tsens2 5>; trips { @@ -11055,7 +11055,7 @@ }; }; - cpu2-2-btm-thermal { + thermal_cpu2_2_btm: cpu2-2-btm-thermal { thermal-sensors = <&tsens2 6>; trips { @@ -11067,7 +11067,7 @@ }; }; - cpu2-3-top-thermal { + thermal_cpu2_3_top: cpu2-3-top-thermal { thermal-sensors = <&tsens2 7>; trips { @@ -11079,7 +11079,7 @@ }; }; - cpu2-3-btm-thermal { + thermal_cpu2_3_btm: cpu2-3-btm-thermal { thermal-sensors = <&tsens2 8>; trips { @@ -11091,7 +11091,7 @@ }; }; - cpuss2-top-thermal { + thermal_cpuss2_top: cpuss2-top-thermal { thermal-sensors = <&tsens2 9>; trips { @@ -11103,7 +11103,7 @@ }; }; - cpuss2-btm-thermal { + thermal_cpuss2_btm: cpuss2-btm-thermal { thermal-sensors = <&tsens2 10>; trips { @@ -11115,7 +11115,7 @@ }; }; - aoss3-thermal { + thermal_aoss3: aoss3-thermal { thermal-sensors = <&tsens3 0>; trips { @@ -11133,7 +11133,7 @@ }; }; - nsp0-thermal { + thermal_nsp0: nsp0-thermal { thermal-sensors = <&tsens3 1>; trips { @@ -11151,7 +11151,7 @@ }; }; - nsp1-thermal { + thermal_nsp1: nsp1-thermal { thermal-sensors = <&tsens3 2>; trips { @@ -11169,7 +11169,7 @@ }; }; - nsp2-thermal { + thermal_nsp2: nsp2-thermal { thermal-sensors = <&tsens3 3>; trips { @@ -11187,7 +11187,7 @@ }; }; - nsp3-thermal { + thermal_nsp3: nsp3-thermal { thermal-sensors = <&tsens3 4>; trips { @@ -11205,7 +11205,7 @@ }; }; - gpuss-0-thermal { + thermal_gpuss_0: gpuss-0-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 5>; @@ -11232,7 +11232,7 @@ }; }; - gpuss-1-thermal { + thermal_gpuss_1: gpuss-1-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 6>; @@ -11259,7 +11259,7 @@ }; }; - gpuss-2-thermal { + thermal_gpuss_2: gpuss-2-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 7>; @@ -11286,7 +11286,7 @@ }; }; - gpuss-3-thermal { + thermal_gpuss_3: gpuss-3-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 8>; @@ -11313,7 +11313,7 @@ }; }; - gpuss-4-thermal { + thermal_gpuss_4: gpuss-4-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 9>; @@ -11340,7 +11340,7 @@ }; }; - gpuss-5-thermal { + thermal_gpuss_5: gpuss-5-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 10>; @@ -11367,7 +11367,7 @@ }; }; - gpuss-6-thermal { + thermal_gpuss_6: gpuss-6-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 11>; @@ -11394,7 +11394,7 @@ }; }; - gpuss-7-thermal { + thermal_gpuss_7: gpuss-7-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 12>; @@ -11421,7 +11421,7 @@ }; }; - camera0-thermal { + thermal_camera0: camera0-thermal { thermal-sensors = <&tsens3 13>; trips { @@ -11439,7 +11439,7 @@ }; }; - camera1-thermal { + thermal_camera1: camera1-thermal { thermal-sensors = <&tsens3 14>; trips { diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 10d2207ce81e9..2b6106c15aee2 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -25,7 +25,21 @@ /delete-node/ &gpu_speed_bin; /delete-node/ &iris_opp_table; /delete-node/ &pcie3_phy; -/delete-node/ &thermal_zones; +/delete-node/ &thermal_aoss3; +/delete-node/ &thermal_cpu2_0_btm; +/delete-node/ &thermal_cpu2_0_top; +/delete-node/ &thermal_cpu2_1_btm; +/delete-node/ &thermal_cpu2_1_top; +/delete-node/ &thermal_cpu2_2_btm; +/delete-node/ &thermal_cpu2_2_top; +/delete-node/ &thermal_cpu2_3_btm; +/delete-node/ &thermal_cpu2_3_top; +/delete-node/ &thermal_cpuss2_btm; +/delete-node/ &thermal_cpuss2_top; +/delete-node/ &thermal_gpuss_4; +/delete-node/ &thermal_gpuss_5; +/delete-node/ &thermal_gpuss_6; +/delete-node/ &thermal_gpuss_7; /delete-node/ &etm8; /delete-node/ &etm9; /delete-node/ &etm10; @@ -434,557 +448,47 @@ }; }; -/* While physically present, this controller is left unconfigured and unused */ -&tsens3 { - status = "disabled"; +&thermal_camera0 { + thermal-sensors = <&tsens2 9>; }; -/ { - thermal-zones { - aoss0-thermal { - thermal-sensors = <&tsens0 0>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-0-top-thermal { - thermal-sensors = <&tsens0 1>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-0-btm-thermal { - thermal-sensors = <&tsens0 2>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-1-top-thermal { - thermal-sensors = <&tsens0 3>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-1-btm-thermal { - thermal-sensors = <&tsens0 4>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-2-top-thermal { - thermal-sensors = <&tsens0 5>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-2-btm-thermal { - thermal-sensors = <&tsens0 6>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-3-top-thermal { - thermal-sensors = <&tsens0 7>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-3-btm-thermal { - thermal-sensors = <&tsens0 8>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuss0-top-thermal { - thermal-sensors = <&tsens0 9>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuss0-btm-thermal { - thermal-sensors = <&tsens0 10>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - mem-thermal { - thermal-sensors = <&tsens0 11>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - video-thermal { - thermal-sensors = <&tsens0 12>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss1-thermal { - thermal-sensors = <&tsens1 0>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-0-top-thermal { - thermal-sensors = <&tsens1 1>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-0-btm-thermal { - thermal-sensors = <&tsens1 2>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-1-top-thermal { - thermal-sensors = <&tsens1 3>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-1-btm-thermal { - thermal-sensors = <&tsens1 4>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-2-top-thermal { - thermal-sensors = <&tsens1 5>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-2-btm-thermal { - thermal-sensors = <&tsens1 6>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-3-top-thermal { - thermal-sensors = <&tsens1 7>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-3-btm-thermal { - thermal-sensors = <&tsens1 8>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuss1-top-thermal { - thermal-sensors = <&tsens1 9>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuss1-btm-thermal { - thermal-sensors = <&tsens1 10>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss2-thermal { - thermal-sensors = <&tsens2 0>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsp0-thermal { - thermal-sensors = <&tsens2 1>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsp1-thermal { - thermal-sensors = <&tsens2 2>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsp2-thermal { - thermal-sensors = <&tsens2 3>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsp3-thermal { - thermal-sensors = <&tsens2 4>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-0-thermal { - polling-delay-passive = <200>; - - thermal-sensors = <&tsens2 5>; - - cooling-maps { - map0 { - trip = <&gpuss0_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - gpuss0_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-1-thermal { - polling-delay-passive = <200>; - - thermal-sensors = <&tsens2 6>; - - cooling-maps { - map0 { - trip = <&gpuss1_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - gpuss1_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-2-thermal { - polling-delay-passive = <200>; +&thermal_camera1 { + thermal-sensors = <&tsens2 10>; +}; - thermal-sensors = <&tsens2 7>; +&thermal_gpuss_0 { + thermal-sensors = <&tsens2 5>; +}; - cooling-maps { - map0 { - trip = <&gpuss2_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; +&thermal_gpuss_1 { + thermal-sensors = <&tsens2 6>; +}; - trips { - gpuss2_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; +&thermal_gpuss_2 { + thermal-sensors = <&tsens2 7>; +}; - gpuss-3-thermal { - polling-delay-passive = <200>; +&thermal_gpuss_3 { + thermal-sensors = <&tsens2 8>; +}; - thermal-sensors = <&tsens2 8>; +&thermal_nsp0 { + thermal-sensors = <&tsens2 1>; +}; - cooling-maps { - map0 { - trip = <&gpuss3_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; +&thermal_nsp1 { + thermal-sensors = <&tsens2 2>; +}; - trips { - gpuss3_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; +&thermal_nsp2 { + thermal-sensors = <&tsens2 3>; +}; - camera0-thermal { - thermal-sensors = <&tsens2 9>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; +&thermal_nsp3 { + thermal-sensors = <&tsens2 4>; +}; - camera1-thermal { - thermal-sensors = <&tsens2 10>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; +/* While physically present, this controller is left unconfigured and unused */ +&tsens3 { + status = "disabled"; }; From 7e676bd6b6ea72caecfcf156d91d5e3784937d63 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Thu, 2 Jul 2026 15:58:25 +0800 Subject: [PATCH 1235/1330] Revert "FROMLIST: usb: dwc3: qcom: notify EUD driver of role changes" This reverts commit 90fe4a0a54e7faed018f5a3111b81d3acdefb1c0. Signed-off-by: Yushan Li (cherry picked from commit 1fcf1033814e530a54cc06a9f8f6a7c6308e02d5) --- drivers/usb/dwc3/Kconfig | 1 - drivers/usb/dwc3/dwc3-qcom.c | 10 ---------- 2 files changed, 11 deletions(-) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 1a2d7c883b50d..240b15bc52cbd 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -132,7 +132,6 @@ config USB_DWC3_QCOM depends on ARCH_QCOM || COMPILE_TEST depends on EXTCON || !EXTCON depends on OF - depends on USB_QCOM_EUD || !USB_QCOM_EUD default USB_DWC3 help Some Qualcomm SoCs use DesignWare Core IP for USB2/3 diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 3479792c2acd7..f578ac46101a1 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -20,7 +19,6 @@ #include #include #include -#include #include "core.h" #include "glue.h" @@ -586,7 +584,6 @@ static int dwc3_qcom_setup_irq(struct dwc3_qcom *qcom, struct platform_device *p static void dwc3_qcom_set_role_notifier(struct dwc3 *dwc, enum usb_role next_role) { struct dwc3_qcom *qcom = to_dwc3_qcom(dwc); - struct device_node *eud_node; if (qcom->current_role == next_role) return; @@ -596,13 +593,6 @@ static void dwc3_qcom_set_role_notifier(struct dwc3 *dwc, enum usb_role next_rol return; } - /* Notify EUD of role change */ - eud_node = of_graph_get_remote_node(qcom->dev->of_node, 0, -1); - if (eud_node) { - qcom_eud_usb_role_notify(eud_node, dwc->usb2_generic_phy[0], next_role); - of_node_put(eud_node); - } - if (qcom->current_role == USB_ROLE_DEVICE) dwc3_qcom_vbus_override_enable(qcom, false); else if (qcom->current_role != USB_ROLE_DEVICE) From 54d9f0cf94d6db0a808ba54910bc7c7cd5ac9266 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Thu, 2 Jul 2026 15:58:40 +0800 Subject: [PATCH 1236/1330] Revert "FROMLIST: coresight: cti: expose banked sysfs registers for Qualcomm extended CTI" This reverts commit 23ddfcaf700a7816870444fb5da8df8dee5affcf. Signed-off-by: Yushan Li (cherry picked from commit e8cf4fe260847afd058dd51c97b9f05e597831a0) --- .../hwtracing/coresight/coresight-cti-sysfs.c | 96 +++---------------- 1 file changed, 13 insertions(+), 83 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 75b8f16ee0399..281e0ee70da1e 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -610,94 +610,24 @@ static struct attribute *coresight_cti_regs_attrs[] = { &dev_attr_appset.attr, &dev_attr_appclear.attr, &dev_attr_apppulse.attr, - coresight_cti_reg(triginstatus, CTITRIGINSTATUS), - coresight_cti_reg(triginstatus1, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 1)), - coresight_cti_reg(triginstatus2, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 2)), - coresight_cti_reg(triginstatus3, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 3)), - coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), - coresight_cti_reg(trigoutstatus1, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 1)), - coresight_cti_reg(trigoutstatus2, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 2)), - coresight_cti_reg(trigoutstatus3, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 3)), - coresight_cti_reg(chinstatus, CTICHINSTATUS), - coresight_cti_reg(choutstatus, CTICHOUTSTATUS), + coresight_cti_reg(triginstatus, INDEX_CTITRIGINSTATUS), + coresight_cti_reg(trigoutstatus, INDEX_CTITRIGOUTSTATUS), + coresight_cti_reg(chinstatus, INDEX_CTICHINSTATUS), + coresight_cti_reg(choutstatus, INDEX_CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS - coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), - coresight_cti_reg(ittrigin, ITTRIGIN), - coresight_cti_reg(ittrigin1, CTI_REG_SET_NR_CONST(ITTRIGIN, 1)), - coresight_cti_reg(ittrigin2, CTI_REG_SET_NR_CONST(ITTRIGIN, 2)), - coresight_cti_reg(ittrigin3, CTI_REG_SET_NR_CONST(ITTRIGIN, 3)), - coresight_cti_reg(itchin, ITCHIN), - coresight_cti_reg_rw(ittrigout, ITTRIGOUT), - coresight_cti_reg_rw(ittrigout1, CTI_REG_SET_NR_CONST(ITTRIGOUT, 1)), - coresight_cti_reg_rw(ittrigout2, CTI_REG_SET_NR_CONST(ITTRIGOUT, 2)), - coresight_cti_reg_rw(ittrigout3, CTI_REG_SET_NR_CONST(ITTRIGOUT, 3)), - coresight_cti_reg_rw(itchout, ITCHOUT), - coresight_cti_reg(itchoutack, ITCHOUTACK), - coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), - coresight_cti_reg(ittrigoutack1, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 1)), - coresight_cti_reg(ittrigoutack2, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 2)), - coresight_cti_reg(ittrigoutack3, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 3)), - coresight_cti_reg_wo(ittriginack, ITTRIGINACK), - coresight_cti_reg_wo(ittriginack1, CTI_REG_SET_NR_CONST(ITTRIGINACK, 1)), - coresight_cti_reg_wo(ittriginack2, CTI_REG_SET_NR_CONST(ITTRIGINACK, 2)), - coresight_cti_reg_wo(ittriginack3, CTI_REG_SET_NR_CONST(ITTRIGINACK, 3)), - coresight_cti_reg_wo(itchinack, ITCHINACK), + coresight_cti_reg_rw(itctrl, INDEX_ITCTRL), + coresight_cti_reg(ittrigin, INDEX_ITTRIGIN), + coresight_cti_reg(itchin, INDEX_ITCHIN), + coresight_cti_reg_rw(ittrigout, INDEX_ITTRIGOUT), + coresight_cti_reg_rw(itchout, INDEX_ITCHOUT), + coresight_cti_reg(itchoutack, INDEX_ITCHOUTACK), + coresight_cti_reg(ittrigoutack, INDEX_ITTRIGOUTACK), + coresight_cti_reg_wo(ittriginack, INDEX_ITTRIGINACK), + coresight_cti_reg_wo(itchinack, INDEX_ITCHINACK), #endif NULL, }; -static umode_t coresight_cti_regs_is_visible(struct kobject *kobj, - struct attribute *attr, int idx) -{ - struct device *dev = kobj_to_dev(kobj); - struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); - static const char * const qcom_suffix_registers[] = { - "triginstatus", - "trigoutstatus", -#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS - "ittrigin", - "ittrigout", - "ittriginack", - "ittrigoutack", -#endif - }; - int i, nr, max_bank; - size_t len; - - if (attr == &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) - return 0; - - /* - * Banked regs are exposed as (nr = 1..3). - * - Hide them on standard CTIs. - * - On QCOM CTIs, hide suffixes beyond the number of banks implied - * by nr_trig_max (32 triggers per bank). - */ - for (i = 0; i < ARRAY_SIZE(qcom_suffix_registers); i++) { - len = strlen(qcom_suffix_registers[i]); - - if (strncmp(attr->name, qcom_suffix_registers[i], len)) - continue; - - if (kstrtoint(attr->name + len, 10, &nr)) - continue; - - if (!drvdata->is_qcom_cti) - return 0; - - if (nr < 1 || nr > 3) - return 0; - - max_bank = DIV_ROUND_UP(drvdata->config.nr_trig_max, 32) - 1; - if (nr > max_bank) - return 0; - - break; - } - - return attr->mode; -} - /* CTI channel x-trigger programming */ static int cti_trig_op_parse(struct device *dev, enum cti_chan_op op, From 6fee2991f863641307302042c11b61b90d6a256a Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Thu, 2 Jul 2026 15:58:52 +0800 Subject: [PATCH 1237/1330] Revert "FROMLIST: coresight: cti: add Qualcomm extended CTI identification and quirks" This reverts commit f4205fdaa351e832b6960bc4db88c5a5b8904f0e. Signed-off-by: Yushan Li (cherry picked from commit a052a54d7818e815ce0e865113adc84d5d6cbaab) --- .../hwtracing/coresight/coresight-cti-core.c | 71 +++++++++++------ drivers/hwtracing/coresight/coresight-cti.h | 36 ++++++++- drivers/hwtracing/coresight/qcom-cti.h | 76 +++++-------------- 3 files changed, 103 insertions(+), 80 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index d6cdea81682e7..dc0bb31916abf 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -23,6 +23,54 @@ #include "coresight-cti.h" #include "qcom-cti.h" +static const u32 cti_normal_offset[] = { + [INDEX_CTIINTACK] = CTIINTACK, + [INDEX_CTIAPPSET] = CTIAPPSET, + [INDEX_CTIAPPCLEAR] = CTIAPPCLEAR, + [INDEX_CTIAPPPULSE] = CTIAPPPULSE, + [INDEX_CTIINEN] = CTIINEN(0), + [INDEX_CTIOUTEN] = CTIOUTEN(0), + [INDEX_CTITRIGINSTATUS] = CTITRIGINSTATUS, + [INDEX_CTITRIGOUTSTATUS] = CTITRIGOUTSTATUS, + [INDEX_CTICHINSTATUS] = CTICHINSTATUS, + [INDEX_CTICHOUTSTATUS] = CTICHOUTSTATUS, + [INDEX_CTIGATE] = CTIGATE, + [INDEX_ASICCTL] = ASICCTL, + [INDEX_ITCHINACK] = ITCHINACK, + [INDEX_ITTRIGINACK] = ITTRIGINACK, + [INDEX_ITCHOUT] = ITCHOUT, + [INDEX_ITTRIGOUT] = ITTRIGOUT, + [INDEX_ITCHOUTACK] = ITCHOUTACK, + [INDEX_ITTRIGOUTACK] = ITTRIGOUTACK, + [INDEX_ITCHIN] = ITCHIN, + [INDEX_ITTRIGIN] = ITTRIGIN, + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, +}; + +static const u32 cti_extended_offset[] = { + [INDEX_CTIINTACK] = QCOM_CTIINTACK, + [INDEX_CTIAPPSET] = QCOM_CTIAPPSET, + [INDEX_CTIAPPCLEAR] = QCOM_CTIAPPCLEAR, + [INDEX_CTIAPPPULSE] = QCOM_CTIAPPPULSE, + [INDEX_CTIINEN] = QCOM_CTIINEN, + [INDEX_CTIOUTEN] = QCOM_CTIOUTEN, + [INDEX_CTITRIGINSTATUS] = QCOM_CTITRIGINSTATUS, + [INDEX_CTITRIGOUTSTATUS] = QCOM_CTITRIGOUTSTATUS, + [INDEX_CTICHINSTATUS] = QCOM_CTICHINSTATUS, + [INDEX_CTICHOUTSTATUS] = QCOM_CTICHOUTSTATUS, + [INDEX_CTIGATE] = QCOM_CTIGATE, + [INDEX_ASICCTL] = QCOM_ASICCTL, + [INDEX_ITCHINACK] = QCOM_ITCHINACK, + [INDEX_ITTRIGINACK] = QCOM_ITTRIGINACK, + [INDEX_ITCHOUT] = QCOM_ITCHOUT, + [INDEX_ITTRIGOUT] = QCOM_ITTRIGOUT, + [INDEX_ITCHOUTACK] = QCOM_ITCHOUTACK, + [INDEX_ITTRIGOUTACK] = QCOM_ITTRIGOUTACK, + [INDEX_ITCHIN] = QCOM_ITCHIN, + [INDEX_ITTRIGIN] = QCOM_ITTRIGIN, + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, +}; + /* * CTI devices can be associated with a PE, or be connected to CoreSight * hardware. We have a list of all CTIs irrespective of CPU bound or @@ -48,10 +96,6 @@ static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg) u32 offset = CTI_REG_CLR_NR(reg); u32 nr = CTI_REG_GET_NR(reg); - /* convert to qcom specific offset */ - if (unlikely(drvdata->is_qcom_cti)) - offset = cti_qcom_reg_off(offset); - return drvdata->base + offset + sizeof(u32) * nr; } @@ -928,22 +972,6 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) raw_spin_lock_init(&drvdata->spinlock); - devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); - if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { - drvdata->is_qcom_cti = true; - /* - * QCOM CTI does not implement Claimtag functionality as - * per CoreSight specification, but its CLAIMSET register - * is incorrectly initialized to 0xF. This can mislead - * tools or drivers into thinking the component is claimed. - * - * Reset CLAIMSET to 0 to reflect that no claims are active. - */ - CS_UNLOCK(drvdata->base); - writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); - CS_LOCK(drvdata->base); - } - /* initialise CTI driver config values */ ret = cti_set_default_config(dev, drvdata); if (ret) @@ -1027,8 +1055,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, - "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); + dev_info(&drvdata->csdev->dev, "CTI initialized; subtype=%d\n", drvdata->subtype); return 0; pm_release: diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index b3e9b1b692305..6fb9681c59404 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -55,12 +55,42 @@ struct fwnode_handle; /* * CTI CSSoc 600 has a max of 32 trigger signals per direction. * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. - * QCOM CTI supports up to 128 trigger signals per direction. * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ #define CTIINOUTEN_MAX 128 +/* Qcom CTI supports up to 128 triggers*/ +enum cti_subtype { + ARM_STD_CTI, + QCOM_CTI, +}; + +/* These registers are remapped in Qcom CTI*/ +enum cti_offset_index { + INDEX_CTIINTACK, + INDEX_CTIAPPSET, + INDEX_CTIAPPCLEAR, + INDEX_CTIAPPPULSE, + INDEX_CTIINEN, + INDEX_CTIOUTEN, + INDEX_CTITRIGINSTATUS, + INDEX_CTITRIGOUTSTATUS, + INDEX_CTICHINSTATUS, + INDEX_CTICHOUTSTATUS, + INDEX_CTIGATE, + INDEX_ASICCTL, + INDEX_ITCHINACK, + INDEX_ITTRIGINACK, + INDEX_ITCHOUT, + INDEX_ITTRIGOUT, + INDEX_ITCHOUTACK, + INDEX_ITTRIGOUTACK, + INDEX_ITCHIN, + INDEX_ITTRIGIN, + INDEX_ITCTRL, +}; + /* * Encode CTI register offset and register index in one u32: * - bits[0:11] : base register offset (0x000 to 0xFFF) @@ -196,7 +226,9 @@ struct cti_drvdata { raw_spinlock_t spinlock; struct cti_config config; struct list_head node; - bool is_qcom_cti; + void (*csdev_release)(struct device *dev); + enum cti_subtype subtype; + const u32 *offsets; }; /* diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h index fd1bf07d7cb4a..3c46317dd81f5 100644 --- a/drivers/hwtracing/coresight/qcom-cti.h +++ b/drivers/hwtracing/coresight/qcom-cti.h @@ -3,63 +3,27 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ -#ifndef _CORESIGHT_QCOM_CTI_H -#define _CORESIGHT_QCOM_CTI_H - -#include "coresight-cti.h" - #define ARCHITECT_QCOM 0x477 /* CTI programming registers */ -#define QCOM_CTIINTACK 0x020 -#define QCOM_CTIAPPSET 0x004 -#define QCOM_CTIAPPCLEAR 0x008 -#define QCOM_CTIAPPPULSE 0x00C -#define QCOM_CTIINEN 0x400 -#define QCOM_CTIOUTEN 0x800 -#define QCOM_CTITRIGINSTATUS 0x040 -#define QCOM_CTITRIGOUTSTATUS 0x060 -#define QCOM_CTICHINSTATUS 0x080 -#define QCOM_CTICHOUTSTATUS 0x084 -#define QCOM_CTIGATE 0x088 -#define QCOM_ASICCTL 0x08C +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08c /* Integration test registers */ -#define QCOM_ITCHINACK 0xE70 -#define QCOM_ITTRIGINACK 0xE80 -#define QCOM_ITCHOUT 0xE74 -#define QCOM_ITTRIGOUT 0xEA0 -#define QCOM_ITCHOUTACK 0xE78 -#define QCOM_ITTRIGOUTACK 0xEC0 -#define QCOM_ITCHIN 0xE7C -#define QCOM_ITTRIGIN 0xEE0 - -static noinline u32 cti_qcom_reg_off(u32 offset) -{ - switch (offset) { - case CTIINTACK: return QCOM_CTIINTACK; - case CTIAPPSET: return QCOM_CTIAPPSET; - case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; - case CTIAPPPULSE: return QCOM_CTIAPPPULSE; - case CTIINEN: return QCOM_CTIINEN; - case CTIOUTEN: return QCOM_CTIOUTEN; - case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; - case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; - case CTICHINSTATUS: return QCOM_CTICHINSTATUS; - case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; - case CTIGATE: return QCOM_CTIGATE; - case ASICCTL: return QCOM_ASICCTL; - case ITCHINACK: return QCOM_ITCHINACK; - case ITTRIGINACK: return QCOM_ITTRIGINACK; - case ITCHOUT: return QCOM_ITCHOUT; - case ITTRIGOUT: return QCOM_ITTRIGOUT; - case ITCHOUTACK: return QCOM_ITCHOUTACK; - case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK; - case ITCHIN: return QCOM_ITCHIN; - case ITTRIGIN: return QCOM_ITTRIGIN; - - default: - return offset; - } -} - -#endif /* _CORESIGHT_QCOM_CTI_H */ +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 From 2fe4511219e945f4bead5c235486f6d47d16f09c Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Thu, 2 Jul 2026 15:59:08 +0800 Subject: [PATCH 1238/1330] Revert "FROMLIST: coresight: cti: encode trigger register index in register offsets" This reverts commit 0c48303577ec112b3f5e0721663a05ba67fefd0d. Signed-off-by: Yushan Li (cherry picked from commit 5b0e30da9c0160620d109769c838ef822c4e3b26) --- .../hwtracing/coresight/coresight-cti-core.c | 55 ++++++++++--------- .../hwtracing/coresight/coresight-cti-sysfs.c | 12 ++-- drivers/hwtracing/coresight/coresight-cti.h | 16 +----- 3 files changed, 36 insertions(+), 47 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index dc0bb31916abf..51b3644e97c4a 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -91,13 +91,20 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) -static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg) -{ - u32 offset = CTI_REG_CLR_NR(reg); - u32 nr = CTI_REG_GET_NR(reg); +/* power management handling */ +static int nr_cti_cpu; - return drvdata->base + offset + sizeof(u32) * nr; -} +/* quick lookup list for CPU bound CTIs when power handling */ +static struct cti_drvdata *cti_cpu_drvdata[NR_CPUS]; + +/* + * CTI naming. CTI bound to cores will have the name cti_cpu where + * N is the CPU ID. System CTIs will have the name cti_sys where I + * is an index allocated by order of discovery. + * + * CTI device name list - for CTI not bound to cores. + */ +DEFINE_CORESIGHT_DEVLIST(cti_sys_devs, "cti_sys"); /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) @@ -113,16 +120,15 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) /* write the CTI trigger registers */ for (i = 0; i < config->nr_trig_max; i++) { writel_relaxed(config->ctiinen[i], - cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIINEN, i))); + drvdata->base + cti_offset(drvdata, INDEX_CTIINEN, i)); writel_relaxed(config->ctiouten[i], - cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIOUTEN, i))); + drvdata->base + cti_offset(drvdata, INDEX_CTIOUTEN, i)); } /* other regs */ - writel_relaxed(config->ctigate, cti_reg_addr(drvdata, CTIGATE)); - if (config->asicctl_impl) - writel_relaxed(config->asicctl, cti_reg_addr(drvdata, ASICCTL)); - writel_relaxed(config->ctiappset, cti_reg_addr(drvdata, CTIAPPSET)); + writel_relaxed(config->ctigate, drvdata->base + cti_offset(drvdata, INDEX_CTIGATE, 0)); + writel_relaxed(config->asicctl, drvdata->base + cti_offset(drvdata, INDEX_ASICCTL, 0)); + writel_relaxed(config->ctiappset, drvdata->base + cti_offset(drvdata, INDEX_CTIAPPSET, 0)); /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -224,21 +230,16 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) raw_spin_unlock(&drvdata->spinlock); return ret; -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset) -{ - int val; - - CS_UNLOCK(drvdata->base); - val = readl_relaxed(cti_reg_addr(drvdata, offset)); - CS_LOCK(drvdata->base); - - return val; + /* not disabled this call */ +cti_not_disabled: + raw_spin_unlock(&drvdata->spinlock); + return ret; } void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) { CS_UNLOCK(drvdata->base); - writel_relaxed(value, cti_reg_addr(drvdata, offset)); + writel_relaxed(value, drvdata->base + offset); CS_LOCK(drvdata->base); } @@ -446,7 +447,8 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, /* update the local register values */ chan_bitmask = BIT(channel_idx); - reg_offset = (direction == CTI_TRIG_IN ? CTIINEN : CTIOUTEN); + reg_offset = (direction == CTI_TRIG_IN ? cti_offset(drvdata, INDEX_CTIINEN, trigger_idx) : + cti_offset(drvdata, INDEX_CTIOUTEN, trigger_idx)); raw_spin_lock(&drvdata->spinlock); @@ -465,10 +467,9 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, config->ctiouten[trigger_idx] = reg_value; /* write through if enabled */ - if (cti_is_active(config)) - cti_write_single_reg(drvdata, - CTI_REG_SET_NR(reg_offset, trigger_idx), - reg_value); + if (cti_active(config)) + cti_write_single_reg(drvdata, reg_offset, reg_value); + raw_spin_unlock(&drvdata->spinlock); return 0; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 281e0ee70da1e..12a4953829994 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -485,9 +485,9 @@ static ssize_t inen_store(struct device *dev, config->ctiinen[index] = val; /* write through if enabled */ - if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIINEN, index), val); - + if (cti_active(config)) + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIINEN, index), val); + raw_spin_unlock(&drvdata->spinlock); return size; } static DEVICE_ATTR_RW(inen); @@ -524,9 +524,9 @@ static ssize_t outen_store(struct device *dev, config->ctiouten[index] = val; /* write through if enabled */ - if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIOUTEN, index), val); - + if (cti_active(config)) + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIOUTEN, index), val); + raw_spin_unlock(&drvdata->spinlock); return size; } static DEVICE_ATTR_RW(outen); diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 6fb9681c59404..fdd6d8892a95a 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -7,7 +7,6 @@ #ifndef _CORESIGHT_CORESIGHT_CTI_H #define _CORESIGHT_CORESIGHT_CTI_H -#include #include #include #include @@ -31,8 +30,8 @@ struct fwnode_handle; #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01C -#define CTIINEN 0x020 -#define CTIOUTEN 0x0A0 +#define CTIINEN(n) (0x020 + (4 * n)) +#define CTIOUTEN(n) (0x0A0 + (4 * n)) #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 @@ -91,17 +90,6 @@ enum cti_offset_index { INDEX_ITCTRL, }; -/* - * Encode CTI register offset and register index in one u32: - * - bits[0:11] : base register offset (0x000 to 0xFFF) - * - bits[24:31] : register index (nr) - */ -#define CTI_REG_NR_MASK GENMASK(31, 24) -#define CTI_REG_GET_NR(reg) FIELD_GET(CTI_REG_NR_MASK, (reg)) -#define CTI_REG_SET_NR_CONST(reg, nr) ((reg) | FIELD_PREP_CONST(CTI_REG_NR_MASK, (nr))) -#define CTI_REG_SET_NR(reg, nr) ((reg) | FIELD_PREP(CTI_REG_NR_MASK, (nr))) -#define CTI_REG_CLR_NR(reg) ((reg) & (~CTI_REG_NR_MASK)) - /** * Group of related trigger signals * From 5ee7372c2e5f69ee0af308b40711aa8275896090 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Thu, 2 Jul 2026 15:59:21 +0800 Subject: [PATCH 1239/1330] Revert "FROMLIST: coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs read operations" This reverts commit 62faa9bb7327ad9652ba576cf1b1eabf9545d7ce. Signed-off-by: Yushan Li (cherry picked from commit f7e3d2e515857e28b505215dad4fe11bb51caad3) --- .../hwtracing/coresight/coresight-tmc-core.c | 168 ++++++++++++------ 1 file changed, 118 insertions(+), 50 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 25b06f3e08eb1..5e873bdcf7bb3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -262,10 +262,11 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; int ret = 0; - if (drvdata->sysfs_ops) - ret = drvdata->sysfs_ops->read_prepare(drvdata); - else - ret = -EINVAL; + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) { + ret = byte_cntr_sysfs_ops->read_prepare(drvdata); + goto out; + } if (drvdata->sysfs_ops) ret = drvdata->sysfs_ops->read_prepare(drvdata); @@ -284,10 +285,11 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvdata) const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; int ret = 0; - if (drvdata->sysfs_ops) - ret = drvdata->sysfs_ops->read_unprepare(drvdata); - else - ret = -EINVAL; + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) { + ret = byte_cntr_sysfs_ops->read_unprepare(drvdata); + goto out; + } if (drvdata->sysfs_ops) ret = drvdata->sysfs_ops->read_unprepare(drvdata); @@ -320,6 +322,12 @@ static int tmc_open(struct inode *inode, struct file *file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp) { + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; + + byte_cntr_sysfs_ops = tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) + return byte_cntr_sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); } @@ -915,40 +923,14 @@ static const struct tmc_sysfs_ops etr_sysfs_ops = { .get_trace_data = tmc_etr_get_sysfs_trace, }; -static int __tmc_probe(struct device *dev, struct resource *res) +static int tmc_add_coresight_dev(struct device *dev) { - int cpu, ret = 0; - void __iomem *base; - struct coresight_platform_data *pdata = NULL; - struct tmc_drvdata *drvdata; - - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); - if (ret) - return ret; - - ret = -ENOMEM; - - /* Validity for the resource is already checked by the AMBA core */ - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) { - ret = PTR_ERR(base); - goto out; - } - - drvdata->base = base; - - raw_spin_lock_init(&drvdata->spinlock); - /* This device is not associated with a session */ - drvdata->pid = -1; - drvdata->etr_mode = ETR_MODE_AUTO; - tmc_get_reserved_region(dev); + struct tmc_drvdata *drvdata = dev_get_drvdata(dev); + struct coresight_desc desc = { 0 }; + struct coresight_dev_list *dev_list = NULL; + int ret = 0; + desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); desc.dev = dev; switch (drvdata->config_type) { @@ -957,7 +939,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops = &tmc_etb_cs_ops; - dev_list = "tmc_etb"; + dev_list = &etb_devs; drvdata->sysfs_ops = &etb_sysfs_ops; break; case TMC_CONFIG_TYPE_ETR: @@ -965,14 +947,14 @@ static int __tmc_probe(struct device *dev, struct resource *res) desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; desc.ops = &tmc_etr_cs_ops; - ret = tmc_etr_setup_caps(dev, devid, &desc.access); + ret = tmc_etr_setup_caps(dev, drvdata->devid, &desc.access); if (ret) - goto out; + return ret; idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); - dev_list = "tmc_etr"; - drvdata->sysfs_ops = &etr_sysfs_ops; + dev_list = &etr_devs; INIT_LIST_HEAD(&drvdata->etr_buf_list); + drvdata->sysfs_ops = &etr_sysfs_ops; break; case TMC_CONFIG_TYPE_ETF: desc.groups = coresight_etf_groups; @@ -980,21 +962,107 @@ static int __tmc_probe(struct device *dev, struct resource *res) desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; desc.ops = &tmc_etf_cs_ops; - dev_list = "tmc_etf"; + dev_list = &etf_devs; drvdata->sysfs_ops = &etb_sysfs_ops; break; default: pr_err("%s: Unsupported TMC config\n", desc.name); - ret = -EINVAL; - goto out; + return -EINVAL; } desc.name = coresight_alloc_device_name(dev_list, dev); - if (!desc.name) { - ret = -ENOMEM; + if (!desc.name) + return -ENOMEM; + + drvdata->desc_name = desc.name; + + desc.pdata = dev->platform_data; + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = desc.name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &tmc_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) + coresight_unregister(drvdata->csdev); + + return ret; +} + +static void tmc_clear_self_claim_tag(struct tmc_drvdata *drvdata) +{ + struct csdev_access access = CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static void tmc_init_hw_config(struct tmc_drvdata *drvdata) +{ + u32 devid; + + devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); + drvdata->config_type = BMVAL(devid, 6, 7); + drvdata->memwidth = tmc_get_memwidth(devid); + drvdata->devid = devid; + drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; + tmc_clear_self_claim_tag(drvdata); +} + +static void tmc_init_on_cpu(void *info) +{ + struct tmc_drvdata *drvdata = info; + + tmc_init_hw_config(drvdata); +} + +static struct cpumask *tmc_get_supported_cpus(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd = pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + +static int __tmc_probe(struct device *dev, struct resource *res) +{ + int cpu, ret = 0; + void __iomem *base; + struct coresight_platform_data *pdata = NULL; + struct tmc_drvdata *drvdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); + if (ret) + return ret; + + ret = -ENOMEM; + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); goto out; } + drvdata->base = base; + + raw_spin_lock_init(&drvdata->spinlock); + /* This device is not associated with a session */ + drvdata->pid = -1; + drvdata->etr_mode = ETR_MODE_AUTO; + tmc_get_reserved_region(dev); + pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) { ret = PTR_ERR(pdata); From 06d3a46129430776bf16aabe66ab4fb37dfeabb0 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Fri, 3 Jul 2026 20:17:29 +0800 Subject: [PATCH 1240/1330] Synchronize with Qualcomm config Signed-off-by: Yushan Li (cherry picked from commit 13e586d16c32e24a66a63ed62b8b0288f5d6b668) --- debian.qcom/config/annotations | 93 +++++++++++++++++++++++++++------- 1 file changed, 75 insertions(+), 18 deletions(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 2faca6451afe3..bab578d1214a2 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -18,14 +18,8 @@ CONFIG_ARCH_ROCKCHIP note<'LP: #1825222'> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': 'y'}> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT note<'LP: #2102032'> -CONFIG_CLK_X1E80100_CAMCC policy<{'arm64': 'y'}> -CONFIG_CLK_X1E80100_CAMCC note<'builtin: apps_smmu camera TBU GDSC must register before built-in clients probe to avoid TLB-sync deadlock'> - -CONFIG_CLK_X1E80100_DISPCC policy<{'arm64': 'y'}> -CONFIG_CLK_X1E80100_DISPCC note<'builtin: apps_smmu display TBU GDSC must register before built-in clients probe to avoid TLB-sync deadlock'> - -CONFIG_CLK_X1E80100_GPUCC policy<{'arm64': 'y'}> -CONFIG_CLK_X1E80100_GPUCC note<'builtin: GPU TBU GDSC must register before built-in clients probe to avoid TLB-sync deadlock'> +CONFIG_CHR_DEV_SG policy<{'arm64': 'y', 'arm64-qcom': 'm'}> +CONFIG_CHR_DEV_SG note<'TODO: update note'> CONFIG_DRM_AMDGPU_CIK policy<{'arm64': '-'}> CONFIG_DRM_AMDGPU_CIK note<'for zesty'> @@ -33,6 +27,9 @@ CONFIG_DRM_AMDGPU_CIK note<'for zesty'> CONFIG_DRM_MGAG200 policy<{'arm64': 'n'}> CONFIG_DRM_MGAG200 note<'LP: #1693337'> +CONFIG_DRM_NOVA policy<{'arm64': 'n', 'arm64-qcom': '-'}> +CONFIG_DRM_NOVA note + CONFIG_EFI_ZBOOT policy<{'arm64': 'n'}> CONFIG_EFI_ZBOOT note<'we use arch/arm64/boot/Image.gz'> @@ -90,6 +87,9 @@ CONFIG_RCU_NOCB_CPU_DEFAULT_ALL note<'TODO: update note'> CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'arm64': 'y'}> CONFIG_REGULATOR_FIXED_VOLTAGE note<'boot essential on arm'> +CONFIG_RUST policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUST note + CONFIG_SERIAL_SH_SCI policy<{'arm64': '-'}> CONFIG_SERIAL_SH_SCI note<'LP: #2022361'> @@ -123,8 +123,10 @@ CONFIG_TOUCHSCREEN_APPLE_Z2 note<'TODO: update note'> # ---- Annotations without notes ---- +CONFIG_842_COMPRESS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_842_DECOMPRESS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_AC97_BUS policy<{'arm64': 'y'}> -CONFIG_ACPI_AEST policy<{'arm64': 'n'}> +CONFIG_ACPI_AEST policy<{'arm64-qcom': 'n'}> CONFIG_ADI_AXI_ADC policy<{'arm64': '-'}> CONFIG_ADI_AXI_DAC policy<{'arm64': '-'}> CONFIG_AEST policy<{'arm64': 'y'}> @@ -138,8 +140,10 @@ CONFIG_AHCI_XGENE policy<{'arm64': '-'}> CONFIG_AIROHA_CPU_PM_DOMAIN policy<{'arm64': '-'}> CONFIG_AIROHA_THERMAL policy<{'arm64': '-'}> CONFIG_AIROHA_WATCHDOG policy<{'arm64': '-'}> +CONFIG_AMCC_QT2025_PHY policy<{'arm64': 'm', 'arm64-qcom': '-'}> CONFIG_AMD_ISP4 policy<{'arm64': '-'}> CONFIG_AMLOGIC_THERMAL policy<{'arm64': '-'}> +CONFIG_ANDROID_BINDER_IPC_RUST policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_APPLE_ADMAC policy<{'arm64': '-'}> CONFIG_APPLE_AIC policy<{'arm64': '-'}> CONFIG_APPLE_DART policy<{'arm64': '-'}> @@ -278,6 +282,7 @@ CONFIG_ARM_TEGRA194_CPUFREQ policy<{'arm64': '-'}> CONFIG_ARM_TEGRA20_CPUFREQ policy<{'arm64': '-'}> CONFIG_ARM_TEGRA_DEVFREQ policy<{'arm64': '-'}> CONFIG_ARM_TI_CPUFREQ policy<{'arm64': '-'}> +CONFIG_AS_VERSION policy<{'arm64': '24600', 'arm64-qcom': '24200'}> CONFIG_ATH10K_DFS_CERTIFIED policy<{'arm64': 'n'}> CONFIG_ATH11K_COREDUMP policy<{'arm64': '-'}> CONFIG_ATH5K_TEST_CHANNELS policy<{'arm64': 'n'}> @@ -287,6 +292,7 @@ CONFIG_ATH9K_TX99 policy<{'arm64': 'n'}> CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING policy<{'arm64': 'n'}> CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS policy<{'arm64': 'y'}> CONFIG_AX88179B policy<{'arm64': '-'}> +CONFIG_AX88796B_RUST_PHY policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_AXI_DMAC policy<{'arm64': '-'}> CONFIG_BACKLIGHT_APPLE_DWI policy<{'arm64': '-'}> CONFIG_BACKLIGHT_QCOM_WLED policy<{'arm64': 'y'}> @@ -300,7 +306,9 @@ CONFIG_BCMDHD_SDIO policy<{'arm64': '-'}> CONFIG_BCMDHD_SDIO_IRQ policy<{'arm64': '-'}> CONFIG_BCMDHD_USB policy<{'arm64': '-'}> CONFIG_BERLIN2_ADC policy<{'arm64': '-'}> +CONFIG_BINDGEN_VERSION_TEXT policy<{'arm64': '"bindgen 0.72.1"', 'arm64-qcom': '-'}> CONFIG_BLK_CGROUP_IOLATENCY policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> +CONFIG_BLK_DEV_RUST_NULL policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_BRIDGE_EBT_BROUTE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_BRIDGE_EBT_T_FILTER policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_BRIDGE_EBT_T_NAT policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> @@ -310,6 +318,11 @@ CONFIG_CAN_RCAR policy<{'arm64': '-'}> CONFIG_CAN_RCAR_CANFD policy<{'arm64': '-'}> CONFIG_CAN_ROCKCHIP_CANFD policy<{'arm64': '-'}> CONFIG_CAVIUM_CPT policy<{'arm64': '-'}> +CONFIG_CC_HAS_COUNTED_BY policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_CC_VERSION_TEXT policy<{'arm64': '"aarch64-linux-gnu-gcc (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'arm64-qcom': '"aarch64-linux-gnu-gcc (Ubuntu 13.3.0-6ubuntu2~24.04.1) 13.3.0"'}> CONFIG_CEC_GPIO policy<{'arm64': 'm', 'arm64-qcom-rt': 'n'}> CONFIG_CEC_MESON_AO policy<{'arm64': '-'}> CONFIG_CEC_MESON_G12A_AO policy<{'arm64': '-'}> @@ -331,7 +344,7 @@ CONFIG_CLK_ELIZA_DISPCC policy<{'arm64-qcom': 'y', 'arm6 CONFIG_CLK_ELIZA_GCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_ELIZA_TCSRCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_GLYMUR_CAMCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> -CONFIG_CLK_GLYMUR_EVACC policy<{'arm64': 'm'}> +CONFIG_CLK_GLYMUR_EVACC policy<{'arm64-qcom': 'm'}> CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_GPUCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_VIDEOCC policy<{'arm64': 'y'}> @@ -400,7 +413,7 @@ CONFIG_CLK_RK3588 policy<{'arm64': '-'}> CONFIG_CLK_RV1126B policy<{'arm64': '-'}> CONFIG_CLK_RZG2L policy<{'arm64': '-'}> CONFIG_CLK_RZV2H policy<{'arm64': '-'}> -CONFIG_CLK_SHIKRA_AUDIOCORECC policy<{'arm64': 'y'}> +CONFIG_CLK_SHIKRA_AUDIOCORECC policy<{'arm64-qcom': 'm'}> CONFIG_CLK_SHIKRA_DISPCC policy<{'arm64': 'm'}> CONFIG_CLK_SHIKRA_GCC policy<{'arm64': 'y'}> CONFIG_CLK_SHIKRA_GPUCC policy<{'arm64': 'm'}> @@ -618,6 +631,7 @@ CONFIG_COMMON_RESET_HI6220 policy<{'arm64': '-'}> CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'arm64': '1', 'arm64-qcom-rt': '0'}> CONFIG_CORESIGHT policy<{'arm64': 'm'}> CONFIG_CORESIGHT_CPU_DEBUG policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_CTCU policy<{'arm64-qcom': '-'}> CONFIG_CORESIGHT_CTI policy<{'arm64': 'n'}> CONFIG_CORESIGHT_DUMMY policy<{'arm64': 'm'}> CONFIG_CORESIGHT_LINKS_AND_SINKS policy<{'arm64': 'm'}> @@ -630,6 +644,7 @@ CONFIG_CORESIGHT_TNOC policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TPDA policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TPDM policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TRBE policy<{'arm64': 'n'}> +CONFIG_CPUFREQ_DT_RUST policy<{'arm64': 'm', 'arm64-qcom': '-'}> CONFIG_CPUMASK_OFFSTACK policy<{'arm64': '-'}> CONFIG_CRC7 policy<{'arm64': 'y'}> CONFIG_CRC_ITU_T policy<{'arm64': 'y'}> @@ -758,7 +773,7 @@ CONFIG_DRM_INNO_HDMI policy<{'arm64': '-'}> CONFIG_DRM_KMB_DISPLAY policy<{'arm64': '-'}> CONFIG_DRM_LOGICVC policy<{'arm64': 'n'}> CONFIG_DRM_LONTIUM_LT8713SX policy<{'arm64': 'm'}> -CONFIG_DRM_LONTIUM_LT9611C policy<{'arm64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611C policy<{'arm64-qcom': 'n'}> CONFIG_DRM_MEDIATEK policy<{'arm64': '-'}> CONFIG_DRM_MEDIATEK_DP policy<{'arm64': '-'}> CONFIG_DRM_MEDIATEK_HDMI policy<{'arm64': '-'}> @@ -767,7 +782,7 @@ CONFIG_DRM_MEDIATEK_HDMI_V2 policy<{'arm64': '-'}> CONFIG_DRM_MESON policy<{'arm64': '-'}> CONFIG_DRM_MESON_DW_HDMI policy<{'arm64': '-'}> CONFIG_DRM_MESON_DW_MIPI_DSI policy<{'arm64': '-'}> -CONFIG_DRM_MSM_VALIDATE_XML policy<{'arm64': '-'}> +CONFIG_DRM_MSM_VALIDATE_XML policy<{'arm64': '-', 'arm64-qcom': 'n'}> CONFIG_DRM_MXS policy<{'arm64': '-'}> CONFIG_DRM_MXSFB policy<{'arm64': '-'}> CONFIG_DRM_NOUVEAU policy<{'arm64': 'n'}> @@ -778,6 +793,7 @@ CONFIG_DRM_NOUVEAU_SIL164 policy<{'arm64': '-'}> CONFIG_DRM_NOUVEAU_SVM policy<{'arm64': '-'}> CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS policy<{'arm64': '-'}> CONFIG_DRM_PANEL_DLC0697 policy<{'arm64': 'y'}> +CONFIG_DRM_PANIC_SCREEN_QR_CODE policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_DRM_PL111 policy<{'arm64': 'n'}> CONFIG_DRM_RADEON policy<{'arm64': 'n'}> CONFIG_DRM_RADEON_USERPTR policy<{'arm64': '-'}> @@ -813,6 +829,7 @@ CONFIG_DRM_TEGRA policy<{'arm64': '-'}> CONFIG_DRM_TEGRA_DEBUG policy<{'arm64': '-'}> CONFIG_DRM_TEGRA_STAGING policy<{'arm64': '-'}> CONFIG_DRM_TIDSS policy<{'arm64': 'n'}> +CONFIG_DRM_TYR policy<{'arm64': 'm', 'arm64-qcom': '-'}> CONFIG_DRM_XE policy<{'arm64': 'n'}> CONFIG_DRM_XE_DEBUG policy<{'arm64': '-'}> CONFIG_DRM_XE_DEBUG_MEM policy<{'arm64': '-'}> @@ -879,6 +896,7 @@ CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA policy<{'arm64': '-'}> CONFIG_FB_SH_MOBILE_LCDC policy<{'arm64': '-'}> CONFIG_FB_XILINX policy<{'arm64': '-'}> CONFIG_FEC policy<{'arm64': '-'}> +CONFIG_FIND_BIT_BENCHMARK_RUST policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_FPGA_MGR_SOCFPGA policy<{'arm64': '-'}> CONFIG_FPGA_MGR_SOCFPGA_A10 policy<{'arm64': '-'}> CONFIG_FPGA_MGR_STRATIX10_SOC policy<{'arm64': '-'}> @@ -908,6 +926,7 @@ CONFIG_FS_DAX_PMD policy<{'arm64': 'y', 'arm64-qco CONFIG_FUEL_GAUGE_SC27XX policy<{'arm64': '-'}> CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT policy<{'arm64': 'y'}> CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND policy<{'arm64': '-'}> +CONFIG_GCC_VERSION policy<{'arm64': '150200', 'arm64-qcom': '130300'}> CONFIG_GENERIC_IRQ_IPI_MUX policy<{'arm64': '-'}> CONFIG_GH_VIRT_WATCHDOG policy<{'arm64': '-'}> CONFIG_GPIO_ALTERA_A10SR policy<{'arm64': '-'}> @@ -959,6 +978,7 @@ CONFIG_HAVE_KVM_IRQ_ROUTING policy<{'arm64': 'y', 'arm64-qco CONFIG_HAVE_KVM_MSI policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_HAVE_KVM_READONLY_MEM policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_HAVE_RUST policy<{'arm64': 'y', 'arm64-qcom': '-'}> CONFIG_HAVE_SCHED_AVG_IRQ policy<{'arm64-qcom-rt': 'y'}> CONFIG_HBMC_AM654 policy<{'arm64': '-'}> CONFIG_HI3660_MBOX policy<{'arm64': '-'}> @@ -1157,6 +1177,7 @@ CONFIG_KVM_MMIO policy<{'arm64': 'y', 'arm64-qco CONFIG_KVM_VFIO policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_LAN966X_OIC policy<{'arm64': '-'}> CONFIG_LAN969X_SWITCH policy<{'arm64': '-'}> +CONFIG_LD_VERSION policy<{'arm64': '24600', 'arm64-qcom': '24200'}> CONFIG_LEDS_SC27XX_BLTC policy<{'arm64': '-'}> CONFIG_LEDS_SUN50I_A100 policy<{'arm64': '-'}> CONFIG_LEDS_TRIGGER_CPU policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> @@ -1165,6 +1186,8 @@ CONFIG_LOG_BUF_SHIFT policy<{'arm64': '17'}> CONFIG_LSM_MMAP_MIN_ADDR policy<{'arm64': '32768'}> CONFIG_LS_EXTIRQ policy<{'arm64': '-'}> CONFIG_LS_SCFG_MSI policy<{'arm64': '-'}> +CONFIG_LZ4HC_COMPRESS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_LZ4_COMPRESS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_MACVLAN policy<{'arm64': 'y'}> CONFIG_MACVTAP policy<{'arm64': 'y'}> CONFIG_MARVELL_CN10K_DDR_PMU policy<{'arm64': '-'}> @@ -1256,6 +1279,9 @@ CONFIG_MMC_TMIO_CORE policy<{'arm64': '-'}> CONFIG_MMP_PDMA policy<{'arm64': '-'}> CONFIG_MMP_TDMA policy<{'arm64': '-'}> CONFIG_MM_ID policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_44 policy<{'arm64': 'n', 'arm64-qcom': '-'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_65 policy<{'arm64': 'n', 'arm64-qcom': '-'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_87 policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_MSM_GCC_8916 policy<{'arm64': 'y'}> CONFIG_MSM_GCC_8994 policy<{'arm64': 'y'}> CONFIG_MSM_GCC_8998 policy<{'arm64': 'y'}> @@ -1350,6 +1376,7 @@ CONFIG_NOUVEAU_DEBUG_DEFAULT policy<{'arm64': '-'}> CONFIG_NOUVEAU_DEBUG_MMU policy<{'arm64': '-'}> CONFIG_NOUVEAU_DEBUG_PUSH policy<{'arm64': '-'}> CONFIG_NOUVEAU_PLATFORM_DRIVER policy<{'arm64': '-'}> +CONFIG_NOVA_CORE policy<{'arm64': 'm', 'arm64-qcom': '-'}> CONFIG_NO_PAGE_MAPCOUNT policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_NPCM7XX_KCS_IPMI_BMC policy<{'arm64': '-'}> CONFIG_NPCM7XX_TIMER policy<{'arm64': '-'}> @@ -1384,7 +1411,7 @@ CONFIG_NVMEM_ZYNQMP policy<{'arm64': '-'}> CONFIG_NVME_APPLE policy<{'arm64': '-'}> CONFIG_NXP_SAR_ADC policy<{'arm64': '-'}> CONFIG_NXP_STM_TIMER policy<{'arm64': '-'}> -CONFIG_OF_AEST policy<{'arm64': 'y'}> +CONFIG_OF_AEST policy<{'arm64-qcom': 'n'}> CONFIG_OLPC_EC policy<{'arm64': '-'}> CONFIG_OLPC_XO175 policy<{'arm64': '-'}> CONFIG_OLPC_XO175_EC policy<{'arm64': '-'}> @@ -1394,12 +1421,14 @@ CONFIG_OMAP_GPMC policy<{'arm64': '-'}> CONFIG_OMAP_GPMC_DEBUG policy<{'arm64': '-'}> CONFIG_OMAP_MBOX_KFIFO_SIZE policy<{'arm64': '-'}> CONFIG_OMAP_USB2 policy<{'arm64': '-'}> +CONFIG_OPENSSL_SUPPORTS_ML_DSA policy<{'arm64': 'y', 'arm64-qcom': '-'}> CONFIG_OWL_DMA policy<{'arm64': '-'}> CONFIG_OWL_EMAC policy<{'arm64': '-'}> CONFIG_OWL_PM_DOMAINS policy<{'arm64': '-'}> CONFIG_OWL_PM_DOMAINS_HELPER policy<{'arm64': '-'}> CONFIG_OWL_TIMER policy<{'arm64': '-'}> CONFIG_PAGE_BLOCK_MAX_ORDER policy<{'arm64': '10'}> +CONFIG_PAHOLE_VERSION policy<{'arm64': '131', 'arm64-qcom': '125'}> CONFIG_PANIC_TIMEOUT policy<{'arm64': '-1'}> CONFIG_PATA_IMX policy<{'arm64': '-'}> CONFIG_PCIE_APPLE policy<{'arm64': '-'}> @@ -1741,6 +1770,7 @@ CONFIG_PINCTRL_VISCONTI policy<{'arm64': '-'}> CONFIG_PINCTRL_X1E80100 policy<{'arm64': 'y'}> CONFIG_PINCTRL_ZYNQMP policy<{'arm64': '-'}> CONFIG_PM_AUTOSLEEP policy<{'arm64': 'y'}> +CONFIG_PM_WAKELOCKS_GC policy<{'arm64': 'y', 'arm64-qcom': 'n'}> CONFIG_PM_WAKELOCKS_LIMIT policy<{'arm64': '0'}> CONFIG_POWER_RESET_HISI policy<{'arm64': '-'}> CONFIG_POWER_RESET_LINKSTATION policy<{'arm64': '-'}> @@ -1799,7 +1829,7 @@ CONFIG_QCOM_APR policy<{'arm64': 'y'}> CONFIG_QCOM_BAM_DMA policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_APCC_MSM8996 policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_APCS_MSM8916 policy<{'arm64': 'y'}> -CONFIG_QCOM_CLK_GP_MND policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_GP_MND policy<{'arm64-qcom': 'n'}> CONFIG_QCOM_CLK_SMD_RPM policy<{'arm64': 'y'}> CONFIG_QCOM_CPR policy<{'arm64': 'y'}> CONFIG_QCOM_CPUCP_MBOX policy<{'arm64': 'y'}> @@ -1848,7 +1878,7 @@ CONFIG_QCOM_SMP2P policy<{'arm64': 'y'}> CONFIG_QCOM_SMP2P_SLEEPSTATE policy<{'arm64': '-'}> CONFIG_QCOM_SMSM policy<{'arm64': 'y'}> CONFIG_QCOM_SOC_DEBUG policy<{'arm64': '-'}> -CONFIG_QCOM_SPEL policy<{'arm64': 'y'}> +CONFIG_QCOM_SPEL policy<{'arm64-qcom': 'm'}> CONFIG_QCOM_SPMI_ADC5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_ADC_TM5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_MBG_TM policy<{'arm64': '-'}> @@ -1900,6 +1930,7 @@ CONFIG_REGULATOR_STM32_BOOSTER policy<{'arm64': '-'}> CONFIG_REGULATOR_STM32_PWR policy<{'arm64': '-'}> CONFIG_REGULATOR_STM32_VREFBUF policy<{'arm64': '-'}> CONFIG_REGULATOR_SUN20I policy<{'arm64': '-'}> +CONFIG_RELR policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_REMOTEPROC_THERMAL policy<{'arm64': 'y'}> CONFIG_RENESAS_DMA policy<{'arm64': '-'}> CONFIG_RENESAS_ETHER_SWITCH policy<{'arm64': '-'}> @@ -1997,7 +2028,23 @@ CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> CONFIG_RTSN policy<{'arm64': '-'}> -CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11)"'}> +CONFIG_RUSTC_HAS_COERCE_POINTEE policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUSTC_HAS_FILE_AS_C_STR policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUSTC_HAS_FILE_WITH_NUL policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUSTC_HAS_SLICE_AS_FLATTENED policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUSTC_HAS_SPAN_FILE policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUSTC_LLVM_VERSION policy<{'arm64': '210108', 'arm64-qcom': '170006'}> +CONFIG_RUSTC_SUPPORTS_ARM64 policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUSTC_VERSION policy<{'arm64': '109301', 'arm64-qcom': '107500'}> +CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11) (built from a source tarball)"', 'arm64-qcom': '-'}> +CONFIG_RUST_BITMAP_HARDENED policy<{'arm64': 'n', 'arm64-qcom': '-'}> +CONFIG_RUST_BUILD_ASSERT_ALLOW policy<{'arm64': 'n', 'arm64-qcom': '-'}> +CONFIG_RUST_DEBUG_ASSERTIONS policy<{'arm64': 'n', 'arm64-qcom': '-'}> +CONFIG_RUST_FW_LOADER_ABSTRACTIONS policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUST_IS_AVAILABLE policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUST_OVERFLOW_CHECKS policy<{'arm64': 'y', 'arm64-qcom': '-'}> +CONFIG_RUST_PHYLIB_ABSTRACTIONS policy<{'arm64': 'y', 'arm64-qcom': '-'}> CONFIG_RZG2L_ADC policy<{'arm64': '-'}> CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> @@ -2007,11 +2054,13 @@ CONFIG_RZ_DMAC policy<{'arm64': '-'}> CONFIG_RZ_MTU3 policy<{'arm64': '-'}> CONFIG_RZ_MTU3_CNT policy<{'arm64': '-'}> CONFIG_S32G_WDT policy<{'arm64': '-'}> +CONFIG_SAMPLES_RUST policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_SAMPLE_CORESIGHT_SYSCFG policy<{'arm64': 'n'}> CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': '-'}> CONFIG_SATA_RCAR policy<{'arm64': '-'}> CONFIG_SC27XX_ADC policy<{'arm64': '-'}> -CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ policy<{'arm64': 'm'}> +CONFIG_SCHED_DEBUG policy<{'arm64-qcom': '-'}> +CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ policy<{'arm64': 'y', 'arm64-qcom': 'm'}> CONFIG_SCSI_UFS_AMD_VERSAL2 policy<{'arm64': '-'}> CONFIG_SCSI_UFS_HISI policy<{'arm64': '-'}> CONFIG_SCSI_UFS_MEDIATEK policy<{'arm64': '-'}> @@ -2510,6 +2559,7 @@ CONFIG_TI_SCI_PM_DOMAINS policy<{'arm64': '-'}> CONFIG_TI_SCI_PROTOCOL policy<{'arm64': '-'}> CONFIG_TI_SYSC policy<{'arm64': '-'}> CONFIG_TI_SYSCON_CLK policy<{'arm64': '-'}> +CONFIG_TOOLS_SUPPORT_RELR policy<{'arm64': 'y', 'arm64-qcom': '-'}> CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C policy<{'arm64': 'n'}> CONFIG_TOUCHSCREEN_SUN4I policy<{'arm64': '-'}> CONFIG_TOUCHSCREEN_TI_AM335X_TSC policy<{'arm64': '-'}> @@ -2572,6 +2622,7 @@ CONFIG_V4L2_ISP policy<{'arm64': '-'}> CONFIG_V4L2_JPEG_HELPER policy<{'arm64': '-'}> CONFIG_V4L2_VP9 policy<{'arm64': '-'}> CONFIG_VCPU_STALL_DETECTOR policy<{'arm64': 'y'}> +CONFIG_VERSION_SIGNATURE policy<{'arm64': '""', 'arm64-qcom': '"Ubuntu 7.0.0-1006.8-qcom 7.0.6"'}> CONFIG_VFIO_FSL_MC policy<{'arm64': '-'}> CONFIG_VHOST policy<{'arm64': 'y'}> CONFIG_VHOST_IOTLB policy<{'arm64': 'y'}> @@ -2653,7 +2704,12 @@ CONFIG_VIRTIO_VSOCKETS_COMMON policy<{'arm64': 'y'}> CONFIG_VISCONTI_WATCHDOG policy<{'arm64': '-'}> CONFIG_VMAP_PFN policy<{'arm64': '-'}> CONFIG_VSOCKETS policy<{'arm64': 'y'}> +CONFIG_VSOCKETS_DIAG policy<{'arm64': 'm', 'arm64-qcom': 'n'}> +CONFIG_VSOCKETS_LOOPBACK policy<{'arm64': 'm', 'arm64-qcom': 'n'}> CONFIG_W1_MASTER_MXC policy<{'arm64': '-'}> +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP policy<{'arm64': 'y', 'arm64-qcom': 'n'}> +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC policy<{'arm64': 'n', 'arm64-qcom': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_WLAN_VENDOR_BCMDHD policy<{'arm64': '-'}> CONFIG_WQ_POWER_EFFICIENT_DEFAULT policy<{'arm64': 'n'}> CONFIG_XE_VFIO_PCI policy<{'arm64': '-'}> @@ -2663,6 +2719,7 @@ CONFIG_XGENE_SLIMPRO_MBOX policy<{'arm64': '-'}> CONFIG_XILINX_AMS policy<{'arm64': '-'}> CONFIG_XLNX_EVENT_MANAGER policy<{'arm64': '-'}> CONFIG_XLNX_R5_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_ZRAM policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_ZYNQMP_FIRMWARE policy<{'arm64': '-'}> CONFIG_ZYNQMP_FIRMWARE_DEBUG policy<{'arm64': '-'}> CONFIG_ZYNQMP_IPI_MBOX policy<{'arm64': '-'}> From ae5d16685a621586f1be38095ac05da7e94e3444 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Mon, 6 Jul 2026 12:13:43 +0800 Subject: [PATCH 1241/1330] Revert "Synchronize with Qualcomm config" This reverts commit 13e586d16c32e24a66a63ed62b8b0288f5d6b668. Signed-off-by: Yushan Li (cherry picked from commit 7d5c72e7a77264de7b60df3c511519ad42b79b06) --- debian.qcom/config/annotations | 78 +--------------------------------- 1 file changed, 2 insertions(+), 76 deletions(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index bab578d1214a2..ef7edbcfbee03 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -18,18 +18,12 @@ CONFIG_ARCH_ROCKCHIP note<'LP: #1825222'> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': 'y'}> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT note<'LP: #2102032'> -CONFIG_CHR_DEV_SG policy<{'arm64': 'y', 'arm64-qcom': 'm'}> -CONFIG_CHR_DEV_SG note<'TODO: update note'> - CONFIG_DRM_AMDGPU_CIK policy<{'arm64': '-'}> CONFIG_DRM_AMDGPU_CIK note<'for zesty'> CONFIG_DRM_MGAG200 policy<{'arm64': 'n'}> CONFIG_DRM_MGAG200 note<'LP: #1693337'> -CONFIG_DRM_NOVA policy<{'arm64': 'n', 'arm64-qcom': '-'}> -CONFIG_DRM_NOVA note - CONFIG_EFI_ZBOOT policy<{'arm64': 'n'}> CONFIG_EFI_ZBOOT note<'we use arch/arm64/boot/Image.gz'> @@ -87,9 +81,6 @@ CONFIG_RCU_NOCB_CPU_DEFAULT_ALL note<'TODO: update note'> CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'arm64': 'y'}> CONFIG_REGULATOR_FIXED_VOLTAGE note<'boot essential on arm'> -CONFIG_RUST policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUST note - CONFIG_SERIAL_SH_SCI policy<{'arm64': '-'}> CONFIG_SERIAL_SH_SCI note<'LP: #2022361'> @@ -123,10 +114,7 @@ CONFIG_TOUCHSCREEN_APPLE_Z2 note<'TODO: update note'> # ---- Annotations without notes ---- -CONFIG_842_COMPRESS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> -CONFIG_842_DECOMPRESS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_AC97_BUS policy<{'arm64': 'y'}> -CONFIG_ACPI_AEST policy<{'arm64-qcom': 'n'}> CONFIG_ADI_AXI_ADC policy<{'arm64': '-'}> CONFIG_ADI_AXI_DAC policy<{'arm64': '-'}> CONFIG_AEST policy<{'arm64': 'y'}> @@ -140,10 +128,8 @@ CONFIG_AHCI_XGENE policy<{'arm64': '-'}> CONFIG_AIROHA_CPU_PM_DOMAIN policy<{'arm64': '-'}> CONFIG_AIROHA_THERMAL policy<{'arm64': '-'}> CONFIG_AIROHA_WATCHDOG policy<{'arm64': '-'}> -CONFIG_AMCC_QT2025_PHY policy<{'arm64': 'm', 'arm64-qcom': '-'}> CONFIG_AMD_ISP4 policy<{'arm64': '-'}> CONFIG_AMLOGIC_THERMAL policy<{'arm64': '-'}> -CONFIG_ANDROID_BINDER_IPC_RUST policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_APPLE_ADMAC policy<{'arm64': '-'}> CONFIG_APPLE_AIC policy<{'arm64': '-'}> CONFIG_APPLE_DART policy<{'arm64': '-'}> @@ -282,7 +268,6 @@ CONFIG_ARM_TEGRA194_CPUFREQ policy<{'arm64': '-'}> CONFIG_ARM_TEGRA20_CPUFREQ policy<{'arm64': '-'}> CONFIG_ARM_TEGRA_DEVFREQ policy<{'arm64': '-'}> CONFIG_ARM_TI_CPUFREQ policy<{'arm64': '-'}> -CONFIG_AS_VERSION policy<{'arm64': '24600', 'arm64-qcom': '24200'}> CONFIG_ATH10K_DFS_CERTIFIED policy<{'arm64': 'n'}> CONFIG_ATH11K_COREDUMP policy<{'arm64': '-'}> CONFIG_ATH5K_TEST_CHANNELS policy<{'arm64': 'n'}> @@ -292,7 +277,6 @@ CONFIG_ATH9K_TX99 policy<{'arm64': 'n'}> CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING policy<{'arm64': 'n'}> CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS policy<{'arm64': 'y'}> CONFIG_AX88179B policy<{'arm64': '-'}> -CONFIG_AX88796B_RUST_PHY policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_AXI_DMAC policy<{'arm64': '-'}> CONFIG_BACKLIGHT_APPLE_DWI policy<{'arm64': '-'}> CONFIG_BACKLIGHT_QCOM_WLED policy<{'arm64': 'y'}> @@ -306,9 +290,7 @@ CONFIG_BCMDHD_SDIO policy<{'arm64': '-'}> CONFIG_BCMDHD_SDIO_IRQ policy<{'arm64': '-'}> CONFIG_BCMDHD_USB policy<{'arm64': '-'}> CONFIG_BERLIN2_ADC policy<{'arm64': '-'}> -CONFIG_BINDGEN_VERSION_TEXT policy<{'arm64': '"bindgen 0.72.1"', 'arm64-qcom': '-'}> CONFIG_BLK_CGROUP_IOLATENCY policy<{'arm64': 'n', 'arm64-qcom-rt': 'y'}> -CONFIG_BLK_DEV_RUST_NULL policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_BRIDGE_EBT_BROUTE policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_BRIDGE_EBT_T_FILTER policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> CONFIG_BRIDGE_EBT_T_NAT policy<{'arm64': 'm', 'arm64-qcom-rt': '-'}> @@ -318,11 +300,6 @@ CONFIG_CAN_RCAR policy<{'arm64': '-'}> CONFIG_CAN_RCAR_CANFD policy<{'arm64': '-'}> CONFIG_CAN_ROCKCHIP_CANFD policy<{'arm64': '-'}> CONFIG_CAVIUM_CPT policy<{'arm64': '-'}> -CONFIG_CC_HAS_COUNTED_BY policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_CC_VERSION_TEXT policy<{'arm64': '"aarch64-linux-gnu-gcc (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'arm64-qcom': '"aarch64-linux-gnu-gcc (Ubuntu 13.3.0-6ubuntu2~24.04.1) 13.3.0"'}> CONFIG_CEC_GPIO policy<{'arm64': 'm', 'arm64-qcom-rt': 'n'}> CONFIG_CEC_MESON_AO policy<{'arm64': '-'}> CONFIG_CEC_MESON_G12A_AO policy<{'arm64': '-'}> @@ -344,7 +321,6 @@ CONFIG_CLK_ELIZA_DISPCC policy<{'arm64-qcom': 'y', 'arm6 CONFIG_CLK_ELIZA_GCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_ELIZA_TCSRCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_GLYMUR_CAMCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> -CONFIG_CLK_GLYMUR_EVACC policy<{'arm64-qcom': 'm'}> CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_GPUCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_VIDEOCC policy<{'arm64': 'y'}> @@ -413,7 +389,6 @@ CONFIG_CLK_RK3588 policy<{'arm64': '-'}> CONFIG_CLK_RV1126B policy<{'arm64': '-'}> CONFIG_CLK_RZG2L policy<{'arm64': '-'}> CONFIG_CLK_RZV2H policy<{'arm64': '-'}> -CONFIG_CLK_SHIKRA_AUDIOCORECC policy<{'arm64-qcom': 'm'}> CONFIG_CLK_SHIKRA_DISPCC policy<{'arm64': 'm'}> CONFIG_CLK_SHIKRA_GCC policy<{'arm64': 'y'}> CONFIG_CLK_SHIKRA_GPUCC policy<{'arm64': 'm'}> @@ -631,7 +606,6 @@ CONFIG_COMMON_RESET_HI6220 policy<{'arm64': '-'}> CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'arm64': '1', 'arm64-qcom-rt': '0'}> CONFIG_CORESIGHT policy<{'arm64': 'm'}> CONFIG_CORESIGHT_CPU_DEBUG policy<{'arm64': 'n'}> -CONFIG_CORESIGHT_CTCU policy<{'arm64-qcom': '-'}> CONFIG_CORESIGHT_CTI policy<{'arm64': 'n'}> CONFIG_CORESIGHT_DUMMY policy<{'arm64': 'm'}> CONFIG_CORESIGHT_LINKS_AND_SINKS policy<{'arm64': 'm'}> @@ -644,7 +618,6 @@ CONFIG_CORESIGHT_TNOC policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TPDA policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TPDM policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TRBE policy<{'arm64': 'n'}> -CONFIG_CPUFREQ_DT_RUST policy<{'arm64': 'm', 'arm64-qcom': '-'}> CONFIG_CPUMASK_OFFSTACK policy<{'arm64': '-'}> CONFIG_CRC7 policy<{'arm64': 'y'}> CONFIG_CRC_ITU_T policy<{'arm64': 'y'}> @@ -773,7 +746,6 @@ CONFIG_DRM_INNO_HDMI policy<{'arm64': '-'}> CONFIG_DRM_KMB_DISPLAY policy<{'arm64': '-'}> CONFIG_DRM_LOGICVC policy<{'arm64': 'n'}> CONFIG_DRM_LONTIUM_LT8713SX policy<{'arm64': 'm'}> -CONFIG_DRM_LONTIUM_LT9611C policy<{'arm64-qcom': 'n'}> CONFIG_DRM_MEDIATEK policy<{'arm64': '-'}> CONFIG_DRM_MEDIATEK_DP policy<{'arm64': '-'}> CONFIG_DRM_MEDIATEK_HDMI policy<{'arm64': '-'}> @@ -782,7 +754,7 @@ CONFIG_DRM_MEDIATEK_HDMI_V2 policy<{'arm64': '-'}> CONFIG_DRM_MESON policy<{'arm64': '-'}> CONFIG_DRM_MESON_DW_HDMI policy<{'arm64': '-'}> CONFIG_DRM_MESON_DW_MIPI_DSI policy<{'arm64': '-'}> -CONFIG_DRM_MSM_VALIDATE_XML policy<{'arm64': '-', 'arm64-qcom': 'n'}> +CONFIG_DRM_MSM_VALIDATE_XML policy<{'arm64': '-'}> CONFIG_DRM_MXS policy<{'arm64': '-'}> CONFIG_DRM_MXSFB policy<{'arm64': '-'}> CONFIG_DRM_NOUVEAU policy<{'arm64': 'n'}> @@ -793,7 +765,6 @@ CONFIG_DRM_NOUVEAU_SIL164 policy<{'arm64': '-'}> CONFIG_DRM_NOUVEAU_SVM policy<{'arm64': '-'}> CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS policy<{'arm64': '-'}> CONFIG_DRM_PANEL_DLC0697 policy<{'arm64': 'y'}> -CONFIG_DRM_PANIC_SCREEN_QR_CODE policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_DRM_PL111 policy<{'arm64': 'n'}> CONFIG_DRM_RADEON policy<{'arm64': 'n'}> CONFIG_DRM_RADEON_USERPTR policy<{'arm64': '-'}> @@ -829,7 +800,6 @@ CONFIG_DRM_TEGRA policy<{'arm64': '-'}> CONFIG_DRM_TEGRA_DEBUG policy<{'arm64': '-'}> CONFIG_DRM_TEGRA_STAGING policy<{'arm64': '-'}> CONFIG_DRM_TIDSS policy<{'arm64': 'n'}> -CONFIG_DRM_TYR policy<{'arm64': 'm', 'arm64-qcom': '-'}> CONFIG_DRM_XE policy<{'arm64': 'n'}> CONFIG_DRM_XE_DEBUG policy<{'arm64': '-'}> CONFIG_DRM_XE_DEBUG_MEM policy<{'arm64': '-'}> @@ -896,7 +866,6 @@ CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA policy<{'arm64': '-'}> CONFIG_FB_SH_MOBILE_LCDC policy<{'arm64': '-'}> CONFIG_FB_XILINX policy<{'arm64': '-'}> CONFIG_FEC policy<{'arm64': '-'}> -CONFIG_FIND_BIT_BENCHMARK_RUST policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_FPGA_MGR_SOCFPGA policy<{'arm64': '-'}> CONFIG_FPGA_MGR_SOCFPGA_A10 policy<{'arm64': '-'}> CONFIG_FPGA_MGR_STRATIX10_SOC policy<{'arm64': '-'}> @@ -926,7 +895,6 @@ CONFIG_FS_DAX_PMD policy<{'arm64': 'y', 'arm64-qco CONFIG_FUEL_GAUGE_SC27XX policy<{'arm64': '-'}> CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT policy<{'arm64': 'y'}> CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND policy<{'arm64': '-'}> -CONFIG_GCC_VERSION policy<{'arm64': '150200', 'arm64-qcom': '130300'}> CONFIG_GENERIC_IRQ_IPI_MUX policy<{'arm64': '-'}> CONFIG_GH_VIRT_WATCHDOG policy<{'arm64': '-'}> CONFIG_GPIO_ALTERA_A10SR policy<{'arm64': '-'}> @@ -978,7 +946,6 @@ CONFIG_HAVE_KVM_IRQ_ROUTING policy<{'arm64': 'y', 'arm64-qco CONFIG_HAVE_KVM_MSI policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_HAVE_KVM_READONLY_MEM policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> -CONFIG_HAVE_RUST policy<{'arm64': 'y', 'arm64-qcom': '-'}> CONFIG_HAVE_SCHED_AVG_IRQ policy<{'arm64-qcom-rt': 'y'}> CONFIG_HBMC_AM654 policy<{'arm64': '-'}> CONFIG_HI3660_MBOX policy<{'arm64': '-'}> @@ -1177,7 +1144,6 @@ CONFIG_KVM_MMIO policy<{'arm64': 'y', 'arm64-qco CONFIG_KVM_VFIO policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> CONFIG_LAN966X_OIC policy<{'arm64': '-'}> CONFIG_LAN969X_SWITCH policy<{'arm64': '-'}> -CONFIG_LD_VERSION policy<{'arm64': '24600', 'arm64-qcom': '24200'}> CONFIG_LEDS_SC27XX_BLTC policy<{'arm64': '-'}> CONFIG_LEDS_SUN50I_A100 policy<{'arm64': '-'}> CONFIG_LEDS_TRIGGER_CPU policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> @@ -1186,8 +1152,6 @@ CONFIG_LOG_BUF_SHIFT policy<{'arm64': '17'}> CONFIG_LSM_MMAP_MIN_ADDR policy<{'arm64': '32768'}> CONFIG_LS_EXTIRQ policy<{'arm64': '-'}> CONFIG_LS_SCFG_MSI policy<{'arm64': '-'}> -CONFIG_LZ4HC_COMPRESS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> -CONFIG_LZ4_COMPRESS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_MACVLAN policy<{'arm64': 'y'}> CONFIG_MACVTAP policy<{'arm64': 'y'}> CONFIG_MARVELL_CN10K_DDR_PMU policy<{'arm64': '-'}> @@ -1279,9 +1243,6 @@ CONFIG_MMC_TMIO_CORE policy<{'arm64': '-'}> CONFIG_MMP_PDMA policy<{'arm64': '-'}> CONFIG_MMP_TDMA policy<{'arm64': '-'}> CONFIG_MM_ID policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> -CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_44 policy<{'arm64': 'n', 'arm64-qcom': '-'}> -CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_65 policy<{'arm64': 'n', 'arm64-qcom': '-'}> -CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_87 policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_MSM_GCC_8916 policy<{'arm64': 'y'}> CONFIG_MSM_GCC_8994 policy<{'arm64': 'y'}> CONFIG_MSM_GCC_8998 policy<{'arm64': 'y'}> @@ -1376,7 +1337,6 @@ CONFIG_NOUVEAU_DEBUG_DEFAULT policy<{'arm64': '-'}> CONFIG_NOUVEAU_DEBUG_MMU policy<{'arm64': '-'}> CONFIG_NOUVEAU_DEBUG_PUSH policy<{'arm64': '-'}> CONFIG_NOUVEAU_PLATFORM_DRIVER policy<{'arm64': '-'}> -CONFIG_NOVA_CORE policy<{'arm64': 'm', 'arm64-qcom': '-'}> CONFIG_NO_PAGE_MAPCOUNT policy<{'arm64': 'n', 'arm64-qcom-rt': '-'}> CONFIG_NPCM7XX_KCS_IPMI_BMC policy<{'arm64': '-'}> CONFIG_NPCM7XX_TIMER policy<{'arm64': '-'}> @@ -1411,7 +1371,6 @@ CONFIG_NVMEM_ZYNQMP policy<{'arm64': '-'}> CONFIG_NVME_APPLE policy<{'arm64': '-'}> CONFIG_NXP_SAR_ADC policy<{'arm64': '-'}> CONFIG_NXP_STM_TIMER policy<{'arm64': '-'}> -CONFIG_OF_AEST policy<{'arm64-qcom': 'n'}> CONFIG_OLPC_EC policy<{'arm64': '-'}> CONFIG_OLPC_XO175 policy<{'arm64': '-'}> CONFIG_OLPC_XO175_EC policy<{'arm64': '-'}> @@ -1421,14 +1380,12 @@ CONFIG_OMAP_GPMC policy<{'arm64': '-'}> CONFIG_OMAP_GPMC_DEBUG policy<{'arm64': '-'}> CONFIG_OMAP_MBOX_KFIFO_SIZE policy<{'arm64': '-'}> CONFIG_OMAP_USB2 policy<{'arm64': '-'}> -CONFIG_OPENSSL_SUPPORTS_ML_DSA policy<{'arm64': 'y', 'arm64-qcom': '-'}> CONFIG_OWL_DMA policy<{'arm64': '-'}> CONFIG_OWL_EMAC policy<{'arm64': '-'}> CONFIG_OWL_PM_DOMAINS policy<{'arm64': '-'}> CONFIG_OWL_PM_DOMAINS_HELPER policy<{'arm64': '-'}> CONFIG_OWL_TIMER policy<{'arm64': '-'}> CONFIG_PAGE_BLOCK_MAX_ORDER policy<{'arm64': '10'}> -CONFIG_PAHOLE_VERSION policy<{'arm64': '131', 'arm64-qcom': '125'}> CONFIG_PANIC_TIMEOUT policy<{'arm64': '-1'}> CONFIG_PATA_IMX policy<{'arm64': '-'}> CONFIG_PCIE_APPLE policy<{'arm64': '-'}> @@ -1770,7 +1727,6 @@ CONFIG_PINCTRL_VISCONTI policy<{'arm64': '-'}> CONFIG_PINCTRL_X1E80100 policy<{'arm64': 'y'}> CONFIG_PINCTRL_ZYNQMP policy<{'arm64': '-'}> CONFIG_PM_AUTOSLEEP policy<{'arm64': 'y'}> -CONFIG_PM_WAKELOCKS_GC policy<{'arm64': 'y', 'arm64-qcom': 'n'}> CONFIG_PM_WAKELOCKS_LIMIT policy<{'arm64': '0'}> CONFIG_POWER_RESET_HISI policy<{'arm64': '-'}> CONFIG_POWER_RESET_LINKSTATION policy<{'arm64': '-'}> @@ -1829,7 +1785,6 @@ CONFIG_QCOM_APR policy<{'arm64': 'y'}> CONFIG_QCOM_BAM_DMA policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_APCC_MSM8996 policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_APCS_MSM8916 policy<{'arm64': 'y'}> -CONFIG_QCOM_CLK_GP_MND policy<{'arm64-qcom': 'n'}> CONFIG_QCOM_CLK_SMD_RPM policy<{'arm64': 'y'}> CONFIG_QCOM_CPR policy<{'arm64': 'y'}> CONFIG_QCOM_CPUCP_MBOX policy<{'arm64': 'y'}> @@ -1878,7 +1833,6 @@ CONFIG_QCOM_SMP2P policy<{'arm64': 'y'}> CONFIG_QCOM_SMP2P_SLEEPSTATE policy<{'arm64': '-'}> CONFIG_QCOM_SMSM policy<{'arm64': 'y'}> CONFIG_QCOM_SOC_DEBUG policy<{'arm64': '-'}> -CONFIG_QCOM_SPEL policy<{'arm64-qcom': 'm'}> CONFIG_QCOM_SPMI_ADC5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_ADC_TM5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_MBG_TM policy<{'arm64': '-'}> @@ -1930,7 +1884,6 @@ CONFIG_REGULATOR_STM32_BOOSTER policy<{'arm64': '-'}> CONFIG_REGULATOR_STM32_PWR policy<{'arm64': '-'}> CONFIG_REGULATOR_STM32_VREFBUF policy<{'arm64': '-'}> CONFIG_REGULATOR_SUN20I policy<{'arm64': '-'}> -CONFIG_RELR policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_REMOTEPROC_THERMAL policy<{'arm64': 'y'}> CONFIG_RENESAS_DMA policy<{'arm64': '-'}> CONFIG_RENESAS_ETHER_SWITCH policy<{'arm64': '-'}> @@ -2028,23 +1981,6 @@ CONFIG_RTC_DRV_XGENE policy<{'arm64': '-'}> CONFIG_RTD119X_WATCHDOG policy<{'arm64': '-'}> CONFIG_RTK_SYSTIMER policy<{'arm64': '-'}> CONFIG_RTSN policy<{'arm64': '-'}> -CONFIG_RUSTC_HAS_COERCE_POINTEE policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUSTC_HAS_FILE_AS_C_STR policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUSTC_HAS_FILE_WITH_NUL policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUSTC_HAS_SLICE_AS_FLATTENED policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUSTC_HAS_SPAN_FILE policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUSTC_LLVM_VERSION policy<{'arm64': '210108', 'arm64-qcom': '170006'}> -CONFIG_RUSTC_SUPPORTS_ARM64 policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUSTC_VERSION policy<{'arm64': '109301', 'arm64-qcom': '107500'}> -CONFIG_RUSTC_VERSION_TEXT policy<{'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11) (built from a source tarball)"', 'arm64-qcom': '-'}> -CONFIG_RUST_BITMAP_HARDENED policy<{'arm64': 'n', 'arm64-qcom': '-'}> -CONFIG_RUST_BUILD_ASSERT_ALLOW policy<{'arm64': 'n', 'arm64-qcom': '-'}> -CONFIG_RUST_DEBUG_ASSERTIONS policy<{'arm64': 'n', 'arm64-qcom': '-'}> -CONFIG_RUST_FW_LOADER_ABSTRACTIONS policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUST_IS_AVAILABLE policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUST_OVERFLOW_CHECKS policy<{'arm64': 'y', 'arm64-qcom': '-'}> -CONFIG_RUST_PHYLIB_ABSTRACTIONS policy<{'arm64': 'y', 'arm64-qcom': '-'}> CONFIG_RZG2L_ADC policy<{'arm64': '-'}> CONFIG_RZG2L_THERMAL policy<{'arm64': '-'}> CONFIG_RZG3E_THERMAL policy<{'arm64': '-'}> @@ -2054,13 +1990,11 @@ CONFIG_RZ_DMAC policy<{'arm64': '-'}> CONFIG_RZ_MTU3 policy<{'arm64': '-'}> CONFIG_RZ_MTU3_CNT policy<{'arm64': '-'}> CONFIG_S32G_WDT policy<{'arm64': '-'}> -CONFIG_SAMPLES_RUST policy<{'arm64': 'n', 'arm64-qcom': '-'}> CONFIG_SAMPLE_CORESIGHT_SYSCFG policy<{'arm64': 'n'}> CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': '-'}> CONFIG_SATA_RCAR policy<{'arm64': '-'}> CONFIG_SC27XX_ADC policy<{'arm64': '-'}> -CONFIG_SCHED_DEBUG policy<{'arm64-qcom': '-'}> -CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ policy<{'arm64': 'y', 'arm64-qcom': 'm'}> +CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ policy<{'arm64': 'y'}> CONFIG_SCSI_UFS_AMD_VERSAL2 policy<{'arm64': '-'}> CONFIG_SCSI_UFS_HISI policy<{'arm64': '-'}> CONFIG_SCSI_UFS_MEDIATEK policy<{'arm64': '-'}> @@ -2559,7 +2493,6 @@ CONFIG_TI_SCI_PM_DOMAINS policy<{'arm64': '-'}> CONFIG_TI_SCI_PROTOCOL policy<{'arm64': '-'}> CONFIG_TI_SYSC policy<{'arm64': '-'}> CONFIG_TI_SYSCON_CLK policy<{'arm64': '-'}> -CONFIG_TOOLS_SUPPORT_RELR policy<{'arm64': 'y', 'arm64-qcom': '-'}> CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C policy<{'arm64': 'n'}> CONFIG_TOUCHSCREEN_SUN4I policy<{'arm64': '-'}> CONFIG_TOUCHSCREEN_TI_AM335X_TSC policy<{'arm64': '-'}> @@ -2622,7 +2555,6 @@ CONFIG_V4L2_ISP policy<{'arm64': '-'}> CONFIG_V4L2_JPEG_HELPER policy<{'arm64': '-'}> CONFIG_V4L2_VP9 policy<{'arm64': '-'}> CONFIG_VCPU_STALL_DETECTOR policy<{'arm64': 'y'}> -CONFIG_VERSION_SIGNATURE policy<{'arm64': '""', 'arm64-qcom': '"Ubuntu 7.0.0-1006.8-qcom 7.0.6"'}> CONFIG_VFIO_FSL_MC policy<{'arm64': '-'}> CONFIG_VHOST policy<{'arm64': 'y'}> CONFIG_VHOST_IOTLB policy<{'arm64': 'y'}> @@ -2704,12 +2636,7 @@ CONFIG_VIRTIO_VSOCKETS_COMMON policy<{'arm64': 'y'}> CONFIG_VISCONTI_WATCHDOG policy<{'arm64': '-'}> CONFIG_VMAP_PFN policy<{'arm64': '-'}> CONFIG_VSOCKETS policy<{'arm64': 'y'}> -CONFIG_VSOCKETS_DIAG policy<{'arm64': 'm', 'arm64-qcom': 'n'}> -CONFIG_VSOCKETS_LOOPBACK policy<{'arm64': 'm', 'arm64-qcom': 'n'}> CONFIG_W1_MASTER_MXC policy<{'arm64': '-'}> -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP policy<{'arm64': 'y', 'arm64-qcom': 'n'}> -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC policy<{'arm64': 'n', 'arm64-qcom': 'y'}> -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_WLAN_VENDOR_BCMDHD policy<{'arm64': '-'}> CONFIG_WQ_POWER_EFFICIENT_DEFAULT policy<{'arm64': 'n'}> CONFIG_XE_VFIO_PCI policy<{'arm64': '-'}> @@ -2719,7 +2646,6 @@ CONFIG_XGENE_SLIMPRO_MBOX policy<{'arm64': '-'}> CONFIG_XILINX_AMS policy<{'arm64': '-'}> CONFIG_XLNX_EVENT_MANAGER policy<{'arm64': '-'}> CONFIG_XLNX_R5_REMOTEPROC policy<{'arm64': '-'}> -CONFIG_ZRAM policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_ZYNQMP_FIRMWARE policy<{'arm64': '-'}> CONFIG_ZYNQMP_FIRMWARE_DEBUG policy<{'arm64': '-'}> CONFIG_ZYNQMP_IPI_MBOX policy<{'arm64': '-'}> From 5082713e1693e16b564b24d15185531665838809 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Mon, 6 Jul 2026 12:17:19 +0800 Subject: [PATCH 1242/1330] Synchronize with Qualcomm config Signed-off-by: Yushan Li (cherry picked from commit 384d076e3cc53f26f628e19871fb2f140598b02e) --- debian.qcom/config/annotations | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index ef7edbcfbee03..f08ef14fae2a5 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -18,6 +18,9 @@ CONFIG_ARCH_ROCKCHIP note<'LP: #1825222'> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': 'y'}> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT note<'LP: #2102032'> +CONFIG_CHR_DEV_SG policy<{'arm64': 'y', 'arm64-qcom': 'm'}> +CONFIG_CHR_DEV_SG note<'TODO: update note'> + CONFIG_DRM_AMDGPU_CIK policy<{'arm64': '-'}> CONFIG_DRM_AMDGPU_CIK note<'for zesty'> @@ -115,6 +118,7 @@ CONFIG_TOUCHSCREEN_APPLE_Z2 note<'TODO: update note'> # ---- Annotations without notes ---- CONFIG_AC97_BUS policy<{'arm64': 'y'}> +CONFIG_ACPI_AEST policy<{'arm64': 'n'}> CONFIG_ADI_AXI_ADC policy<{'arm64': '-'}> CONFIG_ADI_AXI_DAC policy<{'arm64': '-'}> CONFIG_AEST policy<{'arm64': 'y'}> @@ -268,6 +272,11 @@ CONFIG_ARM_TEGRA194_CPUFREQ policy<{'arm64': '-'}> CONFIG_ARM_TEGRA20_CPUFREQ policy<{'arm64': '-'}> CONFIG_ARM_TEGRA_DEVFREQ policy<{'arm64': '-'}> CONFIG_ARM_TI_CPUFREQ policy<{'arm64': '-'}> +CONFIG_ASYNC_CORE policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_ASYNC_MEMCPY policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_ASYNC_PQ policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_ASYNC_RAID6_RECOV policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_ASYNC_XOR policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_ATH10K_DFS_CERTIFIED policy<{'arm64': 'n'}> CONFIG_ATH11K_COREDUMP policy<{'arm64': '-'}> CONFIG_ATH5K_TEST_CHANNELS policy<{'arm64': 'n'}> @@ -321,6 +330,7 @@ CONFIG_CLK_ELIZA_DISPCC policy<{'arm64-qcom': 'y', 'arm6 CONFIG_CLK_ELIZA_GCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_ELIZA_TCSRCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> CONFIG_CLK_GLYMUR_CAMCC policy<{'arm64-qcom': 'y', 'arm64-qcom-rt': 'm'}> +CONFIG_CLK_GLYMUR_EVACC policy<{'arm64': 'm'}> CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_GPUCC policy<{'arm64': 'y'}> CONFIG_CLK_GLYMUR_VIDEOCC policy<{'arm64': 'y'}> @@ -389,6 +399,7 @@ CONFIG_CLK_RK3588 policy<{'arm64': '-'}> CONFIG_CLK_RV1126B policy<{'arm64': '-'}> CONFIG_CLK_RZG2L policy<{'arm64': '-'}> CONFIG_CLK_RZV2H policy<{'arm64': '-'}> +CONFIG_CLK_SHIKRA_AUDIOCORECC policy<{'arm64': 'm'}> CONFIG_CLK_SHIKRA_DISPCC policy<{'arm64': 'm'}> CONFIG_CLK_SHIKRA_GCC policy<{'arm64': 'y'}> CONFIG_CLK_SHIKRA_GPUCC policy<{'arm64': 'm'}> @@ -605,11 +616,14 @@ CONFIG_COMMON_RESET_HI3660 policy<{'arm64': '-'}> CONFIG_COMMON_RESET_HI6220 policy<{'arm64': '-'}> CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'arm64': '1', 'arm64-qcom-rt': '0'}> CONFIG_CORESIGHT policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_CATU policy<{'arm64-qcom': 'n'}> CONFIG_CORESIGHT_CPU_DEBUG policy<{'arm64': 'n'}> -CONFIG_CORESIGHT_CTI policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_CTCU policy<{'arm64-qcom': 'n'}> +CONFIG_CORESIGHT_CTI policy<{'arm64': 'n', 'arm64-qcom': 'm'}> +CONFIG_CORESIGHT_CTI_INTEGRATION_REGS policy<{'arm64-qcom': 'n'}> CONFIG_CORESIGHT_DUMMY policy<{'arm64': 'm'}> CONFIG_CORESIGHT_LINKS_AND_SINKS policy<{'arm64': 'm'}> -CONFIG_CORESIGHT_LINK_AND_SINK_TMC policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_LINK_AND_SINK_TMC policy<{'arm64': 'n', 'arm64-qcom': 'm'}> CONFIG_CORESIGHT_SINK_ETBV10 policy<{'arm64': 'n'}> CONFIG_CORESIGHT_SINK_TPIU policy<{'arm64': 'n'}> CONFIG_CORESIGHT_SOURCE_ETM4X policy<{'arm64': 'm'}> @@ -746,6 +760,7 @@ CONFIG_DRM_INNO_HDMI policy<{'arm64': '-'}> CONFIG_DRM_KMB_DISPLAY policy<{'arm64': '-'}> CONFIG_DRM_LOGICVC policy<{'arm64': 'n'}> CONFIG_DRM_LONTIUM_LT8713SX policy<{'arm64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611C policy<{'arm64': 'm'}> CONFIG_DRM_MEDIATEK policy<{'arm64': '-'}> CONFIG_DRM_MEDIATEK_DP policy<{'arm64': '-'}> CONFIG_DRM_MEDIATEK_HDMI policy<{'arm64': '-'}> @@ -1165,6 +1180,10 @@ CONFIG_MDIO_BUS_MUX_MESON_G12A policy<{'arm64': '-'}> CONFIG_MDIO_BUS_MUX_MESON_GXL policy<{'arm64': '-'}> CONFIG_MDIO_SUN4I policy<{'arm64': '-'}> CONFIG_MDIO_XGENE policy<{'arm64': '-'}> +CONFIG_MD_RAID0 policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_MD_RAID1 policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_MD_RAID10 policy<{'arm64': 'm', 'arm64-qcom': 'y'}> +CONFIG_MD_RAID456 policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_MEDIATEK_2P5GE_PHY policy<{'arm64': '-'}> CONFIG_MEDIATEK_GE_SOC_PHY policy<{'arm64': 'n'}> CONFIG_MEDIATEK_MT6577_AUXADC policy<{'arm64': '-'}> @@ -1371,6 +1390,7 @@ CONFIG_NVMEM_ZYNQMP policy<{'arm64': '-'}> CONFIG_NVME_APPLE policy<{'arm64': '-'}> CONFIG_NXP_SAR_ADC policy<{'arm64': '-'}> CONFIG_NXP_STM_TIMER policy<{'arm64': '-'}> +CONFIG_OF_AEST policy<{'arm64': 'n'}> CONFIG_OLPC_EC policy<{'arm64': '-'}> CONFIG_OLPC_XO175 policy<{'arm64': '-'}> CONFIG_OLPC_XO175_EC policy<{'arm64': '-'}> @@ -1785,6 +1805,7 @@ CONFIG_QCOM_APR policy<{'arm64': 'y'}> CONFIG_QCOM_BAM_DMA policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_APCC_MSM8996 policy<{'arm64': 'y'}> CONFIG_QCOM_CLK_APCS_MSM8916 policy<{'arm64': 'y'}> +CONFIG_QCOM_CLK_GP_MND policy<{'arm64': 'n'}> CONFIG_QCOM_CLK_SMD_RPM policy<{'arm64': 'y'}> CONFIG_QCOM_CPR policy<{'arm64': 'y'}> CONFIG_QCOM_CPUCP_MBOX policy<{'arm64': 'y'}> @@ -1833,6 +1854,7 @@ CONFIG_QCOM_SMP2P policy<{'arm64': 'y'}> CONFIG_QCOM_SMP2P_SLEEPSTATE policy<{'arm64': '-'}> CONFIG_QCOM_SMSM policy<{'arm64': 'y'}> CONFIG_QCOM_SOC_DEBUG policy<{'arm64': '-'}> +CONFIG_QCOM_SPEL policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_ADC5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_ADC_TM5_GEN3 policy<{'arm64': 'm'}> CONFIG_QCOM_SPMI_MBG_TM policy<{'arm64': '-'}> @@ -1852,6 +1874,7 @@ CONFIG_QTI_BCL_PMIC5 policy<{'arm64': '-'}> CONFIG_QTI_DEVFREQ_CDEV policy<{'arm64': '-'}> CONFIG_QTI_TZ_LOG policy<{'arm64': '-'}> CONFIG_QUEUED_RWLOCKS policy<{'arm64': 'y', 'arm64-qcom-rt': '-'}> +CONFIG_RAID6_PQ policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_RAVB policy<{'arm64': '-'}> CONFIG_RCAR_DMAC policy<{'arm64': '-'}> CONFIG_RCAR_GEN3_THERMAL policy<{'arm64': '-'}> @@ -2646,6 +2669,7 @@ CONFIG_XGENE_SLIMPRO_MBOX policy<{'arm64': '-'}> CONFIG_XILINX_AMS policy<{'arm64': '-'}> CONFIG_XLNX_EVENT_MANAGER policy<{'arm64': '-'}> CONFIG_XLNX_R5_REMOTEPROC policy<{'arm64': '-'}> +CONFIG_XOR_BLOCKS policy<{'arm64': 'm', 'arm64-qcom': 'y'}> CONFIG_ZYNQMP_FIRMWARE policy<{'arm64': '-'}> CONFIG_ZYNQMP_FIRMWARE_DEBUG policy<{'arm64': '-'}> CONFIG_ZYNQMP_IPI_MBOX policy<{'arm64': '-'}> From 1b612f397133e90f8603c144d91a5083eda9eca7 Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Tue, 7 Jul 2026 17:48:48 +0800 Subject: [PATCH 1243/1330] FROMLIST: wifi: ath12k: change MAC buffer ring size to 4096 For WCN7850, MAC buffer ring size is updated to 2048 in 955df16f2a4c3 ("wifi: ath12k: change MAC buffer ring size to 2048") to increase peak throughput. But during the RX process, a phenomenon can still be observed where the throughput drops by about 30% from its peak value and then recovers, and this behavior repeats during RX. After increasing MAC buffer ring size to 4096, the data rate drop has gone. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Link: https://lore.kernel.org/all/20260610031358.2043716-1-yingying.tang@oss.qualcomm.com/ Signed-off-by: Yingying Tang (cherry picked from commit 1aa936434ae6d02dabfe3569b81ec5457e74ed8c) --- drivers/net/wireless/ath/ath12k/dp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath12k/dp.h b/drivers/net/wireless/ath/ath12k/dp.h index f8cfc7bb29dd7..6596089d41688 100644 --- a/drivers/net/wireless/ath/ath12k/dp.h +++ b/drivers/net/wireless/ath/ath12k/dp.h @@ -205,7 +205,7 @@ struct ath12k_pdev_dp { #define DP_REO_CMD_RING_SIZE 256 #define DP_REO_STATUS_RING_SIZE 2048 #define DP_RXDMA_BUF_RING_SIZE 4096 -#define DP_RX_MAC_BUF_RING_SIZE 2048 +#define DP_RX_MAC_BUF_RING_SIZE 4096 #define DP_RXDMA_REFILL_RING_SIZE 2048 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 From 9391c1594522c4e2aba2abd10237d15beb953ec5 Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Tue, 7 Jul 2026 17:48:48 +0800 Subject: [PATCH 1244/1330] FROMLIST: wifi: ath12k: Fix low MLO RX throughput on WCN7850 Commit [1] introduced a regression causing severely degraded MLO RX throughput on WCN7850. On WCN7850, there is only a single ar instance, but MLO uses two link IDs. ath12k_dp_peer->hw_links[] is indexed using ar->hw_link_id, which causes both MLO link IDs to be stored at the same index. As a result, an incorrect link ID is assigned to MSDUs in ath12k_dp_rx_deliver_msdu(), leading to severe MLO RX throughput loss. Different chipsets identify the per-MSDU link differently: - On QCN9274 / IPQ5332, the host owns multiple ar instances and the per-MSDU hw_link_id from the RX descriptor maps cleanly through dp_peer->hw_links[hw_link_id] to the IEEE link_id. - On single-ar chipsets like WCN7850 / QCC2072, there is only one ar instance for both MLO links, so dp_peer->hw_links[] has just one valid slot and cannot be used to distinguish the two links. To resolve the link, walk dp_peer->link_peers[] and match by rxcb->peer_id, which on the link_peer side identifies the link peer for the MSDU. Add a new hw_op set_rx_link_id() so each chipset resolves the link on the RX fast path using whatever signal it actually has, and let the op itself decide whether to populate rx_status::link_valid and rx_status::link_id: QCN9274 / IPQ5332 : always derive link_id from dp_peer->hw_links[rxcb->hw_link_id] and set link_valid. WCN7850 / QCC2072 : walk the link_peers[] of dp_peer to find the link_peer whose peer_id matches rxcb->peer_id, and set link_valid only when a match is found. Otherwise leave link_valid clear so that mac80211 can fall back to its own link resolution path (via addr2 / deflink). For WCN7850 / QCC2072, walking dp_peer->link_peers[] is bounded by the number of links actually populated, so introduce a link_peers_map bitmap (unsigned long) in struct ath12k_dp_peer that tracks populated slots and use for_each_set_bit() to iterate. Non-MLO clients hit one slot, current MLO clients hit two; the full ATH12K_NUM_MAX_LINKS array is never scanned. The bitmap is maintained with WRITE_ONCE() on the write side (under dp_hw->peer_lock) paired with READ_ONCE() on both the lockless RX read side and the write-side RMW for KCSAN correctness. Also guard the dp_peer dereference in ath12k_mac_peer_cleanup_all() with a NULL check, since peer->dp_peer can be NULL for self-peers or peers not yet fully assigned, the pre-existing rcu_assign_pointer() call there had the same latent issue. This restores the correct link ID on WCN7850 without changing the QCN9274 / IPQ5332 data path, which keeps its O(1) hw_links[] indexing. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Link: https://lore.kernel.org/all/20260610053315.2249912-1-yingying.tang@oss.qualcomm.com/ Fixes: 11157e0910fd ("wifi: ath12k: Use ath12k_dp_peer in per packet Tx & Rx paths") # [1] Signed-off-by: Yingying Tang (cherry picked from commit aa6f9d56653c998f0ad7066dea069f5648a2f413) --- drivers/net/wireless/ath/ath12k/dp_peer.c | 4 +++ drivers/net/wireless/ath/ath12k/dp_peer.h | 1 + drivers/net/wireless/ath/ath12k/dp_rx.c | 7 ++-- drivers/net/wireless/ath/ath12k/hw.h | 16 +++++++++ drivers/net/wireless/ath/ath12k/mac.c | 10 ++++-- drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c | 33 +++++++++++++++++++ drivers/net/wireless/ath/ath12k/wifi7/dp_rx.h | 6 ++++ drivers/net/wireless/ath/ath12k/wifi7/hw.c | 3 ++ 8 files changed, 73 insertions(+), 7 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/dp_peer.c b/drivers/net/wireless/ath/ath12k/dp_peer.c index 47d009a0d61fe..2660b4c7449be 100644 --- a/drivers/net/wireless/ath/ath12k/dp_peer.c +++ b/drivers/net/wireless/ath/ath12k/dp_peer.c @@ -570,6 +570,8 @@ int ath12k_dp_link_peer_assign(struct ath12k_dp *dp, struct ath12k_dp_hw *dp_hw, peerid_index = ath12k_dp_peer_get_peerid_index(dp, peer->peer_id); rcu_assign_pointer(dp_peer->link_peers[peer->link_id], peer); + WRITE_ONCE(dp_peer->link_peers_map, + READ_ONCE(dp_peer->link_peers_map) | BIT(peer->link_id)); rcu_assign_pointer(dp_hw->dp_peers[peerid_index], dp_peer); @@ -632,6 +634,8 @@ void ath12k_dp_link_peer_unassign(struct ath12k_dp *dp, struct ath12k_dp_hw *dp_ peerid_index = ath12k_dp_peer_get_peerid_index(dp, peer->peer_id); rcu_assign_pointer(dp_peer->link_peers[peer->link_id], NULL); + WRITE_ONCE(dp_peer->link_peers_map, + READ_ONCE(dp_peer->link_peers_map) & ~BIT(peer->link_id)); rcu_assign_pointer(dp_hw->dp_peers[peerid_index], NULL); diff --git a/drivers/net/wireless/ath/ath12k/dp_peer.h b/drivers/net/wireless/ath/ath12k/dp_peer.h index 20294ff095131..3011cf71840fb 100644 --- a/drivers/net/wireless/ath/ath12k/dp_peer.h +++ b/drivers/net/wireless/ath/ath12k/dp_peer.h @@ -141,6 +141,7 @@ struct ath12k_dp_peer { /* Info used in MMIC verification of * RX fragments */ struct crypto_shash *tfm_mmic; struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; + unsigned long link_peers_map; struct ath12k_dp_link_peer __rcu *link_peers[ATH12K_NUM_MAX_LINKS]; struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1]; struct ath12k_dp_rx_tid rx_tid[IEEE80211_NUM_TIDS + 1]; diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.c b/drivers/net/wireless/ath/ath12k/dp_rx.c index 01a45ec88b4b8..f3c641cf93f37 100644 --- a/drivers/net/wireless/ath/ath12k/dp_rx.c +++ b/drivers/net/wireless/ath/ath12k/dp_rx.c @@ -1351,10 +1351,9 @@ void ath12k_dp_rx_deliver_msdu(struct ath12k_pdev_dp *dp_pdev, struct napi_struc pubsta = peer ? peer->sta : NULL; - if (pubsta && pubsta->valid_links) { - status->link_valid = 1; - status->link_id = peer->hw_links[rxcb->hw_link_id]; - } + status->link_valid = 0; + if (pubsta && pubsta->valid_links) + ath12k_hw_set_rx_link_id(dp->hw_params, peer, rxcb, status); ath12k_dbg(dp->ab, ATH12K_DBG_DATA, "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", diff --git a/drivers/net/wireless/ath/ath12k/hw.h b/drivers/net/wireless/ath/ath12k/hw.h index a9888e0521a1d..da75d19ae1a00 100644 --- a/drivers/net/wireless/ath/ath12k/hw.h +++ b/drivers/net/wireless/ath/ath12k/hw.h @@ -13,6 +13,10 @@ #include "wmi.h" #include "hal.h" +struct ath12k_dp_peer; +struct ath12k_skb_rxcb; +struct ieee80211_rx_status; + /* Target configuration defines */ /* Num VDEVS per radio */ @@ -224,6 +228,9 @@ struct ath12k_hw_ops { bool (*dp_srng_is_tx_comp_ring)(int ring_num); bool (*is_frame_link_agnostic)(struct ath12k_link_vif *arvif, struct ieee80211_mgmt *mgmt); + void (*set_rx_link_id)(struct ath12k_dp_peer *dp_peer, + struct ath12k_skb_rxcb *rxcb, + struct ieee80211_rx_status *status); }; static inline @@ -254,6 +261,15 @@ static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw, return 0; } +static inline void ath12k_hw_set_rx_link_id(const struct ath12k_hw_params *hw, + struct ath12k_dp_peer *dp_peer, + struct ath12k_skb_rxcb *rxcb, + struct ieee80211_rx_status *status) +{ + if (hw->hw_ops->set_rx_link_id) + hw->hw_ops->set_rx_link_id(dp_peer, rxcb, status); +} + struct ath12k_fw_ie { __le32 id; __le32 len; diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c index ba0681a94c14e..ed27c55baa4d1 100644 --- a/drivers/net/wireless/ath/ath12k/mac.c +++ b/drivers/net/wireless/ath/ath12k/mac.c @@ -1238,9 +1238,13 @@ void ath12k_mac_peer_cleanup_all(struct ath12k *ar) /* cleanup dp peer */ spin_lock_bh(&dp_hw->peer_lock); dp_peer = peer->dp_peer; - peerid_index = ath12k_dp_peer_get_peerid_index(dp, peer->peer_id); - rcu_assign_pointer(dp_peer->link_peers[peer->link_id], NULL); - rcu_assign_pointer(dp_hw->dp_peers[peerid_index], NULL); + if (dp_peer) { + peerid_index = ath12k_dp_peer_get_peerid_index(dp, peer->peer_id); + rcu_assign_pointer(dp_peer->link_peers[peer->link_id], NULL); + WRITE_ONCE(dp_peer->link_peers_map, + READ_ONCE(dp_peer->link_peers_map) & ~BIT(peer->link_id)); + rcu_assign_pointer(dp_hw->dp_peers[peerid_index], NULL); + } spin_unlock_bh(&dp_hw->peer_lock); ath12k_dp_link_peer_rhash_delete(dp, peer); diff --git a/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c b/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c index 1e280234b9412..3766a2a13c2d3 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c @@ -5,6 +5,7 @@ */ #include "dp_rx.h" +#include "../dp_peer.h" #include "../dp_tx.h" #include "../peer.h" #include "hal_qcn9274.h" @@ -2246,3 +2247,35 @@ ath12k_wifi7_dp_rxdesc_mpdu_valid(struct ath12k_base *ab, return tlv_tag == HAL_RX_MPDU_START; } + +void +ath12k_wifi7_dp_rx_set_link_id_qcn9274(struct ath12k_dp_peer *dp_peer, + struct ath12k_skb_rxcb *rxcb, + struct ieee80211_rx_status *status) +{ + status->link_valid = 1; + status->link_id = dp_peer->hw_links[rxcb->hw_link_id]; +} + +void +ath12k_wifi7_dp_rx_set_link_id_wcn7850(struct ath12k_dp_peer *dp_peer, + struct ath12k_skb_rxcb *rxcb, + struct ieee80211_rx_status *status) +{ + struct ath12k_dp_link_peer *link_peer; + unsigned long links_map; + int i; + + RCU_LOCKDEP_WARN(!rcu_read_lock_held(), + "ath12k set rx link id called without rcu lock"); + + links_map = READ_ONCE(dp_peer->link_peers_map); + for_each_set_bit(i, &links_map, ATH12K_NUM_MAX_LINKS) { + link_peer = rcu_dereference(dp_peer->link_peers[i]); + if (link_peer && link_peer->peer_id == rxcb->peer_id) { + status->link_valid = 1; + status->link_id = link_peer->link_id; + return; + } + } +} diff --git a/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.h b/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.h index 8aa79faf567fd..1d3a4788a2dd9 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.h +++ b/drivers/net/wireless/ath/ath12k/wifi7/dp_rx.h @@ -57,4 +57,10 @@ ath12k_wifi7_dp_rxdesc_mpdu_valid(struct ath12k_base *ab, struct hal_rx_desc *rx_desc); int ath12k_wifi7_dp_rx_tid_delete_handler(struct ath12k_base *ab, struct ath12k_dp_rx_tid_rxq *rx_tid); +void ath12k_wifi7_dp_rx_set_link_id_qcn9274(struct ath12k_dp_peer *dp_peer, + struct ath12k_skb_rxcb *rxcb, + struct ieee80211_rx_status *status); +void ath12k_wifi7_dp_rx_set_link_id_wcn7850(struct ath12k_dp_peer *dp_peer, + struct ath12k_skb_rxcb *rxcb, + struct ieee80211_rx_status *status); #endif diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hw.c b/drivers/net/wireless/ath/ath12k/wifi7/hw.c index df045ddf42da9..094e5495976d7 100644 --- a/drivers/net/wireless/ath/ath12k/wifi7/hw.c +++ b/drivers/net/wireless/ath/ath12k/wifi7/hw.c @@ -158,6 +158,7 @@ static const struct ath12k_hw_ops qcn9274_ops = { .get_ring_selector = ath12k_wifi7_hw_get_ring_selector_qcn9274, .dp_srng_is_tx_comp_ring = ath12k_wifi7_dp_srng_is_comp_ring_qcn9274, .is_frame_link_agnostic = ath12k_wifi7_is_frame_link_agnostic_qcn9274, + .set_rx_link_id = ath12k_wifi7_dp_rx_set_link_id_qcn9274, }; static const struct ath12k_hw_ops wcn7850_ops = { @@ -168,6 +169,7 @@ static const struct ath12k_hw_ops wcn7850_ops = { .get_ring_selector = ath12k_wifi7_hw_get_ring_selector_wcn7850, .dp_srng_is_tx_comp_ring = ath12k_wifi7_dp_srng_is_comp_ring_wcn7850, .is_frame_link_agnostic = ath12k_wifi7_is_frame_link_agnostic_wcn7850, + .set_rx_link_id = ath12k_wifi7_dp_rx_set_link_id_wcn7850, }; static const struct ath12k_hw_ops qcc2072_ops = { @@ -178,6 +180,7 @@ static const struct ath12k_hw_ops qcc2072_ops = { .get_ring_selector = ath12k_wifi7_hw_get_ring_selector_wcn7850, .dp_srng_is_tx_comp_ring = ath12k_wifi7_dp_srng_is_comp_ring_wcn7850, .is_frame_link_agnostic = ath12k_wifi7_is_frame_link_agnostic_wcn7850, + .set_rx_link_id = ath12k_wifi7_dp_rx_set_link_id_wcn7850, }; #define ATH12K_TX_RING_MASK_0 0x1 From 2d261b79f07810043fa114f154ef524be70bf8ad Mon Sep 17 00:00:00 2001 From: Baochen Qiang Date: Tue, 7 Jul 2026 17:48:48 +0800 Subject: [PATCH 1245/1330] FROMLIST: wifi: ath12k: fix EAPOL TX failure caused by stale tcl_metadata bits On WCN7850, after the following sequence: 1. load ath12k and connect to a non-MLO AP 2. disconnect and connect to an MLO AP 3. disconnect and reconnect to the non-MLO AP the third connection always fails with a 4-Way handshake timeout. The supplicant transmits message 2 of 4 four times in response to AP retries of message 1, but the AP never sees any of them. ath12k_dp_vdev_tx_attach() composes dp_link_vif->tcl_metadata using |=, but dp_link_vif is embedded in struct ath12k_dp_vif and its slots are reused across vif/peer teardown and setup. Since tcl_metadata is never cleared on detach, vdev_id bits from a previous attach remain set when the same link slot is reused with a different vdev_id. In this specific issue, the same link slot is used for vdev_id 0, then vdev_id 1, then vdev_id 0 again, the OR yields tcl_metadata == 0x9, which encodes vdev_id 1 in the HTT_TCL_META_DATA_VDEV_ID field even though ti.vdev_id is 0. Firmware then routes the EAPOL frame to the wrong vdev and the AP never receives message 2. Use plain assignment instead of |= so the field is fully recomputed from the current arvif on every attach. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c7-00108-QCAHMTSWPL_V1.0_V2.0_SILICONZ_UPSTREAM-3 Fixes: af66c7640cf9 ("wifi: ath12k: Refactor ath12k_vif structure") Link: https://lore.kernel.org/all/20260609-ath12k-fix-eapol-tcl-metadata-v1-1-d47e6f90d4ee@oss.qualcomm.com/ Signed-off-by: Baochen Qiang Signed-off-by: Yingying Tang (cherry picked from commit b43add1787d8a41058aaa07c3da687bb309f7d88) --- drivers/net/wireless/ath/ath12k/dp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/dp.c b/drivers/net/wireless/ath/ath12k/dp.c index 1c82d927d27b2..841de7cbfd8c7 100644 --- a/drivers/net/wireless/ath/ath12k/dp.c +++ b/drivers/net/wireless/ath/ath12k/dp.c @@ -945,11 +945,11 @@ void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif) dp_link_vif = ath12k_dp_vif_to_dp_link_vif(&ahvif->dp_vif, link_id); - dp_link_vif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) | - u32_encode_bits(arvif->vdev_id, - HTT_TCL_META_DATA_VDEV_ID) | - u32_encode_bits(ar->pdev->pdev_id, - HTT_TCL_META_DATA_PDEV_ID); + dp_link_vif->tcl_metadata = u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) | + u32_encode_bits(arvif->vdev_id, + HTT_TCL_META_DATA_VDEV_ID) | + u32_encode_bits(ar->pdev->pdev_id, + HTT_TCL_META_DATA_PDEV_ID); /* set HTT extension valid bit to 0 by default */ dp_link_vif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT; From e41692278c46a22d7a68fea5aef33cd1e422ef4c Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Tue, 7 Jul 2026 17:52:01 +0800 Subject: [PATCH 1246/1330] FROMLIST: Revert "wifi: ath12k: add panic handler" This reverts commit 809055628bce824b7fe18331abb65e44d02b0ecf. Call trace: rcu_note_context_switch+0x4c4/0x508 (P) __schedule+0xbc/0x1204 schedule+0x34/0x110 schedule_timeout+0x84/0x11c __mhi_device_get_sync+0x164/0x228 [mhi] mhi_device_get_sync+0x1c/0x3c [mhi] ath12k_wifi7_pci_bus_wake_up+0x20/0x2c [ath12k_wifi7] ath12k_pci_read32+0x58/0x350 [ath12k] ath12k_pci_clear_dbg_registers+0x28/0xb8 [ath12k] ath12k_pci_panic_handler+0x20/0x44 [ath12k] ath12k_core_panic_handler+0x28/0x3c [ath12k] notifier_call_chain+0x78/0x1c0 atomic_notifier_call_chain+0x3c/0x5c ath12k_core_panic_handler() is invoked via atomic_notifier_call_chain(), which runs inside an RCU read-side critical section. The current code calls ath12k_pci_sw_reset() synchronously from this context, which eventually reaches mhi_device_get_sync() and schedule_timeout(), triggering a voluntary context switch within RCU. Revert change "wifi: ath12k: add panic handler" to avoid this issue. Tested-on: WLAN.HMT.1.1.c7-00108-QCAHMTSWPL_V1.0_V2.0_SILICONZ_UPSTREAM-3 Link: https://lore.kernel.org/all/20260612032332.2278338-1-yingying.tang@oss.qualcomm.com/ Signed-off-by: Yingying Tang (cherry picked from commit 3f2ef969a148a9a725abda7a753b623ae749ceb0) --- drivers/net/wireless/ath/ath12k/core.c | 35 +------------------------- drivers/net/wireless/ath/ath12k/core.h | 3 --- drivers/net/wireless/ath/ath12k/hif.h | 9 ------- drivers/net/wireless/ath/ath12k/pci.c | 8 ------ 4 files changed, 1 insertion(+), 54 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/ath/ath12k/core.c index e86dcc6ddbb86..2b6c8aa65dd54 100644 --- a/drivers/net/wireless/ath/ath12k/core.c +++ b/drivers/net/wireless/ath/ath12k/core.c @@ -1764,31 +1764,6 @@ int ath12k_core_pre_init(struct ath12k_base *ab) return 0; } -static int ath12k_core_panic_handler(struct notifier_block *nb, - unsigned long action, void *data) -{ - struct ath12k_base *ab = container_of(nb, struct ath12k_base, - panic_nb); - - set_bit(ATH12K_FLAG_PANIC_PROCESSING, &ab->dev_flags); - - return ath12k_hif_panic_handler(ab); -} - -static int ath12k_core_panic_notifier_register(struct ath12k_base *ab) -{ - ab->panic_nb.notifier_call = ath12k_core_panic_handler; - - return atomic_notifier_chain_register(&panic_notifier_list, - &ab->panic_nb); -} - -static void ath12k_core_panic_notifier_unregister(struct ath12k_base *ab) -{ - atomic_notifier_chain_unregister(&panic_notifier_list, - &ab->panic_nb); -} - static inline bool ath12k_core_hw_group_create_ready(struct ath12k_hw_group *ag) { @@ -2185,18 +2160,13 @@ int ath12k_core_init(struct ath12k_base *ab) struct ath12k_hw_group *ag; int ret; - ret = ath12k_core_panic_notifier_register(ab); - if (ret) - ath12k_warn(ab, "failed to register panic handler: %d\n", ret); - mutex_lock(&ath12k_hw_group_mutex); ag = ath12k_core_hw_group_assign(ab); if (!ag) { mutex_unlock(&ath12k_hw_group_mutex); ath12k_warn(ab, "unable to get hw group\n"); - ret = -ENODEV; - goto err_unregister_notifier; + return -ENODEV; } mutex_unlock(&ath12k_hw_group_mutex); @@ -2221,8 +2191,6 @@ int ath12k_core_init(struct ath12k_base *ab) err_unassign_hw_group: ath12k_core_hw_group_unassign(ab); -err_unregister_notifier: - ath12k_core_panic_notifier_unregister(ab); return ret; } @@ -2231,7 +2199,6 @@ void ath12k_core_deinit(struct ath12k_base *ab) { ath12k_core_hw_group_destroy(ab->ag); ath12k_core_hw_group_unassign(ab); - ath12k_core_panic_notifier_unregister(ab); } void ath12k_core_free(struct ath12k_base *ab) diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h index f3fe9565d4767..765b855f7e85a 100644 --- a/drivers/net/wireless/ath/ath12k/core.h +++ b/drivers/net/wireless/ath/ath12k/core.h @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -1116,8 +1115,6 @@ struct ath12k_base { #endif /* CONFIG_ACPI */ - struct notifier_block panic_nb; - struct ath12k_hw_group *ag; struct ath12k_wsi_info wsi_info; enum ath12k_firmware_mode fw_mode; diff --git a/drivers/net/wireless/ath/ath12k/hif.h b/drivers/net/wireless/ath/ath12k/hif.h index e8840fab6061c..42bb00c13ef3d 100644 --- a/drivers/net/wireless/ath/ath12k/hif.h +++ b/drivers/net/wireless/ath/ath12k/hif.h @@ -30,7 +30,6 @@ struct ath12k_hif_ops { void (*ce_irq_enable)(struct ath12k_base *ab); void (*ce_irq_disable)(struct ath12k_base *ab); void (*get_ce_msi_idx)(struct ath12k_base *ab, u32 ce_id, u32 *msi_idx); - int (*panic_handler)(struct ath12k_base *ab); void (*coredump_download)(struct ath12k_base *ab); }; @@ -149,14 +148,6 @@ static inline void ath12k_hif_power_down(struct ath12k_base *ab, bool is_suspend ab->hif.ops->power_down(ab, is_suspend); } -static inline int ath12k_hif_panic_handler(struct ath12k_base *ab) -{ - if (!ab->hif.ops->panic_handler) - return NOTIFY_DONE; - - return ab->hif.ops->panic_handler(ab); -} - static inline void ath12k_hif_coredump_download(struct ath12k_base *ab) { if (ab->hif.ops->coredump_download) diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c index 3a61ace00db9c..5e7c80d912bde 100644 --- a/drivers/net/wireless/ath/ath12k/pci.c +++ b/drivers/net/wireless/ath/ath12k/pci.c @@ -1480,13 +1480,6 @@ void ath12k_pci_power_down(struct ath12k_base *ab, bool is_suspend) ath12k_pci_sw_reset(ab_pci->ab, false); } -static int ath12k_pci_panic_handler(struct ath12k_base *ab) -{ - ath12k_pci_sw_reset(ab, false); - - return NOTIFY_OK; -} - static const struct ath12k_hif_ops ath12k_pci_hif_ops = { .start = ath12k_pci_start, .stop = ath12k_pci_stop, @@ -1504,7 +1497,6 @@ static const struct ath12k_hif_ops ath12k_pci_hif_ops = { .ce_irq_enable = ath12k_pci_hif_ce_irq_enable, .ce_irq_disable = ath12k_pci_hif_ce_irq_disable, .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx, - .panic_handler = ath12k_pci_panic_handler, #ifdef CONFIG_ATH12K_COREDUMP .coredump_download = ath12k_pci_coredump_download, #endif From dfdb8800398b7ef410753da5465e3ea62a758a54 Mon Sep 17 00:00:00 2001 From: Anvesh Jain P Date: Fri, 3 Jul 2026 15:23:41 +0530 Subject: [PATCH 1247/1330] FROMLIST: dt-bindings: embedded-controller: qcom,hamoa-crd-ec: Add Purwa IOT EVK Document the qcom,purwa-iot-evk-ec compatible for the embedded controller found on Purwa IOT EVK boards. Like the CRD, the Purwa IOT EVK carries an on-board embedded controller, provided by ITE and running on a separate MCU, which handles fan control, temperature sensors and EC state-change/suspend notifications. The existing Hamoa IOT EVK documents the same EC via qcom,hamoa-iot-evk-ec. Like the other reference designs, it uses qcom,hamoa-crd-ec as its fallback compatible. Link: https://lore.kernel.org/all/20260703-ec_support_for_purwa_evk-v2-1-c59aac5c6aac@oss.qualcomm.com/ Signed-off-by: Anvesh Jain P (cherry picked from commit 8428b64d1d1f41fe08763eaac53e0e0100a0e7c1) --- .../bindings/embedded-controller/qcom,hamoa-crd-ec.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml index ac5a08f8f76df..c07483aa59370 100644 --- a/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml @@ -22,6 +22,7 @@ properties: - enum: - qcom,glymur-crd-ec - qcom,hamoa-iot-evk-ec + - qcom,purwa-iot-evk-ec - const: qcom,hamoa-crd-ec - enum: - qcom,hamoa-crd-ec From 1d96a5037df4557a7acf524a00171873054333b6 Mon Sep 17 00:00:00 2001 From: Anvesh Jain P Date: Fri, 3 Jul 2026 15:23:42 +0530 Subject: [PATCH 1248/1330] FROMLIST: arm64: dts: qcom: purwa-iot-evk: Add Embedded controller node Add embedded controller node for Purwa IOT EVK boards which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/all/20260703-ec_support_for_purwa_evk-v2-2-c59aac5c6aac@oss.qualcomm.com/ Tested-by: Yushan Li Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Anvesh Jain P (cherry picked from commit 78fe705e66c87605592481f2006f5ebf7b8b7009) --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index dca57f2db1fe1..430bb2958f406 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -857,6 +857,16 @@ pinctrl-0 = <&eusb6_reset_n>; pinctrl-names = "default"; }; + + embedded-controller@76 { + compatible = "qcom,purwa-iot-evk-ec", "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; }; &i2c7 { @@ -1346,6 +1356,12 @@ }; &tlmm { + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From f510e504e7845c74417ca072fe3c3c570d0df2d5 Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Tue, 14 Jul 2026 13:00:20 +0530 Subject: [PATCH 1249/1330] PENDING: arm64: dts: enable iris driver for hamoa kvm Add video firmware node to enable video kvm on the hamoa. Signed-off-by: Renjiang Han (cherry picked from commit c7f74526185c95d50be120e3aae600c4b146dfda) --- arch/arm64/boot/dts/qcom/x1-el2.dtso | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index ee006742d6f3b..8bbe5e61402b0 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -17,8 +17,10 @@ }; &iris { - /* TODO: Add video-firmware iommus to start IRIS from EL2 */ - status = "disabled"; + status = "okay"; + video-firmware { + iommus = <&apps_smmu 0x1942 0x0>; + }; }; /* From bafd95869e37faa3b7dd4b1b12dcc872c6776641 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Mon, 13 Jul 2026 23:04:34 +0530 Subject: [PATCH 1250/1330] FROMLIST: scsi: ufs: ufs-qcom: Enable only lane clocks in lane clock APIs ufs_qcom_enable_lane_clks() and ufs_qcom_disable_lane_clks() currently use clk_bulk_prepare_enable()/clk_bulk_disable_unprepare() on the entire host->clks array obtained from devm_clk_bulk_get_all(). This array contains all device clocks, not just lane symbol clocks. Since the UFS core framework already manages the non-lane clocks via the setup_clocks callback, the bulk enable/disable in the lane clock APIs resulted in duplicate reference count increments on those shared clocks. The extra enable counts were never balanced by a corresponding disable from the framework's clock gating path, preventing the clock reference counts from reaching zero and ultimately blocking CXO shutdown during low-power states. Fix this by restricting the lane clock APIs to only prepare/enable and disable/unprepare the three lane symbol clocks (tx_lane0_sync_clk, rx_lane0_sync_clk, rx_lane1_sync_clk), leaving the handling of all other clocks to the UFS core framewore. Link: https://lore.kernel.org/linux-scsi/20260713173434.883386-1-nitin.rawat@oss.qualcomm.com/ Signed-off-by: Nitin Rawat Signed-off-by: Pradeep P V K (cherry picked from commit 2e93b3bcfad39771161f0eb0ace38dd2976997d6) --- drivers/ufs/host/ufs-qcom.c | 41 ++++++++++++++++++++++++++++++++----- drivers/ufs/host/ufs-qcom.h | 3 +++ 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index f1a19d6a3913a..92988c5bae4df 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -362,7 +362,9 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) if (!host->is_lane_clks_enabled) return; - clk_bulk_disable_unprepare(host->num_clks, host->clks); + clk_disable_unprepare(host->rx_lane1_sync_clk); + clk_disable_unprepare(host->rx_lane0_sync_clk); + clk_disable_unprepare(host->tx_lane0_sync_clk); host->is_lane_clks_enabled = false; } @@ -371,18 +373,35 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) { int err; - err = clk_bulk_prepare_enable(host->num_clks, host->clks); + if (host->is_lane_clks_enabled) + return 0; + + err = clk_prepare_enable(host->tx_lane0_sync_clk); if (err) - return err; + goto out; - host->is_lane_clks_enabled = true; + err = clk_prepare_enable(host->rx_lane0_sync_clk); + if (err) + goto out_disable_tx_lane0; + + err = clk_prepare_enable(host->rx_lane1_sync_clk); + if (err) + goto out_disable_rx_lane0; + host->is_lane_clks_enabled = true; return 0; + +out_disable_rx_lane0: + clk_disable_unprepare(host->rx_lane0_sync_clk); +out_disable_tx_lane0: + clk_disable_unprepare(host->tx_lane0_sync_clk); +out: + return err; } static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) { - int err; + int err, i; struct device *dev = host->hba->dev; if (has_acpi_companion(dev)) @@ -394,6 +413,18 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) host->num_clks = err; + for (i = 0; i < host->num_clks; i++) { + if (!host->clks[i].id) + continue; + if (!strcmp(host->clks[i].id, "tx_lane0_sync_clk")) + host->tx_lane0_sync_clk = host->clks[i].clk; + else if (!strcmp(host->clks[i].id, "rx_lane0_sync_clk")) + host->rx_lane0_sync_clk = host->clks[i].clk; + else if (!strcmp(host->clks[i].id, "rx_lane1_sync_clk")) + if (host->hba->lanes_per_direction > 1) + host->rx_lane1_sync_clk = host->clks[i].clk; + } + return 0; } diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 1111ab34da018..59787648439ff 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -280,6 +280,9 @@ struct ufs_qcom_host { struct ufs_hba *hba; struct ufs_pa_layer_attr dev_req_params; struct clk_bulk_data *clks; + struct clk *tx_lane0_sync_clk; + struct clk *rx_lane0_sync_clk; + struct clk *rx_lane1_sync_clk; u32 num_clks; bool is_lane_clks_enabled; From d07ec03ee0e93b0ac7c4e3664e97fae0f9d4cb51 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Wed, 22 Jul 2026 13:05:57 +0200 Subject: [PATCH 1251/1330] UBUNTU: SAUCE: media: iris: sync to qcom tag resolute-qcom-20260717 final state Reconcile iris driver to the Qualcomm patch drop final state after cherry-picking the revert/re-add churn onto the flattened 1009.12 iris base. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- drivers/media/platform/qcom/iris/Kconfig | 2 +- drivers/media/platform/qcom/iris/Makefile | 2 + .../media/platform/qcom/iris/iris_buffer.c | 14 +- .../media/platform/qcom/iris/iris_common.c | 10 + .../media/platform/qcom/iris/iris_common.h | 1 + drivers/media/platform/qcom/iris/iris_core.c | 9 +- drivers/media/platform/qcom/iris/iris_core.h | 16 ++ .../media/platform/qcom/iris/iris_firmware.c | 114 +++++++++- .../media/platform/qcom/iris/iris_firmware.h | 2 + .../platform/qcom/iris/iris_hfi_common.h | 1 + .../qcom/iris/iris_hfi_gen2_command.c | 19 ++ .../qcom/iris/iris_hfi_gen2_defines.h | 1 + .../media/platform/qcom/iris/iris_hfi_queue.c | 16 +- .../media/platform/qcom/iris/iris_instance.h | 6 + .../platform/qcom/iris/iris_platform_common.h | 36 +++- .../platform/qcom/iris/iris_platform_glymur.c | 71 +++++++ .../platform/qcom/iris/iris_platform_glymur.h | 15 ++ .../qcom/iris/iris_platform_kaanapali.h | 73 +++++++ .../platform/qcom/iris/iris_platform_sc7280.h | 10 +- .../platform/qcom/iris/iris_platform_sm8250.h | 6 +- .../platform/qcom/iris/iris_platform_sm8550.h | 6 +- .../platform/qcom/iris/iris_platform_sm8750.h | 12 +- .../platform/qcom/iris/iris_platform_vpu2.c | 18 +- .../platform/qcom/iris/iris_platform_vpu3x.c | 28 ++- .../platform/qcom/iris/iris_platform_vpu4x.c | 10 +- .../qcom/iris/iris_platform_x1p42100.h | 22 ++ drivers/media/platform/qcom/iris/iris_power.c | 11 +- drivers/media/platform/qcom/iris/iris_probe.c | 43 +++- .../media/platform/qcom/iris/iris_resources.c | 120 ++++++++++- .../media/platform/qcom/iris/iris_resources.h | 8 +- drivers/media/platform/qcom/iris/iris_utils.c | 91 ++++++-- drivers/media/platform/qcom/iris/iris_vb2.c | 4 + drivers/media/platform/qcom/iris/iris_vdec.c | 26 +++ drivers/media/platform/qcom/iris/iris_vdec.h | 1 + drivers/media/platform/qcom/iris/iris_venc.c | 6 + drivers/media/platform/qcom/iris/iris_venc.h | 1 + drivers/media/platform/qcom/iris/iris_vidc.c | 16 +- drivers/media/platform/qcom/iris/iris_vpu2.c | 2 +- drivers/media/platform/qcom/iris/iris_vpu3x.c | 199 +++++++++++++++++- drivers/media/platform/qcom/iris/iris_vpu4x.c | 68 +++--- .../platform/qcom/iris/iris_vpu_common.c | 60 +++--- .../platform/qcom/iris/iris_vpu_common.h | 2 + .../qcom/iris/iris_vpu_register_defines.h | 7 + 43 files changed, 1005 insertions(+), 180 deletions(-) create mode 100644 drivers/media/platform/qcom/iris/iris_platform_glymur.c create mode 100644 drivers/media/platform/qcom/iris/iris_platform_glymur.h create mode 100644 drivers/media/platform/qcom/iris/iris_platform_kaanapali.h create mode 100644 drivers/media/platform/qcom/iris/iris_platform_x1p42100.h diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platform/qcom/iris/Kconfig index af78a1775937b..39b06de6c3e6e 100644 --- a/drivers/media/platform/qcom/iris/Kconfig +++ b/drivers/media/platform/qcom/iris/Kconfig @@ -3,7 +3,7 @@ config VIDEO_QCOM_IRIS depends on VIDEO_DEV depends on ARCH_QCOM || COMPILE_TEST select V4L2_MEM2MEM_DEV - select QCOM_MDT_LOADER + select QCOM_MDT_LOADER if ARCH_QCOM select QCOM_SCM select QCOM_UBWC_CONFIG select VIDEOBUF2_DMA_CONTIG diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 48e415cbc4390..8cdea242f7fdb 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -12,8 +12,10 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ + iris_platform_glymur.o \ iris_platform_vpu2.o \ iris_platform_vpu3x.o \ + iris_platform_vpu4x.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 60e3d14450c8b..0e02eaf17d384 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -336,7 +336,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, enum iris_buffer_type buffer_type, u32 index) { struct iris_buffers *buffers = &inst->buffers[buffer_type]; - struct iris_core *core = inst->core; + struct device *dev = iris_get_cb_dev(inst, buffer_type); struct iris_buffer *buffer; if (!buffers->size) @@ -352,7 +352,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst, buffer->buffer_size = buffers->size; buffer->dma_attrs = DMA_ATTR_WRITE_COMBINE | DMA_ATTR_NO_KERNEL_MAPPING; - buffer->kvaddr = dma_alloc_attrs(core->dev, buffer->buffer_size, + buffer->kvaddr = dma_alloc_attrs(dev, buffer->buffer_size, &buffer->device_addr, GFP_KERNEL, buffer->dma_attrs); if (!buffer->kvaddr) { kfree(buffer); @@ -489,10 +489,10 @@ int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer) { - struct iris_core *core = inst->core; + struct device *dev = iris_get_cb_dev(inst, buffer->type); list_del(&buffer->list); - dma_free_attrs(core->dev, buffer->buffer_size, buffer->kvaddr, + dma_free_attrs(dev, buffer->buffer_size, buffer->kvaddr, buffer->device_addr, buffer->dma_attrs); kfree(buffer); @@ -582,12 +582,10 @@ static int iris_release_internal_buffers(struct iris_inst *inst, continue; if (!(buffer->attr & BUF_ATTR_QUEUED)) continue; - buffer->attr |= BUF_ATTR_PENDING_RELEASE; ret = hfi_ops->session_release_buf(inst, buffer); - if (ret) { - buffer->attr &= ~BUF_ATTR_PENDING_RELEASE; + if (ret) return ret; - } + buffer->attr |= BUF_ATTR_PENDING_RELEASE; } return 0; diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media/platform/qcom/iris/iris_common.c index 25836561bcf3e..dade0273717a2 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -46,6 +46,16 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) inst->metadata_idx++; } +int iris_set_core_id(struct iris_inst *inst) +{ + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; + + if (!inst->core->iris_platform_data->dual_core) + return 0; + + return hfi_ops->session_set_core_id(inst, inst->core_id); +} + int iris_process_streamon_input(struct iris_inst *inst) { const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; diff --git a/drivers/media/platform/qcom/iris/iris_common.h b/drivers/media/platform/qcom/iris/iris_common.h index b2a27b781c9ac..34e32c60f7687 100644 --- a/drivers/media/platform/qcom/iris/iris_common.h +++ b/drivers/media/platform/qcom/iris/iris_common.h @@ -11,6 +11,7 @@ struct iris_buffer; int iris_vb2_buffer_to_driver(struct vb2_buffer *vb2, struct iris_buffer *buf); void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf); +int iris_set_core_id(struct iris_inst *inst); int iris_process_streamon_input(struct iris_inst *inst); int iris_process_streamon_output(struct iris_inst *inst); int iris_session_streamoff(struct iris_inst *inst, u32 plane); diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c index 52bf56e517f91..932c32f95a283 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -18,6 +18,7 @@ void iris_core_deinit(struct iris_core *core) if (core->state != IRIS_CORE_DEINIT) { iris_fw_unload(core); iris_vpu_power_off(core); + iris_fw_deinit(core); iris_hfi_queues_deinit(core); core->state = IRIS_CORE_DEINIT; } @@ -66,10 +67,14 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_queue_deinit; - ret = iris_fw_load(core); + ret = iris_fw_init(core); if (ret) goto error_power_off; + ret = iris_fw_load(core); + if (ret) + goto error_firmware_deinit; + ret = iris_vpu_boot_firmware(core); if (ret) goto error_unload_fw; @@ -90,6 +95,8 @@ int iris_core_init(struct iris_core *core) error_unload_fw: iris_fw_unload(core); +error_firmware_deinit: + iris_fw_deinit(core); error_power_off: iris_vpu_power_off(core); error_queue_deinit: diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 24da60448cf24..1bc001df0cec4 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -32,10 +32,18 @@ enum domain_type { struct qcom_ubwc_cfg_data; +enum iris_vcodec_core_id { + IRIS_VCODEC0 = 1, + IRIS_VCODEC1, +}; + /** * struct iris_core - holds core parameters valid for all instances * * @dev: reference to device structure + * @dev_np: reference to non-pixel context bank device structure + * @dev_p: reference to pixel context bank device structure + * @dev_bs: reference to bitstream context bank device structure * @reg_base: IO memory base address * @irq: iris irq * @v4l2_dev: a holder for v4l2 device structure @@ -81,11 +89,19 @@ struct qcom_ubwc_cfg_data; struct iris_core { struct device *dev; + struct device *dev_np; + struct device *dev_p; + struct device *dev_bs; void __iomem *reg_base; int irq; struct v4l2_device v4l2_dev; struct video_device *vdev_dec; struct video_device *vdev_enc; + struct video_firmware { + struct device *dev; + struct qcom_scm_pas_context *ctx; + struct iommu_domain *iommu_domain; + } fw; const struct v4l2_file_operations *iris_v4l2_file_ops; const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops_dec; const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops_enc; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index 20c07e2ba299f..86ab578a4ec87 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -3,10 +3,15 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include +#include +#include #include +#include #include +#include #include #include "iris_core.h" @@ -95,6 +100,7 @@ static const struct firmware *iris_detect_firmware(struct iris_core *core, static int iris_load_fw_to_memory(struct iris_core *core) { + struct qcom_scm_pas_context *ctx; const struct firmware *firmware = NULL; struct device *dev = core->dev; struct resource res; @@ -102,7 +108,6 @@ static int iris_load_fw_to_memory(struct iris_core *core) const char *fw_name; size_t res_size; ssize_t fw_size; - void *mem_virt; int ret; ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); @@ -132,16 +137,28 @@ static int iris_load_fw_to_memory(struct iris_core *core) goto err_release_fw; } - mem_virt = memremap(mem_phys, res_size, MEMREMAP_WC); - if (!mem_virt) { - ret = -ENOMEM; + ret = qcom_mdt_pas_load(ctx, firmware, fw_name, NULL); + qcom_scm_pas_metadata_release(ctx); + if (ret) goto err_release_fw; + + if (core->fw.iommu_domain) { + ret = iommu_map(core->fw.iommu_domain, 0, mem_phys, res_size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + if (ret) + goto err_release_fw; } - ret = qcom_mdt_load(dev, firmware, fw_name, - IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL); + ret = qcom_scm_pas_prepare_and_auth_reset(ctx); + if (ret) + goto err_iommu_unmap; + + core->fw.ctx = ctx; + + return ret; - memunmap(mem_virt); +err_iommu_unmap: + iommu_unmap(core->fw.iommu_domain, 0, res_size); err_release_fw: release_firmware(firmware); @@ -177,10 +194,91 @@ int iris_fw_load(struct iris_core *core) int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(IRIS_PAS_ID); + struct qcom_scm_pas_context *ctx = core->fw.ctx; + int ret; + + if (!ctx) + return -EINVAL; + + ret = qcom_scm_pas_shutdown(ctx->pas_id); + if (core->fw.iommu_domain) + iommu_unmap(core->fw.iommu_domain, 0, ctx->mem_size); + + core->fw.ctx = NULL; + return ret; } int iris_set_hw_state(struct iris_core *core, bool resume) { return qcom_scm_set_remote_state(resume, 0); } + +int iris_fw_init(struct iris_core *core) +{ + struct platform_device_info info; + struct iommu_domain *iommu_dom; + struct platform_device *pdev; + struct device_node *np; + int ret; + + np = of_get_child_by_name(core->dev->of_node, "video-firmware"); + if (!np) + return 0; + + memset(&info, 0, sizeof(info)); + info.fwnode = &np->fwnode; + info.parent = core->dev; + info.name = np->name; + info.dma_mask = DMA_BIT_MASK(32); + + pdev = platform_device_register_full(&info); + if (IS_ERR(pdev)) { + of_node_put(np); + return PTR_ERR(pdev); + } + + pdev->dev.of_node = np; + + ret = of_dma_configure(&pdev->dev, np, true); + if (ret) + goto err_unregister; + + core->fw.dev = &pdev->dev; + + iommu_dom = iommu_get_domain_for_dev(core->fw.dev); + if (!iommu_dom) { + ret = -EINVAL; + goto err_unset_fw_dev; + } + + ret = iommu_attach_device(iommu_dom, core->fw.dev); + if (ret) + goto err_unset_fw_dev; + + core->fw.iommu_domain = iommu_dom; + + of_node_put(np); + + return 0; + +err_unset_fw_dev: + core->fw.dev = NULL; +err_unregister: + platform_device_unregister(pdev); + of_node_put(np); + return ret; +} + +void iris_fw_deinit(struct iris_core *core) +{ + if (!core->fw.dev) + return; + + if (core->fw.iommu_domain) { + iommu_detach_device(core->fw.iommu_domain, core->fw.dev); + core->fw.iommu_domain = NULL; + } + + platform_device_unregister(to_platform_device(core->fw.dev)); + core->fw.dev = NULL; +} diff --git a/drivers/media/platform/qcom/iris/iris_firmware.h b/drivers/media/platform/qcom/iris/iris_firmware.h index e833ecd348871..adde461099667 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.h +++ b/drivers/media/platform/qcom/iris/iris_firmware.h @@ -11,5 +11,7 @@ struct iris_core; int iris_fw_load(struct iris_core *core); int iris_fw_unload(struct iris_core *core); int iris_set_hw_state(struct iris_core *core, bool resume); +int iris_fw_init(struct iris_core *core); +void iris_fw_deinit(struct iris_core *core); #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h index a27447eb25199..47786529998d5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -131,6 +131,7 @@ struct iris_hfi_session_ops { int (*session_drain)(struct iris_inst *inst, u32 plane); int (*session_resume_drain)(struct iris_inst *inst, u32 plane); int (*session_close)(struct iris_inst *inst); + int (*session_set_core_id)(struct iris_inst *inst, u32 core_id); }; struct hfi_subscription_params { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 7ac69af63eadb..1d8b47e7164ee 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1291,6 +1291,24 @@ static int iris_hfi_gen2_session_release_buffer(struct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } +static int iris_hfi_gen2_set_core_id(struct iris_inst *inst, u32 core_id) +{ + struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst); + u32 payload = core_id; + + iris_hfi_gen2_packet_session_command(inst, + HFI_PROP_CORE_ID, + HFI_HOST_FLAGS_NONE, + HFI_PORT_NONE, + inst->session_id, + HFI_PAYLOAD_U32, + &payload, + sizeof(u32)); + + return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet, + inst_hfi_gen2->packet->size); +} + static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_open = iris_hfi_gen2_session_open, .session_set_config_params = iris_hfi_gen2_session_set_config_params, @@ -1304,6 +1322,7 @@ static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops = { .session_drain = iris_hfi_gen2_session_drain, .session_resume_drain = iris_hfi_gen2_session_resume_drain, .session_close = iris_hfi_gen2_session_close, + .session_set_core_id = iris_hfi_gen2_set_core_id, }; static struct iris_inst *iris_hfi_gen2_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index cecf771c55dd3..600e9dc076690 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -56,6 +56,7 @@ #define HFI_PROP_BUFFER_HOST_MAX_COUNT 0x03000123 #define HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT 0x03000124 #define HFI_PROP_PIC_ORDER_CNT_TYPE 0x03000128 +#define HFI_PROP_CORE_ID 0x030001a9 enum hfi_rate_control { HFI_RC_VBR_CFR = 0x00000000, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_queue.c b/drivers/media/platform/qcom/iris/iris_hfi_queue.c index bf6db23b53e21..f465ff00a9ba3 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_queue.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_queue.c @@ -245,25 +245,26 @@ static void iris_hfi_queue_deinit(struct iris_iface_q_info *iface_q) int iris_hfi_queues_init(struct iris_core *core) { + struct device *dev = core->dev_np ? core->dev_np : core->dev; struct iris_hfi_queue_table_header *q_tbl_hdr; u32 queue_size; /* Iris hardware requires 4K queue alignment */ queue_size = ALIGN((sizeof(*q_tbl_hdr) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ)), SZ_4K); - core->iface_q_table_vaddr = dma_alloc_attrs(core->dev, queue_size, + core->iface_q_table_vaddr = dma_alloc_attrs(dev, queue_size, &core->iface_q_table_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->iface_q_table_vaddr) { - dev_err(core->dev, "queues alloc and map failed\n"); + dev_err(dev, "queues alloc and map failed\n"); return -ENOMEM; } - core->sfr_vaddr = dma_alloc_attrs(core->dev, SFR_SIZE, + core->sfr_vaddr = dma_alloc_attrs(dev, SFR_SIZE, &core->sfr_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->sfr_vaddr) { - dev_err(core->dev, "sfr alloc and map failed\n"); - dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, + dev_err(dev, "sfr alloc and map failed\n"); + dma_free_attrs(dev, sizeof(*q_tbl_hdr), core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); return -ENOMEM; } @@ -291,6 +292,7 @@ int iris_hfi_queues_init(struct iris_core *core) void iris_hfi_queues_deinit(struct iris_core *core) { + struct device *dev = core->dev_np ? core->dev_np : core->dev; u32 queue_size; if (!core->iface_q_table_vaddr) @@ -300,7 +302,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) iris_hfi_queue_deinit(&core->message_queue); iris_hfi_queue_deinit(&core->command_queue); - dma_free_attrs(core->dev, SFR_SIZE, core->sfr_vaddr, + dma_free_attrs(dev, SFR_SIZE, core->sfr_vaddr, core->sfr_daddr, DMA_ATTR_WRITE_COMBINE); core->sfr_vaddr = NULL; @@ -309,7 +311,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) queue_size = ALIGN(sizeof(struct iris_hfi_queue_table_header) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K); - dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, + dma_free_attrs(dev, queue_size, core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); core->iface_q_table_vaddr = NULL; diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h index 352af99699dd5..99491513ee0de 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -39,6 +39,7 @@ struct iris_fmt { * * @list: used for attach an instance to the core * @core: pointer to core structure + * @core_id: specifies the hardware core on which the session runs * @session_id: id of current video session * @hfi_session_ops: iris HFI session ops * @ctx_q_lock: lock to serialize queues related ioctls @@ -70,6 +71,8 @@ struct iris_fmt { * @metadata_idx: index for metadata buffer * @codec: codec type * @last_buffer_dequeued: a flag to indicate that last buffer is sent by driver + * @last_buf_ns: start time of received input buffer for current one second FPS window + * @frame_counter: input buffer counter for current one second FPS window * @frame_rate: frame rate of current instance * @operating_rate: operating rate of current instance * @hfi_rc_type: rate control type @@ -82,6 +85,7 @@ struct iris_fmt { struct iris_inst { struct list_head list; struct iris_core *core; + u32 core_id; u32 session_id; const struct iris_hfi_session_ops *hfi_session_ops; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ @@ -113,6 +117,8 @@ struct iris_inst { u32 metadata_idx; u32 codec; bool last_buffer_dequeued; + u64 last_buf_ns; + u32 frame_counter; u32 frame_rate; u32 operating_rate; u32 hfi_rc_type; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 33c46347c272b..51af2e13fe526 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -29,6 +29,10 @@ struct iris_inst; #define DEFAULT_QP 20 #define BITRATE_DEFAULT 20000000 +#define VIDEO_REGION_SECURE_FW_REGION_ID 0 +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + enum stage_type { STAGE_1 = 1, STAGE_2 = 2, @@ -43,26 +47,32 @@ enum pipe_type { extern const struct iris_firmware_data iris_hfi_gen1_data; extern const struct iris_firmware_data iris_hfi_gen2_data; +extern const struct iris_platform_data glymur_data; +extern const struct iris_platform_data kaanapali_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; extern const struct iris_platform_data sm8550_data; extern const struct iris_platform_data sm8650_data; extern const struct iris_platform_data sm8750_data; +extern const struct iris_platform_data x1p42100_data; enum platform_clk_type { - IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ + IRIS_AXI_VCODEC_CLK, IRIS_CTRL_CLK, IRIS_AHB_CLK, - IRIS_HW_CLK, - IRIS_HW_AHB_CLK, - IRIS_AXI1_CLK, + IRIS_VCODEC_CLK, + IRIS_VCODEC_AHB_CLK, + IRIS_AXI_CTRL_CLK, IRIS_CTRL_FREERUN_CLK, - IRIS_HW_FREERUN_CLK, + IRIS_VCODEC_FREERUN_CLK, IRIS_BSE_HW_CLK, IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, IRIS_APV_HW_CLK, + IRIS_AXI_VCODEC1_CLK, + IRIS_VCODEC1_CLK, + IRIS_VCODEC1_FREERUN_CLK, }; struct platform_clk_data { @@ -197,10 +207,11 @@ struct icc_vote_data { enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, - IRIS_HW_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, + IRIS_VCODEC1_POWER_DOMAIN, }; struct iris_firmware_data { @@ -255,16 +266,24 @@ struct iris_firmware_desc { const char *fwname; }; +struct platform_pd_data { + enum platform_pm_domain_type *pd_types; + const char **pd_names; + u32 pd_count; +}; + struct iris_platform_data { const struct iris_firmware_desc *firmware_desc_gen1, *firmware_desc_gen2; const struct vpu_ops *vpu_ops; + + int (*init_cb_devs)(struct iris_core *core); + void (*deinit_cb_devs)(struct iris_core *core); const struct icc_info *icc_tbl; unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; + const struct platform_pd_data *pmdomain_tbl; const char * const *opp_pd_tbl; unsigned int opp_pd_tbl_size; const struct platform_clk_data *clk_tbl; @@ -287,6 +306,7 @@ struct iris_platform_data { u32 max_core_mbpf; /* max number of macroblocks per second supported */ u32 max_core_mbps; + bool dual_core; }; #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/drivers/media/platform/qcom/iris/iris_platform_glymur.c new file mode 100644 index 0000000000000..194431665e077 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_platform_common.h" +#include "iris_platform_glymur.h" + +const struct platform_clk_data iris_glymur_clk_table[] = { + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_VCODEC1_CLK, "iface2" }, + {IRIS_VCODEC1_CLK, "vcodec1_core" }, + {IRIS_VCODEC1_FREERUN_CLK, "vcodec1_core_freerun" }, +}; + +const char * const iris_glymur_clk_reset_table[] = { + "bus0", + "bus1", + "core", + "vcodec0_core", + "bus2", + "vcodec1_core", +}; + +const char * const iris_glymur_opp_clk_table[] = { + "vcodec0_core", + "vcodec1_core", + "core", + NULL, +}; + +const struct platform_pd_data iris_glymur_pmdomain_table = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + IRIS_VCODEC1_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + "vcodec1", + }, + .pd_count = 3, +}; + +const struct tz_cp_config iris_glymur_tz_cp_config[] = { + { + .cp_start = VIDEO_REGION_SECURE_FW_REGION_ID, + .cp_size = 0, + .cp_nonpixel_start = 0, + .cp_nonpixel_size = 0x1000000, + }, + { + .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + }, + { + .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x25800000, + .cp_nonpixel_size = 0xda600000, + }, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/drivers/media/platform/qcom/iris/iris_platform_glymur.h new file mode 100644 index 0000000000000..875a3c65c58f1 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_GLYMUR_H__ +#define __IRIS_PLATFORM_GLYMUR_H__ + +extern const struct platform_clk_data iris_glymur_clk_table[9]; +extern const char * const iris_glymur_clk_reset_table[6]; +extern const char * const iris_glymur_opp_clk_table[4]; +extern const struct platform_pd_data iris_glymur_pmdomain_table; +extern const struct tz_cp_config iris_glymur_tz_cp_config[3]; + +#endif /* __IRIS_PLATFORM_GLYMUR_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h new file mode 100644 index 0000000000000..cade13ce1985b --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_KAANAPALI_H__ +#define __IRIS_PLATFORM_KAANAPALI_H__ + +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + +static const char *const kaanapali_clk_reset_table[] = { + "bus0", + "bus1", + "core_freerun_reset", + "vcodec0_core_freerun_reset", +}; + +static const struct platform_pd_data kaanapali_pmdomain_table = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + IRIS_VPP0_HW_POWER_DOMAIN, + IRIS_VPP1_HW_POWER_DOMAIN, + IRIS_APV_HW_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + "vpp0", + "vpp1", + "apv", + }, + .pd_count = 5, +}; + +static const struct platform_clk_data kaanapali_clk_table[] = { + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_BSE_HW_CLK, "vcodec_bse" }, + {IRIS_VPP0_HW_CLK, "vcodec_vpp0" }, + {IRIS_VPP1_HW_CLK, "vcodec_vpp1" }, + {IRIS_APV_HW_CLK, "vcodec_apv" }, +}; + +static const char *const kaanapali_opp_clk_table[] = { + "vcodec0_core", + "vcodec_apv", + "vcodec_bse", + "core", + NULL, +}; + +static struct tz_cp_config tz_cp_config_kaanapali[] = { + { + .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x01000000, + .cp_nonpixel_size = 0x24800000, + }, + { + .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x25800000, + .cp_nonpixel_size = 0xda400000, + }, +}; + +#endif /* __IRIS_PLATFORM_KAANAPALI_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h index 0ec8f334df670..6b783e524b819 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -16,11 +16,11 @@ static const struct bw_info sc7280_bw_table_dec[] = { static const char * const sc7280_opp_pd_table[] = { "cx" }; static const struct platform_clk_data sc7280_clk_table[] = { - {IRIS_CTRL_CLK, "core" }, - {IRIS_AXI_CLK, "iface" }, - {IRIS_AHB_CLK, "bus" }, - {IRIS_HW_CLK, "vcodec_core" }, - {IRIS_HW_AHB_CLK, "vcodec_bus" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_VCODEC_CLK, "vcodec_core" }, + {IRIS_VCODEC_AHB_CLK, "vcodec_bus" }, }; static const char * const sc7280_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h index 50306043eb8ec..964e1cd920860 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -16,9 +16,9 @@ static const struct bw_info sm8250_bw_table_dec[] = { static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" }; static const struct platform_clk_data sm8250_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, }; static const char * const sm8250_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h index 3c9dae995bb24..03a63904579e1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -9,9 +9,9 @@ static const char * const sm8550_clk_reset_table[] = { "bus" }; static const struct platform_clk_data sm8550_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, }; static struct platform_inst_caps platform_inst_cap_sm8550 = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h index 719056656a5ba..f843f13251c5c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h @@ -11,12 +11,12 @@ static const char * const sm8750_clk_reset_table[] = { }; static const struct platform_clk_data sm8750_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, - {IRIS_AXI1_CLK, "iface1" }, - {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - {IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, }; #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 4a020300bb794..1105ff897fa10 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -68,7 +68,17 @@ static const struct icc_info iris_icc_info_vpu2[] = { static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" }; -static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" }; +static const struct platform_pd_data iris_pmdomain_table_vpu2 = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + }, + .pd_count = 2, +}; static const struct tz_cp_config tz_cp_config_vpu2[] = { { @@ -87,8 +97,7 @@ const struct iris_platform_data sc7280_data = { .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), .bw_tbl_dec = sc7280_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl = iris_pmdomain_table_vpu2, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), + .pmdomain_tbl = &iris_pmdomain_table_vpu2, .opp_pd_tbl = sc7280_opp_pd_table, .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), .clk_tbl = sc7280_clk_table, @@ -118,8 +127,7 @@ const struct iris_platform_data sm8250_data = { .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2), .bw_tbl_dec = sm8250_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl = iris_pmdomain_table_vpu2, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), + .pmdomain_tbl = &iris_pmdomain_table_vpu2, .opp_pd_tbl = sm8250_opp_pd_table, .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), .clk_tbl = sm8250_clk_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index f7b636101682d..42fad209b6bd3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -12,10 +12,12 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" +#include "iris_platform_glymur.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8550.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" +#include "iris_platform_x1p42100.h" static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, @@ -72,7 +74,17 @@ static const struct bw_info iris_bw_table_dec_vpu3x[] = { { ((1920 * 1080) / 256) * 30, 294000 }, }; -static const char * const iris_pmdomain_table_vpu3x[] = { "venus", "vcodec0" }; +static const struct platform_pd_data iris_pmdomain_table_vpu3x = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + }, + .pd_count = 2, +}; static const char * const iris_opp_pd_table_vpu3x[] = { "mxc", "mmcx" }; @@ -103,8 +115,7 @@ const struct iris_platform_data qcs8300_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -202,14 +213,15 @@ const struct iris_platform_data glymur_data = { const struct iris_platform_data sm8550_data = { .firmware_desc_gen2 = &iris_vpu30_p4_gen2_desc, .vpu_ops = &iris_vpu3_ops, + .init_cb_devs = sm8550_init_cb_devs, + .deinit_cb_devs = sm8550_deinit_cb_devs, .icc_tbl = iris_icc_info_vpu3x, .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), .clk_rst_tbl = sm8550_clk_reset_table, .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -245,8 +257,7 @@ const struct iris_platform_data sm8650_data = { .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8550_clk_table, @@ -274,8 +285,7 @@ const struct iris_platform_data sm8750_data = { .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu3x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl = iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .pmdomain_tbl = &iris_pmdomain_table_vpu3x, .opp_pd_tbl = iris_opp_pd_table_vpu3x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), .clk_tbl = sm8750_clk_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c index 1817315103ac3..103aab2bb1044 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c @@ -14,6 +14,12 @@ #include "iris_platform_kaanapali.h" +const struct iris_firmware_desc iris_vpu40_p2_s7_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu4x_buf_size, + .fwname = "qcom/vpu/vpu40_p2_s7.mbn", +}; + static struct iris_fmt iris_fmts_vpu4x_dec[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, @@ -69,8 +75,7 @@ const struct iris_platform_data kaanapali_data = { .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table), .bw_tbl_dec = iris_bw_table_dec_vpu4x, .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu4x), - .pmdomain_tbl = kaanapali_pmdomain_table, - .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table), + .pmdomain_tbl = &kaanapali_pmdomain_table, .opp_pd_tbl = iris_opp_pd_table_vpu4x, .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu4x), .clk_tbl = kaanapali_clk_table, @@ -78,7 +83,6 @@ const struct iris_platform_data kaanapali_data = { .opp_clk_tbl = kaanapali_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .fwname = "qcom/vpu/vpu40_p2_s7.mbn", .inst_iris_fmts = iris_fmts_vpu4x_dec, .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu4x_dec), .inst_caps = &iris_inst_cap_vpu4x, diff --git a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h new file mode 100644 index 0000000000000..2c0b0644cd5aa --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __IRIS_PLATFORM_X1P42100_H__ +#define __IRIS_PLATFORM_X1P42100_H__ + +static const struct platform_clk_data x1p42100_clk_table[] = { + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_BSE_HW_CLK, "vcodec0_bse" }, +}; + +static const char *const x1p42100_opp_clk_table[] = { + "vcodec0_core", + "vcodec0_bse", + NULL, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/platform/qcom/iris/iris_power.c index 91aa21d4070eb..0e116c63f529d 100644 --- a/drivers/media/platform/qcom/iris/iris_power.c +++ b/drivers/media/platform/qcom/iris/iris_power.c @@ -77,9 +77,9 @@ static int iris_vote_interconnects(struct iris_inst *inst) static int iris_set_clocks(struct iris_inst *inst) { + u64 vcodec0_freq = 0, vcodec1_freq = 0; struct iris_core *core = inst->core; struct iris_inst *instance; - u64 freq = 0; int ret; mutex_lock(&core->lock); @@ -87,11 +87,14 @@ static int iris_set_clocks(struct iris_inst *inst) if (!instance->max_input_data_size) continue; - freq += instance->power.min_freq; + if (instance->core_id == IRIS_VCODEC0) + vcodec0_freq += instance->power.min_freq; + else if (instance->core_id == IRIS_VCODEC1) + vcodec1_freq += instance->power.min_freq; } - core->power.clk_freq = freq; - ret = iris_opp_set_rate(core->dev, freq); + core->power.clk_freq = vcodec0_freq > vcodec1_freq ? vcodec0_freq : vcodec1_freq; + ret = iris_opp_set_rate(core->dev, core->power.clk_freq); mutex_unlock(&core->lock); return ret; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 1a820c1a95ed9..359485bb9f936 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -44,8 +44,8 @@ static int iris_init_power_domains(struct iris_core *core) int ret; struct dev_pm_domain_attach_data iris_pd_data = { - .pd_names = core->iris_platform_data->pmdomain_tbl, - .num_pd_names = core->iris_platform_data->pmdomain_tbl_size, + .pd_names = core->iris_platform_data->pmdomain_tbl->pd_names, + .num_pd_names = core->iris_platform_data->pmdomain_tbl->pd_count, .pd_flags = PD_FLAG_NO_DEV_LINK, }; @@ -124,6 +124,20 @@ static int iris_init_resets(struct iris_core *core) core->iris_platform_data->controller_rst_tbl_size); } +static int iris_init_cb_devs(struct iris_core *core) +{ + if (core->iris_platform_data->init_cb_devs) + return core->iris_platform_data->init_cb_devs(core); + + return 0; +} + +static void iris_deinit_cb_devs(struct iris_core *core) +{ + if (core->iris_platform_data->deinit_cb_devs) + core->iris_platform_data->deinit_cb_devs(core); +} + static int iris_init_resources(struct iris_core *core) { int ret; @@ -194,6 +208,7 @@ static void iris_remove(struct platform_device *pdev) return; iris_core_deinit(core); + iris_deinit_cb_devs(core); video_unregister_device(core->vdev_dec); video_unregister_device(core->vdev_enc); @@ -268,7 +283,7 @@ static int iris_probe(struct platform_device *pdev) ret = v4l2_device_register(dev, &core->v4l2_dev); if (ret) - return ret; + goto err_deinit_cb; ret = iris_register_video_device(core, DECODER); if (ret) @@ -282,9 +297,11 @@ static int iris_probe(struct platform_device *pdev) dma_mask = core->iris_platform_data->dma_mask; - ret = dma_set_mask_and_coherent(dev, dma_mask); - if (ret) - goto err_vdev_unreg_enc; + if (device_iommu_mapped(core->dev)) { + ret = dma_set_mask_and_coherent(core->dev, dma_mask); + if (ret) + goto err_vdev_unreg_enc; + } dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32)); @@ -303,6 +320,8 @@ static int iris_probe(struct platform_device *pdev) video_unregister_device(core->vdev_dec); err_v4l2_unreg: v4l2_device_unregister(&core->v4l2_dev); +err_deinit_cb: + iris_deinit_cb_devs(core); return ret; } @@ -353,6 +372,14 @@ static const struct dev_pm_ops iris_pm_ops = { }; static const struct of_device_id iris_dt_match[] = { + { + .compatible = "qcom,glymur-iris", + .data = &glymur_data, + }, + { + .compatible = "qcom,kaanapali-iris", + .data = &kaanapali_data, + }, { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, @@ -377,6 +404,10 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,sm8750-iris", .data = &sm8750_data, }, + { + .compatible = "qcom,x1p42100-iris", + .data = &x1p42100_data, + }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match); diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c index 773f6548370a2..da783874cc1a4 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -6,12 +6,14 @@ #include #include #include +#include #include #include #include #include #include "iris_core.h" +#include "iris_instance.h" #include "iris_resources.h" #define BW_THRESHOLD 50000 @@ -70,10 +72,43 @@ int iris_opp_set_rate(struct device *dev, unsigned long freq) return dev_pm_opp_set_opp(dev, opp); } -int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev) +static int iris_get_pd_index_by_type(struct iris_core *core, enum platform_pm_domain_type pd_type) { + const struct platform_pd_data *pd_tbl; + u32 pd_count, i; + + pd_tbl = core->iris_platform_data->pmdomain_tbl; + pd_count = core->iris_platform_data->pmdomain_tbl->pd_count; + + for (i = 0; i < pd_count; i++) { + if (pd_tbl->pd_types[i] == pd_type) + return i; + } + + return -EINVAL; +} + +int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type, bool hwmode) +{ + int pd_index = iris_get_pd_index_by_type(core, pd_type); + + if (pd_index < 0) + return pd_index; + + return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[pd_index], hwmode); +} + +int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type) +{ + int pd_index = iris_get_pd_index_by_type(core, pd_type); + struct device *pd_dev; int ret; + if (pd_index < 0) + return pd_index; + + pd_dev = core->pmdomain_tbl->pd_devs[pd_index]; + ret = iris_opp_set_rate(core->dev, ULONG_MAX); if (ret) return ret; @@ -85,10 +120,17 @@ int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev) return ret; } -int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev) +int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type) { + int pd_index = iris_get_pd_index_by_type(core, pd_type); + struct device *pd_dev; int ret; + if (pd_index < 0) + return pd_index; + + pd_dev = core->pmdomain_tbl->pd_devs[pd_index]; + ret = iris_opp_set_rate(core->dev, 0); if (ret) return ret; @@ -141,3 +183,77 @@ int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type return 0; } + +struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id) +{ + struct platform_device *pdev; + int ret; + + pdev = platform_device_alloc(name, 0); + if (!pdev) + return ERR_PTR(-ENOMEM); + + pdev->dev.parent = core->dev; + + ret = platform_device_add(pdev); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(ret); + } + + ret = of_dma_configure_id(&pdev->dev, core->dev->of_node, true, f_id); + if (ret) + goto error_unregister; + + ret = dma_set_mask_and_coherent(&pdev->dev, core->iris_platform_data->dma_mask); + if (ret) + goto error_unregister; + + return &pdev->dev; + +error_unregister: + platform_device_unregister(to_platform_device(&pdev->dev)); + + return ERR_PTR(ret); +} + +struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_type buffer_type) +{ + struct iris_core *core = inst->core; + struct device *dev = NULL; + + switch (buffer_type) { + case BUF_INPUT: + if (inst->domain == DECODER) + dev = core->dev_bs; + else + dev = core->dev_p; + break; + case BUF_OUTPUT: + if (inst->domain == DECODER) + dev = core->dev_p; + else + dev = core->dev_bs; + break; + case BUF_BIN: + dev = core->dev_bs; + break; + case BUF_DPB: + case BUF_PARTIAL: + case BUF_SCRATCH_2: + case BUF_VPSS: + dev = core->dev_p; + break; + case BUF_ARP: + case BUF_COMV: + case BUF_LINE: + case BUF_NON_COMV: + case BUF_PERSIST: + dev = core->dev_np; + break; + default: + dev_err(core->dev, "invalid buffer type: %d\n", buffer_type); + } + + return dev ? dev : core->dev; +} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h index 6bfbd2dc6db09..8b46f036e9121 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -9,11 +9,15 @@ struct iris_core; int iris_opp_set_rate(struct device *dev, unsigned long freq); -int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev); -int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev); +int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type); +int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type); int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); +struct device *iris_create_cb_dev(struct iris_core *core, const char *name, const u32 *f_id); +struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_type buffer_type); +int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type, + bool hwmode); #endif diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/platform/qcom/iris/iris_utils.c index 29b07d88507eb..430b533078c3b 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -87,40 +87,95 @@ struct iris_inst *iris_get_instance(struct iris_core *core, u32 session_id) return NULL; } +static u32 iris_get_mbps(struct iris_inst *inst) +{ + u32 fps = max(inst->frame_rate, inst->operating_rate); + + return iris_get_mbpf(inst) * fps; +} + +static void iris_get_core_load(struct iris_core *core, u32 *core_load, u32 *core_session, bool mbpf) +{ + bool dual_core = core->iris_platform_data->dual_core; + struct iris_inst *inst; + u32 load; + + core_load[0] = 0; + core_load[1] = 0; + core_session[0] = 0; + core_session[1] = 0; + + list_for_each_entry(inst, &core->instances, list) { + if (mbpf) + load = iris_get_mbpf(inst); + else + load = iris_get_mbps(inst); + + if (inst->core_id == IRIS_VCODEC0) { + core_load[0] += load; + core_session[0]++; + } else if (dual_core && inst->core_id == IRIS_VCODEC1) { + core_load[1] += load; + core_session[1]++; + } + } +} + +static int iris_select_core_id(struct iris_inst *inst, u32 *core_load, u32 *core_session, + u32 max_load, u32 new_load) +{ + u32 max_session = inst->core->iris_platform_data->max_session_count; + bool dual_core = inst->core->iris_platform_data->dual_core; + u32 core_index; + + core_index = (core_load[0] > core_load[1] && dual_core) ? 1 : 0; + + if (core_session[core_index] >= max_session) + core_index = core_index == 0 && dual_core ? 1 : 0; + + if (core_session[core_index] >= max_session) + return -ENOMEM; + + if (core_load[core_index] + new_load <= max_load) + inst->core_id = core_index == 0 ? IRIS_VCODEC0 : IRIS_VCODEC1; + else + return -ENOMEM; + + return 0; +} + int iris_check_core_mbpf(struct iris_inst *inst) { + u32 max_core_mbpf = inst->core->iris_platform_data->max_core_mbpf; + u32 core_mbpf[2], core_session[2], new_mbpf; struct iris_core *core = inst->core; - struct iris_inst *instance; - u32 total_mbpf = 0; + int ret; mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) - total_mbpf += iris_get_mbpf(instance); + inst->core_id = 0; + iris_get_core_load(inst->core, core_mbpf, core_session, true); + new_mbpf = iris_get_mbpf(inst); + ret = iris_select_core_id(inst, core_mbpf, core_session, max_core_mbpf, new_mbpf); mutex_unlock(&core->lock); - if (total_mbpf > core->iris_platform_data->max_core_mbpf) - return -ENOMEM; - - return 0; + return ret; } int iris_check_core_mbps(struct iris_inst *inst) { + u32 max_core_mbps = inst->core->iris_platform_data->max_core_mbps; + u32 core_mbps[2] = {0, 0}, core_session[2], new_mbps; struct iris_core *core = inst->core; - struct iris_inst *instance; - u32 total_mbps = 0, fps = 0; + int ret; mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) { - fps = max(instance->frame_rate, instance->operating_rate); - total_mbps += iris_get_mbpf(instance) * fps; - } + inst->core_id = 0; + iris_get_core_load(inst->core, core_mbps, core_session, false); + new_mbps = iris_get_mbps(inst); + ret = iris_select_core_id(inst, core_mbps, core_session, max_core_mbps, new_mbps); mutex_unlock(&core->lock); - if (total_mbps > core->iris_platform_data->max_core_mbps) - return -ENOMEM; - - return 0; + return ret; } bool is_rotation_90_or_270(struct iris_inst *inst) diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/platform/qcom/iris/iris_vb2.c index a2ea2d67f60d0..dbb89396e6514 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -176,6 +176,10 @@ int iris_vb2_start_streaming(struct vb2_queue *q, unsigned int count) if (ret) goto error; + ret = iris_set_core_id(inst); + if (ret) + goto error; + if (V4L2_TYPE_IS_OUTPUT(q->type)) { if (inst->domain == DECODER) ret = iris_vdec_streamon_input(inst); diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index 752198c54514b..dc7b051f2d013 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -54,6 +54,7 @@ int iris_vdec_inst_init(struct iris_inst *inst) f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT); inst->buffers[BUF_OUTPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage; + inst->frame_rate = MAXIMUM_FPS; memcpy(&inst->fw_caps[0], &core->inst_fw_caps_dec[0], INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap)); @@ -61,6 +62,12 @@ int iris_vdec_inst_init(struct iris_inst *inst) return iris_ctrls_init(inst); } +void iris_vdec_inst_deinit(struct iris_inst *inst) +{ + kfree(inst->fmt_dst); + kfree(inst->fmt_src); +} + static const struct iris_fmt iris_vdec_formats_cap[] = { [IRIS_FMT_NV12] = { .pixfmt = V4L2_PIX_FMT_NV12, @@ -364,6 +371,8 @@ int iris_vdec_streamon_input(struct iris_inst *inst) if (ret) return ret; + inst->frame_counter = 0; + return iris_process_streamon_input(inst); } @@ -406,6 +415,7 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) { struct iris_buffer *buf = to_iris_buffer(vbuf); struct vb2_buffer *vb2 = &vbuf->vb2_buf; + u64 cur_buf_ns, delta_ns; struct vb2_queue *q; int ret; @@ -422,6 +432,22 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) return 0; } + if (buf->type == BUF_INPUT) { + cur_buf_ns = ktime_get_ns(); + + if (!inst->frame_counter) + inst->last_buf_ns = cur_buf_ns; + + inst->frame_counter++; + delta_ns = cur_buf_ns - inst->last_buf_ns; + + if (delta_ns >= NSEC_PER_SEC) { + inst->frame_rate = clamp_t(u32, inst->frame_counter, DEFAULT_FPS, + MAXIMUM_FPS); + inst->frame_counter = 0; + } + } + iris_scale_power(inst); return iris_queue_buffer(inst, buf); diff --git a/drivers/media/platform/qcom/iris/iris_vdec.h b/drivers/media/platform/qcom/iris/iris_vdec.h index 5123d2a340e15..ec1ce55d1375f 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.h +++ b/drivers/media/platform/qcom/iris/iris_vdec.h @@ -9,6 +9,7 @@ struct iris_inst; int iris_vdec_inst_init(struct iris_inst *inst); +void iris_vdec_inst_deinit(struct iris_inst *inst); int iris_vdec_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f); int iris_vdec_try_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_vdec_s_fmt(struct iris_inst *inst, struct v4l2_format *f); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c index c11fee4799cdd..aeed756ee9cac 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -79,6 +79,12 @@ int iris_venc_inst_init(struct iris_inst *inst) return iris_ctrls_init(inst); } +void iris_venc_inst_deinit(struct iris_inst *inst) +{ + kfree(inst->fmt_dst); + kfree(inst->fmt_src); +} + static const struct iris_fmt iris_venc_formats_cap[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/platform/qcom/iris/iris_venc.h index 00c1716b2747c..c4db7433da537 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -9,6 +9,7 @@ struct iris_inst; int iris_venc_inst_init(struct iris_inst *inst); +void iris_venc_inst_deinit(struct iris_inst *inst); int iris_venc_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f); int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 372408b894c19..7a94fe9caa134 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -42,16 +42,20 @@ static void iris_v4l2_fh_deinit(struct iris_inst *inst, struct file *filp) static void iris_add_session(struct iris_inst *inst) { + u32 max_session_count = inst->core->iris_platform_data->max_session_count; struct iris_core *core = inst->core; struct iris_inst *iter; u32 count = 0; + if (inst->core->iris_platform_data->dual_core) + max_session_count *= 2; + mutex_lock(&core->lock); list_for_each_entry(iter, &core->instances, list) count++; - if (count < core->iris_platform_data->max_session_count) + if (count < max_session_count) list_add_tail(&inst->list, &core->instances); mutex_unlock(&core->lock); @@ -108,7 +112,7 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_ src_vq->drv_priv = inst; src_vq->buf_struct_size = sizeof(struct iris_buffer); src_vq->min_reqbufs_allocation = MIN_BUFFERS; - src_vq->dev = inst->core->dev; + src_vq->dev = iris_get_cb_dev(inst, BUF_INPUT); src_vq->lock = &inst->ctx_q_lock; ret = vb2_queue_init(src_vq); if (ret) @@ -122,7 +126,7 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_ dst_vq->drv_priv = inst; dst_vq->buf_struct_size = sizeof(struct iris_buffer); dst_vq->min_reqbufs_allocation = MIN_BUFFERS; - dst_vq->dev = inst->core->dev; + dst_vq->dev = iris_get_cb_dev(inst, BUF_OUTPUT); dst_vq->lock = &inst->ctx_q_lock; return vb2_queue_init(dst_vq); @@ -292,6 +296,10 @@ int iris_close(struct file *filp) v4l2_m2m_ctx_release(inst->m2m_ctx); v4l2_m2m_release(inst->m2m_dev); mutex_lock(&inst->lock); + if (inst->domain == DECODER) + iris_vdec_inst_deinit(inst); + else if (inst->domain == ENCODER) + iris_venc_inst_deinit(inst); iris_session_close(inst); iris_inst_change_state(inst, IRIS_INST_DEINIT); iris_v4l2_fh_deinit(inst, filp); @@ -303,8 +311,6 @@ int iris_close(struct file *filp) mutex_unlock(&inst->lock); mutex_destroy(&inst->ctx_q_lock); mutex_destroy(&inst->lock); - kfree(inst->fmt_src); - kfree(inst->fmt_dst); kfree(inst); return 0; diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c index 01ef40f389574..b8714dcbad10a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -18,7 +18,7 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) struct v4l2_format *inp_f = inst->fmt_src; u32 mbs_per_second, mbpf, height, width; unsigned long vpp_freq, vsp_freq; - u32 fps = DEFAULT_FPS; + u32 fps = inst->frame_rate; width = max(inp_f->fmt.pix_mp.width, inst->crop.width); height = max(inp_f->fmt.pix_mp.height, inst->crop.height); diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 3dad47be78b58..ba93c25e9363c 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -27,6 +27,16 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) return pwr_status ? false : true; } +static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) +{ + u32 value, pwr_status; + + value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); + pwr_status = value & BIT(4); + + return !pwr_status; +} + static void iris_vpu3_power_off_hardware(struct iris_core *core) { u32 reg_val = 0, value, i; @@ -71,6 +81,38 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) iris_vpu_power_off_hw(core); } +static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) +{ + int ret; + + ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + if (ret) + return ret; + + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); + if (ret) + goto err_disable_power; + + ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); + if (ret) + goto err_disable_hw_clock; + + return 0; + +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); +err_disable_power: + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + + return ret; +} + +static void iris_vpu3_purwa_power_off_hardware(struct iris_core *core) +{ + iris_vpu3_power_off_hardware(core); + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); +} + static void iris_vpu33_power_off_hardware(struct iris_core *core) { bool handshake_done = false, handshake_busy = false; @@ -208,8 +250,8 @@ static int iris_vpu33_power_off_controller(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); return 0; } @@ -218,30 +260,30 @@ static int iris_vpu35_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); if (ret) goto err_disable_axi_clk; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_hw_free_clk; return 0; err_disable_hw_free_clk: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); err_disable_axi_clk: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); return ret; } @@ -250,8 +292,126 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) { iris_vpu33_power_off_hardware(core); - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); +} + +static int iris_vpu36_power_on_hw1(struct iris_core *core) +{ + int ret; + + ret = iris_enable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); + if (ret) + return ret; + + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC1_CLK); + if (ret) + goto err_disable_hw1_power; + + ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_FREERUN_CLK); + if (ret) + goto err_disable_axi1_clk; + + ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_CLK); + if (ret) + goto err_disable_hw1_free_clk; + + return 0; + +err_disable_hw1_free_clk: + iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); +err_disable_axi1_clk: + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); +err_disable_hw1_power: + iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); + + return ret; +} + +static int iris_vpu36_power_on_hw(struct iris_core *core) +{ + int ret; + + ret = iris_vpu35_power_on_hw(core); + if (ret) + return ret; + + ret = iris_vpu36_power_on_hw1(core); + if (ret) + goto err_power_off_hw; + + return 0; + +err_power_off_hw: + iris_vpu35_power_off_hw(core); + + return ret; +} + +static void iris_vpu36_power_off_hw1(struct iris_core *core) +{ + u32 value, i; + int ret; + + if (iris_vpu36_hw1_power_collapsed(core)) + goto disable_power; + + value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret = readl_poll_timeout(core->reg_base + VCODEC1_SS_IDLE_STATUSN + 4 * i, + value, value & DMA_NOC_IDLE, 2000, 20000); + if (ret) + goto disable_power; + } + + writel(REQ_VCODEC1_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, + value, value & NOC_LPI_VCODEC1_STATUS_DONE, 2000, 20000); + if (ret) + goto disable_power; + + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + writel(VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_power: + iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, false); + iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); + iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); +} + +static void iris_vpu36_power_off_hw(struct iris_core *core) +{ + iris_vpu35_power_off_hw(core); + iris_vpu36_power_off_hw1(core); +} + +static int iris_vpu36_set_hwmode(struct iris_core *core) +{ + int ret; + + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); + if (ret) + return ret; + + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, true); + if (ret) + goto error_disable_hwmode; + + return 0; + +error_disable_hwmode: + iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false); + + return ret; } const struct vpu_ops iris_vpu3_ops = { @@ -260,6 +420,14 @@ const struct vpu_ops iris_vpu3_ops = { .power_off_controller = iris_vpu_power_off_controller, .power_on_controller = iris_vpu_power_on_controller, .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, +}; + +const struct vpu_ops iris_vpu3_purwa_ops = { + .power_off_hw = iris_vpu3_purwa_power_off_hardware, + .power_on_hw = iris_vpu3_purwa_power_on_hw, + .power_off_controller = iris_vpu_power_off_controller, + .power_on_controller = iris_vpu_power_on_controller, + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode = iris_vpu_set_hwmode, }; @@ -281,3 +449,12 @@ const struct vpu_ops iris_vpu35_ops = { .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode = iris_vpu_set_hwmode, }; + +const struct vpu_ops iris_vpu36_ops = { + .power_off_hw = iris_vpu36_power_off_hw, + .power_on_hw = iris_vpu36_power_on_hw, + .power_off_controller = iris_vpu35_vpu4x_power_off_controller, + .power_on_controller = iris_vpu35_vpu4x_power_on_controller, + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode = iris_vpu36_set_hwmode, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c index 02e100a4045fc..bf7ad4e7cb8a4 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -27,27 +27,24 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 { int ret; - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode); + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, hw_mode); if (ret) return ret; if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode); + ret = iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, hw_mode); if (ret) goto restore_hw_domain_mode; } if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode); + ret = iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, hw_mode); if (ret) goto restore_vpp0_domain_mode; } if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_APV_HW_POWER_DOMAIN], hw_mode); + ret = iris_genpd_set_hwmode(core, IRIS_APV_HW_POWER_DOMAIN, hw_mode); if (ret) goto restore_vpp1_domain_mode; } @@ -56,14 +53,12 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 restore_vpp1_domain_mode: if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_DOMAIN], - !hw_mode); + iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, !hw_mode); restore_vpp0_domain_mode: if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN], - !hw_mode); + iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, !hw_mode); restore_hw_domain_mode: - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode); + iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, !hw_mode); return ret; } @@ -72,8 +67,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); if (ret) return ret; @@ -84,7 +78,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core) return 0; disable_apv_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); return ret; } @@ -139,7 +133,7 @@ static void iris_vpu4x_power_off_apv(struct iris_core *core) disable_clocks_and_power: iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN); } static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core) @@ -162,15 +156,15 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v { int ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); if (ret) goto disable_axi_clock; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto disable_hw_free_run_clock; @@ -198,11 +192,11 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v disable_bse_hw_clock: iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); disable_hw_free_run_clock: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); return ret; } @@ -216,9 +210,9 @@ static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32 efuse iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } static int iris_vpu4x_power_on_hardware(struct iris_core *core) @@ -226,20 +220,18 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR); int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); if (ret) return ret; if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); if (ret) goto disable_hw_power_domain; } if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); if (ret) goto disable_vpp0_power_domain; } @@ -260,14 +252,12 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) iris_vpu4x_disable_hardware_clocks(core, efuse_value); disable_vpp1_power_domain: if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); disable_vpp0_power_domain: if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); disable_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); return ret; } @@ -338,14 +328,12 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core) iris_vpu4x_disable_hardware_clocks(core, efuse_value); if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN); if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); } static int iris_vpu4x_set_hwmode(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 7bba3b6209c20..215ed79ab2339 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -78,7 +78,6 @@ int iris_vpu_boot_firmware(struct iris_core *core) iris_vpu_setup_ucregion_memory_map(core); writel(ctrl_init, core->reg_base + CTRL_INIT); - writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); while (!ctrl_status && count < max_tries) { ctrl_status = readl(core->reg_base + CTRL_STATUS); @@ -214,18 +213,18 @@ int iris_vpu_power_off_controller(struct iris_core *core) disable_power: iris_disable_unprepare_clock(core, IRIS_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); return 0; } void iris_vpu_power_off_hw(struct iris_core *core) { - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); + iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); } void iris_vpu_power_off(struct iris_core *core) @@ -244,7 +243,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); if (ret) return ret; @@ -252,7 +251,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) goto err_disable_power; @@ -269,9 +268,9 @@ int iris_vpu_power_on_controller(struct iris_core *core) err_disable_ctrl_clock: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); err_disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); return ret; } @@ -280,35 +279,44 @@ int iris_vpu_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_AHB_CLK); if (ret && ret != -ENOENT) goto err_disable_hw_clock; + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); + if (ret) + goto err_disable_hw_ahb_clock; + return 0; +err_disable_hw_ahb_clock: + iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN); return ret; } int iris_vpu_set_hwmode(struct iris_core *core) { - return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); + return iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); } int iris_vpu_switch_to_hwmode(struct iris_core *core) { + if (!core->iris_platform_data->vpu_ops->set_hwmode) + return 0; + return core->iris_platform_data->vpu_ops->set_hwmode(core); } @@ -367,9 +375,9 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) disable_power: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); reset_control_bulk_reset(clk_rst_tbl_size, core->resets); @@ -380,11 +388,11 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_CTRL_CLK); if (ret) goto err_disable_power; @@ -401,9 +409,9 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) err_disable_ctrl_free_clk: iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); err_disable_axi1_clk: - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN); return ret; } @@ -420,7 +428,7 @@ u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_siz u32 height, width, mbs_per_second, mbpf; u64 fw_cycles, fw_vpp_cycles; u64 vsp_cycles, vpp_cycles; - u32 fps = DEFAULT_FPS; + u32 fps = inst->frame_rate; width = max(inp_f->fmt.pix_mp.width, inst->crop.width); height = max(inp_f->fmt.pix_mp.height, inst->crop.height); @@ -439,6 +447,10 @@ u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_siz if (inst->fw_caps[PIPE].value > 1) vpp_cycles += div_u64(vpp_cycles * 59, 1000); + /* 1.05 is VPP FW overhead */ + if (inst->fw_caps[STAGE].value == STAGE_2) + vpp_cycles += mult_frac(vpp_cycles, 5, 100); + vsp_cycles = fps * data_size * 8; vsp_cycles = div_u64(vsp_cycles, 2); /* VSP FW overhead 1.05 */ diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index 09799a375c142..c0b32ae9e1c6c 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,8 +10,10 @@ struct iris_core; extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; +extern const struct vpu_ops iris_vpu3_purwa_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; +extern const struct vpu_ops iris_vpu36_ops; extern const struct vpu_ops iris_vpu4x_ops; struct vpu_ops { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index 72168b9ffa738..37f234484f1b8 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -7,6 +7,7 @@ #define __IRIS_VPU_REGISTER_DEFINES_H__ #define VCODEC_BASE_OFFS 0x00000000 +#define VCODEC1_BASE_OFFS 0x00040000 #define AON_MVP_NOC_RESET 0x0001F000 #define CPU_BASE_OFFS 0x000A0000 #define WRAPPER_BASE_OFFS 0x000B0000 @@ -14,6 +15,8 @@ #define AON_BASE_OFFS 0x000E0000 #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) +#define VCODEC1_SS_IDLE_STATUSN (VCODEC1_BASE_OFFS + 0x70) +#define DMA_NOC_IDLE BIT(22) #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) @@ -35,6 +38,8 @@ #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) #define CORE_BRIDGE_SW_RESET BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) +#define VCODEC1_BRIDGE_SW_RESET BIT(2) +#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(3) #define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) #define MSK_SIGNAL_FROM_TENSILICA BIT(0) @@ -52,11 +57,13 @@ #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) #define REQ_POWER_DOWN_PREP BIT(0) +#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1) #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) #define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ #define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ #define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ +#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8) #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) From 31f557ce88bfb607fac080f8bf0c4235b07d00e8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 5 Feb 2026 15:56:19 +0100 Subject: [PATCH 1252/1330] media: iris: fix QCOM_MDT_LOADER dependency BugLink: https://bugs.launchpad.net/bugs/2156006 commit a297c5165f91366cbc3490e630aabd1c0f70efb8 upstream. When build-testined with CONFIG_QCOM_MDT_LOADER=m and VIDEO_QCOM_IRIS=y, the kernel fails to link: x86_64-linux-ld: drivers/media/platform/qcom/iris/iris_firmware.o: in function `iris_fw_load': iris_firmware.c:(.text+0xb0): undefined reference to `qcom_mdt_get_size' iris_firmware.c:(.text+0xfd): undefined reference to `qcom_mdt_load' The problem is the conditional 'select' statement. Change this to make the driver built-in here regardless of CONFIG_ARCH_QCOM. Signed-off-by: Arnd Bergmann Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue Fixes: d19b163356b8 ("media: iris: implement video firmware load/unload") Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman Signed-off-by: Noah Wager Signed-off-by: Stefan Bader Signed-off-by: Mehmet Basaran (cherry picked from commit 2f62bf425b334c5dff9e6857197f77e94d881555) --- drivers/media/platform/qcom/iris/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platform/qcom/iris/Kconfig index 39b06de6c3e6e..af78a1775937b 100644 --- a/drivers/media/platform/qcom/iris/Kconfig +++ b/drivers/media/platform/qcom/iris/Kconfig @@ -3,7 +3,7 @@ config VIDEO_QCOM_IRIS depends on VIDEO_DEV depends on ARCH_QCOM || COMPILE_TEST select V4L2_MEM2MEM_DEV - select QCOM_MDT_LOADER if ARCH_QCOM + select QCOM_MDT_LOADER select QCOM_SCM select QCOM_UBWC_CONFIG select VIDEOBUF2_DMA_CONTIG From 15930db6f466070fe16361467bb822e5287596d4 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Mon, 16 Feb 2026 12:37:42 +0530 Subject: [PATCH 1253/1330] media: iris: Fix use-after-free in iris_release_internal_buffers() BugLink: https://bugs.launchpad.net/bugs/2156006 commit f27cfdcfc916bb59297825805f4c3499f89f9e76 upstream. The recent change in commit 1dabf00ee206 ("media: iris: gen1: Destroy internal buffers after FW releases") introduced a regression where session_release_buf() may free the buffer. The caller, iris_release_internal_buffers(), continued to access `buffer` after the call, leading to a potential use-after-free. Fix this by setting BUF_ATTR_PENDING_RELEASE before calling session_release_buf(), and reverting the flag if the call fails. This ensures no dereference occurs after potential freeing. Reported-by: Dan Carpenter Closes: https://lore.kernel.org/lkml/aYXvKAX3Pg3sL37P@stanley.mountain/#r Signed-off-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Fixes: 1dabf00ee206 ("media: iris: gen1: Destroy internal buffers after FW releases") Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman CVE-2026-46240 Signed-off-by: Noah Wager Signed-off-by: Stefan Bader Signed-off-by: Mehmet Basaran (cherry picked from commit 4a464ae3b4f8aeffb4a89847749c661a57c7a56b) --- drivers/media/platform/qcom/iris/iris_buffer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media/platform/qcom/iris/iris_buffer.c index 0e02eaf17d384..32b941c10cd96 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -582,10 +582,12 @@ static int iris_release_internal_buffers(struct iris_inst *inst, continue; if (!(buffer->attr & BUF_ATTR_QUEUED)) continue; + buffer->attr |= BUF_ATTR_PENDING_RELEASE; ret = hfi_ops->session_release_buf(inst, buffer); - if (ret) + if (ret) { + buffer->attr &= ~BUF_ATTR_PENDING_RELEASE; return ret; - buffer->attr |= BUF_ATTR_PENDING_RELEASE; + } } return 0; From bc7163d25942fc44a8bb90ead89010fd0fc3f43d Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Thu, 5 Mar 2026 18:58:31 +0530 Subject: [PATCH 1254/1330] media: iris: fix use-after-free of fmt_src during MBPF check BugLink: https://bugs.launchpad.net/bugs/2156006 commit 3d9593ad1a58c5acc3e5fa2a48222bb7632e6812 upstream. During concurrency testing, multiple instances can run in parallel, and each instance uses its own inst->lock while the core->lock protects the list of active instances. The race happens because these locks cover different scopes, inst->lock protects only the internals of a single instance, while the Macro Blocks Per Frame (MBPF) checker walks the core list under core->lock and reads fields like fmt_src->width and fmt_src->height. At the same time, iris_close() may free fmt_src and fmt_dst under inst->lock while the instance is still present in the core list. This allows a situation where the MBPF checker, still iterating through the core list, reaches an instance whose fmt_src was already freed by another thread and ends up dereferencing a dangling pointer, resulting in a use-after-free. This happens because the MBPF checker assumes that any instance in the core list is fully valid, but the freeing of fmt_src and fmt_dst without removing the instance from the core list is not correct. The correct ordering is to defer freeing fmt_src and fmt_dst until after the instance has been removed from the core list and all teardown under the core lock has completed, ensuring that no dangling pointers are ever exposed during MBPF checks. Reviewed-by: Vikash Garodia Signed-off-by: Vishnu Reddy Reviewed-by: Dikshita Agarwal Fixes: 5ad964ad5656 ("media: iris: Initialize and deinitialize encoder instance structure") Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman CVE-2026-46210 Signed-off-by: Noah Wager Signed-off-by: Stefan Bader Signed-off-by: Mehmet Basaran (cherry picked from commit 9ce6cd87db829367bfa0646b6829a96407c2de78) --- drivers/media/platform/qcom/iris/iris_vdec.c | 6 ------ drivers/media/platform/qcom/iris/iris_vdec.h | 1 - drivers/media/platform/qcom/iris/iris_venc.c | 6 ------ drivers/media/platform/qcom/iris/iris_venc.h | 1 - drivers/media/platform/qcom/iris/iris_vidc.c | 6 ++---- 5 files changed, 2 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index dc7b051f2d013..a0bcbeb426a0c 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -62,12 +62,6 @@ int iris_vdec_inst_init(struct iris_inst *inst) return iris_ctrls_init(inst); } -void iris_vdec_inst_deinit(struct iris_inst *inst) -{ - kfree(inst->fmt_dst); - kfree(inst->fmt_src); -} - static const struct iris_fmt iris_vdec_formats_cap[] = { [IRIS_FMT_NV12] = { .pixfmt = V4L2_PIX_FMT_NV12, diff --git a/drivers/media/platform/qcom/iris/iris_vdec.h b/drivers/media/platform/qcom/iris/iris_vdec.h index ec1ce55d1375f..5123d2a340e15 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.h +++ b/drivers/media/platform/qcom/iris/iris_vdec.h @@ -9,7 +9,6 @@ struct iris_inst; int iris_vdec_inst_init(struct iris_inst *inst); -void iris_vdec_inst_deinit(struct iris_inst *inst); int iris_vdec_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f); int iris_vdec_try_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_vdec_s_fmt(struct iris_inst *inst, struct v4l2_format *f); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c index aeed756ee9cac..c11fee4799cdd 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -79,12 +79,6 @@ int iris_venc_inst_init(struct iris_inst *inst) return iris_ctrls_init(inst); } -void iris_venc_inst_deinit(struct iris_inst *inst) -{ - kfree(inst->fmt_dst); - kfree(inst->fmt_src); -} - static const struct iris_fmt iris_venc_formats_cap[] = { [IRIS_FMT_H264] = { .pixfmt = V4L2_PIX_FMT_H264, diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/platform/qcom/iris/iris_venc.h index c4db7433da537..00c1716b2747c 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -9,7 +9,6 @@ struct iris_inst; int iris_venc_inst_init(struct iris_inst *inst); -void iris_venc_inst_deinit(struct iris_inst *inst); int iris_venc_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f); int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c index 7a94fe9caa134..ae27d12a06b14 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -296,10 +296,6 @@ int iris_close(struct file *filp) v4l2_m2m_ctx_release(inst->m2m_ctx); v4l2_m2m_release(inst->m2m_dev); mutex_lock(&inst->lock); - if (inst->domain == DECODER) - iris_vdec_inst_deinit(inst); - else if (inst->domain == ENCODER) - iris_venc_inst_deinit(inst); iris_session_close(inst); iris_inst_change_state(inst, IRIS_INST_DEINIT); iris_v4l2_fh_deinit(inst, filp); @@ -311,6 +307,8 @@ int iris_close(struct file *filp) mutex_unlock(&inst->lock); mutex_destroy(&inst->ctx_q_lock); mutex_destroy(&inst->lock); + kfree(inst->fmt_src); + kfree(inst->fmt_dst); kfree(inst); return 0; From 48085b4a56acc599cf1f041ff90e77b087fb0fa6 Mon Sep 17 00:00:00 2001 From: Thomas Fourier Date: Fri, 13 Feb 2026 10:13:27 +0100 Subject: [PATCH 1255/1330] media: iris: Fix dma_free_attrs() size in iris_hfi_queues_init() BugLink: https://bugs.launchpad.net/bugs/2156006 commit 4a49ae56b0e4268d48fd96babe0cc68596bc301a upstream. The core->iface_q_table_vaddr buffer is alloc'd with size queue_size but freed with sizeof(*q_tbl_hdr) which is different. Change the dma_free_attrs() size. Signed-off-by: Thomas Fourier Reviewed-by: Dikshita Agarwal Fixes: d7378f84e94e ("media: iris: introduce iris core state management with shared queues") Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman Signed-off-by: Noah Wager Signed-off-by: Stefan Bader Signed-off-by: Mehmet Basaran --- drivers/media/platform/qcom/iris/iris_hfi_queue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_queue.c b/drivers/media/platform/qcom/iris/iris_hfi_queue.c index f465ff00a9ba3..02e56ba20ab86 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_queue.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_queue.c @@ -264,7 +264,7 @@ int iris_hfi_queues_init(struct iris_core *core) GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->sfr_vaddr) { dev_err(dev, "sfr alloc and map failed\n"); - dma_free_attrs(dev, sizeof(*q_tbl_hdr), core->iface_q_table_vaddr, + dma_free_attrs(dev, queue_size, core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); return -ENOMEM; } From e8b0969a169819e38473c467e8db13e37eed88c3 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Wed, 22 Jul 2026 16:16:53 +0200 Subject: [PATCH 1256/1330] UBUNTU: SAUCE: [Config] arm64: restore CONFIG_OF_AEST=y The 'Synchronize with Qualcomm config' patch flipped CONFIG_OF_AEST from y to n on arm64 but left CONFIG_AEST=y. AEST depends on (ACPI_AEST || OF_AEST); with ACPI_AEST=n and OF_AEST=n the AEST option can no longer be enabled, causing the annotations config check to fail: check-config: CONFIG_AEST changed from y to - Restore CONFIG_OF_AEST=y (as in Ubuntu-qcom-7.0.0-1009.12) to satisfy the dependency. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- debian.qcom/config/annotations | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index f08ef14fae2a5..8a1c93b693f03 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -1390,7 +1390,7 @@ CONFIG_NVMEM_ZYNQMP policy<{'arm64': '-'}> CONFIG_NVME_APPLE policy<{'arm64': '-'}> CONFIG_NXP_SAR_ADC policy<{'arm64': '-'}> CONFIG_NXP_STM_TIMER policy<{'arm64': '-'}> -CONFIG_OF_AEST policy<{'arm64': 'n'}> +CONFIG_OF_AEST policy<{'arm64': 'y'}> CONFIG_OLPC_EC policy<{'arm64': '-'}> CONFIG_OLPC_XO175 policy<{'arm64': '-'}> CONFIG_OLPC_XO175_EC policy<{'arm64': '-'}> From 100265fb2977cd43e5cabb092756fc5be29494c2 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Wed, 22 Jul 2026 21:56:07 +0200 Subject: [PATCH 1257/1330] UBUNTU: Start new release Ignore: yes Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index 8444f86a864ab..edb1e80ce58be 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,3 +1,11 @@ +linux-qcom (7.0.0-1010.13) UNRELEASED; urgency=medium + + CHANGELOG: Do not edit directly. Autogenerated at release. + CHANGELOG: Use the printchanges target to see the current changes. + CHANGELOG: Use the insertchanges target to create the final log. + + -- Kuba Pawlak Wed, 22 Jul 2026 21:56:07 +0200 + linux-qcom (7.0.0-1009.12) resolute; urgency=medium * Miscellaneous Ubuntu changes From c4a7d61c58e5ab6d97bf26c973fb7bc2c982d271 Mon Sep 17 00:00:00 2001 From: Kuba Pawlak Date: Wed, 22 Jul 2026 21:57:02 +0200 Subject: [PATCH 1258/1330] UBUNTU: Ubuntu-qcom-7.0.0-1010.13 Signed-off-by: Kuba Pawlak --- debian.qcom/changelog | 120 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 115 insertions(+), 5 deletions(-) diff --git a/debian.qcom/changelog b/debian.qcom/changelog index edb1e80ce58be..05b7e4de7c200 100644 --- a/debian.qcom/changelog +++ b/debian.qcom/changelog @@ -1,10 +1,120 @@ -linux-qcom (7.0.0-1010.13) UNRELEASED; urgency=medium +linux-qcom (7.0.0-1010.13) resolute; urgency=medium - CHANGELOG: Do not edit directly. Autogenerated at release. - CHANGELOG: Use the printchanges target to see the current changes. - CHANGELOG: Use the insertchanges target to create the final log. + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) + - media: iris: fix QCOM_MDT_LOADER dependency + - media: iris: Fix dma_free_attrs() size in iris_hfi_queues_init() + + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46210 + - media: iris: fix use-after-free of fmt_src during MBPF check + + * Resolute update: v7.0.9 upstream stable release (LP: #2156006) // + CVE-2026-46240 + - media: iris: Fix use-after-free in iris_release_internal_buffers() + + * Miscellaneous Ubuntu changes + - SAUCE: media: iris: sync to qcom tag resolute-qcom-20260717 final state + - SAUCE: [Config] arm64: restore CONFIG_OF_AEST=y + + * Miscellaneous upstream changes + - Revert "FROMLIST: arm64: dts: qcom: purwa-iot-evk: Update TSENS thermal + zone" + - Revert "FROMLIST: media: iris: Add platform data for glymur" + - Revert "FROMLIST: media: iris: Add support to select core for dual core + platforms" + - Revert "FROMLIST: media: iris: Add power sequence for Glymur" + - Revert "FROMLIST: media: iris: Use power domain type to look up pd_devs + index" + - Revert "FROMLIST: media: iris: Rename clock and power domain macros to + use vcodec prefix" + - Revert "FROMLIST: media: iris: Fix VM count passed to firmware" + - Revert "FROMLIST: media: iris: Add platform data for X1P42100" + - Revert "FROMLIST: media: iris: Add hardware power on/off ops for + X1P42100" + - Revert "FROMLIST: media: qcom: iris: extract firmware description data" + - Revert "FROMLIST: media: qcom: iris: use new firmware name for SM8250" + - Revert "FROMLIST: media: qcom: iris: split platform data from firmware + data" + - Revert "FROMLIST: media: qcom: iris: split firmware_data from raw + platform data" + - Revert "FROMLIST: media: qcom: iris: drop hw_response_timeout_val from + platform data" + - Revert "FROMLIST: media: qcom: iris: move get_instance to + iris_hfi_sys_ops" + - Revert "FROMLIST: media: qcom: iris: merge hfi_response_ops and + hfi_command_ops" + - Revert "FROMLIST: media: qcom: iris: split HFI session ops from core + ops" + - Revert "FROMLIST: media: qcom: iris: don't use function indirection in + gen2-specific code" + - Revert "FROMLIST: media: qcom: iris: use common set_preset_registers + function" + - Revert "FROMLIST: media: qcom: iris: drop pas_id from the + iris_platform_data struct" + - Revert "PENDING: media: iris: add helper to select context bank device" + - Revert "PENDING: media: iris: add context bank devices using iommu-map" + - Revert "PENDING: media: iris: enable sm8550 context banks via + init_cb_devs" + - Revert "FROMLIST: media: iris: add FPS calculation and VPP FW overhead + in frequency formula" + - Revert "PENDING: media: iris: update MDT PAS load call for new API" + - Revert "FROMLIST: media: iris: Enable Secure PAS support with IOMMU + managed by Linux" + - Revert "FROMLIST: media: iris: Add platform data for kaanapali" + - FROMGIT: media: iris: retrieve UBWC platform configuration + - FROMGIT: media: iris: don't specify min_acc_length in the source code + - FROMGIT: media: iris: don't specify highest_bank_bit in the source code + - FROMGIT: media: iris: don't specify ubwc_swizzle in the source code + - FROMGIT: media: iris: don't specify bank_spreading in the source code + - FROMGIT: media: iris: don't specify max_channels in the source code + - FROMGIT: media: iris: drop remnants of UBWC configuration + - FROMGIT: media: qcom: iris: drop pas_id from the iris_platform_data + struct + - FROMGIT: media: qcom: iris: use common set_preset_registers function + - FROMGIT: media: qcom: iris: don't use function indirection in + gen2-specific code + - FROMGIT: media: qcom: iris: split HFI session ops from core ops + - FROMGIT: media: qcom: iris: merge hfi_response_ops and hfi_command_ops + - FROMGIT: media: qcom: iris: move get_instance to iris_hfi_sys_ops + - FROMGIT: media: qcom: iris: drop hw_response_timeout_val from platform + data + - FROMGIT: media: qcom: iris: split firmware_data from raw platform data + - FROMGIT: media: qcom: iris: split platform data from firmware data + - FROMGIT: media: qcom: iris: use new firmware name for SM8250 + - FROMGIT: media: qcom: iris: extract firmware description data + - FROMLIST: media: iris: Initialize HFI ops after firmware load in core + init + - FROMLIST: media: iris: Add Gen2 firmware autodetect and fallback + - FROMLIST: media: iris: optimize COMV buffer allocation for VPU3x and + VPU4x + - FROMGIT: soc: qcom: ubwc: add helper to get min_acc length + - FROMGIT: soc: qcom: ubwc: add helpers to get programmable values + - arm64: dts: qcom: purwa: deduplicate thermal sensors with Hamoa + - Revert "FROMLIST: usb: dwc3: qcom: notify EUD driver of role changes" + - Revert "FROMLIST: coresight: cti: expose banked sysfs registers for + Qualcomm extended CTI" + - Revert "FROMLIST: coresight: cti: add Qualcomm extended CTI + identification and quirks" + - Revert "FROMLIST: coresight: cti: encode trigger register index in + register offsets" + - Revert "FROMLIST: coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs + read operations" + - Synchronize with Qualcomm config + - Revert "Synchronize with Qualcomm config" + - Synchronize with Qualcomm config + - FROMLIST: wifi: ath12k: change MAC buffer ring size to 4096 + - FROMLIST: wifi: ath12k: Fix low MLO RX throughput on WCN7850 + - FROMLIST: wifi: ath12k: fix EAPOL TX failure caused by stale + tcl_metadata bits + - FROMLIST: Revert "wifi: ath12k: add panic handler" + - FROMLIST: dt-bindings: embedded-controller: qcom,hamoa-crd-ec: Add Purwa + IOT EVK + - FROMLIST: arm64: dts: qcom: purwa-iot-evk: Add Embedded controller node + - PENDING: arm64: dts: enable iris driver for hamoa kvm + - FROMLIST: scsi: ufs: ufs-qcom: Enable only lane clocks in lane clock + APIs - -- Kuba Pawlak Wed, 22 Jul 2026 21:56:07 +0200 + -- Kuba Pawlak Wed, 22 Jul 2026 21:57:01 +0200 linux-qcom (7.0.0-1009.12) resolute; urgency=medium From cb006c1f4dc103b93e760242e79153979bc2ba47 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Wed, 29 Jul 2026 10:25:13 +0800 Subject: [PATCH 1259/1330] Revert "FROMLIST: PCI: qcom: Set max OPP before DBI access during resume" This reverts commit f8df6a99e0746fef34c70f5ebbce99ed2daf0f4e. Revert this patch from its current position so the following updated FROMLIST patches apply without conflict. It is re-applied later in the correct order. Signed-off-by: Yushan Li --- drivers/pci/controller/dwc/pcie-qcom.c | 50 +++++++++----------------- 1 file changed, 16 insertions(+), 34 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6545286bd8754..334ddb2dd5cf0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1676,22 +1676,6 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) } } -static int qcom_pcie_set_max_opp(struct device *dev) -{ - unsigned long max_freq = ULONG_MAX; - struct dev_pm_opp *opp; - int ret; - - opp = dev_pm_opp_find_freq_floor(dev, &max_freq); - if (IS_ERR(opp)) - return PTR_ERR(opp); - - ret = dev_pm_opp_set_opp(dev, opp); - dev_pm_opp_put(opp); - - return ret; -} - static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) { struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); @@ -1924,7 +1908,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct qcom_pcie_perst *perst, *tmp_perst; struct qcom_pcie_port *port, *tmp_port; const struct qcom_pcie_cfg *pcie_cfg; + unsigned long max_freq = ULONG_MAX; struct device *dev = &pdev->dev; + struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; struct resource *res; @@ -2028,9 +2014,21 @@ static int qcom_pcie_probe(struct platform_device *pdev) * probe(), OPP will be updated using qcom_pcie_icc_opp_update(). */ if (!ret) { - ret = qcom_pcie_set_max_opp(dev); + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (IS_ERR(opp)) { + ret = PTR_ERR(opp); + dev_err_probe(pci->dev, ret, + "Unable to find max freq OPP\n"); + goto err_pm_runtime_put; + } else { + ret = dev_pm_opp_set_opp(dev, opp); + } + + dev_pm_opp_put(opp); if (ret) { - dev_err_probe(dev, ret, "Failed to set max OPP in probe\n"); + dev_err_probe(pci->dev, ret, + "Failed to set OPP for freq %lu\n", + max_freq); goto err_pm_runtime_put; } @@ -2139,14 +2137,6 @@ static int qcom_pcie_suspend_noirq(struct device *dev) } } - if (pcie->use_pm_opp) { - ret = qcom_pcie_set_max_opp(dev); - if (ret) { - dev_err(dev, "Failed to set max OPP in resume: %d\n", ret); - return ret; - } - } - /* * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. * Because on some platforms, DBI access can happen very late during the @@ -2192,14 +2182,6 @@ static int qcom_pcie_resume_noirq(struct device *dev) return ret; } else { if (pm_suspend_target_state != PM_SUSPEND_MEM) { - if (pcie->use_pm_opp) { - ret = qcom_pcie_set_max_opp(dev); - if (ret) { - dev_err(dev, "Failed to set max OPP in resume: %d\n", ret); - return ret; - } - } - ret = icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", From cc247b605a5693e7c71e9378eb70b9db46ed7813 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Wed, 29 Jul 2026 10:28:35 +0800 Subject: [PATCH 1260/1330] Revert "FROMLIST: PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks" This reverts commit b11a6d32d4ab7f1846d16be07e36e53f6eaae7da. Revert this patch from its current position so the following updated FROMLIST patches apply without conflict. It is re-applied later in the correct order. Signed-off-by: Yushan Li --- drivers/pci/controller/dwc/pcie-qcom.c | 34 +++----------------------- 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 334ddb2dd5cf0..d3f90e3d10cbb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -519,7 +519,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) u32 val; int ret; - /* Force PHY out of lowest power state */ + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -686,12 +686,6 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - u32 val; - - /* Force PHY to lowest power state*/ - val = readl(pcie->parf + PARF_PHY_CTRL); - val |= PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -724,7 +718,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) { u32 val; - /* Force PHY out of lowest power state */ + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -788,12 +782,6 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; - u32 val; - - /* Force PHY to lowest power state*/ - val = readl(pcie->parf + PARF_PHY_CTRL); - val |= PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); reset_control_bulk_assert(res->num_resets, res->resets); clk_bulk_disable_unprepare(res->num_clks, res->clks); @@ -862,12 +850,6 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; - u32 val; - - /* Force PHY to lowest power state */ - val = readl(pcie->parf + PARF_PHY_CTRL); - val |= PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -923,7 +905,6 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; - /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1019,7 +1000,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); - /* Force PHY out of lowest power state */ + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1092,7 +1073,7 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; u32 val; - /* Force PHY to lowest power state */ + /* Disable PCIe clocks and resets */ val = readl(pcie->parf + PARF_PHY_CTRL); val |= PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1200,12 +1181,6 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; - u32 val; - - /* Force PHY to lowest power state */ - val = readl(pcie->parf + PARF_PHY_CTRL); - val |= PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -1246,7 +1221,6 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) u32 val; int i; - /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); From 1eb88f670620eac37c5cbe9100fd36a1e80f8459 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 29 Apr 2026 12:12:24 +0530 Subject: [PATCH 1261/1330] FROMLIST: PCI: qcom: Add .get_ltssm() helper For older targets like sc7280, we see reading DBI after sending PME turn off message is causing NOC error. To avoid unsafe DBI accesses, introduce qcom_pcie_get_ltssm() to retrieve the LTSSM state. For newer platforms, the LTSSM state is read from the PARF_LTSSM register, while older platforms continue to retrieve it from ELBI_SYS_STTS. This helper is used in place of direct DBI-based link state checks in the D3cold path after sending PME turn-off message, ensuring the LTSSM state can be queried safely even after DBI access is no longer valid. Link: https://lore.kernel.org/r/20260429-d3cold-v5-2-89e9735b9df6@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang (cherry picked from commit a82544790da99023eecd0ed4d7bba94f6029463c) (cherry picked from commit f3932d26489b2387d9a954da88012ce325d52843) --- drivers/pci/controller/dwc/pcie-qcom.c | 153 +++++++++++-------------- 1 file changed, 67 insertions(+), 86 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index d3f90e3d10cbb..61e81b841c37b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -72,6 +71,7 @@ /* ELBI registers */ #define ELBI_SYS_CTRL 0x04 +#define ELBI_SYS_STTS 0x08 /* DBI registers */ #define AXI_MSTR_RESP_COMP_CTRL0 0x818 @@ -146,7 +146,9 @@ /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) -#define ELBI_SYS_CTRL_PME_TURNOFF_MSG BIT(4) + +/* ELBI_SYS_STTS register fields */ +#define ELBI_SYS_STTS_LTSSM_STATE_MASK GENMASK(17, 12) /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 @@ -248,6 +250,7 @@ struct qcom_pcie_ops { void (*deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); + enum dw_pcie_ltssm (*get_ltssm)(struct qcom_pcie *pcie); }; /** @@ -285,6 +288,7 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; struct list_head ports; + bool suspended; bool use_pm_opp; }; @@ -430,6 +434,15 @@ static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) writel(val, pci->elbi_base + ELBI_SYS_CTRL); } +static enum dw_pcie_ltssm qcom_pcie_2_1_0_get_ltssm(struct qcom_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + u32 val; + + val = readl(pci->elbi_base + ELBI_SYS_STTS); + return (enum dw_pcie_ltssm)FIELD_GET(ELBI_SYS_STTS_LTSSM_STATE_MASK, val); +} + static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; @@ -1071,12 +1084,6 @@ static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - u32 val; - - /* Disable PCIe clocks and resets */ - val = readl(pcie->parf + PARF_PHY_CTRL); - val |= PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); @@ -1273,7 +1280,11 @@ static enum dw_pcie_ltssm qcom_pcie_get_ltssm(struct dw_pcie *pci) struct qcom_pcie *pcie = to_qcom_pcie(pci); u32 val; + if (pcie->cfg->ops->get_ltssm) + return pcie->cfg->ops->get_ltssm(pcie); + val = readl(pcie->parf + PARF_LTSSM); + return (enum dw_pcie_ltssm)FIELD_GET(PARF_LTSSM_STATE_MASK, val); } @@ -1385,33 +1396,14 @@ static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct qcom_pcie *pcie = to_qcom_pcie(pci); - /* - * During system suspend, the Qcom RC driver may turn off the PHY and - * remove votes to save power. If the endpoint asserts CLKREQ# to - * exit L1ss, the time required to wake the system and restore the - * PHY/refclk exceeds the strict L1ss exit timing, resulting in Link - * Down (LDn). Set this flag to indicate this limitation to client - * drivers so that they will avoid relying on L1ss during system - * suspend. - */ - pp->bridge->broken_l1ss_resume = true; - if (pcie->cfg->ops->host_post_init) pcie->cfg->ops->host_post_init(pcie); } -static void qcom_pcie_host_pme_turn_off(struct dw_pcie_rp *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - - writel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pci->elbi_base + ELBI_SYS_CTRL); -} - static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { .init = qcom_pcie_host_init, .deinit = qcom_pcie_host_deinit, .post_init = qcom_pcie_host_post_init, - .pme_turn_off = qcom_pcie_host_pme_turn_off, }; /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ @@ -1421,6 +1413,7 @@ static const struct qcom_pcie_ops ops_2_1_0 = { .post_init = qcom_pcie_post_init_2_1_0, .deinit = qcom_pcie_deinit_2_1_0, .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, + .get_ltssm = qcom_pcie_2_1_0_get_ltssm, }; /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */ @@ -1430,6 +1423,7 @@ static const struct qcom_pcie_ops ops_1_0_0 = { .post_init = qcom_pcie_post_init_1_0_0, .deinit = qcom_pcie_deinit_1_0_0, .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, + .get_ltssm = qcom_pcie_2_1_0_get_ltssm, }; /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */ @@ -2076,56 +2070,53 @@ static int qcom_pcie_suspend_noirq(struct device *dev) if (!pcie) return 0; - ret = dw_pcie_suspend_noirq(pcie->pci); - if (ret) - return ret; - - if (pcie->pci->suspended) - dev_pm_genpd_rpm_always_on(dev, false); - else - dev_pm_genpd_rpm_always_on(dev, true); + /* + * Set minimum bandwidth required to keep data path functional during + * suspend. + */ + if (pcie->icc_mem) { + ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); + if (ret) { + dev_err(dev, + "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + return ret; + } + } - if (pcie->pci->suspended) { - ret = icc_disable(pcie->icc_mem); - if (ret) - dev_err(dev, "Failed to disable PCIe-MEM interconnect path: %d\n", ret); + /* + * Turn OFF the resources only for controllers without active PCIe + * devices. For controllers with active devices, the resources are kept + * ON and the link is expected to be in L0/L1 (sub)states. + * + * Turning OFF the resources for controllers with active PCIe devices + * will trigger access violation during the end of the suspend cycle, + * as kernel tries to access the PCIe devices config space for masking + * MSIs. + * + * Also, it is not desirable to put the link into L2/L3 state as that + * implies VDD supply will be removed and the devices may go into + * powerdown state. This will affect the lifetime of the storage devices + * like NVMe. + */ + if (!dw_pcie_link_up(pcie->pci)) { + qcom_pcie_host_deinit(&pcie->pci->pp); + pcie->suspended = true; + } + /* + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. + * Because on some platforms, DBI access can happen very late during the + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC + * error. + */ + if (pm_suspend_target_state != PM_SUSPEND_MEM) { ret = icc_disable(pcie->icc_cpu); if (ret) dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); if (pcie->use_pm_opp) dev_pm_opp_set_opp(pcie->pci->dev, NULL); - } else { - /* - * Set minimum bandwidth required to keep data path functional during - * suspend. - */ - if (pcie->icc_mem) { - ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); - if (ret) { - dev_err(dev, - "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", - ret); - return ret; - } - } - - /* - * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. - * Because on some platforms, DBI access can happen very late during the - * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC - * error. - */ - if (pm_suspend_target_state != PM_SUSPEND_MEM) { - ret = icc_disable(pcie->icc_cpu); - if (ret) - dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", - ret); - - if (pcie->use_pm_opp) - dev_pm_opp_set_opp(pcie->pci->dev, NULL); - } } return ret; } @@ -2139,30 +2130,20 @@ static int qcom_pcie_resume_noirq(struct device *dev) if (!pcie) return 0; - if (pcie->pci->suspended) { + if (pm_suspend_target_state != PM_SUSPEND_MEM) { ret = icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); return ret; } + } - ret = icc_enable(pcie->icc_mem); - if (ret) { - dev_err(dev, "Failed to enable PCIe-MEM interconnect path: %d\n", ret); - return ret; - } - ret = dw_pcie_resume_noirq(pcie->pci); - if (ret && (ret != -ETIMEDOUT)) + if (pcie->suspended) { + ret = qcom_pcie_host_init(&pcie->pci->pp); + if (ret) return ret; - } else { - if (pm_suspend_target_state != PM_SUSPEND_MEM) { - ret = icc_enable(pcie->icc_cpu); - if (ret) { - dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", - ret); - return ret; - } - } + + pcie->suspended = false; } qcom_pcie_icc_opp_update(pcie); From bd0824950d6bafac0526f1edc021af3b86ec3782 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 29 Apr 2026 12:12:25 +0530 Subject: [PATCH 1262/1330] FROMLIST: PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks Some Qcom PCIe controller variants bring the PHY out of test power-down (PHY_TEST_PWR_DOWN) during init. When the link is later transitioned towards D3cold and the driver disables PCIe clocks and/or regulators without explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain partially powered, leading to avoidable power leakage. Update the init-path comments to reflect that PARF_PHY_CTRL is used to power the PHY on. Also, for controller revisions that enable PHY power in init (2.3.2, 2.3.3, 2.4.0, 2.7.0 and 2.9.0), explicitly power the PHY down via PARF_PHY_CTRL in the deinit path before disabling clocks or regulators. This ensures the PHY is put into a defined low-power state prior to removing its supplies, preventing leakage when entering D3cold. Link: https://lore.kernel.org/r/20260429-d3cold-v5-3-89e9735b9df6@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang (cherry picked from commit c49333b62420f49dd4ea833e1be7bc2152edc0e6) (cherry picked from commit e70c938d8f551bf2d84b0cd6417633a19bebedc7) --- drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 61e81b841c37b..568b39e8a688b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -532,7 +532,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) u32 val; int ret; - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -699,6 +699,12 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; + u32 val; + + /* Force PHY to lowest power state*/ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -731,7 +737,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) { u32 val; - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -795,6 +801,12 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; + u32 val; + + /* Force PHY to lowest power state*/ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); reset_control_bulk_assert(res->num_resets, res->resets); clk_bulk_disable_unprepare(res->num_clks, res->clks); @@ -863,6 +875,12 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; + u32 val; + + /* Force PHY to lowest power state */ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -918,6 +936,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1013,7 +1032,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1084,6 +1103,12 @@ static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + u32 val; + + /* Force PHY to lowest power state */ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); @@ -1188,6 +1213,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; + u32 val; + + /* Force PHY to lowest power state */ + val = readl(pcie->parf + PARF_PHY_CTRL); + val |= PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -1228,6 +1259,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) u32 val; int i; + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); From 3bf491073ecfc8e4f900054a3e8bc103895aed76 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 29 Apr 2026 12:12:27 +0530 Subject: [PATCH 1263/1330] FROMLIST: PCI: qcom: Add D3cold support Add support for transitioning PCIe endpoints under host bridge into D3cold by integrating with the DWC core suspend/resume helpers. Implement PME_TurnOff message generation via ELBI_SYS_CTRL and hook it into the DWC host operations so the controller follows the standard PME_TurnOff-based power-down sequence before entering D3cold. When the device is suspended into D3cold, fully tear down interconnect bandwidth, OPP votes. If D3cold is not entered, retain existing behavior by keeping the required interconnect and OPP votes. Use dw_pcie::skip_pwrctrl_off to avoid powering off devices during suspend to preserve wakeup capability of the devices and also not to power on the devices in the init path. Drop the qcom_pcie::suspended flag and rely on the existing dw_pcie::suspended state, which now drives both the power-management flow and the interconnect/OPP handling. Link: https://lore.kernel.org/r/20260429-d3cold-v5-5-89e9735b9df6@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang (cherry picked from commit c266573af0cf27d4d9586ca3984e214ba621028f) (cherry picked from commit 72b56b0e56d636d6a2d892a10cd8c7833c0704c2) --- drivers/pci/controller/dwc/pcie-qcom.c | 155 +++++++++++++++---------- 1 file changed, 95 insertions(+), 60 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 568b39e8a688b..a466596e5601e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -146,6 +146,7 @@ /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) +#define ELBI_SYS_CTRL_PME_TURNOFF_MSG BIT(4) /* ELBI_SYS_STTS register fields */ #define ELBI_SYS_STTS_LTSSM_STATE_MASK GENMASK(17, 12) @@ -288,7 +289,6 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; struct list_head ports; - bool suspended; bool use_pm_opp; }; @@ -1364,13 +1364,17 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) if (ret) goto err_deinit; - ret = pci_pwrctrl_create_devices(pci->dev); - if (ret) - goto err_disable_phy; + if (!pci->suspended) { + ret = pci_pwrctrl_create_devices(pci->dev); + if (ret) + goto err_disable_phy; + } - ret = pci_pwrctrl_power_on_devices(pci->dev); - if (ret) - goto err_pwrctrl_destroy; + if (!pp->skip_pwrctrl_off) { + ret = pci_pwrctrl_power_on_devices(pci->dev); + if (ret) + goto err_pwrctrl_destroy; + } if (pcie->cfg->ops->post_init) { ret = pcie->cfg->ops->post_init(pcie); @@ -1395,9 +1399,10 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) err_assert_reset: qcom_pcie_perst_assert(pcie); err_pwrctrl_power_off: - pci_pwrctrl_power_off_devices(pci->dev); + if (!pp->skip_pwrctrl_off) + pci_pwrctrl_power_off_devices(pci->dev); err_pwrctrl_destroy: - if (ret != -EPROBE_DEFER) + if (ret != -EPROBE_DEFER && !pci->suspended) pci_pwrctrl_destroy_devices(pci->dev); err_disable_phy: qcom_pcie_phy_power_off(pcie); @@ -1414,11 +1419,14 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp) qcom_pcie_perst_assert(pcie); - /* - * No need to destroy pwrctrl devices as this function only gets called - * during system suspend as of now. - */ - pci_pwrctrl_power_off_devices(pci->dev); + if (!pci->pp.skip_pwrctrl_off) { + /* + * No need to destroy pwrctrl devices as this function only gets called + * during system suspend as of now. + */ + pci_pwrctrl_power_off_devices(pci->dev); + } + qcom_pcie_phy_power_off(pcie); pcie->cfg->ops->deinit(pcie); } @@ -1432,10 +1440,18 @@ static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) pcie->cfg->ops->host_post_init(pcie); } +static void qcom_pcie_host_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + writel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pci->elbi_base + ELBI_SYS_CTRL); +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { .init = qcom_pcie_host_init, .deinit = qcom_pcie_host_deinit, .post_init = qcom_pcie_host_post_init, + .pme_turn_off = qcom_pcie_host_pme_turn_off, }; /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ @@ -2102,53 +2118,51 @@ static int qcom_pcie_suspend_noirq(struct device *dev) if (!pcie) return 0; - /* - * Set minimum bandwidth required to keep data path functional during - * suspend. - */ - if (pcie->icc_mem) { - ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); - if (ret) { - dev_err(dev, - "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", - ret); - return ret; - } - } + ret = dw_pcie_suspend_noirq(pcie->pci); + if (ret) + return ret; - /* - * Turn OFF the resources only for controllers without active PCIe - * devices. For controllers with active devices, the resources are kept - * ON and the link is expected to be in L0/L1 (sub)states. - * - * Turning OFF the resources for controllers with active PCIe devices - * will trigger access violation during the end of the suspend cycle, - * as kernel tries to access the PCIe devices config space for masking - * MSIs. - * - * Also, it is not desirable to put the link into L2/L3 state as that - * implies VDD supply will be removed and the devices may go into - * powerdown state. This will affect the lifetime of the storage devices - * like NVMe. - */ - if (!dw_pcie_link_up(pcie->pci)) { - qcom_pcie_host_deinit(&pcie->pci->pp); - pcie->suspended = true; - } + if (pcie->pci->suspended) { + ret = icc_disable(pcie->icc_mem); + if (ret) + dev_err(dev, "Failed to disable PCIe-MEM interconnect path: %d\n", ret); - /* - * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. - * Because on some platforms, DBI access can happen very late during the - * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC - * error. - */ - if (pm_suspend_target_state != PM_SUSPEND_MEM) { ret = icc_disable(pcie->icc_cpu); if (ret) dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); if (pcie->use_pm_opp) dev_pm_opp_set_opp(pcie->pci->dev, NULL); + } else { + /* + * Set minimum bandwidth required to keep data path functional during + * suspend. + */ + if (pcie->icc_mem) { + ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); + if (ret) { + dev_err(dev, + "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + return ret; + } + } + + /* + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. + * Because on some platforms, DBI access can happen very late during the + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC + * error. + */ + if (pm_suspend_target_state != PM_SUSPEND_MEM) { + ret = icc_disable(pcie->icc_cpu); + if (ret) + dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", + ret); + + if (pcie->use_pm_opp) + dev_pm_opp_set_opp(pcie->pci->dev, NULL); + } } return ret; } @@ -2162,25 +2176,46 @@ static int qcom_pcie_resume_noirq(struct device *dev) if (!pcie) return 0; - if (pm_suspend_target_state != PM_SUSPEND_MEM) { + if (pcie->pci->suspended) { ret = icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); return ret; } - } - if (pcie->suspended) { - ret = qcom_pcie_host_init(&pcie->pci->pp); - if (ret) - return ret; + ret = icc_enable(pcie->icc_mem); + if (ret) { + dev_err(dev, "Failed to enable PCIe-MEM interconnect path: %d\n", ret); + goto disable_icc_cpu; + } - pcie->suspended = false; + /* + * Ignore -ENODEV & -EIO here since it is expected when no endpoint is + * connected to the PCIe link. + */ + ret = dw_pcie_resume_noirq(pcie->pci); + if (ret && ret != -ENODEV && ret != -EIO) + goto disable_icc_mem; + } else { + if (pm_suspend_target_state != PM_SUSPEND_MEM) { + ret = icc_enable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", + ret); + return ret; + } + } } qcom_pcie_icc_opp_update(pcie); return 0; +disable_icc_mem: + icc_disable(pcie->icc_mem); +disable_icc_cpu: + icc_disable(pcie->icc_cpu); + + return ret; } static const struct of_device_id qcom_pcie_match[] = { From eaf556b9d74382d6b3a008e7019f8048ece9c190 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 14 May 2026 17:03:23 +0800 Subject: [PATCH 1264/1330] FROMLIST: PCI: qcom: Set max OPP before DBI access during resume Before accessing DBI registers during resume, the OPP (Operating Performance Point) must be set to maximum to ensure the required voltage corner is available. Without this, DBI access may fail on some platforms. Refactor the open-coded max OPP selection in probe() into a helper qcom_pcie_set_max_opp(), and call it during resume before re-enabling the CPU-PCIe interconnect. Link: https://lore.kernel.org/r/20260416-setmaxopp-v1-1-6a74e2d945a0@oss.qualcomm.com Signed-off-by: Qiang Yu Signed-off-by: Ziyue Zhang (cherry picked from commit b1c88d10cb51b9603e79ad9a6420427a8eb02348) (cherry picked from commit b596553be9c6848634f415ecc549a015626c5344) --- drivers/pci/controller/dwc/pcie-qcom.c | 50 +++++++++++++++++--------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a466596e5601e..f52148e539384 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1692,6 +1692,22 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) } } +static int qcom_pcie_set_max_opp(struct device *dev) +{ + unsigned long max_freq = ULONG_MAX; + struct dev_pm_opp *opp; + int ret; + + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + ret = dev_pm_opp_set_opp(dev, opp); + dev_pm_opp_put(opp); + + return ret; +} + static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) { struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); @@ -1924,9 +1940,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct qcom_pcie_perst *perst, *tmp_perst; struct qcom_pcie_port *port, *tmp_port; const struct qcom_pcie_cfg *pcie_cfg; - unsigned long max_freq = ULONG_MAX; struct device *dev = &pdev->dev; - struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; struct resource *res; @@ -2030,21 +2044,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) * probe(), OPP will be updated using qcom_pcie_icc_opp_update(). */ if (!ret) { - opp = dev_pm_opp_find_freq_floor(dev, &max_freq); - if (IS_ERR(opp)) { - ret = PTR_ERR(opp); - dev_err_probe(pci->dev, ret, - "Unable to find max freq OPP\n"); - goto err_pm_runtime_put; - } else { - ret = dev_pm_opp_set_opp(dev, opp); - } - - dev_pm_opp_put(opp); + ret = qcom_pcie_set_max_opp(dev); if (ret) { - dev_err_probe(pci->dev, ret, - "Failed to set OPP for freq %lu\n", - max_freq); + dev_err_probe(dev, ret, "Failed to set max OPP in probe\n"); goto err_pm_runtime_put; } @@ -2189,6 +2191,14 @@ static int qcom_pcie_resume_noirq(struct device *dev) goto disable_icc_cpu; } + if (pcie->use_pm_opp) { + ret = qcom_pcie_set_max_opp(dev); + if (ret) { + dev_err(dev, "Failed to set max OPP in resume: %d\n", ret); + return ret; + } + } + /* * Ignore -ENODEV & -EIO here since it is expected when no endpoint is * connected to the PCIe link. @@ -2198,6 +2208,14 @@ static int qcom_pcie_resume_noirq(struct device *dev) goto disable_icc_mem; } else { if (pm_suspend_target_state != PM_SUSPEND_MEM) { + if (pcie->use_pm_opp) { + ret = qcom_pcie_set_max_opp(dev); + if (ret) { + dev_err(dev, "Failed to set max OPP in resume: %d\n", ret); + return ret; + } + } + ret = icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", From 6d0edc708c7f451022b9796c1cefb0749a11d965 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Wed, 29 Jul 2026 10:56:19 +0800 Subject: [PATCH 1265/1330] Revert "UBUNTU: SAUCE: PCI: dwc: update D3cold eligibility helper call after rename" This reverts commit b8178c85d4fbaaaf4801f0e930f873304abb96b0. This SAUCE commit was a build fix adapting the caller to the renamed pci_host_common_d3cold_possible() helper. The updated FROMLIST version of "PCI: dwc: Use common D3cold eligibility helper in suspend path" already calls the renamed helper directly, so this adaptation is no longer needed. Signed-off-by: Yushan Li --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 59a88cd4a568d..9861768631efa 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1207,14 +1207,13 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) int dw_pcie_suspend_noirq(struct dw_pcie *pci) { - bool pme_capable = false; int ret = 0; u32 val; if (!dw_pcie_link_up(pci)) goto stop_link; - if (!pci_host_common_d3cold_possible(pci->pp.bridge, &pme_capable)) + if (!pci_host_common_can_enter_d3cold(pci->pp.bridge)) return 0; if (pci->pp.ops->pme_turn_off) { From 19fa086e9a12c1fba919969675e1b0a141dca86b Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 29 Apr 2026 12:12:26 +0530 Subject: [PATCH 1266/1330] FROMLIST: PCI: dwc: Use common D3cold eligibility helper in suspend path Previously, the driver skipped putting the link into L2/device state in D3cold whenever L1 ASPM was enabled, since some devices (e.g. NVMe) expect low resume latency and may not tolerate deeper power states. However, such devices typically remain in D0 and are already covered by the new helper's requirement that all endpoints be in D3hot before the devices under host bridge may enter D3cold. So, replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with the shared pci_host_common_d3cold_possible() helper to decide whether the devices under host bridge can safely transition to D3cold. In addition, propagate PME-from-D3cold capability information from the helper and record it in skip_pwrctrl_off. Some devices (e.g. M.2 cards without auxiliary power) may lose PME detection when main power is removed, even if they advertise PME-from-D3cold support. This allows controller power-off to be skipped when required to preserve wakeup functionality. Update the suspended flag in dw_pcie_resume_noirq() only after the PCIe link resumes successfully, to avoid marking the controller active when link resume fails. Link: https://lore.kernel.org/r/20260429-d3cold-v5-4-89e9735b9df6@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang (cherry picked from commit f7f74f61baae49c92e7e63b0f6af04380d10c6b2) --- drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9861768631efa..d1d6ee593dd12 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -16,9 +16,11 @@ #include #include #include +#include #include #include +#include "../pci-host-common.h" #include "../../pci.h" #include "pcie-designware.h" @@ -1207,13 +1209,14 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) int dw_pcie_suspend_noirq(struct dw_pcie *pci) { + bool pme_capable = false; int ret = 0; u32 val; if (!dw_pcie_link_up(pci)) goto stop_link; - if (!pci_host_common_can_enter_d3cold(pci->pp.bridge)) + if (!pci_host_common_d3cold_possible(pci->pp.bridge, &pme_capable)) return 0; if (pci->pp.ops->pme_turn_off) { @@ -1257,6 +1260,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) udelay(1); stop_link: + pci->pp.skip_pwrctrl_off = pme_capable; dw_pcie_stop_link(pci); if (pci->pp.ops->deinit) pci->pp.ops->deinit(&pci->pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 3957babd1c3d8..4d2b5636182a6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -451,6 +451,7 @@ struct dw_pcie_rp { bool ecam_enabled; bool native_ecam; bool skip_l23_ready; + bool skip_pwrctrl_off; }; struct dw_pcie_ep_ops { From ca58641fedd7342ee4ef16869e684de5a3fd8960 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Thu, 16 Apr 2026 17:04:48 +0530 Subject: [PATCH 1267/1330] FROMLIST: arm64: dts: qcom: purwa-iot-evk: Update TSENS thermal zone MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Purwa IOT boards support a different thermal junction temperature specification compared to the base Purwa platform due to package level differences. Update the passive trip thresholds to 105°C to align with the higher temperature specification. Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20260416-purwa_high_tj-v1-1-b538f98d42da@oss.qualcomm.com (cherry picked from commit fd53d0e0a90e65cbc71d202b8cf6efaf893789ed) (cherry picked from commit 02990adca33cb9f601ac3296848cd13a04c0b42c) --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index 430bb2958f406..76dc065c1b806 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -1355,6 +1355,38 @@ }; }; +&thermal_gpuss_0 { + trips { + trip-point0 { + temperature = <105000>; + }; + }; +}; + +&thermal_gpuss_1 { + trips { + trip-point0 { + temperature = <105000>; + }; + }; +}; + +&thermal_gpuss_2 { + trips { + trip-point0 { + temperature = <105000>; + }; + }; +}; + +&thermal_gpuss_3 { + trips { + trip-point0 { + temperature = <105000>; + }; + }; +}; + &tlmm { ec_int_n_default: ec-int-n-state { pins = "gpio66"; From 160266816a6ffe7ed28d9bfed32330ab1e09790d Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Wed, 29 Jul 2026 11:17:04 +0800 Subject: [PATCH 1268/1330] Revert "FROMLIST: arm64: dts: qcom: monaco-evk: Enable SDHCI for SD Card via overlay" This reverts commit 0a14beb6dd9f1f50c7249805a6d31c0799718f07. The "dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtbo" build entry was lost during a previous apply and should be kept. Revert this patch and re-apply a corrected version that preserves that entry. Signed-off-by: Yushan Li --- arch/arm64/boot/dts/qcom/Makefile | 4 +- .../boot/dts/qcom/monaco-evk-sd-card.dtso | 72 ------------------- 2 files changed, 1 insertion(+), 75 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 82248b1d91461..b893f00802c64 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -84,12 +84,10 @@ monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb -monaco-evk-sd-card-dtbs := monaco-evk.dtb monaco-evk-sd-card.dtbo -dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-sd-card.dtb - monaco-evk-emmc-dtbs := monaco-evk.dtb monaco-evk-emmc.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-emmc.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso deleted file mode 100644 index bc4ea12587a2e..0000000000000 --- a/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - vmmc_sdc: regulator-mmc-sdc { - compatible = "regulator-fixed"; - - regulator-name = "vmmc_sdc"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - vreg_sdc: regulator-sdc { - compatible = "regulator-gpio"; - - regulator-name = "vreg_sdc"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - gpios = <&expander1 7 GPIO_ACTIVE_HIGH>; - states = <1800000 1>, <2950000 0>; - - startup-delay-us = <100>; - }; -}; - -&sdhc_1 { - vmmc-supply = <&vmmc_sdc>; - vqmmc-supply = <&vreg_sdc>; - - pinctrl-0 = <&sdc1_state_on>, <&sd_cd>; - pinctrl-1 = <&sdc1_state_off>, <&sd_cd>; - pinctrl-names = "default", "sleep"; - - cap-sd-highspeed; - no-1-8-v; - - bus-width = <4>; - cd-gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; - no-mmc; - no-sdio; - - status = "okay"; -}; - -&sdhc1_opp_table { - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; -}; - -&tlmm { - sd_cd: sd-cd-state { - pins = "gpio11"; - function = "gpio"; - bias-pull-up; - }; -}; From df566b7f6cc8c6f656c5516a1331ad246dd292da Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Thu, 12 Feb 2026 21:55:08 +0530 Subject: [PATCH 1269/1330] FROMLIST: arm64: dts: qcom: monaco-evk: Enable SDHCI for SD Card via overlay The monaco EVK board supports either eMMC or SD-card, but only one can be active at a time. Enable the SD Host Controller Interface (SDHCI) on the monaco EVK board to support SD Card for storage via a device tree overlay. This allows eMMC support to be enabled through a separate overlay when required. Link: https://lore.kernel.org/all/20260227105055.2364348-1-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara (cherry picked from commit daa1cfdb843dab7d2b3cc9997aec2fea6e9a4b9d) (cherry picked from commit 660bd51e8c829e896a6bc7eca96737f7eec8de91) --- arch/arm64/boot/dts/qcom/Makefile | 4 ++ .../boot/dts/qcom/monaco-evk-sd-card.dtso | 72 +++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b893f00802c64..2ed4236f430a7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -88,6 +88,10 @@ monaco-evk-emmc-dtbs := monaco-evk.dtb monaco-evk-emmc.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-emmc.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtbo + +monaco-evk-sd-card-dtbs := monaco-evk.dtb monaco-evk-sd-card.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-sd-card.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso new file mode 100644 index 0000000000000..bc4ea12587a2e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-sd-card.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + vmmc_sdc: regulator-mmc-sdc { + compatible = "regulator-fixed"; + + regulator-name = "vmmc_sdc"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + vreg_sdc: regulator-sdc { + compatible = "regulator-gpio"; + + regulator-name = "vreg_sdc"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + gpios = <&expander1 7 GPIO_ACTIVE_HIGH>; + states = <1800000 1>, <2950000 0>; + + startup-delay-us = <100>; + }; +}; + +&sdhc_1 { + vmmc-supply = <&vmmc_sdc>; + vqmmc-supply = <&vreg_sdc>; + + pinctrl-0 = <&sdc1_state_on>, <&sd_cd>; + pinctrl-1 = <&sdc1_state_off>, <&sd_cd>; + pinctrl-names = "default", "sleep"; + + cap-sd-highspeed; + no-1-8-v; + + bus-width = <4>; + cd-gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + + status = "okay"; +}; + +&sdhc1_opp_table { + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; +}; + +&tlmm { + sd_cd: sd-cd-state { + pins = "gpio11"; + function = "gpio"; + bias-pull-up; + }; +}; From 2c7260db7b222f4e0d86d9d7ecb5f98391e6c220 Mon Sep 17 00:00:00 2001 From: Yushan Li Date: Wed, 29 Jul 2026 11:22:58 +0800 Subject: [PATCH 1270/1330] Revert "FROMLIST: arm64: dts: qcom: monaco: Move eMMC CQE support from SoC to board DT" This reverts commit 057c7d662629536e0758e5c26efe5cf57871fa02. To resolve a context mismatch, this patch added "bus-width = <8>" to monaco.dtsi, but that property properly comes from "arm64: dts: qcom: monaco: Complete SDHC definition". Revert this patch, apply "Complete SDHC definition" first, then re-apply a corrected version. Signed-off-by: Yushan Li --- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index daf2444370fbf..0be35310ff21f 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4887,7 +4887,7 @@ qcom,dll-config = <0x000f64ee>; qcom,ddr-config = <0x80040868>; - bus-width = <8>; + supports-cqe; dma-coherent; qcom,ice = <&sdhc_ice>; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 8b732689dfd12..c926879d93e81 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -726,7 +726,6 @@ vmmc-supply = <&vreg_l8a>; vqmmc-supply = <&vreg_s4a>; - supports-cqe; non-removable; no-sd; no-sdio; From 1fb275dbc69cee086a54d81b25b253e9b652953b Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 16 Jan 2026 22:43:53 +0100 Subject: [PATCH 1271/1330] arm64: dts: qcom: monaco: Complete SDHC definition Add the missing SDHC properties required to enable HS200, HS400, and HS400 Enhanced Strobe modes, as supported by this controller. Select the proper default pinctrls. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260116214354.256878-2-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 978400b7a68f19d09ef3767b69447f855bd5ea43) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 0be35310ff21f..3cacae763bc69 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4885,11 +4885,21 @@ interconnect-names = "sdhc-ddr", "cpu-sdhc"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + qcom,dll-config = <0x000f64ee>; qcom,ddr-config = <0x80040868>; + bus-width = <8>; supports-cqe; dma-coherent; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + qcom,ice = <&sdhc_ice>; status = "disabled"; From 6bb10fd5e497e160accf325727ea44c6e575ba7e Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Thu, 12 Feb 2026 21:35:24 +0530 Subject: [PATCH 1272/1330] FROMLIST: arm64: dts: qcom: monaco: Move eMMC CQE support from SoC to board DT The Monaco SoC SDHC controller supports both eMMC and SD cards. However, the 'supports-cqe' property (Command Queue Engine) is specific to eMMC and conflicts with SD card operation. Remove 'supports-cqe' from the SoC device tree to ensure compatibility with SD cards. Simultaneously, add the property explicitly to the qcs8300-ride board device tree, as this board uses the controller in eMMC mode. This ensures the SoC definition remains generic while enabling features correctly at the board level. Link: https://lore.kernel.org/all/20260227105055.2364348-1-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara --- arch/arm64/boot/dts/qcom/monaco.dtsi | 1 - arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 3cacae763bc69..42f16140ffe99 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4892,7 +4892,6 @@ qcom,dll-config = <0x000f64ee>; qcom,ddr-config = <0x80040868>; bus-width = <8>; - supports-cqe; dma-coherent; mmc-ddr-1_8v; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index c926879d93e81..8b732689dfd12 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -726,6 +726,7 @@ vmmc-supply = <&vreg_l8a>; vqmmc-supply = <&vreg_s4a>; + supports-cqe; non-removable; no-sd; no-sdio; From 3b7105b82432420faabf537e5c63793caa4bdef7 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 27 Nov 2025 17:28:29 +0530 Subject: [PATCH 1273/1330] QCLINUX: arch: arm64: qcom: qcs8300-ride: Enable PCIe Qref regulator PCIe phy needs to be voted for QREF regulator, As the base dtsi changes are still pending we haven't posted the actual fix. Till we post actual fix to upstream, use this change as a workaround. Signed-off-by: Krishna Chaitanya Chundru (cherry picked from commit 05a66a5d0e8c19de43ceca1fb2c150c0d24a8a89) --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 8b732689dfd12..330c7b8ba63f3 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -638,7 +638,7 @@ &pcie0_phy { vdda-phy-supply = <&vreg_l6a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; vdda-qref-supply = <&vreg_l7a>; vdda-refgen-supply = <&refgen>; From 2d4e8209dfb092478d445e4f50468cfc53f4d5b6 Mon Sep 17 00:00:00 2001 From: shubamm Date: Thu, 9 Jul 2026 18:18:55 +0530 Subject: [PATCH 1274/1330] QCLINUX: arm64: dts: qcom: Add Hamoa camera sensor support Add og0a1b VGA camera sensor node (cam-sensor1) on CCI0 and imx688 camera sensor node (cam-sensor4) on CCI1 for Hamoa board. og0a1b (cam-sensor1): - MCLK0 / CCI master 0 - 1.8V IO supply (vreg_l4m_1p8), 2.9V analog supply (vreg_l7m_2p9) - GPIO reset: TLMM 109, MCLK: TLMM 96 - Sensor position: yaw=180 (rear-facing) imx688 (cam-sensor4): - MCLK4 / CCI1 master 1 - 1.8V IO supply (vreg_l4m_1p8), 1.8V analog supply (vreg_l6m_1p8) - 1.056V digital supply (vreg_l1m_1p1), 2.8V custom supply (vreg_l7b_2p8) - GPIO reset: TLMM 237, MCLK: TLMM 100, custom GPIO: TLMM 233 - Sensor position: yaw=180 (rear-facing) Signed-off-by: shubamm (cherry picked from commit 3f8fc45897b308bde58ee32acba85d5f17c2f77a) --- .../boot/dts/qcom/hamoa-camera-sensor.dtsi | 74 ++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi index 7ebfcf1ec3912..1b2e16fe68808 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi @@ -19,7 +19,7 @@ rgltr-cntrl-support; pwm-switch; rgltr-min-voltage = <1800000>; - rgltr-max-voltage = <1800000>; + rgltr-max-voltage = <1808000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -43,6 +43,78 @@ cell-index = <0>; status = "okay"; }; + /*cam1-og0a1b*/ + qcom,cam-sensor1 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l4m_1p8>; + cam_vana-supply = <&vreg_l7m_2p9>; + regulator-names = "cam_vio", "cam_vana"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2912000>; + rgltr-max-voltage = <1808000 2912000>; + rgltr-load-current = <120000 120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend &cam_sensor_suspend_rst0>; + gpios = <&tlmm 96 0>, <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK0", "CAMIF_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <1>; + status = "okay"; + }; +}; + +&cam_cci1 { + /*cam2-imx688*/ + qcom,cam-sensor4 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l4m_1p8>; + cam_vana-supply = <&vreg_l6m_1p8>; + cam_vdig-supply = <&vreg_l1m_1p1>; + cam_v_custom1-supply = <&vreg_l7b_2p8>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_v_custom1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1800000 1056000 2800000>; + rgltr-max-voltage = <1808000 1808000 1200000 2800000>; + rgltr-load-current = <120000 120000 120000 120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend &cam_sensor_suspend_rst4>; + gpios = <&tlmm 100 0>, <&tlmm 237 0>, <&tlmm 233 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK4", "CAMIF_RESET4", "CAM_CUSTOM1"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <4>; + status = "okay"; + }; }; &soc { From 1475340fd4a369094e23a3a29eb2e93365ec4ad1 Mon Sep 17 00:00:00 2001 From: Tingguo Cheng Date: Tue, 23 Jun 2026 17:13:53 +0800 Subject: [PATCH 1275/1330] QCLINUX: arm64: dts: qcom: hamoa: Add pm8010 camera PMIC regulators Add the PM8010 PMIC providing the following voltage rails: - vreg_l1m_1p1 @ 1v1 camera core (DVDD) - vreg_l2m_1p15 @ 1v15 camera core (DVDD) - vreg_l3m_1p8 @ 1v8 camera analog/IO (AVDD2, DOVDD) - vreg_l4m_1p8 @ 1v8 camera IO (DOVDD) - vreg_l5m_3p0 @ 3v0 camera VCM - vreg_l6m_1p8 @ 1v8 camera analog (AVDD2) - vreg_l7m_2p9 @ 2v9 camera analog (AVDD) Signed-off-by: Tingguo Cheng (cherry picked from commit 019709ac4ccd3700762d621048411e8a91a29a93) --- .../dts/qcom/hamoa-camera-regulators.dtsi | 69 +++++++++++++++++++ arch/arm64/boot/dts/qcom/hamoa-evk-camx.dtso | 1 + arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso | 1 + 3 files changed, 71 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/hamoa-camera-regulators.dtsi diff --git a/arch/arm64/boot/dts/qcom/hamoa-camera-regulators.dtsi b/arch/arm64/boot/dts/qcom/hamoa-camera-regulators.dtsi new file mode 100644 index 0000000000000..88d53f33da2a4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-camera-regulators.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&apps_rsc { + /* PM8010_M */ + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l5-supply = <&vreg_bob1>; + vdd-l6-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name = "vreg_l1m_1p1"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2m_1p15: ldo2 { + regulator-name = "vreg_l2m_1p15"; + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vreg_l4m_1p8: ldo4 { + regulator-name = "vreg_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vreg_l5m_3p0: ldo5 { + regulator-name = "vreg_l5m_3p0"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l6m_1p8: ldo6 { + regulator-name = "vreg_l6m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/hamoa-evk-camx.dtso b/arch/arm64/boot/dts/qcom/hamoa-evk-camx.dtso index d63daf990f2a1..df773142192eb 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-evk-camx.dtso +++ b/arch/arm64/boot/dts/qcom/hamoa-evk-camx.dtso @@ -18,6 +18,7 @@ #include #include +#include "hamoa-camera-regulators.dtsi" #include "hamoa-camera.dtsi" #include "hamoa-camera-sensor.dtsi" diff --git a/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso b/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso index 26603aed4eafc..f97d37cf6e1e4 100644 --- a/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso +++ b/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso @@ -18,6 +18,7 @@ #include #include +#include "hamoa-camera-regulators.dtsi" #include "purwa-camera.dtsi" &camss { From 782d1ed5511cf674b13df8389969db2c799bbec4 Mon Sep 17 00:00:00 2001 From: shubamm Date: Thu, 9 Jul 2026 18:17:33 +0530 Subject: [PATCH 1276/1330] QCLINUX: arm64: dts: qcom: Add Purwa sensors support Add og0va1b IR/VGA camera sensor node. Add imx688 camera sensor module node CRs-Fixed: 4561668 Change-Id: I10ff09815e7596180518240b8e1b09e7a770f5e3 Signed-off-by: shubamm (cherry picked from commit 5308a88b4fe6933a6b93a66bc1f7333a2817f380) --- .../boot/dts/qcom/purwa-camera-sensor.dtsi | 89 +++++++++++++++++++ arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso | 1 + 2 files changed, 90 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/purwa-camera-sensor.dtsi diff --git a/arch/arm64/boot/dts/qcom/purwa-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/purwa-camera-sensor.dtsi new file mode 100644 index 0000000000000..c6b319254bace --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-camera-sensor.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci0 { + + /*cam1-og0a1b*/ + qcom,cam-sensor1 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l4m_1p8>; + cam_vana-supply = <&vreg_l7m_2p9>; + regulator-names = "cam_vio", "cam_vana"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2912000>; + rgltr-max-voltage = <1808000 2912000>; + rgltr-load-current = <120000 120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend &cam_sensor_suspend_rst0>; + gpios = <&tlmm 96 0>, <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK0", "CAMIF_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <1>; + status = "okay"; + }; +}; + +&cam_cci1 { + /*cam2-imx688*/ + qcom,cam-sensor4 { + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_l4m_1p8>; + cam_vana-supply = <&vreg_l6m_1p8>; + cam_vdig-supply = <&vreg_l1m_1p1>; + cam_v_custom1-supply = <&vreg_l7b_2p8>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_v_custom1"; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1800000 1056000 2800000>; + rgltr-max-voltage = <1808000 1808000 1200000 2800000>; + rgltr-load-current = <120000 120000 120000 120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend &cam_sensor_suspend_rst4>; + gpios = <&tlmm 100 0>, <&tlmm 237 0>, <&tlmm 233 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK4", "CAMIF_RESET4", "CAM_CUSTOM1"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + cell-index = <4>; + status = "okay"; + }; +}; + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso b/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso index f97d37cf6e1e4..27d1ff2fc2fea 100644 --- a/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso +++ b/arch/arm64/boot/dts/qcom/purwa-evk-camx.dtso @@ -20,6 +20,7 @@ #include "hamoa-camera-regulators.dtsi" #include "purwa-camera.dtsi" +#include "purwa-camera-sensor.dtsi" &camss { status = "disabled"; From a1bbffaf6f00e10dddc7f3b5092e43438fe45c14 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 18 Jun 2026 14:41:57 +0800 Subject: [PATCH 1277/1330] QCLINUX: arm64: dts: qcom: Add shared X1 staging overlay Move the common Hamoa staging overlay contents into x1-staging.dtsi so they can be shared across X1 platforms. Keep hamoa-staging.dtso as a thin wrapper around the shared include and add purwa-staging.dtso to build an identical staging overlay for Purwa. Signed-off-by: Jie Gan (cherry picked from commit 20d9bc2f4c31f9aa31ef9c348b6ad751f1ac2eb8) --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/hamoa-staging.dtso | 108 +------------------ arch/arm64/boot/dts/qcom/purwa-staging.dtso | 11 ++ arch/arm64/boot/dts/qcom/x1-staging.dtsi | 113 ++++++++++++++++++++ 4 files changed, 127 insertions(+), 107 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/purwa-staging.dtso create mode 100644 arch/arm64/boot/dts/qcom/x1-staging.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2ed4236f430a7..5fc63cdf6a34f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -613,6 +613,8 @@ dtb-$(CONFIG_ARCH_QCOM) += glymur-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-staging.dtbo +dtb-$(CONFIG_ARCH_QCOM) += purwa-staging.dtbo + dtb-$(CONFIG_ARCH_QCOM) += sm8750-staging.dtbo dtb-$(CONFIG_ARCH_QCOM) += kaanapali-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/hamoa-staging.dtso b/arch/arm64/boot/dts/qcom/hamoa-staging.dtso index 6a1e106ae8a9a..465e521384842 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-staging.dtso +++ b/arch/arm64/boot/dts/qcom/hamoa-staging.dtso @@ -8,110 +8,4 @@ /dts-v1/; /plugin/; -#include - -&soc { - tgu@10b0e000 { - compatible = "qcom,tgu", "arm,primecell"; - reg = <0x0 0x10b0e000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - tgu@10b0f000 { - compatible = "qcom,tgu", "arm,primecell"; - reg = <0x0 0x10b0f000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - tgu@10b10000 { - compatible = "qcom,tgu", "arm,primecell"; - reg = <0x0 0x10b10000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; -}; - -&remoteproc_cdsp { - cooling { - compatible = "qcom,qmi-cooling-cdsp"; - - cdsp_tmd0: cdsp-tmd0 { - label = "cdsp_sw"; - #cooling-cells = <2>; - }; - }; -}; - -&thermal_nsp0 { - trips { - nsp0_alert0: trip-point1 { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&nsp0_alert0>; - cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&thermal_nsp1 { - trips { - nsp1_alert0: trip-point1 { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&nsp1_alert0>; - cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&thermal_nsp2 { - trips { - nsp2_alert0: trip-point1 { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&nsp2_alert0>; - cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&thermal_nsp3 { - trips { - nsp3_alert0: trip-point1 { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&nsp3_alert0>; - cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - +#include "x1-staging.dtsi" diff --git a/arch/arm64/boot/dts/qcom/purwa-staging.dtso b/arch/arm64/boot/dts/qcom/purwa-staging.dtso new file mode 100644 index 0000000000000..5ab12052dd80f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-staging.dtso @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Purwa staging overlay - add staging-specific device tree modifications here. + */ + +/dts-v1/; +/plugin/; + +#include "x1-staging.dtsi" diff --git a/arch/arm64/boot/dts/qcom/x1-staging.dtsi b/arch/arm64/boot/dts/qcom/x1-staging.dtsi new file mode 100644 index 0000000000000..24dfda988bd9d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-staging.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Shared X1 staging device tree modifications. + */ + +#include + +&soc { + tgu@10b0e000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b0e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@10b0f000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b0f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tgu@10b10000 { + compatible = "qcom,tgu", "arm,primecell"; + reg = <0x0 0x10b10000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; + +&remoteproc_cdsp { + cooling { + compatible = "qcom,qmi-cooling-cdsp"; + + cdsp_tmd0: cdsp-tmd0 { + label = "cdsp_sw"; + #cooling-cells = <2>; + }; + }; +}; + +&thermal_nsp0 { + trips { + nsp0_alert0: trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&nsp0_alert0>; + cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_nsp1 { + trips { + nsp1_alert0: trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&nsp1_alert0>; + cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_nsp2 { + trips { + nsp2_alert0: trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&nsp2_alert0>; + cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_nsp3 { + trips { + nsp3_alert0: trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&nsp3_alert0>; + cooling-device = <&cdsp_tmd0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; From 143d96c59bed521c1d6613c4a54b282876367f1b Mon Sep 17 00:00:00 2001 From: "Signed-off-by: Wenjia Zhang" Date: Wed, 22 Jul 2026 21:27:51 +0530 Subject: [PATCH 1278/1330] FROMLIST: qcom,inline-crypto-engine: Add x1e80100 support Document the compatible string for inline crypto engine found on the Qualcomm X1E80100 SoC, used by the Hamoa IoT EVK board. Link: https://lore.kernel.org/all/20260722-devtool-v2-1-03f6c82d84fe@oss.qualcomm.com/ Signed-off-by: Wenjia Zhang Signed-off-by: Abhinaba Rakshit (cherry picked from commit 904b3fe1504e39f0885dec7a43c0a76d6fde2286) --- .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 79161c8e583d9..23113d21edcaa 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -24,6 +24,7 @@ properties: - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine - qcom,sm8750-inline-crypto-engine + - qcom,x1e80100-inline-crypto-engine - const: qcom,inline-crypto-engine reg: From 820c3ff05c639f07383a8135e53a859ce6fcdd62 Mon Sep 17 00:00:00 2001 From: Wenjia Zhang Date: Wed, 22 Jul 2026 21:29:34 +0530 Subject: [PATCH 1279/1330] FROMLIST: hamoa: Add ICE node for UFS inline encryption Add the Inline Crypto Engine (ICE) device node to describe the hardware-accelerated inline encryption for UFS storage on the Hamoa IoT EVK board (Qualcomm X1E80100 SoC). Link: https://lore.kernel.org/all/20260722-devtool-v2-2-03f6c82d84fe@oss.qualcomm.com/ Signed-off-by: Wenjia Zhang Signed-off-by: Abhinaba Rakshit (cherry picked from commit f1d4cbe393d33412bb15383fefe129426c8821c3) --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 91dfb9fcab105..35a942538fb11 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -4195,6 +4195,8 @@ phys = <&ufs_mem_phy>; phy-names = "ufsphy"; + qcom,ice = <&ice>; + #reset-cells = <1>; status = "disabled"; @@ -4240,6 +4242,17 @@ }; }; + ice: crypto@1d88000 { + compatible = "qcom,x1e80100-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; From 25cf5d0e35caeb61d71b154fba568ee76039f655 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 19:36:05 +0800 Subject: [PATCH 1280/1330] BACKPORT: arm64: dts: qcom: hamoa: Add label properties to CoreSight devices Add label properties to TPDM and CTI nodes in the hamoa device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-7-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 9bc3b08767a61a3a4b3dfd810462424c8d72ae56) --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 35a942538fb11..eaa3b5c324f27 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -7723,6 +7723,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_prng"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -7780,6 +7781,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dcc"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -8042,6 +8044,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_tmess_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8061,6 +8064,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dl_south_0"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -8080,6 +8084,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_spdm"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -8099,6 +8104,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_qm"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -8142,6 +8148,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_cdsp_cscti"; }; tpdm@109d0000 { @@ -8150,6 +8157,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_lpass"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -8170,6 +8178,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_gcc"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -8190,6 +8199,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rpdm_mxa"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8437,6 +8447,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dl_south_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8456,6 +8467,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_3"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8475,6 +8487,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8494,6 +8507,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8513,6 +8527,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dlct"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -8532,6 +8547,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dlmm"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -8602,6 +8618,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -8650,6 +8667,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ddr_lpi"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -8669,6 +8687,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_2"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8802,6 +8821,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8821,6 +8841,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_mx"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -8917,6 +8938,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -9021,6 +9043,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_7"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -9040,6 +9063,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_6"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -9059,6 +9083,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_5"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -9078,6 +9103,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_4"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -9097,6 +9123,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_3"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -9116,6 +9143,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_0"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -9135,6 +9163,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_1"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -9154,6 +9183,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_2"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; From f13271f7cc835ed4fbc09fbf2d9e89c9560984f0 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Fri, 24 Jul 2026 17:35:11 +0530 Subject: [PATCH 1281/1330] QCLINUX: arm64: dts: qcom: Install camx DTBO overlays Install Qualcomm camx DTBO overlay files by adding them to the dtb-$(CONFIG_ARCH_QCOM) build/install list. This makes DTBOs available through the standard dtbs_install flow and ensures they are included in distro kernel packages. Signed-off-by: Chandan Kumar Jha (cherry picked from commit ddb190bd411cd7cfcb0f223045aac611e694b60f) --- arch/arm64/boot/dts/qcom/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5fc63cdf6a34f..20040d00e0b47 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -521,6 +521,7 @@ dtb-$(CONFIG_ARCH_QCOM) += hamoa-evk-camx.dtbo hamoa-camx-el2-dtbs := hamoa-iot-evk-el2.dtb hamoa-evk-camx.dtbo hamoa-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += hamoa-camx-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += hamoa-camx-el2.dtbo lemans-evk-camx-dtbs := lemans-evk.dtb lemans-evk-camx.dtbo @@ -554,10 +555,12 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo purwa-evk-camx-dtbs := purwa-iot-evk.dtb purwa-evk-camx.dtbo dtb-$(CONFIG_ARCH_QCOM) += purwa-evk-camx.dtb +dtb-$(CONFIG_ARCH_QCOM) += purwa-evk-camx.dtbo purwa-camx-el2-dtbs := purwa-iot-evk-el2.dtb purwa-evk-camx.dtbo purwa-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += purwa-camx-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += purwa-camx-el2.dtbo qcs5430-fps-camx-dtbs := qcs6490-rb3gen2.dtb qcs5430-fps-camx.dtbo From 7dc8b764789088c3f48a7411c6511ea7a5c514b6 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Mon, 27 Jul 2026 13:58:01 +0800 Subject: [PATCH 1282/1330] FROMLIST: arm64: dts: qcom: purwa-evk: add DP0/DP1 audio playback support The purwa-evk DTS currently lacks DAI links for DP0 and DP1, preventing the sound card from exposing these playback paths. Add the missing links to enable audio output on both DP interfaces. Link: https://lore.kernel.org/all/20260701063003.3082899-1-le.qi@oss.qualcomm.com/ Signed-off-by: Le Qi (cherry picked from commit f92afa3aa2d7f319cd5ca88f8b37be152586cc1d) --- arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index 76dc065c1b806..a8c9746d101b1 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -633,6 +633,38 @@ sound-dai = <&q6apm>; }; }; + + dp0-dai-link { + link-name = "DP0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dp1-dai-link { + link-name = "DP1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; wcn7850-pmu { From 9cfceee15deb2021c0a16d525c80560eea8e9070 Mon Sep 17 00:00:00 2001 From: Shivam Rawat Date: Fri, 5 Jun 2026 01:38:17 +0530 Subject: [PATCH 1283/1330] FROMLIST: drm/msm/a6xx: Fix stale rpmh votes after suspend There are stale RPMH votes (BCM votes) observed after GMU suspend. This is because the rpmh stop sequences are skipped during gmu suspend. Fix this and also move GMU to reset state to avoid any further activity. Link: https://lore.kernel.org/all/20260605-assorted-fixes-june-v1-1-2caa04f7287c@oss.qualcomm.com/ Fixes: f248d5d5159a ("drm/msm/a6xx: Fix PDC sleep sequence") Signed-off-by: Akhil P Oommen Signed-off-by: Shivam Rawat Signed-off-by: Bhaskar Gusain (cherry picked from commit d63f0ed31cf0c3b708e1060686635a78e27cc719) --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 616198a836a4d..64aa4a8c6a2ab 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -642,7 +642,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) int ret; u32 val; - if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status)) + if (!test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status)) return; if (adreno_is_a840(adreno_gpu)) @@ -1465,6 +1465,9 @@ static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) /* Stop the interrupts and mask the hardware */ a6xx_gmu_irq_disable(gmu); + /* Halt the gmu cm3 core */ + gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); + /* Tell RPMh to power off the GPU */ a6xx_rpmh_stop(gmu); From 7cd1f0f7cf0cf4302cd78cfc3129548b4eec15e2 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 28 Jul 2026 11:09:21 +0800 Subject: [PATCH 1284/1330] Revert "WORKAROUND: phy: qcom: qmp-pcie: add x1e80100 qref supplies" This reverts commit a909091e359489fc0906e18942fd8e4b1404401f. Signed-off-by: Qiang Yu (cherry picked from commit 9a5bed2348e6b82deafd4d02b196355cc9be9da9) --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 9c880cd72b584..e06f4a78bc490 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4528,8 +4528,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = sm8550_qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4560,8 +4560,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = sm8550_qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4595,8 +4595,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = sm8550_qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4628,8 +4628,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = sm8550_qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, From a7679e02ad39129ff95dc70b487e21ff53608f64 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 28 Jul 2026 11:09:31 +0800 Subject: [PATCH 1285/1330] Revert "WORKAROUND: phy: qcom: qmp-pcie: Add vdda-refgen and vdda-qref supplies for Glymur" This reverts commit 74e0e79adb8edc03da93209026ae18950e691f47. Signed-off-by: Qiang Yu (cherry picked from commit dc05b06be89ac4f94757766e99419f197d300441) --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index e06f4a78bc490..7ce254bab3f39 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3387,7 +3387,7 @@ static const char * const qmp_phy_vreg_l[] = { }; static const char * const sm8550_qmp_phy_vreg_l[] = { - "vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2", "vdda-qref","vdda-qref2", + "vdda-phy", "vdda-pll", "vdda-qref", }; static const char * const sa8775p_qmp_phy_vreg_l[] = { @@ -4692,8 +4692,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = sm8550_qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v8_50_regs_layout, @@ -4710,8 +4710,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), - .vreg_list = sm8550_qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v8_regs_layout, @@ -4728,8 +4728,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg = { .num_resets = ARRAY_SIZE(glymur_pciephy_reset_l), .nocsr_reset_list = glymur_pciephy_nocsr_reset_l, .num_nocsr_resets = ARRAY_SIZE(glymur_pciephy_nocsr_reset_l), - .vreg_list = sm8550_qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v8_50_regs_layout, From 88a1a97da5d1ca82c7c9deada396a48923253839 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 28 Jul 2026 11:15:21 +0800 Subject: [PATCH 1286/1330] Revert "WORKAROUND: arm64: dts: qcom: Add qref supply for PCIe PHYs" This reverts commit cd36e0401dea99df5b083eb871cf6fdf5fb7a399. Signed-off-by: Qiang Yu (cherry picked from commit 95fb28bf2451f801d93632166b2f43e72ba972cd) --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index a0443b53b417a..6d369c319f84e 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -415,7 +415,6 @@ &pcie3_phy { vdda-phy-supply = <&vreg_l3c_0p8>; vdda-pll-supply = <&vreg_l3e_1p2>; - vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; @@ -430,7 +429,6 @@ &pcie4_phy { vdda-phy-supply = <&vreg_l3i_0p8>; vdda-pll-supply = <&vreg_l3e_1p2>; - vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; @@ -445,7 +443,6 @@ &pcie5_phy { vdda-phy-supply = <&vreg_l3i_0p8>; vdda-pll-supply = <&vreg_l3e_1p2>; - vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; @@ -460,7 +457,6 @@ &pcie6a_phy { vdda-phy-supply = <&vreg_l1d_0p8>; vdda-pll-supply = <&vreg_l2j_1p2>; - vdda-qref-supply = <&vreg_l3j_0p8>; status = "okay"; }; From ca5227ad17030a342a2b0e1df3f619d983dcec6c Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 2 Jul 2026 00:36:13 -0700 Subject: [PATCH 1287/1330] FROMLIST: clk: qcom: Add generic clkref_en support Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en register controls whether refclk is gated through to the PHY side. These clkref controls are different from typical GCC branch clocks: - only a single enable bit is present, without branch-style config bits - regulators must be voted before enable and unvoted after disable Model this as a dedicated clk_ref clock type with custom clk_ops instead of reusing struct clk_branch semantics. Also provide a common registration/probe API so the same clkref model can be reused regardless of where clkref_en registers are placed, e.g. TCSR on glymur and TLMM on SM8750. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit 586dfe140110152655b64ad1fc903e2d2f8dd276) --- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ref.c | 209 +++++++++++++++++++++++++++++++++++++ include/linux/clk/qcom.h | 67 ++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 drivers/clk/qcom/clk-ref.c create mode 100644 include/linux/clk/qcom.h diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6add2d4ac7ba3..1abc71ffe6a13 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -8,6 +8,7 @@ clk-qcom-y += clk-pll.o clk-qcom-y += clk-rcg.o clk-qcom-y += clk-rcg2.o clk-qcom-y += clk-branch.o +clk-qcom-y += clk-ref.o clk-qcom-y += clk-regmap-divider.o clk-qcom-y += clk-regmap-mux.o clk-qcom-y += clk-regmap-mux-div.o diff --git a/drivers/clk/qcom/clk-ref.c b/drivers/clk/qcom/clk-ref.c new file mode 100644 index 0000000000000..46d414614288a --- /dev/null +++ b/drivers/clk/qcom/clk-ref.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define QCOM_CLK_REF_EN_MASK BIT(0) + +struct qcom_clk_ref_provider { + struct qcom_clk_ref *refs; + size_t num_refs; +}; + +static inline struct qcom_clk_ref *to_qcom_clk_ref(struct clk_hw *hw) +{ + return container_of(hw, struct qcom_clk_ref, hw); +} + +static const struct clk_parent_data qcom_clk_ref_parent_data = { + .index = 0, +}; + +static int qcom_clk_ref_prepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); + int ret; + + if (!rclk->desc.num_regulators) + return 0; + + ret = regulator_bulk_enable(rclk->desc.num_regulators, rclk->regulators); + if (ret) + pr_err("Failed to enable regulators for %s: %d\n", + clk_hw_get_name(hw), ret); + + return ret; +} + +static void qcom_clk_ref_unprepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); + + if (rclk->desc.num_regulators) + regulator_bulk_disable(rclk->desc.num_regulators, rclk->regulators); +} + +static int qcom_clk_ref_enable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); + int ret; + + ret = regmap_set_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK); + if (ret) + return ret; + + udelay(10); + + return 0; +} + +static void qcom_clk_ref_disable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); + + regmap_clear_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK); + udelay(10); +} + +static int qcom_clk_ref_is_enabled(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw); + u32 val; + int ret; + + ret = regmap_read(rclk->regmap, rclk->desc.offset, &val); + if (ret) + return 0; + + return !!(val & QCOM_CLK_REF_EN_MASK); +} + +static const struct clk_ops qcom_clk_ref_ops = { + .prepare = qcom_clk_ref_prepare, + .unprepare = qcom_clk_ref_unprepare, + .enable = qcom_clk_ref_enable, + .disable = qcom_clk_ref_disable, + .is_enabled = qcom_clk_ref_is_enabled, +}; + +static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap, + struct qcom_clk_ref *clk_refs, + const struct qcom_clk_ref_desc * const *descs, + size_t num_clk_refs) +{ + const struct qcom_clk_ref_desc *desc; + struct clk_init_data init_data = {}; + struct qcom_clk_ref *clk_ref; + size_t clk_idx; + unsigned int i; + int ret; + + for (clk_idx = 0; clk_idx < num_clk_refs; clk_idx++) { + clk_ref = &clk_refs[clk_idx]; + desc = descs[clk_idx]; + + /* Skip unpopulated indices; the array is indexed by clock ID. */ + if (!desc) + continue; + + if (WARN_ON(!desc->name)) + continue; + + clk_ref->regmap = regmap; + clk_ref->desc = *desc; + + if (clk_ref->desc.num_regulators) { + clk_ref->regulators = devm_kcalloc(dev, clk_ref->desc.num_regulators, + sizeof(*clk_ref->regulators), + GFP_KERNEL); + if (!clk_ref->regulators) + return -ENOMEM; + + for (i = 0; i < clk_ref->desc.num_regulators; i++) + clk_ref->regulators[i].supply = + clk_ref->desc.regulator_names[i]; + + ret = devm_regulator_bulk_get(dev, clk_ref->desc.num_regulators, + clk_ref->regulators); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get regulators for %s\n", + clk_ref->desc.name); + } + + init_data.name = clk_ref->desc.name; + init_data.parent_data = &qcom_clk_ref_parent_data; + init_data.num_parents = 1; + init_data.ops = &qcom_clk_ref_ops; + clk_ref->hw.init = &init_data; + + ret = devm_clk_hw_register(dev, &clk_ref->hw); + if (ret) + return ret; + } + + return 0; +} + +static struct clk_hw *qcom_clk_ref_provider_get(struct of_phandle_args *clkspec, void *data) +{ + struct qcom_clk_ref_provider *provider = data; + unsigned int idx = clkspec->args[0]; + + if (idx >= provider->num_refs) + return ERR_PTR(-EINVAL); + + if (!provider->refs[idx].regmap) + return ERR_PTR(-ENOENT); + + return &provider->refs[idx].hw; +} + +int qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc * const *descs, + size_t num_clk_refs) +{ + struct qcom_clk_ref_provider *provider; + struct device *dev = &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + + provider->refs = devm_kcalloc(dev, num_clk_refs, sizeof(*provider->refs), + GFP_KERNEL); + if (!provider->refs) + return -ENOMEM; + + provider->num_refs = num_clk_refs; + + ret = qcom_clk_ref_register(dev, regmap, provider->refs, descs, + provider->num_refs); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, qcom_clk_ref_provider_get, provider); +} +EXPORT_SYMBOL_GPL(qcom_clk_ref_probe); diff --git a/include/linux/clk/qcom.h b/include/linux/clk/qcom.h new file mode 100644 index 0000000000000..11ac2d42ff9e1 --- /dev/null +++ b/include/linux/clk/qcom.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __LINUX_CLK_QCOM_H +#define __LINUX_CLK_QCOM_H + +#include +#include +#include +#include +#include + +struct device; +struct platform_device; +struct regulator_bulk_data; + +/** + * struct qcom_clk_ref_desc - descriptor for a clkref_en gate clock + * @name: clock name exposed to the common clock framework + * @offset: clkref_en register offset from the block base + * @regulator_names: optional supply names enabled while preparing the clock + * @num_regulators: number of entries in @regulator_names + */ +struct qcom_clk_ref_desc { + const char *name; + u32 offset; + const char * const *regulator_names; + unsigned int num_regulators; +}; + +/** + * struct qcom_clk_ref - per-clock data for a clkref_en gate clock + * @hw: common clock framework hardware clock handle + * @regmap: register map backing the clkref_en register + * @desc: clock descriptor copied at registration time + * @regulators: optional bulk regulator handles for @desc.regulator_names + */ +struct qcom_clk_ref { + struct clk_hw hw; + struct regmap *regmap; + struct qcom_clk_ref_desc desc; + struct regulator_bulk_data *regulators; +}; + +#if IS_ENABLED(CONFIG_COMMON_CLK_QCOM) + +int qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc * const *descs, + size_t num_clk_refs); + +#else + +static inline int +qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc * const *descs, + size_t num_clk_refs) +{ + return -EOPNOTSUPP; +} + +#endif + +#endif From e02784c2adb91674f0efc2e8a516c449662a1e1e Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 27 Jul 2026 02:53:25 -0700 Subject: [PATCH 1288/1330] FROMLIST: clk: qcom: tcsrcc-glymur: Add regulator supplies and migrate to clk_ref helper Replace local clk_branch-based clkref definitions with descriptor-based registration via qcom_clk_ref_probe(). This keeps the glymur driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu (cherry picked from commit e91e91005f12fd05514d6d3bfe2e756c169ebb3c) --- drivers/clk/qcom/tcsrcc-glymur.c | 360 ++++++++++--------------------- 1 file changed, 115 insertions(+), 245 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c index 215bc2ac548da..4247cc1adb05f 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -12,270 +13,137 @@ #include -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_BI_TCXO_PAD, +static const char * const glymur_tcsr_tx0_rx5_regulators[] = { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qrefrx5-0p9", + "vdda-qreftx0-0p9", + "vdda-qreftx0-1p2", }; -static struct clk_branch tcsr_edp_clkref_en = { - .halt_reg = 0x60, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x60, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_edp_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt0_rx0_regulators[] = { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrx0-0p9", }; -static struct clk_branch tcsr_pcie_1_clkref_en = { - .halt_reg = 0x48, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_pcie_1_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt01_rx1_regulators[] = { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", }; -static struct clk_branch tcsr_pcie_2_clkref_en = { - .halt_reg = 0x4c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x4c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_pcie_2_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt012_rx2_regulators[] = { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", }; -static struct clk_branch tcsr_pcie_3_clkref_en = { - .halt_reg = 0x54, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x54, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_pcie_3_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt34_rx4_regulators[] = { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt3-0p9", + "vdda-qrefrpt4-0p9", + "vdda-qrefrx4-0p9", }; -static struct clk_branch tcsr_pcie_4_clkref_en = { - .halt_reg = 0x58, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x58, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_pcie_4_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const struct regmap_config tcsr_cc_glymur_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x94, + .fast_io = true, }; -static struct clk_branch tcsr_usb2_1_clkref_en = { - .halt_reg = 0x6c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x6c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_usb2_1_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, +static const struct qcom_clk_ref_desc * const tcsr_cc_glymur_clk_descs[] = { + [TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_edp_clkref_en", + .offset = 0x60, + .regulator_names = glymur_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt0_rx0_regulators), }, -}; - -static struct clk_branch tcsr_usb2_2_clkref_en = { - .halt_reg = 0x70, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x70, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_usb2_2_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_PCIE_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_1_clkref_en", + .offset = 0x48, + .regulator_names = glymur_tcsr_tx0_rx5_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators), }, -}; - -static struct clk_branch tcsr_usb2_3_clkref_en = { - .halt_reg = 0x74, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x74, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_usb2_3_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_PCIE_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_2_clkref_en", + .offset = 0x4c, + .regulator_names = glymur_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb2_4_clkref_en = { - .halt_reg = 0x88, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x88, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_usb2_4_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_PCIE_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_3_clkref_en", + .offset = 0x54, + .regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), }, -}; - -static struct clk_branch tcsr_usb3_0_clkref_en = { - .halt_reg = 0x64, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x64, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_usb3_0_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_PCIE_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_4_clkref_en", + .offset = 0x58, + .regulator_names = glymur_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb3_1_clkref_en = { - .halt_reg = 0x68, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x68, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_usb3_1_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_1_clkref_en", + .offset = 0x6c, + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), }, -}; - -static struct clk_branch tcsr_usb4_1_clkref_en = { - .halt_reg = 0x44, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x44, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_usb4_1_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_2_clkref_en", + .offset = 0x70, + .regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), }, -}; - -static struct clk_branch tcsr_usb4_2_clkref_en = { - .halt_reg = 0x5c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_usb4_2_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_USB2_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_3_clkref_en", + .offset = 0x74, + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), + }, + [TCSR_USB2_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_4_clkref_en", + .offset = 0x88, + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), + }, + [TCSR_USB3_0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb3_0_clkref_en", + .offset = 0x64, + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), + }, + [TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb3_1_clkref_en", + .offset = 0x68, + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), + }, + [TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb4_1_clkref_en", + .offset = 0x44, + .regulator_names = glymur_tcsr_tx0_rx5_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators), + }, + [TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb4_2_clkref_en", + .offset = 0x5c, + .regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), }, -}; - -static struct clk_regmap *tcsr_cc_glymur_clocks[] = { - [TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr, - [TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr, - [TCSR_PCIE_2_CLKREF_EN] = &tcsr_pcie_2_clkref_en.clkr, - [TCSR_PCIE_3_CLKREF_EN] = &tcsr_pcie_3_clkref_en.clkr, - [TCSR_PCIE_4_CLKREF_EN] = &tcsr_pcie_4_clkref_en.clkr, - [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr, - [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr, - [TCSR_USB2_3_CLKREF_EN] = &tcsr_usb2_3_clkref_en.clkr, - [TCSR_USB2_4_CLKREF_EN] = &tcsr_usb2_4_clkref_en.clkr, - [TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr, - [TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr, - [TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr, - [TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr, -}; - -static const struct regmap_config tcsr_cc_glymur_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x94, - .fast_io = true, -}; - -static const struct qcom_cc_desc tcsr_cc_glymur_desc = { - .config = &tcsr_cc_glymur_regmap_config, - .clks = tcsr_cc_glymur_clocks, - .num_clks = ARRAY_SIZE(tcsr_cc_glymur_clocks), }; static const struct of_device_id tcsr_cc_glymur_match_table[] = { @@ -286,7 +154,9 @@ MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table); static int tcsr_cc_glymur_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &tcsr_cc_glymur_desc); + return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config, + tcsr_cc_glymur_clk_descs, + ARRAY_SIZE(tcsr_cc_glymur_clk_descs)); } static struct platform_driver tcsr_cc_glymur_driver = { From dfb0deebb3baba69a83bfd68a6739a86f89f93ed Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 2 Jul 2026 00:36:15 -0700 Subject: [PATCH 1289/1330] FROMLIST: clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support Mahua is based on Glymur but uses a different QREF topology, requiring distinct regulator lists and clock descriptors for its PCIe clock references. Add mahua-specific regulator arrays and clk descriptor table, and use match_data to select the correct descriptor table per compatible string at probe time. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit 2ad10ecde93a900d529e85aec20103800f2c2c2e) --- drivers/clk/qcom/tcsrcc-glymur.c | 136 ++++++++++++++++++++++++++++++- 1 file changed, 133 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c index 4247cc1adb05f..31b691bb7f853 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -13,6 +13,11 @@ #include +struct tcsrcc_glymur_data { + const struct qcom_clk_ref_desc * const *descs; + size_t num_descs; +}; + static const char * const glymur_tcsr_tx0_rx5_regulators[] = { "vdda-refgen3-0p9", "vdda-refgen3-1p2", @@ -57,6 +62,43 @@ static const char * const glymur_tcsr_tx1_rpt34_rx4_regulators[] = { "vdda-qrefrx4-0p9", }; +static const char * const mahua_tcsr_tx1_rpt01_rx1_regulators[] = { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", +}; + +static const char * const mahua_tcsr_tx1_rpt012_rx2_regulators[] = { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", +}; + +static const char * const mahua_tcsr_tx1_rpt0_rx0_regulators[] = { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrx0-0p9", +}; + +static const char * const mahua_tcsr_tx1_rpt345_rx3_regulators[] = { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt3-0p9", + "vdda-qrefrpt4-0p9", + "vdda-qrefrpt5-0p9", + "vdda-qrefrx3-0p9", +}; + static const struct regmap_config tcsr_cc_glymur_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -146,17 +188,105 @@ static const struct qcom_clk_ref_desc * const tcsr_cc_glymur_clk_descs[] = { }, }; +static const struct qcom_clk_ref_desc * const tcsr_cc_mahua_clk_descs[] = { + [TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_edp_clkref_en", + .offset = 0x60, + .regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators), + }, + [TCSR_PCIE_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_2_clkref_en", + .offset = 0x4c, + .regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, + [TCSR_PCIE_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_3_clkref_en", + .offset = 0x54, + .regulator_names = mahua_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators), + }, + [TCSR_PCIE_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_4_clkref_en", + .offset = 0x58, + .regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, + [TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_1_clkref_en", + .offset = 0x6c, + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_2_clkref_en", + .offset = 0x70, + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB2_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_3_clkref_en", + .offset = 0x74, + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB2_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_4_clkref_en", + .offset = 0x88, + .regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators), + }, + [TCSR_USB3_0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb3_0_clkref_en", + .offset = 0x64, + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb3_1_clkref_en", + .offset = 0x68, + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb4_1_clkref_en", + .offset = 0x44, + }, + [TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb4_2_clkref_en", + .offset = 0x5c, + .regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, +}; + +static const struct tcsrcc_glymur_data tcsr_cc_glymur_data = { + .descs = tcsr_cc_glymur_clk_descs, + .num_descs = ARRAY_SIZE(tcsr_cc_glymur_clk_descs), +}; + +static const struct tcsrcc_glymur_data tcsr_cc_mahua_data = { + .descs = tcsr_cc_mahua_clk_descs, + .num_descs = ARRAY_SIZE(tcsr_cc_mahua_clk_descs), +}; + static const struct of_device_id tcsr_cc_glymur_match_table[] = { - { .compatible = "qcom,glymur-tcsr" }, + { .compatible = "qcom,glymur-tcsr", .data = &tcsr_cc_glymur_data }, + { .compatible = "qcom,mahua-tcsr", .data = &tcsr_cc_mahua_data }, { } }; MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table); static int tcsr_cc_glymur_probe(struct platform_device *pdev) { + const struct tcsrcc_glymur_data *data = device_get_match_data(&pdev->dev); + + if (!data) + return -ENODEV; + return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config, - tcsr_cc_glymur_clk_descs, - ARRAY_SIZE(tcsr_cc_glymur_clk_descs)); + data->descs, data->num_descs); } static struct platform_driver tcsr_cc_glymur_driver = { From fb2c2a2de66768d68504dec76ea31d19522ffa5c Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 7 Jul 2026 21:12:10 -0700 Subject: [PATCH 1290/1330] FROMLIST: dt-bindings: clock: qcom: Move x1e80100 TCSR to own binding The QREF block supplies reference clocks to PCIe/USB/UFS PHYs and requires dedicated LDO supplies to operate. The digital control interface for QREF (clkref_en registers) resides in TCSR on x1e80100. Since QREF has no dedicated DT node of its own, these supply properties are placed in the TCSR node which acts as the control interface for QREF. Add a dedicated binding file for qcom,x1e80100-tcsr and document the supply properties. Link: https://lore.kernel.org/all/20260714-hamoa_tcsr_qref_0714_2-v1-1-13047922a376@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit ff3270a94d5b301b4ff3db0ce6c2f1e730f5f5cb) --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 1 - .../bindings/clock/qcom,x1e80100-tcsr.yaml | 118 ++++++++++++++++++ 2 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,x1e80100-tcsr.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 784fef8306812..2a8bbc420d1e7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -31,7 +31,6 @@ properties: - qcom,sm8550-tcsr - qcom,sm8650-tcsr - qcom,sm8750-tcsr - - qcom,x1e80100-tcsr - const: syscon clocks: diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-tcsr.yaml new file mode 100644 index 0000000000000..55182cf550e7d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-tcsr.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,x1e80100-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on X1E80100 + +maintainers: + - Bjorn Andersson + - Taniya Das + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on X1E80100 + + See also: + - include/dt-bindings/clock/qcom,x1e80100-tcsr.h + +properties: + compatible: + items: + - enum: + - qcom,x1e80100-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + vdda-qrefrpt0-0p9-supply: true + vdda-qrefrpt1-0p9-supply: true + vdda-qrefrpt2-0p9-supply: true + vdda-qrefrpt3-0p9-supply: true + vdda-qrefrpt4-0p9-supply: true + vdda-qrefrx0-0p9-supply: true + vdda-qrefrx1-0p9-supply: true + vdda-qrefrx2-0p9-supply: true + vdda-qrefrx3-0p9-supply: true + vdda-qrefrx4-0p9-supply: true + vdda-qreftx0-0p9-supply: true + vdda-qreftx0-1p2-supply: true + vdda-qreftx1-0p9-supply: true + vdda-qreftx1-1p2-supply: true + vdda-refgen0-0p9-supply: true + vdda-refgen0-1p2-supply: true + vdda-refgen2-0p9-supply: true + vdda-refgen2-1p2-supply: true + +required: + - compatible + - clocks + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrx0-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx3-0p9-supply + - vdda-qrefrx4-0p9-supply + - vdda-qreftx0-0p9-supply + - vdda-qreftx0-1p2-supply + - vdda-qreftx1-0p9-supply + - vdda-qreftx1-1p2-supply + - vdda-refgen0-0p9-supply + - vdda-refgen0-1p2-supply + - vdda-refgen2-0p9-supply + - vdda-refgen2-1p2-supply + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@1fc0000 { + compatible = "qcom,x1e80100-tcsr", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + vdda-qrefrpt0-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt1-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt2-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt3-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1a>; + vdda-qrefrx0-0p9-supply = <&vreg_l1a>; + vdda-qrefrx1-0p9-supply = <&vreg_l1a>; + vdda-qrefrx2-0p9-supply = <&vreg_l1a>; + vdda-qrefrx3-0p9-supply = <&vreg_l1a>; + vdda-qrefrx4-0p9-supply = <&vreg_l1a>; + vdda-qreftx0-0p9-supply = <&vreg_l1a>; + vdda-qreftx0-1p2-supply = <&vreg_l2a>; + vdda-qreftx1-0p9-supply = <&vreg_l1a>; + vdda-qreftx1-1p2-supply = <&vreg_l2a>; + vdda-refgen0-0p9-supply = <&vreg_l1a>; + vdda-refgen0-1p2-supply = <&vreg_l2a>; + vdda-refgen2-0p9-supply = <&vreg_l1a>; + vdda-refgen2-1p2-supply = <&vreg_l2a>; + }; + }; + +... From 5048efdb343c329ce555f3926fb1532adf488e79 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 27 Jul 2026 03:00:12 -0700 Subject: [PATCH 1291/1330] FROMLIST: clk: qcom: tcsrcc-x1e80100: Migrate to clk_ref helper Replace local clk_branch-based clkref definitions with descriptor-based registration via qcom_clk_ref_probe(). This keeps the x1e80100 driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Link: https://lore.kernel.org/all/20260714-hamoa_tcsr_qref_0714_2-v1-2-13047922a376@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit a2879d5beb397d9569f4600df099336a7d3409b5) --- drivers/clk/qcom/tcsrcc-x1e80100.c | 335 ++++++++++------------------- 1 file changed, 113 insertions(+), 222 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-x1e80100.c b/drivers/clk/qcom/tcsrcc-x1e80100.c index a367e1f55622d..8d8ec7df007eb 100644 --- a/drivers/clk/qcom/tcsrcc-x1e80100.c +++ b/drivers/clk/qcom/tcsrcc-x1e80100.c @@ -5,253 +5,142 @@ */ #include +#include #include #include +#include #include #include #include -#include "clk-branch.h" -#include "clk-regmap.h" -#include "common.h" -#include "reset.h" - -enum { - DT_BI_TCXO_PAD, +static const char * const x1e80100_tcsr_tx1_rpt0_rx0_regulators[] = { + "vdda-refgen0-0p9", + "vdda-refgen0-1p2", + "vdda-qreftx1-0p9", + "vdda-qreftx1-1p2", + "vdda-qrefrpt0-0p9", + "vdda-qrefrx0-0p9", }; -static struct clk_branch tcsr_edp_clkref_en = { - .halt_reg = 0x15130, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15130, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "tcsr_edp_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const char * const x1e80100_tcsr_tx1_rpt1_rx1_regulators[] = { + "vdda-refgen0-0p9", + "vdda-refgen0-1p2", + "vdda-qreftx1-0p9", + "vdda-qreftx1-1p2", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", }; -static struct clk_branch tcsr_pcie_2l_4_clkref_en = { - .halt_reg = 0x15100, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15100, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_pcie_2l_4_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const char * const x1e80100_tcsr_tx1_rpt12_rx2_regulators[] = { + "vdda-refgen0-0p9", + "vdda-refgen0-1p2", + "vdda-qreftx1-0p9", + "vdda-qreftx1-1p2", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", }; -static struct clk_branch tcsr_pcie_2l_5_clkref_en = { - .halt_reg = 0x15104, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15104, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_pcie_2l_5_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const char * const x1e80100_tcsr_tx0_rpt3_rx3_regulators[] = { + "vdda-refgen2-0p9", + "vdda-refgen2-1p2", + "vdda-qreftx0-0p9", + "vdda-qreftx0-1p2", + "vdda-qrefrpt3-0p9", + "vdda-qrefrx3-0p9", }; -static struct clk_branch tcsr_pcie_8l_clkref_en = { - .halt_reg = 0x15108, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15108, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_pcie_8l_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const char * const x1e80100_tcsr_tx0_rpt4_rx4_regulators[] = { + "vdda-refgen2-0p9", + "vdda-refgen2-1p2", + "vdda-qreftx0-0p9", + "vdda-qreftx0-1p2", + "vdda-qrefrpt4-0p9", + "vdda-qrefrx4-0p9", }; -static struct clk_branch tcsr_usb3_mp0_clkref_en = { - .halt_reg = 0x1510c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1510c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_usb3_mp0_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, +static const struct regmap_config tcsr_cc_x1e80100_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x2f000, + .fast_io = true, }; -static struct clk_branch tcsr_usb3_mp1_clkref_en = { - .halt_reg = 0x15110, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15110, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_usb3_mp1_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, +static const struct qcom_clk_ref_desc * const tcsr_cc_x1e80100_clk_descs[] = { + [TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_edp_clkref_en", + .offset = 0x15130, + .regulator_names = x1e80100_tcsr_tx0_rpt3_rx3_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt3_rx3_regulators), }, -}; - -static struct clk_branch tcsr_usb2_1_clkref_en = { - .halt_reg = 0x15114, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15114, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_usb2_1_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_PCIE_2L_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_2l_4_clkref_en", + .offset = 0x15100, + .regulator_names = x1e80100_tcsr_tx1_rpt1_rx1_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt1_rx1_regulators), }, -}; - -static struct clk_branch tcsr_ufs_phy_clkref_en = { - .halt_reg = 0x15118, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15118, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_ufs_phy_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_PCIE_2L_5_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_2l_5_clkref_en", + .offset = 0x15104, + .regulator_names = x1e80100_tcsr_tx1_rpt12_rx2_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt12_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb4_1_clkref_en = { - .halt_reg = 0x15120, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15120, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_usb4_1_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_PCIE_8L_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_8l_clkref_en", + .offset = 0x15108, + .regulator_names = x1e80100_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt0_rx0_regulators), }, -}; - -static struct clk_branch tcsr_usb4_2_clkref_en = { - .halt_reg = 0x15124, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15124, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_usb4_2_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_USB3_MP0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb3_mp0_clkref_en", + .offset = 0x1510c, + .regulator_names = x1e80100_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt0_rx0_regulators), }, -}; - -static struct clk_branch tcsr_usb2_2_clkref_en = { - .halt_reg = 0x15128, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x15128, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_usb2_2_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_USB3_MP1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb3_mp1_clkref_en", + .offset = 0x15110, + .regulator_names = x1e80100_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt0_rx0_regulators), }, -}; - -static struct clk_branch tcsr_pcie_4l_clkref_en = { - .halt_reg = 0x1512c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1512c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "tcsr_pcie_4l_clkref_en", - .parent_data = &(const struct clk_parent_data){ - .index = DT_BI_TCXO_PAD, - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, + [TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_1_clkref_en", + .offset = 0x15114, + .regulator_names = x1e80100_tcsr_tx0_rpt3_rx3_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt3_rx3_regulators), + }, + [TCSR_UFS_PHY_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_ufs_phy_clkref_en", + .offset = 0x15118, + .regulator_names = x1e80100_tcsr_tx1_rpt12_rx2_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt12_rx2_regulators), + }, + [TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb4_1_clkref_en", + .offset = 0x15120, + .regulator_names = x1e80100_tcsr_tx0_rpt4_rx4_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt4_rx4_regulators), + }, + [TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb4_2_clkref_en", + .offset = 0x15124, + .regulator_names = x1e80100_tcsr_tx0_rpt3_rx3_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt3_rx3_regulators), + }, + [TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_usb2_2_clkref_en", + .offset = 0x15128, + .regulator_names = x1e80100_tcsr_tx0_rpt3_rx3_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt3_rx3_regulators), + }, + [TCSR_PCIE_4L_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { + .name = "tcsr_pcie_4l_clkref_en", + .offset = 0x1512c, + .regulator_names = x1e80100_tcsr_tx0_rpt4_rx4_regulators, + .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt4_rx4_regulators), }, -}; - -static struct clk_regmap *tcsr_cc_x1e80100_clocks[] = { - [TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr, - [TCSR_PCIE_2L_4_CLKREF_EN] = &tcsr_pcie_2l_4_clkref_en.clkr, - [TCSR_PCIE_2L_5_CLKREF_EN] = &tcsr_pcie_2l_5_clkref_en.clkr, - [TCSR_PCIE_8L_CLKREF_EN] = &tcsr_pcie_8l_clkref_en.clkr, - [TCSR_USB3_MP0_CLKREF_EN] = &tcsr_usb3_mp0_clkref_en.clkr, - [TCSR_USB3_MP1_CLKREF_EN] = &tcsr_usb3_mp1_clkref_en.clkr, - [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr, - [TCSR_UFS_PHY_CLKREF_EN] = &tcsr_ufs_phy_clkref_en.clkr, - [TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr, - [TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr, - [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr, - [TCSR_PCIE_4L_CLKREF_EN] = &tcsr_pcie_4l_clkref_en.clkr, -}; - -static const struct regmap_config tcsr_cc_x1e80100_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x2f000, - .fast_io = true, -}; - -static const struct qcom_cc_desc tcsr_cc_x1e80100_desc = { - .config = &tcsr_cc_x1e80100_regmap_config, - .clks = tcsr_cc_x1e80100_clocks, - .num_clks = ARRAY_SIZE(tcsr_cc_x1e80100_clocks), }; static const struct of_device_id tcsr_cc_x1e80100_match_table[] = { @@ -262,7 +151,9 @@ MODULE_DEVICE_TABLE(of, tcsr_cc_x1e80100_match_table); static int tcsr_cc_x1e80100_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &tcsr_cc_x1e80100_desc); + return qcom_clk_ref_probe(pdev, &tcsr_cc_x1e80100_regmap_config, + tcsr_cc_x1e80100_clk_descs, + ARRAY_SIZE(tcsr_cc_x1e80100_clk_descs)); } static struct platform_driver tcsr_cc_x1e80100_driver = { From a3be16710e928f56ddcc9bdc45a06c08774715da Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 2 Jul 2026 00:36:11 -0700 Subject: [PATCH 1292/1330] FROMLIST: dt-bindings: clock: qcom: Move glymur TCSR to own binding The QREF block supplies reference clocks to PCIe PHYs and requires dedicated LDO supplies to operate. The digital control interface for QREF (clkref_en registers) resides in TCSR on glymur. Since QREF has no dedicated DT node of its own, these supply properties are placed in the TCSR node which acts as the control interface for QREF. Add a dedicated binding file for qcom,glymur-tcsr and document the supply properties. As this binding will grow to cover more SoCs, mark the required supplies per compatible using an allOf/if/then conditional. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit 625f6023903b26c1714f207085650ddb53f1dc1b) --- .../bindings/clock/qcom,glymur-tcsr.yaml | 126 ++++++++++++++++++ .../bindings/clock/qcom,sm8550-tcsr.yaml | 2 - 2 files changed, 126 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml new file mode 100644 index 0000000000000..ec89feff89e4e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on Glymur + +maintainers: + - Bjorn Andersson + - Taniya Das + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on Glymur + + See also: + - include/dt-bindings/clock/qcom,glymur-tcsr.h + +properties: + compatible: + items: + - enum: + - qcom,glymur-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + vdda-qrefrpt0-0p9-supply: true + vdda-qrefrpt1-0p9-supply: true + vdda-qrefrpt2-0p9-supply: true + vdda-qrefrpt3-0p9-supply: true + vdda-qrefrpt4-0p9-supply: true + vdda-qrefrpt5-0p9-supply: true + vdda-qrefrx0-0p9-supply: true + vdda-qrefrx1-0p9-supply: true + vdda-qrefrx2-0p9-supply: true + vdda-qrefrx3-0p9-supply: true + vdda-qrefrx4-0p9-supply: true + vdda-qrefrx5-0p9-supply: true + vdda-qreftx0-0p9-supply: true + vdda-qreftx0-1p2-supply: true + vdda-qreftx1-0p9-supply: true + vdda-refgen3-0p9-supply: true + vdda-refgen3-1p2-supply: true + vdda-refgen4-0p9-supply: true + vdda-refgen4-1p2-supply: true + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,glymur-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrx0-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx4-0p9-supply + - vdda-qrefrx5-0p9-supply + - vdda-qreftx0-0p9-supply + - vdda-qreftx0-1p2-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply + - vdda-refgen4-0p9-supply + - vdda-refgen4-1p2-supply + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@1fd5000 { + compatible = "qcom,glymur-tcsr", "syscon"; + reg = <0x0 0x1fd5000 0x0 0x21000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + vdda-qrefrpt0-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt1-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt2-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt3-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1a>; + vdda-qrefrx0-0p9-supply = <&vreg_l1a>; + vdda-qrefrx1-0p9-supply = <&vreg_l1a>; + vdda-qrefrx2-0p9-supply = <&vreg_l1a>; + vdda-qrefrx4-0p9-supply = <&vreg_l1a>; + vdda-qrefrx5-0p9-supply = <&vreg_l1a>; + vdda-qreftx0-0p9-supply = <&vreg_l1a>; + vdda-qreftx0-1p2-supply = <&vreg_l2a>; + vdda-qreftx1-0p9-supply = <&vreg_l1a>; + vdda-refgen3-0p9-supply = <&vreg_l1a>; + vdda-refgen3-1p2-supply = <&vreg_l2a>; + vdda-refgen4-0p9-supply = <&vreg_l1a>; + vdda-refgen4-1p2-supply = <&vreg_l2a>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 2a8bbc420d1e7..2139ba8938d31 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -15,7 +15,6 @@ description: | power domains on SM8550 See also: - - include/dt-bindings/clock/qcom,glymur-tcsr.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h - include/dt-bindings/clock/qcom,sm8750-tcsr.h @@ -24,7 +23,6 @@ properties: compatible: items: - enum: - - qcom,glymur-tcsr - qcom,kaanapali-tcsr - qcom,milos-tcsr - qcom,sar2130p-tcsr From aea24187c6a7a93844c0921565bf5dce46d8dfd0 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 2 Jul 2026 00:36:12 -0700 Subject: [PATCH 1293/1330] FROMLIST: dt-bindings: clock: qcom,glymur-tcsr: Add mahua support Mahua shares the same QREF TX/RPT/RX component naming as Glymur, but has a different topology: a single QREF block fed by REFGEN4 only, rather than the two independent blocks fed by REFGEN3 and REFGEN4 on Glymur. Add qcom,mahua-tcsr compatible and document its required supply properties. Note that REFGEN4 is supplied by regulators vdda-refgen3-1p2 and vdda-refgen3-0p9 on Mahua. List: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit 7df2ceed11f2e6d0c3bfeb79812c564d8ca79aa9) --- .../bindings/clock/qcom,glymur-tcsr.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml index ec89feff89e4e..2b64226271657 100644 --- a/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml @@ -22,6 +22,7 @@ properties: items: - enum: - qcom,glymur-tcsr + - qcom,mahua-tcsr - const: syscon clocks: @@ -82,6 +83,25 @@ allOf: - vdda-refgen3-1p2-supply - vdda-refgen4-0p9-supply - vdda-refgen4-1p2-supply + - if: + properties: + compatible: + contains: + const: qcom,mahua-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrpt5-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx3-0p9-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply required: - compatible From b348fa6fb4e1036335c255a961f305f414ea309e Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 23 Jun 2026 06:05:19 -0700 Subject: [PATCH 1294/1330] FROMLIST: arm64: dts: qcom: glymur-crd: Add refgen supplies for PCIe PHY on Glymur The PCIe PHYs on Glymur require a reference voltage provided by REFGEN, which in turn is powered by two LDOs. Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and vdda-refgen1p2 supplies for each PCIe PHY node. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit 1054d87ad6585cfeb37cb1f49710e64a308bc4f1) --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 44c83a6a52c54..e99e8110a28c3 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -747,6 +747,8 @@ &pcie3b_phy { vdda-phy-supply = <&vreg_l3c_e1_0p89>; vdda-pll-supply = <&vreg_l2c_e1_1p14>; + vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>; + vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>; }; &pcie3b_port0 { @@ -764,6 +766,8 @@ &pcie4_phy { vdda-phy-supply = <&vreg_l1c_e1_0p82>; vdda-pll-supply = <&vreg_l4f_e1_1p08>; + vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>; + vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>; status = "okay"; }; @@ -800,6 +804,8 @@ &pcie5_phy { vdda-phy-supply = <&vreg_l2f_e0_0p82>; vdda-pll-supply = <&vreg_l4h_e0_1p2>; + vdda-refgen0p9-supply = <&vreg_l2f_e0_0p82>; + vdda-refgen1p2-supply = <&vreg_l4h_e0_1p2>; status = "okay"; }; @@ -821,6 +827,8 @@ &pcie6_phy { vdda-phy-supply = <&vreg_l1c_e1_0p82>; vdda-pll-supply = <&vreg_l4f_e1_1p08>; + vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>; + vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>; status = "okay"; }; From 505b0df1b9580f482e66a1450c282f90619bcc99 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 2 Jul 2026 00:36:16 -0700 Subject: [PATCH 1295/1330] FROMLIST: arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR The TCSR clkref_en clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu (cherry picked from commit c98d2abea60c7610ce02c82e02c115e595e63812) --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 0efd9e27c82f6..8aa346ac1694f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -12,3 +12,23 @@ model = "Qualcomm Technologies, Inc. Glymur CRD"; compatible = "qcom,glymur-crd", "qcom,glymur"; }; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx4-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0_0p72>; + vdda-qreftx0-0p9-supply = <&vreg_l3f_e0_0p72>; + vdda-qreftx0-1p2-supply = <&vreg_l4h_e0_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen3-0p9-supply = <&vreg_l2f_e0_0p82>; + vdda-refgen3-1p2-supply = <&vreg_l4h_e0_1p2>; + vdda-refgen4-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen4-1p2-supply = <&vreg_l4f_e1_1p08>; +}; From b29fd085b86f8cd3c4693aecc9ec9c6ea10d8cea Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 2 Jul 2026 00:36:17 -0700 Subject: [PATCH 1296/1330] FROMLIST: arm64: dts: qcom: mahua: Add QREF regulator supplies to TCSR Mahua has a different QREF topology from Glymur. Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies on the CRD board. Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk from the CXO0 pad directly and requires no QREF clkref_en voting. Hence, point its ref clock at RPMH_CXO_CLK. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit d7ec83a786eb65098584e044c598f8130d3919f0) --- arch/arm64/boot/dts/qcom/mahua-crd.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/mahua.dtsi | 13 +++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts index 9c8244e892ddd..fa5229064b10e 100644 --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -19,3 +19,19 @@ model = "Qualcomm Technologies, Inc. Mahua CRD"; compatible = "qcom,mahua-crd", "qcom,mahua"; }; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrpt5-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx3-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen3-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen3-1p2-supply = <&vreg_l4f_e1_1p08>; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi index 582a11b37189a..c417bc98c2c7a 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -115,6 +115,15 @@ compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; }; +&pcie5_phy { + clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; +}; + &pcie_east_anoc { compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; }; @@ -286,6 +295,10 @@ }; }; +&tcsr { + compatible = "qcom,mahua-tcsr", "syscon"; +}; + &tlmm { compatible = "qcom,mahua-tlmm"; }; From 408bd1872fec3c5f0bf47c479b9076de27588b99 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 8 Jul 2026 01:12:22 -0700 Subject: [PATCH 1297/1330] FROMLIST: arm64: dts: qcom: hamoa/purwa: Add QREF regulator supplies Wire up the LDO supplies required by the QREF and refgen blocks on Purwa and Hamoa boards. Purwa's QREF topology is same as Hamoa's, so it reuses the same qcom,x1e80100-tcsr compatible and supply set rather than needing a dedicated one. Link: https://lore.kernel.org/linux-arm-msm/20260714-hamoa_tcsr_qref_0714_2-v1-3-13047922a376@oss.qualcomm.com/ Signed-off-by: Qiang Yu (cherry picked from commit 68cee8603520f89f6df3c96095be37912e0eab3e) --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 21 +++++++++++++++++++ arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 21 +++++++++++++++++++ .../boot/dts/qcom/x1-asus-vivobook-s15.dtsi | 21 +++++++++++++++++++ .../boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 21 +++++++++++++++++++ arch/arm64/boot/dts/qcom/x1-crd.dtsi | 21 +++++++++++++++++++ arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 21 +++++++++++++++++++ .../boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 21 +++++++++++++++++++ .../boot/dts/qcom/x1-microsoft-denali.dtsi | 21 +++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 21 +++++++++++++++++++ .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 21 +++++++++++++++++++ .../dts/qcom/x1e80100-dell-xps13-9345.dts | 21 +++++++++++++++++++ .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 21 +++++++++++++++++++ .../qcom/x1e80100-medion-sprchrgd-14-s1.dts | 21 +++++++++++++++++++ .../dts/qcom/x1e80100-microsoft-romulus.dtsi | 21 +++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 21 +++++++++++++++++++ .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 21 +++++++++++++++++++ 16 files changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 6d369c319f84e..373fa5826951a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -493,6 +493,27 @@ status = "okay"; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index cc30ad746df83..59f8fd225ce42 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -475,6 +475,27 @@ status = "okay"; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* TPM LP & INT */ <44 4>; /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi index bae6bb4f03d82..cc896e13db9f8 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi @@ -1036,6 +1036,27 @@ vdd3-supply = <&vreg_l14b_3p0>; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index ca63130466524..36cde43d93125 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -1310,6 +1310,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11, TZ Protected */ <90 1>; /* Unknown, TZ Protected */ diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 84b1860bc66a6..1c41adefa3e37 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1705,6 +1705,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index ebe53046750ca..521dfa8797b3f 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -1366,6 +1366,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ <76 4>, /* SPI19 (TZ Protected) */ diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi index 41063948c583d..a22a427b28ca7 100644 --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -1284,6 +1284,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi index ba6b7b5a91918..8863de9a6006a 100644 --- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -1108,6 +1108,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index d5a60671a3837..a7dc7e731a685 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1193,6 +1193,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>; /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index deaabba8ff103..a0bb9b0dca8ee 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1638,6 +1638,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index cd7018c4995ff..12a1a90084a93 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -1295,6 +1295,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ <76 4>, /* SPI19 (TZ Protected) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 5a27914f5cfa1..7cd8fc553d144 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1482,6 +1482,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts index eec5f2f1f75d6..57ae24da87c79 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -1248,6 +1248,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <28 4>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 37539a09b76ea..63b439a661b65 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -1323,6 +1323,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d>; + vdda-qreftx0-0p9-supply = <&vreg_l3j>; + vdda-qreftx0-1p2-supply = <&vreg_l2j>; + vdda-qreftx1-0p9-supply = <&vreg_l3j>; + vdda-qreftx1-1p2-supply = <&vreg_l3e>; + vdda-refgen0-0p9-supply = <&vreg_l3i>; + vdda-refgen0-1p2-supply = <&vreg_l3e>; + vdda-refgen2-0p9-supply = <&vreg_l3j>; + vdda-refgen2-1p2-supply = <&vreg_l2j>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 1d402ef865124..4105d2d0154b4 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -1177,6 +1177,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 06747b54a38e4..bd2873090193c 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -1324,6 +1324,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <72 2>; /* Secure EC I2C connection (?) */ From a2752ab8925b4ce704ca1f0f2d94e22dc386cd7d Mon Sep 17 00:00:00 2001 From: Bjordis Collaku Date: Tue, 7 Jul 2026 10:33:40 -0700 Subject: [PATCH 1298/1330] ci: add pre-merge PR build check on resolute-qcom-devel Adds .github/workflows/premerge-pr.yml: a pull_request check that builds every PR into resolute-qcom-devel (the merge ref, build-only) via the reusable build-kernel.yml on main. It lives on this branch because GitHub resolves pull_request workflows from the PR base branch, not the default branch. Depends on the workflow_call interface in qualcomm-linux/pkg-linux-qcom-canonical#25; do not merge until #25 lands on main. Signed-off-by: Bjordis Collaku (cherry picked from commit 998080babfae24aa22e61ec31bd0ba1f8b99211f) --- .github/workflows/premerge-pr.yml | 37 +++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 .github/workflows/premerge-pr.yml diff --git a/.github/workflows/premerge-pr.yml b/.github/workflows/premerge-pr.yml new file mode 100644 index 0000000000000..38cba7e8812f5 --- /dev/null +++ b/.github/workflows/premerge-pr.yml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: BSD-3-Clause +# +# premerge-pr.yml - pre-merge validation build for resolute-qcom-devel. +# Lives on resolute-qcom-devel (GitHub resolves pull_request workflows from the PR +# base branch). Thin caller of the reusable build-kernel.yml on main. Rationale +# and security note: docs/PIPELINE.md#pre-merge-validation. +# +# Security: uses pull_request (NOT pull_request_target), so the run gets a +# read-only token and no secrets, and it builds the PR MERGE REF - never a raw +# attacker head under an elevated token. Contributor PRs come from forks, so the +# build runs untrusted PR code on the credentialed self-hosted runner: the repo +# MUST enable "Require approval for all fork pull requests" (Settings > Actions) +# so a maintainer gates every run. + +name: "Pre-merge PR build" + +on: + pull_request: + branches: + - resolute-qcom-devel + types: [opened, synchronize, reopened] + +permissions: + contents: read + +concurrency: + group: premerge-pr-${{ github.event.pull_request.number }} + cancel-in-progress: true + +jobs: + build: + name: "Build check" + uses: qualcomm-linux/pkg-linux-qcom-canonical/.github/workflows/build-kernel.yml@main + with: + suite: resolute-qcom-devel + ref: refs/pull/${{ github.event.pull_request.number }}/merge + skip_s3: true From d03c01d9de84152e0f69678f2125ca2c08fe2304 Mon Sep 17 00:00:00 2001 From: Bjordis Collaku Date: Wed, 15 Jul 2026 16:11:39 -0700 Subject: [PATCH 1299/1330] ci: add Qualcomm copyright header to premerge-pr.yml Add the Qualcomm Technologies copyright line above the existing SPDX-License-Identifier tag, matching the header format used in LICENSE.txt and the other .github/workflows/*.yml files. Signed-off-by: Bjordis Collaku (cherry picked from commit 72ba94691c2469295695070a33f05b778489bf9b) --- .github/workflows/premerge-pr.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/premerge-pr.yml b/.github/workflows/premerge-pr.yml index 38cba7e8812f5..60b5dfdf36cc0 100644 --- a/.github/workflows/premerge-pr.yml +++ b/.github/workflows/premerge-pr.yml @@ -1,3 +1,4 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. # SPDX-License-Identifier: BSD-3-Clause # # premerge-pr.yml - pre-merge validation build for resolute-qcom-devel. From ce3a56a0ea71d230e34f9c8409d89bdfeeb5c5eb Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Thu, 30 Jul 2026 17:47:51 +0800 Subject: [PATCH 1300/1330] Revert "PENDING: media: qcom: iris: move hwmode setup into power_on_hw sequence" This reverts commit 64ba9c970d3d1db7e05499e3b260cf33dd95a6c7. This commit was previously a workaround for a video firmware error. Since the issue no longer occurs in the latest version, it needs to be reverted. --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 9 --------- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index ba93c25e9363c..60359d45ed981 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -420,6 +420,7 @@ const struct vpu_ops iris_vpu3_ops = { .power_off_controller = iris_vpu_power_off_controller, .power_on_controller = iris_vpu_power_on_controller, .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode = iris_vpu_set_hwmode, }; const struct vpu_ops iris_vpu3_purwa_ops = { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 215ed79ab2339..c96c02862aeec 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -291,14 +291,8 @@ int iris_vpu_power_on_hw(struct iris_core *core) if (ret && ret != -ENOENT) goto err_disable_hw_clock; - ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); - if (ret) - goto err_disable_hw_ahb_clock; - return 0; -err_disable_hw_ahb_clock: - iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: @@ -314,9 +308,6 @@ int iris_vpu_set_hwmode(struct iris_core *core) int iris_vpu_switch_to_hwmode(struct iris_core *core) { - if (!core->iris_platform_data->vpu_ops->set_hwmode) - return 0; - return core->iris_platform_data->vpu_ops->set_hwmode(core); } From 0dcaaca32477c7fcb28c105ef0f1bb52c1200da6 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 31 Jul 2026 20:04:04 +0800 Subject: [PATCH 1301/1330] config: disable memory dump driver configs Disable the memory dump driver related configs to disable the memory dump driver. Signed-off-by: Jie Gan --- debian.qcom/config/annotations | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 8a1c93b693f03..a4e6117e5d1c7 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -1824,8 +1824,8 @@ CONFIG_QCOM_HIDMA policy<{'arm64': 'y'}> CONFIG_QCOM_HIDMA_MGMT policy<{'arm64': 'y'}> CONFIG_QCOM_INLINE_CRYPTO_ENGINE policy<{'arm64': 'y'}> CONFIG_QCOM_KVM_ENABLED policy<{'arm64': '-'}> -CONFIG_QCOM_MEMORY_DUMP_DEV policy<{'arm64': 'y'}> -CONFIG_QCOM_MEMORY_DUMP_V2 policy<{'arm64': 'y'}> +CONFIG_QCOM_MEMORY_DUMP_DEV policy<{'arm64': '-'}> +CONFIG_QCOM_MEMORY_DUMP_V2 policy<{'arm64': '-'}> CONFIG_QCOM_MEM_BUF policy<{'arm64': '-'}> CONFIG_QCOM_MEM_BUF_DEV policy<{'arm64': '-'}> CONFIG_QCOM_MINIDUMP policy<{'arm64': '-'}> From 7723814a6196658771b5681eb0aeefa7f94d7411 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 31 Jul 2026 20:05:07 +0800 Subject: [PATCH 1302/1330] config: reset PANIC_TIMEOUT to 0 Reset the PANIC_TIMEOUT to 0 to disable the reboot operation in panic function. Signed-off-by: Jie Gan --- debian.qcom/config/annotations | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index a4e6117e5d1c7..c471b43fddd94 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -1406,7 +1406,7 @@ CONFIG_OWL_PM_DOMAINS policy<{'arm64': '-'}> CONFIG_OWL_PM_DOMAINS_HELPER policy<{'arm64': '-'}> CONFIG_OWL_TIMER policy<{'arm64': '-'}> CONFIG_PAGE_BLOCK_MAX_ORDER policy<{'arm64': '10'}> -CONFIG_PANIC_TIMEOUT policy<{'arm64': '-1'}> +CONFIG_PANIC_TIMEOUT policy<{'arm64': '0'}> CONFIG_PATA_IMX policy<{'arm64': '-'}> CONFIG_PCIE_APPLE policy<{'arm64': '-'}> CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR policy<{'arm64': '-'}> From 7b4ffd817fef79a8c117c8cfa8b529ca68250cc1 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Thu, 25 Jun 2026 17:42:45 +0800 Subject: [PATCH 1303/1330] FROMGIT: i2c: qcom-cci: drop custom suspend/resume and rely on runtime PM helpers cci_resume() unconditionally calls cci_resume_runtime() regardless of the runtime PM state. If the device is already runtime-suspended before system suspend, the clock is re-enabled while runtime_status remains RPM_SUSPENDED. As a result, pm_request_autosuspend() does not arm the timer, leaving the clock permanently enabled. Fixes: e517526195de ("i2c: Add Qualcomm CCI I2C driver") Cc: stable@vger.kernel.org Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Loic Poulain Signed-off-by: Wenmeng Liu Link: https://lore.kernel.org/all/20260625-cci-v1-1-a100cda673ce@oss.qualcomm.com/ --- drivers/i2c/busses/i2c-qcom-cci.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index 884055df1560f..41b11207004d0 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -496,24 +496,8 @@ static int __maybe_unused cci_resume_runtime(struct device *dev) return 0; } -static int __maybe_unused cci_suspend(struct device *dev) -{ - if (!pm_runtime_suspended(dev)) - return cci_suspend_runtime(dev); - - return 0; -} - -static int __maybe_unused cci_resume(struct device *dev) -{ - cci_resume_runtime(dev); - pm_request_autosuspend(dev); - - return 0; -} - static const struct dev_pm_ops qcom_cci_pm = { - SET_SYSTEM_SLEEP_PM_OPS(cci_suspend, cci_resume) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) SET_RUNTIME_PM_OPS(cci_suspend_runtime, cci_resume_runtime, NULL) }; From 45dab13d95ec2c09c03002d88593eb1516843577 Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Fri, 17 Jul 2026 10:30:12 +0800 Subject: [PATCH 1304/1330] FROMLIST: arm64: dts: qcom: hamoa-iot-evk: switch typec0 to PS8830 retimer The Hamoa IoT EVK hardware design uses a Parade PS8830 retimer on I2C3 for USB Type-C port 0. Describe the retimer and route typec0 through it to enable USB 3.0 SuperSpeed and DisplayPort Alt Mode. Supply the PS8830 from the existing vreg_rtmr0_* rails and remove their stale "Left unused" annotation. The FSUSB42 SBU mux chip is present on the PCB but with all signal lines unconnected (NC), so remove the fsusb42 node and its pinctrl group. Tested on the Hamoa IoT EVK: USB 3.0 SuperSpeed at 5 Gbps on typec0 DisplayPort Alt Mode on typec0 Reviewed-by: Dmitry Baryshkov Signed-off-by: Guodong Xu Signed-off-by: Xin Liu Link: https://lore.kernel.org/all/20260803132753.994619-1-xin.liu@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 108 ++++++++++++--------- 1 file changed, 60 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 9abf24c8017d3..383731519f20f 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -126,15 +126,15 @@ reg = <1>; pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; + remote-endpoint = <&retimer_ss0_ss_out>; }; }; port@2 { reg = <2>; - pmic_glink_ss0_sbu: endpoint { - remote-endpoint = <&usb_1_ss0_sbu_mux>; + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; }; }; }; @@ -303,7 +303,6 @@ pinctrl-names = "default"; }; - /* Left unused as the retimer is not used on this board. */ vreg_rtmr0_1p15: regulator-rtmr0-1p15 { compatible = "regulator-fixed"; @@ -675,25 +674,6 @@ }; }; - usb-1-ss0-sbu-mux { - compatible = "onnn,fsusb42", "gpio-sbu-mux"; - - enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; - select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&usb_1_ss0_sbu_default>; - pinctrl-names = "default"; - - mode-switch; - orientation-switch; - - port { - usb_1_ss0_sbu_mux: endpoint { - remote-endpoint = <&pmic_glink_ss0_sbu>; - }; - }; - }; - wcn7850-pmu { compatible = "qcom,wcn7850-pmu"; @@ -809,6 +789,62 @@ }; }; +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + &i2c5 { clock-frequency = <400000>; @@ -1494,30 +1530,6 @@ bias-disable; }; - usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { - mode-pins { - pins = "gpio166"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-high; - }; - - oe-n-pins { - pins = "gpio168"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - - sel-pins { - pins = "gpio167"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - }; - wcd_default: wcd-reset-n-active-state { pins = "gpio191"; function = "gpio"; @@ -1614,7 +1626,7 @@ }; &usb_1_ss0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss0_ss_in>; + remote-endpoint = <&retimer_ss0_ss_in>; }; &usb_1_ss1_dwc3_hs { From b3520e9cd73024ffa40f4cf54674559de1b5800c Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 11 May 2026 12:55:37 +0530 Subject: [PATCH 1305/1330] FROMLIST: gpio: Add fwnode_gpiod_get() helper Add fwnode_gpiod_get() as a convenience wrapper around fwnode_gpiod_get_index() for the common case where only the first GPIO is required. This mirrors existing gpiod_get() and devm_gpiod_get() helpers and avoids open-coding index 0 at call sites. Suggested-by: Manivannan Sadhasivam Acked-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Acked-by: Bartosz Golaszewski Signed-off-by: Krishna Chaitanya Chundru Link: https://patch.msgid.link/20260511-wakeirq_support-v10-1-c10af9c9eb8c@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- include/linux/gpio/consumer.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h index 0d84085829186..fee926c0262ce 100644 --- a/include/linux/gpio/consumer.h +++ b/include/linux/gpio/consumer.h @@ -596,6 +596,15 @@ static inline int gpiod_disable_hw_timestamp_ns(struct gpio_desc *desc, } #endif /* CONFIG_GPIOLIB && CONFIG_HTE */ +static inline +struct gpio_desc *fwnode_gpiod_get(struct fwnode_handle *fwnode, + const char *con_id, + enum gpiod_flags flags, + const char *label) +{ + return fwnode_gpiod_get_index(fwnode, con_id, 0, flags, label); +} + static inline struct gpio_desc *devm_fwnode_gpiod_get(struct device *dev, struct fwnode_handle *fwnode, From bee264c11a700a850b5bb586b3d2c0d77a21f0fe Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 24 Jun 2026 16:55:49 +0530 Subject: [PATCH 1306/1330] FROMLIST: PCI: Add support for PCIe WAKE# interrupt According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2), two link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a hardware-only mechanism and is invisible to software (PCIe r7.0, Section 4.2.7.8.1). This change adds support for the WAKE# mechanism in the PCI core. According to the PCIe specification, multiple WAKE# signals can exist in a system or each component in the hierarchy could share a single WAKE# signal. In configurations involving a PCIe switch, each downstream port (DSP) of the switch may be connected to a separate WAKE# line, allowing each endpoint to signal WAKE# independently. From figure 5.4 in sec 5.3.3.2, WAKE# can also be terminated at the switch itself. Such topologies are typically not described in Device Tree, therefore it is out of scope for this series. To support this, the WAKE# should be described in the device tree node of the endpoint/bridge. If all endpoints share a single WAKE# line, then each endpoint node shall describe the same WAKE# signal or a single WAKE# in the Root Port node. In pci_device_add(), PCI framework will search for the WAKE# in device node. Once found, register for the wake IRQ through dev_pm_set_dedicated_wake_irq() associates a wakeup IRQ with a device and requests it, but the PM core keeps the IRQ disabled by default. The IRQ is enabled by the PM core, only when the device is permitted to wake the system, i.e. during system suspend and after runtime suspend, and only when device wakeup is enabled. If the same WAKE# GPIO is described in multiple device tree nodes, only the first device that successfully registers the wake IRQ will succeed, while subsequent registrations may fail. This limitation does not affect functional correctness, since WAKE# is only used to bring the link to D0, and endpoint-specific wakeup handling is resolved later through PME detection (PME_EN is set in suspend path by PCI core by default). When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() to bring the device back to an active power state, such as transitioning from D3cold to D0. Once the device is active and the link is usable, the endpoint may generate a PME, which is then handled by the PCI core through PME polling or the PCIe PME service driver to complete the wakeup of the endpoint. WAKE# is added in dts schema and merged based on below links. Link: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/ Link: https://github.com/devicetree-org/dt-schema/pull/170 Reviewed-by: Linus Walleij Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260624-wakeirq_support-v11-1-120fbfaebe59@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Bartosz Golaszewski Signed-off-by: Ziyue Zhang --- drivers/pci/of.c | 76 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.c | 11 ++++++ drivers/pci/pci.h | 2 ++ drivers/pci/probe.c | 2 ++ drivers/pci/remove.c | 1 + include/linux/of_pci.h | 6 ++++ include/linux/pci.h | 2 ++ 7 files changed, 100 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 9f8eb5df279ed..e560ac9e9a4d7 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "PCI: OF: " fmt #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include "pci.h" #ifdef CONFIG_PCI @@ -586,6 +588,80 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) return irq_create_of_mapping(&oirq); } EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci); + +static void pci_configure_wake_irq(struct pci_dev *pdev, struct gpio_desc *wake) +{ + int ret, wake_irq; + + wake_irq = gpiod_to_irq(wake); + if (wake_irq < 0) { + pci_err(pdev, "Failed to get wake irq: %d\n", wake_irq); + return; + } + + /* + * dev_pm_set_dedicated_wake_irq() associates a wakeup IRQ with the + * device and requests it, but the PM core keeps it disabled by default. + * The IRQ is enabled only when the device is allowed to wake the system + * (during system suspend and after runtime suspend), and only if device + * wakeup is enabled. + * + * When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() + * to bring the device back to an active power state (e.g. from D3cold to D0). + * Once the device is active and the link is usable, the endpoint may signal + * a PME, which is then handled by the PCI core (either via PME polling or the + * PCIe PME service driver) to wakeup particular endpoint. + */ + ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, wake_irq); + if (ret < 0) { + pci_err(pdev, "Failed to set WAKE# IRQ: %d\n", ret); + return; + } + + ret = irq_set_irq_type(wake_irq, IRQ_TYPE_LEVEL_LOW); + if (ret < 0) { + dev_pm_clear_wake_irq(&pdev->dev); + pci_err(pdev, "Failed to set irq_type: %d\n", ret); + return; + } + + device_init_wakeup(&pdev->dev, true); +} + +void pci_configure_of_wake_gpio(struct pci_dev *dev) +{ + struct device_node *dn = pci_device_to_OF_node(dev); + struct gpio_desc *gpio; + + if (!dn) + return; + /* + * fwnode_gpiod_get() may fail with -EBUSY (e.g. shared WAKE#), but the + * actual WAKE# trigger from the device would still work and the host + * controller driver will enable power to the topology. + * + * -EPROBE_DEFER cannot be propagated here since pci_device_add() has no + * retry mechanism. + */ + gpio = fwnode_gpiod_get(of_fwnode_handle(dn), "wake", GPIOD_IN, NULL); + if (!IS_ERR(gpio)) { + dev->wake = gpio; + pci_configure_wake_irq(dev, gpio); + } +} + +void pci_remove_of_wake_gpio(struct pci_dev *dev) +{ + struct device_node *dn = pci_device_to_OF_node(dev); + + if (!dn) + return; + + device_init_wakeup(&dev->dev, false); + dev_pm_clear_wake_irq(&dev->dev); + gpiod_put(dev->wake); + dev->wake = NULL; +} #endif /* CONFIG_OF_IRQ */ static int pci_parse_request_of_pci_ranges(struct device *dev, diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index faf39d74bc8a9..58e330c78ebad 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -1124,6 +1125,16 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev) return acpi_pci_bridge_d3(dev); } +void platform_pci_configure_wake(struct pci_dev *dev) +{ + pci_configure_of_wake_gpio(dev); +} + +void platform_pci_remove_wake(struct pci_dev *dev) +{ + pci_remove_of_wake_gpio(dev); +} + /** * pci_update_current_state - Read power state of given device and cache it * @dev: PCI device to handle. diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 13d998fbacce6..65ca9551e558d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -282,6 +282,8 @@ void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); +void platform_pci_configure_wake(struct pci_dev *dev); +void platform_pci_remove_wake(struct pci_dev *dev); static inline bool pci_bus_rrs_vendor_id(u32 l) { diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index b4707640e1021..df963152319d3 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2770,6 +2770,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) /* Establish pdev->tsm for newly added (e.g. new SR-IOV VFs) */ pci_tsm_init(dev); + platform_pci_configure_wake(dev); + pci_npem_create(dev); pci_doe_sysfs_init(dev); diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index e9d519993853f..d781b41e57c44 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -35,6 +35,7 @@ static void pci_destroy_dev(struct pci_dev *dev) if (pci_dev_test_and_set_removed(dev)) return; + platform_pci_remove_wake(dev); pci_doe_sysfs_teardown(dev); pci_npem_remove(dev); diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index 29658c0ee71ff..649fe8eafcfa4 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h @@ -30,12 +30,18 @@ static inline void of_pci_check_probe_only(void) { } #if IS_ENABLED(CONFIG_OF_IRQ) int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin); +void pci_configure_of_wake_gpio(struct pci_dev *dev); +void pci_remove_of_wake_gpio(struct pci_dev *dev); #else static inline int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) { return 0; } + +static inline void pci_configure_of_wake_gpio(struct pci_dev *dev) { } + +static inline void pci_remove_of_wake_gpio(struct pci_dev *dev) { } #endif #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index 4330a30ecad89..82dff62062562 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -581,6 +581,8 @@ struct pci_dev { /* These methods index pci_reset_fn_methods[] */ u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ + struct gpio_desc *wake; /* Holds WAKE# gpio */ + #ifdef CONFIG_PCIE_TPH u16 tph_cap; /* TPH capability offset */ u8 tph_mode; /* TPH mode */ From ae2d6b9e6cef397d8e5621f7b36f0558827696ee Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 25 Mar 2026 07:32:27 +0200 Subject: [PATCH 1307/1330] BACKPORT: drm/msm/dpu: correct DP MST interface configuration Due to historical reasons we ended up with dummy values being specified for MST-related interfaces some of them had INTF_NONE, others had non-existing DP controller indices. Those workarounds are no longer necessary. Fix types and indices for all DP-MST related INTF instances. The only exception is INTF_3 on SC8180X, which has unique design. It can be used either with INTF_0 / DP0 or with INTF_4 / DP1. This interface is left with the dummy value until somebody implements necessary bits for that platform. Co-developed-by: Abhinav Kumar Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/713988/ Link: https://lore.kernel.org/r/20260325-fix-dp-mst-interfaces-v1-1-186d1de3fa1b@oss.qualcomm.com Signed-off-by: Vishnu Saini --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h | 6 +++--- .../drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 +- .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 13 ++++++------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 9 ++++----- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 +- .../drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 2 +- .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 7 +++---- 16 files changed, 28 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 56d3c38c87781..bd8139b5d7112 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -378,7 +378,7 @@ static const struct dpu_intf_cfg sm8650_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h index db8cc2d0112c8..73c19a942d295 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h @@ -420,7 +420,7 @@ static const struct dpu_intf_cfg sm8750_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x4bc, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h index 13bb43ba67d3f..a3b590cca21dc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h @@ -426,7 +426,7 @@ static const struct dpu_intf_cfg glymur_intf[] = { }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x400, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -458,7 +458,7 @@ static const struct dpu_intf_cfg glymur_intf[] = { }, { .name = "intf_7", .id = INTF_7, .base = 0x3b000, .len = 0x400, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -466,7 +466,7 @@ static const struct dpu_intf_cfg glymur_intf[] = { }, { .name = "intf_8", .id = INTF_8, .base = 0x3c000, .len = 0x400, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h index e3c47b6702f18..12a9b8bf04785 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h @@ -418,7 +418,7 @@ static const struct dpu_intf_cfg kaanapali_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x190000, .len = 0x4bc, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 5cc9f55d542b7..1a201cb7746d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -258,7 +258,7 @@ static const struct dpu_intf_cfg sdm845_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x6b800, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index ae1b2ed96e9f1..adad0114fbb77 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -317,7 +317,7 @@ static const struct dpu_intf_cfg sm8150_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x6b800, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index a56c288ac10cd..d81d3c616b3b0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -230,7 +230,7 @@ static const struct dpu_intf_cfg sm7150_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x6b800, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index 26883f6b66b3e..e65f198db9a78 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -186,7 +186,7 @@ static const struct dpu_intf_cfg sm6150_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x6b800, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 7b8b7a1c2d767..1562b8363f3fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -301,7 +301,7 @@ static const struct dpu_intf_cfg sm8250_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x6b800, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 85aae40c210f3..1d8a32d109905 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -327,7 +327,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 9f2bceca1789e..c407f01abca79 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -288,7 +288,6 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = { }, }; -/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ static const struct dpu_intf_cfg sc8280xp_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -319,8 +318,8 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, - .type = INTF_NONE, - .controller_id = MSM_DP_CONTROLLER_0, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), @@ -351,16 +350,16 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { }, { .name = "intf_7", .id = INTF_7, .base = 0x3b000, .len = 0x280, - .type = INTF_NONE, - .controller_id = MSM_DP_CONTROLLER_2, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), }, { .name = "intf_8", .id = INTF_8, .base = 0x3c000, .len = 0x280, - .type = INTF_NONE, - .controller_id = MSM_DP_CONTROLLER_1, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_8 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 04b22167f93d6..6a09da5ed6704 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -340,7 +340,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 42cf3bd5a12ad..0b78180eca813 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -316,7 +316,6 @@ static const struct dpu_wb_cfg sa8775p_wb[] = { }, }; -/* TODO: INTF 3, 6, 7 and 8 are used for MST, marked as INTF_NONE for now */ static const struct dpu_intf_cfg sa8775p_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -347,7 +346,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = { }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -363,7 +362,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = { }, { .name = "intf_6", .id = INTF_6, .base = 0x3A000, .len = 0x280, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), @@ -371,7 +370,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = { }, { .name = "intf_7", .id = INTF_7, .base = 0x3b000, .len = 0x280, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -379,7 +378,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = { }, { .name = "intf_8", .id = INTF_8, .base = 0x3c000, .len = 0x280, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 4c7eb55d474c5..1f06710dafad0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -335,7 +335,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h index dec83ea8167d1..078f5285c46b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -335,7 +335,7 @@ static const struct dpu_intf_cfg sar2130p_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 52ff4baa668a4..4d2bf5c7ac982 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -304,7 +304,6 @@ static const struct dpu_wb_cfg x1e80100_wb[] = { }, }; -/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ static const struct dpu_intf_cfg x1e80100_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -335,7 +334,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -367,7 +366,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { }, { .name = "intf_7", .id = INTF_7, .base = 0x3b000, .len = 0x280, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -375,7 +374,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { }, { .name = "intf_8", .id = INTF_8, .base = 0x3c000, .len = 0x280, - .type = INTF_NONE, + .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), From 70cb17019f117b46f9e455f54547d77691b58523 Mon Sep 17 00:00:00 2001 From: Praveen Talari Date: Wed, 1 Jul 2026 11:27:55 +0530 Subject: [PATCH 1308/1330] FROMLIST: serial: qcom-geni: add force suspend/resume to system sleep callbacks During system sleep the hardware resources (clocks, interconnect) are not gated because the runtime-suspend callback is never invoked from the system sleep path. This prevents the platform from reaching its lowest idle state. The system sleep callbacks qcom_geni_serial_suspend() and qcom_geni_serial_resume() rely solely on uart_suspend_port() / uart_resume_port() to manage power. uart_suspend_port() drives the UART PM state machine to UART_PM_STATE_OFF, which in turn calls pm_runtime_put_sync() and eventually the runtime-suspend callback. However, if the runtime-PM usage count is still elevated at the time of system sleep (e.g. the port is held active by an open file descriptor), the runtime-suspend callback is never invoked and the hardware resources (clocks, interconnect) remain enabled across suspend, preventing the platform from reaching its lowest idle state. Fix this by calling pm_runtime_force_suspend() at the end of qcom_geni_serial_suspend() so that the runtime-suspend callback is always executed regardless of the usage count, and by calling pm_runtime_force_resume() at the start of qcom_geni_serial_resume() to restore those resources before uart_resume_port() re-opens the port. Link: https://lore.kernel.org/all/20260701-add_force_suspend_resume_to_system_sleep_callbacks-v1-1-38c9a721a462@oss.qualcomm.com/ Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 9d372db5216fc..e1f484a323598 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1963,6 +1963,7 @@ static int qcom_geni_serial_suspend(struct device *dev) struct qcom_geni_serial_port *port = dev_get_drvdata(dev); struct uart_port *uport = &port->uport; struct qcom_geni_private_data *private_data = uport->private_data; + int ret; /* * This is done so we can hit the lowest possible state in suspend @@ -1972,7 +1973,19 @@ static int qcom_geni_serial_suspend(struct device *dev) geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); geni_icc_set_bw(&port->se); } - return uart_suspend_port(private_data->drv, uport); + + ret = uart_suspend_port(private_data->drv, uport); + if (ret) + return ret; + + /* + * When no_console_suspend is set the console must remain active + * across system sleep, so skip the force suspend path. + */ + if (uart_console(uport) && !uport->suspended) + return 0; + + return pm_runtime_force_suspend(dev); } static int qcom_geni_serial_resume(struct device *dev) @@ -1982,6 +1995,10 @@ static int qcom_geni_serial_resume(struct device *dev) struct uart_port *uport = &port->uport; struct qcom_geni_private_data *private_data = uport->private_data; + ret = pm_runtime_force_resume(dev); + if (ret) + return ret; + ret = uart_resume_port(private_data->drv, uport); if (uart_console(uport)) { geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); From b179b623c9b66f1444ed7cd6505ebd6eefc34fc9 Mon Sep 17 00:00:00 2001 From: Guanquan Tian Date: Thu, 6 Aug 2026 01:39:39 +0800 Subject: [PATCH 1309/1330] ci(premerge-pr): build check with S3 upload, dbgsym off, flavours + s3_prefix Call build-kernel.yml with skip_s3: false so pre-merge build artifacts are uploaded, and pass s3_prefix: premerge so they land under pkg/premerge/, separate from the pkg/temp/ prefix nightly and manual workflow_dispatch runs use. Pin dbgsym: false since dbgsym packages aren't needed for a build-only pre-merge check. Pass flavours: qcom now that build-kernel.yml takes space-separated flavour names and always builds binary-indep alongside them. Signed-off-by: Guanquan Tian --- .github/workflows/premerge-pr.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/premerge-pr.yml b/.github/workflows/premerge-pr.yml index 60b5dfdf36cc0..aad3c1eba7ed4 100644 --- a/.github/workflows/premerge-pr.yml +++ b/.github/workflows/premerge-pr.yml @@ -35,4 +35,7 @@ jobs: with: suite: resolute-qcom-devel ref: refs/pull/${{ github.event.pull_request.number }}/merge - skip_s3: true + skip_s3: false + dbgsym: false + flavours: qcom + s3_prefix: premerge From 3836d861984d81cf745cd794654ac38ef7aef264 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 28 Jul 2026 15:20:46 +0200 Subject: [PATCH 1310/1330] BACKPORT: drm/msm/dp: Drop dev_pm_opp_set_rate(0) dev_pm_opp_set_rate(0) removes the vote specified in required-opps but does not actually park the clock, making it run without the necessary power backing. Drop the explicit calls to it. Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/742781/ Link: https://lore.kernel.org/r/20260728-topic-dpu_power-v1-2-e7783b859a70@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 6642c986c81fe..fdd92326d1f97 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2174,13 +2174,12 @@ static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_mainlink_disable(ctrl); ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; phy_configure(phy, &ctrl->phy_opts); + /* * Disable and re-enable the mainlink clock since the * link clock might have been adjusted as part of the * link maintenance. */ - dev_pm_opp_set_rate(ctrl->dev, 0); - msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); phy_power_off(phy); @@ -2206,7 +2205,6 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); - dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); phy_power_off(phy); @@ -2965,7 +2963,6 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) ctrl->mst_active = false; - dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); phy_power_off(phy); From 70d25182377405e5b1de00ffb0816b52f77f970c Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 10 Aug 2026 16:12:53 +0800 Subject: [PATCH 1311/1330] FROMLIST: drm/bridge: aux-hpd-bridge: replay last HPD status on hpd_enable If a downstream consumer (e.g. drm_bridge_connector attached by the msm/dp driver) registers its HPD callback after an upstream driver has already reported a HPD event through drm_aux_hpd_bridge_notify(), the notification is dropped because bridge->hpd_cb is still NULL. This can affect any user of drm_aux_hpd_bridge_notify() whose downstream consumer arms HPD only after upstream events have started. The race has been observed on Qualcomm X1E-based laptops during boot, when pmic_glink_altmode reports the initial USB-C DP connection state before the DP driver has finished probing and enabled HPD handling on the bridge. The consumer then never observes the initial connected state and the external display remains dark. Cache the last HPD status reported through drm_aux_hpd_bridge_notify() and replay it when HPD is enabled by the downstream consumer. The replay is deferred to a work item so that the replayed HPD notification is delivered outside drm_bridge_hpd_enable()'s call context. This follows the same pattern as display-connector, which also defers an initial HPD notification from .hpd_enable(), but reuses the cached status since aux-hpd-bridge cannot re-detect sink presence on its own. Fixes: e560518a6c2e ("drm/bridge: implement generic DP HPD bridge") Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260803-drm-usbdp-preboot-v1-1-2539b362be00@oss.qualcomm.com/ --- drivers/gpu/drm/bridge/aux-hpd-bridge.c | 53 ++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/aux-hpd-bridge.c b/drivers/gpu/drm/bridge/aux-hpd-bridge.c index f02a38a2638ad..11a3fb87d9c0f 100644 --- a/drivers/gpu/drm/bridge/aux-hpd-bridge.c +++ b/drivers/gpu/drm/bridge/aux-hpd-bridge.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -17,6 +18,17 @@ static DEFINE_IDA(drm_aux_hpd_bridge_ida); struct drm_aux_hpd_bridge_data { struct drm_bridge bridge; struct device *dev; + + /* + * Last HPD status pushed through drm_aux_hpd_bridge_notify(). + * Replayed from .hpd_enable so that consumers registering their + * callback after the initial notification are caught up. + * + * Accessed lockless from the notify path (writer) and hpd_work + * (reader) - use WRITE_ONCE()/READ_ONCE(). + */ + enum drm_connector_status last_status; + struct work_struct hpd_work; }; static void drm_aux_hpd_bridge_release(struct device *dev) @@ -153,6 +165,8 @@ void drm_aux_hpd_bridge_notify(struct device *dev, enum drm_connector_status sta if (!data) return; + WRITE_ONCE(data->last_status, status); + drm_bridge_hpd_notify(&data->bridge, status); } EXPORT_SYMBOL_GPL(drm_aux_hpd_bridge_notify); @@ -164,8 +178,42 @@ static int drm_aux_hpd_bridge_attach(struct drm_bridge *bridge, return flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR ? 0 : -EINVAL; } +static void drm_aux_hpd_bridge_hpd_work(struct work_struct *work) +{ + struct drm_aux_hpd_bridge_data *data = + container_of(work, struct drm_aux_hpd_bridge_data, hpd_work); + enum drm_connector_status status = READ_ONCE(data->last_status); + + if (status == connector_status_unknown) + return; + + drm_bridge_hpd_notify(&data->bridge, status); +} + +/* + * Deferred to a work item so that the replayed HPD notification is + * delivered outside drm_bridge_hpd_enable()'s call context. + */ +static void drm_aux_hpd_bridge_hpd_enable(struct drm_bridge *bridge) +{ + struct drm_aux_hpd_bridge_data *data = + container_of(bridge, struct drm_aux_hpd_bridge_data, bridge); + + schedule_work(&data->hpd_work); +} + +static void drm_aux_hpd_bridge_hpd_disable(struct drm_bridge *bridge) +{ + struct drm_aux_hpd_bridge_data *data = + container_of(bridge, struct drm_aux_hpd_bridge_data, bridge); + + cancel_work_sync(&data->hpd_work); +} + static const struct drm_bridge_funcs drm_aux_hpd_bridge_funcs = { - .attach = drm_aux_hpd_bridge_attach, + .attach = drm_aux_hpd_bridge_attach, + .hpd_enable = drm_aux_hpd_bridge_hpd_enable, + .hpd_disable = drm_aux_hpd_bridge_hpd_disable, }; static int drm_aux_hpd_bridge_probe(struct auxiliary_device *auxdev, @@ -188,6 +236,9 @@ static int drm_aux_hpd_bridge_probe(struct auxiliary_device *auxdev, data->bridge.interlace_allowed = true; data->bridge.ycbcr_420_allowed = true; + data->last_status = connector_status_unknown; + INIT_WORK(&data->hpd_work, drm_aux_hpd_bridge_hpd_work); + auxiliary_set_drvdata(auxdev, data); return devm_drm_bridge_add(data->dev, &data->bridge); From e5cb2811af64769b8c433a2f09f91b80144b97d6 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 10 Aug 2026 17:43:15 +0800 Subject: [PATCH 1312/1330] config: enable coresight_ctcu Enable CONFIG_CORESIGHT_CTCU (built as a module) for the arm64-qcom flavour to support the CoreSight TMC Control Unit. The CTCU driver programs the per-ATID byte counters and manages the trace-ID (ATID) filtering for the TMC-ETR sink. This allows trace data from selected sources to be routed and captured into system DDR, which is required to enable DDR-based CoreSight trace on Qualcomm platforms. Signed-off-by: Jie Gan --- debian.qcom/config/annotations | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index c471b43fddd94..40dcc02073995 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -618,7 +618,7 @@ CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'arm64': '1', 'arm64-qco CONFIG_CORESIGHT policy<{'arm64': 'm'}> CONFIG_CORESIGHT_CATU policy<{'arm64-qcom': 'n'}> CONFIG_CORESIGHT_CPU_DEBUG policy<{'arm64': 'n'}> -CONFIG_CORESIGHT_CTCU policy<{'arm64-qcom': 'n'}> +CONFIG_CORESIGHT_CTCU policy<{'arm64-qcom': 'm'}> CONFIG_CORESIGHT_CTI policy<{'arm64': 'n', 'arm64-qcom': 'm'}> CONFIG_CORESIGHT_CTI_INTEGRATION_REGS policy<{'arm64-qcom': 'n'}> CONFIG_CORESIGHT_DUMMY policy<{'arm64': 'm'}> From 89fb4ac87732a29141de89263955a435242d748a Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 10 Aug 2026 17:48:48 +0800 Subject: [PATCH 1313/1330] config: enable coresight_stm Enable CONFIG_CORESIGHT_STM (built as a module) for the arm64 flavour to support the CoreSight System Trace Macrocell. The STM driver registers an STMipi/STPv2 trace source and exposes a stimulus-port interface (via the stm class) that lets software, both kernel subsystems and user space, emit timestamped software trace messages into the CoreSight trace bus. These messages can then be merged with hardware trace and captured at a CoreSight sink for system-level debugging. Signed-off-by: Jie Gan --- debian.qcom/config/annotations | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index 40dcc02073995..da28b613b802b 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -627,7 +627,7 @@ CONFIG_CORESIGHT_LINK_AND_SINK_TMC policy<{'arm64': 'n', 'arm64-qco CONFIG_CORESIGHT_SINK_ETBV10 policy<{'arm64': 'n'}> CONFIG_CORESIGHT_SINK_TPIU policy<{'arm64': 'n'}> CONFIG_CORESIGHT_SOURCE_ETM4X policy<{'arm64': 'm'}> -CONFIG_CORESIGHT_STM policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_STM policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TNOC policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TPDA policy<{'arm64': 'm'}> CONFIG_CORESIGHT_TPDM policy<{'arm64': 'm'}> From 7c44f3a6e45e51e7a107d21a5b6bc7f1c76c03ce Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Apr 2026 08:11:12 +0000 Subject: [PATCH 1314/1330] UPSTREAM: ASoC: qcom: common: validate cpu dai id during parsing lpass ports numbers have been added but the afe/apm driver never got updated with new max port value that it uses to store dai specific data. There are more than one places these values are cached and always become out of sync. This will result in array out of bounds and weird driver behaviour. To catch such issues, first add a single place where we can define max port and second add a check in common parsing code which can error out before corrupting the memory with out of bounds array access. This should help both avoid and catch these type of mistakes in future. Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260402081118.348071-8-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown --- sound/soc/qcom/common.c | 6 ++++++ sound/soc/qcom/common.h | 3 +++ sound/soc/qcom/lpass.h | 3 ++- sound/soc/qcom/qdsp6/q6afe.h | 3 ++- sound/soc/qcom/qdsp6/q6apm.h | 3 ++- 5 files changed, 15 insertions(+), 3 deletions(-) diff --git a/sound/soc/qcom/common.c b/sound/soc/qcom/common.c index 7ee60a58a3368..cf1f3a767ceef 100644 --- a/sound/soc/qcom/common.c +++ b/sound/soc/qcom/common.c @@ -120,6 +120,12 @@ int qcom_snd_parse_of(struct snd_soc_card *card) link->id = args.args[0]; + if (link->id >= LPASS_MAX_PORT) { + dev_err(dev, "%s: Invalid cpu dai id %d\n", link->name, link->id); + ret = -EINVAL; + goto err; + } + if (platform) { link->platforms->of_node = of_parse_phandle(platform, "sound-dai", diff --git a/sound/soc/qcom/common.h b/sound/soc/qcom/common.h index 1b8d3f90bffaf..ee6662885593c 100644 --- a/sound/soc/qcom/common.h +++ b/sound/soc/qcom/common.h @@ -4,8 +4,11 @@ #ifndef __QCOM_SND_COMMON_H__ #define __QCOM_SND_COMMON_H__ +#include #include +#define LPASS_MAX_PORT (SENARY_MI2S_TX + 1) + int qcom_snd_parse_of(struct snd_soc_card *card); int qcom_snd_wcd_jack_setup(struct snd_soc_pcm_runtime *rtd, struct snd_soc_jack *jack, bool *jack_setup); diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index de3ec6f594c11..68b71039b9814 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -14,10 +14,11 @@ #include #include #include +#include "common.h" #include "lpass-hdmi.h" #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 -#define LPASS_MAX_PORTS (DISPLAY_PORT_RX_7 + 1) +#define LPASS_MAX_PORTS (LPASS_MAX_PORT) #define LPASS_MAX_MI2S_PORTS (8) #define LPASS_MAX_DMA_CHANNELS (8) #define LPASS_MAX_HDMI_DMA_CHANNELS (4) diff --git a/sound/soc/qcom/qdsp6/q6afe.h b/sound/soc/qcom/qdsp6/q6afe.h index a29abe4ce4368..0b8c3ec1315ca 100644 --- a/sound/soc/qcom/qdsp6/q6afe.h +++ b/sound/soc/qcom/qdsp6/q6afe.h @@ -2,8 +2,9 @@ #ifndef __Q6AFE_H__ #define __Q6AFE_H__ +#include "../common.h" -#define AFE_PORT_MAX 137 +#define AFE_PORT_MAX (LPASS_MAX_PORT) #define MSM_AFE_PORT_TYPE_RX 0 #define MSM_AFE_PORT_TYPE_TX 1 diff --git a/sound/soc/qcom/qdsp6/q6apm.h b/sound/soc/qcom/qdsp6/q6apm.h index 7ce08b401e310..5cf538397841a 100644 --- a/sound/soc/qcom/qdsp6/q6apm.h +++ b/sound/soc/qcom/qdsp6/q6apm.h @@ -14,9 +14,10 @@ #include #include #include +#include "../common.h" #include "audioreach.h" -#define APM_PORT_MAX 127 +#define APM_PORT_MAX LPASS_MAX_PORT #define APM_PORT_MAX_AUDIO_CHAN_CNT 8 #define PCM_CHANNEL_NULL 0 #define PCM_CHANNEL_FL 1 /* Front left channel. */ From e1dd3735b8698c5fe8ff68aa019a8931fab90f38 Mon Sep 17 00:00:00 2001 From: Dipa Ramesh Mantre Date: Tue, 11 Aug 2026 14:36:31 +0530 Subject: [PATCH 1315/1330] Revert "QCLINUX: defconfig: Enable Qualcomm BCL driver" This reverts commit 60e114f19a066b6e927b7a2d9f6e403d4a605bb8. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre --- arch/arm64/configs/qcom.config | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 62142b5caeec2..3e7150aeaed7e 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -61,7 +61,6 @@ CONFIG_STM_SOURCE_FTRACE=m CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_SENSORS_AMC6821=y CONFIG_SENSORS_EMC2305=y -CONFIG_SENSORS_QCOM_BCL=y CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y From b4b75322d22ca19cb3e1c12cd156e96b5869f6ec Mon Sep 17 00:00:00 2001 From: Dipa Ramesh Mantre Date: Tue, 11 Aug 2026 14:38:25 +0530 Subject: [PATCH 1316/1330] Revert "FROMLIST: arm64: dts: qcom: pm8350c: Enable Qualcomm BCL device" This reverts commit 024375170e5524e29458fe90fd1a9bdfdf19561a. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index f0cf55a7fc9e5..1a24e6439e36d 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -41,15 +41,6 @@ #pwm-cells = <2>; status = "disabled"; }; - - sensor@4700 { - compatible = "qcom,pm8350c-bcl", "qcom,bcl-v2"; - reg = <0x4700>; - interrupts = <0x2 0x47 0x0 IRQ_TYPE_EDGE_RISING>, - <0x2 0x47 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "bcl-max-min", - "bcl-critical"; - }; }; }; From 2c5bdfb56030b8822c977ea84481342b384b04c8 Mon Sep 17 00:00:00 2001 From: Dipa Ramesh Mantre Date: Tue, 11 Aug 2026 14:39:19 +0530 Subject: [PATCH 1317/1330] Revert "FROMLIST: arm64: dts: qcom: pm7250b: Enable Qualcomm BCL device" This reverts commit 3b7fc440e64baf0ab59abfdb2a23efb2adbc3c3a. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre --- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index dffd84dd87a85..0761e6b5fd8d1 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -202,16 +202,6 @@ interrupt-controller; #interrupt-cells = <2>; }; - - sensor@1d00 { - compatible = "qcom,pm7250b-bcl", "qcom,bcl-v1"; - reg = <0x1d00>; - interrupts = , - ; - interrupt-names = "bcl-max-min", - "bcl-critical"; - overcurrent-thresholds-milliamp = <5500 6000>; - }; }; pmic@PM7250B_SID1 { From 2753ab5f7e6429dd77477f2302bd01fd71fff185 Mon Sep 17 00:00:00 2001 From: Dipa Ramesh Mantre Date: Tue, 11 Aug 2026 14:40:02 +0530 Subject: [PATCH 1318/1330] Revert "FROMLIST: hwmon: Add Qualcomm PMIC BCL hardware monitor driver" This reverts commit 7ee6efc26ac857c8acbba7096410d24600280e1a. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre --- MAINTAINERS | 9 - drivers/hwmon/Kconfig | 9 - drivers/hwmon/Makefile | 1 - drivers/hwmon/qcom-bcl-hwmon.c | 982 --------------------------------- drivers/hwmon/qcom-bcl-hwmon.h | 311 ----------- 5 files changed, 1312 deletions(-) delete mode 100644 drivers/hwmon/qcom-bcl-hwmon.c delete mode 100644 drivers/hwmon/qcom-bcl-hwmon.h diff --git a/MAINTAINERS b/MAINTAINERS index d75a832c09d3c..7eb689d4a2598 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21670,15 +21670,6 @@ S: Maintained F: Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml F: drivers/net/wwan/qcom_bam_dmux.c -QUALCOMM BCL HARDWARE MONITOR DRIVER -M: Manaf Meethalavalappu Pallikunhi -L: linux-hwmon@vger.kernel.org -L: linux-arm-msm@vger.kernel.org -S: Maintained -F: Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml -F: drivers/hwmon/qcom-bcl-hwmon.c -F: drivers/hwmon/qcom-bcl-hwmon.h - QUALCOMM BLUETOOTH DRIVER M: Bartosz Golaszewski L: linux-arm-msm@vger.kernel.org diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index ebb74b9f9e09e..4f203fc74512b 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1916,15 +1916,6 @@ config SENSORS_PWM_FAN This driver can also be built as a module. If so, the module will be called pwm-fan. -config SENSORS_QCOM_BCL - tristate "Qualcomm BCL hardware monitoring" - help - Say yes here to enable support for Qualcomm battery over current - and under voltage alarms monitor. - - This driver can also be built as a module. If so, the module - will be called qcom-bcl-hwmon. - config SENSORS_QNAP_MCU_HWMON tristate "QNAP MCU hardware monitoring" depends on MFD_QNAP_MCU diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index deb9e52c5a0b4..bfbcc5d8b72a0 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -198,7 +198,6 @@ obj-$(CONFIG_SENSORS_POWERZ) += powerz.o obj-$(CONFIG_SENSORS_POWR1220) += powr1220.o obj-$(CONFIG_SENSORS_PT5161L) += pt5161l.o obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o -obj-$(CONFIG_SENSORS_QCOM_BCL) += qcom-bcl-hwmon.o obj-$(CONFIG_SENSORS_QNAP_MCU_HWMON) += qnap-mcu-hwmon.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o obj-$(CONFIG_SENSORS_SBTSI) += sbtsi_temp.o diff --git a/drivers/hwmon/qcom-bcl-hwmon.c b/drivers/hwmon/qcom-bcl-hwmon.c deleted file mode 100644 index 9894b1d14d124..0000000000000 --- a/drivers/hwmon/qcom-bcl-hwmon.c +++ /dev/null @@ -1,982 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Qualcomm pmic BCL hardware driver for battery overcurrent and - * battery or system under voltage monitor - * - * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qcom-bcl-hwmon.h" - -ADD_BCL_HWMON_ALARM_MAPS(in, min, lcrit); -ADD_BCL_HWMON_ALARM_MAPS(curr, max, crit); - -/* Interrupt names for each alarm level */ -static const char * const bcl_int_names[ALARM_MAX] = { - [LVL0] = "bcl-max-min", - [LVL1] = "bcl-critical", -}; - -static const char * const bcl_channel_label[CHANNEL_MAX] = { - "BCL Voltage", - "BCL Current", -}; - -/* Common Reg Fields */ -static const struct reg_field common_reg_fields[COMMON_FIELD_MAX] = { - [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), - [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), - [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), - [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), - [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), -}; - -/* BCL Version/Modes specific fields */ -static const struct reg_field bcl_v1_reg_fields[] = { - [F_IN_MON_EN] = REG_FIELD(MODE_CTL1, 0, 2), - [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), - [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), - [F_IN_INPUT_EN] = REG_FIELD(VADC_CONV_REQ, 0, 0), - [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), - [F_CURR_MON_EN] = REG_FIELD(IADC_CONV_REQ, 0, 0), - [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), - [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 7), - [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), -}; - -static const struct reg_field bcl_v2_reg_fields[] = { - [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 1), - [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), - [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), - [F_IN_INPUT_EN] = REG_FIELD(VADC_CONV_REQ, 0, 0), - [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), - [F_CURR_MON_EN] = REG_FIELD(IADC_CONV_REQ, 0, 0), - [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), - [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 7), - [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), -}; - -static const struct reg_field bcl_v3_bmx_reg_fields[] = { - [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), - [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), - [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), - [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), - [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), - [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), - [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), - [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR_GEN3, 0, 7), - [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), -}; - -static const struct reg_field bcl_v3_wb_reg_fields[] = { - [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), - [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), - [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), - [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), - [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), - [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), - [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), - [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 3), - [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), -}; - -static const struct reg_field bcl_v3_core_reg_fields[] = { - [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), - [F_IN_L0_THR] = REG_FIELD(VCMP_L0_THR, 0, 5), - [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), - [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), - [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), - [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), -}; - -static const struct reg_field bcl_v4_bmx_reg_fields[] = { - [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), - [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), - [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), - [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), - [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 15), - [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), - [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), - [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR_GEN3, 0, 7), - [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 15), -}; - -static const struct reg_field bcl_v4_wb_reg_fields[] = { - [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), - [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), - [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 6), - [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), - [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 15), - [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), - [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), - [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 4), - [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 15), -}; - -static const struct reg_field bcl_v4_core_reg_fields[] = { - [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), - [F_IN_L0_THR] = REG_FIELD(VCMP_L0_THR, 0, 6), - [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 6), - [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), - [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 15), - [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), -}; - -/* V1 BMX and core */ -static const struct bcl_desc pm7250b_data = { - .reg_fields = bcl_v1_reg_fields, - .num_reg_fields = F_MAX_FIELDS, - .data_field_bits_size = 8, - .thresh_field_bits_size = 7, - .channel[IN] = { - .base = 2250, - .max = 3600, - .step = 25, - .default_scale_nu = 194637, - .thresh_type = {ADC, INDEX}, - }, - .channel[CURR] = { - .max = 10000, - .default_scale_nu = 305180, - .thresh_type = {ADC, ADC}, - }, -}; - -/* V2 BMX and core */ -static const struct bcl_desc pm8350_data = { - .reg_fields = bcl_v2_reg_fields, - .num_reg_fields = F_MAX_FIELDS, - .data_field_bits_size = 8, - .thresh_field_bits_size = 8, - .channel[IN] = { - .base = 2250, - .max = 3600, - .step = 25, - .default_scale_nu = 194637, - .thresh_type = {ADC, INDEX}, - }, - .channel[CURR] = { - .max = 10000, - .default_scale_nu = 305180, - .thresh_type = {ADC, ADC}, - }, -}; - -/* V3 BMX */ -static const struct bcl_desc pm8550b_data = { - .reg_fields = bcl_v3_bmx_reg_fields, - .num_reg_fields = F_MAX_FIELDS, - .data_field_bits_size = 8, - .thresh_field_bits_size = 8, - .channel[IN] = { - .base = 2250, - .max = 3600, - .step = 25, - .default_scale_nu = 194637, - .thresh_type = {ADC, INDEX}, - }, - .channel[CURR] = { - .max = 12000, - .default_scale_nu = 366220, - .thresh_type = {ADC, ADC}, - }, -}; - -/* V3 WB */ -static const struct bcl_desc pmw5100_data = { - .reg_fields = bcl_v3_wb_reg_fields, - .num_reg_fields = F_MAX_FIELDS, - .data_field_bits_size = 8, - .thresh_field_bits_size = 8, - .channel[IN] = { - .base = 2250, - .max = 3600, - .step = 25, - .default_scale_nu = 194637, - .thresh_type = {ADC, INDEX}, - }, - .channel[CURR] = { - .base = 800, - .max = 2000, - .step = 100, - .default_scale_nu = 61035, - .thresh_type = {ADC, INDEX}, - }, -}; - -/* V3 CORE */ -static const struct bcl_desc pm8550_data = { - .reg_fields = bcl_v3_core_reg_fields, - .num_reg_fields = F_CURR_MON_EN + 1, - .data_field_bits_size = 8, - .thresh_field_bits_size = 8, - .channel[IN] = { - .base = 2250, - .max = 3600, - .step = 25, - .thresh_type = {INDEX, INDEX}, - }, -}; - -/* V4 BMX */ -static const struct bcl_desc pmih010_data = { - .reg_fields = bcl_v4_bmx_reg_fields, - .num_reg_fields = F_MAX_FIELDS, - .data_field_bits_size = 16, - .thresh_field_bits_size = 8, - .channel[IN] = { - .base = 2250, - .max = 3600, - .step = 25, - .default_scale_nu = 194637, - .thresh_type = {ADC, INDEX}, - }, - .channel[CURR] = { - .max = 20000, - .default_scale_nu = 610370, - .thresh_type = {ADC, ADC}, - }, -}; - -/* V4 WB */ -static const struct bcl_desc pmw6100_data = { - .reg_fields = bcl_v4_wb_reg_fields, - .num_reg_fields = F_MAX_FIELDS, - .data_field_bits_size = 16, - .thresh_field_bits_size = 8, - .channel[IN] = { - .base = 1500, - .max = 4000, - .step = 25, - .default_scale_nu = 194637, - .thresh_type = {ADC, INDEX}, - }, - .channel[CURR] = { - .base = 900, - .max = 3300, - .step = 150, - .default_scale_nu = 152586, - .thresh_type = {ADC, INDEX}, - }, -}; - -/* V4 CORE */ -static const struct bcl_desc pmh010_data = { - .reg_fields = bcl_v4_core_reg_fields, - .num_reg_fields = F_CURR_MON_EN + 1, - .thresh_field_bits_size = 8, - .channel[IN] = { - .base = 1500, - .max = 4000, - .step = 25, - .thresh_type = {INDEX, INDEX}, - }, -}; - -/* V4 BMX with different scale */ -static const struct bcl_desc pmv010_data = { - .reg_fields = bcl_v4_bmx_reg_fields, - .num_reg_fields = F_MAX_FIELDS, - .data_field_bits_size = 16, - .thresh_field_bits_size = 8, - .channel[IN] = { - .base = 2250, - .max = 3600, - .step = 25, - .default_scale_nu = 194637, - .thresh_type = {ADC, INDEX}, - }, - .channel[CURR] = { - .max = 12000, - .default_scale_nu = 366220, - .thresh_type = {ADC, ADC}, - }, -}; - -/** - * bcl_convert_raw_to_milliunit - Convert raw value to milli unit - * @desc: BCL device descriptor - * @raw_val: Raw ADC value from hardware - * @type: type of the channel, in or curr - * @field_width: bits size for data or threshold field - * - * Return: value in milli unit - */ -static unsigned int bcl_convert_raw_to_milliunit(const struct bcl_desc *desc, int raw_val, - enum bcl_channel_type type, u8 field_width) -{ - u32 def_scale = desc->channel[type].default_scale_nu; - u32 lsb_weight = field_width > 8 ? 1 : 1 << field_width; - u32 scaling_factor = def_scale * lsb_weight; - - return div_s64((s64)raw_val * scaling_factor, 1000000); -} - -/** - * bcl_convert_milliunit_to_raw - Convert milli unit to raw value - * @desc: BCL device descriptor - * @ma_val: threshold value in milli unit - * @type: type of the channel, in or curr - * @field_width: bits size for data or threshold field - * - * Return: Raw ADC value for hardware - */ -static unsigned int bcl_convert_milliunit_to_raw(const struct bcl_desc *desc, int mval, - enum bcl_channel_type type, u8 field_width) -{ - u32 def_scale = desc->channel[type].default_scale_nu; - u32 lsb_weight = field_width > 8 ? 1 : 1 << field_width; - u32 scaling_factor = def_scale * lsb_weight; - - return div_s64((s64)mval * 1000000, scaling_factor); -} - -/** - * bcl_convert_milliunit_to_index - Convert milliunit to in or curr index - * @desc: BCL device descriptor - * @val: in or curr value in milli unit - * @type: type of the channel, in or curr - * - * Converts a value in milli unit to an index for BCL that use indexed thresholds. - * - * Return: Voltage index value - */ -static unsigned int bcl_convert_milliunit_to_index(const struct bcl_desc *desc, int val, - enum bcl_channel_type type) -{ - return div_s64((s64)val - desc->channel[type].base, desc->channel[type].step); -} - -/** - * bcl_convert_index_to_milliunit - Convert in or curr index to milli unit - * @desc: BCL device descriptor - * @val: index value - * @type: type of the channel, in or curr - * - * Converts an index value to milli unit for BCL that use indexed thresholds. - * - * Return: Voltage value in millivolts - */ -static unsigned int bcl_convert_index_to_milliunit(const struct bcl_desc *desc, int val, - enum bcl_channel_type type) -{ - return desc->channel[type].base + val * desc->channel[type].step; -} - -static int bcl_in_thresh_write(struct bcl_device *bcl, long value, enum bcl_limit_alarm lvl) -{ - const struct bcl_desc *desc = bcl->desc; - u32 raw_val; - - int thresh = clamp_val(value, desc->channel[IN].base, desc->channel[IN].max); - - if (desc->channel[IN].thresh_type[lvl] == ADC) - raw_val = bcl_convert_milliunit_to_raw(desc, thresh, IN, - desc->thresh_field_bits_size); - else - raw_val = bcl_convert_milliunit_to_index(desc, thresh, IN); - - return regmap_field_write(bcl->fields[F_IN_L0_THR + lvl], raw_val); -} - -static int bcl_curr_thresh_write(struct bcl_device *bcl, long value, enum bcl_limit_alarm lvl) -{ - const struct bcl_desc *desc = bcl->desc; - u32 raw_val; - - /* Clamp only to curr max */ - int thresh = clamp_val(value, value, desc->channel[CURR].max); - - if (desc->channel[CURR].thresh_type[lvl] == ADC) - raw_val = bcl_convert_milliunit_to_raw(desc, thresh, CURR, - desc->thresh_field_bits_size); - else - raw_val = bcl_convert_milliunit_to_index(desc, thresh, CURR); - - return regmap_field_write(bcl->fields[F_CURR_H0_THR + lvl], raw_val); -} - -static int bcl_in_thresh_read(struct bcl_device *bcl, enum bcl_limit_alarm lvl, long *out) -{ - int ret, thresh; - u32 raw_val = 0; - const struct bcl_desc *desc = bcl->desc; - - ret = bcl_read_field_value(bcl, F_IN_L0_THR + lvl, &raw_val); - if (ret) - return ret; - - if (desc->channel[IN].thresh_type[lvl] == ADC) - thresh = bcl_convert_raw_to_milliunit(desc, raw_val, IN, - desc->thresh_field_bits_size); - else - thresh = bcl_convert_index_to_milliunit(desc, raw_val, IN); - - *out = thresh; - - return 0; -} - -static int bcl_curr_thresh_read(struct bcl_device *bcl, enum bcl_limit_alarm lvl, long *out) -{ - int ret, thresh; - u32 raw_val = 0; - const struct bcl_desc *desc = bcl->desc; - - ret = bcl_read_field_value(bcl, F_CURR_H0_THR + lvl, &raw_val); - if (ret) - return ret; - - if (desc->channel[CURR].thresh_type[lvl] == ADC) - thresh = bcl_convert_raw_to_milliunit(desc, raw_val, CURR, - desc->thresh_field_bits_size); - else - thresh = bcl_convert_index_to_milliunit(desc, raw_val, CURR); - - *out = thresh; - - return 0; -} - -static int bcl_curr_input_read(struct bcl_device *bcl, long *out) -{ - int ret; - u32 raw_val = 0; - const struct bcl_desc *desc = bcl->desc; - - ret = bcl_read_field_value(bcl, F_CURR_INPUT, &raw_val); - if (ret) - return ret; - - /* - * The sensor sometime can read a value 0 if there are - * consecutive reads - */ - if (raw_val != 0) - bcl->last_curr_input = - bcl_convert_raw_to_milliunit(desc, raw_val, CURR, - desc->data_field_bits_size); - - *out = bcl->last_curr_input; - - return 0; -} - -static int bcl_in_input_read(struct bcl_device *bcl, long *out) -{ - int ret; - u32 raw_val = 0; - const struct bcl_desc *desc = bcl->desc; - - ret = bcl_read_field_value(bcl, F_IN_INPUT, &raw_val); - if (ret) - return ret; - - if (raw_val < GENMASK(desc->data_field_bits_size - 1, 0)) - bcl->last_in_input = - bcl_convert_raw_to_milliunit(desc, raw_val, IN, - desc->data_field_bits_size); - - *out = bcl->last_in_input; - - return 0; -} - -static int bcl_read_alarm_status(struct bcl_device *bcl, - enum bcl_limit_alarm lvl, long *status) -{ - int ret; - u32 raw_val = 0; - - ret = bcl_read_field_value(bcl, F_LVL0_ALARM + lvl, &raw_val); - if (ret) - return ret; - - *status = raw_val; - - return 0; -} - -static unsigned int bcl_get_version_major(const struct bcl_device *bcl) -{ - u32 raw_val = 0; - - bcl_read_field_value(bcl, F_V_MAJOR, &raw_val); - - return raw_val; -} - -static unsigned int bcl_get_version_minor(const struct bcl_device *bcl) -{ - u32 raw_val = 0; - - bcl_read_field_value(bcl, F_V_MINOR, &raw_val); - - return raw_val; -} - -static void bcl_hwmon_notify_event(struct bcl_device *bcl, enum bcl_limit_alarm alarm) -{ - if (bcl->in_mon_enabled) - hwmon_notify_event(bcl->hwmon_dev, hwmon_in, - in_lvl_to_attr_map[alarm], 0); - if (bcl->curr_mon_enabled) - hwmon_notify_event(bcl->hwmon_dev, hwmon_curr, - curr_lvl_to_attr_map[alarm], 0); -} - -static void bcl_alarm_enable_poll(struct work_struct *work) -{ - struct bcl_alarm_data *alarm = container_of(work, struct bcl_alarm_data, - alarm_poll_work.work); - struct bcl_device *bcl = alarm->device; - long status; - - guard(mutex)(&bcl->lock); - - if (bcl_read_alarm_status(bcl, alarm->type, &status)) - goto re_schedule; - - if (!status & !alarm->irq_enabled) { - bcl_enable_irq(alarm); - bcl_hwmon_notify_event(bcl, alarm->type); - return; - } - -re_schedule: - schedule_delayed_work(&alarm->alarm_poll_work, - msecs_to_jiffies(BCL_ALARM_POLLING_MS)); -} - -static irqreturn_t bcl_handle_alarm(int irq, void *data) -{ - struct bcl_alarm_data *alarm = data; - struct bcl_device *bcl = alarm->device; - long status; - - guard(mutex)(&bcl->lock); - - if (bcl_read_alarm_status(bcl, alarm->type, &status) || !status) - return IRQ_HANDLED; - - if (!bcl->hwmon_dev) - return IRQ_HANDLED; - - bcl_hwmon_notify_event(bcl, alarm->type); - - bcl_disable_irq(alarm); - schedule_delayed_work(&alarm->alarm_poll_work, - msecs_to_jiffies(BCL_ALARM_POLLING_MS)); - - dev_dbg(bcl->dev, "Irq:%d triggered for bcl type:%d\n", - irq, alarm->type); - - return IRQ_HANDLED; -} - -static umode_t bcl_hwmon_is_visible(const void *data, - enum hwmon_sensor_types type, - u32 attr, int channel) -{ - const struct bcl_device *bcl = data; - - switch (type) { - case hwmon_in: - if (!bcl->in_mon_enabled) - return 0; - switch (attr) { - case hwmon_in_input: - return bcl->in_input_enabled ? 0444 : 0; - case hwmon_in_label: - case hwmon_in_min_alarm: - case hwmon_in_lcrit_alarm: - return 0444; - case hwmon_in_min: - case hwmon_in_lcrit: - return 0644; - default: - return 0; - } - case hwmon_curr: - if (!bcl->curr_mon_enabled) - return 0; - switch (attr) { - case hwmon_curr_input: - case hwmon_curr_label: - case hwmon_curr_max_alarm: - case hwmon_curr_crit_alarm: - return 0444; - case hwmon_curr_max: - case hwmon_curr_crit: - return 0644; - default: - return 0; - } - default: - return 0; - } -} - -static int bcl_hwmon_write(struct device *dev, enum hwmon_sensor_types type, - u32 attr, int channel, long val) -{ - struct bcl_device *bcl = dev_get_drvdata(dev); - int ret = -EOPNOTSUPP; - - guard(mutex)(&bcl->lock); - - switch (type) { - case hwmon_in: - switch (attr) { - case hwmon_in_min: - case hwmon_in_lcrit: - ret = bcl_in_thresh_write(bcl, val, in_attr_to_lvl_map[attr]); - break; - default: - ret = -EOPNOTSUPP; - } - break; - case hwmon_curr: - switch (attr) { - case hwmon_curr_max: - case hwmon_curr_crit: - ret = bcl_curr_thresh_write(bcl, val, curr_attr_to_lvl_map[attr]); - break; - default: - ret = -EOPNOTSUPP; - } - break; - default: - break; - } - - return ret; -} - -static int bcl_hwmon_read(struct device *dev, enum hwmon_sensor_types type, - u32 attr, int channel, long *value) -{ - struct bcl_device *bcl = dev_get_drvdata(dev); - int ret; - - guard(mutex)(&bcl->lock); - - switch (type) { - case hwmon_in: - switch (attr) { - case hwmon_in_input: - ret = bcl_in_input_read(bcl, value); - break; - case hwmon_in_min: - case hwmon_in_lcrit: - ret = bcl_in_thresh_read(bcl, in_attr_to_lvl_map[attr], value); - break; - case hwmon_in_min_alarm: - case hwmon_in_lcrit_alarm: - ret = bcl_read_alarm_status(bcl, in_attr_to_lvl_map[attr], value); - break; - default: - ret = -EOPNOTSUPP; - } - break; - case hwmon_curr: - switch (attr) { - case hwmon_curr_input: - ret = bcl_curr_input_read(bcl, value); - break; - case hwmon_curr_max: - case hwmon_curr_crit: - ret = bcl_curr_thresh_read(bcl, curr_attr_to_lvl_map[attr], value); - break; - case hwmon_curr_max_alarm: - case hwmon_curr_crit_alarm: - ret = bcl_read_alarm_status(bcl, curr_attr_to_lvl_map[attr], value); - break; - default: - ret = -EOPNOTSUPP; - } - break; - default: - ret = -EOPNOTSUPP; - break; - } - - return ret; -} - -static int bcl_hwmon_read_string(struct device *dev, - enum hwmon_sensor_types type, - u32 attr, int channel, const char **str) -{ - switch (type) { - case hwmon_in: - if (attr != hwmon_in_label) - break; - *str = bcl_channel_label[IN]; - return 0; - case hwmon_curr: - if (attr != hwmon_curr_label) - break; - *str = bcl_channel_label[CURR]; - return 0; - default: - break; - } - - return -EOPNOTSUPP; -} - -static const struct hwmon_ops bcl_hwmon_ops = { - .is_visible = bcl_hwmon_is_visible, - .read = bcl_hwmon_read, - .read_string = bcl_hwmon_read_string, - .write = bcl_hwmon_write, -}; - -static const struct hwmon_channel_info *bcl_hwmon_info[] = { - HWMON_CHANNEL_INFO(in, - HWMON_I_INPUT | HWMON_I_LABEL | HWMON_I_MIN | - HWMON_I_LCRIT | HWMON_I_MIN_ALARM | - HWMON_I_LCRIT_ALARM), - HWMON_CHANNEL_INFO(curr, - HWMON_C_INPUT | HWMON_C_LABEL | HWMON_C_MAX | - HWMON_C_CRIT | HWMON_C_MAX_ALARM | - HWMON_C_CRIT_ALARM), - NULL, -}; - -static const struct hwmon_chip_info bcl_hwmon_chip_info = { - .ops = &bcl_hwmon_ops, - .info = bcl_hwmon_info, -}; - -static int bcl_curr_thresh_update(struct bcl_device *bcl) -{ - int ret, i; - - if (!bcl->curr_thresholds[0]) - return 0; - - for (i = 0; i < ALARM_MAX; i++) { - ret = bcl_curr_thresh_write(bcl, bcl->curr_thresholds[i], i); - if (ret < 0) - return ret; - } - - return 0; -} - -static void bcl_hw_channel_mon_init(struct bcl_device *bcl) -{ - bcl->in_mon_enabled = bcl_in_monitor_enabled(bcl); - bcl->in_input_enabled = bcl_in_input_enabled(bcl); - bcl->curr_mon_enabled = bcl_curr_monitor_enabled(bcl); -} - -static int bcl_alarm_irq_init(struct platform_device *pdev, - struct bcl_device *bcl) -{ - int ret = 0, irq_num = 0, i = 0; - struct bcl_alarm_data *alarm; - - for (i = LVL0; i < ALARM_MAX; i++) { - alarm = &bcl->bcl_alarms[i]; - alarm->type = i; - alarm->device = bcl; - - ret = devm_delayed_work_autocancel(bcl->dev, &alarm->alarm_poll_work, - bcl_alarm_enable_poll); - if (ret) - return ret; - - irq_num = platform_get_irq_byname(pdev, bcl_int_names[i]); - if (irq_num <= 0) - continue; - - ret = devm_request_threaded_irq(&pdev->dev, irq_num, NULL, - bcl_handle_alarm, IRQF_ONESHOT, - bcl_int_names[i], alarm); - if (ret) { - dev_err(&pdev->dev, "Error requesting irq(%s).err:%d\n", - bcl_int_names[i], ret); - return ret; - } - alarm->irq = irq_num; - enable_irq_wake(alarm->irq); - alarm->irq_enabled = true; - } - - return 0; -} - -static int bcl_regmap_field_init(struct device *dev, struct bcl_device *bcl, - const struct bcl_desc *data) -{ - int i; - struct reg_field fields[F_MAX_FIELDS]; - - BUILD_BUG_ON(ARRAY_SIZE(common_reg_fields) != COMMON_FIELD_MAX); - - for (i = 0; i < data->num_reg_fields; i++) { - if (i < COMMON_FIELD_MAX) - fields[i] = common_reg_fields[i]; - else - fields[i] = data->reg_fields[i]; - - /* Need to adjust BCL base from regmap dynamically */ - fields[i].reg += bcl->base; - } - - return devm_regmap_field_bulk_alloc(dev, bcl->regmap, bcl->fields, - fields, data->num_reg_fields); -} - -static int bcl_get_device_property_data(struct platform_device *pdev, - struct bcl_device *bcl) -{ - struct device *dev = &pdev->dev; - int ret; - u32 reg; - - ret = device_property_read_u32(dev, "reg", ®); - if (ret < 0) - return ret; - - bcl->base = reg; - - device_property_read_u32_array(dev, "overcurrent-thresholds-milliamp", - bcl->curr_thresholds, 2); - return 0; -} - -static int bcl_probe(struct platform_device *pdev) -{ - struct bcl_device *bcl; - int ret; - - bcl = devm_kzalloc(&pdev->dev, sizeof(*bcl), GFP_KERNEL); - if (!bcl) - return -ENOMEM; - - bcl->dev = &pdev->dev; - bcl->desc = device_get_match_data(&pdev->dev); - if (!bcl->desc) - return -EINVAL; - - ret = devm_mutex_init(bcl->dev, &bcl->lock); - if (ret) - return ret; - - bcl->regmap = dev_get_regmap(pdev->dev.parent, NULL); - if (!bcl->regmap) { - dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); - return -EINVAL; - } - - ret = bcl_get_device_property_data(pdev, bcl); - if (ret < 0) - return ret; - - ret = bcl_regmap_field_init(bcl->dev, bcl, bcl->desc); - if (ret < 0) { - dev_err(&pdev->dev, "Unable to allocate regmap fields, err:%d\n", ret); - return ret; - } - - if (!bcl_hw_is_enabled(bcl)) - return -ENODEV; - - ret = bcl_curr_thresh_update(bcl); - if (ret < 0) - return ret; - - ret = bcl_alarm_irq_init(pdev, bcl); - if (ret < 0) - return ret; - - bcl_hw_channel_mon_init(bcl); - - dev_set_drvdata(&pdev->dev, bcl); - - bcl->hwmon_name = devm_hwmon_sanitize_name(&pdev->dev, - dev_name(bcl->dev)); - if (IS_ERR(bcl->hwmon_name)) { - dev_err(&pdev->dev, "Failed to sanitize hwmon name\n"); - return PTR_ERR(bcl->hwmon_name); - } - - bcl->hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, - bcl->hwmon_name, - bcl, - &bcl_hwmon_chip_info, - NULL); - if (IS_ERR(bcl->hwmon_dev)) { - dev_err(&pdev->dev, "Failed to register hwmon device: %ld\n", - PTR_ERR(bcl->hwmon_dev)); - return PTR_ERR(bcl->hwmon_dev); - } - - dev_dbg(&pdev->dev, "BCL hwmon device with version: %u.%u registered\n", - bcl_get_version_major(bcl), bcl_get_version_minor(bcl)); - - return 0; -} - -static const struct of_device_id bcl_match[] = { - { - .compatible = "qcom,bcl-v1", - .data = &pm7250b_data, - }, { - .compatible = "qcom,bcl-v2", - .data = &pm8350_data, - }, { - .compatible = "qcom,bcl-v3-bmx", - .data = &pm8550b_data, - }, { - .compatible = "qcom,bcl-v3-wb", - .data = &pmw5100_data, - }, { - .compatible = "qcom,bcl-v3-core", - .data = &pm8550_data, - }, { - .compatible = "qcom,bcl-v4-bmx", - .data = &pmih010_data, - }, { - .compatible = "qcom,bcl-v4-wb", - .data = &pmw6100_data, - }, { - .compatible = "qcom,bcl-v4-core", - .data = &pmh010_data, - }, { - .compatible = "qcom,bcl-v4-pmv010", - .data = &pmv010_data, - }, - { } -}; -MODULE_DEVICE_TABLE(of, bcl_match); - -static struct platform_driver bcl_driver = { - .probe = bcl_probe, - .driver = { - .name = BCL_DRIVER_NAME, - .of_match_table = bcl_match, - }, -}; - -MODULE_AUTHOR("Manaf Meethalavalappu Pallikunhi "); -MODULE_DESCRIPTION("QCOM BCL HWMON driver"); -module_platform_driver(bcl_driver); -MODULE_LICENSE("GPL"); diff --git a/drivers/hwmon/qcom-bcl-hwmon.h b/drivers/hwmon/qcom-bcl-hwmon.h deleted file mode 100644 index 28a7154d9486a..0000000000000 --- a/drivers/hwmon/qcom-bcl-hwmon.h +++ /dev/null @@ -1,311 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __QCOM_BCL_HWMON_H__ -#define __QCOM_BCL_HWMON_H__ - -#define BCL_DRIVER_NAME "qcom-bcl-hwmon" - -/* BCL common regmap offset */ -#define REVISION1 0x0 -#define REVISION2 0x1 -#define STATUS 0x8 -#define INT_RT_STS 0x10 -#define EN_CTL1 0x46 - -/* BCL GEN1 regmap offsets */ -#define MODE_CTL1 0x41 -#define VADC_L0_THR 0x48 -#define VCMP_L1_THR 0x49 -#define IADC_H0_THR 0x4b -#define IADC_H1_THR 0x4c -#define VADC_CONV_REQ 0x72 -#define IADC_CONV_REQ 0x82 -#define VADC_DATA1 0x76 -#define IADC_DATA1 0x86 - -/* BCL GEN3 regmap offsets */ -#define VCMP_CTL 0x44 -#define VCMP_L0_THR 0x47 -#define PARAM_1 0x0e -#define IADC_H1_THR_GEN3 0x4d - -#define BCL_IN_INC_MV 25 -#define BCL_ALARM_POLLING_MS 50 - -/** - * enum bcl_limit_alarm - BCL alarm threshold levels - * @LVL0: Level 0 alarm threshold (mapped to in_min_alarm or curr_max_alarm) - * @LVL1: Level 1 alarm threshold (mapped to in_lcrit_alarm or curr_crit_alarm) - * @ALARM_MAX: sentinel value - * - * Defines the three threshold levels for BCL monitoring. Each level corresponds - * to different severity of in or curr conditions. - */ -enum bcl_limit_alarm { - LVL0, - LVL1, - - ALARM_MAX, -}; - -/** - * enum bcl_channel_type - BCL supported sensor channel type - * @IN: in (voltage) channel - * @CURR: curr (current) channel - * @CHANNEL_MAX: sentinel value - * - * Defines the supported channel types for bcl. - */ -enum bcl_channel_type { - IN, - CURR, - - CHANNEL_MAX, -}; - -/** - * enum bcl_thresh_type - voltage or current threshold representation type - * @ADC: Raw ADC value representation - * @INDEX: Index-based voltage or current representation - * - * Specifies how voltage or current thresholds are stored and interpreted in - * registers. Some PMICs use raw ADC values while others use indexed values. - */ -enum bcl_thresh_type { - ADC, - INDEX, -}; - -/** - * enum bcl_fields - BCL register field identifiers - * @F_V_MAJOR: Major revision info field - * @F_V_MINOR: Minor revision info field - * @F_CTL_EN: Monitor enable control field - * @F_LVL0_ALARM: Level 0 alarm status field - * @F_LVL1_ALARM: Level 1 alarm status field - * @COMMON_FIELD_MAX: sentinel value for common fields - * @F_IN_MON_EN: voltage monitor enable control field - * @F_IN_L0_THR: voltage level 0 threshold field - * @F_IN_L1_THR: voltage level 1 threshold field - * @F_IN_INPUT_EN: voltage input enable control field - * @F_IN_INPUT: voltage input data field - * @F_CURR_MON_EN: current monitor enable control field - * @F_CURR_H0_THR: current level 0 threshold field - * @F_CURR_H1_THR: current level 1 threshold field - * @F_CURR_INPUT: current input data field - * @F_MAX_FIELDS: sentinel value - * - * Enumeration of all register fields used by the BCL driver for accessing - * registers through regmap fields. - */ -enum bcl_fields { - F_V_MAJOR, - F_V_MINOR, - - F_CTL_EN, - - /* common alarm for in and curr channel */ - F_LVL0_ALARM, - F_LVL1_ALARM, - - COMMON_FIELD_MAX, - - F_IN_MON_EN = COMMON_FIELD_MAX, - F_IN_L0_THR, - F_IN_L1_THR, - - F_IN_INPUT_EN, - F_IN_INPUT, - - F_CURR_MON_EN, - F_CURR_H0_THR, - F_CURR_H1_THR, - - F_CURR_INPUT, - - F_MAX_FIELDS -}; - -#define ADD_BCL_HWMON_ALARM_MAPS(_type, lvl0_attr, lvl1_attr) \ - \ -static const u8 _type##_attr_to_lvl_map[] = { \ - [hwmon_##_type##_##lvl0_attr] = LVL0, \ - [hwmon_##_type##_##lvl1_attr] = LVL1, \ - [hwmon_##_type##_##lvl0_attr##_alarm] = LVL0, \ - [hwmon_##_type##_##lvl1_attr##_alarm] = LVL1, \ -}; \ - \ -static const u8 _type##_lvl_to_attr_map[ALARM_MAX] = { \ - [LVL0] = hwmon_##_type##_##lvl0_attr##_alarm, \ - [LVL1] = hwmon_##_type##_##lvl1_attr##_alarm, \ -} - -/** - * struct bcl_channel_cfg - BCL channel related configuration - * @default_scale_nu: Default scaling factor in nano unit - * @base: Base threshold value in milli unit - * @max: Maximum threshold value in milli unit - * @step: step increment value between two indexed threshold value - * @thresh_type: Array specifying threshold representation type for each alarm level - * - * Contains hardware-specific configuration and scaling parameters for different - * channel(voltage and current).. - */ - -struct bcl_channel_cfg { - u32 default_scale_nu; - u32 base; - u32 max; - u32 step; - u8 thresh_type[ALARM_MAX]; -}; - -/** - * struct bcl_desc - BCL device descriptor - * @reg_fields: Array of register field definitions for this device variant - * @channel: Each channel specific(voltage or current) configuration - * @num_reg_fields: Number of register field definitions for this device variant - * @data_field_bits_size: data read register bit size - * @thresh_field_bits_size: lsb bit size those are not included in threshold register - * - * Contains hardware-specific configuration and scaling parameters for different - * BCL variants. Each PMIC model may have different register layouts and - * conversion factors. - */ - -struct bcl_desc { - const struct reg_field *reg_fields; - struct bcl_channel_cfg channel[CHANNEL_MAX]; - u8 num_reg_fields; - u8 data_field_bits_size; - u8 thresh_field_bits_size; -}; - -struct bcl_device; - -/** - * struct bcl_alarm_data - BCL alarm interrupt data - * @irq: IRQ number assigned to this alarm - * @irq_enabled: Flag indicating if IRQ is enabled - * @type: Alarm level type (LVL0, or LVL1) - * @device: Pointer to parent BCL device structure - * @alarm_poll_work: delayed_work to poll alarm status - * - * Stores interrupt-related information for each alarm threshold level. - * Used by the IRQ handler to identify which alarm triggered. - */ -struct bcl_alarm_data { - int irq; - bool irq_enabled; - enum bcl_limit_alarm type; - struct bcl_device *device; - struct delayed_work alarm_poll_work; -}; - -/** - * struct bcl_device - Main BCL device structure - * @dev: Pointer to device structure - * @regmap: Regmap for accessing PMIC registers - * @fields: Array of regmap fields for register access - * @bcl_alarms: Array of alarm data structures for each threshold level - * @lock: Mutex for protecting concurrent hardware access - * @in_mon_enabled: Flag indicating if voltage monitoring is enabled - * @curr_mon_enabled: Flag indicating if current monitoring is enabled - * @curr_thresholds: Current threshold values in milliamps from dt-binding(LVL0 and LVL1) - * @base: the BCL regbase offset from regmap - * @in_input_enabled: Flag indicating if voltage input reading is enabled - * @last_in_input: Last valid voltage input reading in millivolts - * @last_curr_input: Last valid current input reading in milliamps - * @desc: Pointer to device descriptor with hardware-specific parameters - * @hwmon_dev: Pointer to registered hwmon device - * @hwmon_name: Sanitized name for hwmon device - * - * Main driver structure containing all state and configuration for a BCL - * monitoring instance. Manages voltage and current monitoring, thresholds, - * and alarm handling. - */ -struct bcl_device { - struct device *dev; - struct regmap *regmap; - u16 base; - struct regmap_field *fields[F_MAX_FIELDS]; - struct bcl_alarm_data bcl_alarms[ALARM_MAX]; - struct mutex lock; - u32 curr_thresholds[ALARM_MAX]; - u32 last_in_input; - u32 last_curr_input; - bool in_mon_enabled; - bool curr_mon_enabled; - bool in_input_enabled; - const struct bcl_desc *desc; - struct device *hwmon_dev; - char *hwmon_name; -}; - -/** - * bcl_read_field_value - Read alarm status for a given level - * @bcl: BCL device structure - * @id: Index in bcl->fields[] - * @val: Pointer to store val - * - * Return: 0 on success or regmap error code - */ -static inline int bcl_read_field_value(const struct bcl_device *bcl, enum bcl_fields id, u32 *val) -{ - return regmap_field_read(bcl->fields[id], val); -} - -/** - * bcl_field_enabled - Generic helper to check if a regmap field is enabled - * @bcl: BCL device structure - * @field: Index in bcl->fields[] - * - * Return: true if field is non-zero, false otherwise - */ -static inline bool bcl_field_enabled(const struct bcl_device *bcl, enum bcl_fields id) -{ - int ret; - u32 val = 0; - - ret = regmap_field_read(bcl->fields[id], &val); - if (ret) - return false; - - return !!val; -} - -#define bcl_in_input_enabled(bcl) bcl_field_enabled(bcl, F_IN_INPUT_EN) -#define bcl_curr_monitor_enabled(bcl) bcl_field_enabled(bcl, F_CURR_MON_EN) -#define bcl_in_monitor_enabled(bcl) bcl_field_enabled(bcl, F_IN_MON_EN) -#define bcl_hw_is_enabled(bcl) bcl_field_enabled(bcl, F_CTL_EN) - -/** - * bcl_enable_irq - Generic helper to enable alarm irq - * @alarm: BCL level alarm data - */ -static inline void bcl_enable_irq(struct bcl_alarm_data *alarm) -{ - if (alarm->irq_enabled) - return; - alarm->irq_enabled = true; - enable_irq(alarm->irq); - enable_irq_wake(alarm->irq); -} - -/** - * bcl_disable_irq - Generic helper to disable alarm irq - * @alarm: BCL level alarm data - */ -static inline void bcl_disable_irq(struct bcl_alarm_data *alarm) -{ - if (!alarm->irq_enabled) - return; - alarm->irq_enabled = false; - disable_irq_nosync(alarm->irq); - disable_irq_wake(alarm->irq); -} - -#endif /* __QCOM_BCL_HWMON_H__ */ From 75e153b78f3d1648bbc95b440a0e6002c5c9035d Mon Sep 17 00:00:00 2001 From: Dipa Ramesh Mantre Date: Tue, 11 Aug 2026 14:40:49 +0530 Subject: [PATCH 1319/1330] Revert "FROMLIST: dt-bindings: hwmon: Add qcom,bcl-hwmon yaml bindings" This reverts commit ed4fe7a80ab7db48bc007abe4f431c34532e0003. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre --- .../bindings/hwmon/qcom,bcl-hwmon.yaml | 128 ------------------ .../bindings/mfd/qcom,spmi-pmic.yaml | 4 - 2 files changed, 132 deletions(-) delete mode 100644 Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml diff --git a/Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml deleted file mode 100644 index 6ffadc4d28bcf..0000000000000 --- a/Documentation/devicetree/bindings/hwmon/qcom,bcl-hwmon.yaml +++ /dev/null @@ -1,128 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/hwmon/qcom,bcl-hwmon.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SPMI PMIC Battery Current Limiting (BCL) Hardware Monitor - -maintainers: - - Manaf Meethalavalappu Pallikunhi - -description: | - SPMI PMIC Battery Current Limiting (BCL) hardware provides monitoring and - alarm functionality for battery overcurrent and battery or system under - voltage conditions. It monitors battery voltage and current, and - can trigger interrupts when configurable thresholds are exceeded. - -properties: - compatible: - oneOf: - - description: v1 based BCL - items: - - enum: - - qcom,pm7250b-bcl - - qcom,pm8250b-bcl - - const: qcom,bcl-v1 - - - description: v2 based BCL - items: - - enum: - - qcom,pm8350b-bcl - - qcom,pm8350c-bcl - - const: qcom,bcl-v2 - - - description: v3 bmx based BCL - items: - - enum: - - qcom,pm8550b-bcl - - qcom,pm7550ba-bcl - - const: qcom,bcl-v3-bmx - - - description: v3 core based BCL - items: - - enum: - - qcom,pm8550-bc0l - - qcom,pm7550-bcl - - const: qcom,bcl-v3-core - - - description: v3 wb based BCL - items: - - enum: - - qcom,pmw5100-bcl - - const: qcom,bcl-v3-wb - - - description: v4 bmx based BCL - items: - - enum: - - qcom,pmih010-bcl - - const: qcom,bcl-v4-bmx - - - description: v4 bmx with different scale based BCL - items: - - enum: - - qcom,pmv010-bcl - - const: qcom,bcl-v4-pmv010 - - - description: v4 core based BCL - items: - - enum: - - qcom,pmh010-bcl - - const: qcom,bcl-v4-core - - - description: v4 wb based BCL - items: - - enum: - - qcom,pmw6100-bcl - - const: qcom,bcl-v4-wb - - reg: - maxItems: 1 - description: BCL base address in the SPMI PMIC register map - - interrupts: - minItems: 2 - maxItems: 2 - description: - BCL alarm interrupts for different threshold levels - - interrupt-names: - items: - - const: bcl-max-min - - const: bcl-critical - - overcurrent-thresholds-milliamp: - description: - Current thresholds in milliamperes for the two configurable current - alarm levels (max and critical). These values are used to override - default thresholds if a platform has different battery ocp specification. - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 2 - maxItems: 2 - -required: - - compatible - - reg - - interrupts - - interrupt-names - -unevaluatedProperties: false - -examples: - - | - #include - - pmic { - #address-cells = <1>; - #size-cells = <0>; - - sensor@1d00 { - compatible = "qcom,pm7250b-bcl", "qcom,bcl-v1"; - reg = <0x1d00>; - interrupts = <0x2 0x1d 0x0 IRQ_TYPE_EDGE_RISING>, - <0x2 0x1d 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "bcl-max-min", - "bcl-critical"; - overcurrent-thresholds-milliamp = <5500 6000>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 71cbf1c1058ad..bdd304e9eac13 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -193,10 +193,6 @@ patternProperties: type: object $ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml# - "^sensor@[0-9a-f]+$": - type: object - $ref: /schemas/hwmon/qcom,bcl-hwmon.yaml# - "^temp-alarm@[0-9a-f]+$": type: object $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml# From f5940675ab47ced5b0d16118850ec2e334bae382 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 22 Jul 2026 00:00:06 +0530 Subject: [PATCH 1320/1330] FROMLIST: dt-bindings: hwmon: Describe Qualcomm BCL hardware Qualcomm SPMI PMIC BCL (Battery Current Limiting) is a safety feature that monitors battery or system voltage and current to alert system for overcurrent or undervoltage conditions. It provides: - Real-time voltage and current monitoring - Configurable thresholds per channel - Hardware interrupts when thresholds are violated Add a DeviceTree binding to describe the BCL on Qualcomm's PMICs. Add sensor type to SPMI device list for BCL device. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-1-febe2805e17b@oss.qualcomm.com --- .../bindings/hwmon/qcom,pm7250b-bcl.yaml | 64 +++++++++++++++++++ .../bindings/mfd/qcom,spmi-pmic.yaml | 4 ++ MAINTAINERS | 7 ++ 3 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml diff --git a/Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml b/Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml new file mode 100644 index 0000000000000..3c069e94a34e8 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/qcom,pm7250b-bcl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMIC Battery Current Limiting (BCL) Hardware Monitor + +maintainers: + - Manaf Meethalavalappu Pallikunhi + +description: + SPMI PMIC Battery Current Limiting (BCL) hardware provides monitoring and + alarm functionality for battery overcurrent and battery or system under + voltage conditions. It monitors battery voltage and current, and + can trigger interrupts when configurable thresholds are exceeded. + +properties: + compatible: + enum: + - qcom,pm7250b-bcl + - qcom,pm8350c-bcl + - qcom,pm8550-bcl + - qcom,pmh0101-bcl + - qcom,pmih0108-bcl + - qcom,smb2360-bcl + - qcom,smb2370-bcl + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: max-min + - const: critical + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1d00 { + compatible = "qcom,pm7250b-bcl"; + reg = <0x1d00>; + interrupts = <0x2 0x1d 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x1d 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "max-min", + "critical"; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index bdd304e9eac13..825b2497bd380 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -193,6 +193,10 @@ patternProperties: type: object $ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml# + "^sensor@[0-9a-f]+$": + type: object + $ref: /schemas/hwmon/qcom,pm7250b-bcl.yaml# + "^temp-alarm@[0-9a-f]+$": type: object $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml# diff --git a/MAINTAINERS b/MAINTAINERS index 7eb689d4a2598..60fb8df0349af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21670,6 +21670,13 @@ S: Maintained F: Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml F: drivers/net/wwan/qcom_bam_dmux.c +QUALCOMM BCL HARDWARE MONITOR DRIVER +M: Manaf Meethalavalappu Pallikunhi +L: linux-hwmon@vger.kernel.org +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml + QUALCOMM BLUETOOTH DRIVER M: Bartosz Golaszewski L: linux-arm-msm@vger.kernel.org From c517042e2182fce91c1661fb332b0e5151578aba Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Tue, 11 Aug 2026 15:15:39 +0530 Subject: [PATCH 1321/1330] FROMLIST: hwmon: Add Qualcomm PMIC BCL driver Add driver for Qualcomm SPMI PMIC Battery Current Limiting (BCL) hardware monitor. The driver exposes battery voltage and current monitoring through hwmon interface. The BCL driver provides - Real-time voltage and current readings - Configurable threshold-based alarms - Interrupt-driven notifications when thresholds are exceeded - Automatic threshold management with polling-based recovery - Hardware-specific scaling factors and threshold representations Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-2-febe2805e17b@oss.qualcomm.com --- MAINTAINERS | 1 + drivers/hwmon/Kconfig | 11 + drivers/hwmon/Makefile | 1 + drivers/hwmon/qcom-bcl-hwmon.c | 1443 ++++++++++++++++++++++++++++++++ 4 files changed, 1456 insertions(+) create mode 100644 drivers/hwmon/qcom-bcl-hwmon.c diff --git a/MAINTAINERS b/MAINTAINERS index 60fb8df0349af..68f36c68430a1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21676,6 +21676,7 @@ L: linux-hwmon@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml +F: drivers/hwmon/qcom-bcl-hwmon.c QUALCOMM BLUETOOTH DRIVER M: Bartosz Golaszewski diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 4f203fc74512b..04b672dc079a7 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1916,6 +1916,17 @@ config SENSORS_PWM_FAN This driver can also be built as a module. If so, the module will be called pwm-fan. +config SENSORS_QCOM_SPMI_BCL + tristate "Qualcomm SPMI BCL hardware monitoring" + depends on SPMI + select REGMAP_SPMI + help + Say yes here to enable support for Qualcomm battery over current + and under voltage alarms monitor. + + This driver can also be built as a module. If so, the module + will be called qcom-bcl-hwmon. + config SENSORS_QNAP_MCU_HWMON tristate "QNAP MCU hardware monitoring" depends on MFD_QNAP_MCU diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index bfbcc5d8b72a0..c0441172e2f25 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -198,6 +198,7 @@ obj-$(CONFIG_SENSORS_POWERZ) += powerz.o obj-$(CONFIG_SENSORS_POWR1220) += powr1220.o obj-$(CONFIG_SENSORS_PT5161L) += pt5161l.o obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o +obj-$(CONFIG_SENSORS_QCOM_SPMI_BCL) += qcom-bcl-hwmon.o obj-$(CONFIG_SENSORS_QNAP_MCU_HWMON) += qnap-mcu-hwmon.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o obj-$(CONFIG_SENSORS_SBTSI) += sbtsi_temp.o diff --git a/drivers/hwmon/qcom-bcl-hwmon.c b/drivers/hwmon/qcom-bcl-hwmon.c new file mode 100644 index 0000000000000..33bbdd8196d16 --- /dev/null +++ b/drivers/hwmon/qcom-bcl-hwmon.c @@ -0,0 +1,1443 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Qualcomm pmic BCL driver for battery overcurrent and + * battery or system under voltage monitor + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* BCL common regmap offset */ +#define REVISION1 0x0 +#define REVISION2 0x1 +#define STATUS 0x8 +#define INT_RT_STS 0x10 +#define EN_CTL1 0x46 + +/* BCL GEN1 regmap offsets */ +#define MODE_CTL1 0x41 +#define VADC_L0_THR 0x48 +#define VCMP_L1_THR 0x49 +#define IADC_H0_THR 0x4b +#define IADC_H1_THR 0x4c +#define VADC_CONV_REQ 0x72 +#define IADC_CONV_REQ 0x82 +#define VADC_DATA1 0x76 +#define IADC_DATA1 0x86 + +/* BCL GEN3 regmap offsets */ +#define VCMP_CTL 0x44 +#define VCMP_L0_THR 0x47 +#define PARAM_1 0x0e +#define IADC_H1_THR_GEN3 0x4d + +#define BCL_IN_INC_MV 25 +#define BCL_ALARM_POLLING_MS 50 + +/** + * enum bcl_limit_alarm - BCL alarm threshold levels + * @BCL_LIMIT_ALARM_LVL0: Level 0 alarm threshold + * @BCL_LIMIT_ALARM_LVL1: Level 1 alarm threshold + * @BCL_LIMIT_ALARM_MAX: sentinel value + * + * Defines the two threshold levels for BCL monitoring. Each level corresponds + * to different severity of in or curr conditions. + */ +enum bcl_limit_alarm { + BCL_LIMIT_ALARM_LVL0, + BCL_LIMIT_ALARM_LVL1, + + BCL_LIMIT_ALARM_MAX, +}; + +/** + * enum bcl_channel - BCL supported sensor channel type + * @CHANNEL_IN: in (voltage) channel + * @CHANNEL_CURR: curr (current) channel + * @CHANNEL_MAX: sentinel value + * + * Defines the supported channel types for bcl. + */ +enum bcl_channel { + CHANNEL_IN, + CHANNEL_CURR, + + CHANNEL_MAX, +}; + +/** + * enum bcl_thresh_type - voltage or current threshold representation type + * @THRESH_TYPE_ADC: Raw ADC value representation + * @THRESH_TYPE_INDEX: Index-based voltage or current representation + * + * Specifies how voltage or current thresholds are stored and interpreted in + * registers. Some PMICs use raw ADC values while others use indexed values. + */ +enum bcl_thresh_type { + THRESH_TYPE_ADC, + THRESH_TYPE_INDEX, +}; + +/** + * enum bcl_battery_config - Battery configuration types + * @BCL_BATT_1S: Single cell battery + * @BCL_BATT_2S: Two cells in series + * @BCL_BATT_3S: Three cells in series + * @BCL_BATT_UNKNOWN: Unknown or not applicable + */ +enum bcl_battery_config { + BCL_BATT_1S, + BCL_BATT_2S, + BCL_BATT_3S, + BCL_BATT_UNKNOWN, +}; + +/** + * enum bcl_fields - BCL register field identifiers + * @F_V_MAJOR: Major revision info field + * @F_V_MINOR: Minor revision info field + * @F_CTL_EN: Monitor enable control field + * @F_LVL0_ALARM: Level 0 alarm status field + * @F_LVL1_ALARM: Level 1 alarm status field + * @F_IN_MON_EN: voltage monitor enable control field + * @F_IN_L0_THR: voltage level 0 threshold field + * @F_IN_L1_THR: voltage level 1 threshold field + * @F_IN_INPUT_EN: voltage input enable control field + * @F_IN_INPUT: voltage input data field (LSB for 16-bit data) + * @F_IN_INPUT1: voltage input data MSB for 16-bit voltage data + * @F_CURR_MON_EN: current monitor enable control field + * @F_CURR_H0_THR: current level 0 threshold field + * @F_CURR_H1_THR: current level 1 threshold field + * @F_CURR_INPUT: current input data field (LSB for 16-bit data) + * @F_CURR_INPUT1: current input data MSB for 16-bit current data + * @F_MAX_FIELDS: sentinel value + * + * Enumeration of all register fields used by the BCL driver for accessing + * registers through regmap fields. + */ +enum bcl_fields { + /* Common fields - present in all BCL variants */ + F_V_MAJOR, + F_V_MINOR, + F_CTL_EN, + F_LVL0_ALARM, + F_LVL1_ALARM, + + /* Voltage monitoring fields */ + F_IN_MON_EN, + F_IN_L0_THR, + F_IN_L1_THR, + F_IN_INPUT_EN, + F_IN_INPUT, + F_IN_INPUT1, /* MSB for 16-bit voltage data */ + + /* Current monitoring fields */ + F_CURR_MON_EN, + F_CURR_H0_THR, + F_CURR_H1_THR, + F_CURR_INPUT, + F_CURR_INPUT1, /* MSB for 16-bit current data */ + + F_MAX_FIELDS +}; + +/** + * struct bcl_channel_cfg - BCL channel related configuration + * @default_scale_nu: Default scaling factor in nano unit + * @base: Base threshold value in milli unit + * @max: Maximum threshold value in milli unit + * @step: step increment value between two indexed threshold value + * @thresh_type: Array specifying threshold representation type for each alarm level + * + * Contains hardware-specific configuration and scaling parameters for different + * channel(voltage and current).. + */ +struct bcl_channel_cfg { + u32 default_scale_nu; + u32 base; + u32 max; + u32 step; + u8 thresh_type[BCL_LIMIT_ALARM_MAX]; +}; + +/** + * struct bcl_desc - BCL device descriptor + * @reg_fields: Array of register field definitions for this device variant + * @channel_cfg: Array of channel configurations indexed by battery config + * PMICs without battery detection: only [BCL_BATT_1S] is defined + * PMICs with battery detection: [BCL_BATT_2S], [BCL_BATT_3S] + * @battery_config_field: Register field for battery configuration detection + * NOTE: This is an ABSOLUTE address, not relative to BCL base + * Set to REG_FIELD(0, 0, 0) if not used + * @num_reg_fields: Number of register field definitions for this device variant + * @data_field_bits_size: data read register bit size + * @thresh_field_bits_size: lsb bit size those are not included in threshold register + * + * Contains hardware-specific configuration and scaling parameters for different + * BCL variants. Each PMIC model may have different register layouts and + * conversion factors. + */ +struct bcl_desc { + const struct reg_field *reg_fields; + struct bcl_channel_cfg channel_cfg[BCL_BATT_3S + 1][CHANNEL_MAX]; + const struct reg_field battery_config_field; + u8 num_reg_fields; + u8 data_field_bits_size; + u8 thresh_field_bits_size; +}; + +/** + * struct bcl_alarm_data - BCL alarm interrupt data + * @irq: IRQ number assigned to this alarm + * @irq_enabled: Flag indicating if IRQ is enabled + * @irq_wake_enabled: Flag indicating if IRQ wake is enabled + * @shutting_down: Flag preventing work from re-enabling IRQ during teardown + * @type: Alarm level type (LVL0, or LVL1) + * @device: Pointer to parent BCL device structure + * @a_lock: Mutex for protecting alarm state + * @alarm_poll_work: delayed_work to poll alarm status + * + * Stores interrupt-related information for each alarm threshold level. + * Used by the IRQ handler to identify which alarm triggered. + */ +struct bcl_alarm_data { + int irq; + bool irq_enabled; + bool irq_wake_enabled; + bool shutting_down; + enum bcl_limit_alarm type; + void *device; + /* Protects alarm IRQ enable/disable state */ + struct mutex a_lock; + struct delayed_work alarm_poll_work; +}; + +/** + * struct bcl_device - Main BCL device structure + * @dev: Pointer to device structure + * @regmap: Regmap for accessing PMIC registers + * @fields: Array of regmap fields for register access + * @bcl_alarms: Array of alarm data structures for each threshold level + * @lock: Mutex for protecting concurrent hardware access + * @base: the BCL regbase offset from regmap + * @last_in_input: Last valid voltage input reading in millivolts + * @last_curr_input: Last valid current input reading in milliamps + * @last_in_updated: Timestamp of last voltage input update + * @last_curr_updated: Timestamp of last current input update + * @desc: Pointer to device descriptor with hardware-specific parameters + * @hwmon_dev: Pointer to registered hwmon device + * @hwmon_info: Dynamically built hwmon channel info array + * @hwmon_chip_info: Dynamically built hwmon chip info structure + * @hwmon_name: Sanitized name for hwmon device + * @batt_config: Detected battery configuration (only for SMB2360/2370) + * @batt_config_regfield: Regmap field for battery configuration register + * @in_attrs: Voltage channel attributes mask + * @curr_attrs: Current channel attributes mask + * + * Main driver structure containing all state and configuration for a BCL + * monitoring instance. Manages voltage and current monitoring, thresholds, + * and alarm handling. + */ +struct bcl_device { + struct device *dev; + struct regmap *regmap; + u16 base; + struct regmap_field *fields[F_MAX_FIELDS]; + struct bcl_alarm_data bcl_alarms[BCL_LIMIT_ALARM_MAX]; + /* Protects hardware register access and device state */ + struct mutex lock; + u32 last_in_input; + s32 last_curr_input; + unsigned long last_in_updated; + unsigned long last_curr_updated; + const struct bcl_desc *desc; + struct device *hwmon_dev; + const struct hwmon_channel_info **hwmon_info; + struct hwmon_chip_info hwmon_chip_info; + char *hwmon_name; + enum bcl_battery_config batt_config; + struct regmap_field *batt_config_regfield; + u32 in_attrs; + u32 curr_attrs; +}; + +static const u8 in_attr_to_lvl_map[] = { + [hwmon_in_min] = BCL_LIMIT_ALARM_LVL0, + [hwmon_in_lcrit] = BCL_LIMIT_ALARM_LVL1, + [hwmon_in_min_alarm] = BCL_LIMIT_ALARM_LVL0, + [hwmon_in_lcrit_alarm] = BCL_LIMIT_ALARM_LVL1, +}; + +static const u8 in_lvl_to_attr_map[BCL_LIMIT_ALARM_MAX] = { + [BCL_LIMIT_ALARM_LVL0] = hwmon_in_min_alarm, + [BCL_LIMIT_ALARM_LVL1] = hwmon_in_lcrit_alarm, +}; + +static const u8 curr_attr_to_lvl_map[] = { + [hwmon_curr_max] = BCL_LIMIT_ALARM_LVL0, + [hwmon_curr_crit] = BCL_LIMIT_ALARM_LVL1, + [hwmon_curr_max_alarm] = BCL_LIMIT_ALARM_LVL0, + [hwmon_curr_crit_alarm] = BCL_LIMIT_ALARM_LVL1, +}; + +static const u8 curr_lvl_to_attr_map[BCL_LIMIT_ALARM_MAX] = { + [BCL_LIMIT_ALARM_LVL0] = hwmon_curr_max_alarm, + [BCL_LIMIT_ALARM_LVL1] = hwmon_curr_crit_alarm, +}; + +/* Interrupt names for each alarm level */ +static const char * const bcl_int_names[BCL_LIMIT_ALARM_MAX] = { + [BCL_LIMIT_ALARM_LVL0] = "max-min", + [BCL_LIMIT_ALARM_LVL1] = "critical", +}; + +static const struct reg_field bcl_pm7250b_reg_fields[] = { + [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] = REG_FIELD(MODE_CTL1, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(VADC_CONV_REQ, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(IADC_CONV_REQ, 0, 0), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_pm8350c_reg_fields[] = { + [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 1), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(VADC_CONV_REQ, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(IADC_CONV_REQ, 0, 0), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_pm8550_reg_fields[] = { + [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VCMP_L0_THR, 0, 5), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), +}; + +static const struct reg_field bcl_pmh0101_reg_fields[] = { + [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VCMP_L0_THR, 0, 6), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 6), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_IN_INPUT1] = REG_FIELD(VADC_DATA1 + 1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), +}; + +static const struct reg_field bcl_pmih0108_reg_fields[] = { + [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_IN_INPUT1] = REG_FIELD(VADC_DATA1 + 1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR_GEN3, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), + [F_CURR_INPUT1] = REG_FIELD(IADC_DATA1 + 1, 0, 7), +}; + +static const struct reg_field bcl_smb2360_reg_fields[] = { + [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR_GEN3, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_smb2370_reg_fields[] = { + [F_V_MAJOR] = REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] = REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] = REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] = REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] = REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] = REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] = REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] = REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] = REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] = REG_FIELD(VADC_DATA1, 0, 7), + [F_IN_INPUT1] = REG_FIELD(VADC_DATA1 + 1, 0, 7), + [F_CURR_MON_EN] = REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] = REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] = REG_FIELD(IADC_H1_THR_GEN3, 0, 7), + [F_CURR_INPUT] = REG_FIELD(IADC_DATA1, 0, 7), + [F_CURR_INPUT1] = REG_FIELD(IADC_DATA1 + 1, 0, 7), +}; + +static const struct bcl_desc pm7250b_data = { + .reg_fields = bcl_pm7250b_reg_fields, + .num_reg_fields = F_CURR_INPUT + 1, + .data_field_bits_size = 8, + .thresh_field_bits_size = 7, + .battery_config_field = REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_1S][CHANNEL_CURR] = { + .max = 10000, + .default_scale_nu = 305180, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +static const struct bcl_desc pm8350c_data = { + .reg_fields = bcl_pm8350c_reg_fields, + .num_reg_fields = F_CURR_INPUT + 1, + .data_field_bits_size = 8, + .thresh_field_bits_size = 8, + .battery_config_field = REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_1S][CHANNEL_CURR] = { + .max = 10000, + .default_scale_nu = 305180, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +static const struct bcl_desc pm8550_data = { + .reg_fields = bcl_pm8550_reg_fields, + .num_reg_fields = F_CURR_MON_EN + 1, + .data_field_bits_size = 0, + .thresh_field_bits_size = 8, + .battery_config_field = REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .thresh_type = {THRESH_TYPE_INDEX, THRESH_TYPE_INDEX}, + }, +}; + +static const struct bcl_desc pmih0108_data = { + .reg_fields = bcl_pmih0108_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 16, + .thresh_field_bits_size = 8, + .battery_config_field = REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] = { + .base = 2250, + .max = 3600, + .step = 25, + .default_scale_nu = 194637, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_1S][CHANNEL_CURR] = { + .max = 20000, + .default_scale_nu = 610370, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +static const struct bcl_desc pmh0101_data = { + .reg_fields = bcl_pmh0101_reg_fields, + .num_reg_fields = F_CURR_MON_EN + 1, + .thresh_field_bits_size = 8, + .battery_config_field = REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] = { + .base = 1500, + .max = 4000, + .step = 25, + .thresh_type = {THRESH_TYPE_INDEX, THRESH_TYPE_INDEX}, + }, +}; + +/* Register 0x2a50 mapping: 0 -> 2S, 1 -> 3S */ +static const struct bcl_desc smb2360_data = { + .reg_fields = bcl_smb2360_reg_fields, + .num_reg_fields = F_CURR_INPUT + 1, + .data_field_bits_size = 8, + .thresh_field_bits_size = 8, + .battery_config_field = REG_FIELD(0x2a50, 0, 1), + .channel_cfg[BCL_BATT_2S][CHANNEL_IN] = { + .base = 4500, + .max = 8400, + .step = 50, + .default_scale_nu = 432918, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_2S][CHANNEL_CURR] = { + .max = 20000, + .default_scale_nu = 540679, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, + .channel_cfg[BCL_BATT_3S][CHANNEL_IN] = { + .base = 6750, + .max = 12600, + .step = 75, + .default_scale_nu = 648790, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_3S][CHANNEL_CURR] = { + .max = 20000, + .default_scale_nu = 540679, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +static const struct bcl_desc smb2370_data = { + .reg_fields = bcl_smb2370_reg_fields, + .num_reg_fields = F_MAX_FIELDS, + .data_field_bits_size = 16, + .thresh_field_bits_size = 8, + .battery_config_field = REG_FIELD(0x2a50, 0, 1), + .channel_cfg[BCL_BATT_2S][CHANNEL_IN] = { + .base = 4500, + .max = 8400, + .step = 50, + .default_scale_nu = 432918, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_2S][CHANNEL_CURR] = { + .max = 20000, + .default_scale_nu = 1441603, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, + .channel_cfg[BCL_BATT_3S][CHANNEL_IN] = { + .base = 6750, + .max = 12600, + .step = 75, + .default_scale_nu = 648790, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_3S][CHANNEL_CURR] = { + .max = 20000, + .default_scale_nu = 1441603, + .thresh_type = {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +/** + * bcl_convert_raw_to_milliunit - Convert raw value to milli unit + * @bcl: BCL device structure + * @raw_val: Raw ADC value from hardware (signed for current, unsigned for voltage) + * @type: type of the channel, in or curr + * @field_width: bits size for data or threshold field + * + * Return: value in milli unit + */ +static int bcl_convert_raw_to_milliunit(const struct bcl_device *bcl, + s32 raw_val, + enum bcl_channel type, + u8 field_width) +{ + const struct bcl_desc *desc = bcl->desc; + u32 def_scale = desc->channel_cfg[bcl->batt_config][type].default_scale_nu; + u32 scaling_factor = (field_width > 8) ? def_scale : (def_scale << field_width); + + return DIV_ROUND_CLOSEST((s64)raw_val * scaling_factor, 1000000); +} + +/** + * bcl_convert_milliunit_to_raw - Convert milli unit to raw value + * @bcl: BCL device structure + * @mval: threshold value in milli unit + * @type: type of the channel, in or curr + * @field_width: bits size for data or threshold field + * + * Return: Raw ADC value for hardware + */ +static unsigned int bcl_convert_milliunit_to_raw(const struct bcl_device *bcl, + int mval, + enum bcl_channel type, + u8 field_width) +{ + const struct bcl_desc *desc = bcl->desc; + u32 def_scale = desc->channel_cfg[bcl->batt_config][type].default_scale_nu; + u32 scaling_factor = (field_width > 8) ? def_scale : (def_scale << field_width); + + return DIV_ROUND_CLOSEST_ULL((u64)mval * 1000000, scaling_factor); +} + +/** + * bcl_convert_milliunit_to_index - Convert milliunit to in or curr index + * @bcl: BCL device structure + * @val: in or curr value in milli unit + * @type: type of the channel, in or curr + * + * Converts a value in milli unit to an index for BCL that use indexed thresholds. + * + * Return: Index value + */ +static unsigned int bcl_convert_milliunit_to_index(const struct bcl_device *bcl, + int val, + enum bcl_channel type) +{ + const struct bcl_desc *desc = bcl->desc; + const struct bcl_channel_cfg *cfg = &desc->channel_cfg[bcl->batt_config][type]; + u64 diff = (u64)val - cfg->base; + + return DIV_ROUND_CLOSEST_ULL(diff, cfg->step); +} + +/** + * bcl_convert_index_to_milliunit - Convert in or curr index to milli unit + * @bcl: BCL device structure + * @val: index value + * @type: type of the channel, in or curr + * + * Converts an index value to milli unit for BCL that use indexed thresholds. + * + * Return: Value in millivolts or milliamps + */ +static unsigned int bcl_convert_index_to_milliunit(const struct bcl_device *bcl, + int val, + enum bcl_channel type) +{ + const struct bcl_desc *desc = bcl->desc; + const struct bcl_channel_cfg *cfg = &desc->channel_cfg[bcl->batt_config][type]; + + return cfg->base + val * cfg->step; +} + +static int bcl_in_thresh_write(struct bcl_device *bcl, long value, enum bcl_limit_alarm lvl) +{ + const struct bcl_desc *desc = bcl->desc; + u32 raw_val; + + int thresh = clamp_val(value, desc->channel_cfg[bcl->batt_config][CHANNEL_IN].base, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].max); + + if (desc->channel_cfg[bcl->batt_config][CHANNEL_IN].thresh_type[lvl] == THRESH_TYPE_ADC) + raw_val = bcl_convert_milliunit_to_raw(bcl, thresh, CHANNEL_IN, + desc->thresh_field_bits_size); + else + raw_val = bcl_convert_milliunit_to_index(bcl, thresh, CHANNEL_IN); + + return regmap_field_write(bcl->fields[F_IN_L0_THR + lvl], raw_val); +} + +static int bcl_curr_thresh_write(struct bcl_device *bcl, long value, enum bcl_limit_alarm lvl) +{ + const struct bcl_desc *desc = bcl->desc; + u32 raw_val; + + int thresh = clamp_val(value, 0, desc->channel_cfg[bcl->batt_config][CHANNEL_CURR].max); + + if (desc->channel_cfg[bcl->batt_config][CHANNEL_CURR].thresh_type[lvl] == THRESH_TYPE_ADC) + raw_val = bcl_convert_milliunit_to_raw(bcl, thresh, CHANNEL_CURR, + desc->thresh_field_bits_size); + else + raw_val = bcl_convert_milliunit_to_index(bcl, thresh, CHANNEL_CURR); + + return regmap_field_write(bcl->fields[F_CURR_H0_THR + lvl], raw_val); +} + +static int bcl_in_thresh_read(struct bcl_device *bcl, enum bcl_limit_alarm lvl, long *out) +{ + int ret, thresh; + u32 raw_val = 0; + const struct bcl_desc *desc = bcl->desc; + + ret = regmap_field_read(bcl->fields[F_IN_L0_THR + lvl], &raw_val); + if (ret) + return ret; + + if (desc->channel_cfg[bcl->batt_config][CHANNEL_IN].thresh_type[lvl] == THRESH_TYPE_ADC) + thresh = bcl_convert_raw_to_milliunit(bcl, raw_val, CHANNEL_IN, + desc->thresh_field_bits_size); + else + thresh = bcl_convert_index_to_milliunit(bcl, raw_val, CHANNEL_IN); + + *out = thresh; + + return 0; +} + +static int bcl_curr_thresh_read(struct bcl_device *bcl, enum bcl_limit_alarm lvl, long *out) +{ + int ret, thresh; + u32 raw_val = 0; + const struct bcl_desc *desc = bcl->desc; + + ret = regmap_field_read(bcl->fields[F_CURR_H0_THR + lvl], &raw_val); + if (ret) + return ret; + + if (desc->channel_cfg[bcl->batt_config][CHANNEL_CURR].thresh_type[lvl] == THRESH_TYPE_ADC) + thresh = bcl_convert_raw_to_milliunit(bcl, raw_val, CHANNEL_CURR, + desc->thresh_field_bits_size); + else + thresh = bcl_convert_index_to_milliunit(bcl, raw_val, CHANNEL_CURR); + + *out = thresh; + + return 0; +} + +static int bcl_curr_input_read(struct bcl_device *bcl, long *out) +{ + int ret; + u32 raw_val = 0, msb = 0; + s32 signed_val; + const struct bcl_desc *desc = bcl->desc; + + /* Return cached value if read too soon after last update */ + if (time_before(jiffies, bcl->last_curr_updated + HZ)) { + *out = bcl->last_curr_input; + return 0; + } + + ret = regmap_field_read(bcl->fields[F_CURR_INPUT], &raw_val); + if (ret) + return ret; + + /* For 16-bit data, read MSB and combine with LSB */ + if (desc->data_field_bits_size == 16) { + ret = regmap_field_read(bcl->fields[F_CURR_INPUT1], &msb); + if (ret) + return ret; + raw_val |= FIELD_PREP(GENMASK(15, 8), msb); + } + + /* + * Current ADC reading is in 2's complement form. + * Sign extend the value based on data field bit size. + */ + signed_val = sign_extend32(raw_val, desc->data_field_bits_size - 1); + + bcl->last_curr_input = + bcl_convert_raw_to_milliunit(bcl, signed_val, CHANNEL_CURR, + desc->data_field_bits_size); + bcl->last_curr_updated = jiffies; + + *out = bcl->last_curr_input; + + return 0; +} + +static int bcl_in_input_read(struct bcl_device *bcl, long *out) +{ + int ret; + u32 raw_val = 0, msb = 0; + const struct bcl_desc *desc = bcl->desc; + + /* Return cached value if read too soon after last update */ + if (time_before(jiffies, bcl->last_in_updated + HZ)) { + *out = bcl->last_in_input; + return 0; + } + + ret = regmap_field_read(bcl->fields[F_IN_INPUT], &raw_val); + if (ret) + return ret; + + /* For 16-bit data, read MSB and combine with LSB */ + if (desc->data_field_bits_size == 16) { + ret = regmap_field_read(bcl->fields[F_IN_INPUT1], &msb); + if (ret) + return ret; + raw_val |= FIELD_PREP(GENMASK(15, 8), msb); + } + + bcl->last_in_input = + bcl_convert_raw_to_milliunit(bcl, raw_val, CHANNEL_IN, + desc->data_field_bits_size); + bcl->last_in_updated = jiffies; + + *out = bcl->last_in_input; + + return 0; +} + +static int bcl_read_alarm_status(struct bcl_device *bcl, + enum bcl_limit_alarm lvl, long *status) +{ + int ret; + u32 raw_val = 0; + + ret = regmap_field_read(bcl->fields[F_LVL0_ALARM + lvl], &raw_val); + if (ret) + return ret; + + *status = raw_val; + + return 0; +} + +static unsigned int bcl_get_version_major(const struct bcl_device *bcl) +{ + u32 raw_val = 0; + + regmap_field_read(bcl->fields[F_V_MAJOR], &raw_val); + + return raw_val; +} + +static unsigned int bcl_get_version_minor(const struct bcl_device *bcl) +{ + u32 raw_val = 0; + + regmap_field_read(bcl->fields[F_V_MINOR], &raw_val); + + return raw_val; +} + +static void bcl_hwmon_notify_event(struct bcl_device *bcl, enum bcl_limit_alarm alarm) +{ + if (bcl->in_attrs) + hwmon_notify_event(bcl->hwmon_dev, hwmon_in, + in_lvl_to_attr_map[alarm], 0); + + if (bcl->curr_attrs) + hwmon_notify_event(bcl->hwmon_dev, hwmon_curr, + curr_lvl_to_attr_map[alarm], 0); +} + +static void bcl_alarm_enable_poll(struct work_struct *work) +{ + struct bcl_alarm_data *alarm = container_of(work, struct bcl_alarm_data, + alarm_poll_work.work); + struct bcl_device *bcl = (struct bcl_device *)alarm->device; + long status; + int ret; + + scoped_guard(mutex, &bcl->lock) + ret = bcl_read_alarm_status(bcl, alarm->type, &status); + + /* If read failed or shutting down, reschedule */ + if (ret || READ_ONCE(alarm->shutting_down)) { + if (!READ_ONCE(alarm->shutting_down)) + schedule_delayed_work(&alarm->alarm_poll_work, + msecs_to_jiffies(BCL_ALARM_POLLING_MS)); + return; + } + + /* Check if alarm cleared and IRQ needs re-enabling */ + scoped_guard(mutex, &alarm->a_lock) { + if (!status && !alarm->irq_enabled) { + alarm->irq_enabled = true; + enable_irq(alarm->irq); + + if (!alarm->irq_wake_enabled && !enable_irq_wake(alarm->irq)) + alarm->irq_wake_enabled = true; + + bcl_hwmon_notify_event(bcl, alarm->type); + return; + } + } + + /* Alarm still active, reschedule polling */ + if (!READ_ONCE(alarm->shutting_down)) + schedule_delayed_work(&alarm->alarm_poll_work, + msecs_to_jiffies(BCL_ALARM_POLLING_MS)); +} + +static irqreturn_t bcl_handle_alarm(int irq, void *data) +{ + struct bcl_alarm_data *alarm = data; + struct bcl_device *bcl = (struct bcl_device *)alarm->device; + long status; + + if (READ_ONCE(alarm->shutting_down)) + return IRQ_HANDLED; + + guard(mutex)(&bcl->lock); + + if (bcl_read_alarm_status(bcl, alarm->type, &status) || !status) + return IRQ_HANDLED; + + bcl_hwmon_notify_event(bcl, alarm->type); + + guard(mutex)(&alarm->a_lock); + if (alarm->shutting_down) + return IRQ_HANDLED; + + if (alarm->irq_enabled) { + alarm->irq_enabled = false; + disable_irq_nosync(alarm->irq); + } + + if (alarm->irq_wake_enabled) { + disable_irq_wake(alarm->irq); + alarm->irq_wake_enabled = false; + } + + schedule_delayed_work(&alarm->alarm_poll_work, + msecs_to_jiffies(BCL_ALARM_POLLING_MS)); + + return IRQ_HANDLED; +} + +static umode_t bcl_hwmon_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_input: + case hwmon_in_label: + case hwmon_in_min_alarm: + case hwmon_in_lcrit_alarm: + return 0444; + case hwmon_in_min: + case hwmon_in_lcrit: + return 0644; + default: + return 0; + } + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_label: + case hwmon_curr_max_alarm: + case hwmon_curr_crit_alarm: + return 0444; + case hwmon_curr_max: + case hwmon_curr_crit: + return 0644; + default: + return 0; + } + default: + return 0; + } +} + +static int bcl_hwmon_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct bcl_device *bcl = dev_get_drvdata(dev); + + guard(mutex)(&bcl->lock); + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_min: + case hwmon_in_lcrit: + return bcl_in_thresh_write(bcl, val, in_attr_to_lvl_map[attr]); + default: + return -EOPNOTSUPP; + } + case hwmon_curr: + switch (attr) { + case hwmon_curr_max: + case hwmon_curr_crit: + return bcl_curr_thresh_write(bcl, val, curr_attr_to_lvl_map[attr]); + default: + return -EOPNOTSUPP; + } + default: + return -EOPNOTSUPP; + } +} + +static int bcl_in_read(struct bcl_device *bcl, u32 attr, long *value) +{ + guard(mutex)(&bcl->lock); + + switch (attr) { + case hwmon_in_input: + return bcl_in_input_read(bcl, value); + case hwmon_in_min: + case hwmon_in_lcrit: + return bcl_in_thresh_read(bcl, in_attr_to_lvl_map[attr], value); + case hwmon_in_min_alarm: + case hwmon_in_lcrit_alarm: + return bcl_read_alarm_status(bcl, in_attr_to_lvl_map[attr], value); + default: + return -EOPNOTSUPP; + } +} + +static int bcl_curr_read(struct bcl_device *bcl, u32 attr, long *value) +{ + guard(mutex)(&bcl->lock); + + switch (attr) { + case hwmon_curr_input: + return bcl_curr_input_read(bcl, value); + case hwmon_curr_max: + case hwmon_curr_crit: + return bcl_curr_thresh_read(bcl, curr_attr_to_lvl_map[attr], value); + case hwmon_curr_max_alarm: + case hwmon_curr_crit_alarm: + return bcl_read_alarm_status(bcl, curr_attr_to_lvl_map[attr], value); + default: + return -EOPNOTSUPP; + } +} + +static int bcl_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *value) +{ + struct bcl_device *bcl = dev_get_drvdata(dev); + + switch (type) { + case hwmon_in: + return bcl_in_read(bcl, attr, value); + case hwmon_curr: + return bcl_curr_read(bcl, attr, value); + default: + return -EOPNOTSUPP; + } +} + +static int bcl_hwmon_read_string(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + if (type == hwmon_in && attr == hwmon_in_label) + *str = "Voltage"; + else if (type == hwmon_curr && attr == hwmon_curr_label) + *str = "Current"; + else + *str = NULL; + + return *str ? 0 : -EOPNOTSUPP; +} + +static const struct hwmon_ops bcl_hwmon_ops = { + .is_visible = bcl_hwmon_is_visible, + .read = bcl_hwmon_read, + .read_string = bcl_hwmon_read_string, + .write = bcl_hwmon_write, +}; + +static int bcl_detect_battery_config(struct bcl_device *bcl) +{ + u32 reg_val = 0; + int ret; + + ret = regmap_field_read(bcl->batt_config_regfield, ®_val); + if (ret) { + dev_err(bcl->dev, "Failed to read battery config register: %d\n", ret); + return ret; + } + + /* + * Map register value to battery configuration. + * As per hardware documentation: + * 0 -> 2S, 1 -> 3S, 2 -> 4S (unsupported) + */ + switch (reg_val) { + case 0: + bcl->batt_config = BCL_BATT_2S; + return 0; + case 1: + bcl->batt_config = BCL_BATT_3S; + return 0; + default: + dev_err(bcl->dev, "Unsupported battery configuration: 0x%x\n", + reg_val); + return -EINVAL; + } +} + +static int bcl_update_scaling_factors(struct bcl_device *bcl) +{ + const struct bcl_desc *desc = bcl->desc; + int ret; + + /* Check if battery detection is supported */ + if (desc->battery_config_field.reg == 0) { + /* No battery detection - use BCL_BATT_1S */ + bcl->batt_config = BCL_BATT_1S; + dev_dbg(bcl->dev, "Using default 1S battery configuration\n"); + return 0; + } + + bcl->batt_config_regfield = devm_regmap_field_alloc(bcl->dev, + bcl->regmap, + desc->battery_config_field); + if (IS_ERR(bcl->batt_config_regfield)) { + dev_err(bcl->dev, "Failed to allocate battery config regmap field\n"); + return PTR_ERR(bcl->batt_config_regfield); + } + + ret = bcl_detect_battery_config(bcl); + if (ret < 0) + return ret; + + dev_dbg(bcl->dev, + "%dS battery: BASE=%u mV,MAX=%u mV,STEP=%u mV,V_SCALE=%u nV, I_SCALE=%u nA\n", + bcl->batt_config + 1, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].base, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].max, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].step, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].default_scale_nu, + desc->channel_cfg[bcl->batt_config][CHANNEL_CURR].default_scale_nu); + + return 0; +} + +static int bcl_build_hwmon_info(struct bcl_device *bcl) +{ + const struct bcl_desc *desc = bcl->desc; + struct hwmon_channel_info *in_info = NULL, *curr_info = NULL; + const struct hwmon_channel_info **info_array; + int num_channels = 0; + u32 val = 0; + bool in_mon_enabled = false; + bool in_input_enabled = false; + bool curr_mon_enabled = false; + int ret; + + /* Check if voltage monitoring is enabled */ + ret = regmap_field_read(bcl->fields[F_IN_MON_EN], &val); + if (ret) + return ret; + in_mon_enabled = !!val; + + /* Check if voltage input reading is enabled */ + if (desc->data_field_bits_size != 0) { + ret = regmap_field_read(bcl->fields[F_IN_INPUT_EN], &val); + if (ret) + return ret; + in_input_enabled = !!val; + } + + /* Check if current monitoring is enabled */ + if (desc->num_reg_fields > F_CURR_H0_THR) { + ret = regmap_field_read(bcl->fields[F_CURR_MON_EN], &val); + if (ret) + return ret; + curr_mon_enabled = !!val; + } + + /* Ensure at least one channel is enabled */ + if (!in_mon_enabled && !curr_mon_enabled) { + dev_err(bcl->dev, "No BCL channels enabled in hardware\n"); + return -ENODEV; + } + + if (in_mon_enabled) { + u32 *in_config; + + bcl->in_attrs = HWMON_I_LABEL | HWMON_I_MIN | HWMON_I_LCRIT | + HWMON_I_MIN_ALARM | HWMON_I_LCRIT_ALARM; + + if (in_input_enabled) + bcl->in_attrs |= HWMON_I_INPUT; + + in_info = devm_kzalloc(bcl->dev, sizeof(*in_info), GFP_KERNEL); + if (!in_info) + return -ENOMEM; + + in_config = devm_kzalloc(bcl->dev, 2 * sizeof(u32), GFP_KERNEL); + if (!in_config) + return -ENOMEM; + + in_config[0] = bcl->in_attrs; + in_info->type = hwmon_in; + in_info->config = in_config; + num_channels++; + } + + if (curr_mon_enabled) { + u32 *curr_config; + + bcl->curr_attrs = HWMON_C_INPUT | HWMON_C_LABEL | HWMON_C_MAX | + HWMON_C_CRIT | HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM; + + curr_info = devm_kzalloc(bcl->dev, sizeof(*curr_info), GFP_KERNEL); + if (!curr_info) + return -ENOMEM; + + curr_config = devm_kzalloc(bcl->dev, 2 * sizeof(u32), GFP_KERNEL); + if (!curr_config) + return -ENOMEM; + + curr_config[0] = bcl->curr_attrs; + curr_info->type = hwmon_curr; + curr_info->config = curr_config; + num_channels++; + } + + /* Allocate info array (num_channels + 1 for NULL terminator) */ + info_array = devm_kcalloc(bcl->dev, num_channels + 1, + sizeof(*info_array), GFP_KERNEL); + if (!info_array) + return -ENOMEM; + + num_channels = 0; + if (in_info) + info_array[num_channels++] = in_info; + if (curr_info) + info_array[num_channels++] = curr_info; + + bcl->hwmon_info = info_array; + + bcl->hwmon_chip_info.ops = &bcl_hwmon_ops; + bcl->hwmon_chip_info.info = bcl->hwmon_info; + + return 0; +} + +static void bcl_alarm_work_cleanup_action(void *data) +{ + struct bcl_alarm_data *alarm = data; + + /* Set shutting_down flag to prevent work from being rescheduled */ + scoped_guard(mutex, &alarm->a_lock) + WRITE_ONCE(alarm->shutting_down, true); + + cancel_delayed_work_sync(&alarm->alarm_poll_work); +} + +static void bcl_alarm_wake_cleanup_action(void *data) +{ + struct bcl_alarm_data *alarm = data; + + guard(mutex)(&alarm->a_lock); + if (alarm->irq_wake_enabled) { + disable_irq_wake(alarm->irq); + alarm->irq_wake_enabled = false; + } +} + +static int bcl_alarm_irq_init(struct platform_device *pdev, + struct bcl_device *bcl) +{ + int ret, irq_num, i; + struct bcl_alarm_data *alarm; + + for (i = 0; i < ARRAY_SIZE(bcl->bcl_alarms); i++) { + alarm = &bcl->bcl_alarms[i]; + alarm->type = i; + alarm->device = bcl; + ret = devm_mutex_init(bcl->dev, &alarm->a_lock); + if (ret) + return ret; + + /* Initialize work before IRQ request */ + INIT_DELAYED_WORK(&alarm->alarm_poll_work, bcl_alarm_enable_poll); + + irq_num = platform_get_irq_byname(pdev, bcl_int_names[i]); + if (irq_num < 0) + return irq_num; + + alarm->irq = irq_num; + alarm->irq_enabled = true; + + ret = devm_request_threaded_irq(&pdev->dev, irq_num, NULL, + bcl_handle_alarm, IRQF_ONESHOT, + bcl_int_names[i], alarm); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&pdev->dev, bcl_alarm_work_cleanup_action, + alarm); + if (ret) + return ret; + + if (!enable_irq_wake(irq_num)) + alarm->irq_wake_enabled = true; + + ret = devm_add_action_or_reset(&pdev->dev, bcl_alarm_wake_cleanup_action, + alarm); + if (ret) + return ret; + } + + return 0; +} + +static int bcl_regmap_field_init(struct device *dev, struct bcl_device *bcl, + const struct bcl_desc *data) +{ + int i; + + /* + * Note: We use a mutable local copy of struct reg_field (not const) + * because we need to modify the .reg field to add the BCL base offset. + */ + for (i = 0; i < data->num_reg_fields; i++) { + struct reg_field field = data->reg_fields[i]; + + /* Skip uninitialized fields */ + if (field.reg == 0 && field.lsb == 0 && field.msb == 0) + continue; + + field.reg += bcl->base; + + bcl->fields[i] = devm_regmap_field_alloc(dev, bcl->regmap, field); + if (IS_ERR(bcl->fields[i])) + return PTR_ERR(bcl->fields[i]); + } + + return 0; +} + +static int bcl_probe(struct platform_device *pdev) +{ + struct bcl_device *bcl; + int ret; + u32 reg; + + bcl = devm_kzalloc(&pdev->dev, sizeof(*bcl), GFP_KERNEL); + if (!bcl) + return -ENOMEM; + + bcl->dev = &pdev->dev; + bcl->desc = device_get_match_data(&pdev->dev); + if (!bcl->desc) + return dev_err_probe(&pdev->dev, -EINVAL, "Failed to get device match data\n"); + + ret = devm_mutex_init(bcl->dev, &bcl->lock); + if (ret) + return ret; + + bcl->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!bcl->regmap) + return dev_err_probe(&pdev->dev, -EINVAL, "Couldn't get parent's regmap\n"); + + ret = device_property_read_u32(&pdev->dev, "reg", ®); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to read 'reg' property\n"); + + bcl->base = reg; + + ret = bcl_regmap_field_init(bcl->dev, bcl, bcl->desc); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Unable to allocate regmap fields\n"); + + ret = regmap_field_read(bcl->fields[F_CTL_EN], ®); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to read BCL enable status\n"); + + if (!reg) + return dev_err_probe(&pdev->dev, -ENODEV, "BCL is not enabled by bootloader\n"); + + ret = bcl_update_scaling_factors(bcl); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to update scaling factors\n"); + + ret = bcl_build_hwmon_info(bcl); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to build hwmon info\n"); + + dev_set_drvdata(&pdev->dev, bcl); + + bcl->hwmon_name = devm_hwmon_sanitize_name(&pdev->dev, + dev_name(bcl->dev)); + if (IS_ERR(bcl->hwmon_name)) + return PTR_ERR(bcl->hwmon_name); + + bcl->hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, + bcl->hwmon_name, + bcl, + &bcl->hwmon_chip_info, + NULL); + if (IS_ERR(bcl->hwmon_dev)) + return dev_err_probe(&pdev->dev, PTR_ERR(bcl->hwmon_dev), + "Failed to register hwmon device\n"); + + ret = bcl_alarm_irq_init(pdev, bcl); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to initialize alarm IRQs\n"); + + dev_dbg(&pdev->dev, "BCL hwmon device with version: %u.%u registered\n", + bcl_get_version_major(bcl), bcl_get_version_minor(bcl)); + + return 0; +} + +static const struct of_device_id bcl_match[] = { + { + .compatible = "qcom,pm7250b-bcl", + .data = &pm7250b_data, + }, { + .compatible = "qcom,pm8350c-bcl", + .data = &pm8350c_data, + }, { + .compatible = "qcom,pm8550-bcl", + .data = &pm8550_data, + }, { + .compatible = "qcom,pmh0101-bcl", + .data = &pmh0101_data, + }, { + .compatible = "qcom,pmih0108-bcl", + .data = &pmih0108_data, + }, { + .compatible = "qcom,smb2360-bcl", + .data = &smb2360_data, + }, { + .compatible = "qcom,smb2370-bcl", + .data = &smb2370_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, bcl_match); + +static struct platform_driver bcl_driver = { + .probe = bcl_probe, + .driver = { + .name = "qcom-bcl-hwmon", + .of_match_table = bcl_match, + }, +}; + +module_platform_driver(bcl_driver); + +MODULE_DESCRIPTION("Qualcomm SPMI BCL HWMON driver"); +MODULE_LICENSE("GPL"); From 4c998f2b680ba6f39d496c1ff43d47145b1471d7 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 22 Jul 2026 00:00:09 +0530 Subject: [PATCH 1322/1330] FROMLIST: arm64: dts: qcom: hamoa-pmic: Enable BCL sensor node Add Battery Current Limiting (BCL) hardware monitor node for hamoa-pmic. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-4-febe2805e17b@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi index 2e746ede850f8..d7a0b51e8816a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi @@ -765,6 +765,15 @@ status = "disabled"; + sensor@4700 { + compatible = "qcom,smb2360-bcl"; + reg = <0x4700>; + interrupts = <0x7 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x7 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "max-min", + "critical"; + }; + smb2360_0_eusb2_repeater: phy@fd00 { compatible = "qcom,smb2360-eusb2-repeater"; reg = <0xfd00>; From 5f1505783d1d13de02aa395b21fecd0261abd258 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 22 Jul 2026 00:00:12 +0530 Subject: [PATCH 1323/1330] FROMLIST: arm64: dts: qcom: pm8550: Enable BCL sensor node Add Battery Current Limiting (BCL) hardware monitor node for pm8550 PMIC. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-7-febe2805e17b@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/pm8550.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi index 896bcacb64902..fde76da37bacb 100644 --- a/arch/arm64/boot/dts/qcom/pm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -45,6 +45,15 @@ #thermal-sensor-cells = <0>; }; + sensor@4700 { + compatible = "qcom,pm8550-bcl"; + reg = <0x4700>; + interrupts = <0x1 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x1 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "max-min", + "critical"; + }; + pm8550_gpios: gpio@8800 { compatible = "qcom,pm8550-gpio", "qcom,spmi-gpio"; reg = <0x8800>; From e6adc6ff80d65320518c9bdad73fdbe3b86b9cce Mon Sep 17 00:00:00 2001 From: Dipa Ramesh Mantre Date: Tue, 11 Aug 2026 15:32:31 +0530 Subject: [PATCH 1324/1330] QCLINUX: defconfig: Enable Qualcomm BCL driver Enable Qualcomm BCL driver config. Signed-off-by: Dipa Ramesh Mantre --- arch/arm64/configs/qcom.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 3e7150aeaed7e..6a1502a077cdc 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -61,6 +61,7 @@ CONFIG_STM_SOURCE_FTRACE=m CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_SENSORS_AMC6821=y CONFIG_SENSORS_EMC2305=y +CONFIG_SENSORS_QCOM_SPMI_BCL=y CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y From 055c5750b9dca7cfc4abc75898c6abe0569a2ad3 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Apr 2026 08:11:11 +0000 Subject: [PATCH 1325/1330] UPSTREAM: ASoC: dt-bindings: qcom: add LPASS LPI MI2S dai ids Add new dai ids entries for LPASS LPI MI2S and SENARY MI2S audio lines. Co-developed-by: Mohammad Rafi Shaik Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260402081118.348071-7-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown --- .../bindings/sound/qcom,q6dsp-lpass-ports.yaml | 5 ++++- include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 12 ++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml index 08c618e7e4281..2b27d6c8f58f1 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -126,13 +126,16 @@ patternProperties: reg: contains: # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and - # QUINARY_MI2S_RX - QUINARY_MI2S_TX + # QUINARY_MI2S_RX - QUINARY_MI2S_TX and + # LPI_MI2S_RX_0 - SENARY_MI2S_TX items: oneOf: - minimum: 16 maximum: 23 - minimum: 127 maximum: 128 + - minimum: 137 + maximum: 148 then: required: - qcom,sd-lines diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h index 6d1ce7f5da51c..45850f2d43425 100644 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -140,6 +140,18 @@ #define DISPLAY_PORT_RX_6 134 #define DISPLAY_PORT_RX_7 135 #define USB_RX 136 +#define LPI_MI2S_RX_0 137 +#define LPI_MI2S_TX_0 138 +#define LPI_MI2S_RX_1 139 +#define LPI_MI2S_TX_1 140 +#define LPI_MI2S_RX_2 141 +#define LPI_MI2S_TX_2 142 +#define LPI_MI2S_RX_3 143 +#define LPI_MI2S_TX_3 144 +#define LPI_MI2S_RX_4 145 +#define LPI_MI2S_TX_4 146 +#define SENARY_MI2S_RX 147 +#define SENARY_MI2S_TX 148 #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 From a2eff5467588fb96d2acdaa8efad1c178a009c2a Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Thu, 2 Apr 2026 08:11:14 +0000 Subject: [PATCH 1326/1330] UPSTREAM: ASoC: qcom: q6dsp: Add Senary MI2S audio interface support Introduces support for the Senary MI2S audio interface in the Qualcomm q6dsp. Add new AFE port IDs for Senary MI2S RX and TX and include the necessary mappings in the port configuration to allow audio routing over the Senary MI2S interface. Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Srinivas Kandagatla Tested-by: Val Packett # sm7325-motorola-dubai Link: https://patch.msgid.link/20260402081118.348071-10-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown --- sound/soc/qcom/qdsp6/q6afe-dai.c | 6 +++++ sound/soc/qcom/qdsp6/q6afe.c | 8 +++++++ sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 29 ++++++++++++++++++++++++ 3 files changed, 43 insertions(+) diff --git a/sound/soc/qcom/qdsp6/q6afe-dai.c b/sound/soc/qcom/qdsp6/q6afe-dai.c index 0f47aadaabe17..a0d21034a6264 100644 --- a/sound/soc/qcom/qdsp6/q6afe-dai.c +++ b/sound/soc/qcom/qdsp6/q6afe-dai.c @@ -409,6 +409,7 @@ static int q6afe_dai_prepare(struct snd_pcm_substream *substream, q6afe_slim_port_prepare(dai_data->port[dai->id], &dai_data->port_config[dai->id].slim); break; + case SENARY_MI2S_RX ... SENARY_MI2S_TX: case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: rc = q6afe_i2s_port_prepare(dai_data->port[dai->id], @@ -540,6 +541,7 @@ static const struct snd_soc_dapm_route q6afe_dapm_routes[] = { {"Tertiary MI2S Playback", NULL, "TERT_MI2S_RX"}, {"Quaternary MI2S Playback", NULL, "QUAT_MI2S_RX"}, {"Quinary MI2S Playback", NULL, "QUIN_MI2S_RX"}, + {"Senary MI2S Playback", NULL, "SEN_MI2S_RX"}, {"Primary TDM0 Playback", NULL, "PRIMARY_TDM_RX_0"}, {"Primary TDM1 Playback", NULL, "PRIMARY_TDM_RX_1"}, @@ -636,6 +638,7 @@ static const struct snd_soc_dapm_route q6afe_dapm_routes[] = { {"SEC_MI2S_TX", NULL, "Secondary MI2S Capture"}, {"QUAT_MI2S_TX", NULL, "Quaternary MI2S Capture"}, {"QUIN_MI2S_TX", NULL, "Quinary MI2S Capture"}, + {"SEN_MI2S_TX", NULL, "Senary MI2S Capture"}, {"WSA_CODEC_DMA_RX_0 Playback", NULL, "WSA_CODEC_DMA_RX_0"}, {"WSA_CODEC_DMA_TX_0", NULL, "WSA_CODEC_DMA_TX_0 Capture"}, @@ -770,6 +773,8 @@ static const struct snd_soc_dapm_widget q6afe_dai_widgets[] = { SND_SOC_DAPM_AIF_OUT("SLIMBUS_4_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_5_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_6_TX", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_MI2S_RX", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_MI2S_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_MI2S_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_MI2S_TX", NULL, @@ -1037,6 +1042,7 @@ static void of_q6afe_parse_dai_data(struct device *dev, switch (id) { /* MI2S specific properties */ + case SENARY_MI2S_RX ... SENARY_MI2S_TX: case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: priv = &data->priv[id]; diff --git a/sound/soc/qcom/qdsp6/q6afe.c b/sound/soc/qcom/qdsp6/q6afe.c index 43d877322baee..40237267fda05 100644 --- a/sound/soc/qcom/qdsp6/q6afe.c +++ b/sound/soc/qcom/qdsp6/q6afe.c @@ -130,6 +130,8 @@ #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 #define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 #define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 +#define AFE_PORT_ID_SENARY_MI2S_RX 0x1018 +#define AFE_PORT_ID_SENARY_MI2S_TX 0x1019 /* Start of the range of port IDs for TDM devices. */ #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 @@ -718,6 +720,10 @@ static struct afe_port_map port_maps[AFE_PORT_MAX] = { QUINARY_MI2S_RX, 1, 1}, [QUINARY_MI2S_TX] = { AFE_PORT_ID_QUINARY_MI2S_TX, QUINARY_MI2S_TX, 0, 1}, + [SENARY_MI2S_RX] = { AFE_PORT_ID_SENARY_MI2S_RX, + SENARY_MI2S_RX, 1, 1}, + [SENARY_MI2S_TX] = { AFE_PORT_ID_SENARY_MI2S_TX, + SENARY_MI2S_TX, 0, 1}, [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX, PRIMARY_TDM_RX_0, 1, 1}, [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX, @@ -1777,6 +1783,8 @@ struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) case AFE_PORT_ID_QUATERNARY_MI2S_TX: case AFE_PORT_ID_QUINARY_MI2S_RX: case AFE_PORT_ID_QUINARY_MI2S_TX: + case AFE_PORT_ID_SENARY_MI2S_RX: + case AFE_PORT_ID_SENARY_MI2S_TX: cfg_type = AFE_PARAM_ID_I2S_CONFIG; break; case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c index 8542e620ee02d..3235c814c88c6 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -479,6 +479,34 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { }, .id = QUINARY_MI2S_TX, .name = "QUIN_MI2S_TX", + }, { + .playback = { + .stream_name = "Senary MI2S Playback", + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + .id = SENARY_MI2S_RX, + .name = "SEN_MI2S_RX", + }, { + .capture = { + .stream_name = "Senary MI2S Capture", + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + .id = SENARY_MI2S_TX, + .name = "SEN_MI2S_TX", }, Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0), Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1), @@ -630,6 +658,7 @@ struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev, case SLIMBUS_0_RX ... SLIMBUS_6_TX: q6dsp_audio_fe_dais[i].ops = cfg->q6slim_ops; break; + case SENARY_MI2S_RX ... SENARY_MI2S_TX: case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: q6dsp_audio_fe_dais[i].ops = cfg->q6i2s_ops; From 7bab1944016e293921f79c42f36f2e8876a36308 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 12 Aug 2026 14:11:49 +0800 Subject: [PATCH 1327/1330] config: enable stm_proto_ost Enable CONFIG_STM_PROTO_OST (built as a module) for the arm64 flavour to support the MIPI SyS-T / OST (Open System Trace) protocol driver for the CoreSight STM. The driver implements the OST protocol encoder on top of the STM stimulus ports, framing software trace messages with OST headers before they are emitted onto the CoreSight trace bus. This lets trace tooling identify and demultiplex the software trace streams captured at a CoreSight sink. Signed-off-by: Jie Gan --- debian.qcom/config/annotations | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian.qcom/config/annotations b/debian.qcom/config/annotations index da28b613b802b..b035d35fea147 100644 --- a/debian.qcom/config/annotations +++ b/debian.qcom/config/annotations @@ -2390,7 +2390,7 @@ CONFIG_STM32_RPROC policy<{'arm64': '-'}> CONFIG_STM32_TIMER_CNT policy<{'arm64': '-'}> CONFIG_STM32_WATCHDOG policy<{'arm64': '-'}> CONFIG_STMP_DEVICE policy<{'arm64': '-'}> -CONFIG_STM_PROTO_OST policy<{'arm64': 'n'}> +CONFIG_STM_PROTO_OST policy<{'arm64': 'm'}> CONFIG_STUB_CLK_HI3660 policy<{'arm64': '-'}> CONFIG_STUB_CLK_HI6220 policy<{'arm64': '-'}> CONFIG_ST_THERMAL policy<{'arm64': '-'}> From cd05e9f3052dda0735b22ecbd77e65ea2bfa6df2 Mon Sep 17 00:00:00 2001 From: Bjordis Collaku Date: Thu, 20 Aug 2026 15:08:18 -0700 Subject: [PATCH 1328/1330] test: exercise canonical premerge distro validation - Add a temporary documentation-only change targeting resolute-qcom-devel. - Trigger the Canonical kernel premerge build and S3 package publication. - Exercise pinned server and desktop image generation through qcom-distro-images. - Validate artifact receipts, the completion marker, and the final PR Check Run. Signed-off-by: Bjordis Collaku --- docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md diff --git a/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md b/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md new file mode 100644 index 0000000000000..9717ea6c559db --- /dev/null +++ b/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md @@ -0,0 +1,13 @@ +# Canonical Premerge Distro Validation Smoke Test + +This temporary documentation-only change validates the complete Canonical +premerge pipeline for pull requests targeting `resolute-qcom-devel`. + +The expected flow is: + +1. Build and upload the Canonical kernel Debian packages. +2. Build the pinned Resolute IoT server and desktop images. +3. Publish both image tarballs and validation receipts beside the kernel packages. +4. Validate the completion marker and report the result on this pull request. + +This change is for pipeline validation only and must not be merged. From 91f03d745c7d95bc437c79ea77f320dbd44bdf5c Mon Sep 17 00:00:00 2001 From: Keerthi Gowda Date: Fri, 21 Aug 2026 12:47:27 -0700 Subject: [PATCH 1329/1330] Update CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md Signed-off-by: Keerthi Gowda --- docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md b/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md index 9717ea6c559db..7a5853fdea5ec 100644 --- a/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md +++ b/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md @@ -10,4 +10,4 @@ The expected flow is: 3. Publish both image tarballs and validation receipts beside the kernel packages. 4. Validate the completion marker and report the result on this pull request. -This change is for pipeline validation only and must not be merged. +This change is for pipeline validation only and must not be merged - try 2 From a5b0fe97c0dc8b6f99bde2ac1b213bfe7c54411f Mon Sep 17 00:00:00 2001 From: Bjordis Collaku Date: Fri, 21 Aug 2026 15:12:31 -0700 Subject: [PATCH 1330/1330] Update CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md Signed-off-by: Bjordis Collaku --- docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md b/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md index 7a5853fdea5ec..9717ea6c559db 100644 --- a/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md +++ b/docs/CANONICAL_PREMERGE_DISTRO_SMOKE_TEST.md @@ -10,4 +10,4 @@ The expected flow is: 3. Publish both image tarballs and validation receipts beside the kernel packages. 4. Validate the completion marker and report the result on this pull request. -This change is for pipeline validation only and must not be merged - try 2 +This change is for pipeline validation only and must not be merged.