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feat(bsp): Define RPi5 memory map and feature flags
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4 files changed

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19_kernel_heap/kernel/Cargo.toml

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[package]
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name = "mingo"
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version = "0.19.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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authors = ["Andre Richter <andre.o.richter@gmail.com>", "Devansh Lodha <devanshlodha12@gmail.com>"]
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edition = "2021"
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[features]
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default = []
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debug_prints = []
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bsp_rpi3 = ["tock-registers"]
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bsp_rpi4 = ["tock-registers"]
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bsp_rpi5 = ["tock-registers"]
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test_build = ["qemu-exit"]
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##--------------------------------------------------------------------------------------------------

19_kernel_heap/kernel/src/bsp.rs

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// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2023 Andre Richter <andre.o.richter@gmail.com>
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// Copyright (c) 2026 Devansh Lodha <devanshlodha12@gmail.com>
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//! Conditional reexporting of Board Support Packages.
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mod device_driver;
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#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
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#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4", feature = "bsp_rpi5"))]
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mod raspberrypi;
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#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
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#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4", feature = "bsp_rpi5"))]
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pub use raspberrypi::*;

19_kernel_heap/kernel/src/bsp/raspberrypi.rs

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// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2023 Andre Richter <andre.o.richter@gmail.com>
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// Copyright (c) 2026 Devansh Lodha <devanshlodha12@gmail.com>
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//! Top-level BSP file for the Raspberry Pi 3 and 4.
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@@ -24,4 +25,9 @@ pub fn board_name() -> &'static str {
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{
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"Raspberry Pi 4"
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}
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#[cfg(feature = "bsp_rpi5")]
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{
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"Raspberry Pi 5"
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}
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}

19_kernel_heap/kernel/src/bsp/raspberrypi/memory.rs

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// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2023 Andre Richter <andre.o.richter@gmail.com>
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// Copyright (c) 2026 Devansh Lodha <devanshlodha12@gmail.com>
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//! BSP Memory Management.
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//!
@@ -147,6 +148,45 @@ pub(super) mod map {
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pub const END: Address<Physical> = Address::new(0xFF85_0000);
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}
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/// Physical devices.
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#[cfg(feature = "bsp_rpi5")]
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pub mod mmio {
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use super::*;
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// GICv2 on BCM2712 (Northbridge)
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pub const GICD_START: Address<Physical> = Address::new(0x10_7FFF_9000);
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pub const GICD_SIZE: usize = 0x1000;
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pub const GICC_START: Address<Physical> = Address::new(0x10_7FFF_A000);
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pub const GICC_SIZE: usize = 0x1000;
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// MIP (Machine Interrupt Peripheral)
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pub const MIP_START: Address<Physical> = Address::new(0x10_0013_0000);
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pub const MIP_SIZE: usize = 0x1000;
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// PCIe Root Complex
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pub const PCIE_RC_START: Address<Physical> = Address::new(0x10_0012_0000);
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pub const PCIE_RC_SIZE: usize = 0x1000;
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// RP1 Southbridge Config Space (ECAM)
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// 0x1F_0010_0000 -> 0x1F_0050_0000 (4MB) covers Config Space + MSI-X Table
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pub const RP1_CFG_START: Address<Physical> = Address::new(0x1F_0010_0000);
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pub const RP1_CFG_SIZE: usize = 0x40_0000;
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// RP1 Peripherals
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// UART is at offset 0x30000 in the RP1 peripheral bar
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pub const PL011_UART_START: Address<Physical> = Address::new(0x1F_0003_0000);
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pub const PL011_UART_SIZE: usize = 0x1000;
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pub const GPIO_START: Address<Physical> = Address::new(0x1F_000D_0000);
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pub const GPIO_SIZE: usize = 0x1000;
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pub const PADS_START: Address<Physical> = Address::new(0x1F_000F_0000);
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pub const PADS_SIZE: usize = 0x1000;
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// Used by Translation Table Tool
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pub const END: Address<Physical> = Address::new(0x20_0000_0000);
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}
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pub const END: Address<Physical> = mmio::END;
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}
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