From ac18b5c13c60e8dc0ddab87b80a50c89218167ec Mon Sep 17 00:00:00 2001 From: TechnoPorg Date: Fri, 11 Sep 2026 08:12:26 -0400 Subject: [PATCH 1/2] RISC-V: add note about target features vs. misa extensions --- src/attributes/codegen.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/attributes/codegen.md b/src/attributes/codegen.md index b1a79f3edc..2478a23d30 100644 --- a/src/attributes/codegen.md +++ b/src/attributes/codegen.md @@ -563,6 +563,13 @@ specification. Many specifications are described in the [RISC-V ISA Manual], [version 20250508]: https://github.com/riscv/riscv-isa-manual/tree/20250508 [RISC-V GitHub Account]: https://github.com/riscv +> [!NOTE] +> Some RISC-V standard extensions can be enabled (1) or disabled (0) via their corresponding bits in the [Machine ISA][rv-machine] (`misa`) register. +> For example, the [A][rv-a] and [M][rv-m] bits being cleared means atomic instructions and integer multiplication/division instructions are unimplemented. +> +> Rust code compiled with a RISC-V target feature of the same name as an extension assumes the extension will always be available. +> It is undefined behaviour to execute it in an environment where the extension is disabled (bit is 0 in `misa`). + Feature | Implicitly Enables | Description ------------|---------------------|------------------- `a` | `zaamo`, `zalrsc` | [A][rv-a] --- Atomic instructions @@ -621,6 +628,7 @@ Feature | Implicitly Enables | Description [rv-b]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc [rv-c]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/c-st-ext.adoc [rv-m]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/m-st-ext.adoc +[rv-machine]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/machine.adoc#machine-isa-misa-register [rv-za64rs]: https://github.com/riscv/riscv-profiles/blob/rva23-rvb23-ratified/src/rva23-profile.adoc [rv-za128rs]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc [rv-zaamo]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/a-st-ext.adoc From dfb7886b343243a615f8a401f31439b218efd9da Mon Sep 17 00:00:00 2001 From: TechnoPorg Date: Tue, 15 Sep 2026 18:30:37 -0400 Subject: [PATCH 2/2] Make misa extension rule normative --- src/attributes/codegen.md | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/attributes/codegen.md b/src/attributes/codegen.md index 2478a23d30..4a80d0507d 100644 --- a/src/attributes/codegen.md +++ b/src/attributes/codegen.md @@ -563,13 +563,6 @@ specification. Many specifications are described in the [RISC-V ISA Manual], [version 20250508]: https://github.com/riscv/riscv-isa-manual/tree/20250508 [RISC-V GitHub Account]: https://github.com/riscv -> [!NOTE] -> Some RISC-V standard extensions can be enabled (1) or disabled (0) via their corresponding bits in the [Machine ISA][rv-machine] (`misa`) register. -> For example, the [A][rv-a] and [M][rv-m] bits being cleared means atomic instructions and integer multiplication/division instructions are unimplemented. -> -> Rust code compiled with a RISC-V target feature of the same name as an extension assumes the extension will always be available. -> It is undefined behaviour to execute it in an environment where the extension is disabled (bit is 0 in `misa`). - Feature | Implicitly Enables | Description ------------|---------------------|------------------- `a` | `zaamo`, `zalrsc` | [A][rv-a] --- Atomic instructions @@ -622,13 +615,24 @@ Feature | Implicitly Enables | Description `zkt` | | [Zkt][rv-zkt] --- Data Independent Execution Latency Subset `ztso` | | [Ztso][rv-ztso] --- Total Store Ordering + +r[attributes.codegen.target_feature.riscv.misa] +Some targets implement the [Machine ISA] (`misa`) register. Whether a single-letter extension (`A`, `B`, ...) is present can be queried from the corresponding bit of this register. +The RISC-V specification allows implementations to have a writable `misa` and change the set of supported extensions at runtime. + +Rust code compiled with any target feature, including single-letter target features, requires the feature to be available during execution. +It is [undefined behaviour][ub-target-feature] to violate this requirement. + + +[Machine ISA]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/machine.adoc#machine-isa-misa-register +[ub-target-feature]: undefined.target-feature + [rv-a]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/a-st-ext.adoc [rv-b]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc [rv-c]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/c-st-ext.adoc [rv-m]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/m-st-ext.adoc -[rv-machine]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/machine.adoc#machine-isa-misa-register [rv-za64rs]: https://github.com/riscv/riscv-profiles/blob/rva23-rvb23-ratified/src/rva23-profile.adoc [rv-za128rs]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc [rv-zaamo]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/a-st-ext.adoc