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feat(fpga_diff): support JTAG flash writes #134

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6 changes: 5 additions & 1 deletion fpga_diff/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ PRJ_NAME = fpga_$(CPU)$(if $(strip $(SUFFIX)),-$(strip $(SUFFIX)),)
PRJ_DIR ?= $(ENV_SCRIPTS_HOME)/$(PRJ_NAME)
PRJ ?= $(PRJ_DIR)/$(PRJ_NAME).xpr

.PHONY: bitstream vivado dump_ila
.PHONY: bitstream vivado dump_ila write_jtag_flash

# Get Vivado version
VIVADO_VERSION := $(shell vivado -version 2>/dev/null | head -1 | grep -o '[0-9]\{4\}\.[0-9]' || echo "unknown")
Expand Down Expand Up @@ -73,6 +73,10 @@ halt_soc:
write_jtag_ddr:
vivado -mode tcl -source tools/jtag_write_ddr.tcl -tclargs $(WORKLOAD) $(AXI_WIDTH)

# Write a raw binary image to the BRAM-backed flash via the flash-only JTAG AXI
write_jtag_flash:
vivado -mode tcl -source tools/jtag_write_flash.tcl -tclargs $(WORKLOAD)

# Reset CPU on FPGA
reset_cpu:
vivado -mode tcl -source tools/reset_cpu.tcl -tclargs $(FPGA_BIT_HOME)/fpga_top_debug.ltx
Expand Down
51 changes: 26 additions & 25 deletions fpga_diff/src/rtl/common/core_def_xdma.sv
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Expand Up @@ -1051,32 +1051,33 @@ wire [1 : 0] rom_axi_rresp ;

`ifdef XS_QSPI2ROM
blk_mem_gen_0 u_rom (
.rsta_busy (rsta_busy), // output wire rsta_busy
.rstb_busy (rstb_busy), // output wire rstb_busy
.s_aclk (sys_clk_i), // input wire s_aclk
.s_aresetn (axi_bclk_sync_rstn ), // input wire s_aresetn
.s_axi_awaddr (rom_axi_awaddr ), // input wire [31 : 0] s_axi_awaddr
.s_axi_awlen (rom_axi_awlen ), // input wire [7 : 0] s_axi_awlen
.s_axi_awvalid (rom_axi_awvalid ), // input wire s_axi_awvalid
.s_axi_awready (rom_axi_awready ), // output wire s_axi_awready
.s_axi_wdata (rom_axi_wdata ), // input wire [31 : 0] s_axi_wdata
.s_axi_wstrb (rom_axi_wstrb ), // input wire [3 : 0] s_axi_wstrb
.s_axi_wlast (rom_axi_wlast ), // input wire s_axi_wlast
.s_axi_wvalid (rom_axi_wvalid ), // input wire s_axi_wvalid
.s_axi_wready (rom_axi_wready ), // output wire s_axi_wready
.s_axi_bresp (rom_axi_bresp ), // output wire [1 : 0] s_axi_bresp
.s_axi_bvalid (rom_axi_bvalid ), // output wire s_axi_bvalid
.s_axi_bready (rom_axi_bready ), // input wire s_axi_bready
.s_axi_araddr (rom_axi_araddr ), // input wire [31 : 0] s_axi_araddr
.s_axi_arlen (rom_axi_arlen ), // input wire [7 : 0] s_axi_arlen
.s_axi_arvalid (rom_axi_arvalid ), // input wire s_axi_arvalid
.s_axi_arready (rom_axi_arready ), // output wire s_axi_arready
.s_axi_rdata (rom_axi_rdata ), // output wire [31 : 0] s_axi_rdata
.s_axi_rresp (rom_axi_rresp ), // output wire [1 : 0] s_axi_rresp
.s_axi_rlast (rom_axi_rlast ), // output wire s_axi_rlast
.s_axi_rvalid (rom_axi_rvalid ), // output wire s_axi_rvalid
.s_axi_rready (rom_axi_rready ) // input wire s_axi_rready
.rsta_busy (rsta_busy ),
.rstb_busy (rstb_busy ),
.s_aclk (sys_clk_i ),
.s_aresetn (axi_bclk_sync_rstn ),
.s_axi_awaddr (rom_axi_awaddr ),
.s_axi_awlen (rom_axi_awlen ),
.s_axi_awvalid (rom_axi_awvalid ),
.s_axi_awready (rom_axi_awready ),
.s_axi_wdata (rom_axi_wdata ),
.s_axi_wstrb (rom_axi_wstrb ),
.s_axi_wlast (rom_axi_wlast ),
.s_axi_wvalid (rom_axi_wvalid ),
.s_axi_wready (rom_axi_wready ),
.s_axi_bresp (rom_axi_bresp ),
.s_axi_bvalid (rom_axi_bvalid ),
.s_axi_bready (rom_axi_bready ),
.s_axi_araddr (rom_axi_araddr ),
.s_axi_arlen (rom_axi_arlen ),
.s_axi_arvalid (rom_axi_arvalid ),
.s_axi_arready (rom_axi_arready ),
.s_axi_rdata (rom_axi_rdata ),
.s_axi_rresp (rom_axi_rresp ),
.s_axi_rlast (rom_axi_rlast ),
.s_axi_rvalid (rom_axi_rvalid ),
.s_axi_rready (rom_axi_rready )
);

`endif

`ifndef XS_XDMA
Expand Down
26 changes: 21 additions & 5 deletions fpga_diff/src/tcl/common/AXI_bridge.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -125,6 +125,7 @@ if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_apb_bridge:3.0\
xilinx.com:ip:axi_uart16550:2.0\
xilinx.com:ip:jtag_axi:1.2\
xilinx.com:ip:xlconstant:1.1\
"

Expand Down Expand Up @@ -230,7 +231,7 @@ proc create_root_design { parentCell } {
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {25000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
Expand All @@ -239,9 +240,9 @@ proc create_root_design { parentCell } {
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
] $rom_axi


# Create ports
set ACLK [ create_bd_port -dir I -type clk -freq_hz 25000000 ACLK ]
set_property -dict [ list \
Expand All @@ -265,11 +266,23 @@ proc create_root_design { parentCell } {
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {3} \
CONFIG.NUM_SI {2} \
] $axi_interconnect_0

# Create instance: axi_uart16550_0, and set properties
set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ]

# Create instance: jtag_axi_flash, and set properties
set jtag_axi_flash [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_flash ]
set_property -dict [ list \
CONFIG.M_AXI_ADDR_WIDTH {32} \
CONFIG.M_AXI_DATA_WIDTH {32} \
CONFIG.M_AXI_ID_WIDTH {1} \
CONFIG.M_HAS_BURST {1} \
CONFIG.RD_TXN_QUEUE_LENGTH {8} \
CONFIG.WR_TXN_QUEUE_LENGTH {8} \
] $jtag_axi_flash

# Create instance: xlconstant_0, and set properties
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
set_property -dict [ list \
Expand All @@ -284,11 +297,12 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins axi_uart16550_0/S_AXI]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets axi_interconnect_0_M01_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports rom_axi] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
connect_bd_intf_net -intf_net jtag_axi_flash_M_AXI [get_bd_intf_pins axi_interconnect_0/S01_AXI] [get_bd_intf_pins jtag_axi_flash/M_AXI]
connect_bd_intf_net -intf_net axi_uart16550_0_UART [get_bd_intf_ports UART_0] [get_bd_intf_pins axi_uart16550_0/UART]

# Create port connections
connect_bd_net -net ACLK_0_1 [get_bd_ports ACLK] [get_bd_pins axi_apb_bridge_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk]
connect_bd_net -net ARESETN_0_1 [get_bd_ports ARESETN] [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn]
connect_bd_net -net ACLK_0_1 [get_bd_ports ACLK] [get_bd_pins axi_apb_bridge_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins jtag_axi_flash/aclk]
connect_bd_net -net ARESETN_0_1 [get_bd_ports ARESETN] [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins jtag_axi_flash/aresetn]
connect_bd_net -net SYS_INTER_CLK_1 [get_bd_ports SYS_INTER_CLK] [get_bd_pins axi_interconnect_0/S00_ACLK]
connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_ports uart0_intc] [get_bd_pins axi_uart16550_0/ip2intc_irpt]
connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_uart16550_0/freeze] [get_bd_pins xlconstant_0/dout]
Expand All @@ -297,6 +311,9 @@ proc create_root_design { parentCell } {
assign_bd_address -offset 0x31200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs SYS_CFG_APB/Reg] -force
assign_bd_address -offset 0x310B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force
assign_bd_address -offset 0x10000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs rom_axi/Reg] -force
assign_bd_address -offset 0x10000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jtag_axi_flash/Data] [get_bd_addr_segs rom_axi/Reg] -force
exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces jtag_axi_flash/Data] [get_bd_addr_segs SYS_CFG_APB/Reg]
exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces jtag_axi_flash/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg]


# Restore current instance
Expand All @@ -315,4 +332,3 @@ create_root_design ""


common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."

3 changes: 1 addition & 2 deletions fpga_diff/src/tcl/common/blk_mem_gen_0.tcl
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Expand Up @@ -91,7 +91,7 @@ set_property -dict {
CONFIG.Byte_Size {8}
CONFIG.Assume_Synchronous_Clk {true}
CONFIG.Write_Width_A {32}
CONFIG.Write_Depth_A {1024}
CONFIG.Write_Depth_A {8192}
CONFIG.Read_Width_A {32}
CONFIG.Operating_Mode_A {READ_FIRST}
CONFIG.Write_Width_B {32}
Expand All @@ -114,4 +114,3 @@ set_property -dict {
} $blk_mem_gen_0

##################################################################

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