baochip: New port for the Baochip-1x RISC-V SoC (DABAO board).

[andrewleech]

Summary

New port for the Baochip-1x, a VexRiscv RISC-V SoC with PULP UDMA peripherals, 4 MiB on-chip RRAM, 2 MiB SRAM, and a native USB controller exposed through the vendor boot1 bootloader. First (and currently only) supported board is the Crowd Supply Dabao evaluation board.

What works now: UART2 REPL at 115200 8N1, machine.Pin for all 96 GPIOs with IN/OUT/OPEN_DRAIN, machine.bootloader() to drop back into the vendor boot1 over USB-CDC, and machine.freq() returning the 350 MHz ACLK. Native USB-CDC, filesystem, and the rest of the peripheral drivers are still to come.

Uses dabao-sdk (Apache-2.0), a new open-source C SDK for this chip, separate from the Rust-based pattern that's also in development. Pinned at lib/dabao-sdk as a submodule. Boot signing uses the SDK's developer Ed25519ph key, so the resulting UF2 has a real signature but no meaningful attestation; the CI workflow installs pure25519 for this.

REPL UART RX is interrupt-driven, copying from the hardware 4-byte FIFO into the standard stdin ringbuf.

Open-drain Pin mode is software-emulated. The chip's GPIO block has no OD bit, so OD pins keep the DATA latch at 0 permanently and toggle direction to switch between drive-low (output) and float (input, relying on the external pull-up). A per-port mask tracks which pins are in OD mode so pin.value(v) knows which path to take; the mask is cleared on every soft reset.

A few things are deliberately stubbed with NotImplementedError and TODO markers: unique_id, set_freq, lightsleep with a timeout argument, and deepsleep. reset_cause() returns 0 until the SCG register mapping is done. MICROPY_CONFIG_ROM_LEVEL is set to EXTRA_FEATURES and the default boards/manifest.py includes asyncio.

Testing

Built and tested on the Dabao via the vendor's boot1 USB-CDC flashing path. Smoke tests cover REPL responsiveness, Pin toggle on PB1 (board pin -> CPU pin PA1), machine.bootloader() actually entering boot1, machine.freq() returning 350000000, time.ticks_ms() accuracy on a 100 ms sleep, and a 166-byte single-write burst into UART2 to verify the RX_CHAR path doesn't drop bytes.

No other ports touched.

Trade-offs and Alternatives

Software open-drain costs a small per-port mask in RAM and an extra branch in pin.value(), but the alternative would be to refuse OD mode entirely on this chip.

machine.bootloader() drives PC13 LOW for 1 ms before triggering the software reset. PC13 is dual-use on Dabao: the boot strap AND the 0.85 V regulator feedback path. Holding it LOW for longer interferes with the regulator, so the brief pulse is deliberate.

Generative AI

I used generative AI tools when creating this PR, but a human has checked the code and is responsible for the description above.

[github-actions]

Code size report:

Reference:  github/workflows: Bump actions/github-script from 8 to 9. [1c63211]
Comparison: github/workflows: Add baochip port to CI. [merge of 825f3cc]
  mpy-cross:    +0 +0.000% 
   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
      esp32:    +0 +0.000% ESP32_GENERIC
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO_W
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS
  qemu rv32:    +0 +0.000% VIRT_RV32

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Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 98.47%. Comparing base (1c63211) to head (825f3cc).
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Additional details and impacted files

@@                 Coverage Diff                  @@
##           review/baochip-port      #47   +/-   ##
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  Coverage                98.47%   98.47%           
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  Files                      176      176           
  Lines                    22845    22845           
====================================================
  Hits                     22497    22497           
  Misses                     348      348           

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