media: ipu6: Add MIPI serializer/deserializer enhancements - #40
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Introduce suspend and resume callbacks in the MAX9296A driver and hook them into the I2C driver PM ops. On suspend, hand control to the common max_des suspend flow. On resume, reset the device and then restore the deserializer state through max_des resume. Signed-off-by: Sodhi, Vunny <vunny.sodhi@intel.com>
1G Frequency is doubled when IPU is configuring DPHY link frequency. With 1G, deskew is enabled, and pink frame is observed during streaming. Reducing to 700MHz will disable the deskew and pink frame issue is not observed during streaming. Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
For MAX9296, default is 700MHz. Higher Value will need to adjust the deskew value in MAX9296, which is not handled yet. 700MHz is sufficient for 2 ISX031 use case. For MAX96724, default is 1GHz. Lower Value will not be sufficient to support basic 4 ISX031 use case. Signed-off-by: Khai Wen, Ng <khai.wen.ng@intel.com>
Allow selecting an alternative DPHY clock lane when configuring MAX96724 MIPI PHY routing. Add clock lane handling for lane 0 and lane 5 and reject invalid values with an error, so board configurations using either route are supported safely. Signed-off-by: Yew, Chang Ching <chang.ching.yew@intel.com>
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vunnyso
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khaiwenng
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Aug 19, 2026
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This PR bundles four interconnected improvements to the IPU6 camera subsystem:
MAX96724 Clock Lane Support - Adds flexible DPHY clock lane selection
(lane 0 or lane 5) with validation
Link Frequency Configuration - Establishes optimal default frequencies:
Pink Frame Fix - Reduces MAX9296 frequency to 700MHz to eliminate
deskew-related video artifacts
Power Management - Adds suspend/resume support for MAX9296A deserializer