Source debug_05

.github/workflows/general.yml

@@ -103,10 +103,18 @@ jobs:
       - name: Install software - Verilator
         if: matrix.platform == 'vm'
         run: bash tool/gh_actions/install_verilator.sh
+      - name: Install software - Accellera SystemC
+        run: tool/gh_actions/install_systemc.sh
+
+      - name: Pre-build SystemC PCH and Makefile
+        run: tool/gh_actions/setup_systemc_pch.sh
 
       - name: Run project tests
         run: tool/gh_actions/run_tests.sh ${{ matrix.platform }}
 
+      - name: Clean SystemC temporary files
+        run: tool/gh_actions/cleanup_systemc_tmp.sh
+
       - name: Check temporary test files
         if: always()
         run: tool/gh_actions/check_tmp_test.sh
@@ -132,6 +140,7 @@ jobs:
           runCmd: |
             set -eu
             ROHD_REQUIRE_VERILATOR=1 tool/gh_actions/run_tests.sh ${{ matrix.platform }}
+            tool/gh_actions/cleanup_systemc_tmp.sh
             tool/gh_actions/check_tmp_test.sh
 
   shell-regression-tests:

CHANGELOG.md

@@ -2,6 +2,9 @@
 
 - Fixed `LogicValue.ofRadixString` round trips with empty separators and separators containing regular-expression metacharacters (<https://github.com/intel/rohd/issues/722>).
 
+- Released `rohd_hierarchy` 0.2.0 with the hierarchy query and netlist
+  adapter APIs.
+
 ## 0.6.11
 
 - Added `NetlistSynthesizer` for generating JSON netlists, with configurable synthesis passes, validation, and hierarchy support (<https://github.com/intel/rohd/pull/675>).

README.md

@@ -9,7 +9,6 @@
 [![Chat](https://img.shields.io/discord/1001179329411166267?label=Chat)](https://discord.gg/jubxF84yGw)
 [![License](https://img.shields.io/badge/License-BSD--3-blue)](https://github.com/intel/rohd/blob/main/LICENSE)
 [![Contributor Covenant](https://img.shields.io/badge/Contributor%20Covenant-2.1-4baaaa.svg)](https://github.com/intel/rohd/blob/main/CODE_OF_CONDUCT.md)
-[![Coverage](https://raw.githubusercontent.com/intel/rohd/refs/heads/badges/coverage/main.svg)](https://github.com/intel/rohd/blob/main/.github/workflows/coverage.yml)
 
 ROHD (pronounced like "road") is a framework for describing and verifying hardware in the Dart programming language.
 
@@ -44,8 +43,8 @@ You can also open this repository in a GitHub Codespace to run the example in yo
 - Easy **IP integration** and **interfaces**; using an IP is as easy as an import.  Reduces tedious, redundant, and error prone aspects of integration
 - **Simple and fast build**, free of complex build systems and EDA vendor tools
 - Can use the excellent pub.dev **package manager** and all the packages it has to offer
-- Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform dumper** to .vcd file format
-- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** for integration or downstream tool consumption
+- Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform capture service** to .vcd or .fst file format
+- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** and **SystemC** for integration or downstream tool consumption
 - **Run-time dynamic** module port definitions (numbers, names, widths, etc.) and internal module logic, including recursive module contents
 - Leverage the [ROHD Hardware Component Library (ROHD-HCL)](https://github.com/intel/rohd-hcl) with reusable and configurable design and verification components.
 - Simple, free, **open source tool stack** without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc.
@@ -69,5 +68,6 @@ One of ROHD's goals is to help grow an open-source community around reusable har
 ROHD is under active development.  If you're interested in contributing, have feedback or a question, or found a bug, please see [CONTRIBUTING.md](https://github.com/intel/rohd/blob/main/CONTRIBUTING.md).
 
 ----------------
+
 Copyright (C) 2021-2026 Intel Corporation  
 SPDX-License-Identifier: BSD-3-Clause

dart_test.yaml

@@ -3,3 +3,9 @@ tags:
     timeout: 2x
   verilator:
     timeout: 5m
+  ffi:
+    # Tests requiring dart:ffi and native shared libraries.
+
+presets:
+  no-ffi:
+    exclude_tags: ffi

doc/architecture.md

@@ -24,7 +24,7 @@ The `Simulator` acts as a statically accessible driver of the overall simulation
 
 ### Synthesizer
 
-A separate type of object responsible for taking a `Module` and converting it to some output, such as SystemVerilog.
+A separate type of object responsible for taking a `Module` and converting it to some output, such as SystemVerilog or SystemC.
 
 ## Organization
 
@@ -44,7 +44,7 @@ Contains a collection of `Module` implementations that can be used as primitive
 
 ### Synthesizers
 
-Contains logic for synthesizing `Module`s into some output. It is structured to maximize reusability across different output types (including those not yet supported).
+Contains logic for synthesizing `Module`s into some output (e.g. SystemVerilog, SystemC). It is structured to maximize reusability across different output types.
 
 ### Utilities