FROMLIST: arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedi… - #1815
Merged
Shiraz Hashim (shashim-quic) merged 1 commit intoSep 12, 2026
Conversation
…cated pcie3b_phy Unlike Glymur, Mahua only has PCIe3b wired up; there is no PCIe3a controller and no shared Gen5x8 PHY block. Delete the inherited pcie3a and pcie3_phy nodes, and add a dedicated pcie3b_phy using the existing qcom,glymur-qmp-gen5x4-pcie-phy compatible. Point pcie3b_port0's phys and the GCC pipe clock parent array at &pcie3b_phy instead of the deleted &pcie3_phy. Link: https://lore.kernel.org/all/20260825-glymur_linkmode_0826-v10-3-56ab597d77e4@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
qcomlnxci
requested review from
a team,
knaveen-qc,
Rajendra (rrnayak) and
yijiyang
and removed request for
a team
September 12, 2026 03:46
Shiraz Hashim (shashim-quic)
approved these changes
Sep 12, 2026
Shiraz Hashim (shashim-quic)
merged commit Sep 12, 2026
f9f34b1
into
qualcomm-linux:tech/all/dt/glymur
3 of 6 checks passed
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
…cated pcie3b_phy
Unlike Glymur, Mahua only has PCIe3b wired up; there is no PCIe3a controller and no shared Gen5x8 PHY block. Delete the inherited pcie3a and pcie3_phy nodes, and add a dedicated pcie3b_phy using the existing qcom,glymur-qmp-gen5x4-pcie-phy compatible.
Point pcie3b_port0's phys and the GCC pipe clock parent array at &pcie3b_phy instead of the deleted &pcie3_phy.
Link: https://lore.kernel.org/all/20260825-glymur_linkmode_0826-v10-3-56ab597d77e4@oss.qualcomm.com/
Reviewed-by: Konrad Dybcio konrad.dybcio@oss.qualcomm.com
Reviewed-by: Manivannan Sadhasivam manivannan.sadhasivam@oss.qualcomm.com