Mt8196/v0.1 - #11205
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Mt8196/v0.1#11205
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September 16, 2026 14:05
Replace the hard-coded 16-byte alignment with DCACHE_LINE_SIZE so the DMA buffer alignment follows the platform configuration. Signed-off-by: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>
Move the DRAM base from 0x90000000 to 0x92200000 and update the corresponding cached, non-cacheable and unused MPU regions. Signed-off-by: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>
mtkcyril
requested review from
dbaluta,
kv2019i,
lbetlej,
lgirdwood,
mmaka1 and
plbossart
as code owners
September 16, 2026 08:17
Collaborator
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Can one of the admins verify this patch?
|
lgirdwood
approved these changes
Sep 25, 2026
Member
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@thesofproject/mediatek pls review/merge. |
Contributor
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Hi @mtkcyril , you can merge this PR then. |
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