Xilinx Versal Gen2 ASU port: TRNG, hashes, HMAC offload - #10765

Merged

JacobBarthelmeh merged 2 commits into

wolfSSL:masterfrom

night1rider:Xilinx-ASU-TRNG-Hashes-HMAC

Jul 22, 2026

Commits on Jul 20, 2026

Xilinx Versal Gen2 ASU port: TRNG, hashes, HMAC offload
night1rider
committed
66f6f7c

Commits on Jul 22, 2026

versal_gen2_asu: fix check-source-text native heap false positive and add port macros to .wolfssl_known_macro_extras.
night1rider
committed
64c7699