RISC-V: add note about target features vs. misa extensions - #2354
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RISC-V: add note about target features vs. misa extensions#2354TechnoPorg wants to merge 1 commit into
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| > [!NOTE] | ||
| > Some RISC-V standard extensions can be enabled (1) or disabled (0) via their corresponding bits in the [Machine ISA][rv-machine] (`misa`) register. | ||
| > For example, the [A][rv-a] and [M][rv-m] bits being cleared means atomic instructions and integer multiplication/division instructions are unimplemented. | ||
| > | ||
| > Rust code compiled with a RISC-V target feature of the same name as an extension assumes the extension will always be available. | ||
| > It is undefined behaviour to execute it in an environment where the extension is disabled (bit is 0 in `misa`). |
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I think a note (which is not normative) is not enough here. We need to say, normatively, that code compiled with a "single-letter target feature" (or whatever they are called) is UB to invoke unless the corresponding bit is actually set in the misa register.
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Would that go in the same part of the document, just not as a note?
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As per the discussion in rust-lang/rust#162552 and #t-compiler/risc-v > RISC-V extensions vs. Rust target features, this clarifies that enabling a target feature means the
misabit of the same name (if any) is assumed to always be set. Although this originally came up in the context of theMextension, it applies to many others as well, which are listed in the linked Machine ISA manual page.cc @RalfJung