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RISC-V: add note about target features vs. misa extensions #2354

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RISC-V: add note about target features vs. misa extensions #2354

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8 changes: 8 additions & 0 deletions src/attributes/codegen.md
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Expand Up @@ -563,6 +563,13 @@ specification. Many specifications are described in the [RISC-V ISA Manual],
[version 20250508]: https://github.com/riscv/riscv-isa-manual/tree/20250508
[RISC-V GitHub Account]: https://github.com/riscv

> [!NOTE]
> Some RISC-V standard extensions can be enabled (1) or disabled (0) via their corresponding bits in the [Machine ISA][rv-machine] (`misa`) register.
> For example, the [A][rv-a] and [M][rv-m] bits being cleared means atomic instructions and integer multiplication/division instructions are unimplemented.
>
> Rust code compiled with a RISC-V target feature of the same name as an extension assumes the extension will always be available.
> It is undefined behaviour to execute it in an environment where the extension is disabled (bit is 0 in `misa`).
Comment on lines +566 to +571

@RalfJung RalfJung Sep 12, 2026 •
edited by rustbot
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I think a note (which is not normative) is not enough here. We need to say, normatively, that code compiled with a "single-letter target feature" (or whatever they are called) is UB to invoke unless the corresponding bit is actually set in the misa register.

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@TechnoPorg TechnoPorg Sep 12, 2026

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Would that go in the same part of the document, just not as a note?

@RalfJung RalfJung Sep 12, 2026

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I'm not sure -- @traviscross @ehuss


Feature | Implicitly Enables | Description
------------|---------------------|-------------------
`a` | `zaamo`, `zalrsc` | [A][rv-a] --- Atomic instructions
Expand Down Expand Up @@ -621,6 +628,7 @@ Feature | Implicitly Enables | Description
[rv-b]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
[rv-c]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/c-st-ext.adoc
[rv-m]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/m-st-ext.adoc
[rv-machine]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/machine.adoc#machine-isa-misa-register
[rv-za64rs]: https://github.com/riscv/riscv-profiles/blob/rva23-rvb23-ratified/src/rva23-profile.adoc
[rv-za128rs]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc
[rv-zaamo]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/a-st-ext.adoc
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